mpt_pci.c revision 232411
1255767Sdes/*- 2218767Sdes * PCI specific probe and attach routines for LSI Fusion Adapters 3218767Sdes * FreeBSD Version. 4218767Sdes * 5218767Sdes * Copyright (c) 2000, 2001 by Greg Ansley 6218767Sdes * Partially derived from Matt Jacob's ISP driver. 7218767Sdes * Copyright (c) 1997, 1998, 1999, 2000, 2001, 2002 by Matthew Jacob 8218767Sdes * Feral Software 9218767Sdes * All rights reserved. 10218767Sdes * 11218767Sdes * Redistribution and use in source and binary forms, with or without 12218767Sdes * modification, are permitted provided that the following conditions 13218767Sdes * are met: 14218767Sdes * 1. Redistributions of source code must retain the above copyright 15218767Sdes * notice immediately at the beginning of the file, without modification, 16218767Sdes * this list of conditions, and the following disclaimer. 17218767Sdes * 2. The name of the author may not be used to endorse or promote products 18218767Sdes * derived from this software without specific prior written permission. 19218767Sdes * 20218767Sdes * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21218767Sdes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22218767Sdes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23218767Sdes * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 24218767Sdes * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25218767Sdes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26218767Sdes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27218767Sdes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28218767Sdes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29218767Sdes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30218767Sdes * SUCH DAMAGE. 31218767Sdes */ 32218767Sdes/*- 33218767Sdes * Copyright (c) 2002, 2006 by Matthew Jacob 34218767Sdes * All rights reserved. 35218767Sdes * 36218767Sdes * Redistribution and use in source and binary forms, with or without 37218767Sdes * modification, are permitted provided that the following conditions are 38218767Sdes * met: 39218767Sdes * 1. Redistributions of source code must retain the above copyright 40218767Sdes * notice, this list of conditions and the following disclaimer. 41218767Sdes * 2. Redistributions in binary form must reproduce at minimum a disclaimer 42218767Sdes * substantially similar to the "NO WARRANTY" disclaimer below 43218767Sdes * ("Disclaimer") and any redistribution must be conditioned upon including 44218767Sdes * a substantially similar Disclaimer requirement for further binary 45218767Sdes * redistribution. 46218767Sdes * 3. Neither the names of the above listed copyright holders nor the names 47218767Sdes * of any contributors may be used to endorse or promote products derived 48218767Sdes * from this software without specific prior written permission. 49218767Sdes * 50218767Sdes * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 51218767Sdes * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 52218767Sdes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 53218767Sdes * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 54218767Sdes * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55218767Sdes * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56218767Sdes * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57218767Sdes * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58218767Sdes * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59218767Sdes * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF THE COPYRIGHT 60218767Sdes * OWNER OR CONTRIBUTOR IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61218767Sdes * 62218767Sdes * Support from Chris Ellsworth in order to make SAS adapters work 63218767Sdes * is gratefully acknowledged. 64218767Sdes * 65218767Sdes * Support from LSI-Logic has also gone a great deal toward making this a 66218767Sdes * workable subsystem and is gratefully acknowledged. 67218767Sdes */ 68218767Sdes/* 69218767Sdes * Copyright (c) 2004, Avid Technology, Inc. and its contributors. 70218767Sdes * Copyright (c) 2005, WHEEL Sp. z o.o. 71218767Sdes * Copyright (c) 2004, 2005 Justin T. Gibbs 72218767Sdes * All rights reserved. 73218767Sdes * 74218767Sdes * Redistribution and use in source and binary forms, with or without 75218767Sdes * modification, are permitted provided that the following conditions are 76218767Sdes * met: 77218767Sdes * 1. Redistributions of source code must retain the above copyright 78218767Sdes * notice, this list of conditions and the following disclaimer. 79218767Sdes * 2. Redistributions in binary form must reproduce at minimum a disclaimer 80218767Sdes * substantially similar to the "NO WARRANTY" disclaimer below 81218767Sdes * ("Disclaimer") and any redistribution must be conditioned upon including 82218767Sdes * a substantially similar Disclaimer requirement for further binary 83218767Sdes * redistribution. 84218767Sdes * 3. Neither the names of the above listed copyright holders nor the names 85218767Sdes * of any contributors may be used to endorse or promote products derived 86218767Sdes * from this software without specific prior written permission. 87218767Sdes * 88218767Sdes * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 89218767Sdes * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 90218767Sdes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 91218767Sdes * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 92218767Sdes * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 93218767Sdes * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 94218767Sdes * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 95218767Sdes * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 96218767Sdes * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 97218767Sdes * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF THE COPYRIGHT 98218767Sdes * OWNER OR CONTRIBUTOR IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 99218767Sdes */ 100218767Sdes 101218767Sdes#include <sys/cdefs.h> 102218767Sdes__FBSDID("$FreeBSD: head/sys/dev/mpt/mpt_pci.c 232411 2012-03-02 22:00:40Z ken $"); 103218767Sdes 104218767Sdes#include <dev/mpt/mpt.h> 105218767Sdes#include <dev/mpt/mpt_cam.h> 106218767Sdes#include <dev/mpt/mpt_raid.h> 107218767Sdes 108218767Sdes#if __FreeBSD_version < 700000 109218767Sdes#define pci_msix_count(x) 0 110218767Sdes#define pci_msi_count(x) 0 111218767Sdes#define pci_alloc_msi(x, y) 1 112218767Sdes#define pci_alloc_msix(x, y) 1 113218767Sdes#define pci_release_msi(x) do { ; } while (0) 114218767Sdes#endif 115218767Sdes 116218767Sdes#ifndef PCI_VENDOR_LSI 117218767Sdes#define PCI_VENDOR_LSI 0x1000 118218767Sdes#endif 119218767Sdes 120218767Sdes#ifndef PCI_PRODUCT_LSI_FC909 121218767Sdes#define PCI_PRODUCT_LSI_FC909 0x0620 122255767Sdes#endif 123218767Sdes 124218767Sdes#ifndef PCI_PRODUCT_LSI_FC909A 125255767Sdes#define PCI_PRODUCT_LSI_FC909A 0x0621 126218767Sdes#endif 127218767Sdes 128218767Sdes#ifndef PCI_PRODUCT_LSI_FC919 129218767Sdes#define PCI_PRODUCT_LSI_FC919 0x0624 130218767Sdes#endif 131255767Sdes 132218767Sdes#ifndef PCI_PRODUCT_LSI_FC919_LAN 133218767Sdes#define PCI_PRODUCT_LSI_FC919_LAN 0x0625 134218767Sdes#endif 135218767Sdes 136218767Sdes#ifndef PCI_PRODUCT_LSI_FC929 137218767Sdes#define PCI_PRODUCT_LSI_FC929 0x0622 138218767Sdes#endif 139218767Sdes 140218767Sdes#ifndef PCI_PRODUCT_LSI_FC929_LAN 141218767Sdes#define PCI_PRODUCT_LSI_FC929_LAN 0x0623 142218767Sdes#endif 143218767Sdes 144218767Sdes#ifndef PCI_PRODUCT_LSI_FC929X 145218767Sdes#define PCI_PRODUCT_LSI_FC929X 0x0626 146218767Sdes#endif 147218767Sdes 148240075Sdes#ifndef PCI_PRODUCT_LSI_FC929X_LAN 149218767Sdes#define PCI_PRODUCT_LSI_FC929X_LAN 0x0627 150218767Sdes#endif 151218767Sdes 152255767Sdes#ifndef PCI_PRODUCT_LSI_FC919X 153218767Sdes#define PCI_PRODUCT_LSI_FC919X 0x0628 154218767Sdes#endif 155218767Sdes 156218767Sdes#ifndef PCI_PRODUCT_LSI_FC919X_LAN 157218767Sdes#define PCI_PRODUCT_LSI_FC919X_LAN 0x0629 158218767Sdes#endif 159218767Sdes 160218767Sdes#ifndef PCI_PRODUCT_LSI_FC7X04X 161218767Sdes#define PCI_PRODUCT_LSI_FC7X04X 0x0640 162218767Sdes#endif 163218767Sdes 164218767Sdes#ifndef PCI_PRODUCT_LSI_FC646 165218767Sdes#define PCI_PRODUCT_LSI_FC646 0x0646 166218767Sdes#endif 167218767Sdes 168218767Sdes#ifndef PCI_PRODUCT_LSI_1030 169218767Sdes#define PCI_PRODUCT_LSI_1030 0x0030 170#endif 171 172#ifndef PCI_PRODUCT_LSI_1030ZC 173#define PCI_PRODUCT_LSI_1030ZC 0x0031 174#endif 175 176#ifndef PCI_PRODUCT_LSI_SAS1064 177#define PCI_PRODUCT_LSI_SAS1064 0x0050 178#endif 179 180#ifndef PCI_PRODUCT_LSI_SAS1064A 181#define PCI_PRODUCT_LSI_SAS1064A 0x005C 182#endif 183 184#ifndef PCI_PRODUCT_LSI_SAS1064E 185#define PCI_PRODUCT_LSI_SAS1064E 0x0056 186#endif 187 188#ifndef PCI_PRODUCT_LSI_SAS1066 189#define PCI_PRODUCT_LSI_SAS1066 0x005E 190#endif 191 192#ifndef PCI_PRODUCT_LSI_SAS1066E 193#define PCI_PRODUCT_LSI_SAS1066E 0x005A 194#endif 195 196#ifndef PCI_PRODUCT_LSI_SAS1068 197#define PCI_PRODUCT_LSI_SAS1068 0x0054 198#endif 199 200#ifndef PCI_PRODUCT_LSI_SAS1068A 201#define PCI_PRODUCT_LSI_SAS1068A 0x0055 202#endif 203 204#ifndef PCI_PRODUCT_LSI_SAS1068E 205#define PCI_PRODUCT_LSI_SAS1068E 0x0058 206#endif 207 208#ifndef PCI_PRODUCT_LSI_SAS1078 209#define PCI_PRODUCT_LSI_SAS1078 0x0062 210#endif 211 212#ifndef PCI_PRODUCT_LSI_SAS1078DE 213#define PCI_PRODUCT_LSI_SAS1078DE 0x007C 214#endif 215 216#ifndef PCIM_CMD_SERRESPEN 217#define PCIM_CMD_SERRESPEN 0x0100 218#endif 219 220static int mpt_pci_probe(device_t); 221static int mpt_pci_attach(device_t); 222static void mpt_free_bus_resources(struct mpt_softc *mpt); 223static int mpt_pci_detach(device_t); 224static int mpt_pci_shutdown(device_t); 225static int mpt_dma_mem_alloc(struct mpt_softc *mpt); 226static void mpt_dma_mem_free(struct mpt_softc *mpt); 227static void mpt_read_config_regs(struct mpt_softc *mpt); 228#if 0 229static void mpt_set_config_regs(struct mpt_softc *mpt); 230#endif 231static void mpt_pci_intr(void *); 232 233static device_method_t mpt_methods[] = { 234 /* Device interface */ 235 DEVMETHOD(device_probe, mpt_pci_probe), 236 DEVMETHOD(device_attach, mpt_pci_attach), 237 DEVMETHOD(device_detach, mpt_pci_detach), 238 DEVMETHOD(device_shutdown, mpt_pci_shutdown), 239 { 0, 0 } 240}; 241 242static driver_t mpt_driver = { 243 "mpt", mpt_methods, sizeof(struct mpt_softc) 244}; 245static devclass_t mpt_devclass; 246DRIVER_MODULE(mpt, pci, mpt_driver, mpt_devclass, 0, 0); 247MODULE_DEPEND(mpt, pci, 1, 1, 1); 248MODULE_VERSION(mpt, 1); 249 250static int 251mpt_pci_probe(device_t dev) 252{ 253 char *desc; 254 255 if (pci_get_vendor(dev) != PCI_VENDOR_LSI) { 256 return (ENXIO); 257 } 258 259 switch (pci_get_device(dev)) { 260 case PCI_PRODUCT_LSI_FC909: 261 desc = "LSILogic FC909 FC Adapter"; 262 break; 263 case PCI_PRODUCT_LSI_FC909A: 264 desc = "LSILogic FC909A FC Adapter"; 265 break; 266 case PCI_PRODUCT_LSI_FC919: 267 desc = "LSILogic FC919 FC Adapter"; 268 break; 269 case PCI_PRODUCT_LSI_FC919_LAN: 270 desc = "LSILogic FC919 LAN Adapter"; 271 break; 272 case PCI_PRODUCT_LSI_FC929: 273 desc = "Dual LSILogic FC929 FC Adapter"; 274 break; 275 case PCI_PRODUCT_LSI_FC929_LAN: 276 desc = "Dual LSILogic FC929 LAN Adapter"; 277 break; 278 case PCI_PRODUCT_LSI_FC919X: 279 desc = "LSILogic FC919 FC PCI-X Adapter"; 280 break; 281 case PCI_PRODUCT_LSI_FC919X_LAN: 282 desc = "LSILogic FC919 LAN PCI-X Adapter"; 283 break; 284 case PCI_PRODUCT_LSI_FC929X: 285 desc = "Dual LSILogic FC929X 2Gb/s FC PCI-X Adapter"; 286 break; 287 case PCI_PRODUCT_LSI_FC929X_LAN: 288 desc = "Dual LSILogic FC929X LAN PCI-X Adapter"; 289 break; 290 case PCI_PRODUCT_LSI_FC646: 291 desc = "Dual LSILogic FC7X04X 4Gb/s FC PCI-Express Adapter"; 292 break; 293 case PCI_PRODUCT_LSI_FC7X04X: 294 desc = "Dual LSILogic FC7X04X 4Gb/s FC PCI-X Adapter"; 295 break; 296 case PCI_PRODUCT_LSI_1030: 297 case PCI_PRODUCT_LSI_1030ZC: 298 desc = "LSILogic 1030 Ultra4 Adapter"; 299 break; 300 case PCI_PRODUCT_LSI_SAS1064: 301 case PCI_PRODUCT_LSI_SAS1064A: 302 case PCI_PRODUCT_LSI_SAS1064E: 303 case PCI_PRODUCT_LSI_SAS1066: 304 case PCI_PRODUCT_LSI_SAS1066E: 305 case PCI_PRODUCT_LSI_SAS1068: 306 case PCI_PRODUCT_LSI_SAS1068A: 307 case PCI_PRODUCT_LSI_SAS1068E: 308 case PCI_PRODUCT_LSI_SAS1078: 309 case PCI_PRODUCT_LSI_SAS1078DE: 310 desc = "LSILogic SAS/SATA Adapter"; 311 break; 312 default: 313 return (ENXIO); 314 } 315 316 device_set_desc(dev, desc); 317 return (0); 318} 319 320#if __FreeBSD_version < 500000 321static void 322mpt_set_options(struct mpt_softc *mpt) 323{ 324 int bitmap; 325 326 bitmap = 0; 327 if (getenv_int("mpt_disable", &bitmap)) { 328 if (bitmap & (1 << mpt->unit)) { 329 mpt->disabled = 1; 330 } 331 } 332 bitmap = 0; 333 if (getenv_int("mpt_debug", &bitmap)) { 334 if (bitmap & (1 << mpt->unit)) { 335 mpt->verbose = MPT_PRT_DEBUG; 336 } 337 } 338 bitmap = 0; 339 if (getenv_int("mpt_debug1", &bitmap)) { 340 if (bitmap & (1 << mpt->unit)) { 341 mpt->verbose = MPT_PRT_DEBUG1; 342 } 343 } 344 bitmap = 0; 345 if (getenv_int("mpt_debug2", &bitmap)) { 346 if (bitmap & (1 << mpt->unit)) { 347 mpt->verbose = MPT_PRT_DEBUG2; 348 } 349 } 350 bitmap = 0; 351 if (getenv_int("mpt_debug3", &bitmap)) { 352 if (bitmap & (1 << mpt->unit)) { 353 mpt->verbose = MPT_PRT_DEBUG3; 354 } 355 } 356 357 mpt->cfg_role = MPT_ROLE_DEFAULT; 358 bitmap = 0; 359 if (getenv_int("mpt_nil_role", &bitmap)) { 360 if (bitmap & (1 << mpt->unit)) { 361 mpt->cfg_role = 0; 362 } 363 mpt->do_cfg_role = 1; 364 } 365 bitmap = 0; 366 if (getenv_int("mpt_tgt_role", &bitmap)) { 367 if (bitmap & (1 << mpt->unit)) { 368 mpt->cfg_role |= MPT_ROLE_TARGET; 369 } 370 mpt->do_cfg_role = 1; 371 } 372 bitmap = 0; 373 if (getenv_int("mpt_ini_role", &bitmap)) { 374 if (bitmap & (1 << mpt->unit)) { 375 mpt->cfg_role |= MPT_ROLE_INITIATOR; 376 } 377 mpt->do_cfg_role = 1; 378 } 379 mpt->msi_enable = 0; 380} 381#else 382static void 383mpt_set_options(struct mpt_softc *mpt) 384{ 385 int tval; 386 387 tval = 0; 388 if (resource_int_value(device_get_name(mpt->dev), 389 device_get_unit(mpt->dev), "disable", &tval) == 0 && tval != 0) { 390 mpt->disabled = 1; 391 } 392 tval = 0; 393 if (resource_int_value(device_get_name(mpt->dev), 394 device_get_unit(mpt->dev), "debug", &tval) == 0 && tval != 0) { 395 mpt->verbose = tval; 396 } 397 tval = -1; 398 if (resource_int_value(device_get_name(mpt->dev), 399 device_get_unit(mpt->dev), "role", &tval) == 0 && tval >= 0 && 400 tval <= 3) { 401 mpt->cfg_role = tval; 402 mpt->do_cfg_role = 1; 403 } 404 tval = 0; 405 mpt->msi_enable = 0; 406 if (mpt->is_sas) 407 mpt->msi_enable = 1; 408 if (resource_int_value(device_get_name(mpt->dev), 409 device_get_unit(mpt->dev), "msi_enable", &tval) == 0) { 410 mpt->msi_enable = tval; 411 } 412} 413#endif 414 415static void 416mpt_link_peer(struct mpt_softc *mpt) 417{ 418 struct mpt_softc *mpt2; 419 420 if (mpt->unit == 0) { 421 return; 422 } 423 /* 424 * XXX: depends on probe order 425 */ 426 mpt2 = (struct mpt_softc *)devclass_get_softc(mpt_devclass,mpt->unit-1); 427 428 if (mpt2 == NULL) { 429 return; 430 } 431 if (pci_get_vendor(mpt2->dev) != pci_get_vendor(mpt->dev)) { 432 return; 433 } 434 if (pci_get_device(mpt2->dev) != pci_get_device(mpt->dev)) { 435 return; 436 } 437 mpt->mpt2 = mpt2; 438 mpt2->mpt2 = mpt; 439 if (mpt->verbose >= MPT_PRT_DEBUG) { 440 mpt_prt(mpt, "linking with peer (mpt%d)\n", 441 device_get_unit(mpt2->dev)); 442 } 443} 444 445static void 446mpt_unlink_peer(struct mpt_softc *mpt) 447{ 448 449 if (mpt->mpt2) { 450 mpt->mpt2->mpt2 = NULL; 451 } 452} 453 454static int 455mpt_pci_attach(device_t dev) 456{ 457 struct mpt_softc *mpt; 458 int iqd; 459 uint32_t data, cmd; 460 int mpt_io_bar, mpt_mem_bar; 461 462 /* Allocate the softc structure */ 463 mpt = (struct mpt_softc*)device_get_softc(dev); 464 if (mpt == NULL) { 465 device_printf(dev, "cannot allocate softc\n"); 466 return (ENOMEM); 467 } 468 memset(mpt, 0, sizeof(struct mpt_softc)); 469 switch (pci_get_device(dev)) { 470 case PCI_PRODUCT_LSI_FC909: 471 case PCI_PRODUCT_LSI_FC909A: 472 case PCI_PRODUCT_LSI_FC919: 473 case PCI_PRODUCT_LSI_FC919_LAN: 474 case PCI_PRODUCT_LSI_FC929: 475 case PCI_PRODUCT_LSI_FC929_LAN: 476 case PCI_PRODUCT_LSI_FC929X: 477 case PCI_PRODUCT_LSI_FC929X_LAN: 478 case PCI_PRODUCT_LSI_FC919X: 479 case PCI_PRODUCT_LSI_FC919X_LAN: 480 case PCI_PRODUCT_LSI_FC646: 481 case PCI_PRODUCT_LSI_FC7X04X: 482 mpt->is_fc = 1; 483 break; 484 case PCI_PRODUCT_LSI_SAS1078: 485 case PCI_PRODUCT_LSI_SAS1078DE: 486 mpt->is_1078 = 1; 487 /* FALLTHROUGH */ 488 case PCI_PRODUCT_LSI_SAS1064: 489 case PCI_PRODUCT_LSI_SAS1064A: 490 case PCI_PRODUCT_LSI_SAS1064E: 491 case PCI_PRODUCT_LSI_SAS1066: 492 case PCI_PRODUCT_LSI_SAS1066E: 493 case PCI_PRODUCT_LSI_SAS1068: 494 case PCI_PRODUCT_LSI_SAS1068A: 495 case PCI_PRODUCT_LSI_SAS1068E: 496 mpt->is_sas = 1; 497 break; 498 default: 499 mpt->is_spi = 1; 500 break; 501 } 502 mpt->dev = dev; 503 mpt->unit = device_get_unit(dev); 504 mpt->raid_resync_rate = MPT_RAID_RESYNC_RATE_DEFAULT; 505 mpt->raid_mwce_setting = MPT_RAID_MWCE_DEFAULT; 506 mpt->raid_queue_depth = MPT_RAID_QUEUE_DEPTH_DEFAULT; 507 mpt->verbose = MPT_PRT_NONE; 508 mpt->role = MPT_ROLE_NONE; 509 mpt->mpt_ini_id = MPT_INI_ID_NONE; 510#ifdef __sparc64__ 511 if (mpt->is_spi) 512 mpt->mpt_ini_id = OF_getscsinitid(dev); 513#endif 514 mpt_set_options(mpt); 515 if (mpt->verbose == MPT_PRT_NONE) { 516 mpt->verbose = MPT_PRT_WARN; 517 /* Print INFO level (if any) if bootverbose is set */ 518 mpt->verbose += (bootverbose != 0)? 1 : 0; 519 } 520 /* Make sure memory access decoders are enabled */ 521 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 522 if ((cmd & PCIM_CMD_MEMEN) == 0) { 523 device_printf(dev, "Memory accesses disabled"); 524 return (ENXIO); 525 } 526 527 /* 528 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER are set. 529 */ 530 cmd |= 531 PCIM_CMD_SERRESPEN | PCIM_CMD_PERRESPEN | 532 PCIM_CMD_BUSMASTEREN | PCIM_CMD_MWRICEN; 533 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 534 535 /* 536 * Make sure we've disabled the ROM. 537 */ 538 data = pci_read_config(dev, PCIR_BIOS, 4); 539 data &= ~PCIM_BIOS_ENABLE; 540 pci_write_config(dev, PCIR_BIOS, data, 4); 541 542 /* 543 * Is this part a dual? 544 * If so, link with our partner (around yet) 545 */ 546 switch (pci_get_device(dev)) { 547 case PCI_PRODUCT_LSI_FC929: 548 case PCI_PRODUCT_LSI_FC929_LAN: 549 case PCI_PRODUCT_LSI_FC646: 550 case PCI_PRODUCT_LSI_FC7X04X: 551 case PCI_PRODUCT_LSI_1030: 552 case PCI_PRODUCT_LSI_1030ZC: 553 mpt_link_peer(mpt); 554 break; 555 default: 556 break; 557 } 558 559 /* 560 * Figure out which are the I/O and MEM Bars 561 */ 562 data = pci_read_config(dev, PCIR_BAR(0), 4); 563 if (PCI_BAR_IO(data)) { 564 /* BAR0 is IO, BAR1 is memory */ 565 mpt_io_bar = 0; 566 mpt_mem_bar = 1; 567 } else { 568 /* BAR0 is memory, BAR1 is IO */ 569 mpt_mem_bar = 0; 570 mpt_io_bar = 1; 571 } 572 573 /* 574 * Set up register access. PIO mode is required for 575 * certain reset operations (but must be disabled for 576 * some cards otherwise). 577 */ 578 mpt_io_bar = PCIR_BAR(mpt_io_bar); 579 mpt->pci_pio_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 580 &mpt_io_bar, RF_ACTIVE); 581 if (mpt->pci_pio_reg == NULL) { 582 if (bootverbose) { 583 device_printf(dev, 584 "unable to map registers in PIO mode\n"); 585 } 586 } else { 587 mpt->pci_pio_st = rman_get_bustag(mpt->pci_pio_reg); 588 mpt->pci_pio_sh = rman_get_bushandle(mpt->pci_pio_reg); 589 } 590 591 /* Allocate kernel virtual memory for the 9x9's Mem0 region */ 592 mpt_mem_bar = PCIR_BAR(mpt_mem_bar); 593 mpt->pci_reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 594 &mpt_mem_bar, RF_ACTIVE); 595 if (mpt->pci_reg == NULL) { 596 if (bootverbose || mpt->is_sas || mpt->pci_pio_reg == NULL) { 597 device_printf(dev, 598 "Unable to memory map registers.\n"); 599 } 600 if (mpt->is_sas || mpt->pci_pio_reg == NULL) { 601 device_printf(dev, "Giving Up.\n"); 602 goto bad; 603 } 604 if (bootverbose) { 605 device_printf(dev, "Falling back to PIO mode.\n"); 606 } 607 mpt->pci_st = mpt->pci_pio_st; 608 mpt->pci_sh = mpt->pci_pio_sh; 609 } else { 610 mpt->pci_st = rman_get_bustag(mpt->pci_reg); 611 mpt->pci_sh = rman_get_bushandle(mpt->pci_reg); 612 } 613 614 /* Get a handle to the interrupt */ 615 iqd = 0; 616 if (mpt->msi_enable) { 617 /* 618 * First try to alloc an MSI-X message. If that 619 * fails, then try to alloc an MSI message instead. 620 */ 621 if (pci_msix_count(dev) == 1) { 622 mpt->pci_msi_count = 1; 623 if (pci_alloc_msix(dev, &mpt->pci_msi_count) == 0) { 624 iqd = 1; 625 } else { 626 mpt->pci_msi_count = 0; 627 } 628 } 629 if (iqd == 0 && pci_msi_count(dev) == 1) { 630 mpt->pci_msi_count = 1; 631 if (pci_alloc_msi(dev, &mpt->pci_msi_count) == 0) { 632 iqd = 1; 633 } else { 634 mpt->pci_msi_count = 0; 635 } 636 } 637 } 638 mpt->pci_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &iqd, 639 RF_ACTIVE | (mpt->pci_msi_count ? 0 : RF_SHAREABLE)); 640 if (mpt->pci_irq == NULL) { 641 device_printf(dev, "could not allocate interrupt\n"); 642 goto bad; 643 } 644 645 MPT_LOCK_SETUP(mpt); 646 647 /* Disable interrupts at the part */ 648 mpt_disable_ints(mpt); 649 650 /* Register the interrupt handler */ 651 if (mpt_setup_intr(dev, mpt->pci_irq, MPT_IFLAGS, NULL, mpt_pci_intr, 652 mpt, &mpt->ih)) { 653 device_printf(dev, "could not setup interrupt\n"); 654 goto bad; 655 } 656 657 /* Allocate dma memory */ 658 if (mpt_dma_mem_alloc(mpt)) { 659 mpt_prt(mpt, "Could not allocate DMA memory\n"); 660 goto bad; 661 } 662 663 /* 664 * Save the PCI config register values 665 * 666 * Hard resets are known to screw up the BAR for diagnostic 667 * memory accesses (Mem1). 668 * 669 * Using Mem1 is known to make the chip stop responding to 670 * configuration space transfers, so we need to save it now 671 */ 672 673 mpt_read_config_regs(mpt); 674 675 /* 676 * Disable PIO until we need it 677 */ 678 if (mpt->is_sas) { 679 pci_disable_io(dev, SYS_RES_IOPORT); 680 } 681 682 /* Initialize the hardware */ 683 if (mpt->disabled == 0) { 684 if (mpt_attach(mpt) != 0) { 685 goto bad; 686 } 687 } else { 688 mpt_prt(mpt, "device disabled at user request\n"); 689 goto bad; 690 } 691 692 mpt->eh = EVENTHANDLER_REGISTER(shutdown_post_sync, mpt_pci_shutdown, 693 dev, SHUTDOWN_PRI_DEFAULT); 694 695 if (mpt->eh == NULL) { 696 mpt_prt(mpt, "shutdown event registration failed\n"); 697 (void) mpt_detach(mpt); 698 goto bad; 699 } 700 return (0); 701 702bad: 703 mpt_dma_mem_free(mpt); 704 mpt_free_bus_resources(mpt); 705 mpt_unlink_peer(mpt); 706 707 MPT_LOCK_DESTROY(mpt); 708 709 /* 710 * but return zero to preserve unit numbering 711 */ 712 return (0); 713} 714 715/* 716 * Free bus resources 717 */ 718static void 719mpt_free_bus_resources(struct mpt_softc *mpt) 720{ 721 722 if (mpt->ih) { 723 bus_teardown_intr(mpt->dev, mpt->pci_irq, mpt->ih); 724 mpt->ih = NULL; 725 } 726 727 if (mpt->pci_irq) { 728 bus_release_resource(mpt->dev, SYS_RES_IRQ, 729 rman_get_rid(mpt->pci_irq), mpt->pci_irq); 730 mpt->pci_irq = NULL; 731 } 732 733 if (mpt->pci_msi_count) { 734 pci_release_msi(mpt->dev); 735 mpt->pci_msi_count = 0; 736 } 737 738 if (mpt->pci_pio_reg) { 739 bus_release_resource(mpt->dev, SYS_RES_IOPORT, 740 rman_get_rid(mpt->pci_pio_reg), mpt->pci_pio_reg); 741 mpt->pci_pio_reg = NULL; 742 } 743 if (mpt->pci_reg) { 744 bus_release_resource(mpt->dev, SYS_RES_MEMORY, 745 rman_get_rid(mpt->pci_reg), mpt->pci_reg); 746 mpt->pci_reg = NULL; 747 } 748 MPT_LOCK_DESTROY(mpt); 749} 750 751/* 752 * Disconnect ourselves from the system. 753 */ 754static int 755mpt_pci_detach(device_t dev) 756{ 757 struct mpt_softc *mpt; 758 759 mpt = (struct mpt_softc*)device_get_softc(dev); 760 761 if (mpt) { 762 mpt_disable_ints(mpt); 763 mpt_detach(mpt); 764 mpt_reset(mpt, /*reinit*/FALSE); 765 mpt_dma_mem_free(mpt); 766 mpt_free_bus_resources(mpt); 767 mpt_raid_free_mem(mpt); 768 if (mpt->eh != NULL) { 769 EVENTHANDLER_DEREGISTER(shutdown_post_sync, mpt->eh); 770 } 771 } 772 return(0); 773} 774 775/* 776 * Disable the hardware 777 */ 778static int 779mpt_pci_shutdown(device_t dev) 780{ 781 struct mpt_softc *mpt; 782 783 mpt = (struct mpt_softc *)device_get_softc(dev); 784 if (mpt) { 785 int r; 786 r = mpt_shutdown(mpt); 787 return (r); 788 } 789 return(0); 790} 791 792static int 793mpt_dma_mem_alloc(struct mpt_softc *mpt) 794{ 795 size_t len; 796 struct mpt_map_info mi; 797 798 /* Check if we alreay have allocated the reply memory */ 799 if (mpt->reply_phys != 0) { 800 return 0; 801 } 802 803 len = sizeof (request_t) * MPT_MAX_REQUESTS(mpt); 804#ifdef RELENG_4 805 mpt->request_pool = (request_t *)malloc(len, M_DEVBUF, M_WAITOK); 806 if (mpt->request_pool == NULL) { 807 mpt_prt(mpt, "cannot allocate request pool\n"); 808 return (1); 809 } 810 memset(mpt->request_pool, 0, len); 811#else 812 mpt->request_pool = (request_t *)malloc(len, M_DEVBUF, M_WAITOK|M_ZERO); 813 if (mpt->request_pool == NULL) { 814 mpt_prt(mpt, "cannot allocate request pool\n"); 815 return (1); 816 } 817#endif 818 819 /* 820 * Create a parent dma tag for this device. 821 * 822 * Align at byte boundaries, 823 * Limit to 32-bit addressing for request/reply queues. 824 */ 825 if (mpt_dma_tag_create(mpt, /*parent*/bus_get_dma_tag(mpt->dev), 826 /*alignment*/1, /*boundary*/0, /*lowaddr*/BUS_SPACE_MAXADDR, 827 /*highaddr*/BUS_SPACE_MAXADDR, /*filter*/NULL, /*filterarg*/NULL, 828 /*maxsize*/BUS_SPACE_MAXSIZE_32BIT, 829 /*nsegments*/BUS_SPACE_UNRESTRICTED, 830 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, /*flags*/0, 831 &mpt->parent_dmat) != 0) { 832 mpt_prt(mpt, "cannot create parent dma tag\n"); 833 return (1); 834 } 835 836 /* Create a child tag for reply buffers */ 837 if (mpt_dma_tag_create(mpt, mpt->parent_dmat, PAGE_SIZE, 0, 838 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 839 NULL, NULL, 2 * PAGE_SIZE, 1, BUS_SPACE_MAXSIZE_32BIT, 0, 840 &mpt->reply_dmat) != 0) { 841 mpt_prt(mpt, "cannot create a dma tag for replies\n"); 842 return (1); 843 } 844 845 /* Allocate some DMA accessible memory for replies */ 846 if (bus_dmamem_alloc(mpt->reply_dmat, (void **)&mpt->reply, 847 BUS_DMA_NOWAIT, &mpt->reply_dmap) != 0) { 848 mpt_prt(mpt, "cannot allocate %lu bytes of reply memory\n", 849 (u_long) (2 * PAGE_SIZE)); 850 return (1); 851 } 852 853 mi.mpt = mpt; 854 mi.error = 0; 855 856 /* Load and lock it into "bus space" */ 857 bus_dmamap_load(mpt->reply_dmat, mpt->reply_dmap, mpt->reply, 858 2 * PAGE_SIZE, mpt_map_rquest, &mi, 0); 859 860 if (mi.error) { 861 mpt_prt(mpt, "error %d loading dma map for DMA reply queue\n", 862 mi.error); 863 return (1); 864 } 865 mpt->reply_phys = mi.phys; 866 867 return (0); 868} 869 870/* Deallocate memory that was allocated by mpt_dma_mem_alloc 871 */ 872static void 873mpt_dma_mem_free(struct mpt_softc *mpt) 874{ 875 876 /* Make sure we aren't double destroying */ 877 if (mpt->reply_dmat == 0) { 878 mpt_lprt(mpt, MPT_PRT_DEBUG, "already released dma memory\n"); 879 return; 880 } 881 882 bus_dmamap_unload(mpt->reply_dmat, mpt->reply_dmap); 883 bus_dmamem_free(mpt->reply_dmat, mpt->reply, mpt->reply_dmap); 884 bus_dma_tag_destroy(mpt->reply_dmat); 885 bus_dma_tag_destroy(mpt->parent_dmat); 886 mpt->reply_dmat = NULL; 887 free(mpt->request_pool, M_DEVBUF); 888 mpt->request_pool = NULL; 889} 890 891/* Reads modifiable (via PCI transactions) config registers */ 892static void 893mpt_read_config_regs(struct mpt_softc *mpt) 894{ 895 896 mpt->pci_cfg.Command = pci_read_config(mpt->dev, PCIR_COMMAND, 2); 897 mpt->pci_cfg.LatencyTimer_LineSize = 898 pci_read_config(mpt->dev, PCIR_CACHELNSZ, 2); 899 mpt->pci_cfg.IO_BAR = pci_read_config(mpt->dev, PCIR_BAR(0), 4); 900 mpt->pci_cfg.Mem0_BAR[0] = pci_read_config(mpt->dev, PCIR_BAR(1), 4); 901 mpt->pci_cfg.Mem0_BAR[1] = pci_read_config(mpt->dev, PCIR_BAR(2), 4); 902 mpt->pci_cfg.Mem1_BAR[0] = pci_read_config(mpt->dev, PCIR_BAR(3), 4); 903 mpt->pci_cfg.Mem1_BAR[1] = pci_read_config(mpt->dev, PCIR_BAR(4), 4); 904 mpt->pci_cfg.ROM_BAR = pci_read_config(mpt->dev, PCIR_BIOS, 4); 905 mpt->pci_cfg.IntLine = pci_read_config(mpt->dev, PCIR_INTLINE, 1); 906 mpt->pci_cfg.PMCSR = pci_read_config(mpt->dev, 0x44, 4); 907} 908 909#if 0 910/* Sets modifiable config registers */ 911static void 912mpt_set_config_regs(struct mpt_softc *mpt) 913{ 914 uint32_t val; 915 916#define MPT_CHECK(reg, offset, size) \ 917 val = pci_read_config(mpt->dev, offset, size); \ 918 if (mpt->pci_cfg.reg != val) { \ 919 mpt_prt(mpt, \ 920 "Restoring " #reg " to 0x%X from 0x%X\n", \ 921 mpt->pci_cfg.reg, val); \ 922 } 923 924 if (mpt->verbose >= MPT_PRT_DEBUG) { 925 MPT_CHECK(Command, PCIR_COMMAND, 2); 926 MPT_CHECK(LatencyTimer_LineSize, PCIR_CACHELNSZ, 2); 927 MPT_CHECK(IO_BAR, PCIR_BAR(0), 4); 928 MPT_CHECK(Mem0_BAR[0], PCIR_BAR(1), 4); 929 MPT_CHECK(Mem0_BAR[1], PCIR_BAR(2), 4); 930 MPT_CHECK(Mem1_BAR[0], PCIR_BAR(3), 4); 931 MPT_CHECK(Mem1_BAR[1], PCIR_BAR(4), 4); 932 MPT_CHECK(ROM_BAR, PCIR_BIOS, 4); 933 MPT_CHECK(IntLine, PCIR_INTLINE, 1); 934 MPT_CHECK(PMCSR, 0x44, 4); 935 } 936#undef MPT_CHECK 937 938 pci_write_config(mpt->dev, PCIR_COMMAND, mpt->pci_cfg.Command, 2); 939 pci_write_config(mpt->dev, PCIR_CACHELNSZ, 940 mpt->pci_cfg.LatencyTimer_LineSize, 2); 941 pci_write_config(mpt->dev, PCIR_BAR(0), mpt->pci_cfg.IO_BAR, 4); 942 pci_write_config(mpt->dev, PCIR_BAR(1), mpt->pci_cfg.Mem0_BAR[0], 4); 943 pci_write_config(mpt->dev, PCIR_BAR(2), mpt->pci_cfg.Mem0_BAR[1], 4); 944 pci_write_config(mpt->dev, PCIR_BAR(3), mpt->pci_cfg.Mem1_BAR[0], 4); 945 pci_write_config(mpt->dev, PCIR_BAR(4), mpt->pci_cfg.Mem1_BAR[1], 4); 946 pci_write_config(mpt->dev, PCIR_BIOS, mpt->pci_cfg.ROM_BAR, 4); 947 pci_write_config(mpt->dev, PCIR_INTLINE, mpt->pci_cfg.IntLine, 1); 948 pci_write_config(mpt->dev, 0x44, mpt->pci_cfg.PMCSR, 4); 949} 950#endif 951 952static void 953mpt_pci_intr(void *arg) 954{ 955 struct mpt_softc *mpt; 956 957 mpt = (struct mpt_softc *)arg; 958 MPT_LOCK(mpt); 959 mpt_intr(mpt); 960 MPT_UNLOCK(mpt); 961} 962