mpi2_ioc.h revision 319435
1/*- 2 * Copyright (c) 2012-2015 LSI Corp. 3 * Copyright (c) 2013-2016 Avago Technologies 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the author nor the names of any co-contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD 31 * 32 * $FreeBSD: stable/11/sys/dev/mpr/mpi/mpi2_ioc.h 319435 2017-06-01 15:39:09Z slm $ 33 */ 34 35/* 36 * Copyright (c) 2000-2015 LSI Corporation. 37 * Copyright (c) 2013-2016 Avago Technologies 38 * All rights reserved. 39 * 40 * 41 * Name: mpi2_ioc.h 42 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages 43 * Creation Date: October 11, 2006 44 * 45 * mpi2_ioc.h Version: 02.00.30 46 * 47 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 48 * prefix are for use only on MPI v2.5 products, and must not be used 49 * with MPI v2.0 products. Unless otherwise noted, names beginning with 50 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 51 * 52 * Version History 53 * --------------- 54 * 55 * Date Version Description 56 * -------- -------- ------------------------------------------------------ 57 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 58 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to 59 * MaxTargets. 60 * Added TotalImageSize field to FWDownload Request. 61 * Added reserved words to FWUpload Request. 62 * 06-26-07 02.00.02 Added IR Configuration Change List Event. 63 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit 64 * request and replaced it with 65 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth. 66 * Replaced the MinReplyQueueDepth field of the IOCFacts 67 * reply with MaxReplyDescriptorPostQueueDepth. 68 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum 69 * depth for the Reply Descriptor Post Queue. 70 * Added SASAddress field to Initiator Device Table 71 * Overflow Event data. 72 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING 73 * for SAS Initiator Device Status Change Event data. 74 * Modified Reason Code defines for SAS Topology Change 75 * List Event data, including adding a bit for PHY Vacant 76 * status, and adding a mask for the Reason Code. 77 * Added define for 78 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING. 79 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID. 80 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of 81 * the IOCFacts Reply. 82 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. 83 * Moved MPI2_VERSION_UNION to mpi2.h. 84 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks 85 * instead of enables, and added SASBroadcastPrimitiveMasks 86 * field. 87 * Added Log Entry Added Event and related structure. 88 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID. 89 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET. 90 * Added MaxVolumes and MaxPersistentEntries fields to 91 * IOCFacts reply. 92 * Added ProtocalFlags and IOCCapabilities fields to 93 * MPI2_FW_IMAGE_HEADER. 94 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT. 95 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to 96 * a U16 (from a U32). 97 * Removed extra 's' from EventMasks name. 98 * 06-27-08 02.00.08 Fixed an offset in a comment. 99 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST. 100 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and 101 * renamed MinReplyFrameSize to ReplyFrameSize. 102 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX. 103 * Added two new RAIDOperation values for Integrated RAID 104 * Operations Status Event data. 105 * Added four new IR Configuration Change List Event data 106 * ReasonCode values. 107 * Added two new ReasonCode defines for SAS Device Status 108 * Change Event data. 109 * Added three new DiscoveryStatus bits for the SAS 110 * Discovery event data. 111 * Added Multiplexing Status Change bit to the PhyStatus 112 * field of the SAS Topology Change List event data. 113 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY. 114 * BootFlags are now product-specific. 115 * Added defines for the indivdual signature bytes 116 * for MPI2_INIT_IMAGE_FOOTER. 117 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define. 118 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR 119 * define. 120 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE 121 * define. 122 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define. 123 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define. 124 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define. 125 * Added two new reason codes for SAS Device Status Change 126 * Event. 127 * Added new event: SAS PHY Counter. 128 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure. 129 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. 130 * Added new product id family for 2208. 131 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST. 132 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY. 133 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY. 134 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY. 135 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define. 136 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define. 137 * Added Host Based Discovery Phy Event data. 138 * Added defines for ProductID Product field 139 * (MPI2_FW_HEADER_PID_). 140 * Modified values for SAS ProductID Family 141 * (MPI2_FW_HEADER_PID_FAMILY_). 142 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines. 143 * Added PowerManagementControl Request structures and 144 * defines. 145 * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete. 146 * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define. 147 * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC. 148 * 02-23-11 02.00.17 Added SAS NOTIFY Primitive event, and added 149 * SASNotifyPrimitiveMasks field to 150 * MPI2_EVENT_NOTIFICATION_REQUEST. 151 * Added Temperature Threshold Event. 152 * Added Host Message Event. 153 * Added Send Host Message request and reply. 154 * 05-25-11 02.00.18 For Extended Image Header, added 155 * MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and 156 * MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines. 157 * Deprecated MPI2_EXT_IMAGE_TYPE_MAX define. 158 * 08-24-11 02.00.19 Added PhysicalPort field to 159 * MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure. 160 * Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete. 161 * 11-18-11 02.00.20 Incorporating additions for MPI v2.5. 162 * 03-29-12 02.00.21 Added a product specific range to event values. 163 * 07-26-12 02.00.22 Added MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE. 164 * Added ElapsedSeconds field to 165 * MPI2_EVENT_DATA_IR_OPERATION_STATUS. 166 * 08-19-13 02.00.23 For IOCInit, added MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE 167 * and MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY. 168 * Added MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE. 169 * Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY. 170 * Added Encrypted Hash Extended Image. 171 * 12-05-13 02.00.24 Added MPI25_HASH_IMAGE_TYPE_BIOS. 172 * 11-18-14 02.00.25 Updated copyright information. 173 * 03-16-15 02.00.26 Updated for MPI v2.6. 174 * Added MPI2_EVENT_ACTIVE_CABLE_EXCEPTION and 175 * MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT. 176 * Added MPI2_EVENT_PCIE_LINK_COUNTER and 177 * MPI26_EVENT_DATA_PCIE_LINK_COUNTER. 178 * Added MPI26_CTRL_OP_SHUTDOWN. 179 * Added MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG 180 * Added MPI26_FW_HEADER_PID_FAMILY_3324_SAS and 181 * MPI26_FW_HEADER_PID_FAMILY_3516_SAS. 182 * 08-25-15 02.00.27 Added IC ARCH Class based signature defines. 183 * Added MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED event. 184 * Added ConigurationFlags field to IOCInit message to 185 * support NVMe SGL format control. 186 * Added PCIe SRIOV support. 187 * 02-17-16 02.00.28 Added SAS 4 22.5 gbs speed support. 188 * Added PCIe 4 16.0 GT/sec speec support. 189 * Removed AHCI support. 190 * Removed SOP support. 191 * 07-01-16 02.00.29 Added Archclass for 4008 product. 192 * Added IOCException MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED 193 * 08-23-16 02.00.30 Added new defines for the ImageType field of FWDownload 194 * Request Message. 195 * Added new defines for the ImageType field of FWUpload 196 * Request Message. 197 * Added new values for the RegionType field in the Layout 198 * Data sections of the FLASH Layout Extended Image Data. 199 * Added new defines for the ReasonCode field of 200 * Active Cable Exception Event. 201 * Added MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE and 202 * MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE. 203 * -------------------------------------------------------------------------- 204 */ 205 206#ifndef MPI2_IOC_H 207#define MPI2_IOC_H 208 209/***************************************************************************** 210* 211* IOC Messages 212* 213*****************************************************************************/ 214 215/**************************************************************************** 216* IOCInit message 217****************************************************************************/ 218 219/* IOCInit Request message */ 220typedef struct _MPI2_IOC_INIT_REQUEST 221{ 222 U8 WhoInit; /* 0x00 */ 223 U8 Reserved1; /* 0x01 */ 224 U8 ChainOffset; /* 0x02 */ 225 U8 Function; /* 0x03 */ 226 U16 Reserved2; /* 0x04 */ 227 U8 Reserved3; /* 0x06 */ 228 U8 MsgFlags; /* 0x07 */ 229 U8 VP_ID; /* 0x08 */ 230 U8 VF_ID; /* 0x09 */ 231 U16 Reserved4; /* 0x0A */ 232 U16 MsgVersion; /* 0x0C */ 233 U16 HeaderVersion; /* 0x0E */ 234 U32 Reserved5; /* 0x10 */ 235 U16 ConfigurationFlags; /* 0x14 */ 236 U8 HostPageSize; /* 0x16 */ 237 U8 HostMSIxVectors; /* 0x17 */ 238 U16 Reserved8; /* 0x18 */ 239 U16 SystemRequestFrameSize; /* 0x1A */ 240 U16 ReplyDescriptorPostQueueDepth; /* 0x1C */ 241 U16 ReplyFreeQueueDepth; /* 0x1E */ 242 U32 SenseBufferAddressHigh; /* 0x20 */ 243 U32 SystemReplyAddressHigh; /* 0x24 */ 244 U64 SystemRequestFrameBaseAddress; /* 0x28 */ 245 U64 ReplyDescriptorPostQueueAddress;/* 0x30 */ 246 U64 ReplyFreeQueueAddress; /* 0x38 */ 247 U64 TimeStamp; /* 0x40 */ 248} MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST, 249 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t; 250 251/* WhoInit values */ 252#define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 253#define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 254#define MPI2_WHOINIT_ROM_BIOS (0x02) 255#define MPI2_WHOINIT_PCI_PEER (0x03) 256#define MPI2_WHOINIT_HOST_DRIVER (0x04) 257#define MPI2_WHOINIT_MANUFACTURER (0x05) 258 259/* MsgFlags */ 260#define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01) 261 262/* MsgVersion */ 263#define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00) 264#define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8) 265#define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF) 266#define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0) 267 268/* HeaderVersion */ 269#define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00) 270#define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8) 271#define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF) 272#define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0) 273 274/* ConfigurationFlags */ 275#define MPI26_IOCINIT_CFGFLAGS_NVME_SGL_FORMAT (0x0001) 276 277/* minimum depth for a Reply Descriptor Post Queue */ 278#define MPI2_RDPQ_DEPTH_MIN (16) 279 280/* Reply Descriptor Post Queue Array Entry */ 281typedef struct _MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY 282{ 283 U64 RDPQBaseAddress; /* 0x00 */ 284 U32 Reserved1; /* 0x08 */ 285 U32 Reserved2; /* 0x0C */ 286} MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY, 287 MPI2_POINTER PTR_MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY, 288 Mpi2IOCInitRDPQArrayEntry, MPI2_POINTER pMpi2IOCInitRDPQArrayEntry; 289 290/* IOCInit Reply message */ 291typedef struct _MPI2_IOC_INIT_REPLY 292{ 293 U8 WhoInit; /* 0x00 */ 294 U8 Reserved1; /* 0x01 */ 295 U8 MsgLength; /* 0x02 */ 296 U8 Function; /* 0x03 */ 297 U16 Reserved2; /* 0x04 */ 298 U8 Reserved3; /* 0x06 */ 299 U8 MsgFlags; /* 0x07 */ 300 U8 VP_ID; /* 0x08 */ 301 U8 VF_ID; /* 0x09 */ 302 U16 Reserved4; /* 0x0A */ 303 U16 Reserved5; /* 0x0C */ 304 U16 IOCStatus; /* 0x0E */ 305 U32 IOCLogInfo; /* 0x10 */ 306} MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY, 307 Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t; 308 309 310/**************************************************************************** 311* IOCFacts message 312****************************************************************************/ 313 314/* IOCFacts Request message */ 315typedef struct _MPI2_IOC_FACTS_REQUEST 316{ 317 U16 Reserved1; /* 0x00 */ 318 U8 ChainOffset; /* 0x02 */ 319 U8 Function; /* 0x03 */ 320 U16 Reserved2; /* 0x04 */ 321 U8 Reserved3; /* 0x06 */ 322 U8 MsgFlags; /* 0x07 */ 323 U8 VP_ID; /* 0x08 */ 324 U8 VF_ID; /* 0x09 */ 325 U16 Reserved4; /* 0x0A */ 326} MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST, 327 Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t; 328 329 330/* IOCFacts Reply message */ 331typedef struct _MPI2_IOC_FACTS_REPLY 332{ 333 U16 MsgVersion; /* 0x00 */ 334 U8 MsgLength; /* 0x02 */ 335 U8 Function; /* 0x03 */ 336 U16 HeaderVersion; /* 0x04 */ 337 U8 IOCNumber; /* 0x06 */ 338 U8 MsgFlags; /* 0x07 */ 339 U8 VP_ID; /* 0x08 */ 340 U8 VF_ID; /* 0x09 */ 341 U16 Reserved1; /* 0x0A */ 342 U16 IOCExceptions; /* 0x0C */ 343 U16 IOCStatus; /* 0x0E */ 344 U32 IOCLogInfo; /* 0x10 */ 345 U8 MaxChainDepth; /* 0x14 */ 346 U8 WhoInit; /* 0x15 */ 347 U8 NumberOfPorts; /* 0x16 */ 348 U8 MaxMSIxVectors; /* 0x17 */ 349 U16 RequestCredit; /* 0x18 */ 350 U16 ProductID; /* 0x1A */ 351 U32 IOCCapabilities; /* 0x1C */ 352 MPI2_VERSION_UNION FWVersion; /* 0x20 */ 353 U16 IOCRequestFrameSize; /* 0x24 */ 354 U16 IOCMaxChainSegmentSize; /* 0x26 */ /* MPI 2.5 only; Reserved in MPI 2.0 */ 355 U16 MaxInitiators; /* 0x28 */ 356 U16 MaxTargets; /* 0x2A */ 357 U16 MaxSasExpanders; /* 0x2C */ 358 U16 MaxEnclosures; /* 0x2E */ 359 U16 ProtocolFlags; /* 0x30 */ 360 U16 HighPriorityCredit; /* 0x32 */ 361 U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */ 362 U8 ReplyFrameSize; /* 0x36 */ 363 U8 MaxVolumes; /* 0x37 */ 364 U16 MaxDevHandle; /* 0x38 */ 365 U16 MaxPersistentEntries; /* 0x3A */ 366 U16 MinDevHandle; /* 0x3C */ 367 U8 CurrentHostPageSize; /* 0x3E */ 368 U8 Reserved4; /* 0x3F */ 369 U8 SGEModifierMask; /* 0x40 */ 370 U8 SGEModifierValue; /* 0x41 */ 371 U8 SGEModifierShift; /* 0x42 */ 372 U8 Reserved5; /* 0x43 */ 373} MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY, 374 Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t; 375 376/* MsgVersion */ 377#define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00) 378#define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8) 379#define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF) 380#define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0) 381 382/* HeaderVersion */ 383#define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00) 384#define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8) 385#define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF) 386#define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0) 387 388/* IOCExceptions */ 389#define MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED (0x0400) 390#define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0200) 391#define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100) 392 393#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0) 394#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000) 395#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020) 396#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040) 397#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060) 398 399#define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010) 400#define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008) 401#define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004) 402#define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002) 403#define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001) 404 405/* defines for WhoInit field are after the IOCInit Request */ 406 407/* ProductID field uses MPI2_FW_HEADER_PID_ */ 408 409/* IOCCapabilities */ 410#define MPI26_IOCFACTS_CAPABILITY_PCIE_SRIOV (0x00100000) 411#define MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ (0x00080000) 412#define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE (0x00040000) 413#define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE (0x00020000) 414#define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000) 415#define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000) 416#define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000) 417#define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000) 418#define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000) 419#define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800) 420#define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100) 421#define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080) 422#define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040) 423#define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020) 424#define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010) 425#define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008) 426#define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004) 427 428/* ProtocolFlags */ 429#define MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES (0x0008) /* MPI v2.6 and later */ 430#define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002) 431#define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001) 432 433 434/**************************************************************************** 435* PortFacts message 436****************************************************************************/ 437 438/* PortFacts Request message */ 439typedef struct _MPI2_PORT_FACTS_REQUEST 440{ 441 U16 Reserved1; /* 0x00 */ 442 U8 ChainOffset; /* 0x02 */ 443 U8 Function; /* 0x03 */ 444 U16 Reserved2; /* 0x04 */ 445 U8 PortNumber; /* 0x06 */ 446 U8 MsgFlags; /* 0x07 */ 447 U8 VP_ID; /* 0x08 */ 448 U8 VF_ID; /* 0x09 */ 449 U16 Reserved3; /* 0x0A */ 450} MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST, 451 Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t; 452 453/* PortFacts Reply message */ 454typedef struct _MPI2_PORT_FACTS_REPLY 455{ 456 U16 Reserved1; /* 0x00 */ 457 U8 MsgLength; /* 0x02 */ 458 U8 Function; /* 0x03 */ 459 U16 Reserved2; /* 0x04 */ 460 U8 PortNumber; /* 0x06 */ 461 U8 MsgFlags; /* 0x07 */ 462 U8 VP_ID; /* 0x08 */ 463 U8 VF_ID; /* 0x09 */ 464 U16 Reserved3; /* 0x0A */ 465 U16 Reserved4; /* 0x0C */ 466 U16 IOCStatus; /* 0x0E */ 467 U32 IOCLogInfo; /* 0x10 */ 468 U8 Reserved5; /* 0x14 */ 469 U8 PortType; /* 0x15 */ 470 U16 Reserved6; /* 0x16 */ 471 U16 MaxPostedCmdBuffers; /* 0x18 */ 472 U16 Reserved7; /* 0x1A */ 473} MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY, 474 Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t; 475 476/* PortType values */ 477#define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00) 478#define MPI2_PORTFACTS_PORTTYPE_FC (0x10) 479#define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20) 480#define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30) 481#define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31) 482#define MPI2_PORTFACTS_PORTTYPE_TRI_MODE (0x40) /* MPI v2.6 and later */ 483 484 485/**************************************************************************** 486* PortEnable message 487****************************************************************************/ 488 489/* PortEnable Request message */ 490typedef struct _MPI2_PORT_ENABLE_REQUEST 491{ 492 U16 Reserved1; /* 0x00 */ 493 U8 ChainOffset; /* 0x02 */ 494 U8 Function; /* 0x03 */ 495 U8 Reserved2; /* 0x04 */ 496 U8 PortFlags; /* 0x05 */ 497 U8 Reserved3; /* 0x06 */ 498 U8 MsgFlags; /* 0x07 */ 499 U8 VP_ID; /* 0x08 */ 500 U8 VF_ID; /* 0x09 */ 501 U16 Reserved4; /* 0x0A */ 502} MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST, 503 Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t; 504 505 506/* PortEnable Reply message */ 507typedef struct _MPI2_PORT_ENABLE_REPLY 508{ 509 U16 Reserved1; /* 0x00 */ 510 U8 MsgLength; /* 0x02 */ 511 U8 Function; /* 0x03 */ 512 U8 Reserved2; /* 0x04 */ 513 U8 PortFlags; /* 0x05 */ 514 U8 Reserved3; /* 0x06 */ 515 U8 MsgFlags; /* 0x07 */ 516 U8 VP_ID; /* 0x08 */ 517 U8 VF_ID; /* 0x09 */ 518 U16 Reserved4; /* 0x0A */ 519 U16 Reserved5; /* 0x0C */ 520 U16 IOCStatus; /* 0x0E */ 521 U32 IOCLogInfo; /* 0x10 */ 522} MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY, 523 Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t; 524 525 526/**************************************************************************** 527* EventNotification message 528****************************************************************************/ 529 530/* EventNotification Request message */ 531#define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4) 532 533typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST 534{ 535 U16 Reserved1; /* 0x00 */ 536 U8 ChainOffset; /* 0x02 */ 537 U8 Function; /* 0x03 */ 538 U16 Reserved2; /* 0x04 */ 539 U8 Reserved3; /* 0x06 */ 540 U8 MsgFlags; /* 0x07 */ 541 U8 VP_ID; /* 0x08 */ 542 U8 VF_ID; /* 0x09 */ 543 U16 Reserved4; /* 0x0A */ 544 U32 Reserved5; /* 0x0C */ 545 U32 Reserved6; /* 0x10 */ 546 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */ 547 U16 SASBroadcastPrimitiveMasks; /* 0x24 */ 548 U16 SASNotifyPrimitiveMasks; /* 0x26 */ 549 U32 Reserved8; /* 0x28 */ 550} MPI2_EVENT_NOTIFICATION_REQUEST, 551 MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST, 552 Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t; 553 554 555/* EventNotification Reply message */ 556typedef struct _MPI2_EVENT_NOTIFICATION_REPLY 557{ 558 U16 EventDataLength; /* 0x00 */ 559 U8 MsgLength; /* 0x02 */ 560 U8 Function; /* 0x03 */ 561 U16 Reserved1; /* 0x04 */ 562 U8 AckRequired; /* 0x06 */ 563 U8 MsgFlags; /* 0x07 */ 564 U8 VP_ID; /* 0x08 */ 565 U8 VF_ID; /* 0x09 */ 566 U16 Reserved2; /* 0x0A */ 567 U16 Reserved3; /* 0x0C */ 568 U16 IOCStatus; /* 0x0E */ 569 U32 IOCLogInfo; /* 0x10 */ 570 U16 Event; /* 0x14 */ 571 U16 Reserved4; /* 0x16 */ 572 U32 EventContext; /* 0x18 */ 573 U32 EventData[1]; /* 0x1C */ 574} MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY, 575 Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t; 576 577/* AckRequired */ 578#define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00) 579#define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01) 580 581/* Event */ 582#define MPI2_EVENT_LOG_DATA (0x0001) 583#define MPI2_EVENT_STATE_CHANGE (0x0002) 584#define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005) 585#define MPI2_EVENT_EVENT_CHANGE (0x000A) 586#define MPI2_EVENT_TASK_SET_FULL (0x000E) /* obsolete */ 587#define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F) 588#define MPI2_EVENT_IR_OPERATION_STATUS (0x0014) 589#define MPI2_EVENT_SAS_DISCOVERY (0x0016) 590#define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017) 591#define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018) 592#define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019) 593#define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C) 594#define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D) 595#define MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE (0x001D) /* MPI v2.6 and later */ 596#define MPI2_EVENT_IR_VOLUME (0x001E) 597#define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F) 598#define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020) 599#define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021) 600#define MPI2_EVENT_SAS_PHY_COUNTER (0x0022) 601#define MPI2_EVENT_GPIO_INTERRUPT (0x0023) 602#define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024) 603#define MPI2_EVENT_SAS_QUIESCE (0x0025) 604#define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE (0x0026) 605#define MPI2_EVENT_TEMP_THRESHOLD (0x0027) 606#define MPI2_EVENT_HOST_MESSAGE (0x0028) 607#define MPI2_EVENT_POWER_PERFORMANCE_CHANGE (0x0029) 608#define MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE (0x0030) /* MPI v2.6 and later */ 609#define MPI2_EVENT_PCIE_ENUMERATION (0x0031) /* MPI v2.6 and later */ 610#define MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST (0x0032) /* MPI v2.6 and later */ 611#define MPI2_EVENT_PCIE_LINK_COUNTER (0x0033) /* MPI v2.6 and later */ 612#define MPI2_EVENT_ACTIVE_CABLE_EXCEPTION (0x0034) /* MPI v2.6 and later */ 613#define MPI2_EVENT_MIN_PRODUCT_SPECIFIC (0x006E) 614#define MPI2_EVENT_MAX_PRODUCT_SPECIFIC (0x007F) 615 616 617/* Log Entry Added Event data */ 618 619/* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */ 620#define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C) 621 622typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED 623{ 624 U64 TimeStamp; /* 0x00 */ 625 U32 Reserved1; /* 0x08 */ 626 U16 LogSequence; /* 0x0C */ 627 U16 LogEntryQualifier; /* 0x0E */ 628 U8 VP_ID; /* 0x10 */ 629 U8 VF_ID; /* 0x11 */ 630 U16 Reserved2; /* 0x12 */ 631 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */ 632} MPI2_EVENT_DATA_LOG_ENTRY_ADDED, 633 MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED, 634 Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t; 635 636 637/* GPIO Interrupt Event data */ 638 639typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT 640{ 641 U8 GPIONum; /* 0x00 */ 642 U8 Reserved1; /* 0x01 */ 643 U16 Reserved2; /* 0x02 */ 644} MPI2_EVENT_DATA_GPIO_INTERRUPT, 645 MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT, 646 Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t; 647 648 649/* Temperature Threshold Event data */ 650 651typedef struct _MPI2_EVENT_DATA_TEMPERATURE 652{ 653 U16 Status; /* 0x00 */ 654 U8 SensorNum; /* 0x02 */ 655 U8 Reserved1; /* 0x03 */ 656 U16 CurrentTemperature; /* 0x04 */ 657 U16 Reserved2; /* 0x06 */ 658 U32 Reserved3; /* 0x08 */ 659 U32 Reserved4; /* 0x0C */ 660} MPI2_EVENT_DATA_TEMPERATURE, 661 MPI2_POINTER PTR_MPI2_EVENT_DATA_TEMPERATURE, 662 Mpi2EventDataTemperature_t, MPI2_POINTER pMpi2EventDataTemperature_t; 663 664/* Temperature Threshold Event data Status bits */ 665#define MPI2_EVENT_TEMPERATURE3_EXCEEDED (0x0008) 666#define MPI2_EVENT_TEMPERATURE2_EXCEEDED (0x0004) 667#define MPI2_EVENT_TEMPERATURE1_EXCEEDED (0x0002) 668#define MPI2_EVENT_TEMPERATURE0_EXCEEDED (0x0001) 669 670 671/* Host Message Event data */ 672 673typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE 674{ 675 U8 SourceVF_ID; /* 0x00 */ 676 U8 Reserved1; /* 0x01 */ 677 U16 Reserved2; /* 0x02 */ 678 U32 Reserved3; /* 0x04 */ 679 U32 HostData[1]; /* 0x08 */ 680} MPI2_EVENT_DATA_HOST_MESSAGE, MPI2_POINTER PTR_MPI2_EVENT_DATA_HOST_MESSAGE, 681 Mpi2EventDataHostMessage_t, MPI2_POINTER pMpi2EventDataHostMessage_t; 682 683 684/* Power Performance Change Event data */ 685 686typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE 687{ 688 U8 CurrentPowerMode; /* 0x00 */ 689 U8 PreviousPowerMode; /* 0x01 */ 690 U16 Reserved1; /* 0x02 */ 691} MPI2_EVENT_DATA_POWER_PERF_CHANGE, 692 MPI2_POINTER PTR_MPI2_EVENT_DATA_POWER_PERF_CHANGE, 693 Mpi2EventDataPowerPerfChange_t, MPI2_POINTER pMpi2EventDataPowerPerfChange_t; 694 695/* defines for CurrentPowerMode and PreviousPowerMode fields */ 696#define MPI2_EVENT_PM_INIT_MASK (0xC0) 697#define MPI2_EVENT_PM_INIT_UNAVAILABLE (0x00) 698#define MPI2_EVENT_PM_INIT_HOST (0x40) 699#define MPI2_EVENT_PM_INIT_IO_UNIT (0x80) 700#define MPI2_EVENT_PM_INIT_PCIE_DPA (0xC0) 701 702#define MPI2_EVENT_PM_MODE_MASK (0x07) 703#define MPI2_EVENT_PM_MODE_UNAVAILABLE (0x00) 704#define MPI2_EVENT_PM_MODE_UNKNOWN (0x01) 705#define MPI2_EVENT_PM_MODE_FULL_POWER (0x04) 706#define MPI2_EVENT_PM_MODE_REDUCED_POWER (0x05) 707#define MPI2_EVENT_PM_MODE_STANDBY (0x06) 708 709 710/* Active Cable Exception Event data */ 711 712typedef struct _MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT 713{ 714 U32 ActiveCablePowerRequirement; /* 0x00 */ 715 U8 ReasonCode; /* 0x04 */ 716 U8 ReceptacleID; /* 0x05 */ 717 U16 Reserved1; /* 0x06 */ 718} MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT, 719 MPI2_POINTER PTR_MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT, 720 Mpi26EventDataActiveCableExcept_t, 721 MPI2_POINTER pMpi26EventDataActiveCableExcept_t; 722 723/* defines for ReasonCode field */ 724#define MPI26_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER (0x00) 725#define MPI26_EVENT_ACTIVE_CABLE_PRESENT (0x01) 726#define MPI26_EVENT_ACTIVE_CABLE_DEGRADED (0x02) 727 728/* Hard Reset Received Event data */ 729 730typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED 731{ 732 U8 Reserved1; /* 0x00 */ 733 U8 Port; /* 0x01 */ 734 U16 Reserved2; /* 0x02 */ 735} MPI2_EVENT_DATA_HARD_RESET_RECEIVED, 736 MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED, 737 Mpi2EventDataHardResetReceived_t, 738 MPI2_POINTER pMpi2EventDataHardResetReceived_t; 739 740 741/* Task Set Full Event data */ 742/* this event is obsolete */ 743 744typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL 745{ 746 U16 DevHandle; /* 0x00 */ 747 U16 CurrentDepth; /* 0x02 */ 748} MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL, 749 Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t; 750 751 752/* SAS Device Status Change Event data */ 753 754typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE 755{ 756 U16 TaskTag; /* 0x00 */ 757 U8 ReasonCode; /* 0x02 */ 758 U8 PhysicalPort; /* 0x03 */ 759 U8 ASC; /* 0x04 */ 760 U8 ASCQ; /* 0x05 */ 761 U16 DevHandle; /* 0x06 */ 762 U32 Reserved2; /* 0x08 */ 763 U64 SASAddress; /* 0x0C */ 764 U8 LUN[8]; /* 0x14 */ 765} MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 766 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 767 Mpi2EventDataSasDeviceStatusChange_t, 768 MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t; 769 770/* SAS Device Status Change Event data ReasonCode values */ 771#define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05) 772#define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07) 773#define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08) 774#define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09) 775#define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A) 776#define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B) 777#define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C) 778#define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D) 779#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E) 780#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F) 781#define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10) 782#define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11) 783#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12) 784 785 786/* Integrated RAID Operation Status Event data */ 787 788typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS 789{ 790 U16 VolDevHandle; /* 0x00 */ 791 U16 Reserved1; /* 0x02 */ 792 U8 RAIDOperation; /* 0x04 */ 793 U8 PercentComplete; /* 0x05 */ 794 U16 Reserved2; /* 0x06 */ 795 U32 ElapsedSeconds; /* 0x08 */ 796} MPI2_EVENT_DATA_IR_OPERATION_STATUS, 797 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS, 798 Mpi2EventDataIrOperationStatus_t, 799 MPI2_POINTER pMpi2EventDataIrOperationStatus_t; 800 801/* Integrated RAID Operation Status Event data RAIDOperation values */ 802#define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00) 803#define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01) 804#define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02) 805#define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03) 806#define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04) 807 808 809/* Integrated RAID Volume Event data */ 810 811typedef struct _MPI2_EVENT_DATA_IR_VOLUME 812{ 813 U16 VolDevHandle; /* 0x00 */ 814 U8 ReasonCode; /* 0x02 */ 815 U8 Reserved1; /* 0x03 */ 816 U32 NewValue; /* 0x04 */ 817 U32 PreviousValue; /* 0x08 */ 818} MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME, 819 Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t; 820 821/* Integrated RAID Volume Event data ReasonCode values */ 822#define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01) 823#define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02) 824#define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03) 825 826 827/* Integrated RAID Physical Disk Event data */ 828 829typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK 830{ 831 U16 Reserved1; /* 0x00 */ 832 U8 ReasonCode; /* 0x02 */ 833 U8 PhysDiskNum; /* 0x03 */ 834 U16 PhysDiskDevHandle; /* 0x04 */ 835 U16 Reserved2; /* 0x06 */ 836 U16 Slot; /* 0x08 */ 837 U16 EnclosureHandle; /* 0x0A */ 838 U32 NewValue; /* 0x0C */ 839 U32 PreviousValue; /* 0x10 */ 840} MPI2_EVENT_DATA_IR_PHYSICAL_DISK, 841 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK, 842 Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t; 843 844/* Integrated RAID Physical Disk Event data ReasonCode values */ 845#define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01) 846#define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02) 847#define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03) 848 849 850/* Integrated RAID Configuration Change List Event data */ 851 852/* 853 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 854 * one and check NumElements at runtime. 855 */ 856#ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT 857#define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1) 858#endif 859 860typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT 861{ 862 U16 ElementFlags; /* 0x00 */ 863 U16 VolDevHandle; /* 0x02 */ 864 U8 ReasonCode; /* 0x04 */ 865 U8 PhysDiskNum; /* 0x05 */ 866 U16 PhysDiskDevHandle; /* 0x06 */ 867} MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT, 868 Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t; 869 870/* IR Configuration Change List Event data ElementFlags values */ 871#define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F) 872#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000) 873#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001) 874#define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002) 875 876/* IR Configuration Change List Event data ReasonCode values */ 877#define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01) 878#define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02) 879#define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03) 880#define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04) 881#define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05) 882#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06) 883#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07) 884#define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08) 885#define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09) 886 887typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST 888{ 889 U8 NumElements; /* 0x00 */ 890 U8 Reserved1; /* 0x01 */ 891 U8 Reserved2; /* 0x02 */ 892 U8 ConfigNum; /* 0x03 */ 893 U32 Flags; /* 0x04 */ 894 MPI2_EVENT_IR_CONFIG_ELEMENT ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT]; /* 0x08 */ 895} MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, 896 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, 897 Mpi2EventDataIrConfigChangeList_t, 898 MPI2_POINTER pMpi2EventDataIrConfigChangeList_t; 899 900/* IR Configuration Change List Event data Flags values */ 901#define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001) 902 903 904/* SAS Discovery Event data */ 905 906typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY 907{ 908 U8 Flags; /* 0x00 */ 909 U8 ReasonCode; /* 0x01 */ 910 U8 PhysicalPort; /* 0x02 */ 911 U8 Reserved1; /* 0x03 */ 912 U32 DiscoveryStatus; /* 0x04 */ 913} MPI2_EVENT_DATA_SAS_DISCOVERY, 914 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY, 915 Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t; 916 917/* SAS Discovery Event data Flags values */ 918#define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02) 919#define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01) 920 921/* SAS Discovery Event data ReasonCode values */ 922#define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01) 923#define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02) 924 925/* SAS Discovery Event data DiscoveryStatus values */ 926#define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 927#define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000) 928#define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000) 929#define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 930#define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000) 931#define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 932#define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 933#define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000) 934#define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 935#define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800) 936#define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400) 937#define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200) 938#define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100) 939#define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080) 940#define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040) 941#define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020) 942#define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010) 943#define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004) 944#define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002) 945#define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001) 946 947 948/* SAS Broadcast Primitive Event data */ 949 950typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE 951{ 952 U8 PhyNum; /* 0x00 */ 953 U8 Port; /* 0x01 */ 954 U8 PortWidth; /* 0x02 */ 955 U8 Primitive; /* 0x03 */ 956} MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 957 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 958 Mpi2EventDataSasBroadcastPrimitive_t, 959 MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t; 960 961/* defines for the Primitive field */ 962#define MPI2_EVENT_PRIMITIVE_CHANGE (0x01) 963#define MPI2_EVENT_PRIMITIVE_SES (0x02) 964#define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03) 965#define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04) 966#define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05) 967#define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06) 968#define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07) 969#define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08) 970 971 972/* SAS Notify Primitive Event data */ 973 974typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE 975{ 976 U8 PhyNum; /* 0x00 */ 977 U8 Port; /* 0x01 */ 978 U8 Reserved1; /* 0x02 */ 979 U8 Primitive; /* 0x03 */ 980} MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE, 981 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE, 982 Mpi2EventDataSasNotifyPrimitive_t, 983 MPI2_POINTER pMpi2EventDataSasNotifyPrimitive_t; 984 985/* defines for the Primitive field */ 986#define MPI2_EVENT_NOTIFY_ENABLE_SPINUP (0x01) 987#define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED (0x02) 988#define MPI2_EVENT_NOTIFY_RESERVED1 (0x03) 989#define MPI2_EVENT_NOTIFY_RESERVED2 (0x04) 990 991 992/* SAS Initiator Device Status Change Event data */ 993 994typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE 995{ 996 U8 ReasonCode; /* 0x00 */ 997 U8 PhysicalPort; /* 0x01 */ 998 U16 DevHandle; /* 0x02 */ 999 U64 SASAddress; /* 0x04 */ 1000} MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 1001 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 1002 Mpi2EventDataSasInitDevStatusChange_t, 1003 MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t; 1004 1005/* SAS Initiator Device Status Change event ReasonCode values */ 1006#define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01) 1007#define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02) 1008 1009 1010/* SAS Initiator Device Table Overflow Event data */ 1011 1012typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW 1013{ 1014 U16 MaxInit; /* 0x00 */ 1015 U16 CurrentInit; /* 0x02 */ 1016 U64 SASAddress; /* 0x04 */ 1017} MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 1018 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 1019 Mpi2EventDataSasInitTableOverflow_t, 1020 MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t; 1021 1022 1023/* SAS Topology Change List Event data */ 1024 1025/* 1026 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1027 * one and check NumEntries at runtime. 1028 */ 1029#ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT 1030#define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1) 1031#endif 1032 1033typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY 1034{ 1035 U16 AttachedDevHandle; /* 0x00 */ 1036 U8 LinkRate; /* 0x02 */ 1037 U8 PhyStatus; /* 0x03 */ 1038} MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY, 1039 Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t; 1040 1041typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST 1042{ 1043 U16 EnclosureHandle; /* 0x00 */ 1044 U16 ExpanderDevHandle; /* 0x02 */ 1045 U8 NumPhys; /* 0x04 */ 1046 U8 Reserved1; /* 0x05 */ 1047 U16 Reserved2; /* 0x06 */ 1048 U8 NumEntries; /* 0x08 */ 1049 U8 StartPhyNum; /* 0x09 */ 1050 U8 ExpStatus; /* 0x0A */ 1051 U8 PhysicalPort; /* 0x0B */ 1052 MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/ 1053} MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, 1054 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, 1055 Mpi2EventDataSasTopologyChangeList_t, 1056 MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t; 1057 1058/* values for the ExpStatus field */ 1059#define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00) 1060#define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01) 1061#define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02) 1062#define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03) 1063#define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04) 1064 1065/* defines for the LinkRate field */ 1066#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0) 1067#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4) 1068#define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F) 1069#define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0) 1070 1071#define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00) 1072#define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01) 1073#define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02) 1074#define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03) 1075#define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04) 1076#define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05) 1077#define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06) 1078#define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08) 1079#define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09) 1080#define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A) 1081#define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0B) 1082#define MPI26_EVENT_SAS_TOPO_LR_RATE_22_5 (0x0C) 1083 1084/* values for the PhyStatus field */ 1085#define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80) 1086#define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10) 1087/* values for the PhyStatus ReasonCode sub-field */ 1088#define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F) 1089#define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01) 1090#define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02) 1091#define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03) 1092#define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04) 1093#define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05) 1094 1095 1096/* SAS Enclosure Device Status Change Event data */ 1097 1098typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE 1099{ 1100 U16 EnclosureHandle; /* 0x00 */ 1101 U8 ReasonCode; /* 0x02 */ 1102 U8 PhysicalPort; /* 0x03 */ 1103 U64 EnclosureLogicalID; /* 0x04 */ 1104 U16 NumSlots; /* 0x0C */ 1105 U16 StartSlot; /* 0x0E */ 1106 U32 PhyBits; /* 0x10 */ 1107} MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, 1108 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, 1109 Mpi2EventDataSasEnclDevStatusChange_t, 1110 MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t, 1111 MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE, 1112 MPI2_POINTER PTR_MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE, 1113 Mpi26EventDataEnclDevStatusChange_t, 1114 MPI2_POINTER pMpi26EventDataEnclDevStatusChange_t; 1115 1116/* SAS Enclosure Device Status Change event ReasonCode values */ 1117#define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01) 1118#define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02) 1119 1120/* Enclosure Device Status Change event ReasonCode values */ 1121#define MPI26_EVENT_ENCL_RC_ADDED (0x01) 1122#define MPI26_EVENT_ENCL_RC_NOT_RESPONDING (0x02) 1123 1124/* SAS PHY Counter Event data */ 1125 1126typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER 1127{ 1128 U64 TimeStamp; /* 0x00 */ 1129 U32 Reserved1; /* 0x08 */ 1130 U8 PhyEventCode; /* 0x0C */ 1131 U8 PhyNum; /* 0x0D */ 1132 U16 Reserved2; /* 0x0E */ 1133 U32 PhyEventInfo; /* 0x10 */ 1134 U8 CounterType; /* 0x14 */ 1135 U8 ThresholdWindow; /* 0x15 */ 1136 U8 TimeUnits; /* 0x16 */ 1137 U8 Reserved3; /* 0x17 */ 1138 U32 EventThreshold; /* 0x18 */ 1139 U16 ThresholdFlags; /* 0x1C */ 1140 U16 Reserved4; /* 0x1E */ 1141} MPI2_EVENT_DATA_SAS_PHY_COUNTER, 1142 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER, 1143 Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t; 1144 1145/* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the PhyEventCode field */ 1146 1147/* use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType field */ 1148 1149/* use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits field */ 1150 1151/* use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags field */ 1152 1153 1154/* SAS Quiesce Event data */ 1155 1156typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE 1157{ 1158 U8 ReasonCode; /* 0x00 */ 1159 U8 Reserved1; /* 0x01 */ 1160 U16 Reserved2; /* 0x02 */ 1161 U32 Reserved3; /* 0x04 */ 1162} MPI2_EVENT_DATA_SAS_QUIESCE, 1163 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_QUIESCE, 1164 Mpi2EventDataSasQuiesce_t, MPI2_POINTER pMpi2EventDataSasQuiesce_t; 1165 1166/* SAS Quiesce Event data ReasonCode values */ 1167#define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01) 1168#define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02) 1169 1170 1171/* Host Based Discovery Phy Event data */ 1172 1173typedef struct _MPI2_EVENT_HBD_PHY_SAS 1174{ 1175 U8 Flags; /* 0x00 */ 1176 U8 NegotiatedLinkRate; /* 0x01 */ 1177 U8 PhyNum; /* 0x02 */ 1178 U8 PhysicalPort; /* 0x03 */ 1179 U32 Reserved1; /* 0x04 */ 1180 U8 InitialFrame[28]; /* 0x08 */ 1181} MPI2_EVENT_HBD_PHY_SAS, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS, 1182 Mpi2EventHbdPhySas_t, MPI2_POINTER pMpi2EventHbdPhySas_t; 1183 1184/* values for the Flags field */ 1185#define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02) 1186#define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01) 1187 1188/* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for the NegotiatedLinkRate field */ 1189 1190typedef union _MPI2_EVENT_HBD_DESCRIPTOR 1191{ 1192 MPI2_EVENT_HBD_PHY_SAS Sas; 1193} MPI2_EVENT_HBD_DESCRIPTOR, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR, 1194 Mpi2EventHbdDescriptor_t, MPI2_POINTER pMpi2EventHbdDescriptor_t; 1195 1196typedef struct _MPI2_EVENT_DATA_HBD_PHY 1197{ 1198 U8 DescriptorType; /* 0x00 */ 1199 U8 Reserved1; /* 0x01 */ 1200 U16 Reserved2; /* 0x02 */ 1201 U32 Reserved3; /* 0x04 */ 1202 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /* 0x08 */ 1203} MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY, 1204 Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t; 1205 1206/* values for the DescriptorType field */ 1207#define MPI2_EVENT_HBD_DT_SAS (0x01) 1208 1209 1210/* PCIe Device Status Change Event data (MPI v2.6 and later) */ 1211 1212typedef struct _MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE 1213{ 1214 U16 TaskTag; /* 0x00 */ 1215 U8 ReasonCode; /* 0x02 */ 1216 U8 PhysicalPort; /* 0x03 */ 1217 U8 ASC; /* 0x04 */ 1218 U8 ASCQ; /* 0x05 */ 1219 U16 DevHandle; /* 0x06 */ 1220 U32 Reserved2; /* 0x08 */ 1221 U64 WWID; /* 0x0C */ 1222 U8 LUN[8]; /* 0x14 */ 1223} MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE, 1224 MPI2_POINTER PTR_MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE, 1225 Mpi26EventDataPCIeDeviceStatusChange_t, 1226 MPI2_POINTER pMpi26EventDataPCIeDeviceStatusChange_t; 1227 1228/* PCIe Device Status Change Event data ReasonCode values */ 1229#define MPI26_EVENT_PCIDEV_STAT_RC_SMART_DATA (0x05) 1230#define MPI26_EVENT_PCIDEV_STAT_RC_UNSUPPORTED (0x07) 1231#define MPI26_EVENT_PCIDEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08) 1232#define MPI26_EVENT_PCIDEV_STAT_RC_TASK_ABORT_INTERNAL (0x09) 1233#define MPI26_EVENT_PCIDEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A) 1234#define MPI26_EVENT_PCIDEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B) 1235#define MPI26_EVENT_PCIDEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C) 1236#define MPI26_EVENT_PCIDEV_STAT_RC_ASYNC_NOTIFICATION (0x0D) 1237#define MPI26_EVENT_PCIDEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E) 1238#define MPI26_EVENT_PCIDEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F) 1239#define MPI26_EVENT_PCIDEV_STAT_RC_DEV_INIT_FAILURE (0x10) 1240 1241 1242/* PCIe Enumeration Event data (MPI v2.6 and later) */ 1243 1244typedef struct _MPI26_EVENT_DATA_PCIE_ENUMERATION 1245{ 1246 U8 Flags; /* 0x00 */ 1247 U8 ReasonCode; /* 0x01 */ 1248 U8 PhysicalPort; /* 0x02 */ 1249 U8 Reserved1; /* 0x03 */ 1250 U32 EnumerationStatus; /* 0x04 */ 1251} MPI26_EVENT_DATA_PCIE_ENUMERATION, 1252 MPI2_POINTER PTR_MPI26_EVENT_DATA_PCIE_ENUMERATION, 1253 Mpi26EventDataPCIeEnumeration_t, 1254 MPI2_POINTER pMpi26EventDataPCIeEnumeration_t; 1255 1256/* PCIe Enumeration Event data Flags values */ 1257#define MPI26_EVENT_PCIE_ENUM_DEVICE_CHANGE (0x02) 1258#define MPI26_EVENT_PCIE_ENUM_IN_PROGRESS (0x01) 1259 1260/* PCIe Enumeration Event data ReasonCode values */ 1261#define MPI26_EVENT_PCIE_ENUM_RC_STARTED (0x01) 1262#define MPI26_EVENT_PCIE_ENUM_RC_COMPLETED (0x02) 1263 1264/* PCIe Enumeration Event data EnumerationStatus values */ 1265#define MPI26_EVENT_PCIE_ENUM_ES_MAX_SWITCHES_EXCEED (0x40000000) 1266#define MPI26_EVENT_PCIE_ENUM_ES_MAX_DEVICES_EXCEED (0x20000000) 1267#define MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED (0x10000000) 1268 1269 1270/* PCIe Topology Change List Event data (MPI v2.6 and later) */ 1271 1272/* 1273 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1274 * one and check NumEntries at runtime. 1275 */ 1276#ifndef MPI26_EVENT_PCIE_TOPO_PORT_COUNT 1277#define MPI26_EVENT_PCIE_TOPO_PORT_COUNT (1) 1278#endif 1279 1280typedef struct _MPI26_EVENT_PCIE_TOPO_PORT_ENTRY 1281{ 1282 U16 AttachedDevHandle; /* 0x00 */ 1283 U8 PortStatus; /* 0x02 */ 1284 U8 Reserved1; /* 0x03 */ 1285 U8 CurrentPortInfo; /* 0x04 */ 1286 U8 Reserved2; /* 0x05 */ 1287 U8 PreviousPortInfo; /* 0x06 */ 1288 U8 Reserved3; /* 0x07 */ 1289} MPI26_EVENT_PCIE_TOPO_PORT_ENTRY, 1290 MPI2_POINTER PTR_MPI26_EVENT_PCIE_TOPO_PORT_ENTRY, 1291 Mpi26EventPCIeTopoPortEntry_t, 1292 MPI2_POINTER pMpi26EventPCIeTopoPortEntry_t; 1293 1294/* PCIe Topology Change List Event data PortStatus values */ 1295#define MPI26_EVENT_PCIE_TOPO_PS_DEV_ADDED (0x01) 1296#define MPI26_EVENT_PCIE_TOPO_PS_NOT_RESPONDING (0x02) 1297#define MPI26_EVENT_PCIE_TOPO_PS_PORT_CHANGED (0x03) 1298#define MPI26_EVENT_PCIE_TOPO_PS_NO_CHANGE (0x04) 1299#define MPI26_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING (0x05) 1300 1301/* PCIe Topology Change List Event data defines for CurrentPortInfo and PreviousPortInfo */ 1302#define MPI26_EVENT_PCIE_TOPO_PI_LANE_MASK (0xF0) 1303#define MPI26_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN (0x00) 1304#define MPI26_EVENT_PCIE_TOPO_PI_1_LANE (0x10) 1305#define MPI26_EVENT_PCIE_TOPO_PI_2_LANES (0x20) 1306#define MPI26_EVENT_PCIE_TOPO_PI_4_LANES (0x30) 1307#define MPI26_EVENT_PCIE_TOPO_PI_8_LANES (0x40) 1308 1309#define MPI26_EVENT_PCIE_TOPO_PI_RATE_MASK (0x0F) 1310#define MPI26_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN (0x00) 1311#define MPI26_EVENT_PCIE_TOPO_PI_RATE_DISABLED (0x01) 1312#define MPI26_EVENT_PCIE_TOPO_PI_RATE_2_5 (0x02) 1313#define MPI26_EVENT_PCIE_TOPO_PI_RATE_5_0 (0x03) 1314#define MPI26_EVENT_PCIE_TOPO_PI_RATE_8_0 (0x04) 1315#define MPI26_EVENT_PCIE_TOPO_PI_RATE_16_0 (0x05) 1316 1317typedef struct _MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST 1318{ 1319 U16 EnclosureHandle; /* 0x00 */ 1320 U16 SwitchDevHandle; /* 0x02 */ 1321 U8 NumPorts; /* 0x04 */ 1322 U8 Reserved1; /* 0x05 */ 1323 U16 Reserved2; /* 0x06 */ 1324 U8 NumEntries; /* 0x08 */ 1325 U8 StartPortNum; /* 0x09 */ 1326 U8 SwitchStatus; /* 0x0A */ 1327 U8 PhysicalPort; /* 0x0B */ 1328 MPI26_EVENT_PCIE_TOPO_PORT_ENTRY PortEntry[MPI26_EVENT_PCIE_TOPO_PORT_COUNT]; /* 0x0C */ 1329} MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST, 1330 MPI2_POINTER PTR_MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST, 1331 Mpi26EventDataPCIeTopologyChangeList_t, 1332 MPI2_POINTER pMpi26EventDataPCIeTopologyChangeList_t; 1333 1334/* PCIe Topology Change List Event data SwitchStatus values */ 1335#define MPI26_EVENT_PCIE_TOPO_SS_NO_PCIE_SWITCH (0x00) 1336#define MPI26_EVENT_PCIE_TOPO_SS_ADDED (0x01) 1337#define MPI26_EVENT_PCIE_TOPO_SS_NOT_RESPONDING (0x02) 1338#define MPI26_EVENT_PCIE_TOPO_SS_RESPONDING (0x03) 1339#define MPI26_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING (0x04) 1340 1341/* PCIe Link Counter Event data (MPI v2.6 and later) */ 1342 1343typedef struct _MPI26_EVENT_DATA_PCIE_LINK_COUNTER 1344{ 1345 U64 TimeStamp; /* 0x00 */ 1346 U32 Reserved1; /* 0x08 */ 1347 U8 LinkEventCode; /* 0x0C */ 1348 U8 LinkNum; /* 0x0D */ 1349 U16 Reserved2; /* 0x0E */ 1350 U32 LinkEventInfo; /* 0x10 */ 1351 U8 CounterType; /* 0x14 */ 1352 U8 ThresholdWindow; /* 0x15 */ 1353 U8 TimeUnits; /* 0x16 */ 1354 U8 Reserved3; /* 0x17 */ 1355 U32 EventThreshold; /* 0x18 */ 1356 U16 ThresholdFlags; /* 0x1C */ 1357 U16 Reserved4; /* 0x1E */ 1358} MPI26_EVENT_DATA_PCIE_LINK_COUNTER, 1359 MPI2_POINTER PTR_MPI26_EVENT_DATA_PCIE_LINK_COUNTER, 1360 Mpi26EventDataPcieLinkCounter_t, MPI2_POINTER pMpi26EventDataPcieLinkCounter_t; 1361 1362 1363/* use MPI26_PCIELINK3_EVTCODE_ values from mpi2_cnfg.h for the LinkEventCode field */ 1364 1365/* use MPI26_PCIELINK3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType field */ 1366 1367/* use MPI26_PCIELINK3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits field */ 1368 1369/* use MPI26_PCIELINK3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags field */ 1370 1371/**************************************************************************** 1372* EventAck message 1373****************************************************************************/ 1374 1375/* EventAck Request message */ 1376typedef struct _MPI2_EVENT_ACK_REQUEST 1377{ 1378 U16 Reserved1; /* 0x00 */ 1379 U8 ChainOffset; /* 0x02 */ 1380 U8 Function; /* 0x03 */ 1381 U16 Reserved2; /* 0x04 */ 1382 U8 Reserved3; /* 0x06 */ 1383 U8 MsgFlags; /* 0x07 */ 1384 U8 VP_ID; /* 0x08 */ 1385 U8 VF_ID; /* 0x09 */ 1386 U16 Reserved4; /* 0x0A */ 1387 U16 Event; /* 0x0C */ 1388 U16 Reserved5; /* 0x0E */ 1389 U32 EventContext; /* 0x10 */ 1390} MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST, 1391 Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t; 1392 1393 1394/* EventAck Reply message */ 1395typedef struct _MPI2_EVENT_ACK_REPLY 1396{ 1397 U16 Reserved1; /* 0x00 */ 1398 U8 MsgLength; /* 0x02 */ 1399 U8 Function; /* 0x03 */ 1400 U16 Reserved2; /* 0x04 */ 1401 U8 Reserved3; /* 0x06 */ 1402 U8 MsgFlags; /* 0x07 */ 1403 U8 VP_ID; /* 0x08 */ 1404 U8 VF_ID; /* 0x09 */ 1405 U16 Reserved4; /* 0x0A */ 1406 U16 Reserved5; /* 0x0C */ 1407 U16 IOCStatus; /* 0x0E */ 1408 U32 IOCLogInfo; /* 0x10 */ 1409} MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY, 1410 Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t; 1411 1412 1413/**************************************************************************** 1414* SendHostMessage message 1415****************************************************************************/ 1416 1417/* SendHostMessage Request message */ 1418typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST 1419{ 1420 U16 HostDataLength; /* 0x00 */ 1421 U8 ChainOffset; /* 0x02 */ 1422 U8 Function; /* 0x03 */ 1423 U16 Reserved1; /* 0x04 */ 1424 U8 Reserved2; /* 0x06 */ 1425 U8 MsgFlags; /* 0x07 */ 1426 U8 VP_ID; /* 0x08 */ 1427 U8 VF_ID; /* 0x09 */ 1428 U16 Reserved3; /* 0x0A */ 1429 U8 Reserved4; /* 0x0C */ 1430 U8 DestVF_ID; /* 0x0D */ 1431 U16 Reserved5; /* 0x0E */ 1432 U32 Reserved6; /* 0x10 */ 1433 U32 Reserved7; /* 0x14 */ 1434 U32 Reserved8; /* 0x18 */ 1435 U32 Reserved9; /* 0x1C */ 1436 U32 Reserved10; /* 0x20 */ 1437 U32 HostData[1]; /* 0x24 */ 1438} MPI2_SEND_HOST_MESSAGE_REQUEST, 1439 MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REQUEST, 1440 Mpi2SendHostMessageRequest_t, MPI2_POINTER pMpi2SendHostMessageRequest_t; 1441 1442 1443/* SendHostMessage Reply message */ 1444typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY 1445{ 1446 U16 HostDataLength; /* 0x00 */ 1447 U8 MsgLength; /* 0x02 */ 1448 U8 Function; /* 0x03 */ 1449 U16 Reserved1; /* 0x04 */ 1450 U8 Reserved2; /* 0x06 */ 1451 U8 MsgFlags; /* 0x07 */ 1452 U8 VP_ID; /* 0x08 */ 1453 U8 VF_ID; /* 0x09 */ 1454 U16 Reserved3; /* 0x0A */ 1455 U16 Reserved4; /* 0x0C */ 1456 U16 IOCStatus; /* 0x0E */ 1457 U32 IOCLogInfo; /* 0x10 */ 1458} MPI2_SEND_HOST_MESSAGE_REPLY, MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REPLY, 1459 Mpi2SendHostMessageReply_t, MPI2_POINTER pMpi2SendHostMessageReply_t; 1460 1461 1462/**************************************************************************** 1463* FWDownload message 1464****************************************************************************/ 1465 1466/* MPI v2.0 FWDownload Request message */ 1467typedef struct _MPI2_FW_DOWNLOAD_REQUEST 1468{ 1469 U8 ImageType; /* 0x00 */ 1470 U8 Reserved1; /* 0x01 */ 1471 U8 ChainOffset; /* 0x02 */ 1472 U8 Function; /* 0x03 */ 1473 U16 Reserved2; /* 0x04 */ 1474 U8 Reserved3; /* 0x06 */ 1475 U8 MsgFlags; /* 0x07 */ 1476 U8 VP_ID; /* 0x08 */ 1477 U8 VF_ID; /* 0x09 */ 1478 U16 Reserved4; /* 0x0A */ 1479 U32 TotalImageSize; /* 0x0C */ 1480 U32 Reserved5; /* 0x10 */ 1481 MPI2_MPI_SGE_UNION SGL; /* 0x14 */ 1482} MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST, 1483 Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest; 1484 1485#define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01) 1486 1487#define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01) 1488#define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02) 1489#define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06) 1490#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07) 1491#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08) 1492#define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09) 1493#define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A) 1494#define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1495#define MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY (0x0C) /* MPI v2.5 and newer */ 1496#define MPI2_FW_DOWNLOAD_ITYPE_SBR (0x0E) 1497#define MPI2_FW_DOWNLOAD_ITYPE_SBR_BACKUP (0x0F) 1498#define MPI2_FW_DOWNLOAD_ITYPE_HIIM (0x10) 1499#define MPI2_FW_DOWNLOAD_ITYPE_HIIA (0x11) 1500#define MPI2_FW_DOWNLOAD_ITYPE_CTLR (0x12) 1501#define MPI2_FW_DOWNLOAD_ITYPE_IMR_FIRMWARE (0x13) 1502#define MPI2_FW_DOWNLOAD_ITYPE_MR_NVDATA (0x14) 1503#define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0) 1504 1505/* MPI v2.0 FWDownload TransactionContext Element */ 1506typedef struct _MPI2_FW_DOWNLOAD_TCSGE 1507{ 1508 U8 Reserved1; /* 0x00 */ 1509 U8 ContextSize; /* 0x01 */ 1510 U8 DetailsLength; /* 0x02 */ 1511 U8 Flags; /* 0x03 */ 1512 U32 Reserved2; /* 0x04 */ 1513 U32 ImageOffset; /* 0x08 */ 1514 U32 ImageSize; /* 0x0C */ 1515} MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE, 1516 Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t; 1517 1518 1519/* MPI v2.5 FWDownload Request message */ 1520typedef struct _MPI25_FW_DOWNLOAD_REQUEST 1521{ 1522 U8 ImageType; /* 0x00 */ 1523 U8 Reserved1; /* 0x01 */ 1524 U8 ChainOffset; /* 0x02 */ 1525 U8 Function; /* 0x03 */ 1526 U16 Reserved2; /* 0x04 */ 1527 U8 Reserved3; /* 0x06 */ 1528 U8 MsgFlags; /* 0x07 */ 1529 U8 VP_ID; /* 0x08 */ 1530 U8 VF_ID; /* 0x09 */ 1531 U16 Reserved4; /* 0x0A */ 1532 U32 TotalImageSize; /* 0x0C */ 1533 U32 Reserved5; /* 0x10 */ 1534 U32 Reserved6; /* 0x14 */ 1535 U32 ImageOffset; /* 0x18 */ 1536 U32 ImageSize; /* 0x1C */ 1537 MPI25_SGE_IO_UNION SGL; /* 0x20 */ 1538} MPI25_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI25_FW_DOWNLOAD_REQUEST, 1539 Mpi25FWDownloadRequest, MPI2_POINTER pMpi25FWDownloadRequest; 1540 1541 1542/* FWDownload Reply message */ 1543typedef struct _MPI2_FW_DOWNLOAD_REPLY 1544{ 1545 U8 ImageType; /* 0x00 */ 1546 U8 Reserved1; /* 0x01 */ 1547 U8 MsgLength; /* 0x02 */ 1548 U8 Function; /* 0x03 */ 1549 U16 Reserved2; /* 0x04 */ 1550 U8 Reserved3; /* 0x06 */ 1551 U8 MsgFlags; /* 0x07 */ 1552 U8 VP_ID; /* 0x08 */ 1553 U8 VF_ID; /* 0x09 */ 1554 U16 Reserved4; /* 0x0A */ 1555 U16 Reserved5; /* 0x0C */ 1556 U16 IOCStatus; /* 0x0E */ 1557 U32 IOCLogInfo; /* 0x10 */ 1558} MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY, 1559 Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t; 1560 1561 1562/**************************************************************************** 1563* FWUpload message 1564****************************************************************************/ 1565 1566/* MPI v2.0 FWUpload Request message */ 1567typedef struct _MPI2_FW_UPLOAD_REQUEST 1568{ 1569 U8 ImageType; /* 0x00 */ 1570 U8 Reserved1; /* 0x01 */ 1571 U8 ChainOffset; /* 0x02 */ 1572 U8 Function; /* 0x03 */ 1573 U16 Reserved2; /* 0x04 */ 1574 U8 Reserved3; /* 0x06 */ 1575 U8 MsgFlags; /* 0x07 */ 1576 U8 VP_ID; /* 0x08 */ 1577 U8 VF_ID; /* 0x09 */ 1578 U16 Reserved4; /* 0x0A */ 1579 U32 Reserved5; /* 0x0C */ 1580 U32 Reserved6; /* 0x10 */ 1581 MPI2_MPI_SGE_UNION SGL; /* 0x14 */ 1582} MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST, 1583 Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t; 1584 1585#define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00) 1586#define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01) 1587#define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02) 1588#define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05) 1589#define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06) 1590#define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07) 1591#define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08) 1592#define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09) 1593#define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A) 1594#define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1595#define MPI2_FW_UPLOAD_ITYPE_CBB_BACKUP (0x0D) 1596#define MPI2_FW_UPLOAD_ITYPE_SBR (0x0E) 1597#define MPI2_FW_UPLOAD_ITYPE_SBR_BACKUP (0x0F) 1598#define MPI2_FW_UPLOAD_ITYPE_HIIM (0x10) 1599#define MPI2_FW_UPLOAD_ITYPE_HIIA (0x11) 1600#define MPI2_FW_UPLOAD_ITYPE_CTLR (0x12) 1601#define MPI2_FW_UPLOAD_ITYPE_IMR_FIRMWARE (0x13) 1602#define MPI2_FW_UPLOAD_ITYPE_MR_NVDATA (0x14) 1603 1604/* MPI v2.0 FWUpload TransactionContext Element */ 1605typedef struct _MPI2_FW_UPLOAD_TCSGE 1606{ 1607 U8 Reserved1; /* 0x00 */ 1608 U8 ContextSize; /* 0x01 */ 1609 U8 DetailsLength; /* 0x02 */ 1610 U8 Flags; /* 0x03 */ 1611 U32 Reserved2; /* 0x04 */ 1612 U32 ImageOffset; /* 0x08 */ 1613 U32 ImageSize; /* 0x0C */ 1614} MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE, 1615 Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t; 1616 1617 1618/* MPI v2.5 FWUpload Request message */ 1619typedef struct _MPI25_FW_UPLOAD_REQUEST 1620{ 1621 U8 ImageType; /* 0x00 */ 1622 U8 Reserved1; /* 0x01 */ 1623 U8 ChainOffset; /* 0x02 */ 1624 U8 Function; /* 0x03 */ 1625 U16 Reserved2; /* 0x04 */ 1626 U8 Reserved3; /* 0x06 */ 1627 U8 MsgFlags; /* 0x07 */ 1628 U8 VP_ID; /* 0x08 */ 1629 U8 VF_ID; /* 0x09 */ 1630 U16 Reserved4; /* 0x0A */ 1631 U32 Reserved5; /* 0x0C */ 1632 U32 Reserved6; /* 0x10 */ 1633 U32 Reserved7; /* 0x14 */ 1634 U32 ImageOffset; /* 0x18 */ 1635 U32 ImageSize; /* 0x1C */ 1636 MPI25_SGE_IO_UNION SGL; /* 0x20 */ 1637} MPI25_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI25_FW_UPLOAD_REQUEST, 1638 Mpi25FWUploadRequest_t, MPI2_POINTER pMpi25FWUploadRequest_t; 1639 1640 1641/* FWUpload Reply message */ 1642typedef struct _MPI2_FW_UPLOAD_REPLY 1643{ 1644 U8 ImageType; /* 0x00 */ 1645 U8 Reserved1; /* 0x01 */ 1646 U8 MsgLength; /* 0x02 */ 1647 U8 Function; /* 0x03 */ 1648 U16 Reserved2; /* 0x04 */ 1649 U8 Reserved3; /* 0x06 */ 1650 U8 MsgFlags; /* 0x07 */ 1651 U8 VP_ID; /* 0x08 */ 1652 U8 VF_ID; /* 0x09 */ 1653 U16 Reserved4; /* 0x0A */ 1654 U16 Reserved5; /* 0x0C */ 1655 U16 IOCStatus; /* 0x0E */ 1656 U32 IOCLogInfo; /* 0x10 */ 1657 U32 ActualImageSize; /* 0x14 */ 1658} MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY, 1659 Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t; 1660 1661 1662/* FW Image Header */ 1663typedef struct _MPI2_FW_IMAGE_HEADER 1664{ 1665 U32 Signature; /* 0x00 */ 1666 U32 Signature0; /* 0x04 */ 1667 U32 Signature1; /* 0x08 */ 1668 U32 Signature2; /* 0x0C */ 1669 MPI2_VERSION_UNION MPIVersion; /* 0x10 */ 1670 MPI2_VERSION_UNION FWVersion; /* 0x14 */ 1671 MPI2_VERSION_UNION NVDATAVersion; /* 0x18 */ 1672 MPI2_VERSION_UNION PackageVersion; /* 0x1C */ 1673 U16 VendorID; /* 0x20 */ 1674 U16 ProductID; /* 0x22 */ 1675 U16 ProtocolFlags; /* 0x24 */ 1676 U16 Reserved26; /* 0x26 */ 1677 U32 IOCCapabilities; /* 0x28 */ 1678 U32 ImageSize; /* 0x2C */ 1679 U32 NextImageHeaderOffset; /* 0x30 */ 1680 U32 Checksum; /* 0x34 */ 1681 U32 Reserved38; /* 0x38 */ 1682 U32 Reserved3C; /* 0x3C */ 1683 U32 Reserved40; /* 0x40 */ 1684 U32 Reserved44; /* 0x44 */ 1685 U32 Reserved48; /* 0x48 */ 1686 U32 Reserved4C; /* 0x4C */ 1687 U32 Reserved50; /* 0x50 */ 1688 U32 Reserved54; /* 0x54 */ 1689 U32 Reserved58; /* 0x58 */ 1690 U32 Reserved5C; /* 0x5C */ 1691 U32 BootFlags; /* 0x60 */ /* reserved in MPI v2.5 and earlier */ 1692 U32 FirmwareVersionNameWhat; /* 0x64 */ 1693 U8 FirmwareVersionName[32]; /* 0x68 */ 1694 U32 VendorNameWhat; /* 0x88 */ 1695 U8 VendorName[32]; /* 0x8C */ 1696 U32 PackageNameWhat; /* 0x88 */ 1697 U8 PackageName[32]; /* 0x8C */ 1698 U32 ReservedD0; /* 0xD0 */ 1699 U32 ReservedD4; /* 0xD4 */ 1700 U32 ReservedD8; /* 0xD8 */ 1701 U32 ReservedDC; /* 0xDC */ 1702 U32 ReservedE0; /* 0xE0 */ 1703 U32 ReservedE4; /* 0xE4 */ 1704 U32 ReservedE8; /* 0xE8 */ 1705 U32 ReservedEC; /* 0xEC */ 1706 U32 ReservedF0; /* 0xF0 */ 1707 U32 ReservedF4; /* 0xF4 */ 1708 U32 ReservedF8; /* 0xF8 */ 1709 U32 ReservedFC; /* 0xFC */ 1710} MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER, 1711 Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t; 1712 1713/* Signature field */ 1714#define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00) 1715#define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000) 1716#define MPI2_FW_HEADER_SIGNATURE (0xEA000000) 1717#define MPI26_FW_HEADER_SIGNATURE (0xEB000000) 1718 1719/* Signature0 field */ 1720#define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04) 1721#define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A) 1722#define MPI26_FW_HEADER_SIGNATURE0_BASE (0x5AEAA500) /* Last byte is defined by architecture */ 1723#define MPI26_FW_HEADER_SIGNATURE0_ARC_0 (0x5A) 1724#define MPI26_FW_HEADER_SIGNATURE0_ARC_1 (0x00) 1725#define MPI26_FW_HEADER_SIGNATURE0_ARC_2 (0x01) 1726#define MPI26_FW_HEADER_SIGNATURE0_ARC_3 (0x02) 1727#define MPI26_FW_HEADER_SIGNATURE0 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_0) // legacy (0x5AEAA55A) 1728#define MPI26_FW_HEADER_SIGNATURE0_3516 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_1) 1729#define MPI26_FW_HEADER_SIGNATURE0_4008 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_3) 1730 1731/* Signature1 field */ 1732#define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08) 1733#define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5) 1734#define MPI26_FW_HEADER_SIGNATURE1 (0xA55AEAA5) 1735 1736/* Signature2 field */ 1737#define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C) 1738#define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA) 1739#define MPI26_FW_HEADER_SIGNATURE2 (0x5AA55AEA) 1740 1741 1742/* defines for using the ProductID field */ 1743#define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000) 1744#define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000) 1745 1746#define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00) 1747#define MPI2_FW_HEADER_PID_PROD_A (0x0000) 1748#define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200) 1749#define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700) 1750 1751 1752#define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF) 1753/* SAS ProductID Family bits */ 1754#define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013) 1755#define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014) 1756#define MPI25_FW_HEADER_PID_FAMILY_3108_SAS (0x0021) 1757#define MPI26_FW_HEADER_PID_FAMILY_3324_SAS (0x0028) 1758#define MPI26_FW_HEADER_PID_FAMILY_3516_SAS (0x0031) 1759 1760/* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */ 1761 1762/* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */ 1763 1764 1765#define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C) 1766#define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30) 1767#define MPI26_FW_HEADER_BOOTFLAGS_OFFSET (0x60) 1768#define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64) 1769 1770#define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840) 1771 1772#define MPI2_FW_HEADER_SIZE (0x100) 1773 1774 1775/* Extended Image Header */ 1776typedef struct _MPI2_EXT_IMAGE_HEADER 1777 1778{ 1779 U8 ImageType; /* 0x00 */ 1780 U8 Reserved1; /* 0x01 */ 1781 U16 Reserved2; /* 0x02 */ 1782 U32 Checksum; /* 0x04 */ 1783 U32 ImageSize; /* 0x08 */ 1784 U32 NextImageHeaderOffset; /* 0x0C */ 1785 U32 PackageVersion; /* 0x10 */ 1786 U32 Reserved3; /* 0x14 */ 1787 U32 Reserved4; /* 0x18 */ 1788 U32 Reserved5; /* 0x1C */ 1789 U8 IdentifyString[32]; /* 0x20 */ 1790} MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER, 1791 Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t; 1792 1793/* useful offsets */ 1794#define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00) 1795#define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08) 1796#define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C) 1797 1798#define MPI2_EXT_IMAGE_HEADER_SIZE (0x40) 1799 1800/* defines for the ImageType field */ 1801#define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00) 1802#define MPI2_EXT_IMAGE_TYPE_FW (0x01) 1803#define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03) 1804#define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04) 1805#define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05) 1806#define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06) 1807#define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07) 1808#define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08) 1809#define MPI2_EXT_IMAGE_TYPE_ENCRYPTED_HASH (0x09) /* MPI v2.5 and newer */ 1810#define MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC (0x80) 1811#define MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC (0xFF) 1812 1813#define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC) /* deprecated */ 1814 1815 1816 1817/* FLASH Layout Extended Image Data */ 1818 1819/* 1820 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1821 * one and check RegionsPerLayout at runtime. 1822 */ 1823#ifndef MPI2_FLASH_NUMBER_OF_REGIONS 1824#define MPI2_FLASH_NUMBER_OF_REGIONS (1) 1825#endif 1826 1827/* 1828 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1829 * one and check NumberOfLayouts at runtime. 1830 */ 1831#ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS 1832#define MPI2_FLASH_NUMBER_OF_LAYOUTS (1) 1833#endif 1834 1835typedef struct _MPI2_FLASH_REGION 1836{ 1837 U8 RegionType; /* 0x00 */ 1838 U8 Reserved1; /* 0x01 */ 1839 U16 Reserved2; /* 0x02 */ 1840 U32 RegionOffset; /* 0x04 */ 1841 U32 RegionSize; /* 0x08 */ 1842 U32 Reserved3; /* 0x0C */ 1843} MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION, 1844 Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t; 1845 1846typedef struct _MPI2_FLASH_LAYOUT 1847{ 1848 U32 FlashSize; /* 0x00 */ 1849 U32 Reserved1; /* 0x04 */ 1850 U32 Reserved2; /* 0x08 */ 1851 U32 Reserved3; /* 0x0C */ 1852 MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */ 1853} MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT, 1854 Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t; 1855 1856typedef struct _MPI2_FLASH_LAYOUT_DATA 1857{ 1858 U8 ImageRevision; /* 0x00 */ 1859 U8 Reserved1; /* 0x01 */ 1860 U8 SizeOfRegion; /* 0x02 */ 1861 U8 Reserved2; /* 0x03 */ 1862 U16 NumberOfLayouts; /* 0x04 */ 1863 U16 RegionsPerLayout; /* 0x06 */ 1864 U16 MinimumSectorAlignment; /* 0x08 */ 1865 U16 Reserved3; /* 0x0A */ 1866 U32 Reserved4; /* 0x0C */ 1867 MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */ 1868} MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA, 1869 Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t; 1870 1871/* defines for the RegionType field */ 1872#define MPI2_FLASH_REGION_UNUSED (0x00) 1873#define MPI2_FLASH_REGION_FIRMWARE (0x01) 1874#define MPI2_FLASH_REGION_BIOS (0x02) 1875#define MPI2_FLASH_REGION_NVDATA (0x03) 1876#define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05) 1877#define MPI2_FLASH_REGION_MFG_INFORMATION (0x06) 1878#define MPI2_FLASH_REGION_CONFIG_1 (0x07) 1879#define MPI2_FLASH_REGION_CONFIG_2 (0x08) 1880#define MPI2_FLASH_REGION_MEGARAID (0x09) 1881#define MPI2_FLASH_REGION_COMMON_BOOT_BLOCK (0x0A) 1882#define MPI2_FLASH_REGION_INIT (MPI2_FLASH_REGION_COMMON_BOOT_BLOCK) /* older name */ 1883#define MPI2_FLASH_REGION_CBB_BACKUP (0x0D) 1884#define MPI2_FLASH_REGION_SBR (0x0E) 1885#define MPI2_FLASH_REGION_SBR_BACKUP (0x0F) 1886#define MPI2_FLASH_REGION_HIIM (0x10) 1887#define MPI2_FLASH_REGION_HIIA (0x11) 1888#define MPI2_FLASH_REGION_CTLR (0x12) 1889#define MPI2_FLASH_REGION_IMR_FIRMWARE (0x13) 1890#define MPI2_FLASH_REGION_MR_NVDATA (0x14) 1891 1892/* ImageRevision */ 1893#define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00) 1894 1895 1896 1897/* Supported Devices Extended Image Data */ 1898 1899/* 1900 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1901 * one and check NumberOfDevices at runtime. 1902 */ 1903#ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES 1904#define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1) 1905#endif 1906 1907typedef struct _MPI2_SUPPORTED_DEVICE 1908{ 1909 U16 DeviceID; /* 0x00 */ 1910 U16 VendorID; /* 0x02 */ 1911 U16 DeviceIDMask; /* 0x04 */ 1912 U16 Reserved1; /* 0x06 */ 1913 U8 LowPCIRev; /* 0x08 */ 1914 U8 HighPCIRev; /* 0x09 */ 1915 U16 Reserved2; /* 0x0A */ 1916 U32 Reserved3; /* 0x0C */ 1917} MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE, 1918 Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t; 1919 1920typedef struct _MPI2_SUPPORTED_DEVICES_DATA 1921{ 1922 U8 ImageRevision; /* 0x00 */ 1923 U8 Reserved1; /* 0x01 */ 1924 U8 NumberOfDevices; /* 0x02 */ 1925 U8 Reserved2; /* 0x03 */ 1926 U32 Reserved3; /* 0x04 */ 1927 MPI2_SUPPORTED_DEVICE SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */ 1928} MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA, 1929 Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t; 1930 1931/* ImageRevision */ 1932#define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00) 1933 1934 1935/* Init Extended Image Data */ 1936 1937typedef struct _MPI2_INIT_IMAGE_FOOTER 1938 1939{ 1940 U32 BootFlags; /* 0x00 */ 1941 U32 ImageSize; /* 0x04 */ 1942 U32 Signature0; /* 0x08 */ 1943 U32 Signature1; /* 0x0C */ 1944 U32 Signature2; /* 0x10 */ 1945 U32 ResetVector; /* 0x14 */ 1946} MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER, 1947 Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t; 1948 1949/* defines for the BootFlags field */ 1950#define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00) 1951 1952/* defines for the ImageSize field */ 1953#define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04) 1954 1955/* defines for the Signature0 field */ 1956#define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08) 1957#define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA) 1958 1959/* defines for the Signature1 field */ 1960#define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C) 1961#define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5) 1962 1963/* defines for the Signature2 field */ 1964#define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10) 1965#define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A) 1966 1967/* Signature fields as individual bytes */ 1968#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA) 1969#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A) 1970#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5) 1971#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A) 1972 1973#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5) 1974#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA) 1975#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A) 1976#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5) 1977 1978#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A) 1979#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5) 1980#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA) 1981#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A) 1982 1983/* defines for the ResetVector field */ 1984#define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14) 1985 1986 1987/* Encrypted Hash Extended Image Data */ 1988 1989typedef struct _MPI25_ENCRYPTED_HASH_ENTRY 1990{ 1991 U8 HashImageType; /* 0x00 */ 1992 U8 HashAlgorithm; /* 0x01 */ 1993 U8 EncryptionAlgorithm; /* 0x02 */ 1994 U8 Reserved1; /* 0x03 */ 1995 U32 Reserved2; /* 0x04 */ 1996 U32 EncryptedHash[1]; /* 0x08 */ /* variable length */ 1997} MPI25_ENCRYPTED_HASH_ENTRY, MPI2_POINTER PTR_MPI25_ENCRYPTED_HASH_ENTRY, 1998 Mpi25EncryptedHashEntry_t, MPI2_POINTER pMpi25EncryptedHashEntry_t; 1999 2000/* values for HashImageType */ 2001#define MPI25_HASH_IMAGE_TYPE_UNUSED (0x00) 2002#define MPI25_HASH_IMAGE_TYPE_FIRMWARE (0x01) 2003#define MPI25_HASH_IMAGE_TYPE_BIOS (0x02) 2004 2005/* values for HashAlgorithm */ 2006#define MPI25_HASH_ALGORITHM_UNUSED (0x00) 2007#define MPI25_HASH_ALGORITHM_SHA256 (0x01) 2008 2009/* values for EncryptionAlgorithm */ 2010#define MPI25_ENCRYPTION_ALG_UNUSED (0x00) 2011#define MPI25_ENCRYPTION_ALG_RSA256 (0x01) 2012 2013typedef struct _MPI25_ENCRYPTED_HASH_DATA 2014{ 2015 U8 ImageVersion; /* 0x00 */ 2016 U8 NumHash; /* 0x01 */ 2017 U16 Reserved1; /* 0x02 */ 2018 U32 Reserved2; /* 0x04 */ 2019 MPI25_ENCRYPTED_HASH_ENTRY EncryptedHashEntry[1]; /* 0x08 */ /* variable number of entries */ 2020} MPI25_ENCRYPTED_HASH_DATA, MPI2_POINTER PTR_MPI25_ENCRYPTED_HASH_DATA, 2021 Mpi25EncryptedHashData_t, MPI2_POINTER pMpi25EncryptedHashData_t; 2022 2023/**************************************************************************** 2024* PowerManagementControl message 2025****************************************************************************/ 2026 2027/* PowerManagementControl Request message */ 2028typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST 2029{ 2030 U8 Feature; /* 0x00 */ 2031 U8 Reserved1; /* 0x01 */ 2032 U8 ChainOffset; /* 0x02 */ 2033 U8 Function; /* 0x03 */ 2034 U16 Reserved2; /* 0x04 */ 2035 U8 Reserved3; /* 0x06 */ 2036 U8 MsgFlags; /* 0x07 */ 2037 U8 VP_ID; /* 0x08 */ 2038 U8 VF_ID; /* 0x09 */ 2039 U16 Reserved4; /* 0x0A */ 2040 U8 Parameter1; /* 0x0C */ 2041 U8 Parameter2; /* 0x0D */ 2042 U8 Parameter3; /* 0x0E */ 2043 U8 Parameter4; /* 0x0F */ 2044 U32 Reserved5; /* 0x10 */ 2045 U32 Reserved6; /* 0x14 */ 2046} MPI2_PWR_MGMT_CONTROL_REQUEST, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REQUEST, 2047 Mpi2PwrMgmtControlRequest_t, MPI2_POINTER pMpi2PwrMgmtControlRequest_t; 2048 2049/* defines for the Feature field */ 2050#define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01) 2051#define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02) 2052#define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03) /* obsolete */ 2053#define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04) 2054#define MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE (0x05) /* reserved in MPI 2.0 */ 2055#define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80) 2056#define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF) 2057 2058/* parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */ 2059/* Parameter1 contains a PHY number */ 2060/* Parameter2 indicates power condition action using these defines */ 2061#define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01) 2062#define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02) 2063#define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03) 2064/* Parameter3 and Parameter4 are reserved */ 2065 2066/* parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION Feature */ 2067/* Parameter1 contains SAS port width modulation group number */ 2068/* Parameter2 indicates IOC action using these defines */ 2069#define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01) 2070#define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02) 2071#define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03) 2072/* Parameter3 indicates desired modulation level using these defines */ 2073#define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00) 2074#define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01) 2075#define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02) 2076#define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03) 2077/* Parameter4 is reserved */ 2078 2079/* this next set (_PCIE_LINK) is obsolete */ 2080/* parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */ 2081/* Parameter1 indicates desired PCIe link speed using these defines */ 2082#define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00) /* obsolete */ 2083#define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01) /* obsolete */ 2084#define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02) /* obsolete */ 2085/* Parameter2 indicates desired PCIe link width using these defines */ 2086#define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01) /* obsolete */ 2087#define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02) /* obsolete */ 2088#define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04) /* obsolete */ 2089#define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08) /* obsolete */ 2090/* Parameter3 and Parameter4 are reserved */ 2091 2092/* parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */ 2093/* Parameter1 indicates desired IOC hardware clock speed using these defines */ 2094#define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01) 2095#define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02) 2096#define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04) 2097#define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08) 2098/* Parameter2, Parameter3, and Parameter4 are reserved */ 2099 2100/* parameter usage for the MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE Feature */ 2101/* Parameter1 indicates host action regarding global power management mode */ 2102#define MPI2_PM_CONTROL_PARAM1_TAKE_CONTROL (0x01) 2103#define MPI2_PM_CONTROL_PARAM1_CHANGE_GLOBAL_MODE (0x02) 2104#define MPI2_PM_CONTROL_PARAM1_RELEASE_CONTROL (0x03) 2105/* Parameter2 indicates the requested global power management mode */ 2106#define MPI2_PM_CONTROL_PARAM2_FULL_PWR_PERF (0x01) 2107#define MPI2_PM_CONTROL_PARAM2_REDUCED_PWR_PERF (0x08) 2108#define MPI2_PM_CONTROL_PARAM2_STANDBY (0x40) 2109/* Parameter3 and Parameter4 are reserved */ 2110 2111 2112/* PowerManagementControl Reply message */ 2113typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY 2114{ 2115 U8 Feature; /* 0x00 */ 2116 U8 Reserved1; /* 0x01 */ 2117 U8 MsgLength; /* 0x02 */ 2118 U8 Function; /* 0x03 */ 2119 U16 Reserved2; /* 0x04 */ 2120 U8 Reserved3; /* 0x06 */ 2121 U8 MsgFlags; /* 0x07 */ 2122 U8 VP_ID; /* 0x08 */ 2123 U8 VF_ID; /* 0x09 */ 2124 U16 Reserved4; /* 0x0A */ 2125 U16 Reserved5; /* 0x0C */ 2126 U16 IOCStatus; /* 0x0E */ 2127 U32 IOCLogInfo; /* 0x10 */ 2128} MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY, 2129 Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t; 2130 2131 2132/**************************************************************************** 2133* IO Unit Control messages (MPI v2.6 and later only.) 2134****************************************************************************/ 2135 2136/* IO Unit Control Request Message */ 2137typedef struct _MPI26_IOUNIT_CONTROL_REQUEST 2138{ 2139 U8 Operation; /* 0x00 */ 2140 U8 Reserved1; /* 0x01 */ 2141 U8 ChainOffset; /* 0x02 */ 2142 U8 Function; /* 0x03 */ 2143 U16 DevHandle; /* 0x04 */ 2144 U8 IOCParameter; /* 0x06 */ 2145 U8 MsgFlags; /* 0x07 */ 2146 U8 VP_ID; /* 0x08 */ 2147 U8 VF_ID; /* 0x09 */ 2148 U16 Reserved3; /* 0x0A */ 2149 U16 Reserved4; /* 0x0C */ 2150 U8 PhyNum; /* 0x0E */ 2151 U8 PrimFlags; /* 0x0F */ 2152 U32 Primitive; /* 0x10 */ 2153 U8 LookupMethod; /* 0x14 */ 2154 U8 Reserved5; /* 0x15 */ 2155 U16 SlotNumber; /* 0x16 */ 2156 U64 LookupAddress; /* 0x18 */ 2157 U32 IOCParameterValue; /* 0x20 */ 2158 U32 Reserved7; /* 0x24 */ 2159 U32 Reserved8; /* 0x28 */ 2160} MPI26_IOUNIT_CONTROL_REQUEST, 2161 MPI2_POINTER PTR_MPI26_IOUNIT_CONTROL_REQUEST, 2162 Mpi26IoUnitControlRequest_t, MPI2_POINTER pMpi26IoUnitControlRequest_t; 2163 2164/* values for the Operation field */ 2165#define MPI26_CTRL_OP_CLEAR_ALL_PERSISTENT (0x02) 2166#define MPI26_CTRL_OP_SAS_PHY_LINK_RESET (0x06) 2167#define MPI26_CTRL_OP_SAS_PHY_HARD_RESET (0x07) 2168#define MPI26_CTRL_OP_PHY_CLEAR_ERROR_LOG (0x08) 2169#define MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG (0x09) 2170#define MPI26_CTRL_OP_SAS_SEND_PRIMITIVE (0x0A) 2171#define MPI26_CTRL_OP_FORCE_FULL_DISCOVERY (0x0B) 2172#define MPI26_CTRL_OP_REMOVE_DEVICE (0x0D) 2173#define MPI26_CTRL_OP_LOOKUP_MAPPING (0x0E) 2174#define MPI26_CTRL_OP_SET_IOC_PARAMETER (0x0F) 2175#define MPI26_CTRL_OP_ENABLE_FP_DEVICE (0x10) 2176#define MPI26_CTRL_OP_DISABLE_FP_DEVICE (0x11) 2177#define MPI26_CTRL_OP_ENABLE_FP_ALL (0x12) 2178#define MPI26_CTRL_OP_DISABLE_FP_ALL (0x13) 2179#define MPI26_CTRL_OP_DEV_ENABLE_NCQ (0x14) 2180#define MPI26_CTRL_OP_DEV_DISABLE_NCQ (0x15) 2181#define MPI26_CTRL_OP_SHUTDOWN (0x16) 2182#define MPI26_CTRL_OP_DEV_ENABLE_PERSIST_CONNECTION (0x17) 2183#define MPI26_CTRL_OP_DEV_DISABLE_PERSIST_CONNECTION (0x18) 2184#define MPI26_CTRL_OP_DEV_CLOSE_PERSIST_CONNECTION (0x19) 2185#define MPI26_CTRL_OP_ENABLE_NVME_SGL_FORMAT (0x1A) 2186#define MPI26_CTRL_OP_DISABLE_NVME_SGL_FORMAT (0x1B) 2187#define MPI26_CTRL_OP_PRODUCT_SPECIFIC_MIN (0x80) 2188 2189/* values for the PrimFlags field */ 2190#define MPI26_CTRL_PRIMFLAGS_SINGLE (0x08) 2191#define MPI26_CTRL_PRIMFLAGS_TRIPLE (0x02) 2192#define MPI26_CTRL_PRIMFLAGS_REDUNDANT (0x01) 2193 2194/* values for the LookupMethod field */ 2195#define MPI26_CTRL_LOOKUP_METHOD_WWID_ADDRESS (0x01) 2196#define MPI26_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT (0x02) 2197#define MPI26_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03) 2198 2199 2200/* IO Unit Control Reply Message */ 2201typedef struct _MPI26_IOUNIT_CONTROL_REPLY 2202{ 2203 U8 Operation; /* 0x00 */ 2204 U8 Reserved1; /* 0x01 */ 2205 U8 MsgLength; /* 0x02 */ 2206 U8 Function; /* 0x03 */ 2207 U16 DevHandle; /* 0x04 */ 2208 U8 IOCParameter; /* 0x06 */ 2209 U8 MsgFlags; /* 0x07 */ 2210 U8 VP_ID; /* 0x08 */ 2211 U8 VF_ID; /* 0x09 */ 2212 U16 Reserved3; /* 0x0A */ 2213 U16 Reserved4; /* 0x0C */ 2214 U16 IOCStatus; /* 0x0E */ 2215 U32 IOCLogInfo; /* 0x10 */ 2216} MPI26_IOUNIT_CONTROL_REPLY, MPI2_POINTER PTR_MPI26_IOUNIT_CONTROL_REPLY, 2217 Mpi26IoUnitControlReply_t, MPI2_POINTER pMpi26IoUnitControlReply_t; 2218 2219 2220#endif 2221 2222