1265236Sken/*- 2283661Sslm * Copyright (c) 2012-2015 LSI Corp. 3299263Sslm * Copyright (c) 2013-2016 Avago Technologies 4265236Sken * All rights reserved. 5265236Sken * 6265236Sken * Redistribution and use in source and binary forms, with or without 7265236Sken * modification, are permitted provided that the following conditions 8265236Sken * are met: 9265236Sken * 1. Redistributions of source code must retain the above copyright 10265236Sken * notice, this list of conditions and the following disclaimer. 11265236Sken * 2. Redistributions in binary form must reproduce the above copyright 12265236Sken * notice, this list of conditions and the following disclaimer in the 13265236Sken * documentation and/or other materials provided with the distribution. 14265236Sken * 3. Neither the name of the author nor the names of any co-contributors 15265236Sken * may be used to endorse or promote products derived from this software 16265236Sken * without specific prior written permission. 17265236Sken * 18265236Sken * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19265236Sken * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20265236Sken * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21265236Sken * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22265236Sken * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23265236Sken * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24265236Sken * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25265236Sken * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26265236Sken * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27265236Sken * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28265236Sken * SUCH DAMAGE. 29265236Sken * 30283661Sslm * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD 31265236Sken * 32265236Sken * $FreeBSD: stable/11/sys/dev/mpr/mpi/mpi2_cnfg.h 331903 2018-04-03 02:29:17Z mav $ 33265236Sken */ 34265236Sken 35265236Sken/* 36283661Sslm * Copyright (c) 2000-2015 LSI Corporation. 37299263Sslm * Copyright (c) 2013-2016 Avago Technologies 38299263Sslm * All rights reserved. 39265236Sken * 40265236Sken * 41265236Sken * Name: mpi2_cnfg.h 42265236Sken * Title: MPI Configuration messages and pages 43265236Sken * Creation Date: November 10, 2006 44265236Sken * 45331903Smav * mpi2_cnfg.h Version: 02.00.40 46265236Sken * 47265236Sken * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 48265236Sken * prefix are for use only on MPI v2.5 products, and must not be used 49265236Sken * with MPI v2.0 products. Unless otherwise noted, names beginning with 50265236Sken * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 51265236Sken * 52265236Sken * Version History 53265236Sken * --------------- 54265236Sken * 55265236Sken * Date Version Description 56265236Sken * -------- -------- ------------------------------------------------------ 57265236Sken * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 58265236Sken * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags. 59265236Sken * Added Manufacturing Page 11. 60265236Sken * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE 61265236Sken * define. 62265236Sken * 06-26-07 02.00.02 Adding generic structure for product-specific 63265236Sken * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS. 64265236Sken * Rework of BIOS Page 2 configuration page. 65265236Sken * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the 66265236Sken * forms. 67265236Sken * Added configuration pages IOC Page 8 and Driver 68265236Sken * Persistent Mapping Page 0. 69265236Sken * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated 70265236Sken * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1, 71265236Sken * RAID Physical Disk Pages 0 and 1, RAID Configuration 72265236Sken * Page 0). 73265236Sken * Added new value for AccessStatus field of SAS Device 74265236Sken * Page 0 (_SATA_NEEDS_INITIALIZATION). 75265236Sken * 10-31-07 02.00.04 Added missing SEPDevHandle field to 76265236Sken * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 77265236Sken * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for 78265236Sken * NVDATA. 79265236Sken * Modified IOC Page 7 to use masks and added field for 80265236Sken * SASBroadcastPrimitiveMasks. 81265236Sken * Added MPI2_CONFIG_PAGE_BIOS_4. 82265236Sken * Added MPI2_CONFIG_PAGE_LOG_0. 83265236Sken * 02-29-08 02.00.06 Modified various names to make them 32-character unique. 84265236Sken * Added SAS Device IDs. 85265236Sken * Updated Integrated RAID configuration pages including 86265236Sken * Manufacturing Page 4, IOC Page 6, and RAID Configuration 87265236Sken * Page 0. 88265236Sken * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA. 89265236Sken * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION. 90265236Sken * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING. 91265236Sken * Added missing MaxNumRoutedSasAddresses field to 92265236Sken * MPI2_CONFIG_PAGE_EXPANDER_0. 93265236Sken * Added SAS Port Page 0. 94265236Sken * Modified structure layout for 95265236Sken * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0. 96265236Sken * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use 97265236Sken * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array. 98265236Sken * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF 99265236Sken * to 0x000000FF. 100265236Sken * Added two new values for the Physical Disk Coercion Size 101265236Sken * bits in the Flags field of Manufacturing Page 4. 102265236Sken * Added product-specific Manufacturing pages 16 to 31. 103265236Sken * Modified Flags bits for controlling write cache on SATA 104265236Sken * drives in IO Unit Page 1. 105265236Sken * Added new bit to AdditionalControlFlags of SAS IO Unit 106265236Sken * Page 1 to control Invalid Topology Correction. 107265236Sken * Added additional defines for RAID Volume Page 0 108265236Sken * VolumeStatusFlags field. 109265236Sken * Modified meaning of RAID Volume Page 0 VolumeSettings 110265236Sken * define for auto-configure of hot-swap drives. 111265236Sken * Added SupportedPhysDisks field to RAID Volume Page 1 and 112265236Sken * added related defines. 113265236Sken * Added PhysDiskAttributes field (and related defines) to 114265236Sken * RAID Physical Disk Page 0. 115265236Sken * Added MPI2_SAS_PHYINFO_PHY_VACANT define. 116265236Sken * Added three new DiscoveryStatus bits for SAS IO Unit 117265236Sken * Page 0 and SAS Expander Page 0. 118265236Sken * Removed multiplexing information from SAS IO Unit pages. 119265236Sken * Added BootDeviceWaitTime field to SAS IO Unit Page 4. 120265236Sken * Removed Zone Address Resolved bit from PhyInfo and from 121265236Sken * Expander Page 0 Flags field. 122265236Sken * Added two new AccessStatus values to SAS Device Page 0 123265236Sken * for indicating routing problems. Added 3 reserved words 124265236Sken * to this page. 125265236Sken * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3. 126265236Sken * Inserted missing reserved field into structure for IOC 127265236Sken * Page 6. 128265236Sken * Added more pending task bits to RAID Volume Page 0 129265236Sken * VolumeStatusFlags defines. 130265236Sken * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define. 131265236Sken * Added a new DiscoveryStatus bit for SAS IO Unit Page 0 132265236Sken * and SAS Expander Page 0 to flag a downstream initiator 133265236Sken * when in simplified routing mode. 134265236Sken * Removed SATA Init Failure defines for DiscoveryStatus 135265236Sken * fields of SAS IO Unit Page 0 and SAS Expander Page 0. 136265236Sken * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define. 137265236Sken * Added PortGroups, DmaGroup, and ControlGroup fields to 138265236Sken * SAS Device Page 0. 139265236Sken * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO 140265236Sken * Unit Page 6. 141265236Sken * Added expander reduced functionality data to SAS 142265236Sken * Expander Page 0. 143265236Sken * Added SAS PHY Page 2 and SAS PHY Page 3. 144265236Sken * 07-30-09 02.00.12 Added IO Unit Page 7. 145265236Sken * Added new device ids. 146265236Sken * Added SAS IO Unit Page 5. 147265236Sken * Added partial and slumber power management capable flags 148265236Sken * to SAS Device Page 0 Flags field. 149265236Sken * Added PhyInfo defines for power condition. 150265236Sken * Added Ethernet configuration pages. 151265236Sken * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY. 152265236Sken * Added SAS PHY Page 4 structure and defines. 153265236Sken * 02-10-10 02.00.14 Modified the comments for the configuration page 154265236Sken * structures that contain an array of data. The host 155265236Sken * should use the "count" field in the page data (e.g. the 156265236Sken * NumPhys field) to determine the number of valid elements 157265236Sken * in the array. 158265236Sken * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines. 159265236Sken * Added PowerManagementCapabilities to IO Unit Page 7. 160265236Sken * Added PortWidthModGroup field to 161265236Sken * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS. 162265236Sken * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines. 163265236Sken * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines. 164265236Sken * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines. 165265236Sken * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT 166265236Sken * define. 167265236Sken * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define. 168265236Sken * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define. 169265236Sken * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing) 170265236Sken * defines. 171265236Sken * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to 172265236Sken * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for 173265236Sken * the Pinout field. 174265236Sken * Added BoardTemperature and BoardTemperatureUnits fields 175265236Sken * to MPI2_CONFIG_PAGE_IO_UNIT_7. 176265236Sken * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define 177265236Sken * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure. 178265236Sken * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST. 179265236Sken * Added IO Unit Page 8, IO Unit Page 9, 180265236Sken * and IO Unit Page 10. 181265236Sken * Added SASNotifyPrimitiveMasks field to 182265236Sken * MPI2_CONFIG_PAGE_IOC_7. 183265236Sken * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec). 184265236Sken * 05-25-11 02.00.20 Cleaned up a few comments. 185265236Sken * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities 186265236Sken * for PCIe link as obsolete. 187265236Sken * Added SpinupFlags field containing a Disable Spin-up bit 188265236Sken * to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO 189265236Sken * Unit Page 4. 190265236Sken * 11-18-11 02.00.22 Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT. 191265236Sken * Added UEFIVersion field to BIOS Page 1 and defined new 192265236Sken * BiosOptions bits. 193265236Sken * Incorporating additions for MPI v2.5. 194265236Sken * 11-27-12 02.00.23 Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER. 195265236Sken * Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID. 196265236Sken * 12-20-12 02.00.24 Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as 197265236Sken * obsolete for MPI v2.5 and later. 198265236Sken * Added some defines for 12G SAS speeds. 199265236Sken * 04-09-13 02.00.25 Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK. 200265236Sken * Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to 201265236Sken * match the specification. 202265236Sken * 08-19-13 02.00.26 Added reserved words to MPI2_CONFIG_PAGE_IO_UNIT_7 for 203265236Sken * future use. 204265236Sken * 12-05-13 02.00.27 Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for 205265236Sken * MPI2_CONFIG_PAGE_MAN_7. 206265236Sken * Added EnclosureLevel and ConnectorName fields to 207265236Sken * MPI2_CONFIG_PAGE_SAS_DEV_0. 208265236Sken * Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for 209265236Sken * MPI2_CONFIG_PAGE_SAS_DEV_0. 210265236Sken * Added EnclosureLevel field to 211265236Sken * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 212265236Sken * Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for 213265236Sken * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 214299263Sslm * 01-08-14 02.00.28 Added more defines for the BiosOptions field of 215299263Sslm * MPI2_CONFIG_PAGE_BIOS_1. 216299263Sslm * 06-13-14 02.00.29 Added SSUTimeout field to MPI2_CONFIG_PAGE_BIOS_1, and 217299263Sslm * more defines for the BiosOptions field. 218299263Sslm * 11-18-14 02.00.30 Updated copyright information. 219299263Sslm * Added MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG. 220299263Sslm * Added AdapterOrderAux fields to BIOS Page 3. 221299263Sslm * 03-16-15 02.00.31 Updated for MPI v2.6. 222299263Sslm * Added BoardPowerRequirement, PCISlotPowerAllocation, and 223299263Sslm * Flags field to IO Unit Page 7. 224299263Sslm * Added IO Unit Page 11. 225299263Sslm * Added new SAS Phy Event codes 226319435Sslm * Added PCIe configuration pages. 227319435Sslm * 03-19-15 02.00.32 Fixed PCIe Link Config page structure names to be 228319435Sslm * unique in first 32 characters. 229299263Sslm * 05-25-15 02.00.33 Added more defines for the BiosOptions field of 230299263Sslm * MPI2_CONFIG_PAGE_BIOS_1. 231319435Sslm * 08-25-15 02.00.34 Added PCIe Device Page 2 SGL format capability. 232299263Sslm * 12-18-15 02.00.35 Added SATADeviceWaitTime to SAS IO Unit Page 4. 233319435Sslm * 01-21-16 02.00.36 Added/modified MPI2_MFGPAGE_DEVID_SAS defines. 234319435Sslm * Added Link field to PCIe Link Pages 235319435Sslm * Added EnclosureLevel and ConnectorName to PCIe 236319435Sslm * Device Page 0. 237319435Sslm * Added define for PCIE IoUnit page 1 max rate shift. 238319435Sslm * Added comment for reserved ExtPageTypes. 239319435Sslm * Added SAS 4 22.5 gbs speed support. 240319435Sslm * Added PCIe 4 16.0 GT/sec speec support. 241319435Sslm * Removed AHCI support. 242319435Sslm * Removed SOP support. 243319435Sslm * Added NegotiatedLinkRate and NegotiatedPortWidth to 244319435Sslm * PCIe device page 0. 245319435Sslm * 04-10-16 02.00.37 Fixed MPI2_MFGPAGE_DEVID_SAS3616/3708 defines 246319435Sslm * 07-01-16 02.00.38 Added Manufacturing page 7 Connector types. 247319435Sslm * Changed declaration of ConnectorName in PCIe DevicePage0 248319435Sslm * to match SAS DevicePage 0. 249319435Sslm * Added SATADeviceWaitTime to IO Unit Page 11. 250319435Sslm * Added MPI26_MFGPAGE_DEVID_SAS4008 251319435Sslm * Added x16 PCIe width to IO Unit Page 7 252319435Sslm * Added LINKFLAGS to control SRIS in PCIe IO Unit page 1 253319435Sslm * phy data. 254319435Sslm * Added InitStatus to PCIe IO Unit Page 1 header. 255319435Sslm * 09-01-16 02.00.39 Added MPI26_CONFIG_PAGE_ENCLOSURE_0 and related defines. 256319435Sslm * Added MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE and 257319435Sslm * MPI26_ENCLOS_PGAD_FORM_HANDLE page address formats. 258331903Smav * 02-02-17 02.00.40 Added MPI2_MANPAGE7_SLOT_UNKNOWN. 259331903Smav * Added ChassisSlot field to SAS Enclosure Page 0. 260331903Smav * Added ChassisSlot Valid bit (bit 5) to the Flags field 261331903Smav * in SAS Enclosure Page 0. 262265236Sken * -------------------------------------------------------------------------- 263265236Sken */ 264265236Sken 265265236Sken#ifndef MPI2_CNFG_H 266265236Sken#define MPI2_CNFG_H 267265236Sken 268265236Sken/***************************************************************************** 269265236Sken* Configuration Page Header and defines 270265236Sken*****************************************************************************/ 271265236Sken 272265236Sken/* Config Page Header */ 273265236Skentypedef struct _MPI2_CONFIG_PAGE_HEADER 274265236Sken{ 275265236Sken U8 PageVersion; /* 0x00 */ 276265236Sken U8 PageLength; /* 0x01 */ 277265236Sken U8 PageNumber; /* 0x02 */ 278265236Sken U8 PageType; /* 0x03 */ 279265236Sken} MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER, 280265236Sken Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t; 281265236Sken 282265236Skentypedef union _MPI2_CONFIG_PAGE_HEADER_UNION 283265236Sken{ 284265236Sken MPI2_CONFIG_PAGE_HEADER Struct; 285265236Sken U8 Bytes[4]; 286265236Sken U16 Word16[2]; 287265236Sken U32 Word32; 288265236Sken} MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION, 289265236Sken Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion; 290265236Sken 291265236Sken/* Extended Config Page Header */ 292265236Skentypedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER 293265236Sken{ 294265236Sken U8 PageVersion; /* 0x00 */ 295265236Sken U8 Reserved1; /* 0x01 */ 296265236Sken U8 PageNumber; /* 0x02 */ 297265236Sken U8 PageType; /* 0x03 */ 298265236Sken U16 ExtPageLength; /* 0x04 */ 299265236Sken U8 ExtPageType; /* 0x06 */ 300265236Sken U8 Reserved2; /* 0x07 */ 301265236Sken} MPI2_CONFIG_EXTENDED_PAGE_HEADER, 302265236Sken MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER, 303265236Sken Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t; 304265236Sken 305265236Skentypedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION 306265236Sken{ 307265236Sken MPI2_CONFIG_PAGE_HEADER Struct; 308265236Sken MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext; 309265236Sken U8 Bytes[8]; 310265236Sken U16 Word16[4]; 311265236Sken U32 Word32[2]; 312265236Sken} MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 313265236Sken Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion; 314265236Sken 315265236Sken 316265236Sken/* PageType field values */ 317265236Sken#define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 318265236Sken#define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 319265236Sken#define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 320265236Sken#define MPI2_CONFIG_PAGEATTR_MASK (0xF0) 321265236Sken 322265236Sken#define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00) 323265236Sken#define MPI2_CONFIG_PAGETYPE_IOC (0x01) 324265236Sken#define MPI2_CONFIG_PAGETYPE_BIOS (0x02) 325265236Sken#define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 326265236Sken#define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09) 327265236Sken#define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 328265236Sken#define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F) 329265236Sken#define MPI2_CONFIG_PAGETYPE_MASK (0x0F) 330265236Sken 331265236Sken#define MPI2_CONFIG_TYPENUM_MASK (0x0FFF) 332265236Sken 333265236Sken 334265236Sken/* ExtPageType field values */ 335265236Sken#define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 336265236Sken#define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 337265236Sken#define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 338265236Sken#define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 339265236Sken#define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14) 340265236Sken#define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 341265236Sken#define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 342265236Sken#define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 343265236Sken#define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 344265236Sken#define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19) 345265236Sken#define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A) 346319435Sslm#define MPI2_CONFIG_EXTPAGETYPE_PCIE_IO_UNIT (0x1B) /* MPI v2.6 and later */ 347319435Sslm#define MPI2_CONFIG_EXTPAGETYPE_PCIE_SWITCH (0x1C) /* MPI v2.6 and later */ 348319435Sslm#define MPI2_CONFIG_EXTPAGETYPE_PCIE_DEVICE (0x1D) /* MPI v2.6 and later */ 349319435Sslm#define MPI2_CONFIG_EXTPAGETYPE_PCIE_LINK (0x1E) /* MPI v2.6 and later */ 350319435Sslm/* Product specific reserved values 0xE0 - 0xEF */ 351319435Sslm/* Vendor specific reserved values 0xF0 - 0xFF */ 352265236Sken 353265236Sken 354265236Sken/***************************************************************************** 355265236Sken* PageAddress defines 356265236Sken*****************************************************************************/ 357265236Sken 358265236Sken/* RAID Volume PageAddress format */ 359265236Sken#define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000) 360265236Sken#define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 361265236Sken#define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000) 362265236Sken 363265236Sken#define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF) 364265236Sken 365265236Sken 366265236Sken/* RAID Physical Disk PageAddress format */ 367265236Sken#define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000) 368265236Sken#define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000) 369265236Sken#define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000) 370265236Sken#define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000) 371265236Sken 372265236Sken#define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 373265236Sken#define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF) 374265236Sken 375265236Sken 376265236Sken/* SAS Expander PageAddress format */ 377265236Sken#define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 378265236Sken#define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 379265236Sken#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000) 380265236Sken#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000) 381265236Sken 382265236Sken#define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) 383265236Sken#define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) 384265236Sken#define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 385265236Sken 386265236Sken 387265236Sken/* SAS Device PageAddress format */ 388265236Sken#define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 389265236Sken#define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 390265236Sken#define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000) 391265236Sken 392265236Sken#define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 393265236Sken 394265236Sken 395265236Sken/* SAS PHY PageAddress format */ 396265236Sken#define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 397265236Sken#define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 398265236Sken#define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000) 399265236Sken 400265236Sken#define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 401265236Sken#define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 402265236Sken 403265236Sken 404265236Sken/* SAS Port PageAddress format */ 405265236Sken#define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000) 406265236Sken#define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 407265236Sken#define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 408265236Sken 409265236Sken#define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF) 410265236Sken 411265236Sken 412265236Sken/* SAS Enclosure PageAddress format */ 413265236Sken#define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 414265236Sken#define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 415265236Sken#define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 416265236Sken 417265236Sken#define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 418265236Sken 419319435Sslm/* Enclosure PageAddress format */ 420319435Sslm#define MPI26_ENCLOS_PGAD_FORM_MASK (0xF0000000) 421319435Sslm#define MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 422319435Sslm#define MPI26_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 423265236Sken 424319435Sslm#define MPI26_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 425319435Sslm 426265236Sken/* RAID Configuration PageAddress format */ 427265236Sken#define MPI2_RAID_PGAD_FORM_MASK (0xF0000000) 428265236Sken#define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000) 429265236Sken#define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000) 430265236Sken#define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000) 431265236Sken 432265236Sken#define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF) 433265236Sken 434265236Sken 435265236Sken/* Driver Persistent Mapping PageAddress format */ 436265236Sken#define MPI2_DPM_PGAD_FORM_MASK (0xF0000000) 437265236Sken#define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000) 438265236Sken 439265236Sken#define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000) 440265236Sken#define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16) 441265236Sken#define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF) 442265236Sken 443265236Sken 444265236Sken/* Ethernet PageAddress format */ 445265236Sken#define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000) 446265236Sken#define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000) 447265236Sken 448265236Sken#define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF) 449265236Sken 450265236Sken 451319435Sslm/* PCIe Switch PageAddress format */ 452319435Sslm#define MPI26_PCIE_SWITCH_PGAD_FORM_MASK (0xF0000000) 453319435Sslm#define MPI26_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 454319435Sslm#define MPI26_PCIE_SWITCH_PGAD_FORM_HNDL_PORTNUM (0x10000000) 455319435Sslm#define MPI26_PCIE_SWITCH_EXPAND_PGAD_FORM_HNDL (0x20000000) 456319435Sslm 457319435Sslm#define MPI26_PCIE_SWITCH_PGAD_HANDLE_MASK (0x0000FFFF) 458319435Sslm#define MPI26_PCIE_SWITCH_PGAD_PORTNUM_MASK (0x00FF0000) 459319435Sslm#define MPI26_PCIE_SWITCH_PGAD_PORTNUM_SHIFT (16) 460319435Sslm 461319435Sslm 462319435Sslm/* PCIe Device PageAddress format */ 463319435Sslm#define MPI26_PCIE_DEVICE_PGAD_FORM_MASK (0xF0000000) 464319435Sslm#define MPI26_PCIE_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 465319435Sslm#define MPI26_PCIE_DEVICE_PGAD_FORM_HANDLE (0x20000000) 466319435Sslm 467319435Sslm#define MPI26_PCIE_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 468319435Sslm 469319435Sslm/* PCIe Link PageAddress format */ 470319435Sslm#define MPI26_PCIE_LINK_PGAD_FORM_MASK (0xF0000000) 471319435Sslm#define MPI26_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK (0x00000000) 472319435Sslm#define MPI26_PCIE_LINK_PGAD_FORM_LINK_NUM (0x10000000) 473319435Sslm 474319435Sslm#define MPI26_PCIE_DEVICE_PGAD_LINKNUM_MASK (0x000000FF) 475319435Sslm 476319435Sslm 477319435Sslm 478265236Sken/**************************************************************************** 479265236Sken* Configuration messages 480265236Sken****************************************************************************/ 481265236Sken 482265236Sken/* Configuration Request Message */ 483265236Skentypedef struct _MPI2_CONFIG_REQUEST 484265236Sken{ 485265236Sken U8 Action; /* 0x00 */ 486265236Sken U8 SGLFlags; /* 0x01 */ 487265236Sken U8 ChainOffset; /* 0x02 */ 488265236Sken U8 Function; /* 0x03 */ 489265236Sken U16 ExtPageLength; /* 0x04 */ 490265236Sken U8 ExtPageType; /* 0x06 */ 491265236Sken U8 MsgFlags; /* 0x07 */ 492265236Sken U8 VP_ID; /* 0x08 */ 493265236Sken U8 VF_ID; /* 0x09 */ 494265236Sken U16 Reserved1; /* 0x0A */ 495265236Sken U8 Reserved2; /* 0x0C */ 496265236Sken U8 ProxyVF_ID; /* 0x0D */ 497265236Sken U16 Reserved4; /* 0x0E */ 498265236Sken U32 Reserved3; /* 0x10 */ 499265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 500265236Sken U32 PageAddress; /* 0x18 */ 501265236Sken MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */ 502265236Sken} MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST, 503265236Sken Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t; 504265236Sken 505265236Sken/* values for the Action field */ 506265236Sken#define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00) 507265236Sken#define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 508265236Sken#define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 509265236Sken#define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03) 510265236Sken#define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 511265236Sken#define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 512265236Sken#define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 513265236Sken#define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07) 514265236Sken 515265236Sken/* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */ 516265236Sken 517265236Sken 518265236Sken/* Config Reply Message */ 519265236Skentypedef struct _MPI2_CONFIG_REPLY 520265236Sken{ 521265236Sken U8 Action; /* 0x00 */ 522265236Sken U8 SGLFlags; /* 0x01 */ 523265236Sken U8 MsgLength; /* 0x02 */ 524265236Sken U8 Function; /* 0x03 */ 525265236Sken U16 ExtPageLength; /* 0x04 */ 526265236Sken U8 ExtPageType; /* 0x06 */ 527265236Sken U8 MsgFlags; /* 0x07 */ 528265236Sken U8 VP_ID; /* 0x08 */ 529265236Sken U8 VF_ID; /* 0x09 */ 530265236Sken U16 Reserved1; /* 0x0A */ 531265236Sken U16 Reserved2; /* 0x0C */ 532265236Sken U16 IOCStatus; /* 0x0E */ 533265236Sken U32 IOCLogInfo; /* 0x10 */ 534265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 535265236Sken} MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY, 536265236Sken Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t; 537265236Sken 538265236Sken 539265236Sken 540265236Sken/***************************************************************************** 541265236Sken* 542265236Sken* C o n f i g u r a t i o n P a g e s 543265236Sken* 544265236Sken*****************************************************************************/ 545265236Sken 546265236Sken/**************************************************************************** 547265236Sken* Manufacturing Config pages 548265236Sken****************************************************************************/ 549265236Sken 550265236Sken#define MPI2_MFGPAGE_VENDORID_LSI (0x1000) 551265236Sken 552265236Sken/* MPI v2.0 SAS products */ 553265236Sken#define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070) 554265236Sken#define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072) 555265236Sken#define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074) 556265236Sken#define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076) 557265236Sken#define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077) 558265236Sken#define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064) 559265236Sken#define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065) 560265236Sken 561265236Sken#define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E) 562265236Sken 563265236Sken#define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080) 564265236Sken#define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081) 565265236Sken#define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082) 566265236Sken#define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083) 567265236Sken#define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084) 568265236Sken#define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085) 569265236Sken#define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086) 570265236Sken#define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087) 571265236Sken#define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E) 572265236Sken 573265236Sken/* MPI v2.5 SAS products */ 574265236Sken#define MPI25_MFGPAGE_DEVID_SAS3004 (0x0096) 575265236Sken#define MPI25_MFGPAGE_DEVID_SAS3008 (0x0097) 576265236Sken#define MPI25_MFGPAGE_DEVID_SAS3108_1 (0x0090) 577265236Sken#define MPI25_MFGPAGE_DEVID_SAS3108_2 (0x0091) 578265236Sken#define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094) 579265236Sken#define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095) 580265236Sken 581299263Sslm/* MPI v2.6 SAS Products */ 582299263Sslm#define MPI26_MFGPAGE_DEVID_SAS3216 (0x00C9) 583299263Sslm#define MPI26_MFGPAGE_DEVID_SAS3224 (0x00C4) 584299263Sslm#define MPI26_MFGPAGE_DEVID_SAS3316_1 (0x00C5) 585299263Sslm#define MPI26_MFGPAGE_DEVID_SAS3316_2 (0x00C6) 586299263Sslm#define MPI26_MFGPAGE_DEVID_SAS3316_3 (0x00C7) 587299263Sslm#define MPI26_MFGPAGE_DEVID_SAS3316_4 (0x00C8) 588299263Sslm#define MPI26_MFGPAGE_DEVID_SAS3324_1 (0x00C0) 589299263Sslm#define MPI26_MFGPAGE_DEVID_SAS3324_2 (0x00C1) 590299263Sslm#define MPI26_MFGPAGE_DEVID_SAS3324_3 (0x00C2) 591299263Sslm#define MPI26_MFGPAGE_DEVID_SAS3324_4 (0x00C3) 592265236Sken 593319435Sslm#define MPI26_MFGPAGE_DEVID_SAS3516 (0x00AA) 594319435Sslm#define MPI26_MFGPAGE_DEVID_SAS3516_1 (0x00AB) 595319435Sslm#define MPI26_MFGPAGE_DEVID_SAS3416 (0x00AC) 596319435Sslm#define MPI26_MFGPAGE_DEVID_SAS3508 (0x00AD) 597319435Sslm#define MPI26_MFGPAGE_DEVID_SAS3508_1 (0x00AE) 598319435Sslm#define MPI26_MFGPAGE_DEVID_SAS3408 (0x00AF) 599319435Sslm 600319435Sslm#define MPI26_MFGPAGE_DEVID_SAS3716 (0x00D0) 601319435Sslm#define MPI26_MFGPAGE_DEVID_SAS3616 (0x00D1) 602319435Sslm#define MPI26_MFGPAGE_DEVID_SAS3708 (0x00D2) 603319435Sslm 604319435Sslm#define MPI26_MFGPAGE_DEVID_SAS4008 (0x00A1) 605319435Sslm 606319435Sslm 607265236Sken/* Manufacturing Page 0 */ 608265236Sken 609265236Skentypedef struct _MPI2_CONFIG_PAGE_MAN_0 610265236Sken{ 611265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 612265236Sken U8 ChipName[16]; /* 0x04 */ 613265236Sken U8 ChipRevision[8]; /* 0x14 */ 614265236Sken U8 BoardName[16]; /* 0x1C */ 615265236Sken U8 BoardAssembly[16]; /* 0x2C */ 616265236Sken U8 BoardTracerNumber[16]; /* 0x3C */ 617265236Sken} MPI2_CONFIG_PAGE_MAN_0, 618265236Sken MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0, 619265236Sken Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t; 620265236Sken 621265236Sken#define MPI2_MANUFACTURING0_PAGEVERSION (0x00) 622265236Sken 623265236Sken 624265236Sken/* Manufacturing Page 1 */ 625265236Sken 626265236Skentypedef struct _MPI2_CONFIG_PAGE_MAN_1 627265236Sken{ 628265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 629265236Sken U8 VPD[256]; /* 0x04 */ 630265236Sken} MPI2_CONFIG_PAGE_MAN_1, 631265236Sken MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1, 632265236Sken Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t; 633265236Sken 634265236Sken#define MPI2_MANUFACTURING1_PAGEVERSION (0x00) 635265236Sken 636265236Sken 637265236Skentypedef struct _MPI2_CHIP_REVISION_ID 638265236Sken{ 639265236Sken U16 DeviceID; /* 0x00 */ 640265236Sken U8 PCIRevisionID; /* 0x02 */ 641265236Sken U8 Reserved; /* 0x03 */ 642265236Sken} MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID, 643265236Sken Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t; 644265236Sken 645265236Sken 646265236Sken/* Manufacturing Page 2 */ 647265236Sken 648265236Sken/* 649265236Sken * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 650265236Sken * one and check Header.PageLength at runtime. 651265236Sken */ 652265236Sken#ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS 653265236Sken#define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 654265236Sken#endif 655265236Sken 656265236Skentypedef struct _MPI2_CONFIG_PAGE_MAN_2 657265236Sken{ 658265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 659265236Sken MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 660265236Sken U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */ 661265236Sken} MPI2_CONFIG_PAGE_MAN_2, 662265236Sken MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2, 663265236Sken Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t; 664265236Sken 665265236Sken#define MPI2_MANUFACTURING2_PAGEVERSION (0x00) 666265236Sken 667265236Sken 668265236Sken/* Manufacturing Page 3 */ 669265236Sken 670265236Sken/* 671265236Sken * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 672265236Sken * one and check Header.PageLength at runtime. 673265236Sken */ 674265236Sken#ifndef MPI2_MAN_PAGE_3_INFO_WORDS 675265236Sken#define MPI2_MAN_PAGE_3_INFO_WORDS (1) 676265236Sken#endif 677265236Sken 678265236Skentypedef struct _MPI2_CONFIG_PAGE_MAN_3 679265236Sken{ 680265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 681265236Sken MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 682265236Sken U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */ 683265236Sken} MPI2_CONFIG_PAGE_MAN_3, 684265236Sken MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3, 685265236Sken Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t; 686265236Sken 687265236Sken#define MPI2_MANUFACTURING3_PAGEVERSION (0x00) 688265236Sken 689265236Sken 690265236Sken/* Manufacturing Page 4 */ 691265236Sken 692265236Skentypedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS 693265236Sken{ 694265236Sken U8 PowerSaveFlags; /* 0x00 */ 695265236Sken U8 InternalOperationsSleepTime; /* 0x01 */ 696265236Sken U8 InternalOperationsRunTime; /* 0x02 */ 697265236Sken U8 HostIdleTime; /* 0x03 */ 698265236Sken} MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 699265236Sken MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 700265236Sken Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t; 701265236Sken 702265236Sken/* defines for the PowerSaveFlags field */ 703265236Sken#define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03) 704265236Sken#define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00) 705265236Sken#define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01) 706265236Sken#define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02) 707265236Sken 708265236Skentypedef struct _MPI2_CONFIG_PAGE_MAN_4 709265236Sken{ 710265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 711265236Sken U32 Reserved1; /* 0x04 */ 712265236Sken U32 Flags; /* 0x08 */ 713265236Sken U8 InquirySize; /* 0x0C */ 714265236Sken U8 Reserved2; /* 0x0D */ 715265236Sken U16 Reserved3; /* 0x0E */ 716265236Sken U8 InquiryData[56]; /* 0x10 */ 717265236Sken U32 RAID0VolumeSettings; /* 0x48 */ 718265236Sken U32 RAID1EVolumeSettings; /* 0x4C */ 719265236Sken U32 RAID1VolumeSettings; /* 0x50 */ 720265236Sken U32 RAID10VolumeSettings; /* 0x54 */ 721265236Sken U32 Reserved4; /* 0x58 */ 722265236Sken U32 Reserved5; /* 0x5C */ 723265236Sken MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */ 724265236Sken U8 MaxOCEDisks; /* 0x64 */ 725265236Sken U8 ResyncRate; /* 0x65 */ 726265236Sken U16 DataScrubDuration; /* 0x66 */ 727265236Sken U8 MaxHotSpares; /* 0x68 */ 728265236Sken U8 MaxPhysDisksPerVol; /* 0x69 */ 729265236Sken U8 MaxPhysDisks; /* 0x6A */ 730265236Sken U8 MaxVolumes; /* 0x6B */ 731265236Sken} MPI2_CONFIG_PAGE_MAN_4, 732265236Sken MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4, 733265236Sken Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t; 734265236Sken 735265236Sken#define MPI2_MANUFACTURING4_PAGEVERSION (0x0A) 736265236Sken 737265236Sken/* Manufacturing Page 4 Flags field */ 738265236Sken#define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000) 739265236Sken#define MPI2_MANPAGE4_METADATA_512MB (0x00000000) 740265236Sken 741265236Sken#define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000) 742265236Sken#define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000) 743265236Sken#define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000) 744265236Sken 745265236Sken#define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00) 746265236Sken#define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000) 747265236Sken#define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400) 748265236Sken#define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800) 749265236Sken#define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00) 750265236Sken 751265236Sken#define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300) 752265236Sken#define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000) 753265236Sken#define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100) 754265236Sken#define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200) 755265236Sken 756265236Sken#define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080) 757265236Sken#define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040) 758265236Sken#define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020) 759265236Sken#define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010) 760265236Sken#define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008) 761265236Sken#define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004) 762265236Sken#define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002) 763265236Sken#define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001) 764265236Sken 765265236Sken 766265236Sken/* Manufacturing Page 5 */ 767265236Sken 768265236Sken/* 769265236Sken * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 770265236Sken * one and check the value returned for NumPhys at runtime. 771265236Sken */ 772265236Sken#ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES 773265236Sken#define MPI2_MAN_PAGE_5_PHY_ENTRIES (1) 774265236Sken#endif 775265236Sken 776265236Skentypedef struct _MPI2_MANUFACTURING5_ENTRY 777265236Sken{ 778265236Sken U64 WWID; /* 0x00 */ 779265236Sken U64 DeviceName; /* 0x08 */ 780265236Sken} MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY, 781265236Sken Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t; 782265236Sken 783265236Skentypedef struct _MPI2_CONFIG_PAGE_MAN_5 784265236Sken{ 785265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 786265236Sken U8 NumPhys; /* 0x04 */ 787265236Sken U8 Reserved1; /* 0x05 */ 788265236Sken U16 Reserved2; /* 0x06 */ 789265236Sken U32 Reserved3; /* 0x08 */ 790265236Sken U32 Reserved4; /* 0x0C */ 791265236Sken MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */ 792265236Sken} MPI2_CONFIG_PAGE_MAN_5, 793265236Sken MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5, 794265236Sken Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t; 795265236Sken 796265236Sken#define MPI2_MANUFACTURING5_PAGEVERSION (0x03) 797265236Sken 798265236Sken 799265236Sken/* Manufacturing Page 6 */ 800265236Sken 801265236Skentypedef struct _MPI2_CONFIG_PAGE_MAN_6 802265236Sken{ 803265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 804265236Sken U32 ProductSpecificInfo;/* 0x04 */ 805265236Sken} MPI2_CONFIG_PAGE_MAN_6, 806265236Sken MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6, 807265236Sken Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t; 808265236Sken 809265236Sken#define MPI2_MANUFACTURING6_PAGEVERSION (0x00) 810265236Sken 811265236Sken 812265236Sken/* Manufacturing Page 7 */ 813265236Sken 814265236Skentypedef struct _MPI2_MANPAGE7_CONNECTOR_INFO 815265236Sken{ 816265236Sken U32 Pinout; /* 0x00 */ 817265236Sken U8 Connector[16]; /* 0x04 */ 818265236Sken U8 Location; /* 0x14 */ 819265236Sken U8 ReceptacleID; /* 0x15 */ 820265236Sken U16 Slot; /* 0x16 */ 821265236Sken U32 Reserved2; /* 0x18 */ 822265236Sken} MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO, 823265236Sken Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t; 824265236Sken 825265236Sken/* defines for the Pinout field */ 826265236Sken#define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00) 827265236Sken#define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8) 828265236Sken 829265236Sken#define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF) 830265236Sken#define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00) 831265236Sken#define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01) 832265236Sken#define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02) 833265236Sken#define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03) 834265236Sken#define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04) 835265236Sken#define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05) 836265236Sken#define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06) 837265236Sken#define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07) 838265236Sken#define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08) 839265236Sken#define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09) 840265236Sken#define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A) 841265236Sken#define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B) 842265236Sken#define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C) 843265236Sken#define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D) 844319435Sslm#define MPI2_MANPAGE7_PINOUT_SFF_8088_A (0x0E) 845319435Sslm#define MPI2_MANPAGE7_PINOUT_SFF_8643_16i (0x0F) 846319435Sslm#define MPI2_MANPAGE7_PINOUT_SFF_8654_4i (0x10) 847319435Sslm#define MPI2_MANPAGE7_PINOUT_SFF_8654_8i (0x11) 848319435Sslm#define MPI2_MANPAGE7_PINOUT_SFF_8611_4i (0x12) 849319435Sslm#define MPI2_MANPAGE7_PINOUT_SFF_8611_8i (0x13) 850265236Sken 851265236Sken/* defines for the Location field */ 852265236Sken#define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01) 853265236Sken#define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02) 854265236Sken#define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04) 855265236Sken#define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08) 856265236Sken#define MPI2_MANPAGE7_LOCATION_AUTO (0x10) 857265236Sken#define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 858265236Sken#define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 859265236Sken 860331903Smav/* defines for the Slot field */ 861331903Smav#define MPI2_MANPAGE7_SLOT_UNKNOWN (0xFFFF) 862331903Smav 863265236Sken/* 864265236Sken * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 865265236Sken * one and check the value returned for NumPhys at runtime. 866265236Sken */ 867265236Sken#ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX 868265236Sken#define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1) 869265236Sken#endif 870265236Sken 871265236Skentypedef struct _MPI2_CONFIG_PAGE_MAN_7 872265236Sken{ 873265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 874265236Sken U32 Reserved1; /* 0x04 */ 875265236Sken U32 Reserved2; /* 0x08 */ 876265236Sken U32 Flags; /* 0x0C */ 877265236Sken U8 EnclosureName[16]; /* 0x10 */ 878265236Sken U8 NumPhys; /* 0x20 */ 879265236Sken U8 Reserved3; /* 0x21 */ 880265236Sken U16 Reserved4; /* 0x22 */ 881265236Sken MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */ 882265236Sken} MPI2_CONFIG_PAGE_MAN_7, 883265236Sken MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7, 884265236Sken Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t; 885265236Sken 886265236Sken#define MPI2_MANUFACTURING7_PAGEVERSION (0x01) 887265236Sken 888265236Sken/* defines for the Flags field */ 889265236Sken#define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL (0x00000008) 890265236Sken#define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER (0x00000002) 891265236Sken#define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 892265236Sken 893265236Sken 894265236Sken/* 895265236Sken * Generic structure to use for product-specific manufacturing pages 896265236Sken * (currently Manufacturing Page 8 through Manufacturing Page 31). 897265236Sken */ 898265236Sken 899265236Skentypedef struct _MPI2_CONFIG_PAGE_MAN_PS 900265236Sken{ 901265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 902265236Sken U32 ProductSpecificInfo;/* 0x04 */ 903265236Sken} MPI2_CONFIG_PAGE_MAN_PS, 904265236Sken MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS, 905265236Sken Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t; 906265236Sken 907265236Sken#define MPI2_MANUFACTURING8_PAGEVERSION (0x00) 908265236Sken#define MPI2_MANUFACTURING9_PAGEVERSION (0x00) 909265236Sken#define MPI2_MANUFACTURING10_PAGEVERSION (0x00) 910265236Sken#define MPI2_MANUFACTURING11_PAGEVERSION (0x00) 911265236Sken#define MPI2_MANUFACTURING12_PAGEVERSION (0x00) 912265236Sken#define MPI2_MANUFACTURING13_PAGEVERSION (0x00) 913265236Sken#define MPI2_MANUFACTURING14_PAGEVERSION (0x00) 914265236Sken#define MPI2_MANUFACTURING15_PAGEVERSION (0x00) 915265236Sken#define MPI2_MANUFACTURING16_PAGEVERSION (0x00) 916265236Sken#define MPI2_MANUFACTURING17_PAGEVERSION (0x00) 917265236Sken#define MPI2_MANUFACTURING18_PAGEVERSION (0x00) 918265236Sken#define MPI2_MANUFACTURING19_PAGEVERSION (0x00) 919265236Sken#define MPI2_MANUFACTURING20_PAGEVERSION (0x00) 920265236Sken#define MPI2_MANUFACTURING21_PAGEVERSION (0x00) 921265236Sken#define MPI2_MANUFACTURING22_PAGEVERSION (0x00) 922265236Sken#define MPI2_MANUFACTURING23_PAGEVERSION (0x00) 923265236Sken#define MPI2_MANUFACTURING24_PAGEVERSION (0x00) 924265236Sken#define MPI2_MANUFACTURING25_PAGEVERSION (0x00) 925265236Sken#define MPI2_MANUFACTURING26_PAGEVERSION (0x00) 926265236Sken#define MPI2_MANUFACTURING27_PAGEVERSION (0x00) 927265236Sken#define MPI2_MANUFACTURING28_PAGEVERSION (0x00) 928265236Sken#define MPI2_MANUFACTURING29_PAGEVERSION (0x00) 929265236Sken#define MPI2_MANUFACTURING30_PAGEVERSION (0x00) 930265236Sken#define MPI2_MANUFACTURING31_PAGEVERSION (0x00) 931265236Sken 932265236Sken 933265236Sken/**************************************************************************** 934265236Sken* IO Unit Config Pages 935265236Sken****************************************************************************/ 936265236Sken 937265236Sken/* IO Unit Page 0 */ 938265236Sken 939265236Skentypedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 940265236Sken{ 941265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 942265236Sken U64 UniqueValue; /* 0x04 */ 943265236Sken MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */ 944265236Sken MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */ 945265236Sken} MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0, 946265236Sken Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t; 947265236Sken 948265236Sken#define MPI2_IOUNITPAGE0_PAGEVERSION (0x02) 949265236Sken 950265236Sken 951265236Sken/* IO Unit Page 1 */ 952265236Sken 953265236Skentypedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 954265236Sken{ 955265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 956265236Sken U32 Flags; /* 0x04 */ 957265236Sken} MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1, 958265236Sken Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t; 959265236Sken 960265236Sken#define MPI2_IOUNITPAGE1_PAGEVERSION (0x04) 961265236Sken 962265236Sken/* IO Unit Page 1 Flags defines */ 963265236Sken#define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK (0x00004000) 964265236Sken#define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000) 965265236Sken#define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000) 966265236Sken#define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800) 967265236Sken#define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600) 968265236Sken#define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9) 969265236Sken#define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000) 970265236Sken#define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200) 971265236Sken#define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400) 972265236Sken#define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 973265236Sken#define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040) 974265236Sken#define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020) 975265236Sken#define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 976265236Sken 977265236Sken 978265236Sken/* IO Unit Page 3 */ 979265236Sken 980265236Sken/* 981265236Sken * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 982265236Sken * one and check the value returned for GPIOCount at runtime. 983265236Sken */ 984265236Sken#ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX 985265236Sken#define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 986265236Sken#endif 987265236Sken 988265236Skentypedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 989265236Sken{ 990265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 991265236Sken U8 GPIOCount; /* 0x04 */ 992265236Sken U8 Reserved1; /* 0x05 */ 993265236Sken U16 Reserved2; /* 0x06 */ 994265236Sken U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */ 995265236Sken} MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3, 996265236Sken Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t; 997265236Sken 998265236Sken#define MPI2_IOUNITPAGE3_PAGEVERSION (0x01) 999265236Sken 1000265236Sken/* defines for IO Unit Page 3 GPIOVal field */ 1001265236Sken#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC) 1002265236Sken#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 1003265236Sken#define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000) 1004265236Sken#define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001) 1005265236Sken 1006265236Sken 1007265236Sken/* IO Unit Page 5 */ 1008265236Sken 1009265236Sken/* 1010265236Sken * Upper layer code (drivers, utilities, etc.) should leave this define set to 1011265236Sken * one and check the value returned for NumDmaEngines at runtime. 1012265236Sken */ 1013265236Sken#ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES 1014265236Sken#define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1) 1015265236Sken#endif 1016265236Sken 1017265236Skentypedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 1018265236Sken{ 1019265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1020265236Sken U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */ 1021265236Sken U64 RaidAcceleratorBufferSize; /* 0x0C */ 1022265236Sken U64 RaidAcceleratorControlBaseAddress; /* 0x14 */ 1023265236Sken U8 RAControlSize; /* 0x1C */ 1024265236Sken U8 NumDmaEngines; /* 0x1D */ 1025265236Sken U8 RAMinControlSize; /* 0x1E */ 1026265236Sken U8 RAMaxControlSize; /* 0x1F */ 1027265236Sken U32 Reserved1; /* 0x20 */ 1028265236Sken U32 Reserved2; /* 0x24 */ 1029265236Sken U32 Reserved3; /* 0x28 */ 1030265236Sken U32 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */ 1031265236Sken} MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5, 1032265236Sken Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t; 1033265236Sken 1034265236Sken#define MPI2_IOUNITPAGE5_PAGEVERSION (0x00) 1035265236Sken 1036265236Sken/* defines for IO Unit Page 5 DmaEngineCapabilities field */ 1037265236Sken#define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFFFF0000) 1038265236Sken#define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16) 1039265236Sken 1040265236Sken#define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008) 1041265236Sken#define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004) 1042265236Sken#define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002) 1043265236Sken#define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001) 1044265236Sken 1045265236Sken 1046265236Sken/* IO Unit Page 6 */ 1047265236Sken 1048265236Skentypedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 1049265236Sken{ 1050265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1051265236Sken U16 Flags; /* 0x04 */ 1052265236Sken U8 RAHostControlSize; /* 0x06 */ 1053265236Sken U8 Reserved0; /* 0x07 */ 1054265236Sken U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */ 1055265236Sken U32 Reserved1; /* 0x10 */ 1056265236Sken U32 Reserved2; /* 0x14 */ 1057265236Sken U32 Reserved3; /* 0x18 */ 1058265236Sken} MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6, 1059265236Sken Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t; 1060265236Sken 1061265236Sken#define MPI2_IOUNITPAGE6_PAGEVERSION (0x00) 1062265236Sken 1063265236Sken/* defines for IO Unit Page 6 Flags field */ 1064265236Sken#define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001) 1065265236Sken 1066265236Sken 1067265236Sken/* IO Unit Page 7 */ 1068265236Sken 1069265236Skentypedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 1070265236Sken{ 1071265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1072265236Sken U8 CurrentPowerMode; /* 0x04 */ /* reserved in MPI 2.0 */ 1073265236Sken U8 PreviousPowerMode; /* 0x05 */ /* reserved in MPI 2.0 */ 1074265236Sken U8 PCIeWidth; /* 0x06 */ 1075265236Sken U8 PCIeSpeed; /* 0x07 */ 1076265236Sken U32 ProcessorState; /* 0x08 */ 1077265236Sken U32 PowerManagementCapabilities; /* 0x0C */ 1078265236Sken U16 IOCTemperature; /* 0x10 */ 1079265236Sken U8 IOCTemperatureUnits; /* 0x12 */ 1080265236Sken U8 IOCSpeed; /* 0x13 */ 1081265236Sken U16 BoardTemperature; /* 0x14 */ 1082265236Sken U8 BoardTemperatureUnits; /* 0x16 */ 1083265236Sken U8 Reserved3; /* 0x17 */ 1084299263Sslm U32 BoardPowerRequirement; /* 0x18 */ /* reserved prior to MPI v2.6 */ 1085299263Sslm U32 PCISlotPowerAllocation; /* 0x1C */ /* reserved prior to MPI v2.6 */ 1086299263Sslm U8 Flags; /* 0x20 */ /* reserved prior to MPI v2.6 */ 1087299263Sslm U8 Reserved6; /* 0x21 */ 1088299263Sslm U16 Reserved7; /* 0x22 */ 1089299263Sslm U32 Reserved8; /* 0x24 */ 1090265236Sken} MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7, 1091265236Sken Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t; 1092265236Sken 1093299263Sslm#define MPI2_IOUNITPAGE7_PAGEVERSION (0x05) 1094265236Sken 1095265236Sken/* defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */ 1096265236Sken#define MPI25_IOUNITPAGE7_PM_INIT_MASK (0xC0) 1097265236Sken#define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE (0x00) 1098265236Sken#define MPI25_IOUNITPAGE7_PM_INIT_HOST (0x40) 1099265236Sken#define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT (0x80) 1100265236Sken#define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA (0xC0) 1101265236Sken 1102265236Sken#define MPI25_IOUNITPAGE7_PM_MODE_MASK (0x07) 1103265236Sken#define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE (0x00) 1104265236Sken#define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN (0x01) 1105265236Sken#define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER (0x04) 1106265236Sken#define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER (0x05) 1107265236Sken#define MPI25_IOUNITPAGE7_PM_MODE_STANDBY (0x06) 1108265236Sken 1109265236Sken 1110265236Sken/* defines for IO Unit Page 7 PCIeWidth field */ 1111265236Sken#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01) 1112265236Sken#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02) 1113265236Sken#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04) 1114265236Sken#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08) 1115319435Sslm#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X16 (0x10) 1116265236Sken 1117265236Sken/* defines for IO Unit Page 7 PCIeSpeed field */ 1118265236Sken#define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00) 1119265236Sken#define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01) 1120265236Sken#define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02) 1121319435Sslm#define MPI2_IOUNITPAGE7_PCIE_SPEED_16_0_GBPS (0x03) 1122265236Sken 1123265236Sken/* defines for IO Unit Page 7 ProcessorState field */ 1124265236Sken#define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F) 1125265236Sken#define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0) 1126265236Sken 1127265236Sken#define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00) 1128265236Sken#define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01) 1129265236Sken#define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02) 1130265236Sken 1131265236Sken/* defines for IO Unit Page 7 PowerManagementCapabilities field */ 1132265236Sken#define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE (0x00400000) 1133265236Sken#define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE (0x00200000) 1134265236Sken#define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE (0x00100000) 1135265236Sken#define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE (0x00040000) 1136265236Sken#define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE (0x00020000) 1137265236Sken#define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE (0x00010000) 1138265236Sken#define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE (0x00004000) 1139265236Sken#define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE (0x00002000) 1140265236Sken#define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE (0x00001000) 1141265236Sken#define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED (0x00000400) 1142265236Sken#define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED (0x00000200) 1143265236Sken#define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED (0x00000100) 1144265236Sken#define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED (0x00000040) 1145265236Sken#define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED (0x00000020) 1146265236Sken#define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED (0x00000010) 1147265236Sken#define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE (0x00000008) /* obsolete */ 1148265236Sken#define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE (0x00000004) /* obsolete */ 1149265236Sken#define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE (0x00000002) /* obsolete */ 1150265236Sken#define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE (0x00000001) /* obsolete */ 1151265236Sken 1152265236Sken/* obsolete names for the PowerManagementCapabilities bits (above) */ 1153265236Sken#define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400) 1154265236Sken#define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200) 1155265236Sken#define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100) 1156265236Sken#define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /* obsolete */ 1157265236Sken#define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /* obsolete */ 1158265236Sken 1159265236Sken 1160265236Sken/* defines for IO Unit Page 7 IOCTemperatureUnits field */ 1161265236Sken#define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00) 1162265236Sken#define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01) 1163265236Sken#define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02) 1164265236Sken 1165265236Sken/* defines for IO Unit Page 7 IOCSpeed field */ 1166265236Sken#define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01) 1167265236Sken#define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02) 1168265236Sken#define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04) 1169265236Sken#define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08) 1170265236Sken 1171265236Sken/* defines for IO Unit Page 7 BoardTemperatureUnits field */ 1172265236Sken#define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00) 1173265236Sken#define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01) 1174265236Sken#define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02) 1175265236Sken 1176299263Sslm/* defines for IO Unit Page 7 Flags field */ 1177299263Sslm#define MPI2_IOUNITPAGE7_FLAG_CABLE_POWER_EXC (0x01) 1178265236Sken 1179319435Sslm 1180265236Sken/* IO Unit Page 8 */ 1181265236Sken 1182265236Sken#define MPI2_IOUNIT8_NUM_THRESHOLDS (4) 1183265236Sken 1184265236Skentypedef struct _MPI2_IOUNIT8_SENSOR 1185265236Sken{ 1186265236Sken U16 Flags; /* 0x00 */ 1187265236Sken U16 Reserved1; /* 0x02 */ 1188265236Sken U16 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /* 0x04 */ 1189265236Sken U32 Reserved2; /* 0x0C */ 1190265236Sken U32 Reserved3; /* 0x10 */ 1191265236Sken U32 Reserved4; /* 0x14 */ 1192265236Sken} MPI2_IOUNIT8_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT8_SENSOR, 1193265236Sken Mpi2IOUnit8Sensor_t, MPI2_POINTER pMpi2IOUnit8Sensor_t; 1194265236Sken 1195265236Sken/* defines for IO Unit Page 8 Sensor Flags field */ 1196265236Sken#define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008) 1197265236Sken#define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004) 1198265236Sken#define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002) 1199265236Sken#define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001) 1200265236Sken 1201265236Sken/* 1202265236Sken * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1203265236Sken * one and check the value returned for NumSensors at runtime. 1204265236Sken */ 1205265236Sken#ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES 1206265236Sken#define MPI2_IOUNITPAGE8_SENSOR_ENTRIES (1) 1207265236Sken#endif 1208265236Sken 1209265236Skentypedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 1210265236Sken{ 1211265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1212265236Sken U32 Reserved1; /* 0x04 */ 1213265236Sken U32 Reserved2; /* 0x08 */ 1214265236Sken U8 NumSensors; /* 0x0C */ 1215265236Sken U8 PollingInterval; /* 0x0D */ 1216265236Sken U16 Reserved3; /* 0x0E */ 1217265236Sken MPI2_IOUNIT8_SENSOR Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/* 0x10 */ 1218265236Sken} MPI2_CONFIG_PAGE_IO_UNIT_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_8, 1219265236Sken Mpi2IOUnitPage8_t, MPI2_POINTER pMpi2IOUnitPage8_t; 1220265236Sken 1221265236Sken#define MPI2_IOUNITPAGE8_PAGEVERSION (0x00) 1222265236Sken 1223265236Sken 1224265236Sken/* IO Unit Page 9 */ 1225265236Sken 1226265236Skentypedef struct _MPI2_IOUNIT9_SENSOR 1227265236Sken{ 1228265236Sken U16 CurrentTemperature; /* 0x00 */ 1229265236Sken U16 Reserved1; /* 0x02 */ 1230265236Sken U8 Flags; /* 0x04 */ 1231265236Sken U8 Reserved2; /* 0x05 */ 1232265236Sken U16 Reserved3; /* 0x06 */ 1233265236Sken U32 Reserved4; /* 0x08 */ 1234265236Sken U32 Reserved5; /* 0x0C */ 1235265236Sken} MPI2_IOUNIT9_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT9_SENSOR, 1236265236Sken Mpi2IOUnit9Sensor_t, MPI2_POINTER pMpi2IOUnit9Sensor_t; 1237265236Sken 1238265236Sken/* defines for IO Unit Page 9 Sensor Flags field */ 1239265236Sken#define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01) 1240265236Sken 1241265236Sken/* 1242265236Sken * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1243265236Sken * one and check the value returned for NumSensors at runtime. 1244265236Sken */ 1245265236Sken#ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES 1246265236Sken#define MPI2_IOUNITPAGE9_SENSOR_ENTRIES (1) 1247265236Sken#endif 1248265236Sken 1249265236Skentypedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 1250265236Sken{ 1251265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1252265236Sken U32 Reserved1; /* 0x04 */ 1253265236Sken U32 Reserved2; /* 0x08 */ 1254265236Sken U8 NumSensors; /* 0x0C */ 1255265236Sken U8 Reserved4; /* 0x0D */ 1256265236Sken U16 Reserved3; /* 0x0E */ 1257265236Sken MPI2_IOUNIT9_SENSOR Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/* 0x10 */ 1258265236Sken} MPI2_CONFIG_PAGE_IO_UNIT_9, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_9, 1259265236Sken Mpi2IOUnitPage9_t, MPI2_POINTER pMpi2IOUnitPage9_t; 1260265236Sken 1261265236Sken#define MPI2_IOUNITPAGE9_PAGEVERSION (0x00) 1262265236Sken 1263265236Sken 1264265236Sken/* IO Unit Page 10 */ 1265265236Sken 1266265236Skentypedef struct _MPI2_IOUNIT10_FUNCTION 1267265236Sken{ 1268265236Sken U8 CreditPercent; /* 0x00 */ 1269265236Sken U8 Reserved1; /* 0x01 */ 1270265236Sken U16 Reserved2; /* 0x02 */ 1271265236Sken} MPI2_IOUNIT10_FUNCTION, MPI2_POINTER PTR_MPI2_IOUNIT10_FUNCTION, 1272265236Sken Mpi2IOUnit10Function_t, MPI2_POINTER pMpi2IOUnit10Function_t; 1273265236Sken 1274265236Sken/* 1275265236Sken * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1276265236Sken * one and check the value returned for NumFunctions at runtime. 1277265236Sken */ 1278265236Sken#ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES 1279265236Sken#define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES (1) 1280265236Sken#endif 1281265236Sken 1282265236Skentypedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 1283265236Sken{ 1284265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1285265236Sken U8 NumFunctions; /* 0x04 */ 1286265236Sken U8 Reserved1; /* 0x05 */ 1287265236Sken U16 Reserved2; /* 0x06 */ 1288265236Sken U32 Reserved3; /* 0x08 */ 1289265236Sken U32 Reserved4; /* 0x0C */ 1290265236Sken MPI2_IOUNIT10_FUNCTION Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES]; /* 0x10 */ 1291265236Sken} MPI2_CONFIG_PAGE_IO_UNIT_10, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_10, 1292265236Sken Mpi2IOUnitPage10_t, MPI2_POINTER pMpi2IOUnitPage10_t; 1293265236Sken 1294265236Sken#define MPI2_IOUNITPAGE10_PAGEVERSION (0x01) 1295265236Sken 1296265236Sken 1297299263Sslm/* IO Unit Page 11 (for MPI v2.6 and later) */ 1298265236Sken 1299299263Sslmtypedef struct _MPI26_IOUNIT11_SPINUP_GROUP 1300299263Sslm{ 1301299263Sslm U8 MaxTargetSpinup; /* 0x00 */ 1302299263Sslm U8 SpinupDelay; /* 0x01 */ 1303299263Sslm U8 SpinupFlags; /* 0x02 */ 1304299263Sslm U8 Reserved1; /* 0x03 */ 1305299263Sslm} MPI26_IOUNIT11_SPINUP_GROUP, MPI2_POINTER PTR_MPI26_IOUNIT11_SPINUP_GROUP, 1306299263Sslm Mpi26IOUnit11SpinupGroup_t, MPI2_POINTER pMpi26IOUnit11SpinupGroup_t; 1307299263Sslm 1308299263Sslm/* defines for IO Unit Page 11 SpinupFlags */ 1309299263Sslm#define MPI26_IOUNITPAGE11_SPINUP_DISABLE_FLAG (0x01) 1310299263Sslm 1311299263Sslm 1312299263Sslm/* 1313299263Sslm * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1314299263Sslm * four and check the value returned for NumPhys at runtime. 1315299263Sslm */ 1316299263Sslm#ifndef MPI26_IOUNITPAGE11_PHY_MAX 1317299263Sslm#define MPI26_IOUNITPAGE11_PHY_MAX (4) 1318299263Sslm#endif 1319299263Sslm 1320299263Sslmtypedef struct _MPI26_CONFIG_PAGE_IO_UNIT_11 1321299263Sslm{ 1322299263Sslm MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1323299263Sslm U32 Reserved1; /* 0x04 */ 1324299263Sslm MPI26_IOUNIT11_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ 1325299263Sslm U32 Reserved2; /* 0x18 */ 1326299263Sslm U32 Reserved3; /* 0x1C */ 1327299263Sslm U32 Reserved4; /* 0x20 */ 1328299263Sslm U8 BootDeviceWaitTime; /* 0x24 */ 1329319435Sslm U8 SATADeviceWaitTime; /* 0x25 */ 1330299263Sslm U16 Reserved6; /* 0x26 */ 1331299263Sslm U8 NumPhys; /* 0x28 */ 1332299263Sslm U8 PEInitialSpinupDelay; /* 0x29 */ 1333299263Sslm U8 PEReplyDelay; /* 0x2A */ 1334299263Sslm U8 Flags; /* 0x2B */ 1335299263Sslm U8 PHY[MPI26_IOUNITPAGE11_PHY_MAX];/* 0x2C */ 1336299263Sslm} MPI26_CONFIG_PAGE_IO_UNIT_11, 1337299263Sslm MPI2_POINTER PTR_MPI26_CONFIG_PAGE_IO_UNIT_11, 1338299263Sslm Mpi26IOUnitPage11_t, MPI2_POINTER pMpi26IOUnitPage11_t; 1339299263Sslm 1340299263Sslm#define MPI26_IOUNITPAGE11_PAGEVERSION (0x00) 1341299263Sslm 1342299263Sslm/* defines for Flags field */ 1343299263Sslm#define MPI26_IOUNITPAGE11_FLAGS_AUTO_PORTENABLE (0x01) 1344299263Sslm 1345299263Sslm/* defines for PHY field */ 1346299263Sslm#define MPI26_IOUNITPAGE11_PHY_SPINUP_GROUP_MASK (0x03) 1347299263Sslm 1348299263Sslm 1349299263Sslm 1350265236Sken/**************************************************************************** 1351265236Sken* IOC Config Pages 1352265236Sken****************************************************************************/ 1353265236Sken 1354265236Sken/* IOC Page 0 */ 1355265236Sken 1356265236Skentypedef struct _MPI2_CONFIG_PAGE_IOC_0 1357265236Sken{ 1358265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1359265236Sken U32 Reserved1; /* 0x04 */ 1360265236Sken U32 Reserved2; /* 0x08 */ 1361265236Sken U16 VendorID; /* 0x0C */ 1362265236Sken U16 DeviceID; /* 0x0E */ 1363265236Sken U8 RevisionID; /* 0x10 */ 1364265236Sken U8 Reserved3; /* 0x11 */ 1365265236Sken U16 Reserved4; /* 0x12 */ 1366265236Sken U32 ClassCode; /* 0x14 */ 1367265236Sken U16 SubsystemVendorID; /* 0x18 */ 1368265236Sken U16 SubsystemID; /* 0x1A */ 1369265236Sken} MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0, 1370265236Sken Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t; 1371265236Sken 1372265236Sken#define MPI2_IOCPAGE0_PAGEVERSION (0x02) 1373265236Sken 1374265236Sken 1375265236Sken/* IOC Page 1 */ 1376265236Sken 1377265236Skentypedef struct _MPI2_CONFIG_PAGE_IOC_1 1378265236Sken{ 1379265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1380265236Sken U32 Flags; /* 0x04 */ 1381265236Sken U32 CoalescingTimeout; /* 0x08 */ 1382265236Sken U8 CoalescingDepth; /* 0x0C */ 1383265236Sken U8 PCISlotNum; /* 0x0D */ 1384265236Sken U8 PCIBusNum; /* 0x0E */ 1385265236Sken U8 PCIDomainSegment; /* 0x0F */ 1386265236Sken U32 Reserved1; /* 0x10 */ 1387265236Sken U32 Reserved2; /* 0x14 */ 1388265236Sken} MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1, 1389265236Sken Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t; 1390265236Sken 1391265236Sken#define MPI2_IOCPAGE1_PAGEVERSION (0x05) 1392265236Sken 1393265236Sken/* defines for IOC Page 1 Flags field */ 1394265236Sken#define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001) 1395265236Sken 1396265236Sken#define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 1397265236Sken#define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF) 1398265236Sken#define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF) 1399265236Sken 1400265236Sken/* IOC Page 6 */ 1401265236Sken 1402265236Skentypedef struct _MPI2_CONFIG_PAGE_IOC_6 1403265236Sken{ 1404265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1405265236Sken U32 CapabilitiesFlags; /* 0x04 */ 1406265236Sken U8 MaxDrivesRAID0; /* 0x08 */ 1407265236Sken U8 MaxDrivesRAID1; /* 0x09 */ 1408265236Sken U8 MaxDrivesRAID1E; /* 0x0A */ 1409265236Sken U8 MaxDrivesRAID10; /* 0x0B */ 1410265236Sken U8 MinDrivesRAID0; /* 0x0C */ 1411265236Sken U8 MinDrivesRAID1; /* 0x0D */ 1412265236Sken U8 MinDrivesRAID1E; /* 0x0E */ 1413265236Sken U8 MinDrivesRAID10; /* 0x0F */ 1414265236Sken U32 Reserved1; /* 0x10 */ 1415265236Sken U8 MaxGlobalHotSpares; /* 0x14 */ 1416265236Sken U8 MaxPhysDisks; /* 0x15 */ 1417265236Sken U8 MaxVolumes; /* 0x16 */ 1418265236Sken U8 MaxConfigs; /* 0x17 */ 1419265236Sken U8 MaxOCEDisks; /* 0x18 */ 1420265236Sken U8 Reserved2; /* 0x19 */ 1421265236Sken U16 Reserved3; /* 0x1A */ 1422265236Sken U32 SupportedStripeSizeMapRAID0; /* 0x1C */ 1423265236Sken U32 SupportedStripeSizeMapRAID1E; /* 0x20 */ 1424265236Sken U32 SupportedStripeSizeMapRAID10; /* 0x24 */ 1425265236Sken U32 Reserved4; /* 0x28 */ 1426265236Sken U32 Reserved5; /* 0x2C */ 1427265236Sken U16 DefaultMetadataSize; /* 0x30 */ 1428265236Sken U16 Reserved6; /* 0x32 */ 1429265236Sken U16 MaxBadBlockTableEntries; /* 0x34 */ 1430265236Sken U16 Reserved7; /* 0x36 */ 1431265236Sken U32 IRNvsramVersion; /* 0x38 */ 1432265236Sken} MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6, 1433265236Sken Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t; 1434265236Sken 1435265236Sken#define MPI2_IOCPAGE6_PAGEVERSION (0x05) 1436265236Sken 1437265236Sken/* defines for IOC Page 6 CapabilitiesFlags */ 1438265236Sken#define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT (0x00000020) 1439265236Sken#define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010) 1440265236Sken#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008) 1441265236Sken#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004) 1442265236Sken#define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002) 1443265236Sken#define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 1444265236Sken 1445265236Sken 1446265236Sken/* IOC Page 7 */ 1447265236Sken 1448265236Sken#define MPI2_IOCPAGE7_EVENTMASK_WORDS (4) 1449265236Sken 1450265236Skentypedef struct _MPI2_CONFIG_PAGE_IOC_7 1451265236Sken{ 1452265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1453265236Sken U32 Reserved1; /* 0x04 */ 1454265236Sken U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */ 1455265236Sken U16 SASBroadcastPrimitiveMasks; /* 0x18 */ 1456265236Sken U16 SASNotifyPrimitiveMasks; /* 0x1A */ 1457265236Sken U32 Reserved3; /* 0x1C */ 1458265236Sken} MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7, 1459265236Sken Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t; 1460265236Sken 1461265236Sken#define MPI2_IOCPAGE7_PAGEVERSION (0x02) 1462265236Sken 1463265236Sken 1464265236Sken/* IOC Page 8 */ 1465265236Sken 1466265236Skentypedef struct _MPI2_CONFIG_PAGE_IOC_8 1467265236Sken{ 1468265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1469265236Sken U8 NumDevsPerEnclosure; /* 0x04 */ 1470265236Sken U8 Reserved1; /* 0x05 */ 1471265236Sken U16 Reserved2; /* 0x06 */ 1472265236Sken U16 MaxPersistentEntries; /* 0x08 */ 1473265236Sken U16 MaxNumPhysicalMappedIDs; /* 0x0A */ 1474265236Sken U16 Flags; /* 0x0C */ 1475265236Sken U16 Reserved3; /* 0x0E */ 1476265236Sken U16 IRVolumeMappingFlags; /* 0x10 */ 1477265236Sken U16 Reserved4; /* 0x12 */ 1478265236Sken U32 Reserved5; /* 0x14 */ 1479265236Sken} MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8, 1480265236Sken Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t; 1481265236Sken 1482265236Sken#define MPI2_IOCPAGE8_PAGEVERSION (0x00) 1483265236Sken 1484265236Sken/* defines for IOC Page 8 Flags field */ 1485265236Sken#define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020) 1486265236Sken#define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010) 1487265236Sken 1488265236Sken#define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E) 1489265236Sken#define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000) 1490265236Sken#define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002) 1491265236Sken 1492265236Sken#define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001) 1493265236Sken#define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000) 1494265236Sken 1495265236Sken/* defines for IOC Page 8 IRVolumeMappingFlags */ 1496265236Sken#define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003) 1497265236Sken#define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000) 1498265236Sken#define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001) 1499265236Sken 1500265236Sken 1501265236Sken/**************************************************************************** 1502265236Sken* BIOS Config Pages 1503265236Sken****************************************************************************/ 1504265236Sken 1505265236Sken/* BIOS Page 1 */ 1506265236Sken 1507265236Skentypedef struct _MPI2_CONFIG_PAGE_BIOS_1 1508265236Sken{ 1509265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1510265236Sken U32 BiosOptions; /* 0x04 */ 1511265236Sken U32 IOCSettings; /* 0x08 */ 1512299263Sslm U8 SSUTimeout; /* 0x0C */ 1513299263Sslm U8 Reserved1; /* 0x0D */ 1514299263Sslm U16 Reserved2; /* 0x0E */ 1515265236Sken U32 DeviceSettings; /* 0x10 */ 1516265236Sken U16 NumberOfDevices; /* 0x14 */ 1517265236Sken U16 UEFIVersion; /* 0x16 */ 1518265236Sken U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */ 1519265236Sken U16 IOTimeoutSequential; /* 0x1A */ 1520265236Sken U16 IOTimeoutOther; /* 0x1C */ 1521265236Sken U16 IOTimeoutBlockDevicesRM; /* 0x1E */ 1522265236Sken} MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1, 1523265236Sken Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t; 1524265236Sken 1525299263Sslm#define MPI2_BIOSPAGE1_PAGEVERSION (0x07) 1526265236Sken 1527265236Sken/* values for BIOS Page 1 BiosOptions field */ 1528299263Sslm#define MPI2_BIOSPAGE1_OPTIONS_BOOT_LIST_ADD_ALT_BOOT_DEVICE (0x00008000) 1529299263Sslm#define MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG (0x00004000) 1530265236Sken 1531299263Sslm#define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800) 1532299263Sslm#define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL (0x00000000) 1533299263Sslm#define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE (0x00000800) 1534299263Sslm#define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID (0x00001000) 1535299263Sslm#define MPI2_BIOSPAGE1_OPTIONS_PNS_PSENS (0x00001800) 1536299263Sslm#define MPI2_BIOSPAGE1_OPTIONS_PNS_ESPHY (0x00002000) 1537265236Sken 1538299263Sslm#define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS (0x00000400) 1539265236Sken 1540299263Sslm#define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD (0x00000300) 1541299263Sslm#define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD (0x00000000) 1542299263Sslm#define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD (0x00000100) 1543299263Sslm#define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD (0x00000200) 1544299263Sslm#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD (0x00000300) 1545299263Sslm 1546299263Sslm#define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0) 1547299263Sslm#define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000) 1548299263Sslm 1549299263Sslm#define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006) 1550299263Sslm#define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000) 1551299263Sslm#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002) 1552299263Sslm#define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004) 1553299263Sslm 1554299263Sslm#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1555299263Sslm 1556265236Sken/* values for BIOS Page 1 IOCSettings field */ 1557265236Sken#define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1558265236Sken#define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1559265236Sken#define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1560265236Sken 1561265236Sken#define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1562265236Sken#define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1563265236Sken#define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1564265236Sken#define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1565265236Sken 1566265236Sken#define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1567265236Sken#define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1568265236Sken#define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1569265236Sken#define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1570265236Sken#define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1571265236Sken 1572265236Sken#define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1573265236Sken 1574265236Sken/* values for BIOS Page 1 DeviceSettings field */ 1575265236Sken#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 1576265236Sken#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1577265236Sken#define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1578265236Sken#define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1579265236Sken#define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1580265236Sken 1581265236Sken/* defines for BIOS Page 1 UEFIVersion field */ 1582265236Sken#define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK (0xFF00) 1583265236Sken#define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT (8) 1584265236Sken#define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK (0x00FF) 1585265236Sken#define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT (0) 1586265236Sken 1587265236Sken 1588265236Sken 1589265236Sken/* BIOS Page 2 */ 1590265236Sken 1591265236Skentypedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER 1592265236Sken{ 1593265236Sken U32 Reserved1; /* 0x00 */ 1594265236Sken U32 Reserved2; /* 0x04 */ 1595265236Sken U32 Reserved3; /* 0x08 */ 1596265236Sken U32 Reserved4; /* 0x0C */ 1597265236Sken U32 Reserved5; /* 0x10 */ 1598265236Sken U32 Reserved6; /* 0x14 */ 1599265236Sken} MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1600265236Sken MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1601265236Sken Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t; 1602265236Sken 1603265236Skentypedef struct _MPI2_BOOT_DEVICE_SAS_WWID 1604265236Sken{ 1605265236Sken U64 SASAddress; /* 0x00 */ 1606265236Sken U8 LUN[8]; /* 0x08 */ 1607265236Sken U32 Reserved1; /* 0x10 */ 1608265236Sken U32 Reserved2; /* 0x14 */ 1609265236Sken} MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID, 1610265236Sken Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t; 1611265236Sken 1612265236Skentypedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT 1613265236Sken{ 1614265236Sken U64 EnclosureLogicalID; /* 0x00 */ 1615265236Sken U32 Reserved1; /* 0x08 */ 1616265236Sken U32 Reserved2; /* 0x0C */ 1617265236Sken U16 SlotNumber; /* 0x10 */ 1618265236Sken U16 Reserved3; /* 0x12 */ 1619265236Sken U32 Reserved4; /* 0x14 */ 1620265236Sken} MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1621265236Sken MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1622265236Sken Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t; 1623265236Sken 1624265236Skentypedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME 1625265236Sken{ 1626265236Sken U64 DeviceName; /* 0x00 */ 1627265236Sken U8 LUN[8]; /* 0x08 */ 1628265236Sken U32 Reserved1; /* 0x10 */ 1629265236Sken U32 Reserved2; /* 0x14 */ 1630265236Sken} MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME, 1631265236Sken Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t; 1632265236Sken 1633265236Skentypedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE 1634265236Sken{ 1635265236Sken MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1636265236Sken MPI2_BOOT_DEVICE_SAS_WWID SasWwid; 1637265236Sken MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1638265236Sken MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName; 1639265236Sken} MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE, 1640265236Sken Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t; 1641265236Sken 1642265236Skentypedef struct _MPI2_CONFIG_PAGE_BIOS_2 1643265236Sken{ 1644265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1645265236Sken U32 Reserved1; /* 0x04 */ 1646265236Sken U32 Reserved2; /* 0x08 */ 1647265236Sken U32 Reserved3; /* 0x0C */ 1648265236Sken U32 Reserved4; /* 0x10 */ 1649265236Sken U32 Reserved5; /* 0x14 */ 1650265236Sken U32 Reserved6; /* 0x18 */ 1651265236Sken U8 ReqBootDeviceForm; /* 0x1C */ 1652265236Sken U8 Reserved7; /* 0x1D */ 1653265236Sken U16 Reserved8; /* 0x1E */ 1654265236Sken MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */ 1655265236Sken U8 ReqAltBootDeviceForm; /* 0x38 */ 1656265236Sken U8 Reserved9; /* 0x39 */ 1657265236Sken U16 Reserved10; /* 0x3A */ 1658265236Sken MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */ 1659265236Sken U8 CurrentBootDeviceForm; /* 0x58 */ 1660265236Sken U8 Reserved11; /* 0x59 */ 1661265236Sken U16 Reserved12; /* 0x5A */ 1662265236Sken MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */ 1663265236Sken} MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2, 1664265236Sken Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t; 1665265236Sken 1666265236Sken#define MPI2_BIOSPAGE2_PAGEVERSION (0x04) 1667265236Sken 1668265236Sken/* values for BIOS Page 2 BootDeviceForm fields */ 1669265236Sken#define MPI2_BIOSPAGE2_FORM_MASK (0x0F) 1670265236Sken#define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00) 1671265236Sken#define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05) 1672265236Sken#define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1673265236Sken#define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07) 1674265236Sken 1675265236Sken 1676265236Sken/* BIOS Page 3 */ 1677265236Sken 1678299263Sslm#define MPI2_BIOSPAGE3_NUM_ADAPTER (4) 1679299263Sslm 1680265236Skentypedef struct _MPI2_ADAPTER_INFO 1681265236Sken{ 1682265236Sken U8 PciBusNumber; /* 0x00 */ 1683265236Sken U8 PciDeviceAndFunctionNumber; /* 0x01 */ 1684265236Sken U16 AdapterFlags; /* 0x02 */ 1685265236Sken} MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO, 1686265236Sken Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t; 1687265236Sken 1688265236Sken#define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 1689265236Sken#define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 1690265236Sken 1691299263Sslmtypedef struct _MPI2_ADAPTER_ORDER_AUX 1692299263Sslm{ 1693299263Sslm U64 WWID; /* 0x00 */ 1694299263Sslm U32 Reserved1; /* 0x08 */ 1695299263Sslm U32 Reserved2; /* 0x0C */ 1696299263Sslm} MPI2_ADAPTER_ORDER_AUX, MPI2_POINTER PTR_MPI2_ADAPTER_ORDER_AUX, 1697299263Sslm Mpi2AdapterOrderAux_t, MPI2_POINTER pMpi2AdapterOrderAux_t; 1698299263Sslm 1699265236Skentypedef struct _MPI2_CONFIG_PAGE_BIOS_3 1700265236Sken{ 1701265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1702265236Sken U32 GlobalFlags; /* 0x04 */ 1703265236Sken U32 BiosVersion; /* 0x08 */ 1704299263Sslm MPI2_ADAPTER_INFO AdapterOrder[MPI2_BIOSPAGE3_NUM_ADAPTER]; /* 0x0C */ 1705265236Sken U32 Reserved1; /* 0x1C */ 1706299263Sslm MPI2_ADAPTER_ORDER_AUX AdapterOrderAux[MPI2_BIOSPAGE3_NUM_ADAPTER]; /* 0x20 */ /* MPI v2.5 and newer */ 1707265236Sken} MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3, 1708265236Sken Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t; 1709265236Sken 1710299263Sslm#define MPI2_BIOSPAGE3_PAGEVERSION (0x01) 1711265236Sken 1712265236Sken/* values for BIOS Page 3 GlobalFlags */ 1713265236Sken#define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) 1714265236Sken#define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004) 1715265236Sken#define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010) 1716265236Sken 1717265236Sken#define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 1718265236Sken#define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 1719265236Sken#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020) 1720265236Sken#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 1721265236Sken 1722265236Sken 1723265236Sken/* BIOS Page 4 */ 1724265236Sken 1725265236Sken/* 1726265236Sken * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1727265236Sken * one and check the value returned for NumPhys at runtime. 1728265236Sken */ 1729265236Sken#ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES 1730265236Sken#define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1) 1731265236Sken#endif 1732265236Sken 1733265236Skentypedef struct _MPI2_BIOS4_ENTRY 1734265236Sken{ 1735265236Sken U64 ReassignmentWWID; /* 0x00 */ 1736265236Sken U64 ReassignmentDeviceName; /* 0x08 */ 1737265236Sken} MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY, 1738265236Sken Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t; 1739265236Sken 1740265236Skentypedef struct _MPI2_CONFIG_PAGE_BIOS_4 1741265236Sken{ 1742265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1743265236Sken U8 NumPhys; /* 0x04 */ 1744265236Sken U8 Reserved1; /* 0x05 */ 1745265236Sken U16 Reserved2; /* 0x06 */ 1746265236Sken MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */ 1747265236Sken} MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4, 1748265236Sken Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t; 1749265236Sken 1750265236Sken#define MPI2_BIOSPAGE4_PAGEVERSION (0x01) 1751265236Sken 1752265236Sken 1753265236Sken/**************************************************************************** 1754265236Sken* RAID Volume Config Pages 1755265236Sken****************************************************************************/ 1756265236Sken 1757265236Sken/* RAID Volume Page 0 */ 1758265236Sken 1759265236Skentypedef struct _MPI2_RAIDVOL0_PHYS_DISK 1760265236Sken{ 1761265236Sken U8 RAIDSetNum; /* 0x00 */ 1762265236Sken U8 PhysDiskMap; /* 0x01 */ 1763265236Sken U8 PhysDiskNum; /* 0x02 */ 1764265236Sken U8 Reserved; /* 0x03 */ 1765265236Sken} MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK, 1766265236Sken Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t; 1767265236Sken 1768265236Sken/* defines for the PhysDiskMap field */ 1769265236Sken#define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1770265236Sken#define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1771265236Sken 1772265236Skentypedef struct _MPI2_RAIDVOL0_SETTINGS 1773265236Sken{ 1774265236Sken U16 Settings; /* 0x00 */ 1775265236Sken U8 HotSparePool; /* 0x01 */ 1776265236Sken U8 Reserved; /* 0x02 */ 1777265236Sken} MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS, 1778265236Sken Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t; 1779265236Sken 1780265236Sken/* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1781265236Sken#define MPI2_RAID_HOT_SPARE_POOL_0 (0x01) 1782265236Sken#define MPI2_RAID_HOT_SPARE_POOL_1 (0x02) 1783265236Sken#define MPI2_RAID_HOT_SPARE_POOL_2 (0x04) 1784265236Sken#define MPI2_RAID_HOT_SPARE_POOL_3 (0x08) 1785265236Sken#define MPI2_RAID_HOT_SPARE_POOL_4 (0x10) 1786265236Sken#define MPI2_RAID_HOT_SPARE_POOL_5 (0x20) 1787265236Sken#define MPI2_RAID_HOT_SPARE_POOL_6 (0x40) 1788265236Sken#define MPI2_RAID_HOT_SPARE_POOL_7 (0x80) 1789265236Sken 1790265236Sken/* RAID Volume Page 0 VolumeSettings defines */ 1791265236Sken#define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008) 1792265236Sken#define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004) 1793265236Sken 1794265236Sken#define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003) 1795265236Sken#define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000) 1796265236Sken#define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001) 1797265236Sken#define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002) 1798265236Sken 1799265236Sken/* 1800265236Sken * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1801265236Sken * one and check the value returned for NumPhysDisks at runtime. 1802265236Sken */ 1803265236Sken#ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX 1804265236Sken#define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 1805265236Sken#endif 1806265236Sken 1807265236Skentypedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 1808265236Sken{ 1809265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1810265236Sken U16 DevHandle; /* 0x04 */ 1811265236Sken U8 VolumeState; /* 0x06 */ 1812265236Sken U8 VolumeType; /* 0x07 */ 1813265236Sken U32 VolumeStatusFlags; /* 0x08 */ 1814265236Sken MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */ 1815265236Sken U64 MaxLBA; /* 0x10 */ 1816265236Sken U32 StripeSize; /* 0x18 */ 1817265236Sken U16 BlockSize; /* 0x1C */ 1818265236Sken U16 Reserved1; /* 0x1E */ 1819265236Sken U8 SupportedPhysDisks; /* 0x20 */ 1820265236Sken U8 ResyncRate; /* 0x21 */ 1821265236Sken U16 DataScrubDuration; /* 0x22 */ 1822265236Sken U8 NumPhysDisks; /* 0x24 */ 1823265236Sken U8 Reserved2; /* 0x25 */ 1824265236Sken U8 Reserved3; /* 0x26 */ 1825265236Sken U8 InactiveStatus; /* 0x27 */ 1826265236Sken MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */ 1827265236Sken} MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0, 1828265236Sken Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t; 1829265236Sken 1830265236Sken#define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A) 1831265236Sken 1832265236Sken/* values for RAID VolumeState */ 1833265236Sken#define MPI2_RAID_VOL_STATE_MISSING (0x00) 1834265236Sken#define MPI2_RAID_VOL_STATE_FAILED (0x01) 1835265236Sken#define MPI2_RAID_VOL_STATE_INITIALIZING (0x02) 1836265236Sken#define MPI2_RAID_VOL_STATE_ONLINE (0x03) 1837265236Sken#define MPI2_RAID_VOL_STATE_DEGRADED (0x04) 1838265236Sken#define MPI2_RAID_VOL_STATE_OPTIMAL (0x05) 1839265236Sken 1840265236Sken/* values for RAID VolumeType */ 1841265236Sken#define MPI2_RAID_VOL_TYPE_RAID0 (0x00) 1842265236Sken#define MPI2_RAID_VOL_TYPE_RAID1E (0x01) 1843265236Sken#define MPI2_RAID_VOL_TYPE_RAID1 (0x02) 1844265236Sken#define MPI2_RAID_VOL_TYPE_RAID10 (0x05) 1845265236Sken#define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF) 1846265236Sken 1847265236Sken/* values for RAID Volume Page 0 VolumeStatusFlags field */ 1848265236Sken#define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000) 1849265236Sken#define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000) 1850265236Sken#define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000) 1851265236Sken#define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000) 1852265236Sken#define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000) 1853265236Sken#define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000) 1854265236Sken#define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000) 1855265236Sken#define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000) 1856265236Sken#define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000) 1857265236Sken#define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000) 1858265236Sken#define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080) 1859265236Sken#define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040) 1860265236Sken#define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020) 1861265236Sken#define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000) 1862265236Sken#define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010) 1863265236Sken#define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008) 1864265236Sken#define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004) 1865265236Sken#define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002) 1866265236Sken#define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001) 1867265236Sken 1868265236Sken/* values for RAID Volume Page 0 SupportedPhysDisks field */ 1869265236Sken#define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08) 1870265236Sken#define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04) 1871265236Sken#define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02) 1872265236Sken#define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01) 1873265236Sken 1874265236Sken/* values for RAID Volume Page 0 InactiveStatus field */ 1875265236Sken#define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 1876265236Sken#define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 1877265236Sken#define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 1878265236Sken#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 1879265236Sken#define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 1880265236Sken#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 1881265236Sken#define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 1882265236Sken 1883265236Sken 1884265236Sken/* RAID Volume Page 1 */ 1885265236Sken 1886265236Skentypedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 1887265236Sken{ 1888265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1889265236Sken U16 DevHandle; /* 0x04 */ 1890265236Sken U16 Reserved0; /* 0x06 */ 1891265236Sken U8 GUID[24]; /* 0x08 */ 1892265236Sken U8 Name[16]; /* 0x20 */ 1893265236Sken U64 WWID; /* 0x30 */ 1894265236Sken U32 Reserved1; /* 0x38 */ 1895265236Sken U32 Reserved2; /* 0x3C */ 1896265236Sken} MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1, 1897265236Sken Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t; 1898265236Sken 1899265236Sken#define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03) 1900265236Sken 1901265236Sken 1902265236Sken/**************************************************************************** 1903265236Sken* RAID Physical Disk Config Pages 1904265236Sken****************************************************************************/ 1905265236Sken 1906265236Sken/* RAID Physical Disk Page 0 */ 1907265236Sken 1908265236Skentypedef struct _MPI2_RAIDPHYSDISK0_SETTINGS 1909265236Sken{ 1910265236Sken U16 Reserved1; /* 0x00 */ 1911265236Sken U8 HotSparePool; /* 0x02 */ 1912265236Sken U8 Reserved2; /* 0x03 */ 1913265236Sken} MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS, 1914265236Sken Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t; 1915265236Sken 1916265236Sken/* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */ 1917265236Sken 1918265236Skentypedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA 1919265236Sken{ 1920265236Sken U8 VendorID[8]; /* 0x00 */ 1921265236Sken U8 ProductID[16]; /* 0x08 */ 1922265236Sken U8 ProductRevLevel[4]; /* 0x18 */ 1923265236Sken U8 SerialNum[32]; /* 0x1C */ 1924265236Sken} MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1925265236Sken MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1926265236Sken Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t; 1927265236Sken 1928265236Skentypedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 1929265236Sken{ 1930265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1931265236Sken U16 DevHandle; /* 0x04 */ 1932265236Sken U8 Reserved1; /* 0x06 */ 1933265236Sken U8 PhysDiskNum; /* 0x07 */ 1934265236Sken MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */ 1935265236Sken U32 Reserved2; /* 0x0C */ 1936265236Sken MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */ 1937265236Sken U32 Reserved3; /* 0x4C */ 1938265236Sken U8 PhysDiskState; /* 0x50 */ 1939265236Sken U8 OfflineReason; /* 0x51 */ 1940265236Sken U8 IncompatibleReason; /* 0x52 */ 1941265236Sken U8 PhysDiskAttributes; /* 0x53 */ 1942265236Sken U32 PhysDiskStatusFlags; /* 0x54 */ 1943265236Sken U64 DeviceMaxLBA; /* 0x58 */ 1944265236Sken U64 HostMaxLBA; /* 0x60 */ 1945265236Sken U64 CoercedMaxLBA; /* 0x68 */ 1946265236Sken U16 BlockSize; /* 0x70 */ 1947265236Sken U16 Reserved5; /* 0x72 */ 1948265236Sken U32 Reserved6; /* 0x74 */ 1949265236Sken} MPI2_CONFIG_PAGE_RD_PDISK_0, 1950265236Sken MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0, 1951265236Sken Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t; 1952265236Sken 1953265236Sken#define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05) 1954265236Sken 1955265236Sken/* PhysDiskState defines */ 1956265236Sken#define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00) 1957265236Sken#define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01) 1958265236Sken#define MPI2_RAID_PD_STATE_OFFLINE (0x02) 1959265236Sken#define MPI2_RAID_PD_STATE_ONLINE (0x03) 1960265236Sken#define MPI2_RAID_PD_STATE_HOT_SPARE (0x04) 1961265236Sken#define MPI2_RAID_PD_STATE_DEGRADED (0x05) 1962265236Sken#define MPI2_RAID_PD_STATE_REBUILDING (0x06) 1963265236Sken#define MPI2_RAID_PD_STATE_OPTIMAL (0x07) 1964265236Sken 1965265236Sken/* OfflineReason defines */ 1966265236Sken#define MPI2_PHYSDISK0_ONLINE (0x00) 1967265236Sken#define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01) 1968265236Sken#define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03) 1969265236Sken#define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04) 1970265236Sken#define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05) 1971265236Sken#define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06) 1972265236Sken#define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF) 1973265236Sken 1974265236Sken/* IncompatibleReason defines */ 1975265236Sken#define MPI2_PHYSDISK0_COMPATIBLE (0x00) 1976265236Sken#define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01) 1977265236Sken#define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02) 1978265236Sken#define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03) 1979265236Sken#define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04) 1980265236Sken#define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05) 1981265236Sken#define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06) 1982265236Sken#define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF) 1983265236Sken 1984265236Sken/* PhysDiskAttributes defines */ 1985265236Sken#define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C) 1986265236Sken#define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08) 1987265236Sken#define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04) 1988265236Sken 1989265236Sken#define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03) 1990265236Sken#define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02) 1991265236Sken#define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01) 1992265236Sken 1993265236Sken/* PhysDiskStatusFlags defines */ 1994265236Sken#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040) 1995265236Sken#define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020) 1996265236Sken#define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010) 1997265236Sken#define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000) 1998265236Sken#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008) 1999265236Sken#define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004) 2000265236Sken#define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002) 2001265236Sken#define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001) 2002265236Sken 2003265236Sken 2004265236Sken/* RAID Physical Disk Page 1 */ 2005265236Sken 2006265236Sken/* 2007265236Sken * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2008265236Sken * one and check the value returned for NumPhysDiskPaths at runtime. 2009265236Sken */ 2010265236Sken#ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX 2011265236Sken#define MPI2_RAID_PHYS_DISK1_PATH_MAX (1) 2012265236Sken#endif 2013265236Sken 2014265236Skentypedef struct _MPI2_RAIDPHYSDISK1_PATH 2015265236Sken{ 2016265236Sken U16 DevHandle; /* 0x00 */ 2017265236Sken U16 Reserved1; /* 0x02 */ 2018265236Sken U64 WWID; /* 0x04 */ 2019265236Sken U64 OwnerWWID; /* 0x0C */ 2020265236Sken U8 OwnerIdentifier; /* 0x14 */ 2021265236Sken U8 Reserved2; /* 0x15 */ 2022265236Sken U16 Flags; /* 0x16 */ 2023265236Sken} MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH, 2024265236Sken Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t; 2025265236Sken 2026265236Sken/* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */ 2027265236Sken#define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004) 2028265236Sken#define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 2029265236Sken#define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 2030265236Sken 2031265236Skentypedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 2032265236Sken{ 2033265236Sken MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2034265236Sken U8 NumPhysDiskPaths; /* 0x04 */ 2035265236Sken U8 PhysDiskNum; /* 0x05 */ 2036265236Sken U16 Reserved1; /* 0x06 */ 2037265236Sken U32 Reserved2; /* 0x08 */ 2038265236Sken MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */ 2039265236Sken} MPI2_CONFIG_PAGE_RD_PDISK_1, 2040265236Sken MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1, 2041265236Sken Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t; 2042265236Sken 2043265236Sken#define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02) 2044265236Sken 2045265236Sken 2046265236Sken/**************************************************************************** 2047265236Sken* values for fields used by several types of SAS Config Pages 2048265236Sken****************************************************************************/ 2049265236Sken 2050265236Sken/* values for NegotiatedLinkRates fields */ 2051265236Sken#define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0) 2052265236Sken#define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4) 2053265236Sken#define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 2054265236Sken/* link rates used for Negotiated Physical and Logical Link Rate */ 2055265236Sken#define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 2056265236Sken#define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 2057265236Sken#define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 2058265236Sken#define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 2059265236Sken#define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 2060265236Sken#define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 2061265236Sken#define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 2062265236Sken#define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08) 2063265236Sken#define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09) 2064265236Sken#define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A) 2065265236Sken#define MPI25_SAS_NEG_LINK_RATE_12_0 (0x0B) 2066319435Sslm#define MPI26_SAS_NEG_LINK_RATE_22_5 (0x0C) 2067265236Sken 2068265236Sken 2069265236Sken/* values for AttachedPhyInfo fields */ 2070265236Sken#define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 2071265236Sken#define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 2072265236Sken#define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 2073265236Sken 2074265236Sken#define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F) 2075265236Sken#define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 2076265236Sken#define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 2077265236Sken#define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 2078265236Sken#define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 2079265236Sken#define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 2080265236Sken#define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 2081265236Sken#define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 2082265236Sken#define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 2083265236Sken#define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 2084265236Sken 2085265236Sken 2086265236Sken/* values for PhyInfo fields */ 2087265236Sken#define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000) 2088265236Sken 2089265236Sken#define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 2090265236Sken#define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27) 2091265236Sken#define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000) 2092265236Sken#define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000) 2093265236Sken#define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000) 2094265236Sken 2095265236Sken#define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000) 2096265236Sken#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000) 2097265236Sken#define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000) 2098265236Sken#define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 2099265236Sken#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000) 2100265236Sken#define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 2101265236Sken 2102265236Sken#define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000) 2103265236Sken#define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 2104265236Sken#define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 2105265236Sken#define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 2106265236Sken#define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 2107265236Sken#define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 2108265236Sken#define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 2109265236Sken#define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 2110265236Sken#define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 2111265236Sken#define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 2112265236Sken 2113265236Sken#define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000) 2114265236Sken#define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 2115265236Sken#define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 2116265236Sken#define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 2117265236Sken 2118265236Sken#define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 2119265236Sken#define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 2120265236Sken 2121265236Sken#define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 2122265236Sken#define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000) 2123265236Sken#define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 2124265236Sken#define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020) 2125265236Sken 2126265236Sken 2127265236Sken/* values for SAS ProgrammedLinkRate fields */ 2128265236Sken#define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0) 2129265236Sken#define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 2130265236Sken#define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80) 2131265236Sken#define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90) 2132265236Sken#define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0) 2133265236Sken#define MPI25_SAS_PRATE_MAX_RATE_12_0 (0xB0) 2134319435Sslm#define MPI26_SAS_PRATE_MAX_RATE_22_5 (0xC0) 2135265236Sken#define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F) 2136265236Sken#define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 2137265236Sken#define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08) 2138265236Sken#define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09) 2139265236Sken#define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A) 2140265236Sken#define MPI25_SAS_PRATE_MIN_RATE_12_0 (0x0B) 2141319435Sslm#define MPI26_SAS_PRATE_MIN_RATE_22_5 (0x0C) 2142265236Sken 2143265236Sken 2144265236Sken/* values for SAS HwLinkRate fields */ 2145265236Sken#define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0) 2146265236Sken#define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80) 2147265236Sken#define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90) 2148265236Sken#define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0) 2149265236Sken#define MPI25_SAS_HWRATE_MAX_RATE_12_0 (0xB0) 2150319435Sslm#define MPI26_SAS_HWRATE_MAX_RATE_22_5 (0xC0) 2151265236Sken#define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F) 2152265236Sken#define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08) 2153265236Sken#define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09) 2154265236Sken#define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A) 2155265236Sken#define MPI25_SAS_HWRATE_MIN_RATE_12_0 (0x0B) 2156319435Sslm#define MPI26_SAS_HWRATE_MIN_RATE_22_5 (0x0C) 2157265236Sken 2158265236Sken 2159265236Sken 2160265236Sken/**************************************************************************** 2161265236Sken* SAS IO Unit Config Pages 2162265236Sken****************************************************************************/ 2163265236Sken 2164265236Sken/* SAS IO Unit Page 0 */ 2165265236Sken 2166265236Skentypedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA 2167265236Sken{ 2168265236Sken U8 Port; /* 0x00 */ 2169265236Sken U8 PortFlags; /* 0x01 */ 2170265236Sken U8 PhyFlags; /* 0x02 */ 2171265236Sken U8 NegotiatedLinkRate; /* 0x03 */ 2172265236Sken U32 ControllerPhyDeviceInfo;/* 0x04 */ 2173265236Sken U16 AttachedDevHandle; /* 0x08 */ 2174265236Sken U16 ControllerDevHandle; /* 0x0A */ 2175265236Sken U32 DiscoveryStatus; /* 0x0C */ 2176265236Sken U32 Reserved; /* 0x10 */ 2177265236Sken} MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA, 2178265236Sken Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t; 2179265236Sken 2180265236Sken/* 2181265236Sken * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2182265236Sken * one and check the value returned for NumPhys at runtime. 2183265236Sken */ 2184265236Sken#ifndef MPI2_SAS_IOUNIT0_PHY_MAX 2185265236Sken#define MPI2_SAS_IOUNIT0_PHY_MAX (1) 2186265236Sken#endif 2187265236Sken 2188265236Skentypedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 2189265236Sken{ 2190265236Sken MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2191265236Sken U32 Reserved1; /* 0x08 */ 2192265236Sken U8 NumPhys; /* 0x0C */ 2193265236Sken U8 Reserved2; /* 0x0D */ 2194265236Sken U16 Reserved3; /* 0x0E */ 2195265236Sken MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */ 2196265236Sken} MPI2_CONFIG_PAGE_SASIOUNIT_0, 2197265236Sken MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0, 2198265236Sken Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t; 2199265236Sken 2200265236Sken#define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05) 2201265236Sken 2202265236Sken/* values for SAS IO Unit Page 0 PortFlags */ 2203265236Sken#define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08) 2204265236Sken#define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) 2205265236Sken 2206265236Sken/* values for SAS IO Unit Page 0 PhyFlags */ 2207299263Sslm#define MPI2_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2208299263Sslm#define MPI2_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2209265236Sken#define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) 2210265236Sken#define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 2211265236Sken 2212265236Sken/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2213265236Sken 2214265236Sken/* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 2215265236Sken 2216265236Sken/* values for SAS IO Unit Page 0 DiscoveryStatus */ 2217265236Sken#define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2218265236Sken#define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2219265236Sken#define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000) 2220265236Sken#define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2221265236Sken#define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2222265236Sken#define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2223265236Sken#define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2224265236Sken#define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 2225265236Sken#define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2226265236Sken#define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 2227265236Sken#define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400) 2228265236Sken#define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 2229265236Sken#define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 2230265236Sken#define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 2231265236Sken#define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 2232265236Sken#define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2233265236Sken#define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010) 2234265236Sken#define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 2235265236Sken#define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2236265236Sken#define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001) 2237265236Sken 2238265236Sken 2239265236Sken/* SAS IO Unit Page 1 */ 2240265236Sken 2241265236Skentypedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA 2242265236Sken{ 2243265236Sken U8 Port; /* 0x00 */ 2244265236Sken U8 PortFlags; /* 0x01 */ 2245265236Sken U8 PhyFlags; /* 0x02 */ 2246265236Sken U8 MaxMinLinkRate; /* 0x03 */ 2247265236Sken U32 ControllerPhyDeviceInfo; /* 0x04 */ 2248265236Sken U16 MaxTargetPortConnectTime; /* 0x08 */ 2249265236Sken U16 Reserved1; /* 0x0A */ 2250265236Sken} MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA, 2251265236Sken Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t; 2252265236Sken 2253265236Sken/* 2254265236Sken * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2255265236Sken * one and check the value returned for NumPhys at runtime. 2256265236Sken */ 2257265236Sken#ifndef MPI2_SAS_IOUNIT1_PHY_MAX 2258265236Sken#define MPI2_SAS_IOUNIT1_PHY_MAX (1) 2259265236Sken#endif 2260265236Sken 2261265236Skentypedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 2262265236Sken{ 2263265236Sken MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2264265236Sken U16 ControlFlags; /* 0x08 */ 2265265236Sken U16 SASNarrowMaxQueueDepth; /* 0x0A */ 2266265236Sken U16 AdditionalControlFlags; /* 0x0C */ 2267265236Sken U16 SASWideMaxQueueDepth; /* 0x0E */ 2268265236Sken U8 NumPhys; /* 0x10 */ 2269265236Sken U8 SATAMaxQDepth; /* 0x11 */ 2270265236Sken U8 ReportDeviceMissingDelay; /* 0x12 */ 2271265236Sken U8 IODeviceMissingDelay; /* 0x13 */ 2272265236Sken MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */ 2273265236Sken} MPI2_CONFIG_PAGE_SASIOUNIT_1, 2274265236Sken MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1, 2275265236Sken Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t; 2276265236Sken 2277265236Sken#define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09) 2278265236Sken 2279265236Sken/* values for SAS IO Unit Page 1 ControlFlags */ 2280265236Sken#define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 2281265236Sken#define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 2282265236Sken#define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) /* MPI v2.0 only. Obsolete in MPI v2.5 and later. */ 2283265236Sken#define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 2284265236Sken 2285265236Sken#define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 2286265236Sken#define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 2287265236Sken#define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0) 2288265236Sken#define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1) 2289265236Sken#define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2) 2290265236Sken 2291265236Sken#define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 2292265236Sken#define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 2293265236Sken#define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 2294265236Sken#define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 2295265236Sken#define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 2296265236Sken#define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 2297265236Sken#define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 2298265236Sken#define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) /* MPI v2.0 only. Obsolete in MPI v2.5 and later. */ 2299265236Sken 2300265236Sken/* values for SAS IO Unit Page 1 AdditionalControlFlags */ 2301299263Sslm#define MPI2_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100) 2302265236Sken#define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 2303265236Sken#define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 2304265236Sken#define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 2305265236Sken#define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 2306265236Sken#define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 2307265236Sken#define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 2308265236Sken#define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 2309265236Sken#define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 2310265236Sken 2311265236Sken/* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 2312265236Sken#define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 2313265236Sken#define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 2314265236Sken 2315265236Sken/* values for SAS IO Unit Page 1 PortFlags */ 2316265236Sken#define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2317265236Sken 2318265236Sken/* values for SAS IO Unit Page 1 PhyFlags */ 2319299263Sslm#define MPI2_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2320299263Sslm#define MPI2_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2321265236Sken#define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) 2322265236Sken#define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 2323265236Sken 2324265236Sken/* values for SAS IO Unit Page 1 MaxMinLinkRate */ 2325265236Sken#define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) 2326265236Sken#define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) 2327265236Sken#define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) 2328265236Sken#define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) 2329265236Sken#define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0) 2330319435Sslm#define MPI26_SASIOUNIT1_MAX_RATE_22_5 (0xC0) 2331265236Sken#define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) 2332265236Sken#define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) 2333265236Sken#define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) 2334265236Sken#define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) 2335265236Sken#define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B) 2336319435Sslm#define MPI26_SASIOUNIT1_MIN_RATE_22_5 (0x0C) 2337265236Sken 2338265236Sken/* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 2339265236Sken 2340265236Sken 2341299263Sslm/* SAS IO Unit Page 4 (for MPI v2.5 and earlier) */ 2342265236Sken 2343265236Skentypedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP 2344265236Sken{ 2345265236Sken U8 MaxTargetSpinup; /* 0x00 */ 2346265236Sken U8 SpinupDelay; /* 0x01 */ 2347265236Sken U8 SpinupFlags; /* 0x02 */ 2348265236Sken U8 Reserved1; /* 0x03 */ 2349265236Sken} MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP, 2350265236Sken Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t; 2351265236Sken 2352265236Sken/* defines for SAS IO Unit Page 4 SpinupFlags */ 2353265236Sken#define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01) 2354265236Sken 2355265236Sken 2356265236Sken/* 2357265236Sken * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2358265236Sken * one and check the value returned for NumPhys at runtime. 2359265236Sken */ 2360265236Sken#ifndef MPI2_SAS_IOUNIT4_PHY_MAX 2361265236Sken#define MPI2_SAS_IOUNIT4_PHY_MAX (4) 2362265236Sken#endif 2363265236Sken 2364265236Skentypedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 2365265236Sken{ 2366265236Sken MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2367265236Sken MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ 2368265236Sken U32 Reserved1; /* 0x18 */ 2369265236Sken U32 Reserved2; /* 0x1C */ 2370265236Sken U32 Reserved3; /* 0x20 */ 2371265236Sken U8 BootDeviceWaitTime; /* 0x24 */ 2372299263Sslm U8 SATADeviceWaitTime; /* 0x25 */ 2373265236Sken U16 Reserved5; /* 0x26 */ 2374265236Sken U8 NumPhys; /* 0x28 */ 2375265236Sken U8 PEInitialSpinupDelay; /* 0x29 */ 2376265236Sken U8 PEReplyDelay; /* 0x2A */ 2377265236Sken U8 Flags; /* 0x2B */ 2378265236Sken U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */ 2379265236Sken} MPI2_CONFIG_PAGE_SASIOUNIT_4, 2380265236Sken MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4, 2381265236Sken Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t; 2382265236Sken 2383265236Sken#define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02) 2384265236Sken 2385265236Sken/* defines for Flags field */ 2386265236Sken#define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01) 2387265236Sken 2388265236Sken/* defines for PHY field */ 2389265236Sken#define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03) 2390265236Sken 2391265236Sken 2392265236Sken/* SAS IO Unit Page 5 */ 2393265236Sken 2394265236Skentypedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS 2395265236Sken{ 2396265236Sken U8 ControlFlags; /* 0x00 */ 2397265236Sken U8 PortWidthModGroup; /* 0x01 */ 2398265236Sken U16 InactivityTimerExponent; /* 0x02 */ 2399265236Sken U8 SATAPartialTimeout; /* 0x04 */ 2400265236Sken U8 Reserved2; /* 0x05 */ 2401265236Sken U8 SATASlumberTimeout; /* 0x06 */ 2402265236Sken U8 Reserved3; /* 0x07 */ 2403265236Sken U8 SASPartialTimeout; /* 0x08 */ 2404265236Sken U8 Reserved4; /* 0x09 */ 2405265236Sken U8 SASSlumberTimeout; /* 0x0A */ 2406265236Sken U8 Reserved5; /* 0x0B */ 2407265236Sken} MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2408265236Sken MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2409265236Sken Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t; 2410265236Sken 2411265236Sken/* defines for ControlFlags field */ 2412265236Sken#define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08) 2413265236Sken#define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04) 2414265236Sken#define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02) 2415265236Sken#define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01) 2416265236Sken 2417265236Sken/* defines for PortWidthModeGroup field */ 2418265236Sken#define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF) 2419265236Sken 2420265236Sken/* defines for InactivityTimerExponent field */ 2421265236Sken#define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000) 2422265236Sken#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12) 2423265236Sken#define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700) 2424265236Sken#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8) 2425265236Sken#define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070) 2426265236Sken#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4) 2427265236Sken#define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007) 2428265236Sken#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0) 2429265236Sken 2430265236Sken#define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7) 2431265236Sken#define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6) 2432265236Sken#define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5) 2433265236Sken#define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4) 2434265236Sken#define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3) 2435265236Sken#define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2) 2436265236Sken#define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1) 2437265236Sken#define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0) 2438265236Sken 2439265236Sken/* 2440265236Sken * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2441265236Sken * one and check the value returned for NumPhys at runtime. 2442265236Sken */ 2443265236Sken#ifndef MPI2_SAS_IOUNIT5_PHY_MAX 2444265236Sken#define MPI2_SAS_IOUNIT5_PHY_MAX (1) 2445265236Sken#endif 2446265236Sken 2447265236Skentypedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 2448265236Sken{ 2449265236Sken MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2450265236Sken U8 NumPhys; /* 0x08 */ 2451265236Sken U8 Reserved1; /* 0x09 */ 2452265236Sken U16 Reserved2; /* 0x0A */ 2453265236Sken U32 Reserved3; /* 0x0C */ 2454265236Sken MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */ 2455265236Sken} MPI2_CONFIG_PAGE_SASIOUNIT_5, 2456265236Sken MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5, 2457265236Sken Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t; 2458265236Sken 2459265236Sken#define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01) 2460265236Sken 2461265236Sken 2462265236Sken/* SAS IO Unit Page 6 */ 2463265236Sken 2464265236Skentypedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 2465265236Sken{ 2466265236Sken U8 CurrentStatus; /* 0x00 */ 2467265236Sken U8 CurrentModulation; /* 0x01 */ 2468265236Sken U8 CurrentUtilization; /* 0x02 */ 2469265236Sken U8 Reserved1; /* 0x03 */ 2470265236Sken U32 Reserved2; /* 0x04 */ 2471265236Sken} MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2472265236Sken MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2473265236Sken Mpi2SasIOUnit6PortWidthModGroupStatus_t, 2474265236Sken MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t; 2475265236Sken 2476265236Sken/* defines for CurrentStatus field */ 2477265236Sken#define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00) 2478265236Sken#define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01) 2479265236Sken#define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02) 2480265236Sken#define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03) 2481265236Sken#define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04) 2482265236Sken#define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05) 2483265236Sken#define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06) 2484265236Sken#define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07) 2485265236Sken 2486265236Sken/* defines for CurrentModulation field */ 2487265236Sken#define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00) 2488265236Sken#define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01) 2489265236Sken#define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02) 2490265236Sken#define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03) 2491265236Sken 2492265236Sken/* 2493265236Sken * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2494265236Sken * one and check the value returned for NumGroups at runtime. 2495265236Sken */ 2496265236Sken#ifndef MPI2_SAS_IOUNIT6_GROUP_MAX 2497265236Sken#define MPI2_SAS_IOUNIT6_GROUP_MAX (1) 2498265236Sken#endif 2499265236Sken 2500265236Skentypedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 2501265236Sken{ 2502265236Sken MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2503265236Sken U32 Reserved1; /* 0x08 */ 2504265236Sken U32 Reserved2; /* 0x0C */ 2505265236Sken U8 NumGroups; /* 0x10 */ 2506265236Sken U8 Reserved3; /* 0x11 */ 2507265236Sken U16 Reserved4; /* 0x12 */ 2508265236Sken MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 2509265236Sken PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */ 2510265236Sken} MPI2_CONFIG_PAGE_SASIOUNIT_6, 2511265236Sken MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6, 2512265236Sken Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t; 2513265236Sken 2514265236Sken#define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00) 2515265236Sken 2516265236Sken 2517265236Sken/* SAS IO Unit Page 7 */ 2518265236Sken 2519265236Skentypedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2520265236Sken{ 2521265236Sken U8 Flags; /* 0x00 */ 2522265236Sken U8 Reserved1; /* 0x01 */ 2523265236Sken U16 Reserved2; /* 0x02 */ 2524265236Sken U8 Threshold75Pct; /* 0x04 */ 2525265236Sken U8 Threshold50Pct; /* 0x05 */ 2526265236Sken U8 Threshold25Pct; /* 0x06 */ 2527265236Sken U8 Reserved3; /* 0x07 */ 2528265236Sken} MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2529265236Sken MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2530265236Sken Mpi2SasIOUnit7PortWidthModGroupSettings_t, 2531265236Sken MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t; 2532265236Sken 2533265236Sken/* defines for Flags field */ 2534265236Sken#define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01) 2535265236Sken 2536265236Sken 2537265236Sken/* 2538265236Sken * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2539265236Sken * one and check the value returned for NumGroups at runtime. 2540265236Sken */ 2541265236Sken#ifndef MPI2_SAS_IOUNIT7_GROUP_MAX 2542265236Sken#define MPI2_SAS_IOUNIT7_GROUP_MAX (1) 2543265236Sken#endif 2544265236Sken 2545265236Skentypedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 2546265236Sken{ 2547265236Sken MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2548265236Sken U8 SamplingInterval; /* 0x08 */ 2549265236Sken U8 WindowLength; /* 0x09 */ 2550265236Sken U16 Reserved1; /* 0x0A */ 2551265236Sken U32 Reserved2; /* 0x0C */ 2552265236Sken U32 Reserved3; /* 0x10 */ 2553265236Sken U8 NumGroups; /* 0x14 */ 2554265236Sken U8 Reserved4; /* 0x15 */ 2555265236Sken U16 Reserved5; /* 0x16 */ 2556265236Sken MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2557265236Sken PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */ 2558265236Sken} MPI2_CONFIG_PAGE_SASIOUNIT_7, 2559265236Sken MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7, 2560265236Sken Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t; 2561265236Sken 2562265236Sken#define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00) 2563265236Sken 2564265236Sken 2565265236Sken/* SAS IO Unit Page 8 */ 2566265236Sken 2567265236Skentypedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 2568265236Sken{ 2569265236Sken MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2570265236Sken U32 Reserved1; /* 0x08 */ 2571265236Sken U32 PowerManagementCapabilities; /* 0x0C */ 2572265236Sken U8 TxRxSleepStatus; /* 0x10 */ /* reserved in MPI 2.0 */ 2573265236Sken U8 Reserved2; /* 0x11 */ 2574265236Sken U16 Reserved3; /* 0x12 */ 2575265236Sken} MPI2_CONFIG_PAGE_SASIOUNIT_8, 2576265236Sken MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8, 2577265236Sken Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t; 2578265236Sken 2579265236Sken#define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00) 2580265236Sken 2581265236Sken/* defines for PowerManagementCapabilities field */ 2582265236Sken#define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000) 2583265236Sken#define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800) 2584265236Sken#define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400) 2585265236Sken#define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200) 2586265236Sken#define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100) 2587265236Sken#define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010) 2588265236Sken#define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008) 2589265236Sken#define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004) 2590265236Sken#define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002) 2591265236Sken#define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001) 2592265236Sken 2593265236Sken/* defines for TxRxSleepStatus field */ 2594265236Sken#define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED (0x00) 2595265236Sken#define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED (0x01) 2596265236Sken#define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE (0x02) 2597265236Sken#define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN (0x03) 2598265236Sken 2599265236Sken 2600265236Sken 2601265236Sken/* SAS IO Unit Page 16 */ 2602265236Sken 2603265236Skentypedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 2604265236Sken{ 2605265236Sken MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2606265236Sken U64 TimeStamp; /* 0x08 */ 2607265236Sken U32 Reserved1; /* 0x10 */ 2608265236Sken U32 Reserved2; /* 0x14 */ 2609265236Sken U32 FastPathPendedRequests; /* 0x18 */ 2610265236Sken U32 FastPathUnPendedRequests; /* 0x1C */ 2611265236Sken U32 FastPathHostRequestStarts; /* 0x20 */ 2612265236Sken U32 FastPathFirmwareRequestStarts; /* 0x24 */ 2613265236Sken U32 FastPathHostCompletions; /* 0x28 */ 2614265236Sken U32 FastPathFirmwareCompletions; /* 0x2C */ 2615265236Sken U32 NonFastPathRequestStarts; /* 0x30 */ 2616265236Sken U32 NonFastPathHostCompletions; /* 0x30 */ 2617265236Sken} MPI2_CONFIG_PAGE_SASIOUNIT16, 2618265236Sken MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT16, 2619265236Sken Mpi2SasIOUnitPage16_t, MPI2_POINTER pMpi2SasIOUnitPage16_t; 2620265236Sken 2621265236Sken#define MPI2_SASIOUNITPAGE16_PAGEVERSION (0x00) 2622265236Sken 2623265236Sken 2624265236Sken/**************************************************************************** 2625265236Sken* SAS Expander Config Pages 2626265236Sken****************************************************************************/ 2627265236Sken 2628265236Sken/* SAS Expander Page 0 */ 2629265236Sken 2630265236Skentypedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 2631265236Sken{ 2632265236Sken MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2633265236Sken U8 PhysicalPort; /* 0x08 */ 2634265236Sken U8 ReportGenLength; /* 0x09 */ 2635265236Sken U16 EnclosureHandle; /* 0x0A */ 2636265236Sken U64 SASAddress; /* 0x0C */ 2637265236Sken U32 DiscoveryStatus; /* 0x14 */ 2638265236Sken U16 DevHandle; /* 0x18 */ 2639265236Sken U16 ParentDevHandle; /* 0x1A */ 2640265236Sken U16 ExpanderChangeCount; /* 0x1C */ 2641265236Sken U16 ExpanderRouteIndexes; /* 0x1E */ 2642265236Sken U8 NumPhys; /* 0x20 */ 2643265236Sken U8 SASLevel; /* 0x21 */ 2644265236Sken U16 Flags; /* 0x22 */ 2645265236Sken U16 STPBusInactivityTimeLimit; /* 0x24 */ 2646265236Sken U16 STPMaxConnectTimeLimit; /* 0x26 */ 2647265236Sken U16 STP_SMP_NexusLossTime; /* 0x28 */ 2648265236Sken U16 MaxNumRoutedSasAddresses; /* 0x2A */ 2649265236Sken U64 ActiveZoneManagerSASAddress;/* 0x2C */ 2650265236Sken U16 ZoneLockInactivityLimit; /* 0x34 */ 2651265236Sken U16 Reserved1; /* 0x36 */ 2652265236Sken U8 TimeToReducedFunc; /* 0x38 */ 2653265236Sken U8 InitialTimeToReducedFunc; /* 0x39 */ 2654265236Sken U8 MaxReducedFuncTime; /* 0x3A */ 2655265236Sken U8 Reserved2; /* 0x3B */ 2656265236Sken} MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0, 2657265236Sken Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t; 2658265236Sken 2659265236Sken#define MPI2_SASEXPANDER0_PAGEVERSION (0x06) 2660265236Sken 2661265236Sken/* values for SAS Expander Page 0 DiscoveryStatus field */ 2662265236Sken#define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2663265236Sken#define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2664265236Sken#define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000) 2665265236Sken#define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2666265236Sken#define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2667265236Sken#define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2668265236Sken#define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2669265236Sken#define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000) 2670265236Sken#define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2671265236Sken#define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2672265236Sken#define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2673265236Sken#define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2674265236Sken#define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2675265236Sken#define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2676265236Sken#define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2677265236Sken#define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2678265236Sken#define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2679265236Sken#define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2680265236Sken#define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2681265236Sken#define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2682265236Sken 2683265236Sken/* values for SAS Expander Page 0 Flags field */ 2684265236Sken#define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 2685265236Sken#define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 2686265236Sken#define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 2687265236Sken#define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 2688265236Sken#define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 2689265236Sken#define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 2690265236Sken#define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 2691265236Sken#define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 2692265236Sken#define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 2693265236Sken#define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 2694265236Sken#define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 2695265236Sken 2696265236Sken 2697265236Sken/* SAS Expander Page 1 */ 2698265236Sken 2699265236Skentypedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 2700265236Sken{ 2701265236Sken MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2702265236Sken U8 PhysicalPort; /* 0x08 */ 2703265236Sken U8 Reserved1; /* 0x09 */ 2704265236Sken U16 Reserved2; /* 0x0A */ 2705265236Sken U8 NumPhys; /* 0x0C */ 2706265236Sken U8 Phy; /* 0x0D */ 2707265236Sken U16 NumTableEntriesProgrammed; /* 0x0E */ 2708265236Sken U8 ProgrammedLinkRate; /* 0x10 */ 2709265236Sken U8 HwLinkRate; /* 0x11 */ 2710265236Sken U16 AttachedDevHandle; /* 0x12 */ 2711265236Sken U32 PhyInfo; /* 0x14 */ 2712265236Sken U32 AttachedDeviceInfo; /* 0x18 */ 2713265236Sken U16 ExpanderDevHandle; /* 0x1C */ 2714265236Sken U8 ChangeCount; /* 0x1E */ 2715265236Sken U8 NegotiatedLinkRate; /* 0x1F */ 2716265236Sken U8 PhyIdentifier; /* 0x20 */ 2717265236Sken U8 AttachedPhyIdentifier; /* 0x21 */ 2718265236Sken U8 Reserved3; /* 0x22 */ 2719265236Sken U8 DiscoveryInfo; /* 0x23 */ 2720265236Sken U32 AttachedPhyInfo; /* 0x24 */ 2721265236Sken U8 ZoneGroup; /* 0x28 */ 2722265236Sken U8 SelfConfigStatus; /* 0x29 */ 2723265236Sken U16 Reserved4; /* 0x2A */ 2724265236Sken} MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1, 2725265236Sken Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t; 2726265236Sken 2727265236Sken#define MPI2_SASEXPANDER1_PAGEVERSION (0x02) 2728265236Sken 2729265236Sken/* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2730265236Sken 2731265236Sken/* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2732265236Sken 2733265236Sken/* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2734265236Sken 2735265236Sken/* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */ 2736265236Sken 2737265236Sken/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2738265236Sken 2739265236Sken/* values for SAS Expander Page 1 DiscoveryInfo field */ 2740265236Sken#define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2741265236Sken#define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2742265236Sken#define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2743265236Sken 2744265236Sken/* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2745265236Sken 2746265236Sken 2747265236Sken/**************************************************************************** 2748265236Sken* SAS Device Config Pages 2749265236Sken****************************************************************************/ 2750265236Sken 2751265236Sken/* SAS Device Page 0 */ 2752265236Sken 2753265236Skentypedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 2754265236Sken{ 2755265236Sken MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2756265236Sken U16 Slot; /* 0x08 */ 2757265236Sken U16 EnclosureHandle; /* 0x0A */ 2758265236Sken U64 SASAddress; /* 0x0C */ 2759265236Sken U16 ParentDevHandle; /* 0x14 */ 2760265236Sken U8 PhyNum; /* 0x16 */ 2761265236Sken U8 AccessStatus; /* 0x17 */ 2762265236Sken U16 DevHandle; /* 0x18 */ 2763265236Sken U8 AttachedPhyIdentifier; /* 0x1A */ 2764265236Sken U8 ZoneGroup; /* 0x1B */ 2765265236Sken U32 DeviceInfo; /* 0x1C */ 2766265236Sken U16 Flags; /* 0x20 */ 2767265236Sken U8 PhysicalPort; /* 0x22 */ 2768265236Sken U8 MaxPortConnections; /* 0x23 */ 2769265236Sken U64 DeviceName; /* 0x24 */ 2770265236Sken U8 PortGroups; /* 0x2C */ 2771265236Sken U8 DmaGroup; /* 0x2D */ 2772265236Sken U8 ControlGroup; /* 0x2E */ 2773265236Sken U8 EnclosureLevel; /* 0x2F */ 2774265236Sken U8 ConnectorName[4]; /* 0x30 */ 2775265236Sken U32 Reserved3; /* 0x34 */ 2776265236Sken} MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0, 2777265236Sken Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t; 2778265236Sken 2779265236Sken#define MPI2_SASDEVICE0_PAGEVERSION (0x09) 2780265236Sken 2781265236Sken/* values for SAS Device Page 0 AccessStatus field */ 2782265236Sken#define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2783265236Sken#define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2784265236Sken#define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2785265236Sken#define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2786265236Sken#define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2787265236Sken#define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05) 2788265236Sken#define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06) 2789265236Sken#define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07) 2790265236Sken/* specific values for SATA Init failures */ 2791265236Sken#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2792265236Sken#define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2793265236Sken#define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2794265236Sken#define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2795265236Sken#define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2796265236Sken#define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2797265236Sken#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2798265236Sken#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2799265236Sken#define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2800265236Sken#define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2801265236Sken#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2802265236Sken 2803265236Sken/* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2804265236Sken 2805265236Sken/* values for SAS Device Page 0 Flags field */ 2806265236Sken#define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000) 2807265236Sken#define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH (0x4000) 2808265236Sken#define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE (0x2000) 2809265236Sken#define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000) 2810265236Sken#define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800) 2811265236Sken#define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2812265236Sken#define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2813265236Sken#define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2814265236Sken#define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2815265236Sken#define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2816265236Sken#define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2817265236Sken#define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2818265236Sken#define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2819299263Sslm#define MPI2_SAS_DEVICE0_FLAGS_PERSIST_CAPABLE (0x0004) 2820265236Sken#define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID (0x0002) 2821265236Sken#define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2822265236Sken 2823265236Sken/* SAS Device Page 1 */ 2824265236Sken 2825265236Skentypedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 2826265236Sken{ 2827265236Sken MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2828265236Sken U32 Reserved1; /* 0x08 */ 2829265236Sken U64 SASAddress; /* 0x0C */ 2830265236Sken U32 Reserved2; /* 0x14 */ 2831265236Sken U16 DevHandle; /* 0x18 */ 2832265236Sken U16 Reserved3; /* 0x1A */ 2833265236Sken U8 InitialRegDeviceFIS[20];/* 0x1C */ 2834265236Sken} MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1, 2835265236Sken Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t; 2836265236Sken 2837265236Sken#define MPI2_SASDEVICE1_PAGEVERSION (0x01) 2838265236Sken 2839265236Sken 2840265236Sken/**************************************************************************** 2841265236Sken* SAS PHY Config Pages 2842265236Sken****************************************************************************/ 2843265236Sken 2844265236Sken/* SAS PHY Page 0 */ 2845265236Sken 2846265236Skentypedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 2847265236Sken{ 2848265236Sken MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2849265236Sken U16 OwnerDevHandle; /* 0x08 */ 2850265236Sken U16 Reserved1; /* 0x0A */ 2851265236Sken U16 AttachedDevHandle; /* 0x0C */ 2852265236Sken U8 AttachedPhyIdentifier; /* 0x0E */ 2853265236Sken U8 Reserved2; /* 0x0F */ 2854265236Sken U32 AttachedPhyInfo; /* 0x10 */ 2855265236Sken U8 ProgrammedLinkRate; /* 0x14 */ 2856265236Sken U8 HwLinkRate; /* 0x15 */ 2857265236Sken U8 ChangeCount; /* 0x16 */ 2858265236Sken U8 Flags; /* 0x17 */ 2859265236Sken U32 PhyInfo; /* 0x18 */ 2860265236Sken U8 NegotiatedLinkRate; /* 0x1C */ 2861265236Sken U8 Reserved3; /* 0x1D */ 2862265236Sken U16 Reserved4; /* 0x1E */ 2863265236Sken} MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0, 2864265236Sken Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t; 2865265236Sken 2866265236Sken#define MPI2_SASPHY0_PAGEVERSION (0x03) 2867265236Sken 2868265236Sken/* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2869265236Sken 2870265236Sken/* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2871265236Sken 2872265236Sken/* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2873265236Sken 2874265236Sken/* values for SAS PHY Page 0 Flags field */ 2875265236Sken#define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 2876265236Sken 2877265236Sken/* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2878265236Sken 2879265236Sken/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2880265236Sken 2881265236Sken 2882265236Sken/* SAS PHY Page 1 */ 2883265236Sken 2884265236Skentypedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 2885265236Sken{ 2886265236Sken MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2887265236Sken U32 Reserved1; /* 0x08 */ 2888265236Sken U32 InvalidDwordCount; /* 0x0C */ 2889265236Sken U32 RunningDisparityErrorCount; /* 0x10 */ 2890265236Sken U32 LossDwordSynchCount; /* 0x14 */ 2891265236Sken U32 PhyResetProblemCount; /* 0x18 */ 2892265236Sken} MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1, 2893265236Sken Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t; 2894265236Sken 2895265236Sken#define MPI2_SASPHY1_PAGEVERSION (0x01) 2896265236Sken 2897265236Sken 2898265236Sken/* SAS PHY Page 2 */ 2899265236Sken 2900265236Skentypedef struct _MPI2_SASPHY2_PHY_EVENT 2901265236Sken{ 2902265236Sken U8 PhyEventCode; /* 0x00 */ 2903265236Sken U8 Reserved1; /* 0x01 */ 2904265236Sken U16 Reserved2; /* 0x02 */ 2905265236Sken U32 PhyEventInfo; /* 0x04 */ 2906265236Sken} MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT, 2907265236Sken Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t; 2908265236Sken 2909265236Sken/* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */ 2910265236Sken 2911265236Sken 2912265236Sken/* 2913265236Sken * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2914265236Sken * one and check the value returned for NumPhyEvents at runtime. 2915265236Sken */ 2916265236Sken#ifndef MPI2_SASPHY2_PHY_EVENT_MAX 2917265236Sken#define MPI2_SASPHY2_PHY_EVENT_MAX (1) 2918265236Sken#endif 2919265236Sken 2920265236Skentypedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 2921265236Sken{ 2922265236Sken MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2923265236Sken U32 Reserved1; /* 0x08 */ 2924265236Sken U8 NumPhyEvents; /* 0x0C */ 2925265236Sken U8 Reserved2; /* 0x0D */ 2926265236Sken U16 Reserved3; /* 0x0E */ 2927265236Sken MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /* 0x10 */ 2928265236Sken} MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2, 2929265236Sken Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t; 2930265236Sken 2931265236Sken#define MPI2_SASPHY2_PAGEVERSION (0x00) 2932265236Sken 2933265236Sken 2934265236Sken/* SAS PHY Page 3 */ 2935265236Sken 2936265236Skentypedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG 2937265236Sken{ 2938265236Sken U8 PhyEventCode; /* 0x00 */ 2939265236Sken U8 Reserved1; /* 0x01 */ 2940265236Sken U16 Reserved2; /* 0x02 */ 2941265236Sken U8 CounterType; /* 0x04 */ 2942265236Sken U8 ThresholdWindow; /* 0x05 */ 2943265236Sken U8 TimeUnits; /* 0x06 */ 2944265236Sken U8 Reserved3; /* 0x07 */ 2945265236Sken U32 EventThreshold; /* 0x08 */ 2946265236Sken U16 ThresholdFlags; /* 0x0C */ 2947265236Sken U16 Reserved4; /* 0x0E */ 2948265236Sken} MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG, 2949265236Sken Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t; 2950265236Sken 2951265236Sken/* values for PhyEventCode field */ 2952265236Sken#define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 2953265236Sken#define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 2954265236Sken#define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 2955265236Sken#define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 2956265236Sken#define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 2957265236Sken#define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 2958265236Sken#define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 2959265236Sken#define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 2960265236Sken#define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 2961265236Sken#define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 2962265236Sken#define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 2963265236Sken#define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 2964265236Sken#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 2965265236Sken#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 2966265236Sken#define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 2967265236Sken#define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 2968265236Sken#define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 2969265236Sken#define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A) 2970265236Sken#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B) 2971265236Sken#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C) 2972265236Sken#define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D) 2973265236Sken#define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E) 2974265236Sken#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 2975265236Sken#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 2976265236Sken#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 2977265236Sken#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 2978265236Sken#define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 2979265236Sken#define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 2980265236Sken#define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 2981265236Sken#define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 2982265236Sken#define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 2983265236Sken#define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 2984265236Sken#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 2985265236Sken#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 2986265236Sken#define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) 2987265236Sken#define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) 2988265236Sken#define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2) 2989299263Sslm/* Following codes are product specific and in MPI v2.6 and later */ 2990299263Sslm#define MPI2_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xD3) 2991299263Sslm#define MPI2_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xD4) 2992299263Sslm#define MPI2_SASPHY3_EVENT_CODE_LCCONN_TIME (0xD5) 2993299263Sslm#define MPI2_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xD6) 2994299263Sslm#define MPI2_SASPHY3_EVENT_CODE_SATA_TX_START (0xD7) 2995299263Sslm#define MPI2_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xD8) 2996299263Sslm#define MPI2_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xD9) 2997299263Sslm#define MPI2_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xDA) 2998299263Sslm#define MPI2_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xDB) 2999299263Sslm#define MPI2_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xDC) 3000299263Sslm 3001265236Sken/* values for the CounterType field */ 3002265236Sken#define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 3003265236Sken#define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 3004265236Sken#define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 3005265236Sken 3006265236Sken/* values for the TimeUnits field */ 3007265236Sken#define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 3008265236Sken#define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 3009265236Sken#define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 3010265236Sken#define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 3011265236Sken 3012265236Sken/* values for the ThresholdFlags field */ 3013265236Sken#define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002) 3014265236Sken#define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 3015265236Sken 3016265236Sken/* 3017265236Sken * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3018265236Sken * one and check the value returned for NumPhyEvents at runtime. 3019265236Sken */ 3020265236Sken#ifndef MPI2_SASPHY3_PHY_EVENT_MAX 3021265236Sken#define MPI2_SASPHY3_PHY_EVENT_MAX (1) 3022265236Sken#endif 3023265236Sken 3024265236Skentypedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 3025265236Sken{ 3026265236Sken MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3027265236Sken U32 Reserved1; /* 0x08 */ 3028265236Sken U8 NumPhyEvents; /* 0x0C */ 3029265236Sken U8 Reserved2; /* 0x0D */ 3030265236Sken U16 Reserved3; /* 0x0E */ 3031265236Sken MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */ 3032265236Sken} MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3, 3033265236Sken Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t; 3034265236Sken 3035265236Sken#define MPI2_SASPHY3_PAGEVERSION (0x00) 3036265236Sken 3037265236Sken 3038265236Sken/* SAS PHY Page 4 */ 3039265236Sken 3040265236Skentypedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 3041265236Sken{ 3042265236Sken MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3043265236Sken U16 Reserved1; /* 0x08 */ 3044265236Sken U8 Reserved2; /* 0x0A */ 3045265236Sken U8 Flags; /* 0x0B */ 3046265236Sken U8 InitialFrame[28]; /* 0x0C */ 3047265236Sken} MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4, 3048265236Sken Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t; 3049265236Sken 3050265236Sken#define MPI2_SASPHY4_PAGEVERSION (0x00) 3051265236Sken 3052265236Sken/* values for the Flags field */ 3053265236Sken#define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02) 3054265236Sken#define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01) 3055265236Sken 3056265236Sken 3057265236Sken 3058265236Sken 3059265236Sken/**************************************************************************** 3060265236Sken* SAS Port Config Pages 3061265236Sken****************************************************************************/ 3062265236Sken 3063265236Sken/* SAS Port Page 0 */ 3064265236Sken 3065265236Skentypedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 3066265236Sken{ 3067265236Sken MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3068265236Sken U8 PortNumber; /* 0x08 */ 3069265236Sken U8 PhysicalPort; /* 0x09 */ 3070265236Sken U8 PortWidth; /* 0x0A */ 3071265236Sken U8 PhysicalPortWidth; /* 0x0B */ 3072265236Sken U8 ZoneGroup; /* 0x0C */ 3073265236Sken U8 Reserved1; /* 0x0D */ 3074265236Sken U16 Reserved2; /* 0x0E */ 3075265236Sken U64 SASAddress; /* 0x10 */ 3076265236Sken U32 DeviceInfo; /* 0x18 */ 3077265236Sken U32 Reserved3; /* 0x1C */ 3078265236Sken U32 Reserved4; /* 0x20 */ 3079265236Sken} MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0, 3080265236Sken Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t; 3081265236Sken 3082265236Sken#define MPI2_SASPORT0_PAGEVERSION (0x00) 3083265236Sken 3084265236Sken/* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */ 3085265236Sken 3086265236Sken 3087265236Sken/**************************************************************************** 3088265236Sken* SAS Enclosure Config Pages 3089265236Sken****************************************************************************/ 3090265236Sken 3091319435Sslm/* SAS Enclosure Page 0, Enclosure Page 0 */ 3092265236Sken 3093265236Skentypedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 3094265236Sken{ 3095265236Sken MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3096265236Sken U32 Reserved1; /* 0x08 */ 3097265236Sken U64 EnclosureLogicalID; /* 0x0C */ 3098265236Sken U16 Flags; /* 0x14 */ 3099265236Sken U16 EnclosureHandle; /* 0x16 */ 3100265236Sken U16 NumSlots; /* 0x18 */ 3101265236Sken U16 StartSlot; /* 0x1A */ 3102331903Smav U8 ChassisSlot; /* 0x1C */ 3103265236Sken U8 EnclosureLevel; /* 0x1D */ 3104265236Sken U16 SEPDevHandle; /* 0x1E */ 3105331903Smav U32 Reserved2; /* 0x20 */ 3106331903Smav U32 Reserved3; /* 0x24 */ 3107265236Sken} MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3108265236Sken MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3109319435Sslm Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t, 3110319435Sslm MPI26_CONFIG_PAGE_ENCLOSURE_0, 3111319435Sslm MPI2_POINTER PTR_MPI26_CONFIG_PAGE_ENCLOSURE_0, 3112319435Sslm Mpi26EnclosurePage0_t, MPI2_POINTER pMpi26EnclosurePage0_t; 3113265236Sken 3114265236Sken#define MPI2_SASENCLOSURE0_PAGEVERSION (0x04) 3115265236Sken 3116265236Sken/* values for SAS Enclosure Page 0 Flags field */ 3117331903Smav#define MPI2_SAS_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020) 3118265236Sken#define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010) 3119265236Sken#define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 3120265236Sken#define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3121265236Sken#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3122265236Sken#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3123265236Sken#define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3124265236Sken#define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3125265236Sken#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3126265236Sken 3127319435Sslm#define MPI26_ENCLOSURE0_PAGEVERSION (0x04) 3128265236Sken 3129319435Sslm/* Values for Enclosure Page 0 Flags field */ 3130331903Smav#define MPI26_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020) 3131319435Sslm#define MPI26_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010) 3132319435Sslm#define MPI26_ENCLS0_FLAGS_MNG_MASK (0x000F) 3133319435Sslm#define MPI26_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3134319435Sslm#define MPI26_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3135319435Sslm#define MPI26_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3136319435Sslm#define MPI26_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3137319435Sslm#define MPI26_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3138319435Sslm#define MPI26_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3139319435Sslm 3140265236Sken/**************************************************************************** 3141265236Sken* Log Config Page 3142265236Sken****************************************************************************/ 3143265236Sken 3144265236Sken/* Log Page 0 */ 3145265236Sken 3146265236Sken/* 3147265236Sken * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3148265236Sken * one and check the value returned for NumLogEntries at runtime. 3149265236Sken */ 3150265236Sken#ifndef MPI2_LOG_0_NUM_LOG_ENTRIES 3151265236Sken#define MPI2_LOG_0_NUM_LOG_ENTRIES (1) 3152265236Sken#endif 3153265236Sken 3154265236Sken#define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C) 3155265236Sken 3156265236Skentypedef struct _MPI2_LOG_0_ENTRY 3157265236Sken{ 3158265236Sken U64 TimeStamp; /* 0x00 */ 3159265236Sken U32 Reserved1; /* 0x08 */ 3160265236Sken U16 LogSequence; /* 0x0C */ 3161265236Sken U16 LogEntryQualifier; /* 0x0E */ 3162265236Sken U8 VP_ID; /* 0x10 */ 3163265236Sken U8 VF_ID; /* 0x11 */ 3164265236Sken U16 Reserved2; /* 0x12 */ 3165265236Sken U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */ 3166265236Sken} MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY, 3167265236Sken Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t; 3168265236Sken 3169265236Sken/* values for Log Page 0 LogEntry LogEntryQualifier field */ 3170265236Sken#define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 3171265236Sken#define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 3172265236Sken#define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002) 3173265236Sken#define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000) 3174265236Sken#define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF) 3175265236Sken 3176265236Skentypedef struct _MPI2_CONFIG_PAGE_LOG_0 3177265236Sken{ 3178265236Sken MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3179265236Sken U32 Reserved1; /* 0x08 */ 3180265236Sken U32 Reserved2; /* 0x0C */ 3181265236Sken U16 NumLogEntries; /* 0x10 */ 3182265236Sken U16 Reserved3; /* 0x12 */ 3183265236Sken MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */ 3184265236Sken} MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0, 3185265236Sken Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t; 3186265236Sken 3187265236Sken#define MPI2_LOG_0_PAGEVERSION (0x02) 3188265236Sken 3189265236Sken 3190265236Sken/**************************************************************************** 3191265236Sken* RAID Config Page 3192265236Sken****************************************************************************/ 3193265236Sken 3194265236Sken/* RAID Page 0 */ 3195265236Sken 3196265236Sken/* 3197265236Sken * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3198265236Sken * one and check the value returned for NumElements at runtime. 3199265236Sken */ 3200265236Sken#ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS 3201265236Sken#define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1) 3202265236Sken#endif 3203265236Sken 3204265236Skentypedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT 3205265236Sken{ 3206265236Sken U16 ElementFlags; /* 0x00 */ 3207265236Sken U16 VolDevHandle; /* 0x02 */ 3208265236Sken U8 HotSparePool; /* 0x04 */ 3209265236Sken U8 PhysDiskNum; /* 0x05 */ 3210265236Sken U16 PhysDiskDevHandle; /* 0x06 */ 3211265236Sken} MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3212265236Sken MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3213265236Sken Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t; 3214265236Sken 3215265236Sken/* values for the ElementFlags field */ 3216265236Sken#define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F) 3217265236Sken#define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000) 3218265236Sken#define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001) 3219265236Sken#define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002) 3220265236Sken#define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003) 3221265236Sken 3222265236Sken 3223265236Skentypedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 3224265236Sken{ 3225265236Sken MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3226265236Sken U8 NumHotSpares; /* 0x08 */ 3227265236Sken U8 NumPhysDisks; /* 0x09 */ 3228265236Sken U8 NumVolumes; /* 0x0A */ 3229265236Sken U8 ConfigNum; /* 0x0B */ 3230265236Sken U32 Flags; /* 0x0C */ 3231265236Sken U8 ConfigGUID[24]; /* 0x10 */ 3232265236Sken U32 Reserved1; /* 0x28 */ 3233265236Sken U8 NumElements; /* 0x2C */ 3234265236Sken U8 Reserved2; /* 0x2D */ 3235265236Sken U16 Reserved3; /* 0x2E */ 3236265236Sken MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */ 3237265236Sken} MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3238265236Sken MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3239265236Sken Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t; 3240265236Sken 3241265236Sken#define MPI2_RAIDCONFIG0_PAGEVERSION (0x00) 3242265236Sken 3243265236Sken/* values for RAID Configuration Page 0 Flags field */ 3244265236Sken#define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001) 3245265236Sken 3246265236Sken 3247265236Sken/**************************************************************************** 3248265236Sken* Driver Persistent Mapping Config Pages 3249265236Sken****************************************************************************/ 3250265236Sken 3251265236Sken/* Driver Persistent Mapping Page 0 */ 3252265236Sken 3253265236Skentypedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY 3254265236Sken{ 3255265236Sken U64 PhysicalIdentifier; /* 0x00 */ 3256265236Sken U16 MappingInformation; /* 0x08 */ 3257265236Sken U16 DeviceIndex; /* 0x0A */ 3258265236Sken U32 PhysicalBitsMapping; /* 0x0C */ 3259265236Sken U32 Reserved1; /* 0x10 */ 3260265236Sken} MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3261265236Sken MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3262265236Sken Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t; 3263265236Sken 3264265236Skentypedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 3265265236Sken{ 3266265236Sken MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3267265236Sken MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */ 3268265236Sken} MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3269265236Sken MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3270265236Sken Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t; 3271265236Sken 3272265236Sken#define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00) 3273265236Sken 3274265236Sken/* values for Driver Persistent Mapping Page 0 MappingInformation field */ 3275265236Sken#define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0) 3276265236Sken#define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4) 3277265236Sken#define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F) 3278265236Sken 3279265236Sken 3280265236Sken/**************************************************************************** 3281265236Sken* Ethernet Config Pages 3282265236Sken****************************************************************************/ 3283265236Sken 3284265236Sken/* Ethernet Page 0 */ 3285265236Sken 3286265236Sken/* IP address (union of IPv4 and IPv6) */ 3287265236Skentypedef union _MPI2_ETHERNET_IP_ADDR 3288265236Sken{ 3289265236Sken U32 IPv4Addr; 3290265236Sken U32 IPv6Addr[4]; 3291265236Sken} MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR, 3292265236Sken Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t; 3293265236Sken 3294265236Sken#define MPI2_ETHERNET_HOST_NAME_LENGTH (32) 3295265236Sken 3296265236Skentypedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 3297265236Sken{ 3298265236Sken MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3299265236Sken U8 NumInterfaces; /* 0x08 */ 3300265236Sken U8 Reserved0; /* 0x09 */ 3301265236Sken U16 Reserved1; /* 0x0A */ 3302265236Sken U32 Status; /* 0x0C */ 3303265236Sken U8 MediaState; /* 0x10 */ 3304265236Sken U8 Reserved2; /* 0x11 */ 3305265236Sken U16 Reserved3; /* 0x12 */ 3306265236Sken U8 MacAddress[6]; /* 0x14 */ 3307265236Sken U8 Reserved4; /* 0x1A */ 3308265236Sken U8 Reserved5; /* 0x1B */ 3309265236Sken MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */ 3310265236Sken MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */ 3311265236Sken MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */ 3312265236Sken MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */ 3313265236Sken MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */ 3314265236Sken MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */ 3315265236Sken U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 3316265236Sken} MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0, 3317265236Sken Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t; 3318265236Sken 3319265236Sken#define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00) 3320265236Sken 3321265236Sken/* values for Ethernet Page 0 Status field */ 3322265236Sken#define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000) 3323265236Sken#define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000) 3324265236Sken#define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000) 3325265236Sken#define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100) 3326265236Sken#define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080) 3327265236Sken#define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040) 3328265236Sken#define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020) 3329265236Sken#define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010) 3330265236Sken#define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008) 3331265236Sken#define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004) 3332265236Sken#define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002) 3333265236Sken#define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001) 3334265236Sken 3335265236Sken/* values for Ethernet Page 0 MediaState field */ 3336265236Sken#define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80) 3337265236Sken#define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00) 3338265236Sken#define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80) 3339265236Sken 3340265236Sken#define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07) 3341265236Sken#define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00) 3342265236Sken#define MPI2_ETHPG0_MS_10MBIT (0x01) 3343265236Sken#define MPI2_ETHPG0_MS_100MBIT (0x02) 3344265236Sken#define MPI2_ETHPG0_MS_1GBIT (0x03) 3345265236Sken 3346265236Sken 3347265236Sken/* Ethernet Page 1 */ 3348265236Sken 3349265236Skentypedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 3350265236Sken{ 3351265236Sken MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3352265236Sken U32 Reserved0; /* 0x08 */ 3353265236Sken U32 Flags; /* 0x0C */ 3354265236Sken U8 MediaState; /* 0x10 */ 3355265236Sken U8 Reserved1; /* 0x11 */ 3356265236Sken U16 Reserved2; /* 0x12 */ 3357265236Sken U8 MacAddress[6]; /* 0x14 */ 3358265236Sken U8 Reserved3; /* 0x1A */ 3359265236Sken U8 Reserved4; /* 0x1B */ 3360265236Sken MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */ 3361265236Sken MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */ 3362265236Sken MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */ 3363265236Sken MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */ 3364265236Sken MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */ 3365265236Sken U32 Reserved5; /* 0x6C */ 3366265236Sken U32 Reserved6; /* 0x70 */ 3367265236Sken U32 Reserved7; /* 0x74 */ 3368265236Sken U32 Reserved8; /* 0x78 */ 3369265236Sken U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 3370265236Sken} MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1, 3371265236Sken Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t; 3372265236Sken 3373265236Sken#define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00) 3374265236Sken 3375265236Sken/* values for Ethernet Page 1 Flags field */ 3376265236Sken#define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100) 3377265236Sken#define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080) 3378265236Sken#define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040) 3379265236Sken#define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020) 3380265236Sken#define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010) 3381265236Sken#define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008) 3382265236Sken#define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004) 3383265236Sken#define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002) 3384265236Sken#define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001) 3385265236Sken 3386265236Sken/* values for Ethernet Page 1 MediaState field */ 3387265236Sken#define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80) 3388265236Sken#define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00) 3389265236Sken#define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80) 3390265236Sken 3391265236Sken#define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07) 3392265236Sken#define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00) 3393265236Sken#define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01) 3394265236Sken#define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02) 3395265236Sken#define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03) 3396265236Sken 3397265236Sken 3398265236Sken/**************************************************************************** 3399265236Sken* Extended Manufacturing Config Pages 3400265236Sken****************************************************************************/ 3401265236Sken 3402265236Sken/* 3403265236Sken * Generic structure to use for product-specific extended manufacturing pages 3404265236Sken * (currently Extended Manufacturing Page 40 through Extended Manufacturing 3405265236Sken * Page 60). 3406265236Sken */ 3407265236Sken 3408265236Skentypedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS 3409265236Sken{ 3410265236Sken MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3411265236Sken U32 ProductSpecificInfo; /* 0x08 */ 3412265236Sken} MPI2_CONFIG_PAGE_EXT_MAN_PS, 3413265236Sken MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS, 3414265236Sken Mpi2ExtManufacturingPagePS_t, MPI2_POINTER pMpi2ExtManufacturingPagePS_t; 3415265236Sken 3416265236Sken/* PageVersion should be provided by product-specific code */ 3417265236Sken 3418319435Sslm 3419319435Sslm/**************************************************************************** 3420319435Sslm* values for fields used by several types of PCIe Config Pages 3421319435Sslm****************************************************************************/ 3422319435Sslm 3423319435Sslm/* values for NegotiatedLinkRates fields */ 3424319435Sslm#define MPI26_PCIE_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 3425319435Sslm/* link rates used for Negotiated Physical Link Rate */ 3426319435Sslm#define MPI26_PCIE_NEG_LINK_RATE_UNKNOWN (0x00) 3427319435Sslm#define MPI26_PCIE_NEG_LINK_RATE_PHY_DISABLED (0x01) 3428319435Sslm#define MPI26_PCIE_NEG_LINK_RATE_2_5 (0x02) 3429319435Sslm#define MPI26_PCIE_NEG_LINK_RATE_5_0 (0x03) 3430319435Sslm#define MPI26_PCIE_NEG_LINK_RATE_8_0 (0x04) 3431319435Sslm#define MPI26_PCIE_NEG_LINK_RATE_16_0 (0x05) 3432319435Sslm 3433319435Sslm 3434319435Sslm/**************************************************************************** 3435319435Sslm* PCIe IO Unit Config Pages (MPI v2.6 and later) 3436319435Sslm****************************************************************************/ 3437319435Sslm 3438319435Sslm/* PCIe IO Unit Page 0 */ 3439319435Sslm 3440319435Sslmtypedef struct _MPI26_PCIE_IO_UNIT0_PHY_DATA 3441319435Sslm{ 3442319435Sslm U8 Link; /* 0x00 */ 3443319435Sslm U8 LinkFlags; /* 0x01 */ 3444319435Sslm U8 PhyFlags; /* 0x02 */ 3445319435Sslm U8 NegotiatedLinkRate; /* 0x03 */ 3446319435Sslm U32 ControllerPhyDeviceInfo;/* 0x04 */ 3447319435Sslm U16 AttachedDevHandle; /* 0x08 */ 3448319435Sslm U16 ControllerDevHandle; /* 0x0A */ 3449319435Sslm U32 EnumerationStatus; /* 0x0C */ 3450319435Sslm U32 Reserved1; /* 0x10 */ 3451319435Sslm} MPI26_PCIE_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI26_PCIE_IO_UNIT0_PHY_DATA, 3452319435Sslm Mpi26PCIeIOUnit0PhyData_t, MPI2_POINTER pMpi26PCIeIOUnit0PhyData_t; 3453319435Sslm 3454319435Sslm/* 3455319435Sslm * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3456319435Sslm * one and check the value returned for NumPhys at runtime. 3457319435Sslm */ 3458319435Sslm#ifndef MPI26_PCIE_IOUNIT0_PHY_MAX 3459319435Sslm#define MPI26_PCIE_IOUNIT0_PHY_MAX (1) 3460265236Sken#endif 3461265236Sken 3462319435Sslmtypedef struct _MPI26_CONFIG_PAGE_PIOUNIT_0 3463319435Sslm{ 3464319435Sslm MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3465319435Sslm U32 Reserved1; /* 0x08 */ 3466319435Sslm U8 NumPhys; /* 0x0C */ 3467319435Sslm U8 InitStatus; /* 0x0D */ 3468319435Sslm U16 Reserved3; /* 0x0E */ 3469319435Sslm MPI26_PCIE_IO_UNIT0_PHY_DATA PhyData[MPI26_PCIE_IOUNIT0_PHY_MAX]; /* 0x10 */ 3470319435Sslm} MPI26_CONFIG_PAGE_PIOUNIT_0, 3471319435Sslm MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PIOUNIT_0, 3472319435Sslm Mpi26PCIeIOUnitPage0_t, MPI2_POINTER pMpi26PCIeIOUnitPage0_t; 3473319435Sslm 3474319435Sslm#define MPI26_PCIEIOUNITPAGE0_PAGEVERSION (0x00) 3475319435Sslm 3476319435Sslm/* values for PCIe IO Unit Page 0 LinkFlags */ 3477319435Sslm#define MPI26_PCIEIOUNIT0_LINKFLAGS_ENUMERATION_IN_PROGRESS (0x08) 3478319435Sslm 3479319435Sslm/* values for PCIe IO Unit Page 0 PhyFlags */ 3480319435Sslm#define MPI26_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 3481319435Sslm 3482319435Sslm/* use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3483319435Sslm 3484319435Sslm/* see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo values */ 3485319435Sslm 3486319435Sslm/* values for PCIe IO Unit Page 0 EnumerationStatus */ 3487319435Sslm#define MPI26_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED (0x40000000) 3488319435Sslm#define MPI26_PCIEIOUNIT0_ES_MAX_DEVICES_EXCEEDED (0x20000000) 3489319435Sslm 3490319435Sslm 3491319435Sslm/* PCIe IO Unit Page 1 */ 3492319435Sslm 3493319435Sslmtypedef struct _MPI26_PCIE_IO_UNIT1_PHY_DATA 3494319435Sslm{ 3495319435Sslm U8 Link; /* 0x00 */ 3496319435Sslm U8 LinkFlags; /* 0x01 */ 3497319435Sslm U8 PhyFlags; /* 0x02 */ 3498319435Sslm U8 MaxMinLinkRate; /* 0x03 */ 3499319435Sslm U32 ControllerPhyDeviceInfo; /* 0x04 */ 3500319435Sslm U32 Reserved1; /* 0x08 */ 3501319435Sslm} MPI26_PCIE_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI26_PCIE_IO_UNIT1_PHY_DATA, 3502319435Sslm Mpi26PCIeIOUnit1PhyData_t, MPI2_POINTER pMpi26PCIeIOUnit1PhyData_t; 3503319435Sslm 3504319435Sslm/* values for LinkFlags */ 3505319435Sslm#define MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SRIS (0x00) 3506319435Sslm#define MPI26_PCIEIOUNIT1_LINKFLAGS_EN_SRIS (0x01) 3507319435Sslm 3508319435Sslm/* 3509319435Sslm * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3510319435Sslm * one and check the value returned for NumPhys at runtime. 3511319435Sslm */ 3512319435Sslm#ifndef MPI26_PCIE_IOUNIT1_PHY_MAX 3513319435Sslm#define MPI26_PCIE_IOUNIT1_PHY_MAX (1) 3514319435Sslm#endif 3515319435Sslm 3516319435Sslmtypedef struct _MPI26_CONFIG_PAGE_PIOUNIT_1 3517319435Sslm{ 3518319435Sslm MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3519319435Sslm U16 ControlFlags; /* 0x08 */ 3520319435Sslm U16 Reserved; /* 0x0A */ 3521319435Sslm U16 AdditionalControlFlags; /* 0x0C */ 3522319435Sslm U16 NVMeMaxQueueDepth; /* 0x0E */ 3523319435Sslm U8 NumPhys; /* 0x10 */ 3524319435Sslm U8 Reserved1; /* 0x11 */ 3525319435Sslm U16 Reserved2; /* 0x12 */ 3526319435Sslm MPI26_PCIE_IO_UNIT1_PHY_DATA PhyData[MPI26_PCIE_IOUNIT1_PHY_MAX];/* 0x14 */ 3527319435Sslm} MPI26_CONFIG_PAGE_PIOUNIT_1, 3528319435Sslm MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PIOUNIT_1, 3529319435Sslm Mpi26PCIeIOUnitPage1_t, MPI2_POINTER pMpi26PCIeIOUnitPage1_t; 3530319435Sslm 3531319435Sslm#define MPI26_PCIEIOUNITPAGE1_PAGEVERSION (0x00) 3532319435Sslm 3533319435Sslm/* values for PCIe IO Unit Page 1 PhyFlags */ 3534319435Sslm#define MPI26_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 3535319435Sslm#define MPI26_PCIEIOUNIT1_PHYFLAGS_ENDPOINT_ONLY (0x01) 3536319435Sslm 3537319435Sslm/* values for PCIe IO Unit Page 1 MaxMinLinkRate */ 3538319435Sslm#define MPI26_PCIEIOUNIT1_MAX_RATE_MASK (0xF0) 3539319435Sslm#define MPI26_PCIEIOUNIT1_MAX_RATE_SHIFT (4) 3540319435Sslm#define MPI26_PCIEIOUNIT1_MAX_RATE_2_5 (0x20) 3541319435Sslm#define MPI26_PCIEIOUNIT1_MAX_RATE_5_0 (0x30) 3542319435Sslm#define MPI26_PCIEIOUNIT1_MAX_RATE_8_0 (0x40) 3543319435Sslm#define MPI26_PCIEIOUNIT1_MAX_RATE_16_0 (0x50) 3544319435Sslm 3545319435Sslm/* see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo values */ 3546319435Sslm 3547319435Sslm 3548319435Sslm/**************************************************************************** 3549319435Sslm* PCIe Switch Config Pages (MPI v2.6 and later) 3550319435Sslm****************************************************************************/ 3551319435Sslm 3552319435Sslm/* PCIe Switch Page 0 */ 3553319435Sslm 3554319435Sslmtypedef struct _MPI26_CONFIG_PAGE_PSWITCH_0 3555319435Sslm{ 3556319435Sslm MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3557319435Sslm U8 PhysicalPort; /* 0x08 */ 3558319435Sslm U8 Reserved1; /* 0x09 */ 3559319435Sslm U16 Reserved2; /* 0x0A */ 3560319435Sslm U16 DevHandle; /* 0x0C */ 3561319435Sslm U16 ParentDevHandle; /* 0x0E */ 3562319435Sslm U8 NumPorts; /* 0x10 */ 3563319435Sslm U8 PCIeLevel; /* 0x11 */ 3564319435Sslm U16 Reserved3; /* 0x12 */ 3565319435Sslm U32 Reserved4; /* 0x14 */ 3566319435Sslm U32 Reserved5; /* 0x18 */ 3567319435Sslm U32 Reserved6; /* 0x1C */ 3568319435Sslm} MPI26_CONFIG_PAGE_PSWITCH_0, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PSWITCH_0, 3569319435Sslm Mpi26PCIeSwitchPage0_t, MPI2_POINTER pMpi26PCIeSwitchPage0_t; 3570319435Sslm 3571319435Sslm#define MPI26_PCIESWITCH0_PAGEVERSION (0x00) 3572319435Sslm 3573319435Sslm 3574319435Sslm/* PCIe Switch Page 1 */ 3575319435Sslm 3576319435Sslmtypedef struct _MPI26_CONFIG_PAGE_PSWITCH_1 3577319435Sslm{ 3578319435Sslm MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3579319435Sslm U8 PhysicalPort; /* 0x08 */ 3580319435Sslm U8 Reserved1; /* 0x09 */ 3581319435Sslm U16 Reserved2; /* 0x0A */ 3582319435Sslm U8 NumPorts; /* 0x0C */ 3583319435Sslm U8 PortNum; /* 0x0D */ 3584319435Sslm U16 AttachedDevHandle; /* 0x0E */ 3585319435Sslm U16 SwitchDevHandle; /* 0x10 */ 3586319435Sslm U8 NegotiatedPortWidth; /* 0x12 */ 3587319435Sslm U8 NegotiatedLinkRate; /* 0x13 */ 3588319435Sslm U32 Reserved4; /* 0x14 */ 3589319435Sslm U32 Reserved5; /* 0x18 */ 3590319435Sslm} MPI26_CONFIG_PAGE_PSWITCH_1, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PSWITCH_1, 3591319435Sslm Mpi26PCIeSwitchPage1_t, MPI2_POINTER pMpi26PCIeSwitchPage1_t; 3592319435Sslm 3593319435Sslm#define MPI26_PCIESWITCH1_PAGEVERSION (0x00) 3594319435Sslm 3595319435Sslm/* use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3596319435Sslm 3597319435Sslm 3598319435Sslm/**************************************************************************** 3599319435Sslm* PCIe Device Config Pages (MPI v2.6 and later) 3600319435Sslm****************************************************************************/ 3601319435Sslm 3602319435Sslm/* PCIe Device Page 0 */ 3603319435Sslm 3604319435Sslmtypedef struct _MPI26_CONFIG_PAGE_PCIEDEV_0 3605319435Sslm{ 3606319435Sslm MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3607319435Sslm U16 Slot; /* 0x08 */ 3608319435Sslm U16 EnclosureHandle; /* 0x0A */ 3609319435Sslm U64 WWID; /* 0x0C */ 3610319435Sslm U16 ParentDevHandle; /* 0x14 */ 3611319435Sslm U8 PortNum; /* 0x16 */ 3612319435Sslm U8 AccessStatus; /* 0x17 */ 3613319435Sslm U16 DevHandle; /* 0x18 */ 3614319435Sslm U8 PhysicalPort; /* 0x1A */ 3615319435Sslm U8 Reserved1; /* 0x1B */ 3616319435Sslm U32 DeviceInfo; /* 0x1C */ 3617319435Sslm U32 Flags; /* 0x20 */ 3618319435Sslm U8 SupportedLinkRates; /* 0x24 */ 3619319435Sslm U8 MaxPortWidth; /* 0x25 */ 3620319435Sslm U8 NegotiatedPortWidth; /* 0x26 */ 3621319435Sslm U8 NegotiatedLinkRate; /* 0x27 */ 3622319435Sslm U8 EnclosureLevel; /* 0x28 */ 3623319435Sslm U8 Reserved2; /* 0x29 */ 3624319435Sslm U16 Reserved3; /* 0x2A */ 3625319435Sslm U8 ConnectorName[4]; /* 0x2C */ 3626319435Sslm U32 Reserved4; /* 0x30 */ 3627319435Sslm U32 Reserved5; /* 0x34 */ 3628319435Sslm} MPI26_CONFIG_PAGE_PCIEDEV_0, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIEDEV_0, 3629319435Sslm Mpi26PCIeDevicePage0_t, MPI2_POINTER pMpi26PCIeDevicePage0_t; 3630319435Sslm 3631319435Sslm#define MPI26_PCIEDEVICE0_PAGEVERSION (0x01) 3632319435Sslm 3633319435Sslm/* values for PCIe Device Page 0 AccessStatus field */ 3634319435Sslm#define MPI26_PCIEDEV0_ASTATUS_NO_ERRORS (0x00) 3635319435Sslm#define MPI26_PCIEDEV0_ASTATUS_NEEDS_INITIALIZATION (0x04) 3636319435Sslm#define MPI26_PCIEDEV0_ASTATUS_CAPABILITY_FAILED (0x02) 3637319435Sslm#define MPI26_PCIEDEV0_ASTATUS_DEVICE_BLOCKED (0x07) 3638319435Sslm#define MPI26_PCIEDEV0_ASTATUS_MEMORY_SPACE_ACCESS_FAILED (0x08) 3639319435Sslm#define MPI26_PCIEDEV0_ASTATUS_UNSUPPORTED_DEVICE (0x09) 3640319435Sslm#define MPI26_PCIEDEV0_ASTATUS_MSIX_REQUIRED (0x0A) 3641319435Sslm#define MPI26_PCIEDEV0_ASTATUS_UNKNOWN (0x10) 3642319435Sslm 3643319435Sslm#define MPI26_PCIEDEV0_ASTATUS_NVME_READY_TIMEOUT (0x30) 3644319435Sslm#define MPI26_PCIEDEV0_ASTATUS_NVME_DEVCFG_UNSUPPORTED (0x31) 3645319435Sslm#define MPI26_PCIEDEV0_ASTATUS_NVME_IDENTIFY_FAILED (0x32) 3646319435Sslm#define MPI26_PCIEDEV0_ASTATUS_NVME_QCONFIG_FAILED (0x33) 3647319435Sslm#define MPI26_PCIEDEV0_ASTATUS_NVME_QCREATION_FAILED (0x34) 3648319435Sslm#define MPI26_PCIEDEV0_ASTATUS_NVME_EVENTCFG_FAILED (0x35) 3649319435Sslm#define MPI26_PCIEDEV0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED (0x36) 3650319435Sslm#define MPI26_PCIEDEV0_ASTATUS_NVME_IDLE_TIMEOUT (0x37) 3651319435Sslm#define MPI26_PCIEDEV0_ASTATUS_NVME_FAILURE_STATUS (0x38) 3652319435Sslm 3653319435Sslm#define MPI26_PCIEDEV0_ASTATUS_INIT_FAIL_MAX (0x3F) 3654319435Sslm 3655319435Sslm/* see mpi2_pci.h for the MPI26_PCIE_DEVINFO_ defines used for the DeviceInfo field */ 3656319435Sslm 3657319435Sslm/* values for PCIe Device Page 0 Flags field */ 3658319435Sslm#define MPI26_PCIEDEV0_FLAGS_UNAUTHORIZED_DEVICE (0x8000) 3659319435Sslm#define MPI26_PCIEDEV0_FLAGS_ENABLED_FAST_PATH (0x4000) 3660319435Sslm#define MPI26_PCIEDEV0_FLAGS_FAST_PATH_CAPABLE (0x2000) 3661319435Sslm#define MPI26_PCIEDEV0_FLAGS_ASYNCHRONOUS_NOTIFICATION (0x0400) 3662319435Sslm#define MPI26_PCIEDEV0_FLAGS_ATA_SW_PRESERVATION (0x0200) 3663319435Sslm#define MPI26_PCIEDEV0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 3664319435Sslm#define MPI26_PCIEDEV0_FLAGS_ATA_48BIT_LBA_SUPPORTED (0x0080) 3665319435Sslm#define MPI26_PCIEDEV0_FLAGS_ATA_SMART_SUPPORTED (0x0040) 3666319435Sslm#define MPI26_PCIEDEV0_FLAGS_ATA_NCQ_SUPPORTED (0x0020) 3667319435Sslm#define MPI26_PCIEDEV0_FLAGS_ATA_FUA_SUPPORTED (0x0010) 3668319435Sslm#define MPI26_PCIEDEV0_FLAGS_ENCL_LEVEL_VALID (0x0002) 3669319435Sslm#define MPI26_PCIEDEV0_FLAGS_DEVICE_PRESENT (0x0001) 3670319435Sslm 3671319435Sslm/* values for PCIe Device Page 0 SupportedLinkRates field */ 3672319435Sslm#define MPI26_PCIEDEV0_LINK_RATE_16_0_SUPPORTED (0x08) 3673319435Sslm#define MPI26_PCIEDEV0_LINK_RATE_8_0_SUPPORTED (0x04) 3674319435Sslm#define MPI26_PCIEDEV0_LINK_RATE_5_0_SUPPORTED (0x02) 3675319435Sslm#define MPI26_PCIEDEV0_LINK_RATE_2_5_SUPPORTED (0x01) 3676319435Sslm 3677319435Sslm/* use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3678319435Sslm 3679319435Sslm 3680319435Sslm/* PCIe Device Page 2 */ 3681319435Sslm 3682319435Sslmtypedef struct _MPI26_CONFIG_PAGE_PCIEDEV_2 3683319435Sslm{ 3684319435Sslm MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3685319435Sslm U16 DevHandle; /* 0x08 */ 3686319435Sslm U16 Reserved1; /* 0x0A */ 3687319435Sslm U32 MaximumDataTransferSize;/* 0x0C */ 3688319435Sslm U32 Capabilities; /* 0x10 */ 3689319435Sslm U32 Reserved2; /* 0x14 */ 3690319435Sslm} MPI26_CONFIG_PAGE_PCIEDEV_2, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIEDEV_2, 3691319435Sslm Mpi26PCIeDevicePage2_t, MPI2_POINTER pMpi26PCIeDevicePage2_t; 3692319435Sslm 3693319435Sslm#define MPI26_PCIEDEVICE2_PAGEVERSION (0x00) 3694319435Sslm 3695319435Sslm/* defines for PCIe Device Page 2 Capabilities field */ 3696319435Sslm#define MPI26_PCIEDEV2_CAP_SGL_FORMAT (0x00000004) 3697319435Sslm#define MPI26_PCIEDEV2_CAP_BIT_BUCKET_SUPPORT (0x00000002) 3698319435Sslm#define MPI26_PCIEDEV2_CAP_SGL_SUPPORT (0x00000001) 3699319435Sslm 3700319435Sslm 3701319435Sslm/**************************************************************************** 3702319435Sslm* PCIe Link Config Pages (MPI v2.6 and later) 3703319435Sslm****************************************************************************/ 3704319435Sslm 3705319435Sslm/* PCIe Link Page 1 */ 3706319435Sslm 3707319435Sslmtypedef struct _MPI26_CONFIG_PAGE_PCIELINK_1 3708319435Sslm{ 3709319435Sslm MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3710319435Sslm U8 Link; /* 0x08 */ 3711319435Sslm U8 Reserved1; /* 0x09 */ 3712319435Sslm U16 Reserved2; /* 0x0A */ 3713319435Sslm U32 CorrectableErrorCount; /* 0x0C */ 3714319435Sslm U16 NonFatalErrorCount; /* 0x10 */ 3715319435Sslm U16 Reserved3; /* 0x12 */ 3716319435Sslm U16 FatalErrorCount; /* 0x14 */ 3717319435Sslm U16 Reserved4; /* 0x16 */ 3718319435Sslm} MPI26_CONFIG_PAGE_PCIELINK_1, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIELINK_1, 3719319435Sslm Mpi26PcieLinkPage1_t, MPI2_POINTER pMpi26PcieLinkPage1_t; 3720319435Sslm 3721319435Sslm#define MPI26_PCIELINK1_PAGEVERSION (0x00) 3722319435Sslm 3723319435Sslm/* PCIe Link Page 2 */ 3724319435Sslm 3725319435Sslmtypedef struct _MPI26_PCIELINK2_LINK_EVENT 3726319435Sslm{ 3727319435Sslm U8 LinkEventCode; /* 0x00 */ 3728319435Sslm U8 Reserved1; /* 0x01 */ 3729319435Sslm U16 Reserved2; /* 0x02 */ 3730319435Sslm U32 LinkEventInfo; /* 0x04 */ 3731319435Sslm} MPI26_PCIELINK2_LINK_EVENT, MPI2_POINTER PTR_MPI26_PCIELINK2_LINK_EVENT, 3732319435Sslm Mpi26PcieLink2LinkEvent_t, MPI2_POINTER pMpi26PcieLink2LinkEvent_t; 3733319435Sslm 3734319435Sslm/* use MPI26_PCIELINK3_EVTCODE_ for the LinkEventCode field */ 3735319435Sslm 3736319435Sslm 3737319435Sslm/* 3738319435Sslm * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3739319435Sslm * one and check the value returned for NumLinkEvents at runtime. 3740319435Sslm */ 3741319435Sslm#ifndef MPI26_PCIELINK2_LINK_EVENT_MAX 3742319435Sslm#define MPI26_PCIELINK2_LINK_EVENT_MAX (1) 3743319435Sslm#endif 3744319435Sslm 3745319435Sslmtypedef struct _MPI26_CONFIG_PAGE_PCIELINK_2 3746319435Sslm{ 3747319435Sslm MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3748319435Sslm U8 Link; /* 0x08 */ 3749319435Sslm U8 Reserved1; /* 0x09 */ 3750319435Sslm U16 Reserved2; /* 0x0A */ 3751319435Sslm U8 NumLinkEvents; /* 0x0C */ 3752319435Sslm U8 Reserved3; /* 0x0D */ 3753319435Sslm U16 Reserved4; /* 0x0E */ 3754319435Sslm MPI26_PCIELINK2_LINK_EVENT LinkEvent[MPI26_PCIELINK2_LINK_EVENT_MAX]; /* 0x10 */ 3755319435Sslm} MPI26_CONFIG_PAGE_PCIELINK_2, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIELINK_2, 3756319435Sslm Mpi26PcieLinkPage2_t, MPI2_POINTER pMpi26PcieLinkPage2_t; 3757319435Sslm 3758319435Sslm#define MPI26_PCIELINK2_PAGEVERSION (0x00) 3759319435Sslm 3760319435Sslm 3761319435Sslm/* PCIe Link Page 3 */ 3762319435Sslm 3763319435Sslmtypedef struct _MPI26_PCIELINK3_LINK_EVENT_CONFIG 3764319435Sslm{ 3765319435Sslm U8 LinkEventCode; /* 0x00 */ 3766319435Sslm U8 Reserved1; /* 0x01 */ 3767319435Sslm U16 Reserved2; /* 0x02 */ 3768319435Sslm U8 CounterType; /* 0x04 */ 3769319435Sslm U8 ThresholdWindow; /* 0x05 */ 3770319435Sslm U8 TimeUnits; /* 0x06 */ 3771319435Sslm U8 Reserved3; /* 0x07 */ 3772319435Sslm U32 EventThreshold; /* 0x08 */ 3773319435Sslm U16 ThresholdFlags; /* 0x0C */ 3774319435Sslm U16 Reserved4; /* 0x0E */ 3775319435Sslm} MPI26_PCIELINK3_LINK_EVENT_CONFIG, MPI2_POINTER PTR_MPI26_PCIELINK3_LINK_EVENT_CONFIG, 3776319435Sslm Mpi26PcieLink3LinkEventConfig_t, MPI2_POINTER pMpi26PcieLink3LinkEventConfig_t; 3777319435Sslm 3778319435Sslm/* values for LinkEventCode field */ 3779319435Sslm#define MPI26_PCIELINK3_EVTCODE_NO_EVENT (0x00) 3780319435Sslm#define MPI26_PCIELINK3_EVTCODE_CORRECTABLE_ERROR_RECEIVED (0x01) 3781319435Sslm#define MPI26_PCIELINK3_EVTCODE_NON_FATAL_ERROR_RECEIVED (0x02) 3782319435Sslm#define MPI26_PCIELINK3_EVTCODE_FATAL_ERROR_RECEIVED (0x03) 3783319435Sslm#define MPI26_PCIELINK3_EVTCODE_DATA_LINK_ERROR_DETECTED (0x04) 3784319435Sslm#define MPI26_PCIELINK3_EVTCODE_TRANSACTION_LAYER_ERROR_DETECTED (0x05) 3785319435Sslm#define MPI26_PCIELINK3_EVTCODE_TLP_ECRC_ERROR_DETECTED (0x06) 3786319435Sslm#define MPI26_PCIELINK3_EVTCODE_POISONED_TLP (0x07) 3787319435Sslm#define MPI26_PCIELINK3_EVTCODE_RECEIVED_NAK_DLLP (0x08) 3788319435Sslm#define MPI26_PCIELINK3_EVTCODE_SENT_NAK_DLLP (0x09) 3789319435Sslm#define MPI26_PCIELINK3_EVTCODE_LTSSM_RECOVERY_STATE (0x0A) 3790319435Sslm#define MPI26_PCIELINK3_EVTCODE_LTSSM_RXL0S_STATE (0x0B) 3791319435Sslm#define MPI26_PCIELINK3_EVTCODE_LTSSM_TXL0S_STATE (0x0C) 3792319435Sslm#define MPI26_PCIELINK3_EVTCODE_LTSSM_L1_STATE (0x0D) 3793319435Sslm#define MPI26_PCIELINK3_EVTCODE_LTSSM_DISABLED_STATE (0x0E) 3794319435Sslm#define MPI26_PCIELINK3_EVTCODE_LTSSM_HOT_RESET_STATE (0x0F) 3795319435Sslm#define MPI26_PCIELINK3_EVTCODE_SYSTEM_ERROR (0x10) 3796319435Sslm#define MPI26_PCIELINK3_EVTCODE_DECODE_ERROR (0x11) 3797319435Sslm#define MPI26_PCIELINK3_EVTCODE_DISPARITY_ERROR (0x12) 3798319435Sslm 3799319435Sslm/* values for the CounterType field */ 3800319435Sslm#define MPI26_PCIELINK3_COUNTER_TYPE_WRAPPING (0x00) 3801319435Sslm#define MPI26_PCIELINK3_COUNTER_TYPE_SATURATING (0x01) 3802319435Sslm#define MPI26_PCIELINK3_COUNTER_TYPE_PEAK_VALUE (0x02) 3803319435Sslm 3804319435Sslm/* values for the TimeUnits field */ 3805319435Sslm#define MPI26_PCIELINK3_TM_UNITS_10_MICROSECONDS (0x00) 3806319435Sslm#define MPI26_PCIELINK3_TM_UNITS_100_MICROSECONDS (0x01) 3807319435Sslm#define MPI26_PCIELINK3_TM_UNITS_1_MILLISECOND (0x02) 3808319435Sslm#define MPI26_PCIELINK3_TM_UNITS_10_MILLISECONDS (0x03) 3809319435Sslm 3810319435Sslm/* values for the ThresholdFlags field */ 3811319435Sslm#define MPI26_PCIELINK3_TFLAGS_EVENT_NOTIFY (0x0001) 3812319435Sslm 3813319435Sslm/* 3814319435Sslm * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3815319435Sslm * one and check the value returned for NumLinkEvents at runtime. 3816319435Sslm */ 3817319435Sslm#ifndef MPI26_PCIELINK3_LINK_EVENT_MAX 3818319435Sslm#define MPI26_PCIELINK3_LINK_EVENT_MAX (1) 3819319435Sslm#endif 3820319435Sslm 3821319435Sslmtypedef struct _MPI26_CONFIG_PAGE_PCIELINK_3 3822319435Sslm{ 3823319435Sslm MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3824319435Sslm U8 Link; /* 0x08 */ 3825319435Sslm U8 Reserved1; /* 0x09 */ 3826319435Sslm U16 Reserved2; /* 0x0A */ 3827319435Sslm U8 NumLinkEvents; /* 0x0C */ 3828319435Sslm U8 Reserved3; /* 0x0D */ 3829319435Sslm U16 Reserved4; /* 0x0E */ 3830319435Sslm MPI26_PCIELINK3_LINK_EVENT_CONFIG LinkEventConfig[MPI26_PCIELINK3_LINK_EVENT_MAX]; /* 0x10 */ 3831319435Sslm} MPI26_CONFIG_PAGE_PCIELINK_3, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIELINK_3, 3832319435Sslm Mpi26PcieLinkPage3_t, MPI2_POINTER pMpi26PcieLinkPage3_t; 3833319435Sslm 3834319435Sslm#define MPI26_PCIELINK3_PAGEVERSION (0x00) 3835319435Sslm 3836319435Sslm 3837319435Sslm#endif 3838319435Sslm 3839