if_mn.c revision 78254
1/* 2 * ---------------------------------------------------------------------------- 3 * "THE BEER-WARE LICENSE" (Revision 42): 4 * <phk@FreeBSD.org> wrote this file. As long as you retain this notice you 5 * can do whatever you want with this stuff. If we meet some day, and you think 6 * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp 7 * ---------------------------------------------------------------------------- 8 * 9 * $Id: if_mn.c,v 1.1 1999/02/01 13:06:40 phk Exp $ 10 * 11 * Driver for Siemens reference design card "Easy321-R1". 12 * 13 * This card contains a FALC54 E1/T1 framer and a MUNICH32X 32-channel HDLC 14 * controller. 15 * 16 * The driver supports E1 mode with up to 31 channels. We send CRC4 but don't 17 * check it coming in. 18 * 19 * The FALC54 and MUNICH32X have far too many registers and weird modes for 20 * comfort, so I have not bothered typing it all into a "fooreg.h" file, 21 * you will (badly!) need the documentation anyway if you want to mess with 22 * this gadget. 23 * 24 * $FreeBSD: head/sys/pci/if_mn.c 78254 2001-06-15 07:39:12Z peter $ 25 */ 26 27/* 28 * Stuff to describe the MUNIC32X and FALC54 chips. 29 */ 30 31#define M32_CHAN 32 /* We have 32 channels */ 32#define M32_TS 32 /* We have 32 timeslots */ 33 34#define NG_MN_NODE_TYPE "mn" 35 36#include <sys/param.h> 37#include <sys/kernel.h> 38#include <sys/sysctl.h> 39#include <sys/bus.h> 40#include <sys/mbuf.h> 41#include <sys/systm.h> 42#include <sys/malloc.h> 43 44#include <pci/pcireg.h> 45#include <pci/pcivar.h> 46#include "pci_if.h" 47 48#include <machine/bus.h> 49#include <machine/resource.h> 50 51#include <sys/rman.h> 52 53#include <vm/vm.h> 54#include <vm/pmap.h> 55 56#include <netgraph/ng_message.h> 57#include <netgraph/netgraph.h> 58 59 60static int mn_maxlatency = 1000; 61SYSCTL_INT(_debug, OID_AUTO, mn_maxlatency, CTLFLAG_RW, 62 &mn_maxlatency, 0, 63 "The number of milliseconds a packet is allowed to spend in the output queue. " 64 "If the output queue is longer than this number of milliseconds when the packet " 65 "arrives for output, the packet will be dropped." 66); 67 68#ifndef NMN 69/* Most machines don't support more than 4 busmaster PCI slots, if even that many */ 70#define NMN 4 71#endif 72 73/* From: PEB 20321 data sheet, p187, table 22 */ 74struct m32xreg { 75 u_int32_t conf, cmd, stat, imask; 76 u_int32_t fill10, piqba, piql, fill1c; 77 u_int32_t mode1, mode2, ccba, txpoll; 78 u_int32_t tiqba, tiql, riqba, riql; 79 u_int32_t lconf, lccba, fill48, ltran; 80 u_int32_t ltiqba, ltiql, lriqba, lriql; 81 u_int32_t lreg0, lreg1, lreg2, lreg3; 82 u_int32_t lreg4, lreg5, lre6, lstat; 83 u_int32_t gpdir, gpdata, gpod, fill8c; 84 u_int32_t ssccon, sscbr, ssctb, sscrb; 85 u_int32_t ssccse, sscim, fillab, fillac; 86 u_int32_t iomcon1, iomcon2, iomstat, fillbc; 87 u_int32_t iomcit0, iomcit1, iomcir0, iomcir1; 88 u_int32_t iomtmo, iomrmo, filld8, filldc; 89 u_int32_t mbcmd, mbdata1, mbdata2, mbdata3; 90 u_int32_t mbdata4, mbdata5, mbdata6, mbdata7; 91}; 92 93/* From: PEB 2254 data sheet, p80, table 10 */ 94struct f54wreg { 95 u_int16_t xfifo; 96 u_int8_t cmdr, mode, rah1, rah2, ral1, ral2; 97 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 98 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 99 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 100 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 101 u_int8_t test1, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr3; 102 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 103 u_int8_t lim2, fill39[7]; 104 u_int8_t fill40[8]; 105 u_int8_t fill48[8]; 106 u_int8_t fill50[8]; 107 u_int8_t fill58[8]; 108 u_int8_t dec, fill61, test2, fill63[5]; 109 u_int8_t fill68[8]; 110 u_int8_t xs[16]; 111}; 112 113/* From: PEB 2254 data sheet, p117, table 10 */ 114struct f54rreg { 115 u_int16_t rfifo; 116 u_int8_t fill2, mode, rah1, rah2, ral1, ral2; 117 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 118 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 119 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 120 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 121 u_int8_t test, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr13; 122 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 123 u_int8_t lim2, fill39[7]; 124 u_int8_t fill40[8]; 125 u_int8_t fill48[4], frs0, frs1, rsw, rsp; 126 u_int16_t fec, cvc, cec1, ebc; 127 u_int16_t cec2, cec3; 128 u_int8_t rsa4, rsa5, rsa6, rsa7; 129 u_int8_t rsa8, rsa6s, tsr0, tsr1, sis, rsis; 130 u_int16_t rbc; 131 u_int8_t isr0, isr1, isr2, isr3, fill6c, fill6d, gis, vstr; 132 u_int8_t rs[16]; 133}; 134 135/* Transmit & receive descriptors */ 136struct trxd { 137 u_int32_t flags; 138 vm_offset_t next; 139 vm_offset_t data; 140 u_int32_t status; /* only used for receive */ 141 struct mbuf *m; /* software use only */ 142 struct trxd *vnext; /* software use only */ 143}; 144 145/* Channel specification */ 146struct cspec { 147 u_int32_t flags; 148 vm_offset_t rdesc; 149 vm_offset_t tdesc; 150 u_int32_t itbs; 151}; 152 153struct m32_mem { 154 vm_offset_t csa; 155 u_int32_t ccb; 156 u_int32_t reserve1[2]; 157 u_int32_t ts[M32_TS]; 158 struct cspec cs[M32_CHAN]; 159 vm_offset_t crxd[M32_CHAN]; 160 vm_offset_t ctxd[M32_CHAN]; 161}; 162 163struct softc; 164struct sockaddr; 165struct rtentry; 166 167static int mn_probe (device_t self); 168static int mn_attach (device_t self); 169static void mn_create_channel(struct softc *sc, int chan); 170static int mn_reset(struct softc *sc); 171static struct trxd * mn_alloc_desc(void); 172static void mn_free_desc(struct trxd *dp); 173static void mn_intr(void *xsc); 174static u_int32_t mn_parse_ts(const char *s, int *nbit); 175#ifdef notyet 176static void m32_dump(struct softc *sc); 177static void f54_dump(struct softc *sc); 178static void mn_fmt_ts(char *p, u_int32_t ts); 179#endif /* notyet */ 180static void f54_init(struct softc *sc); 181 182static ng_constructor_t ngmn_constructor; 183static ng_rcvmsg_t ngmn_rcvmsg; 184static ng_shutdown_t ngmn_shutdown; 185static ng_newhook_t ngmn_newhook; 186static ng_connect_t ngmn_connect; 187static ng_rcvdata_t ngmn_rcvdata; 188static ng_disconnect_t ngmn_disconnect; 189 190static struct ng_type mntypestruct = { 191 NG_ABI_VERSION, 192 NG_MN_NODE_TYPE, 193 NULL, 194 ngmn_constructor, 195 ngmn_rcvmsg, 196 ngmn_shutdown, 197 ngmn_newhook, 198 NULL, 199 ngmn_connect, 200 ngmn_rcvdata, 201 ngmn_disconnect, 202 NULL 203}; 204 205static MALLOC_DEFINE(M_MN, "mn", "Mx driver related"); 206 207#define NIQB 64 208 209struct schan { 210 enum {DOWN, UP} state; 211 struct softc *sc; 212 int chan; 213 u_int32_t ts; 214 char name[8]; 215 struct trxd *r1, *rl; 216 struct trxd *x1, *xl; 217 hook_p hook; 218 219 time_t last_recv; 220 time_t last_rxerr; 221 time_t last_xmit; 222 223 u_long rx_error; 224 225 u_long short_error; 226 u_long crc_error; 227 u_long dribble_error; 228 u_long long_error; 229 u_long abort_error; 230 u_long overflow_error; 231 232 int last_error; 233 int prev_error; 234 235 u_long tx_pending; 236 u_long tx_limit; 237}; 238 239enum framing {WHOKNOWS, E1, E1U, T1, T1U}; 240 241struct softc { 242 int unit; 243 device_t dev; 244 struct resource *irq; 245 void *intrhand; 246 enum framing framing; 247 int nhooks; 248 void *m0v, *m1v; 249 vm_offset_t m0p, m1p; 250 struct m32xreg *m32x; 251 struct f54wreg *f54w; 252 struct f54rreg *f54r; 253 struct m32_mem m32_mem; 254 u_int32_t tiqb[NIQB]; 255 u_int32_t riqb[NIQB]; 256 u_int32_t piqb[NIQB]; 257 u_int32_t ltiqb[NIQB]; 258 u_int32_t lriqb[NIQB]; 259 char name[8]; 260 u_int32_t falc_irq, falc_state, framer_state; 261 struct schan *ch[M32_CHAN]; 262 char nodename[NG_NODELEN + 1]; 263 node_p node; 264 265 u_long cnt_fec; 266 u_long cnt_cvc; 267 u_long cnt_cec1; 268 u_long cnt_ebc; 269 u_long cnt_cec2; 270 u_long cnt_cec3; 271 u_long cnt_rbc; 272}; 273 274static int 275ngmn_constructor(node_p node) 276{ 277 278 return (EINVAL); 279} 280 281static int 282ngmn_shutdown(node_p nodep) 283{ 284 285 return (EINVAL); 286} 287 288static void 289ngmn_config(node_p node, char *set, char *ret) 290{ 291 struct softc *sc; 292 enum framing wframing; 293 294 sc = NG_NODE_PRIVATE(node); 295 296 if (set != NULL) { 297 if (!strncmp(set, "line ", 5)) { 298 wframing = sc->framing; 299 if (!strcmp(set, "line e1")) { 300 wframing = E1; 301 } else if (!strcmp(set, "line e1u")) { 302 wframing = E1U; 303 } else { 304 strcat(ret, "ENOGROK\n"); 305 return; 306 } 307 if (wframing == sc->framing) 308 return; 309 if (sc->nhooks > 0) { 310 sprintf(ret, "Cannot change line when %d hooks open\n", sc->nhooks); 311 return; 312 } 313 sc->framing = wframing; 314#if 1 315 f54_init(sc); 316#else 317 mn_reset(sc); 318#endif 319 } else { 320 printf("%s CONFIG SET [%s]\n", sc->nodename, set); 321 strcat(ret, "ENOGROK\n"); 322 return; 323 } 324 } 325 326} 327 328static int 329ngmn_rcvmsg(node_p node, item_p item, hook_p lasthook) 330{ 331 struct softc *sc; 332 struct ng_mesg *resp = NULL; 333 struct schan *sch; 334 char *s, *r; 335 int pos, i; 336 struct ng_mesg *msg; 337 338 NGI_GET_MSG(item, msg); 339 sc = NG_NODE_PRIVATE(node); 340 341 if (msg->header.typecookie != NGM_GENERIC_COOKIE) { 342 NG_FREE_ITEM(item); 343 NG_FREE_MSG(msg); 344 return (EINVAL); 345 } 346 347 if (msg->header.cmd != NGM_TEXT_CONFIG && 348 msg->header.cmd != NGM_TEXT_STATUS) { 349 NG_FREE_ITEM(item); 350 NG_FREE_MSG(msg); 351 return (EINVAL); 352 } 353 354 NG_MKRESPONSE(resp, msg, sizeof(struct ng_mesg) + NG_TEXTRESPONSE, 355 M_NOWAIT); 356 if (resp == NULL) { 357 NG_FREE_ITEM(item); 358 NG_FREE_MSG(msg); 359 return (ENOMEM); 360 } 361 362 if (msg->header.arglen) 363 s = (char *)msg->data; 364 else 365 s = NULL; 366 r = (char *)resp->data; 367 *r = '\0'; 368 369 if (msg->header.cmd == NGM_TEXT_CONFIG) { 370 ngmn_config(node, s, r); 371 resp->header.arglen = strlen(r) + 1; 372 FREE(msg, M_NETGRAPH); 373 return (0); 374 } 375 pos = 0; 376 pos += sprintf(pos + r,"Framer status %b;\n", sc->framer_state, "\20" 377 "\40LOS\37AIS\36LFA\35RRA" 378 "\34AUXP\33NMF\32LMFA\31frs0.0" 379 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 380 "\24TS16LFA\23frs1.2\22XLS\21XLO" 381 "\20RS1\17rsw.6\16RRA\15RY0" 382 "\14RY1\13RY2\12RY3\11RY4" 383 "\10SI1\7SI2\6rsp.5\5rsp.4" 384 "\4rsp.3\3RSIF\2RS13\1RS15"); 385 pos += sprintf(pos + r," Framing errors: %lu", sc->cnt_fec); 386 pos += sprintf(pos + r," Code Violations: %lu\n", sc->cnt_cvc); 387 388 pos += sprintf(pos + r," Falc State %b;\n", sc->falc_state, "\20" 389 "\40LOS\37AIS\36LFA\35RRA" 390 "\34AUXP\33NMF\32LMFA\31frs0.0" 391 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 392 "\24TS16LFA\23frs1.2\22XLS\21XLO" 393 "\20RS1\17rsw.6\16RRA\15RY0" 394 "\14RY1\13RY2\12RY3\11RY4" 395 "\10SI1\7SI2\6rsp.5\5rsp.4" 396 "\4rsp.3\3RSIF\2RS13\1RS15"); 397 pos += sprintf(pos + r, " Falc IRQ %b\n", sc->falc_irq, "\20" 398 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 399 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 400 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 401 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 402 for (i = 0; i < M32_CHAN; i++) { 403 if (!sc->ch[i]) 404 continue; 405 sch = sc->ch[i]; 406 407 pos += sprintf(r + pos, " Chan %d <%s> ", 408 i, NG_HOOK_NAME(sch->hook)); 409 410 pos += sprintf(r + pos, " Last Rx: "); 411 if (sch->last_recv) 412 pos += sprintf(r + pos, "%lu s", 413 (unsigned long)(time_second - sch->last_recv)); 414 else 415 pos += sprintf(r + pos, "never"); 416 417 pos += sprintf(r + pos, ", last RxErr: "); 418 if (sch->last_rxerr) 419 pos += sprintf(r + pos, "%lu s", 420 (unsigned long)(time_second - sch->last_rxerr)); 421 else 422 pos += sprintf(r + pos, "never"); 423 424 pos += sprintf(r + pos, ", last Tx: "); 425 if (sch->last_xmit) 426 pos += sprintf(r + pos, "%lu s\n", 427 (unsigned long)(time_second - sch->last_xmit)); 428 else 429 pos += sprintf(r + pos, "never\n"); 430 431 pos += sprintf(r + pos, " RX error(s) %lu", sch->rx_error); 432 pos += sprintf(r + pos, " Short: %lu", sch->short_error); 433 pos += sprintf(r + pos, " CRC: %lu", sch->crc_error); 434 pos += sprintf(r + pos, " Mod8: %lu", sch->dribble_error); 435 pos += sprintf(r + pos, " Long: %lu", sch->long_error); 436 pos += sprintf(r + pos, " Abort: %lu", sch->abort_error); 437 pos += sprintf(r + pos, " Overflow: %lu\n", sch->overflow_error); 438 439 pos += sprintf(r + pos, " Last error: %b Prev error: %b\n", 440 sch->last_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN", 441 sch->prev_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN"); 442 pos += sprintf(r + pos, " Xmit bytes pending %ld\n", 443 sch->tx_pending); 444 } 445 resp->header.arglen = pos + 1; 446 447 /* Take care of synchronous response, if any */ 448 NG_RESPOND_MSG(i, node, item, resp); 449 NG_FREE_MSG(msg); 450 return (0); 451} 452 453static int 454ngmn_newhook(node_p node, hook_p hook, const char *name) 455{ 456 u_int32_t ts, chan; 457 struct softc *sc; 458 int nbit; 459 460 sc = NG_NODE_PRIVATE(node); 461 462 if (name[0] != 't' || name[1] != 's') 463 return (EINVAL); 464 465 ts = mn_parse_ts(name + 2, &nbit); 466 printf("%d bits %x\n", nbit, ts); 467 if (sc->framing == E1 && (ts & 1)) 468 return (EINVAL); 469 if (sc->framing == E1U && nbit != 32) 470 return (EINVAL); 471 if (ts == 0) 472 return (EINVAL); 473 if (sc->framing == E1) 474 chan = ffs(ts) - 1; 475 else 476 chan = 1; 477 if (!sc->ch[chan]) 478 mn_create_channel(sc, chan); 479 else if (sc->ch[chan]->state == UP) 480 return (EBUSY); 481 sc->ch[chan]->ts = ts; 482 sc->ch[chan]->hook = hook; 483 sc->ch[chan]->tx_limit = nbit * 8; 484 NG_HOOK_SET_PRIVATE(hook, sc->ch[chan]); 485 sc->nhooks++; 486 return(0); 487} 488 489 490static struct trxd *mn_desc_free; 491 492static struct trxd * 493mn_alloc_desc(void) 494{ 495 struct trxd *dp; 496 497 dp = mn_desc_free; 498 if (dp) 499 mn_desc_free = dp->vnext; 500 else 501 dp = (struct trxd *)malloc(sizeof *dp, M_MN, M_NOWAIT); 502 return (dp); 503} 504 505static void 506mn_free_desc(struct trxd *dp) 507{ 508 dp->vnext = mn_desc_free; 509 mn_desc_free = dp; 510} 511 512static u_int32_t 513mn_parse_ts(const char *s, int *nbit) 514{ 515 unsigned r; 516 int i, j; 517 char *p; 518 519 r = 0; 520 j = -1; 521 *nbit = 0; 522 while(*s) { 523 i = strtol(s, &p, 0); 524 if (i < 0 || i > 31) 525 return (0); 526 while (j != -1 && j < i) { 527 r |= 1 << j++; 528 (*nbit)++; 529 } 530 j = -1; 531 r |= 1 << i; 532 (*nbit)++; 533 if (*p == ',') { 534 s = p + 1; 535 continue; 536 } else if (*p == '-') { 537 j = i + 1; 538 s = p + 1; 539 continue; 540 } else if (!*p) { 541 break; 542 } else { 543 return (0); 544 } 545 } 546 return (r); 547} 548 549#ifdef notyet 550static void 551mn_fmt_ts(char *p, u_int32_t ts) 552{ 553 char *s; 554 int j; 555 556 s = ""; 557 ts &= 0xffffffff; 558 for (j = 0; j < 32; j++) { 559 if (!(ts & (1 << j))) 560 continue; 561 sprintf(p, "%s%d", s, j); 562 p += strlen(p); 563 s = ","; 564 if (!(ts & (1 << (j+1)))) 565 continue; 566 for (; j < 32; j++) 567 if (!(ts & (1 << (j+1)))) 568 break; 569 sprintf(p, "-%d", j); 570 p += strlen(p); 571 s = ","; 572 } 573} 574#endif /* notyet */ 575 576/* 577 * OUTPUT 578 */ 579 580static int 581ngmn_rcvdata(hook_p hook, item_p item) 582{ 583 struct mbuf *m2; 584 struct trxd *dp, *dp2; 585 struct schan *sch; 586 struct softc *sc; 587 int chan, pitch, len; 588 struct mbuf *m; 589 590 sch = NG_HOOK_PRIVATE(hook); 591 sc = sch->sc; 592 chan = sch->chan; 593 594 if (sch->state != UP) { 595 NG_FREE_ITEM(item); 596 return (0); 597 } 598 NGI_GET_M(item, m); 599 if (sch->tx_pending + m->m_pkthdr.len > sch->tx_limit * mn_maxlatency) { 600 NG_FREE_M(m); 601 NG_FREE_ITEM(item); 602 return (0); 603 } 604 NG_FREE_ITEM(item); 605 pitch = 0; 606 m2 = m; 607 dp2 = sc->ch[chan]->xl; 608 len = m->m_pkthdr.len; 609 while (len) { 610 dp = mn_alloc_desc(); 611 if (!dp) { 612 pitch++; 613 m_freem(m); 614 sc->ch[chan]->xl = dp2; 615 dp = dp2->vnext; 616 while (dp) { 617 dp2 = dp->vnext; 618 mn_free_desc(dp); 619 dp = dp2; 620 } 621 sc->ch[chan]->xl->vnext = 0; 622 break; 623 } 624 dp->data = vtophys(m2->m_data); 625 dp->flags = m2->m_len << 16; 626 dp->flags += 1; 627 len -= m2->m_len; 628 dp->next = vtophys(dp); 629 dp->vnext = 0; 630 sc->ch[chan]->xl->next = vtophys(dp); 631 sc->ch[chan]->xl->vnext = dp; 632 sc->ch[chan]->xl = dp; 633 if (!len) { 634 dp->m = m; 635 dp->flags |= 0xc0000000; 636 dp2->flags &= ~0x40000000; 637 } else { 638 dp->m = 0; 639 m2 = m2->m_next; 640 } 641 } 642 if (pitch) 643 printf("%s%d: Short on mem, pitched %d packets\n", 644 sc->name, chan, pitch); 645 else { 646#if 0 647 printf("%d = %d + %d (%p)\n", 648 sch->tx_pending + m->m_pkthdr.len, 649 sch->tx_pending , m->m_pkthdr.len, m); 650#endif 651 sch->tx_pending += m->m_pkthdr.len; 652 sc->m32x->txpoll &= ~(1 << chan); 653 } 654 return (0); 655} 656 657/* 658 * OPEN 659 */ 660static int 661ngmn_connect(hook_p hook) 662{ 663 int i, nts, chan; 664 struct trxd *dp, *dp2; 665 struct mbuf *m; 666 struct softc *sc; 667 struct schan *sch; 668 u_int32_t u; 669 670 sch = NG_HOOK_PRIVATE(hook); 671 chan = sch->chan; 672 sc = sch->sc; 673 674 if (sch->state == UP) 675 return (0); 676 sch->state = UP; 677 678 /* Count and configure the timeslots for this channel */ 679 for (nts = i = 0; i < 32; i++) 680 if (sch->ts & (1 << i)) { 681 sc->m32_mem.ts[i] = 0x00ff00ff | 682 (chan << 24) | (chan << 8); 683 nts++; 684 } 685 686 /* Init the receiver & xmitter to HDLC */ 687 sc->m32_mem.cs[chan].flags = 0x80e90006; 688 /* Allocate two buffers per timeslot */ 689 if (nts == 32) 690 sc->m32_mem.cs[chan].itbs = 63; 691 else 692 sc->m32_mem.cs[chan].itbs = nts * 2; 693 694 /* Setup a transmit chain with one descriptor */ 695 /* XXX: we actually send a 1 byte packet */ 696 dp = mn_alloc_desc(); 697 MGETHDR(m, M_TRYWAIT, MT_DATA); 698 if (m == NULL) 699 return ENOBUFS; 700 m->m_pkthdr.len = 0; 701 dp->m = m; 702 dp->flags = 0xc0000000 + (1 << 16); 703 dp->next = vtophys(dp); 704 dp->vnext = 0; 705 dp->data = vtophys(sc->name); 706 sc->m32_mem.cs[chan].tdesc = vtophys(dp); 707 sc->ch[chan]->x1 = dp; 708 sc->ch[chan]->xl = dp; 709 710 /* Setup a receive chain with 5 + NTS descriptors */ 711 712 dp = mn_alloc_desc(); 713 m = NULL; 714 MGETHDR(m, M_TRYWAIT, MT_DATA); 715 if (m == NULL) { 716 mn_free_desc(dp); 717 return (ENOBUFS); 718 } 719 MCLGET(m, M_TRYWAIT); 720 if ((m->m_flags & M_EXT) == 0) { 721 mn_free_desc(dp); 722 m_freem(m); 723 return (ENOBUFS); 724 } 725 dp->m = m; 726 dp->data = vtophys(m->m_data); 727 dp->flags = 0x40000000; 728 dp->flags += 1600 << 16; 729 dp->next = vtophys(dp); 730 dp->vnext = 0; 731 sc->ch[chan]->rl = dp; 732 733 for (i = 0; i < (nts + 10); i++) { 734 dp2 = dp; 735 dp = mn_alloc_desc(); 736 m = NULL; 737 MGETHDR(m, M_TRYWAIT, MT_DATA); 738 if (m == NULL) { 739 mn_free_desc(dp); 740 m_freem(m); 741 return (ENOBUFS); 742 } 743 MCLGET(m, M_TRYWAIT); 744 if ((m->m_flags & M_EXT) == 0) { 745 mn_free_desc(dp); 746 m_freem(m); 747 return (ENOBUFS); 748 } 749 dp->m = m; 750 dp->data = vtophys(m->m_data); 751 dp->flags = 0x00000000; 752 dp->flags += 1600 << 16; 753 dp->next = vtophys(dp2); 754 dp->vnext = dp2; 755 } 756 sc->m32_mem.cs[chan].rdesc = vtophys(dp); 757 sc->ch[chan]->r1 = dp; 758 759 /* Initialize this channel */ 760 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 761 sc->m32x->cmd = 0x1; 762 DELAY(1000); 763 u = sc->m32x->stat; 764 if (!(u & 1)) 765 printf("%s: init chan %d stat %08x\n", sc->name, chan, u); 766 sc->m32x->stat = 1; 767 /* probably not at splnet, force outward queueing */ 768 NG_HOOK_FORCE_QUEUE(NG_HOOK_PEER(hook)); 769 770 return (0); 771} 772 773/* 774 * CLOSE 775 */ 776static int 777ngmn_disconnect(hook_p hook) 778{ 779 int chan, i; 780 struct softc *sc; 781 struct schan *sch; 782 struct trxd *dp, *dp2; 783 u_int32_t u; 784 785 sch = NG_HOOK_PRIVATE(hook); 786 chan = sch->chan; 787 sc = sch->sc; 788 789 if (sch->state == DOWN) 790 return (0); 791 sch->state = DOWN; 792 793 /* Set receiver & transmitter off */ 794 sc->m32_mem.cs[chan].flags = 0x80920006; 795 sc->m32_mem.cs[chan].itbs = 0; 796 797 /* free the timeslots */ 798 for (i = 0; i < 32; i++) 799 if (sc->ch[chan]->ts & (1 << i)) 800 sc->m32_mem.ts[i] = 0x20002000; 801 802 /* Initialize this channel */ 803 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 804 sc->m32x->cmd = 0x1; 805 DELAY(30); 806 u = sc->m32x->stat; 807 if (!(u & 1)) 808 printf("%s: zap chan %d stat %08x\n", sc->name, chan, u); 809 sc->m32x->stat = 1; 810 811 /* Free all receive descriptors and mbufs */ 812 for (dp = sc->ch[chan]->r1; dp ; dp = dp2) { 813 if (dp->m) 814 m_freem(dp->m); 815 sc->ch[chan]->r1 = dp2 = dp->vnext; 816 mn_free_desc(dp); 817 } 818 819 /* Free all transmit descriptors and mbufs */ 820 for (dp = sc->ch[chan]->x1; dp ; dp = dp2) { 821 if (dp->m) { 822 sc->ch[chan]->tx_pending -= dp->m->m_pkthdr.len; 823 m_freem(dp->m); 824 } 825 sc->ch[chan]->x1 = dp2 = dp->vnext; 826 mn_free_desc(dp); 827 } 828 sc->nhooks--; 829 return(0); 830} 831 832/* 833 * Create a new channel. 834 */ 835static void 836mn_create_channel(struct softc *sc, int chan) 837{ 838 struct schan *sch; 839 840 sch = sc->ch[chan] = (struct schan *)malloc(sizeof *sc->ch[chan], 841 M_MN, M_WAITOK | M_ZERO); 842 sch->sc = sc; 843 sch->state = DOWN; 844 sch->chan = chan; 845 sprintf(sch->name, "%s%d", sc->name, chan); 846 return; 847} 848 849#ifdef notyet 850/* 851 * Dump Munich32x state 852 */ 853static void 854m32_dump(struct softc *sc) 855{ 856 u_int32_t *tp4; 857 int i, j; 858 859 printf("mn%d: MUNICH32X dump\n", sc->unit); 860 tp4 = (u_int32_t *)sc->m0v; 861 for(j = 0; j < 64; j += 8) { 862 printf("%02x", j * sizeof *tp4); 863 for(i = 0; i < 8; i++) 864 printf(" %08x", tp4[i+j]); 865 printf("\n"); 866 } 867 for(j = 0; j < M32_CHAN; j++) { 868 if (!sc->ch[j]) 869 continue; 870 printf("CH%d: state %d ts %08x", 871 j, sc->ch[j]->state, sc->ch[j]->ts); 872 printf(" %08x %08x %08x %08x %08x %08x\n", 873 sc->m32_mem.cs[j].flags, 874 sc->m32_mem.cs[j].rdesc, 875 sc->m32_mem.cs[j].tdesc, 876 sc->m32_mem.cs[j].itbs, 877 sc->m32_mem.crxd[j], 878 sc->m32_mem.ctxd[j] ); 879 } 880} 881 882/* 883 * Dump Falch54 state 884 */ 885static void 886f54_dump(struct softc *sc) 887{ 888 u_int8_t *tp1; 889 int i, j; 890 891 printf("%s: FALC54 dump\n", sc->name); 892 tp1 = (u_int8_t *)sc->m1v; 893 for(j = 0; j < 128; j += 16) { 894 printf("%s: %02x |", sc->name, j * sizeof *tp1); 895 for(i = 0; i < 16; i++) 896 printf(" %02x", tp1[i+j]); 897 printf("\n"); 898 } 899} 900#endif /* notyet */ 901 902/* 903 * Init Munich32x 904 */ 905static void 906m32_init(struct softc *sc) 907{ 908 909 sc->m32x->conf = 0x00000000; 910 sc->m32x->mode1 = 0x81048000 + 1600; /* XXX: temp */ 911#if 1 912 sc->m32x->mode2 = 0x00000081; 913 sc->m32x->txpoll = 0xffffffff; 914#elif 1 915 sc->m32x->mode2 = 0x00000081; 916 sc->m32x->txpoll = 0xffffffff; 917#else 918 sc->m32x->mode2 = 0x00000101; 919#endif 920 sc->m32x->lconf = 0x6060009B; 921 sc->m32x->imask = 0x00000000; 922} 923 924/* 925 * Init the Falc54 926 */ 927static void 928f54_init(struct softc *sc) 929{ 930 sc->f54w->ipc = 0x07; 931 932 sc->f54w->xpm0 = 0xbd; 933 sc->f54w->xpm1 = 0x03; 934 sc->f54w->xpm2 = 0x00; 935 936 sc->f54w->imr0 = 0x18; /* RMB, CASC */ 937 sc->f54w->imr1 = 0x08; /* XMB */ 938 sc->f54w->imr2 = 0x00; 939 sc->f54w->imr3 = 0x38; /* LMFA16, AIS16, RA16 */ 940 sc->f54w->imr4 = 0x00; 941 942 sc->f54w->fmr0 = 0xf0; /* X: HDB3, R: HDB3 */ 943 sc->f54w->fmr1 = 0x0e; /* Send CRC4, 2Mbit, ECM */ 944 if (sc->framing == E1) 945 sc->f54w->fmr2 = 0x03; /* Auto Rem-Alarm, Auto resync */ 946 else if (sc->framing == E1U) 947 sc->f54w->fmr2 = 0x33; /* dais, rtm, Auto Rem-Alarm, Auto resync */ 948 949 sc->f54w->lim1 = 0xb0; /* XCLK=8kHz, .62V threshold */ 950 sc->f54w->pcd = 0x0a; 951 sc->f54w->pcr = 0x15; 952 sc->f54w->xsw = 0x9f; /* fmr4 */ 953 if (sc->framing == E1) 954 sc->f54w->xsp = 0x1c; /* fmr5 */ 955 else if (sc->framing == E1U) 956 sc->f54w->xsp = 0x3c; /* tt0, fmr5 */ 957 sc->f54w->xc0 = 0x07; 958 sc->f54w->xc1 = 0x3d; 959 sc->f54w->rc0 = 0x05; 960 sc->f54w->rc1 = 0x00; 961 sc->f54w->cmdr = 0x51; 962} 963 964static int 965mn_reset(struct softc *sc) 966{ 967 u_int32_t u; 968 int i; 969 970 sc->m32x->ccba = vtophys(&sc->m32_mem.csa); 971 sc->m32_mem.csa = vtophys(&sc->m32_mem.ccb); 972 973 bzero(sc->tiqb, sizeof sc->tiqb); 974 sc->m32x->tiqba = vtophys(&sc->tiqb); 975 sc->m32x->tiql = NIQB / 16 - 1; 976 977 bzero(sc->riqb, sizeof sc->riqb); 978 sc->m32x->riqba = vtophys(&sc->riqb); 979 sc->m32x->riql = NIQB / 16 - 1; 980 981 bzero(sc->ltiqb, sizeof sc->ltiqb); 982 sc->m32x->ltiqba = vtophys(&sc->ltiqb); 983 sc->m32x->ltiql = NIQB / 16 - 1; 984 985 bzero(sc->lriqb, sizeof sc->lriqb); 986 sc->m32x->lriqba = vtophys(&sc->lriqb); 987 sc->m32x->lriql = NIQB / 16 - 1; 988 989 bzero(sc->piqb, sizeof sc->piqb); 990 sc->m32x->piqba = vtophys(&sc->piqb); 991 sc->m32x->piql = NIQB / 16 - 1; 992 993 m32_init(sc); 994 f54_init(sc); 995 996 u = sc->m32x->stat; 997 sc->m32x->stat = u; 998 sc->m32_mem.ccb = 0x4; 999 sc->m32x->cmd = 0x1; 1000 DELAY(1000); 1001 u = sc->m32x->stat; 1002 sc->m32x->stat = u; 1003 1004 /* set all timeslots to known state */ 1005 for (i = 0; i < 32; i++) 1006 sc->m32_mem.ts[i] = 0x20002000; 1007 1008 if (!(u & 1)) { 1009 printf( 1010"mn%d: WARNING: Controller failed the PCI bus-master test.\n" 1011"mn%d: WARNING: Use a PCI slot which can support bus-master cards.\n", 1012 sc->unit, sc->unit); 1013 return (0); 1014 } 1015 return (1); 1016} 1017 1018/* 1019 * FALC54 interrupt handling 1020 */ 1021static void 1022f54_intr(struct softc *sc) 1023{ 1024 unsigned g, u, s; 1025 1026 g = sc->f54r->gis; 1027 u = sc->f54r->isr0 << 24; 1028 u |= sc->f54r->isr1 << 16; 1029 u |= sc->f54r->isr2 << 8; 1030 u |= sc->f54r->isr3; 1031 sc->falc_irq = u; 1032 /* don't chat about the 1 sec heart beat */ 1033 if (u & ~0x40) { 1034#if 0 1035 printf("%s*: FALC54 IRQ GIS:%02x %b\n", sc->name, g, u, "\20" 1036 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 1037 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 1038 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 1039 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 1040#endif 1041 s = sc->f54r->frs0 << 24; 1042 s |= sc->f54r->frs1 << 16; 1043 s |= sc->f54r->rsw << 8; 1044 s |= sc->f54r->rsp; 1045 sc->falc_state = s; 1046 1047 s &= ~0x01844038; /* undefined or static bits */ 1048 s &= ~0x00009fc7; /* bits we don't care about */ 1049 s &= ~0x00780000; /* XXX: TS16 related */ 1050 s &= ~0x06000000; /* XXX: Multiframe related */ 1051#if 0 1052 printf("%s*: FALC54 Status %b\n", sc->name, s, "\20" 1053 "\40LOS\37AIS\36LFA\35RRA\34AUXP\33NMF\32LMFA\31frs0.0" 1054 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS\24TS16LFA\23frs1.2\22XLS\21XLO" 1055 "\20RS1\17rsw.6\16RRA\15RY0\14RY1\13RY2\12RY3\11RY4" 1056 "\10SI1\7SI2\6rsp.5\5rsp.4\4rsp.3\3RSIF\2RS13\1RS15"); 1057#endif 1058 if (s != sc->framer_state) { 1059#if 0 1060 for (i = 0; i < M32_CHAN; i++) { 1061 if (!sc->ch[i]) 1062 continue; 1063 sp = &sc->ch[i]->ifsppp; 1064 if (!(sp->pp_if.if_flags & IFF_UP)) 1065 continue; 1066 if (s) 1067 timeout((timeout_t *)sp->pp_down, sp, 1 * hz); 1068 else 1069 timeout((timeout_t *)sp->pp_up, sp, 1 * hz); 1070 } 1071#endif 1072 sc->framer_state = s; 1073 } 1074 } 1075 /* Once per second check error counters */ 1076 /* XXX: not clear if this is actually ok */ 1077 if (!(u & 0x40)) 1078 return; 1079 sc->cnt_fec += sc->f54r->fec; 1080 sc->cnt_cvc += sc->f54r->cvc; 1081 sc->cnt_cec1 += sc->f54r->cec1; 1082 sc->cnt_ebc += sc->f54r->ebc; 1083 sc->cnt_cec2 += sc->f54r->cec2; 1084 sc->cnt_cec3 += sc->f54r->cec3; 1085 sc->cnt_rbc += sc->f54r->rbc; 1086} 1087 1088/* 1089 * Transmit interrupt for one channel 1090 */ 1091static void 1092mn_tx_intr(struct softc *sc, u_int32_t vector) 1093{ 1094 u_int32_t chan; 1095 struct trxd *dp; 1096 struct mbuf *m; 1097 1098 chan = vector & 0x1f; 1099 if (!sc->ch[chan]) 1100 return; 1101 if (sc->ch[chan]->state != UP) { 1102 printf("%s: tx_intr when not UP\n", sc->name); 1103 return; 1104 } 1105 for (;;) { 1106 dp = sc->ch[chan]->x1; 1107 if (vtophys(dp) == sc->m32_mem.ctxd[chan]) 1108 return; 1109 m = dp->m; 1110 if (m) { 1111#if 0 1112 printf("%d = %d - %d (%p)\n", 1113 sc->ch[chan]->tx_pending - m->m_pkthdr.len, 1114 sc->ch[chan]->tx_pending , m->m_pkthdr.len, m); 1115#endif 1116 sc->ch[chan]->tx_pending -= m->m_pkthdr.len; 1117 m_freem(m); 1118 } 1119 sc->ch[chan]->last_xmit = time_second; 1120 sc->ch[chan]->x1 = dp->vnext; 1121 mn_free_desc(dp); 1122 } 1123} 1124 1125/* 1126 * Receive interrupt for one channel 1127 */ 1128static void 1129mn_rx_intr(struct softc *sc, u_int32_t vector) 1130{ 1131 u_int32_t chan, err; 1132 struct trxd *dp; 1133 struct mbuf *m; 1134 struct schan *sch; 1135 1136 chan = vector & 0x1f; 1137 if (!sc->ch[chan]) 1138 return; 1139 sch = sc->ch[chan]; 1140 if (sch->state != UP) { 1141 printf("%s: rx_intr when not UP\n", sc->name); 1142 return; 1143 } 1144 vector &= ~0x1f; 1145 if (vector == 0x30000b00) 1146 sch->rx_error++; 1147 for (;;) { 1148 dp = sch->r1; 1149 if (vtophys(dp) == sc->m32_mem.crxd[chan]) 1150 return; 1151 m = dp->m; 1152 dp->m = 0; 1153 m->m_pkthdr.len = m->m_len = (dp->status >> 16) & 0x1fff; 1154 err = (dp->status >> 8) & 0xff; 1155 if (!err) { 1156 int error; 1157 NG_SEND_DATA_ONLY(error, sch->hook, m); 1158 sch->last_recv = time_second; 1159 /* we could be down by now... */ 1160 if (sch->state != UP) 1161 return; 1162 } else if (err & 0x40) { 1163 sch->short_error++; 1164 } else if (err & 0x10) { 1165 sch->crc_error++; 1166 } else if (err & 0x08) { 1167 sch->dribble_error++; 1168 } else if (err & 0x04) { 1169 sch->long_error++; 1170 } else if (err & 0x02) { 1171 sch->abort_error++; 1172 } else if (err & 0x01) { 1173 sch->overflow_error++; 1174 } 1175 if (err) { 1176 sch->last_rxerr = time_second; 1177 sch->prev_error = sch->last_error; 1178 sch->last_error = err; 1179 } 1180 1181 sc->ch[chan]->r1 = dp->vnext; 1182 1183 /* Replenish desc + mbuf supplies */ 1184 if (!m) { 1185 MGETHDR(m, M_DONTWAIT, MT_DATA); 1186 if (m == NULL) { 1187 mn_free_desc(dp); 1188 return; /* ENOBUFS */ 1189 } 1190 MCLGET(m, M_DONTWAIT); 1191 if((m->m_flags & M_EXT) == 0) { 1192 mn_free_desc(dp); 1193 m_freem(m); 1194 return; /* ENOBUFS */ 1195 } 1196 } 1197 dp->m = m; 1198 dp->data = vtophys(m->m_data); 1199 dp->flags = 0x40000000; 1200 dp->flags += 1600 << 16; 1201 dp->next = vtophys(dp); 1202 dp->vnext = 0; 1203 sc->ch[chan]->rl->next = vtophys(dp); 1204 sc->ch[chan]->rl->vnext = dp; 1205 sc->ch[chan]->rl->flags &= ~0x40000000; 1206 sc->ch[chan]->rl = dp; 1207 } 1208} 1209 1210 1211/* 1212 * Interupt handler 1213 */ 1214 1215static void 1216mn_intr(void *xsc) 1217{ 1218 struct softc *sc; 1219 u_int32_t stat, lstat, u; 1220 int i, j; 1221 1222 sc = xsc; 1223 stat = sc->m32x->stat; 1224 lstat = sc->m32x->lstat; 1225#if 0 1226 if (!stat && !(lstat & 2)) 1227 return; 1228#endif 1229 1230 if (stat & ~0xc200) { 1231 printf("%s: I stat=%08x lstat=%08x\n", sc->name, stat, lstat); 1232 } 1233 1234 if ((stat & 0x200) || (lstat & 2)) 1235 f54_intr(sc); 1236 1237 for (j = i = 0; i < 64; i ++) { 1238 u = sc->riqb[i]; 1239 if (u) { 1240 sc->riqb[i] = 0; 1241 mn_rx_intr(sc, u); 1242 if ((u & ~0x1f) == 0x30000800 || (u & ~0x1f) == 0x30000b00) 1243 continue; 1244 u &= ~0x30000400; /* bits we don't care about */ 1245 if ((u & ~0x1f) == 0x00000900) 1246 continue; 1247 if (!(u & ~0x1f)) 1248 continue; 1249 if (!j) 1250 printf("%s*: RIQB:", sc->name); 1251 printf(" [%d]=%08x", i, u); 1252 j++; 1253 } 1254 } 1255 if (j) 1256 printf("\n"); 1257 1258 for (j = i = 0; i < 64; i ++) { 1259 u = sc->tiqb[i]; 1260 if (u) { 1261 sc->tiqb[i] = 0; 1262 mn_tx_intr(sc, u); 1263 if ((u & ~0x1f) == 0x20000800) 1264 continue; 1265 u &= ~0x20000000; /* bits we don't care about */ 1266 if (!u) 1267 continue; 1268 if (!j) 1269 printf("%s*: TIQB:", sc->name); 1270 printf(" [%d]=%08x", i, u); 1271 j++; 1272 } 1273 } 1274 if (j) 1275 printf("\n"); 1276 sc->m32x->stat = stat; 1277} 1278 1279static void 1280mn_timeout(void *xsc) 1281{ 1282 static int round = 0; 1283 struct softc *sc; 1284 1285 mn_intr(xsc); 1286 sc = xsc; 1287 timeout(mn_timeout, xsc, 10 * hz); 1288 round++; 1289 if (round == 2) { 1290 sc->m32_mem.ccb = 0x00008004; 1291 sc->m32x->cmd = 0x1; 1292 } else if (round > 2) { 1293 printf("%s: timeout\n", sc->name); 1294 } 1295} 1296 1297/* 1298 * PCI initialization stuff 1299 */ 1300 1301static int 1302mn_probe (device_t self) 1303{ 1304 u_int id = pci_get_devid(self); 1305 1306 if (sizeof (struct m32xreg) != 256) { 1307 printf("MN: sizeof(struct m32xreg) = %d, should have been 256\n", sizeof (struct m32xreg)); 1308 return (ENXIO); 1309 } 1310 if (sizeof (struct f54rreg) != 128) { 1311 printf("MN: sizeof(struct f54rreg) = %d, should have been 128\n", sizeof (struct f54rreg)); 1312 return (ENXIO); 1313 } 1314 if (sizeof (struct f54wreg) != 128) { 1315 printf("MN: sizeof(struct f54wreg) = %d, should have been 128\n", sizeof (struct f54wreg)); 1316 return (ENXIO); 1317 } 1318 1319 if (id != 0x2101110a) 1320 return (ENXIO); 1321 1322 device_set_desc_copy(self, "Munich32X E1/T1 HDLC Controller"); 1323 return (0); 1324} 1325 1326static int 1327mn_attach (device_t self) 1328{ 1329 struct softc *sc; 1330 u_int32_t u; 1331 u_int32_t ver; 1332 static int once; 1333 int rid, error; 1334 struct resource *res; 1335 1336 if (!once) { 1337 if (ng_newtype(&mntypestruct)) 1338 printf("ng_newtype failed\n"); 1339 once++; 1340 } 1341 1342 sc = (struct softc *)malloc(sizeof *sc, M_MN, M_WAITOK | M_ZERO); 1343 device_set_softc(self, sc); 1344 1345 sc->dev = self; 1346 sc->unit = device_get_unit(self); 1347 sc->framing = E1; 1348 sprintf(sc->name, "mn%d", sc->unit); 1349 1350 rid = PCIR_MAPS; 1351 res = bus_alloc_resource(self, SYS_RES_MEMORY, &rid, 1352 0, ~0, 1, RF_ACTIVE); 1353 if (res == NULL) { 1354 device_printf(self, "Could not map memory\n"); 1355 return ENXIO; 1356 } 1357 sc->m0v = rman_get_virtual(res); 1358 sc->m0p = rman_get_start(res); 1359 1360 rid = PCIR_MAPS + 4; 1361 res = bus_alloc_resource(self, SYS_RES_MEMORY, &rid, 1362 0, ~0, 1, RF_ACTIVE); 1363 if (res == NULL) { 1364 device_printf(self, "Could not map memory\n"); 1365 return ENXIO; 1366 } 1367 sc->m1v = rman_get_virtual(res); 1368 sc->m1p = rman_get_start(res); 1369 1370 /* Allocate interrupt */ 1371 rid = 0; 1372 sc->irq = bus_alloc_resource(self, SYS_RES_IRQ, &rid, 0, ~0, 1373 1, RF_SHAREABLE | RF_ACTIVE); 1374 1375 if (sc->irq == NULL) { 1376 printf("couldn't map interrupt\n"); 1377 return(ENXIO); 1378 } 1379 1380 error = bus_setup_intr(self, sc->irq, INTR_TYPE_NET, mn_intr, sc, &sc->intrhand); 1381 1382 if (error) { 1383 printf("couldn't set up irq\n"); 1384 return(ENXIO); 1385 } 1386 1387 u = pci_read_config(self, PCIR_COMMAND, 1); 1388 printf("%x\n", u); 1389 pci_write_config(self, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN, 1); 1390#if 0 1391 pci_write_config(self, PCIR_COMMAND, 0x02800046, 4); 1392#endif 1393 u = pci_read_config(self, PCIR_COMMAND, 1); 1394 printf("%x\n", u); 1395 1396 ver = pci_get_revid(self); 1397 1398 sc->m32x = (struct m32xreg *) sc->m0v; 1399 sc->f54w = (struct f54wreg *) sc->m1v; 1400 sc->f54r = (struct f54rreg *) sc->m1v; 1401 1402 /* We must reset before poking at FALC54 registers */ 1403 u = mn_reset(sc); 1404 if (!u) 1405 return (0); 1406 1407 printf("mn%d: Munich32X", sc->unit); 1408 switch (ver) { 1409 case 0x13: 1410 printf(" Rev 2.2"); 1411 break; 1412 default: 1413 printf(" Rev 0x%x\n", ver); 1414 } 1415 printf(", Falc54"); 1416 switch (sc->f54r->vstr) { 1417 case 0: 1418 printf(" Rev < 1.3\n"); 1419 break; 1420 case 1: 1421 printf(" Rev 1.3\n"); 1422 break; 1423 case 2: 1424 printf(" Rev 1.4\n"); 1425 break; 1426 case 0x10: 1427 printf("-LH Rev 1.1\n"); 1428 break; 1429 case 0x13: 1430 printf("-LH Rev 1.3\n"); 1431 break; 1432 default: 1433 printf(" Rev 0x%x\n", sc->f54r->vstr); 1434 } 1435 1436 if (ng_make_node_common(&mntypestruct, &sc->node) != 0) { 1437 printf("ng_make_node_common failed\n"); 1438 return (0); 1439 } 1440 NG_NODE_SET_PRIVATE(sc->node, sc); 1441 sprintf(sc->nodename, "%s%d", NG_MN_NODE_TYPE, sc->unit); 1442 if (ng_name_node(sc->node, sc->nodename)) { 1443 NG_NODE_UNREF(sc->node); 1444 return (0); 1445 } 1446 1447 return (0); 1448} 1449 1450 1451static device_method_t mn_methods[] = { 1452 /* Device interface */ 1453 DEVMETHOD(device_probe, mn_probe), 1454 DEVMETHOD(device_attach, mn_attach), 1455 DEVMETHOD(device_suspend, bus_generic_suspend), 1456 DEVMETHOD(device_resume, bus_generic_resume), 1457 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1458 1459 {0, 0} 1460}; 1461 1462static driver_t mn_driver = { 1463 "mn", 1464 mn_methods, 1465 0 1466}; 1467 1468static devclass_t mn_devclass; 1469 1470DRIVER_MODULE(mn, pci, mn_driver, mn_devclass, 0, 0); 1471