if_mn.c revision 71344
1/* 2 * ---------------------------------------------------------------------------- 3 * "THE BEER-WARE LICENSE" (Revision 42): 4 * <phk@FreeBSD.org> wrote this file. As long as you retain this notice you 5 * can do whatever you want with this stuff. If we meet some day, and you think 6 * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp 7 * ---------------------------------------------------------------------------- 8 * 9 * $Id: if_mn.c,v 1.1 1999/02/01 13:06:40 phk Exp $ 10 * 11 * Driver for Siemens reference design card "Easy321-R1". 12 * 13 * This card contains a FALC54 E1/T1 framer and a MUNICH32X 32-channel HDLC 14 * controller. 15 * 16 * The driver supports E1 mode with up to 31 channels. We send CRC4 but don't 17 * check it coming in. 18 * 19 * The FALC54 and MUNICH32X have far too many registers and weird modes for 20 * comfort, so I have not bothered typing it all into a "fooreg.h" file, 21 * you will (badly!) need the documentation anyway if you want to mess with 22 * this gadget. 23 * 24 * $FreeBSD: head/sys/pci/if_mn.c 71344 2001-01-21 22:16:20Z phk $ 25 */ 26 27/* 28 * Stuff to describe the MUNIC32X and FALC54 chips. 29 */ 30 31#define M32_CHAN 32 /* We have 32 channels */ 32#define M32_TS 32 /* We have 32 timeslots */ 33 34#define NG_MN_NODE_TYPE "mn" 35 36#include <sys/param.h> 37#include <sys/kernel.h> 38#include <sys/sysctl.h> 39#include <sys/bus.h> 40#include <sys/mbuf.h> 41#include <sys/systm.h> 42#include <sys/malloc.h> 43 44#include <pci/pcireg.h> 45#include <pci/pcivar.h> 46#include "pci_if.h" 47 48#include <machine/bus.h> 49#include <machine/resource.h> 50 51#include <sys/rman.h> 52 53#include <vm/vm.h> 54#include <vm/pmap.h> 55 56#include <netgraph/ng_message.h> 57#include <netgraph/netgraph.h> 58 59 60static int mn_maxlatency = 1000; 61SYSCTL_INT(_debug, OID_AUTO, mn_maxlatency, CTLFLAG_RW, 62 &mn_maxlatency, 0, 63 "The number of milliseconds a packet is allowed to spend in the output queue. " 64 "If the output queue is longer than this number of milliseconds when the packet " 65 "arrives for output, the packet will be dropped." 66); 67 68#ifndef NMN 69/* Most machines don't support more than 4 busmaster PCI slots, if even that many */ 70#define NMN 4 71#endif 72 73/* From: PEB 20321 data sheet, p187, table 22 */ 74struct m32xreg { 75 u_int32_t conf, cmd, stat, imask; 76 u_int32_t fill10, piqba, piql, fill1c; 77 u_int32_t mode1, mode2, ccba, txpoll; 78 u_int32_t tiqba, tiql, riqba, riql; 79 u_int32_t lconf, lccba, fill48, ltran; 80 u_int32_t ltiqba, ltiql, lriqba, lriql; 81 u_int32_t lreg0, lreg1, lreg2, lreg3; 82 u_int32_t lreg4, lreg5, lre6, lstat; 83 u_int32_t gpdir, gpdata, gpod, fill8c; 84 u_int32_t ssccon, sscbr, ssctb, sscrb; 85 u_int32_t ssccse, sscim, fillab, fillac; 86 u_int32_t iomcon1, iomcon2, iomstat, fillbc; 87 u_int32_t iomcit0, iomcit1, iomcir0, iomcir1; 88 u_int32_t iomtmo, iomrmo, filld8, filldc; 89 u_int32_t mbcmd, mbdata1, mbdata2, mbdata3; 90 u_int32_t mbdata4, mbdata5, mbdata6, mbdata7; 91}; 92 93/* From: PEB 2254 data sheet, p80, table 10 */ 94struct f54wreg { 95 u_int16_t xfifo; 96 u_int8_t cmdr, mode, rah1, rah2, ral1, ral2; 97 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 98 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 99 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 100 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 101 u_int8_t test1, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr3; 102 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 103 u_int8_t lim2, fill39[7]; 104 u_int8_t fill40[8]; 105 u_int8_t fill48[8]; 106 u_int8_t fill50[8]; 107 u_int8_t fill58[8]; 108 u_int8_t dec, fill61, test2, fill63[5]; 109 u_int8_t fill68[8]; 110 u_int8_t xs[16]; 111}; 112 113/* From: PEB 2254 data sheet, p117, table 10 */ 114struct f54rreg { 115 u_int16_t rfifo; 116 u_int8_t fill2, mode, rah1, rah2, ral1, ral2; 117 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 118 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 119 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 120 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 121 u_int8_t test, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr13; 122 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 123 u_int8_t lim2, fill39[7]; 124 u_int8_t fill40[8]; 125 u_int8_t fill48[4], frs0, frs1, rsw, rsp; 126 u_int16_t fec, cvc, cec1, ebc; 127 u_int16_t cec2, cec3; 128 u_int8_t rsa4, rsa5, rsa6, rsa7; 129 u_int8_t rsa8, rsa6s, tsr0, tsr1, sis, rsis; 130 u_int16_t rbc; 131 u_int8_t isr0, isr1, isr2, isr3, fill6c, fill6d, gis, vstr; 132 u_int8_t rs[16]; 133}; 134 135/* Transmit & receive descriptors */ 136struct trxd { 137 u_int32_t flags; 138 vm_offset_t next; 139 vm_offset_t data; 140 u_int32_t status; /* only used for receive */ 141 struct mbuf *m; /* software use only */ 142 struct trxd *vnext; /* software use only */ 143}; 144 145/* Channel specification */ 146struct cspec { 147 u_int32_t flags; 148 vm_offset_t rdesc; 149 vm_offset_t tdesc; 150 u_int32_t itbs; 151}; 152 153struct m32_mem { 154 vm_offset_t csa; 155 u_int32_t ccb; 156 u_int32_t reserve1[2]; 157 u_int32_t ts[M32_TS]; 158 struct cspec cs[M32_CHAN]; 159 vm_offset_t crxd[M32_CHAN]; 160 vm_offset_t ctxd[M32_CHAN]; 161}; 162 163struct softc; 164struct sockaddr; 165struct rtentry; 166 167static int mn_probe (device_t self); 168static int mn_attach (device_t self); 169static void mn_create_channel(struct softc *sc, int chan); 170static int mn_reset(struct softc *sc); 171static struct trxd * mn_alloc_desc(void); 172static void mn_free_desc(struct trxd *dp); 173static void mn_intr(void *xsc); 174static u_int32_t mn_parse_ts(const char *s, int *nbit); 175#ifdef notyet 176static void m32_dump(struct softc *sc); 177static void f54_dump(struct softc *sc); 178static void mn_fmt_ts(char *p, u_int32_t ts); 179#endif /* notyet */ 180static void f54_init(struct softc *sc); 181 182static ng_constructor_t ngmn_constructor; 183static ng_rcvmsg_t ngmn_rcvmsg; 184static ng_shutdown_t ngmn_shutdown; 185static ng_newhook_t ngmn_newhook; 186static ng_connect_t ngmn_connect; 187static ng_rcvdata_t ngmn_rcvdata; 188static ng_disconnect_t ngmn_disconnect; 189 190static struct ng_type mntypestruct = { 191 NG_ABI_VERSION, 192 NG_MN_NODE_TYPE, 193 NULL, 194 ngmn_constructor, 195 ngmn_rcvmsg, 196 ngmn_shutdown, 197 ngmn_newhook, 198 NULL, 199 ngmn_connect, 200 ngmn_rcvdata, 201 ngmn_disconnect, 202 NULL 203}; 204 205static MALLOC_DEFINE(M_MN, "mn", "Mx driver related"); 206 207#define NIQB 64 208 209struct schan { 210 enum {DOWN, UP} state; 211 struct softc *sc; 212 int chan; 213 u_int32_t ts; 214 char name[8]; 215 struct trxd *r1, *rl; 216 struct trxd *x1, *xl; 217 hook_p hook; 218 219 time_t last_recv; 220 time_t last_rxerr; 221 time_t last_xmit; 222 223 u_long rx_error; 224 225 u_long short_error; 226 u_long crc_error; 227 u_long dribble_error; 228 u_long long_error; 229 u_long abort_error; 230 u_long overflow_error; 231 232 int last_error; 233 int prev_error; 234 235 u_long tx_pending; 236 u_long tx_limit; 237}; 238 239enum framing {WHOKNOWS, E1, E1U, T1, T1U}; 240 241struct softc { 242 int unit; 243 device_t dev; 244 struct resource *irq; 245 void *intrhand; 246 enum framing framing; 247 int nhooks; 248 void *m0v, *m1v; 249 vm_offset_t m0p, m1p; 250 struct m32xreg *m32x; 251 struct f54wreg *f54w; 252 struct f54rreg *f54r; 253 struct m32_mem m32_mem; 254 u_int32_t tiqb[NIQB]; 255 u_int32_t riqb[NIQB]; 256 u_int32_t piqb[NIQB]; 257 u_int32_t ltiqb[NIQB]; 258 u_int32_t lriqb[NIQB]; 259 char name[8]; 260 u_int32_t falc_irq, falc_state, framer_state; 261 struct schan *ch[M32_CHAN]; 262 char nodename[NG_NODELEN + 1]; 263 node_p node; 264 265 u_long cnt_fec; 266 u_long cnt_cvc; 267 u_long cnt_cec1; 268 u_long cnt_ebc; 269 u_long cnt_cec2; 270 u_long cnt_cec3; 271 u_long cnt_rbc; 272}; 273 274static int 275ngmn_constructor(node_p node) 276{ 277 278 return (EINVAL); 279} 280 281static int 282ngmn_shutdown(node_p nodep) 283{ 284 285 return (EINVAL); 286} 287 288static void 289ngmn_config(node_p node, char *set, char *ret) 290{ 291 struct softc *sc; 292 enum framing wframing; 293 294 sc = NG_NODE_PRIVATE(node); 295 296 if (set != NULL) { 297 if (!strncmp(set, "line ", 5)) { 298 wframing = sc->framing; 299 if (!strcmp(set, "line e1")) { 300 wframing = E1; 301 } else if (!strcmp(set, "line e1u")) { 302 wframing = E1U; 303 } else { 304 strcat(ret, "ENOGROK\n"); 305 return; 306 } 307 if (wframing == sc->framing) 308 return; 309 if (sc->nhooks > 0) { 310 sprintf(ret, "Cannot change line when %d hooks open\n", sc->nhooks); 311 return; 312 } 313 sc->framing = wframing; 314#if 1 315 f54_init(sc); 316#else 317 mn_reset(sc); 318#endif 319 } else { 320 printf("%s CONFIG SET [%s]\n", sc->nodename, set); 321 strcat(ret, "ENOGROK\n"); 322 return; 323 } 324 } 325 326} 327 328static int 329ngmn_rcvmsg(node_p node, item_p item, hook_p lasthook) 330{ 331 struct softc *sc; 332 struct ng_mesg *resp = NULL; 333 struct schan *sch; 334 char *s, *r; 335 int pos, i; 336 struct ng_mesg *msg; 337 338 NGI_GET_MSG(item, msg); 339 sc = NG_NODE_PRIVATE(node); 340 341 if (msg->header.typecookie != NGM_GENERIC_COOKIE) { 342 NG_FREE_ITEM(item); 343 NG_FREE_MSG(msg); 344 return (EINVAL); 345 } 346 347 if (msg->header.cmd != NGM_TEXT_CONFIG && 348 msg->header.cmd != NGM_TEXT_STATUS) { 349 NG_FREE_ITEM(item); 350 NG_FREE_MSG(msg); 351 return (EINVAL); 352 } 353 354 NG_MKRESPONSE(resp, msg, sizeof(struct ng_mesg) + NG_TEXTRESPONSE, 355 M_NOWAIT); 356 if (resp == NULL) { 357 NG_FREE_ITEM(item); 358 NG_FREE_MSG(msg); 359 return (ENOMEM); 360 } 361 362 if (msg->header.arglen) 363 s = (char *)msg->data; 364 else 365 s = NULL; 366 r = (char *)resp->data; 367 *r = '\0'; 368 369 if (msg->header.cmd == NGM_TEXT_CONFIG) { 370 ngmn_config(node, s, r); 371 resp->header.arglen = strlen(r) + 1; 372 FREE(msg, M_NETGRAPH); 373 return (0); 374 } 375 pos = 0; 376 pos += sprintf(pos + r,"Framer status %b;\n", sc->framer_state, "\20" 377 "\40LOS\37AIS\36LFA\35RRA" 378 "\34AUXP\33NMF\32LMFA\31frs0.0" 379 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 380 "\24TS16LFA\23frs1.2\22XLS\21XLO" 381 "\20RS1\17rsw.6\16RRA\15RY0" 382 "\14RY1\13RY2\12RY3\11RY4" 383 "\10SI1\7SI2\6rsp.5\5rsp.4" 384 "\4rsp.3\3RSIF\2RS13\1RS15"); 385 pos += sprintf(pos + r," Framing errors: %lu", sc->cnt_fec); 386 pos += sprintf(pos + r," Code Violations: %lu\n", sc->cnt_cvc); 387 388 pos += sprintf(pos + r," Falc State %b;\n", sc->falc_state, "\20" 389 "\40LOS\37AIS\36LFA\35RRA" 390 "\34AUXP\33NMF\32LMFA\31frs0.0" 391 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 392 "\24TS16LFA\23frs1.2\22XLS\21XLO" 393 "\20RS1\17rsw.6\16RRA\15RY0" 394 "\14RY1\13RY2\12RY3\11RY4" 395 "\10SI1\7SI2\6rsp.5\5rsp.4" 396 "\4rsp.3\3RSIF\2RS13\1RS15"); 397 pos += sprintf(pos + r, " Falc IRQ %b\n", sc->falc_irq, "\20" 398 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 399 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 400 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 401 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 402 for (i = 0; i < M32_CHAN; i++) { 403 if (!sc->ch[i]) 404 continue; 405 sch = sc->ch[i]; 406 407 pos += sprintf(r + pos, " Chan %d <%s> ", 408 i, NG_HOOK_NAME(sch->hook)); 409 410 pos += sprintf(r + pos, " Last Rx: "); 411 if (sch->last_recv) 412 pos += sprintf(r + pos, "%lu s", time_second - sch->last_recv); 413 else 414 pos += sprintf(r + pos, "never"); 415 416 pos += sprintf(r + pos, ", last RxErr: "); 417 if (sch->last_rxerr) 418 pos += sprintf(r + pos, "%lu s", time_second - sch->last_rxerr); 419 else 420 pos += sprintf(r + pos, "never"); 421 422 pos += sprintf(r + pos, ", last Tx: "); 423 if (sch->last_xmit) 424 pos += sprintf(r + pos, "%lu s\n", time_second - sch->last_xmit); 425 else 426 pos += sprintf(r + pos, "never\n"); 427 428 pos += sprintf(r + pos, " RX error(s) %lu", sch->rx_error); 429 pos += sprintf(r + pos, " Short: %lu", sch->short_error); 430 pos += sprintf(r + pos, " CRC: %lu", sch->crc_error); 431 pos += sprintf(r + pos, " Mod8: %lu", sch->dribble_error); 432 pos += sprintf(r + pos, " Long: %lu", sch->long_error); 433 pos += sprintf(r + pos, " Abort: %lu", sch->abort_error); 434 pos += sprintf(r + pos, " Overflow: %lu\n", sch->overflow_error); 435 436 pos += sprintf(r + pos, " Last error: %b Prev error: %b\n", 437 sch->last_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN", 438 sch->prev_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN"); 439 pos += sprintf(r + pos, " Xmit bytes pending %ld\n", 440 sch->tx_pending); 441 } 442 resp->header.arglen = pos + 1; 443 444 /* Take care of synchronous response, if any */ 445 NG_RESPOND_MSG(i, node, item, resp); 446 NG_FREE_MSG(msg); 447 return (0); 448} 449 450static int 451ngmn_newhook(node_p node, hook_p hook, const char *name) 452{ 453 u_int32_t ts, chan; 454 struct softc *sc; 455 int nbit; 456 457 sc = NG_NODE_PRIVATE(node); 458 459 if (name[0] != 't' || name[1] != 's') 460 return (EINVAL); 461 462 ts = mn_parse_ts(name + 2, &nbit); 463 printf("%d bits %x\n", nbit, ts); 464 if (sc->framing == E1 && (ts & 1)) 465 return (EINVAL); 466 if (sc->framing == E1U && nbit != 32) 467 return (EINVAL); 468 if (ts == 0) 469 return (EINVAL); 470 if (sc->framing == E1) 471 chan = ffs(ts) - 1; 472 else 473 chan = 1; 474 if (!sc->ch[chan]) 475 mn_create_channel(sc, chan); 476 else if (sc->ch[chan]->state == UP) 477 return (EBUSY); 478 sc->ch[chan]->ts = ts; 479 sc->ch[chan]->hook = hook; 480 sc->ch[chan]->tx_limit = nbit * 8; 481 NG_HOOK_SET_PRIVATE(hook, sc->ch[chan]); 482 sc->nhooks++; 483 return(0); 484} 485 486 487static struct trxd *mn_desc_free; 488 489static struct trxd * 490mn_alloc_desc(void) 491{ 492 struct trxd *dp; 493 494 dp = mn_desc_free; 495 if (dp) 496 mn_desc_free = dp->vnext; 497 else 498 dp = (struct trxd *)malloc(sizeof *dp, M_MN, M_NOWAIT); 499 return (dp); 500} 501 502static void 503mn_free_desc(struct trxd *dp) 504{ 505 dp->vnext = mn_desc_free; 506 mn_desc_free = dp; 507} 508 509static u_int32_t 510mn_parse_ts(const char *s, int *nbit) 511{ 512 unsigned r; 513 int i, j; 514 char *p; 515 516 r = 0; 517 j = -1; 518 *nbit = 0; 519 while(*s) { 520 i = strtol(s, &p, 0); 521 if (i < 0 || i > 31) 522 return (0); 523 while (j != -1 && j < i) { 524 r |= 1 << j++; 525 (*nbit)++; 526 } 527 j = -1; 528 r |= 1 << i; 529 (*nbit)++; 530 if (*p == ',') { 531 s = p + 1; 532 continue; 533 } else if (*p == '-') { 534 j = i + 1; 535 s = p + 1; 536 continue; 537 } else if (!*p) { 538 break; 539 } else { 540 return (0); 541 } 542 } 543 return (r); 544} 545 546#ifdef notyet 547static void 548mn_fmt_ts(char *p, u_int32_t ts) 549{ 550 char *s; 551 int j; 552 553 s = ""; 554 ts &= 0xffffffff; 555 for (j = 0; j < 32; j++) { 556 if (!(ts & (1 << j))) 557 continue; 558 sprintf(p, "%s%d", s, j); 559 p += strlen(p); 560 s = ","; 561 if (!(ts & (1 << (j+1)))) 562 continue; 563 for (; j < 32; j++) 564 if (!(ts & (1 << (j+1)))) 565 break; 566 sprintf(p, "-%d", j); 567 p += strlen(p); 568 s = ","; 569 } 570} 571#endif /* notyet */ 572 573/* 574 * OUTPUT 575 */ 576 577static int 578ngmn_rcvdata(hook_p hook, item_p item) 579{ 580 struct mbuf *m2; 581 struct trxd *dp, *dp2; 582 struct schan *sch; 583 struct softc *sc; 584 int chan, pitch, len; 585 struct mbuf *m; 586 587 sch = NG_HOOK_PRIVATE(hook); 588 sc = sch->sc; 589 chan = sch->chan; 590 591 if (sch->state != UP) { 592 NG_FREE_ITEM(item); 593 return (0); 594 } 595 NGI_GET_M(item, m); 596 if (sch->tx_pending + m->m_pkthdr.len > sch->tx_limit * mn_maxlatency) { 597 NG_FREE_M(m); 598 NG_FREE_ITEM(item); 599 return (0); 600 } 601 NG_FREE_ITEM(item); 602 pitch = 0; 603 m2 = m; 604 dp2 = sc->ch[chan]->xl; 605 len = m->m_pkthdr.len; 606 while (len) { 607 dp = mn_alloc_desc(); 608 if (!dp) { 609 pitch++; 610 m_freem(m); 611 sc->ch[chan]->xl = dp2; 612 dp = dp2->vnext; 613 while (dp) { 614 dp2 = dp->vnext; 615 mn_free_desc(dp); 616 dp = dp2; 617 } 618 sc->ch[chan]->xl->vnext = 0; 619 break; 620 } 621 dp->data = vtophys(m2->m_data); 622 dp->flags = m2->m_len << 16; 623 dp->flags += 1; 624 len -= m2->m_len; 625 dp->next = vtophys(dp); 626 dp->vnext = 0; 627 sc->ch[chan]->xl->next = vtophys(dp); 628 sc->ch[chan]->xl->vnext = dp; 629 sc->ch[chan]->xl = dp; 630 if (!len) { 631 dp->m = m; 632 dp->flags |= 0xc0000000; 633 dp2->flags &= ~0x40000000; 634 } else { 635 dp->m = 0; 636 m2 = m2->m_next; 637 } 638 } 639 if (pitch) 640 printf("%s%d: Short on mem, pitched %d packets\n", 641 sc->name, chan, pitch); 642 else { 643#if 0 644 printf("%d = %d + %d (%p)\n", 645 sch->tx_pending + m->m_pkthdr.len, 646 sch->tx_pending , m->m_pkthdr.len, m); 647#endif 648 sch->tx_pending += m->m_pkthdr.len; 649 sc->m32x->txpoll &= ~(1 << chan); 650 } 651 return (0); 652} 653 654/* 655 * OPEN 656 */ 657static int 658ngmn_connect(hook_p hook) 659{ 660 int i, nts, chan; 661 struct trxd *dp, *dp2; 662 struct mbuf *m; 663 struct softc *sc; 664 struct schan *sch; 665 u_int32_t u; 666 667 sch = NG_HOOK_PRIVATE(hook); 668 chan = sch->chan; 669 sc = sch->sc; 670 671 if (sch->state == UP) 672 return (0); 673 sch->state = UP; 674 675 /* Count and configure the timeslots for this channel */ 676 for (nts = i = 0; i < 32; i++) 677 if (sch->ts & (1 << i)) { 678 sc->m32_mem.ts[i] = 0x00ff00ff | 679 (chan << 24) | (chan << 8); 680 nts++; 681 } 682 683 /* Init the receiver & xmitter to HDLC */ 684 sc->m32_mem.cs[chan].flags = 0x80e90006; 685 /* Allocate two buffers per timeslot */ 686 if (nts == 32) 687 sc->m32_mem.cs[chan].itbs = 63; 688 else 689 sc->m32_mem.cs[chan].itbs = nts * 2; 690 691 /* Setup a transmit chain with one descriptor */ 692 /* XXX: we actually send a 1 byte packet */ 693 dp = mn_alloc_desc(); 694 MGETHDR(m, M_TRYWAIT, MT_DATA); 695 if (m == NULL) 696 return ENOBUFS; 697 m->m_pkthdr.len = 0; 698 dp->m = m; 699 dp->flags = 0xc0000000 + (1 << 16); 700 dp->next = vtophys(dp); 701 dp->vnext = 0; 702 dp->data = vtophys(sc->name); 703 sc->m32_mem.cs[chan].tdesc = vtophys(dp); 704 sc->ch[chan]->x1 = dp; 705 sc->ch[chan]->xl = dp; 706 707 /* Setup a receive chain with 5 + NTS descriptors */ 708 709 dp = mn_alloc_desc(); 710 m = NULL; 711 MGETHDR(m, M_TRYWAIT, MT_DATA); 712 if (m == NULL) { 713 mn_free_desc(dp); 714 return (ENOBUFS); 715 } 716 MCLGET(m, M_TRYWAIT); 717 if ((m->m_flags & M_EXT) == 0) { 718 mn_free_desc(dp); 719 m_freem(m); 720 return (ENOBUFS); 721 } 722 dp->m = m; 723 dp->data = vtophys(m->m_data); 724 dp->flags = 0x40000000; 725 dp->flags += 1600 << 16; 726 dp->next = vtophys(dp); 727 dp->vnext = 0; 728 sc->ch[chan]->rl = dp; 729 730 for (i = 0; i < (nts + 10); i++) { 731 dp2 = dp; 732 dp = mn_alloc_desc(); 733 m = NULL; 734 MGETHDR(m, M_TRYWAIT, MT_DATA); 735 if (m == NULL) { 736 mn_free_desc(dp); 737 m_freem(m); 738 return (ENOBUFS); 739 } 740 MCLGET(m, M_TRYWAIT); 741 if ((m->m_flags & M_EXT) == 0) { 742 mn_free_desc(dp); 743 m_freem(m); 744 return (ENOBUFS); 745 } 746 dp->m = m; 747 dp->data = vtophys(m->m_data); 748 dp->flags = 0x00000000; 749 dp->flags += 1600 << 16; 750 dp->next = vtophys(dp2); 751 dp->vnext = dp2; 752 } 753 sc->m32_mem.cs[chan].rdesc = vtophys(dp); 754 sc->ch[chan]->r1 = dp; 755 756 /* Initialize this channel */ 757 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 758 sc->m32x->cmd = 0x1; 759 DELAY(1000); 760 u = sc->m32x->stat; 761 if (!(u & 1)) 762 printf("%s: init chan %d stat %08x\n", sc->name, chan, u); 763 sc->m32x->stat = 1; 764 /* probably not at splnet, force outward queueing */ 765 NG_HOOK_FORCE_QUEUE(NG_HOOK_PEER(hook)); 766 767 return (0); 768} 769 770/* 771 * CLOSE 772 */ 773static int 774ngmn_disconnect(hook_p hook) 775{ 776 int chan, i; 777 struct softc *sc; 778 struct schan *sch; 779 struct trxd *dp, *dp2; 780 u_int32_t u; 781 782 sch = NG_HOOK_PRIVATE(hook); 783 chan = sch->chan; 784 sc = sch->sc; 785 786 if (sch->state == DOWN) 787 return (0); 788 sch->state = DOWN; 789 790 /* Set receiver & transmitter off */ 791 sc->m32_mem.cs[chan].flags = 0x80920006; 792 sc->m32_mem.cs[chan].itbs = 0; 793 794 /* free the timeslots */ 795 for (i = 0; i < 32; i++) 796 if (sc->ch[chan]->ts & (1 << i)) 797 sc->m32_mem.ts[i] = 0x20002000; 798 799 /* Initialize this channel */ 800 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 801 sc->m32x->cmd = 0x1; 802 DELAY(30); 803 u = sc->m32x->stat; 804 if (!(u & 1)) 805 printf("%s: zap chan %d stat %08x\n", sc->name, chan, u); 806 sc->m32x->stat = 1; 807 808 /* Free all receive descriptors and mbufs */ 809 for (dp = sc->ch[chan]->r1; dp ; dp = dp2) { 810 if (dp->m) 811 m_freem(dp->m); 812 sc->ch[chan]->r1 = dp2 = dp->vnext; 813 mn_free_desc(dp); 814 } 815 816 /* Free all transmit descriptors and mbufs */ 817 for (dp = sc->ch[chan]->x1; dp ; dp = dp2) { 818 if (dp->m) { 819 sc->ch[chan]->tx_pending -= dp->m->m_pkthdr.len; 820 m_freem(dp->m); 821 } 822 sc->ch[chan]->x1 = dp2 = dp->vnext; 823 mn_free_desc(dp); 824 } 825 sc->nhooks--; 826 return(0); 827} 828 829/* 830 * Create a new channel. 831 */ 832static void 833mn_create_channel(struct softc *sc, int chan) 834{ 835 struct schan *sch; 836 837 sch = sc->ch[chan] = (struct schan *)malloc(sizeof *sc->ch[chan], 838 M_MN, M_WAITOK | M_ZERO); 839 sch->sc = sc; 840 sch->state = DOWN; 841 sch->chan = chan; 842 sprintf(sch->name, "%s%d", sc->name, chan); 843 return; 844} 845 846#ifdef notyet 847/* 848 * Dump Munich32x state 849 */ 850static void 851m32_dump(struct softc *sc) 852{ 853 u_int32_t *tp4; 854 int i, j; 855 856 printf("mn%d: MUNICH32X dump\n", sc->unit); 857 tp4 = (u_int32_t *)sc->m0v; 858 for(j = 0; j < 64; j += 8) { 859 printf("%02x", j * sizeof *tp4); 860 for(i = 0; i < 8; i++) 861 printf(" %08x", tp4[i+j]); 862 printf("\n"); 863 } 864 for(j = 0; j < M32_CHAN; j++) { 865 if (!sc->ch[j]) 866 continue; 867 printf("CH%d: state %d ts %08x", 868 j, sc->ch[j]->state, sc->ch[j]->ts); 869 printf(" %08x %08x %08x %08x %08x %08x\n", 870 sc->m32_mem.cs[j].flags, 871 sc->m32_mem.cs[j].rdesc, 872 sc->m32_mem.cs[j].tdesc, 873 sc->m32_mem.cs[j].itbs, 874 sc->m32_mem.crxd[j], 875 sc->m32_mem.ctxd[j] ); 876 } 877} 878 879/* 880 * Dump Falch54 state 881 */ 882static void 883f54_dump(struct softc *sc) 884{ 885 u_int8_t *tp1; 886 int i, j; 887 888 printf("%s: FALC54 dump\n", sc->name); 889 tp1 = (u_int8_t *)sc->m1v; 890 for(j = 0; j < 128; j += 16) { 891 printf("%s: %02x |", sc->name, j * sizeof *tp1); 892 for(i = 0; i < 16; i++) 893 printf(" %02x", tp1[i+j]); 894 printf("\n"); 895 } 896} 897#endif /* notyet */ 898 899/* 900 * Init Munich32x 901 */ 902static void 903m32_init(struct softc *sc) 904{ 905 906 sc->m32x->conf = 0x00000000; 907 sc->m32x->mode1 = 0x81048000 + 1600; /* XXX: temp */ 908#if 1 909 sc->m32x->mode2 = 0x00000081; 910 sc->m32x->txpoll = 0xffffffff; 911#elif 1 912 sc->m32x->mode2 = 0x00000081; 913 sc->m32x->txpoll = 0xffffffff; 914#else 915 sc->m32x->mode2 = 0x00000101; 916#endif 917 sc->m32x->lconf = 0x6060009B; 918 sc->m32x->imask = 0x00000000; 919} 920 921/* 922 * Init the Falc54 923 */ 924static void 925f54_init(struct softc *sc) 926{ 927 sc->f54w->ipc = 0x07; 928 929 sc->f54w->xpm0 = 0xbd; 930 sc->f54w->xpm1 = 0x03; 931 sc->f54w->xpm2 = 0x00; 932 933 sc->f54w->imr0 = 0x18; /* RMB, CASC */ 934 sc->f54w->imr1 = 0x08; /* XMB */ 935 sc->f54w->imr2 = 0x00; 936 sc->f54w->imr3 = 0x38; /* LMFA16, AIS16, RA16 */ 937 sc->f54w->imr4 = 0x00; 938 939 sc->f54w->fmr0 = 0xf0; /* X: HDB3, R: HDB3 */ 940 sc->f54w->fmr1 = 0x0e; /* Send CRC4, 2Mbit, ECM */ 941 if (sc->framing == E1) 942 sc->f54w->fmr2 = 0x03; /* Auto Rem-Alarm, Auto resync */ 943 else if (sc->framing == E1U) 944 sc->f54w->fmr2 = 0x33; /* dais, rtm, Auto Rem-Alarm, Auto resync */ 945 946 sc->f54w->lim1 = 0xb0; /* XCLK=8kHz, .62V threshold */ 947 sc->f54w->pcd = 0x0a; 948 sc->f54w->pcr = 0x15; 949 sc->f54w->xsw = 0x9f; /* fmr4 */ 950 if (sc->framing == E1) 951 sc->f54w->xsp = 0x1c; /* fmr5 */ 952 else if (sc->framing == E1U) 953 sc->f54w->xsp = 0x3c; /* tt0, fmr5 */ 954 sc->f54w->xc0 = 0x07; 955 sc->f54w->xc1 = 0x3d; 956 sc->f54w->rc0 = 0x05; 957 sc->f54w->rc1 = 0x00; 958 sc->f54w->cmdr = 0x51; 959} 960 961static int 962mn_reset(struct softc *sc) 963{ 964 u_int32_t u; 965 int i; 966 967 sc->m32x->ccba = vtophys(&sc->m32_mem.csa); 968 sc->m32_mem.csa = vtophys(&sc->m32_mem.ccb); 969 970 bzero(sc->tiqb, sizeof sc->tiqb); 971 sc->m32x->tiqba = vtophys(&sc->tiqb); 972 sc->m32x->tiql = NIQB / 16 - 1; 973 974 bzero(sc->riqb, sizeof sc->riqb); 975 sc->m32x->riqba = vtophys(&sc->riqb); 976 sc->m32x->riql = NIQB / 16 - 1; 977 978 bzero(sc->ltiqb, sizeof sc->ltiqb); 979 sc->m32x->ltiqba = vtophys(&sc->ltiqb); 980 sc->m32x->ltiql = NIQB / 16 - 1; 981 982 bzero(sc->lriqb, sizeof sc->lriqb); 983 sc->m32x->lriqba = vtophys(&sc->lriqb); 984 sc->m32x->lriql = NIQB / 16 - 1; 985 986 bzero(sc->piqb, sizeof sc->piqb); 987 sc->m32x->piqba = vtophys(&sc->piqb); 988 sc->m32x->piql = NIQB / 16 - 1; 989 990 m32_init(sc); 991 f54_init(sc); 992 993 u = sc->m32x->stat; 994 sc->m32x->stat = u; 995 sc->m32_mem.ccb = 0x4; 996 sc->m32x->cmd = 0x1; 997 DELAY(1000); 998 u = sc->m32x->stat; 999 sc->m32x->stat = u; 1000 1001 /* set all timeslots to known state */ 1002 for (i = 0; i < 32; i++) 1003 sc->m32_mem.ts[i] = 0x20002000; 1004 1005 if (!(u & 1)) { 1006 printf( 1007"mn%d: WARNING: Controller failed the PCI bus-master test.\n" 1008"mn%d: WARNING: Use a PCI slot which can support bus-master cards.\n", 1009 sc->unit, sc->unit); 1010 return (0); 1011 } 1012 return (1); 1013} 1014 1015/* 1016 * FALC54 interrupt handling 1017 */ 1018static void 1019f54_intr(struct softc *sc) 1020{ 1021 unsigned g, u, s; 1022 1023 g = sc->f54r->gis; 1024 u = sc->f54r->isr0 << 24; 1025 u |= sc->f54r->isr1 << 16; 1026 u |= sc->f54r->isr2 << 8; 1027 u |= sc->f54r->isr3; 1028 sc->falc_irq = u; 1029 /* don't chat about the 1 sec heart beat */ 1030 if (u & ~0x40) { 1031#if 0 1032 printf("%s*: FALC54 IRQ GIS:%02x %b\n", sc->name, g, u, "\20" 1033 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 1034 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 1035 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 1036 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 1037#endif 1038 s = sc->f54r->frs0 << 24; 1039 s |= sc->f54r->frs1 << 16; 1040 s |= sc->f54r->rsw << 8; 1041 s |= sc->f54r->rsp; 1042 sc->falc_state = s; 1043 1044 s &= ~0x01844038; /* undefined or static bits */ 1045 s &= ~0x00009fc7; /* bits we don't care about */ 1046 s &= ~0x00780000; /* XXX: TS16 related */ 1047 s &= ~0x06000000; /* XXX: Multiframe related */ 1048#if 0 1049 printf("%s*: FALC54 Status %b\n", sc->name, s, "\20" 1050 "\40LOS\37AIS\36LFA\35RRA\34AUXP\33NMF\32LMFA\31frs0.0" 1051 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS\24TS16LFA\23frs1.2\22XLS\21XLO" 1052 "\20RS1\17rsw.6\16RRA\15RY0\14RY1\13RY2\12RY3\11RY4" 1053 "\10SI1\7SI2\6rsp.5\5rsp.4\4rsp.3\3RSIF\2RS13\1RS15"); 1054#endif 1055 if (s != sc->framer_state) { 1056#if 0 1057 for (i = 0; i < M32_CHAN; i++) { 1058 if (!sc->ch[i]) 1059 continue; 1060 sp = &sc->ch[i]->ifsppp; 1061 if (!(sp->pp_if.if_flags & IFF_UP)) 1062 continue; 1063 if (s) 1064 timeout((timeout_t *)sp->pp_down, sp, 1 * hz); 1065 else 1066 timeout((timeout_t *)sp->pp_up, sp, 1 * hz); 1067 } 1068#endif 1069 sc->framer_state = s; 1070 } 1071 } 1072 /* Once per second check error counters */ 1073 /* XXX: not clear if this is actually ok */ 1074 if (!(u & 0x40)) 1075 return; 1076 sc->cnt_fec += sc->f54r->fec; 1077 sc->cnt_cvc += sc->f54r->cvc; 1078 sc->cnt_cec1 += sc->f54r->cec1; 1079 sc->cnt_ebc += sc->f54r->ebc; 1080 sc->cnt_cec2 += sc->f54r->cec2; 1081 sc->cnt_cec3 += sc->f54r->cec3; 1082 sc->cnt_rbc += sc->f54r->rbc; 1083} 1084 1085/* 1086 * Transmit interrupt for one channel 1087 */ 1088static void 1089mn_tx_intr(struct softc *sc, u_int32_t vector) 1090{ 1091 u_int32_t chan; 1092 struct trxd *dp; 1093 struct mbuf *m; 1094 1095 chan = vector & 0x1f; 1096 if (!sc->ch[chan]) 1097 return; 1098 if (sc->ch[chan]->state != UP) { 1099 printf("%s: tx_intr when not UP\n", sc->name); 1100 return; 1101 } 1102 for (;;) { 1103 dp = sc->ch[chan]->x1; 1104 if (vtophys(dp) == sc->m32_mem.ctxd[chan]) 1105 return; 1106 m = dp->m; 1107 if (m) { 1108#if 0 1109 printf("%d = %d - %d (%p)\n", 1110 sc->ch[chan]->tx_pending - m->m_pkthdr.len, 1111 sc->ch[chan]->tx_pending , m->m_pkthdr.len, m); 1112#endif 1113 sc->ch[chan]->tx_pending -= m->m_pkthdr.len; 1114 m_freem(m); 1115 } 1116 sc->ch[chan]->last_xmit = time_second; 1117 sc->ch[chan]->x1 = dp->vnext; 1118 mn_free_desc(dp); 1119 } 1120} 1121 1122/* 1123 * Receive interrupt for one channel 1124 */ 1125static void 1126mn_rx_intr(struct softc *sc, u_int32_t vector) 1127{ 1128 u_int32_t chan, err; 1129 struct trxd *dp; 1130 struct mbuf *m; 1131 struct schan *sch; 1132 1133 chan = vector & 0x1f; 1134 if (!sc->ch[chan]) 1135 return; 1136 sch = sc->ch[chan]; 1137 if (sch->state != UP) { 1138 printf("%s: rx_intr when not UP\n", sc->name); 1139 return; 1140 } 1141 vector &= ~0x1f; 1142 if (vector == 0x30000b00) 1143 sch->rx_error++; 1144 for (;;) { 1145 dp = sch->r1; 1146 if (vtophys(dp) == sc->m32_mem.crxd[chan]) 1147 return; 1148 m = dp->m; 1149 dp->m = 0; 1150 m->m_pkthdr.len = m->m_len = (dp->status >> 16) & 0x1fff; 1151 err = (dp->status >> 8) & 0xff; 1152 if (!err) { 1153 int error; 1154 NG_SEND_DATA_ONLY(error, sch->hook, m); 1155 sch->last_recv = time_second; 1156 /* we could be down by now... */ 1157 if (sch->state != UP) 1158 return; 1159 } else if (err & 0x40) { 1160 sch->short_error++; 1161 } else if (err & 0x10) { 1162 sch->crc_error++; 1163 } else if (err & 0x08) { 1164 sch->dribble_error++; 1165 } else if (err & 0x04) { 1166 sch->long_error++; 1167 } else if (err & 0x02) { 1168 sch->abort_error++; 1169 } else if (err & 0x01) { 1170 sch->overflow_error++; 1171 } 1172 if (err) { 1173 sch->last_rxerr = time_second; 1174 sch->prev_error = sch->last_error; 1175 sch->last_error = err; 1176 } 1177 1178 sc->ch[chan]->r1 = dp->vnext; 1179 1180 /* Replenish desc + mbuf supplies */ 1181 if (!m) { 1182 MGETHDR(m, M_DONTWAIT, MT_DATA); 1183 if (m == NULL) { 1184 mn_free_desc(dp); 1185 return; /* ENOBUFS */ 1186 } 1187 MCLGET(m, M_DONTWAIT); 1188 if((m->m_flags & M_EXT) == 0) { 1189 mn_free_desc(dp); 1190 m_freem(m); 1191 return; /* ENOBUFS */ 1192 } 1193 } 1194 dp->m = m; 1195 dp->data = vtophys(m->m_data); 1196 dp->flags = 0x40000000; 1197 dp->flags += 1600 << 16; 1198 dp->next = vtophys(dp); 1199 dp->vnext = 0; 1200 sc->ch[chan]->rl->next = vtophys(dp); 1201 sc->ch[chan]->rl->vnext = dp; 1202 sc->ch[chan]->rl->flags &= ~0x40000000; 1203 sc->ch[chan]->rl = dp; 1204 } 1205} 1206 1207 1208/* 1209 * Interupt handler 1210 */ 1211 1212static void 1213mn_intr(void *xsc) 1214{ 1215 struct softc *sc; 1216 u_int32_t stat, lstat, u; 1217 int i, j; 1218 1219 sc = xsc; 1220 stat = sc->m32x->stat; 1221 lstat = sc->m32x->lstat; 1222#if 0 1223 if (!stat && !(lstat & 2)) 1224 return; 1225#endif 1226 1227 if (stat & ~0xc200) { 1228 printf("%s: I stat=%08x lstat=%08x\n", sc->name, stat, lstat); 1229 } 1230 1231 if ((stat & 0x200) || (lstat & 2)) 1232 f54_intr(sc); 1233 1234 for (j = i = 0; i < 64; i ++) { 1235 u = sc->riqb[i]; 1236 if (u) { 1237 sc->riqb[i] = 0; 1238 mn_rx_intr(sc, u); 1239 if ((u & ~0x1f) == 0x30000800 || (u & ~0x1f) == 0x30000b00) 1240 continue; 1241 u &= ~0x30000400; /* bits we don't care about */ 1242 if ((u & ~0x1f) == 0x00000900) 1243 continue; 1244 if (!(u & ~0x1f)) 1245 continue; 1246 if (!j) 1247 printf("%s*: RIQB:", sc->name); 1248 printf(" [%d]=%08x", i, u); 1249 j++; 1250 } 1251 } 1252 if (j) 1253 printf("\n"); 1254 1255 for (j = i = 0; i < 64; i ++) { 1256 u = sc->tiqb[i]; 1257 if (u) { 1258 sc->tiqb[i] = 0; 1259 mn_tx_intr(sc, u); 1260 if ((u & ~0x1f) == 0x20000800) 1261 continue; 1262 u &= ~0x20000000; /* bits we don't care about */ 1263 if (!u) 1264 continue; 1265 if (!j) 1266 printf("%s*: TIQB:", sc->name); 1267 printf(" [%d]=%08x", i, u); 1268 j++; 1269 } 1270 } 1271 if (j) 1272 printf("\n"); 1273 sc->m32x->stat = stat; 1274} 1275 1276static void 1277mn_timeout(void *xsc) 1278{ 1279 static int round = 0; 1280 struct softc *sc; 1281 1282 mn_intr(xsc); 1283 sc = xsc; 1284 timeout(mn_timeout, xsc, 10 * hz); 1285 round++; 1286 if (round == 2) { 1287 sc->m32_mem.ccb = 0x00008004; 1288 sc->m32x->cmd = 0x1; 1289 } else if (round > 2) { 1290 printf("%s: timeout\n", sc->name); 1291 } 1292} 1293 1294/* 1295 * PCI initialization stuff 1296 */ 1297 1298static int 1299mn_probe (device_t self) 1300{ 1301 u_int id = pci_get_devid(self); 1302 1303 if (sizeof (struct m32xreg) != 256) { 1304 printf("MN: sizeof(struct m32xreg) = %d, should have been 256\n", sizeof (struct m32xreg)); 1305 return (ENXIO); 1306 } 1307 if (sizeof (struct f54rreg) != 128) { 1308 printf("MN: sizeof(struct f54rreg) = %d, should have been 128\n", sizeof (struct f54rreg)); 1309 return (ENXIO); 1310 } 1311 if (sizeof (struct f54wreg) != 128) { 1312 printf("MN: sizeof(struct f54wreg) = %d, should have been 128\n", sizeof (struct f54wreg)); 1313 return (ENXIO); 1314 } 1315 1316 if (id != 0x2101110a) 1317 return (ENXIO); 1318 1319 device_set_desc_copy(self, "Munich32X E1/T1 HDLC Controller"); 1320 return (0); 1321} 1322 1323static int 1324mn_attach (device_t self) 1325{ 1326 struct softc *sc; 1327 u_int32_t u; 1328 u_int32_t ver; 1329 static int once; 1330 int rid, error; 1331 struct resource *res; 1332 1333 if (!once) { 1334 if (ng_newtype(&mntypestruct)) 1335 printf("ng_newtype failed\n"); 1336 once++; 1337 } 1338 1339 sc = (struct softc *)malloc(sizeof *sc, M_MN, M_WAITOK | M_ZERO); 1340 device_set_softc(self, sc); 1341 1342 sc->dev = self; 1343 sc->unit = device_get_unit(self); 1344 sc->framing = E1; 1345 sprintf(sc->name, "mn%d", sc->unit); 1346 1347 rid = PCIR_MAPS; 1348 res = bus_alloc_resource(self, SYS_RES_MEMORY, &rid, 1349 0, ~0, 1, RF_ACTIVE); 1350 if (res == NULL) { 1351 device_printf(self, "Could not map memory\n"); 1352 return ENXIO; 1353 } 1354 sc->m0v = rman_get_virtual(res); 1355 sc->m0p = rman_get_start(res); 1356 1357 rid = PCIR_MAPS + 4; 1358 res = bus_alloc_resource(self, SYS_RES_MEMORY, &rid, 1359 0, ~0, 1, RF_ACTIVE); 1360 if (res == NULL) { 1361 device_printf(self, "Could not map memory\n"); 1362 return ENXIO; 1363 } 1364 sc->m1v = rman_get_virtual(res); 1365 sc->m1p = rman_get_start(res); 1366 1367 /* Allocate interrupt */ 1368 rid = 0; 1369 sc->irq = bus_alloc_resource(self, SYS_RES_IRQ, &rid, 0, ~0, 1370 1, RF_SHAREABLE | RF_ACTIVE); 1371 1372 if (sc->irq == NULL) { 1373 printf("couldn't map interrupt\n"); 1374 return(ENXIO); 1375 } 1376 1377 error = bus_setup_intr(self, sc->irq, INTR_TYPE_NET, mn_intr, sc, &sc->intrhand); 1378 1379 if (error) { 1380 printf("couldn't set up irq\n"); 1381 return(ENXIO); 1382 } 1383 1384 u = pci_read_config(self, PCIR_COMMAND, 1); 1385 printf("%x\n", u); 1386 pci_write_config(self, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN, 1); 1387#if 0 1388 pci_write_config(self, PCIR_COMMAND, 0x02800046, 4); 1389#endif 1390 u = pci_read_config(self, PCIR_COMMAND, 1); 1391 printf("%x\n", u); 1392 1393 ver = pci_get_revid(self); 1394 1395 sc->m32x = (struct m32xreg *) sc->m0v; 1396 sc->f54w = (struct f54wreg *) sc->m1v; 1397 sc->f54r = (struct f54rreg *) sc->m1v; 1398 1399 /* We must reset before poking at FALC54 registers */ 1400 u = mn_reset(sc); 1401 if (!u) 1402 return (0); 1403 1404 printf("mn%d: Munich32X", sc->unit); 1405 switch (ver) { 1406 case 0x13: 1407 printf(" Rev 2.2"); 1408 break; 1409 default: 1410 printf(" Rev 0x%x\n", ver); 1411 } 1412 printf(", Falc54"); 1413 switch (sc->f54r->vstr) { 1414 case 0: 1415 printf(" Rev < 1.3\n"); 1416 break; 1417 case 1: 1418 printf(" Rev 1.3\n"); 1419 break; 1420 case 2: 1421 printf(" Rev 1.4\n"); 1422 break; 1423 case 0x10: 1424 printf("-LH Rev 1.1\n"); 1425 break; 1426 case 0x13: 1427 printf("-LH Rev 1.3\n"); 1428 break; 1429 default: 1430 printf(" Rev 0x%x\n", sc->f54r->vstr); 1431 } 1432 1433 if (ng_make_node_common(&mntypestruct, &sc->node) != 0) { 1434 printf("ng_make_node_common failed\n"); 1435 return (0); 1436 } 1437 NG_NODE_SET_PRIVATE(sc->node, sc); 1438 sprintf(sc->nodename, "%s%d", NG_MN_NODE_TYPE, sc->unit); 1439 if (ng_name_node(sc->node, sc->nodename)) { 1440 NG_NODE_UNREF(sc->node); 1441 return (0); 1442 } 1443 1444 return (0); 1445} 1446 1447 1448static device_method_t mn_methods[] = { 1449 /* Device interface */ 1450 DEVMETHOD(device_probe, mn_probe), 1451 DEVMETHOD(device_attach, mn_attach), 1452 DEVMETHOD(device_suspend, bus_generic_suspend), 1453 DEVMETHOD(device_resume, bus_generic_resume), 1454 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1455 1456 {0, 0} 1457}; 1458 1459static driver_t mn_driver = { 1460 "mn", 1461 mn_methods, 1462 0 1463}; 1464 1465static devclass_t mn_devclass; 1466 1467DRIVER_MODULE(mn, pci, mn_driver, mn_devclass, 0, 0); 1468