if_mn.c revision 70068
1/* 2 * ---------------------------------------------------------------------------- 3 * "THE BEER-WARE LICENSE" (Revision 42): 4 * <phk@FreeBSD.org> wrote this file. As long as you retain this notice you 5 * can do whatever you want with this stuff. If we meet some day, and you think 6 * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp 7 * ---------------------------------------------------------------------------- 8 * 9 * $Id: if_mn.c,v 1.1 1999/02/01 13:06:40 phk Exp $ 10 * 11 * Driver for Siemens reference design card "Easy321-R1". 12 * 13 * This card contains a FALC54 E1/T1 framer and a MUNICH32X 32-channel HDLC 14 * controller. 15 * 16 * The driver supports E1 mode with up to 31 channels. We send CRC4 but don't 17 * check it coming in. 18 * 19 * The FALC54 and MUNICH32X have far too many registers and weird modes for 20 * comfort, so I have not bothered typing it all into a "fooreg.h" file, 21 * you will (badly!) need the documentation anyway if you want to mess with 22 * this gadget. 23 * 24 * $FreeBSD: head/sys/pci/if_mn.c 70068 2000-12-15 21:06:55Z bmilekic $ 25 */ 26 27/* 28 * Stuff to describe the MUNIC32X and FALC54 chips. 29 */ 30 31#define M32_CHAN 32 /* We have 32 channels */ 32#define M32_TS 32 /* We have 32 timeslots */ 33 34#define NG_MN_NODE_TYPE "mn" 35 36#include <sys/param.h> 37#include <sys/kernel.h> 38#include <sys/sysctl.h> 39#include <sys/bus.h> 40#include <sys/mbuf.h> 41#include <sys/systm.h> 42#include <sys/malloc.h> 43 44#include <pci/pcireg.h> 45#include <pci/pcivar.h> 46#include "pci_if.h" 47 48#include <machine/bus.h> 49#include <machine/resource.h> 50 51#include <sys/rman.h> 52 53#include <vm/vm.h> 54#include <vm/pmap.h> 55 56#include <netgraph/ng_message.h> 57#include <netgraph/netgraph.h> 58 59 60static int mn_maxlatency = 1000; 61SYSCTL_INT(_debug, OID_AUTO, mn_maxlatency, CTLFLAG_RW, 62 &mn_maxlatency, 0, 63 "The number of milliseconds a packet is allowed to spend in the output queue. " 64 "If the output queue is longer than this number of milliseconds when the packet " 65 "arrives for output, the packet will be dropped." 66); 67 68#ifndef NMN 69/* Most machines don't support more than 4 busmaster PCI slots, if even that many */ 70#define NMN 4 71#endif 72 73/* From: PEB 20321 data sheet, p187, table 22 */ 74struct m32xreg { 75 u_int32_t conf, cmd, stat, imask; 76 u_int32_t fill10, piqba, piql, fill1c; 77 u_int32_t mode1, mode2, ccba, txpoll; 78 u_int32_t tiqba, tiql, riqba, riql; 79 u_int32_t lconf, lccba, fill48, ltran; 80 u_int32_t ltiqba, ltiql, lriqba, lriql; 81 u_int32_t lreg0, lreg1, lreg2, lreg3; 82 u_int32_t lreg4, lreg5, lre6, lstat; 83 u_int32_t gpdir, gpdata, gpod, fill8c; 84 u_int32_t ssccon, sscbr, ssctb, sscrb; 85 u_int32_t ssccse, sscim, fillab, fillac; 86 u_int32_t iomcon1, iomcon2, iomstat, fillbc; 87 u_int32_t iomcit0, iomcit1, iomcir0, iomcir1; 88 u_int32_t iomtmo, iomrmo, filld8, filldc; 89 u_int32_t mbcmd, mbdata1, mbdata2, mbdata3; 90 u_int32_t mbdata4, mbdata5, mbdata6, mbdata7; 91}; 92 93/* From: PEB 2254 data sheet, p80, table 10 */ 94struct f54wreg { 95 u_int16_t xfifo; 96 u_int8_t cmdr, mode, rah1, rah2, ral1, ral2; 97 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 98 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 99 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 100 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 101 u_int8_t test1, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr3; 102 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 103 u_int8_t lim2, fill39[7]; 104 u_int8_t fill40[8]; 105 u_int8_t fill48[8]; 106 u_int8_t fill50[8]; 107 u_int8_t fill58[8]; 108 u_int8_t dec, fill61, test2, fill63[5]; 109 u_int8_t fill68[8]; 110 u_int8_t xs[16]; 111}; 112 113/* From: PEB 2254 data sheet, p117, table 10 */ 114struct f54rreg { 115 u_int16_t rfifo; 116 u_int8_t fill2, mode, rah1, rah2, ral1, ral2; 117 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 118 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 119 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 120 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 121 u_int8_t test, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr13; 122 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 123 u_int8_t lim2, fill39[7]; 124 u_int8_t fill40[8]; 125 u_int8_t fill48[4], frs0, frs1, rsw, rsp; 126 u_int16_t fec, cvc, cec1, ebc; 127 u_int16_t cec2, cec3; 128 u_int8_t rsa4, rsa5, rsa6, rsa7; 129 u_int8_t rsa8, rsa6s, tsr0, tsr1, sis, rsis; 130 u_int16_t rbc; 131 u_int8_t isr0, isr1, isr2, isr3, fill6c, fill6d, gis, vstr; 132 u_int8_t rs[16]; 133}; 134 135/* Transmit & receive descriptors */ 136struct trxd { 137 u_int32_t flags; 138 vm_offset_t next; 139 vm_offset_t data; 140 u_int32_t status; /* only used for receive */ 141 struct mbuf *m; /* software use only */ 142 struct trxd *vnext; /* software use only */ 143}; 144 145/* Channel specification */ 146struct cspec { 147 u_int32_t flags; 148 vm_offset_t rdesc; 149 vm_offset_t tdesc; 150 u_int32_t itbs; 151}; 152 153struct m32_mem { 154 vm_offset_t csa; 155 u_int32_t ccb; 156 u_int32_t reserve1[2]; 157 u_int32_t ts[M32_TS]; 158 struct cspec cs[M32_CHAN]; 159 vm_offset_t crxd[M32_CHAN]; 160 vm_offset_t ctxd[M32_CHAN]; 161}; 162 163struct softc; 164struct sockaddr; 165struct rtentry; 166 167static int mn_probe (device_t self); 168static int mn_attach (device_t self); 169static void mn_create_channel(struct softc *sc, int chan); 170static int mn_reset(struct softc *sc); 171static struct trxd * mn_alloc_desc(void); 172static void mn_free_desc(struct trxd *dp); 173static void mn_intr(void *xsc); 174static u_int32_t mn_parse_ts(const char *s, int *nbit); 175#ifdef notyet 176static void m32_dump(struct softc *sc); 177static void f54_dump(struct softc *sc); 178static void mn_fmt_ts(char *p, u_int32_t ts); 179#endif /* notyet */ 180 181static ng_constructor_t ngmn_constructor; 182static ng_rcvmsg_t ngmn_rcvmsg; 183static ng_shutdown_t ngmn_shutdown; 184static ng_newhook_t ngmn_newhook; 185static ng_connect_t ngmn_connect; 186static ng_rcvdata_t ngmn_rcvdata; 187static ng_disconnect_t ngmn_disconnect; 188 189static struct ng_type mntypestruct = { 190 NG_VERSION, 191 NG_MN_NODE_TYPE, 192 NULL, 193 ngmn_constructor, 194 ngmn_rcvmsg, 195 ngmn_shutdown, 196 ngmn_newhook, 197 NULL, 198 ngmn_connect, 199 ngmn_rcvdata, 200 ngmn_disconnect, 201 NULL 202}; 203 204static MALLOC_DEFINE(M_MN, "mn", "Mx driver related"); 205 206#define NIQB 64 207 208struct schan { 209 enum {DOWN, UP} state; 210 struct softc *sc; 211 int chan; 212 u_int32_t ts; 213 char name[8]; 214 struct trxd *r1, *rl; 215 struct trxd *x1, *xl; 216 hook_p hook; 217 218 time_t last_recv; 219 time_t last_rxerr; 220 time_t last_xmit; 221 222 u_long rx_error; 223 224 u_long short_error; 225 u_long crc_error; 226 u_long dribble_error; 227 u_long long_error; 228 u_long abort_error; 229 u_long overflow_error; 230 231 int last_error; 232 int prev_error; 233 234 u_long tx_pending; 235 u_long tx_limit; 236}; 237 238struct softc { 239 int unit; 240 device_t dev; 241 struct resource *irq; 242 void *intrhand; 243 void *m0v, *m1v; 244 vm_offset_t m0p, m1p; 245 struct m32xreg *m32x; 246 struct f54wreg *f54w; 247 struct f54rreg *f54r; 248 struct m32_mem m32_mem; 249 u_int32_t tiqb[NIQB]; 250 u_int32_t riqb[NIQB]; 251 u_int32_t piqb[NIQB]; 252 u_int32_t ltiqb[NIQB]; 253 u_int32_t lriqb[NIQB]; 254 char name[8]; 255 u_int32_t falc_irq, falc_state, framer_state; 256 struct schan *ch[M32_CHAN]; 257 char nodename[NG_NODELEN + 1]; 258 node_p node; 259 260 u_long cnt_fec; 261 u_long cnt_cvc; 262 u_long cnt_cec1; 263 u_long cnt_ebc; 264 u_long cnt_cec2; 265 u_long cnt_cec3; 266 u_long cnt_rbc; 267}; 268 269static int 270ngmn_constructor(node_p *nodep) 271{ 272 273 return (EINVAL); 274} 275 276static int 277ngmn_shutdown(node_p nodep) 278{ 279 280 return (EINVAL); 281} 282 283static int 284ngmn_rcvmsg(node_p node, struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp, hook_p lasthook) 285{ 286 struct softc *sc; 287 struct schan *sch; 288 char *arg; 289 int pos, i; 290 291 sc = node->private; 292 293 if (msg->header.typecookie != NGM_GENERIC_COOKIE || 294 msg->header.cmd != NGM_TEXT_STATUS) { 295 if (resp) 296 *resp = NULL; 297 FREE(msg, M_NETGRAPH); 298 return (EINVAL); 299 } 300 NG_MKRESPONSE(*resp, msg, sizeof(struct ng_mesg) + NG_TEXTRESPONSE, 301 M_NOWAIT); 302 if (*resp == NULL) { 303 FREE(msg, M_NETGRAPH); 304 return (ENOMEM); 305 } 306 arg = (char *)(*resp)->data; 307 pos = 0; 308 pos += sprintf(pos + arg,"Framer status %b;\n", sc->framer_state, "\20" 309 "\40LOS\37AIS\36LFA\35RRA" 310 "\34AUXP\33NMF\32LMFA\31frs0.0" 311 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 312 "\24TS16LFA\23frs1.2\22XLS\21XLO" 313 "\20RS1\17rsw.6\16RRA\15RY0" 314 "\14RY1\13RY2\12RY3\11RY4" 315 "\10SI1\7SI2\6rsp.5\5rsp.4" 316 "\4rsp.3\3RSIF\2RS13\1RS15"); 317 pos += sprintf(pos + arg," Framing errors: %lu", sc->cnt_fec); 318 pos += sprintf(pos + arg," Code Violations: %lu\n", sc->cnt_cvc); 319 320 pos += sprintf(pos + arg," Falc State %b;\n", sc->falc_state, "\20" 321 "\40LOS\37AIS\36LFA\35RRA" 322 "\34AUXP\33NMF\32LMFA\31frs0.0" 323 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 324 "\24TS16LFA\23frs1.2\22XLS\21XLO" 325 "\20RS1\17rsw.6\16RRA\15RY0" 326 "\14RY1\13RY2\12RY3\11RY4" 327 "\10SI1\7SI2\6rsp.5\5rsp.4" 328 "\4rsp.3\3RSIF\2RS13\1RS15"); 329 pos += sprintf(pos + arg, " Falc IRQ %b\n", sc->falc_irq, "\20" 330 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 331 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 332 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 333 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 334 for (i = 0; i < M32_CHAN; i++) { 335 if (!sc->ch[i]) 336 continue; 337 sch = sc->ch[i]; 338 339 pos += sprintf(arg + pos, " Chan %d <%s> ", 340 i, sch->hook->name); 341 342 pos += sprintf(arg + pos, " Last Rx: "); 343 if (sch->last_recv) 344 pos += sprintf(arg + pos, "%lu s", time_second - sch->last_recv); 345 else 346 pos += sprintf(arg + pos, "never"); 347 348 pos += sprintf(arg + pos, ", last RxErr: "); 349 if (sch->last_rxerr) 350 pos += sprintf(arg + pos, "%lu s", time_second - sch->last_rxerr); 351 else 352 pos += sprintf(arg + pos, "never"); 353 354 pos += sprintf(arg + pos, ", last Tx: "); 355 if (sch->last_xmit) 356 pos += sprintf(arg + pos, "%lu s\n", time_second - sch->last_xmit); 357 else 358 pos += sprintf(arg + pos, "never\n"); 359 360 pos += sprintf(arg + pos, " RX error(s) %lu", sch->rx_error); 361 pos += sprintf(arg + pos, " Short: %lu", sch->short_error); 362 pos += sprintf(arg + pos, " CRC: %lu", sch->crc_error); 363 pos += sprintf(arg + pos, " Mod8: %lu", sch->dribble_error); 364 pos += sprintf(arg + pos, " Long: %lu", sch->long_error); 365 pos += sprintf(arg + pos, " Abort: %lu", sch->abort_error); 366 pos += sprintf(arg + pos, " Overflow: %lu\n", sch->overflow_error); 367 368 pos += sprintf(arg + pos, " Last error: %b Prev error: %b\n", 369 sch->last_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN", 370 sch->prev_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN"); 371 pos += sprintf(arg + pos, " Xmit bytes pending %ld\n", 372 sch->tx_pending); 373 } 374 (*resp)->header.arglen = pos + 1; 375 FREE(msg, M_NETGRAPH); 376 return (0); 377} 378 379static int 380ngmn_newhook(node_p node, hook_p hook, const char *name) 381{ 382 u_int32_t ts, chan; 383 struct softc *sc; 384 int nbit; 385 386 sc = node->private; 387 388 if (name[0] != 't' || name[1] != 's') 389 return (EINVAL); 390 391 ts = mn_parse_ts(name + 2, &nbit); 392 if (ts == 0) 393 return (EINVAL); 394 chan = ffs(ts) - 1; 395 if (!sc->ch[chan]) 396 mn_create_channel(sc, chan); 397 else if (sc->ch[chan]->state == UP) 398 return (EBUSY); 399 sc->ch[chan]->ts = ts; 400 sc->ch[chan]->hook = hook; 401 sc->ch[chan]->tx_limit = nbit * 8; 402 hook->private = sc->ch[chan]; 403 return(0); 404} 405 406 407static struct trxd *mn_desc_free; 408 409static struct trxd * 410mn_alloc_desc(void) 411{ 412 struct trxd *dp; 413 414 dp = mn_desc_free; 415 if (dp) 416 mn_desc_free = dp->vnext; 417 else 418 dp = (struct trxd *)malloc(sizeof *dp, M_MN, M_NOWAIT); 419 return (dp); 420} 421 422static void 423mn_free_desc(struct trxd *dp) 424{ 425 dp->vnext = mn_desc_free; 426 mn_desc_free = dp; 427} 428 429static u_int32_t 430mn_parse_ts(const char *s, int *nbit) 431{ 432 unsigned r; 433 int i, j; 434 char *p; 435 436 r = 0; 437 j = 0; 438 *nbit = 0; 439 while(*s) { 440 i = strtol(s, &p, 0); 441 if (i < 1 || i > 31) 442 return (0); 443 while (j && j < i) { 444 r |= 1 << j++; 445 (*nbit)++; 446 } 447 j = 0; 448 r |= 1 << i; 449 (*nbit)++; 450 if (*p == ',') { 451 s = p + 1; 452 continue; 453 } else if (*p == '-') { 454 j = i; 455 s = p + 1; 456 continue; 457 } else if (!*p) { 458 break; 459 } else { 460 return (0); 461 } 462 } 463 return (r); 464} 465 466#ifdef notyet 467static void 468mn_fmt_ts(char *p, u_int32_t ts) 469{ 470 char *s; 471 int j; 472 473 s = ""; 474 ts &= 0xfffffffe; 475 for (j = 1; j < 32; j++) { 476 if (!(ts & (1 << j))) 477 continue; 478 sprintf(p, "%s%d", s, j); 479 p += strlen(p); 480 s = ","; 481 if (!(ts & (1 << (j+1)))) 482 continue; 483 for (; j < 32; j++) 484 if (!(ts & (1 << (j+1)))) 485 break; 486 sprintf(p, "-%d", j); 487 p += strlen(p); 488 s = ","; 489 } 490} 491#endif /* notyet */ 492 493/* 494 * OUTPUT 495 */ 496 497static int 498ngmn_rcvdata(hook_p hook, struct mbuf *m, meta_p meta, 499 struct mbuf **ret_m, meta_p *ret_meta, struct ng_mesg **resp) 500{ 501 struct mbuf *m2; 502 struct trxd *dp, *dp2; 503 struct schan *sch; 504 struct softc *sc; 505 int chan, pitch, len; 506 507 sch = hook->private; 508 sc = sch->sc; 509 chan = sch->chan; 510 511 if (sch->state != UP) { 512 NG_FREE_DATA(m, meta); 513 return (0); 514 } 515 if (sch->tx_pending + m->m_pkthdr.len > sch->tx_limit * mn_maxlatency) { 516 NG_FREE_DATA(m, meta); 517 return (0); 518 } 519 NG_FREE_META(meta); 520 pitch = 0; 521 m2 = m; 522 dp2 = sc->ch[chan]->xl; 523 len = m->m_pkthdr.len; 524 while (len) { 525 dp = mn_alloc_desc(); 526 if (!dp) { 527 pitch++; 528 m_freem(m); 529 sc->ch[chan]->xl = dp2; 530 dp = dp2->vnext; 531 while (dp) { 532 dp2 = dp->vnext; 533 mn_free_desc(dp); 534 dp = dp2; 535 } 536 sc->ch[chan]->xl->vnext = 0; 537 break; 538 } 539 dp->data = vtophys(m2->m_data); 540 dp->flags = m2->m_len << 16; 541 dp->flags += 1; 542 len -= m2->m_len; 543 dp->next = vtophys(dp); 544 dp->vnext = 0; 545 sc->ch[chan]->xl->next = vtophys(dp); 546 sc->ch[chan]->xl->vnext = dp; 547 sc->ch[chan]->xl = dp; 548 if (!len) { 549 dp->m = m; 550 dp->flags |= 0xc0000000; 551 dp2->flags &= ~0x40000000; 552 } else { 553 dp->m = 0; 554 m2 = m2->m_next; 555 } 556 } 557 if (pitch) 558 printf("%s%d: Short on mem, pitched %d packets\n", 559 sc->name, chan, pitch); 560 else { 561#if 0 562 printf("%d = %d + %d (%p)\n", 563 sch->tx_pending + m->m_pkthdr.len, 564 sch->tx_pending , m->m_pkthdr.len, m); 565#endif 566 sch->tx_pending += m->m_pkthdr.len; 567 } 568 return (0); 569} 570 571/* 572 * OPEN 573 */ 574static int 575ngmn_connect(hook_p hook) 576{ 577 int i, nts, chan; 578 struct trxd *dp, *dp2; 579 struct mbuf *m; 580 struct softc *sc; 581 struct schan *sch; 582 u_int32_t u; 583 584 sch = hook->private; 585 chan = sch->chan; 586 sc = sch->sc; 587 588 if (sch->state == UP) 589 return (0); 590 sch->state = UP; 591 592 /* Count and configure the timeslots for this channel */ 593 for (nts = i = 0; i < 32; i++) 594 if (sch->ts & (1 << i)) { 595 sc->m32_mem.ts[i] = 0x00ff00ff | 596 (chan << 24) | (chan << 8); 597 nts++; 598 } 599 600 /* Init the receiver & xmitter to HDLC */ 601 sc->m32_mem.cs[chan].flags = 0x80e90006; 602 /* Allocate two buffers per timeslot */ 603 sc->m32_mem.cs[chan].itbs = nts * 2; 604 605 /* Setup a transmit chain with one descriptor */ 606 /* XXX: we actually send a 1 byte packet */ 607 dp = mn_alloc_desc(); 608 MGETHDR(m, M_WAIT, MT_DATA); 609 if (m == NULL) 610 return ENOBUFS; 611 m->m_pkthdr.len = 0; 612 dp->m = m; 613 dp->flags = 0xc0000000 + (1 << 16); 614 dp->next = vtophys(dp); 615 dp->vnext = 0; 616 dp->data = vtophys(sc->name); 617 sc->m32_mem.cs[chan].tdesc = vtophys(dp); 618 sc->ch[chan]->x1 = dp; 619 sc->ch[chan]->xl = dp; 620 621 /* Setup a receive chain with 5 + NTS descriptors */ 622 623 dp = mn_alloc_desc(); 624 m = NULL; 625 MGETHDR(m, M_WAIT, MT_DATA); 626 if (m == NULL) { 627 mn_free_desc(dp); 628 return (ENOBUFS); 629 } 630 MCLGET(m, M_WAIT); 631 if ((m->m_flags & M_EXT) == 0) { 632 mn_free_desc(dp); 633 m_freem(m); 634 return (ENOBUFS); 635 } 636 dp->m = m; 637 dp->data = vtophys(m->m_data); 638 dp->flags = 0x40000000; 639 dp->flags += 1600 << 16; 640 dp->next = vtophys(dp); 641 dp->vnext = 0; 642 sc->ch[chan]->rl = dp; 643 644 for (i = 0; i < (nts + 10); i++) { 645 dp2 = dp; 646 dp = mn_alloc_desc(); 647 m = NULL; 648 MGETHDR(m, M_WAIT, MT_DATA); 649 if (m == NULL) { 650 mn_free_desc(dp); 651 m_freem(m); 652 return (ENOBUFS); 653 } 654 MCLGET(m, M_WAIT); 655 if ((m->m_flags & M_EXT) == 0) { 656 mn_free_desc(dp); 657 m_freem(m); 658 return (ENOBUFS); 659 } 660 dp->m = m; 661 dp->data = vtophys(m->m_data); 662 dp->flags = 0x00000000; 663 dp->flags += 1600 << 16; 664 dp->next = vtophys(dp2); 665 dp->vnext = dp2; 666 } 667 sc->m32_mem.cs[chan].rdesc = vtophys(dp); 668 sc->ch[chan]->r1 = dp; 669 670 /* Initialize this channel */ 671 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 672 sc->m32x->cmd = 0x1; 673 DELAY(1000); 674 u = sc->m32x->stat; 675 if (!(u & 1)) 676 printf("%s: init chan %d stat %08x\n", sc->name, chan, u); 677 sc->m32x->stat = 1; 678 /* probably not at splnet, force outward queueing */ 679 hook->peer->flags |= HK_QUEUE; 680 681 return (0); 682} 683 684/* 685 * CLOSE 686 */ 687static int 688ngmn_disconnect(hook_p hook) 689{ 690 int chan, i; 691 struct softc *sc; 692 struct schan *sch; 693 struct trxd *dp, *dp2; 694 u_int32_t u; 695 696 sch = hook->private; 697 chan = sch->chan; 698 sc = sch->sc; 699 700 if (sch->state == DOWN) 701 return (0); 702 sch->state = DOWN; 703 704 /* Set receiver & transmitter off */ 705 sc->m32_mem.cs[chan].flags = 0x80920006; 706 sc->m32_mem.cs[chan].itbs = 0; 707 708 /* free the timeslots */ 709 for (i = 0; i < 32; i++) 710 if (sc->ch[chan]->ts & (1 << i)) 711 sc->m32_mem.ts[i] = 0x20002000; 712 713 /* Initialize this channel */ 714 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 715 sc->m32x->cmd = 0x1; 716 DELAY(30); 717 u = sc->m32x->stat; 718 if (!(u & 1)) 719 printf("%s: zap chan %d stat %08x\n", sc->name, chan, u); 720 sc->m32x->stat = 1; 721 722 /* Free all receive descriptors and mbufs */ 723 for (dp = sc->ch[chan]->r1; dp ; dp = dp2) { 724 if (dp->m) 725 m_freem(dp->m); 726 sc->ch[chan]->r1 = dp2 = dp->vnext; 727 mn_free_desc(dp); 728 } 729 730 /* Free all transmit descriptors and mbufs */ 731 for (dp = sc->ch[chan]->x1; dp ; dp = dp2) { 732 if (dp->m) { 733 sc->ch[chan]->tx_pending -= dp->m->m_pkthdr.len; 734 m_freem(dp->m); 735 } 736 sc->ch[chan]->x1 = dp2 = dp->vnext; 737 mn_free_desc(dp); 738 } 739 return(0); 740} 741 742/* 743 * Create a new channel. 744 */ 745static void 746mn_create_channel(struct softc *sc, int chan) 747{ 748 struct schan *sch; 749 750 sch = sc->ch[chan] = (struct schan *)malloc(sizeof *sc->ch[chan], 751 M_MN, M_WAITOK | M_ZERO); 752 sch->sc = sc; 753 sch->state = DOWN; 754 sch->chan = chan; 755 sprintf(sch->name, "%s%d", sc->name, chan); 756 return; 757} 758 759#ifdef notyet 760/* 761 * Dump Munich32x state 762 */ 763static void 764m32_dump(struct softc *sc) 765{ 766 u_int32_t *tp4; 767 int i, j; 768 769 printf("mn%d: MUNICH32X dump\n", sc->unit); 770 tp4 = (u_int32_t *)sc->m0v; 771 for(j = 0; j < 64; j += 8) { 772 printf("%02x", j * sizeof *tp4); 773 for(i = 0; i < 8; i++) 774 printf(" %08x", tp4[i+j]); 775 printf("\n"); 776 } 777 for(j = 0; j < M32_CHAN; j++) { 778 if (!sc->ch[j]) 779 continue; 780 printf("CH%d: state %d ts %08x", 781 j, sc->ch[j]->state, sc->ch[j]->ts); 782 printf(" %08x %08x %08x %08x %08x %08x\n", 783 sc->m32_mem.cs[j].flags, 784 sc->m32_mem.cs[j].rdesc, 785 sc->m32_mem.cs[j].tdesc, 786 sc->m32_mem.cs[j].itbs, 787 sc->m32_mem.crxd[j], 788 sc->m32_mem.ctxd[j] ); 789 } 790} 791 792/* 793 * Dump Falch54 state 794 */ 795static void 796f54_dump(struct softc *sc) 797{ 798 u_int8_t *tp1; 799 int i, j; 800 801 printf("%s: FALC54 dump\n", sc->name); 802 tp1 = (u_int8_t *)sc->m1v; 803 for(j = 0; j < 128; j += 16) { 804 printf("%s: %02x |", sc->name, j * sizeof *tp1); 805 for(i = 0; i < 16; i++) 806 printf(" %02x", tp1[i+j]); 807 printf("\n"); 808 } 809} 810#endif /* notyet */ 811 812/* 813 * Init Munich32x 814 */ 815static void 816m32_init(struct softc *sc) 817{ 818 819 sc->m32x->conf = 0x00000000; 820 sc->m32x->mode1 = 0x81048000 + 1600; /* XXX: temp */ 821#if 1 822 sc->m32x->mode2 = 0x00000081; 823 sc->m32x->txpoll = 0xffffffff; 824#else 825 sc->m32x->mode2 = 0x00000101; 826#endif 827 sc->m32x->lconf = 0x6060009B; 828 sc->m32x->imask = 0x00000000; 829} 830 831/* 832 * Init the Falc54 833 */ 834static void 835f54_init(struct softc *sc) 836{ 837 sc->f54w->ipc = 0x07; 838 839 sc->f54w->xpm0 = 0xbd; 840 sc->f54w->xpm1 = 0x03; 841 sc->f54w->xpm2 = 0x00; 842 843 sc->f54w->imr0 = 0x18; /* RMB, CASC */ 844 sc->f54w->imr1 = 0x08; /* XMB */ 845 sc->f54w->imr2 = 0x00; 846 sc->f54w->imr3 = 0x38; /* LMFA16, AIS16, RA16 */ 847 sc->f54w->imr4 = 0x00; 848 849 sc->f54w->fmr0 = 0xf0; /* X: HDB3, R: HDB3 */ 850 sc->f54w->fmr1 = 0x0e; /* Send CRC4, 2Mbit, ECM */ 851 sc->f54w->fmr2 = 0x03; /* Auto Rem-Alarm, Auto resync */ 852 853 sc->f54w->lim1 = 0xb0; /* XCLK=8kHz, .62V threshold */ 854 sc->f54w->pcd = 0x0a; 855 sc->f54w->pcr = 0x15; 856 sc->f54w->xsw = 0x9f; /* fmr4 */ 857 sc->f54w->xsp = 0x1c; /* fmr5 */ 858 sc->f54w->xc0 = 0x07; 859 sc->f54w->xc1 = 0x3d; 860 sc->f54w->rc0 = 0x05; 861 sc->f54w->rc1 = 0x00; 862 sc->f54w->cmdr = 0x51; 863} 864 865static int 866mn_reset(struct softc *sc) 867{ 868 u_int32_t u; 869 int i; 870 871 sc->m32x->ccba = vtophys(&sc->m32_mem.csa); 872 sc->m32_mem.csa = vtophys(&sc->m32_mem.ccb); 873 874 bzero(sc->tiqb, sizeof sc->tiqb); 875 sc->m32x->tiqba = vtophys(&sc->tiqb); 876 sc->m32x->tiql = NIQB / 16 - 1; 877 878 bzero(sc->riqb, sizeof sc->riqb); 879 sc->m32x->riqba = vtophys(&sc->riqb); 880 sc->m32x->riql = NIQB / 16 - 1; 881 882 bzero(sc->ltiqb, sizeof sc->ltiqb); 883 sc->m32x->ltiqba = vtophys(&sc->ltiqb); 884 sc->m32x->ltiql = NIQB / 16 - 1; 885 886 bzero(sc->lriqb, sizeof sc->lriqb); 887 sc->m32x->lriqba = vtophys(&sc->lriqb); 888 sc->m32x->lriql = NIQB / 16 - 1; 889 890 bzero(sc->piqb, sizeof sc->piqb); 891 sc->m32x->piqba = vtophys(&sc->piqb); 892 sc->m32x->piql = NIQB / 16 - 1; 893 894 m32_init(sc); 895 f54_init(sc); 896 897 u = sc->m32x->stat; 898 sc->m32x->stat = u; 899 sc->m32_mem.ccb = 0x4; 900 sc->m32x->cmd = 0x1; 901 DELAY(1000); 902 u = sc->m32x->stat; 903 sc->m32x->stat = u; 904 905 /* set all timeslots to known state */ 906 for (i = 0; i < 32; i++) 907 sc->m32_mem.ts[i] = 0x20002000; 908 909 if (!(u & 1)) { 910 printf( 911"mn%d: WARNING: Controller failed the PCI bus-master test.\n" 912"mn%d: WARNING: Use a PCI slot which can support bus-master cards.\n", 913 sc->unit, sc->unit); 914 return (0); 915 } 916 return (1); 917} 918 919/* 920 * FALC54 interrupt handling 921 */ 922static void 923f54_intr(struct softc *sc) 924{ 925 unsigned g, u, s; 926 927 g = sc->f54r->gis; 928 u = sc->f54r->isr0 << 24; 929 u |= sc->f54r->isr1 << 16; 930 u |= sc->f54r->isr2 << 8; 931 u |= sc->f54r->isr3; 932 sc->falc_irq = u; 933 /* don't chat about the 1 sec heart beat */ 934 if (u & ~0x40) { 935#if 0 936 printf("%s*: FALC54 IRQ GIS:%02x %b\n", sc->name, g, u, "\20" 937 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 938 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 939 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 940 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 941#endif 942 s = sc->f54r->frs0 << 24; 943 s |= sc->f54r->frs1 << 16; 944 s |= sc->f54r->rsw << 8; 945 s |= sc->f54r->rsp; 946 sc->falc_state = s; 947 948 s &= ~0x01844038; /* undefined or static bits */ 949 s &= ~0x00009fc7; /* bits we don't care about */ 950 s &= ~0x00780000; /* XXX: TS16 related */ 951 s &= ~0x06000000; /* XXX: Multiframe related */ 952#if 0 953 printf("%s*: FALC54 Status %b\n", sc->name, s, "\20" 954 "\40LOS\37AIS\36LFA\35RRA\34AUXP\33NMF\32LMFA\31frs0.0" 955 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS\24TS16LFA\23frs1.2\22XLS\21XLO" 956 "\20RS1\17rsw.6\16RRA\15RY0\14RY1\13RY2\12RY3\11RY4" 957 "\10SI1\7SI2\6rsp.5\5rsp.4\4rsp.3\3RSIF\2RS13\1RS15"); 958#endif 959 if (s != sc->framer_state) { 960#if 0 961 for (i = 0; i < M32_CHAN; i++) { 962 if (!sc->ch[i]) 963 continue; 964 sp = &sc->ch[i]->ifsppp; 965 if (!(sp->pp_if.if_flags & IFF_UP)) 966 continue; 967 if (s) 968 timeout((timeout_t *)sp->pp_down, sp, 1 * hz); 969 else 970 timeout((timeout_t *)sp->pp_up, sp, 1 * hz); 971 } 972#endif 973 sc->framer_state = s; 974 } 975 } 976 /* Once per second check error counters */ 977 /* XXX: not clear if this is actually ok */ 978 if (!(u & 0x40)) 979 return; 980 sc->cnt_fec += sc->f54r->fec; 981 sc->cnt_cvc += sc->f54r->cvc; 982 sc->cnt_cec1 += sc->f54r->cec1; 983 sc->cnt_ebc += sc->f54r->ebc; 984 sc->cnt_cec2 += sc->f54r->cec2; 985 sc->cnt_cec3 += sc->f54r->cec3; 986 sc->cnt_rbc += sc->f54r->rbc; 987} 988 989/* 990 * Transmit interrupt for one channel 991 */ 992static void 993mn_tx_intr(struct softc *sc, u_int32_t vector) 994{ 995 u_int32_t chan; 996 struct trxd *dp; 997 struct mbuf *m; 998 999 chan = vector & 0x1f; 1000 if (!sc->ch[chan]) 1001 return; 1002 if (sc->ch[chan]->state != UP) { 1003 printf("%s: tx_intr when not UP\n", sc->name); 1004 return; 1005 } 1006 for (;;) { 1007 dp = sc->ch[chan]->x1; 1008 if (vtophys(dp) == sc->m32_mem.ctxd[chan]) 1009 return; 1010 m = dp->m; 1011 if (m) { 1012#if 0 1013 printf("%d = %d - %d (%p)\n", 1014 sc->ch[chan]->tx_pending - m->m_pkthdr.len, 1015 sc->ch[chan]->tx_pending , m->m_pkthdr.len, m); 1016#endif 1017 sc->ch[chan]->tx_pending -= m->m_pkthdr.len; 1018 m_freem(m); 1019 } 1020 sc->ch[chan]->last_xmit = time_second; 1021 sc->ch[chan]->x1 = dp->vnext; 1022 mn_free_desc(dp); 1023 } 1024} 1025 1026/* 1027 * Receive interrupt for one channel 1028 */ 1029static void 1030mn_rx_intr(struct softc *sc, u_int32_t vector) 1031{ 1032 u_int32_t chan, err; 1033 struct trxd *dp; 1034 struct mbuf *m; 1035 struct schan *sch; 1036 1037 chan = vector & 0x1f; 1038 if (!sc->ch[chan]) 1039 return; 1040 sch = sc->ch[chan]; 1041 if (sch->state != UP) { 1042 printf("%s: rx_intr when not UP\n", sc->name); 1043 return; 1044 } 1045 vector &= ~0x1f; 1046 if (vector == 0x30000b00) 1047 sch->rx_error++; 1048 for (;;) { 1049 dp = sch->r1; 1050 if (vtophys(dp) == sc->m32_mem.crxd[chan]) 1051 return; 1052 m = dp->m; 1053 dp->m = 0; 1054 m->m_pkthdr.len = m->m_len = (dp->status >> 16) & 0x1fff; 1055 err = (dp->status >> 8) & 0xff; 1056 if (!err) { 1057 int error; 1058 NG_SEND_DATA_ONLY(error, sch->hook, m); 1059 sch->last_recv = time_second; 1060 /* we could be down by now... */ 1061 if (sch->state != UP) 1062 return; 1063 } else if (err & 0x40) { 1064 sch->short_error++; 1065 } else if (err & 0x10) { 1066 sch->crc_error++; 1067 } else if (err & 0x08) { 1068 sch->dribble_error++; 1069 } else if (err & 0x04) { 1070 sch->long_error++; 1071 } else if (err & 0x02) { 1072 sch->abort_error++; 1073 } else if (err & 0x01) { 1074 sch->overflow_error++; 1075 } 1076 if (err) { 1077 sch->last_rxerr = time_second; 1078 sch->prev_error = sch->last_error; 1079 sch->last_error = err; 1080 } 1081 1082 sc->ch[chan]->r1 = dp->vnext; 1083 1084 /* Replenish desc + mbuf supplies */ 1085 if (!m) { 1086 MGETHDR(m, M_DONTWAIT, MT_DATA); 1087 if (m == NULL) { 1088 mn_free_desc(dp); 1089 return; /* ENOBUFS */ 1090 } 1091 MCLGET(m, M_DONTWAIT); 1092 if((m->m_flags & M_EXT) == 0) { 1093 mn_free_desc(dp); 1094 m_freem(m); 1095 return; /* ENOBUFS */ 1096 } 1097 } 1098 dp->m = m; 1099 dp->data = vtophys(m->m_data); 1100 dp->flags = 0x40000000; 1101 dp->flags += 1600 << 16; 1102 dp->next = vtophys(dp); 1103 dp->vnext = 0; 1104 sc->ch[chan]->rl->next = vtophys(dp); 1105 sc->ch[chan]->rl->vnext = dp; 1106 sc->ch[chan]->rl->flags &= ~0x40000000; 1107 sc->ch[chan]->rl = dp; 1108 } 1109} 1110 1111 1112/* 1113 * Interupt handler 1114 */ 1115 1116static void 1117mn_intr(void *xsc) 1118{ 1119 struct softc *sc; 1120 u_int32_t stat, lstat, u; 1121 int i, j; 1122 1123 sc = xsc; 1124 stat = sc->m32x->stat; 1125 lstat = sc->m32x->lstat; 1126#if 0 1127 if (!stat && !(lstat & 2)) 1128 return; 1129#endif 1130 1131 if (stat & ~0xc200) { 1132 printf("%s: I stat=%08x lstat=%08x\n", sc->name, stat, lstat); 1133 } 1134 1135 if ((stat & 0x200) || (lstat & 2)) 1136 f54_intr(sc); 1137 1138 for (j = i = 0; i < 64; i ++) { 1139 u = sc->riqb[i]; 1140 if (u) { 1141 sc->riqb[i] = 0; 1142 mn_rx_intr(sc, u); 1143 if ((u & ~0x1f) == 0x30000800 || (u & ~0x1f) == 0x30000b00) 1144 continue; 1145 u &= ~0x30000400; /* bits we don't care about */ 1146 if ((u & ~0x1f) == 0x00000900) 1147 continue; 1148 if (!(u & ~0x1f)) 1149 continue; 1150 if (!j) 1151 printf("%s*: RIQB:", sc->name); 1152 printf(" [%d]=%08x", i, u); 1153 j++; 1154 } 1155 } 1156 if (j) 1157 printf("\n"); 1158 1159 for (j = i = 0; i < 64; i ++) { 1160 u = sc->tiqb[i]; 1161 if (u) { 1162 sc->tiqb[i] = 0; 1163 mn_tx_intr(sc, u); 1164 if ((u & ~0x1f) == 0x20000800) 1165 continue; 1166 u &= ~0x20000000; /* bits we don't care about */ 1167 if (!u) 1168 continue; 1169 if (!j) 1170 printf("%s*: TIQB:", sc->name); 1171 printf(" [%d]=%08x", i, u); 1172 j++; 1173 } 1174 } 1175 if (j) 1176 printf("\n"); 1177 sc->m32x->stat = stat; 1178} 1179 1180static void 1181mn_timeout(void *xsc) 1182{ 1183 static int round = 0; 1184 struct softc *sc; 1185 1186 mn_intr(xsc); 1187 sc = xsc; 1188 timeout(mn_timeout, xsc, 10 * hz); 1189 round++; 1190 if (round == 2) { 1191 sc->m32_mem.ccb = 0x00008004; 1192 sc->m32x->cmd = 0x1; 1193 } else if (round > 2) { 1194 printf("%s: timeout\n", sc->name); 1195 } 1196} 1197 1198/* 1199 * PCI initialization stuff 1200 */ 1201 1202static int 1203mn_probe (device_t self) 1204{ 1205 u_int id = pci_get_devid(self); 1206 1207 if (sizeof (struct m32xreg) != 256) { 1208 printf("MN: sizeof(struct m32xreg) = %d, should have been 256\n", sizeof (struct m32xreg)); 1209 return (ENXIO); 1210 } 1211 if (sizeof (struct f54rreg) != 128) { 1212 printf("MN: sizeof(struct f54rreg) = %d, should have been 128\n", sizeof (struct f54rreg)); 1213 return (ENXIO); 1214 } 1215 if (sizeof (struct f54wreg) != 128) { 1216 printf("MN: sizeof(struct f54wreg) = %d, should have been 128\n", sizeof (struct f54wreg)); 1217 return (ENXIO); 1218 } 1219 1220 if (id != 0x2101110a) 1221 return (ENXIO); 1222 1223 device_set_desc_copy(self, "Munich32X E1/T1 HDLC Controller"); 1224 return (0); 1225} 1226 1227static int 1228mn_attach (device_t self) 1229{ 1230 struct softc *sc; 1231 u_int32_t u; 1232 u_int32_t ver; 1233 static int once; 1234 int rid, error; 1235 struct resource *res; 1236 1237 if (!once) { 1238 if (ng_newtype(&mntypestruct)) 1239 printf("ng_newtype failed\n"); 1240 once++; 1241 } 1242 1243 sc = (struct softc *)malloc(sizeof *sc, M_MN, M_WAITOK | M_ZERO); 1244 device_set_softc(self, sc); 1245 1246 sc->dev = self; 1247 sc->unit = device_get_unit(self); 1248 sprintf(sc->name, "mn%d", sc->unit); 1249 1250 rid = PCIR_MAPS; 1251 res = bus_alloc_resource(self, SYS_RES_MEMORY, &rid, 1252 0, ~0, 1, RF_ACTIVE); 1253 if (res == NULL) { 1254 device_printf(self, "Could not map memory\n"); 1255 return ENXIO; 1256 } 1257 sc->m0v = rman_get_virtual(res); 1258 sc->m0p = rman_get_start(res); 1259 1260 rid = PCIR_MAPS + 4; 1261 res = bus_alloc_resource(self, SYS_RES_MEMORY, &rid, 1262 0, ~0, 1, RF_ACTIVE); 1263 if (res == NULL) { 1264 device_printf(self, "Could not map memory\n"); 1265 return ENXIO; 1266 } 1267 sc->m1v = rman_get_virtual(res); 1268 sc->m1p = rman_get_start(res); 1269 1270 /* Allocate interrupt */ 1271 rid = 0; 1272 sc->irq = bus_alloc_resource(self, SYS_RES_IRQ, &rid, 0, ~0, 1273 1, RF_SHAREABLE | RF_ACTIVE); 1274 1275 if (sc->irq == NULL) { 1276 printf("couldn't map interrupt\n"); 1277 return(ENXIO); 1278 } 1279 1280 error = bus_setup_intr(self, sc->irq, INTR_TYPE_NET, mn_intr, sc, &sc->intrhand); 1281 1282 if (error) { 1283 printf("couldn't set up irq\n"); 1284 return(ENXIO); 1285 } 1286 1287 u = pci_read_config(self, PCIR_COMMAND, 1); 1288 printf("%x\n", u); 1289 pci_write_config(self, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN, 1); 1290#if 0 1291 pci_write_config(self, PCIR_COMMAND, 0x02800046, 4); 1292#endif 1293 u = pci_read_config(self, PCIR_COMMAND, 1); 1294 printf("%x\n", u); 1295 1296 ver = pci_read_config(self, PCI_CLASS_REG, 4); 1297 1298 sc->m32x = (struct m32xreg *) sc->m0v; 1299 sc->f54w = (struct f54wreg *) sc->m1v; 1300 sc->f54r = (struct f54rreg *) sc->m1v; 1301 1302 /* We must reset before poking at FALC54 registers */ 1303 u = mn_reset(sc); 1304 if (!u) 1305 return (0); 1306 1307 printf("mn%d: Munich32X", sc->unit); 1308 switch (ver & 0xff) { 1309 case 0x13: 1310 printf(" Rev 2.2"); 1311 break; 1312 default: 1313 printf(" Rev 0x%x\n", ver & 0xff); 1314 } 1315 printf(", Falc54"); 1316 switch (sc->f54r->vstr) { 1317 case 0: 1318 printf(" Rev < 1.3\n"); 1319 break; 1320 case 1: 1321 printf(" Rev 1.3\n"); 1322 break; 1323 case 2: 1324 printf(" Rev 1.4\n"); 1325 break; 1326 case 0x10: 1327 printf("-LH Rev 1.1\n"); 1328 break; 1329 case 0x13: 1330 printf("-LH Rev 1.3\n"); 1331 break; 1332 default: 1333 printf(" Rev 0x%x\n", sc->f54r->vstr); 1334 } 1335 1336 if (ng_make_node_common(&mntypestruct, &sc->node) != 0) { 1337 printf("ng_make_node_common failed\n"); 1338 return (0); 1339 } 1340 sc->node->private = sc; 1341 sprintf(sc->nodename, "%s%d", NG_MN_NODE_TYPE, sc->unit); 1342 if (ng_name_node(sc->node, sc->nodename)) { 1343 ng_rmnode(sc->node); 1344 ng_unref(sc->node); 1345 return (0); 1346 } 1347 1348 return (0); 1349} 1350 1351 1352static device_method_t mn_methods[] = { 1353 /* Device interface */ 1354 DEVMETHOD(device_probe, mn_probe), 1355 DEVMETHOD(device_attach, mn_attach), 1356 DEVMETHOD(device_suspend, bus_generic_suspend), 1357 DEVMETHOD(device_resume, bus_generic_resume), 1358 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1359 1360 {0, 0} 1361}; 1362 1363static driver_t mn_driver = { 1364 "mn", 1365 mn_methods, 1366 0 1367}; 1368 1369static devclass_t mn_devclass; 1370 1371DRIVER_MODULE(mn, pci, mn_driver, mn_devclass, 0, 0); 1372