if_mn.c revision 67164
1/* 2 * ---------------------------------------------------------------------------- 3 * "THE BEER-WARE LICENSE" (Revision 42): 4 * <phk@FreeBSD.org> wrote this file. As long as you retain this notice you 5 * can do whatever you want with this stuff. If we meet some day, and you think 6 * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp 7 * ---------------------------------------------------------------------------- 8 * 9 * $Id: if_mn.c,v 1.1 1999/02/01 13:06:40 phk Exp $ 10 * 11 * Driver for Siemens reference design card "Easy321-R1". 12 * 13 * This card contains a FALC54 E1/T1 framer and a MUNICH32X 32-channel HDLC 14 * controller. 15 * 16 * The driver supports E1 mode with up to 31 channels. We send CRC4 but don't 17 * check it coming in. 18 * 19 * The FALC54 and MUNICH32X have far too many registers and weird modes for 20 * comfort, so I have not bothered typing it all into a "fooreg.h" file, 21 * you will (badly!) need the documentation anyway if you want to mess with 22 * this gadget. 23 * 24 * $FreeBSD: head/sys/pci/if_mn.c 67164 2000-10-15 14:19:01Z phk $ 25 */ 26 27/* 28 * Stuff to describe the MUNIC32X and FALC54 chips. 29 */ 30 31#define M32_CHAN 32 /* We have 32 channels */ 32#define M32_TS 32 /* We have 32 timeslots */ 33 34#define NG_MN_NODE_TYPE "mn" 35 36#include <sys/param.h> 37#include <sys/kernel.h> 38#include <sys/sysctl.h> 39#include <sys/bus.h> 40#include <sys/mbuf.h> 41#include <sys/systm.h> 42#include <sys/malloc.h> 43 44#include <pci/pcireg.h> 45#include <pci/pcivar.h> 46#include "pci_if.h" 47 48#include <machine/bus.h> 49#include <machine/resource.h> 50 51#include <sys/rman.h> 52 53#include <vm/vm.h> 54#include <vm/pmap.h> 55 56#include <netgraph/ng_message.h> 57#include <netgraph/netgraph.h> 58 59 60static int mn_maxlatency = 1000; 61SYSCTL_INT(_debug, OID_AUTO, mn_maxlatency, CTLFLAG_RW, 62 &mn_maxlatency, 0, 63 "The number of milliseconds a packet is allowed to spend in the output queue. " 64 "If the output queue is longer than this number of milliseconds when the packet " 65 "arrives for output, the packet will be dropped." 66); 67 68#ifndef NMN 69/* Most machines don't support more than 4 busmaster PCI slots, if even that many */ 70#define NMN 4 71#endif 72 73/* From: PEB 20321 data sheet, p187, table 22 */ 74struct m32xreg { 75 u_int32_t conf, cmd, stat, imask; 76 u_int32_t fill10, piqba, piql, fill1c; 77 u_int32_t mode1, mode2, ccba, txpoll; 78 u_int32_t tiqba, tiql, riqba, riql; 79 u_int32_t lconf, lccba, fill48, ltran; 80 u_int32_t ltiqba, ltiql, lriqba, lriql; 81 u_int32_t lreg0, lreg1, lreg2, lreg3; 82 u_int32_t lreg4, lreg5, lre6, lstat; 83 u_int32_t gpdir, gpdata, gpod, fill8c; 84 u_int32_t ssccon, sscbr, ssctb, sscrb; 85 u_int32_t ssccse, sscim, fillab, fillac; 86 u_int32_t iomcon1, iomcon2, iomstat, fillbc; 87 u_int32_t iomcit0, iomcit1, iomcir0, iomcir1; 88 u_int32_t iomtmo, iomrmo, filld8, filldc; 89 u_int32_t mbcmd, mbdata1, mbdata2, mbdata3; 90 u_int32_t mbdata4, mbdata5, mbdata6, mbdata7; 91}; 92 93/* From: PEB 2254 data sheet, p80, table 10 */ 94struct f54wreg { 95 u_int16_t xfifo; 96 u_int8_t cmdr, mode, rah1, rah2, ral1, ral2; 97 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 98 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 99 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 100 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 101 u_int8_t test1, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr3; 102 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 103 u_int8_t lim2, fill39[7]; 104 u_int8_t fill40[8]; 105 u_int8_t fill48[8]; 106 u_int8_t fill50[8]; 107 u_int8_t fill58[8]; 108 u_int8_t dec, fill61, test2, fill63[5]; 109 u_int8_t fill68[8]; 110 u_int8_t xs[16]; 111}; 112 113/* From: PEB 2254 data sheet, p117, table 10 */ 114struct f54rreg { 115 u_int16_t rfifo; 116 u_int8_t fill2, mode, rah1, rah2, ral1, ral2; 117 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 118 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 119 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 120 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 121 u_int8_t test, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr13; 122 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 123 u_int8_t lim2, fill39[7]; 124 u_int8_t fill40[8]; 125 u_int8_t fill48[4], frs0, frs1, rsw, rsp; 126 u_int16_t fec, cvc, cec1, ebc; 127 u_int16_t cec2, cec3; 128 u_int8_t rsa4, rsa5, rsa6, rsa7; 129 u_int8_t rsa8, rsa6s, tsr0, tsr1, sis, rsis; 130 u_int16_t rbc; 131 u_int8_t isr0, isr1, isr2, isr3, fill6c, fill6d, gis, vstr; 132 u_int8_t rs[16]; 133}; 134 135/* Transmit & receive descriptors */ 136struct trxd { 137 u_int32_t flags; 138 vm_offset_t next; 139 vm_offset_t data; 140 u_int32_t status; /* only used for receive */ 141 struct mbuf *m; /* software use only */ 142 struct trxd *vnext; /* software use only */ 143}; 144 145/* Channel specification */ 146struct cspec { 147 u_int32_t flags; 148 vm_offset_t rdesc; 149 vm_offset_t tdesc; 150 u_int32_t itbs; 151}; 152 153struct m32_mem { 154 vm_offset_t csa; 155 u_int32_t ccb; 156 u_int32_t reserve1[2]; 157 u_int32_t ts[M32_TS]; 158 struct cspec cs[M32_CHAN]; 159 vm_offset_t crxd[M32_CHAN]; 160 vm_offset_t ctxd[M32_CHAN]; 161}; 162 163struct softc; 164struct sockaddr; 165struct rtentry; 166 167static int mn_probe (device_t self); 168static int mn_attach (device_t self); 169static void mn_create_channel(struct softc *sc, int chan); 170static int mn_reset(struct softc *sc); 171static struct trxd * mn_alloc_desc(void); 172static void mn_free_desc(struct trxd *dp); 173static void mn_intr(void *xsc); 174static u_int32_t mn_parse_ts(const char *s, int *nbit); 175#ifdef notyet 176static void m32_dump(struct softc *sc); 177static void f54_dump(struct softc *sc); 178static void mn_fmt_ts(char *p, u_int32_t ts); 179#endif /* notyet */ 180 181static ng_constructor_t ngmn_constructor; 182static ng_rcvmsg_t ngmn_rcvmsg; 183static ng_shutdown_t ngmn_shutdown; 184static ng_newhook_t ngmn_newhook; 185static ng_connect_t ngmn_connect; 186static ng_rcvdata_t ngmn_rcvdata; 187static ng_disconnect_t ngmn_disconnect; 188 189static struct ng_type mntypestruct = { 190 NG_VERSION, 191 NG_MN_NODE_TYPE, 192 NULL, 193 ngmn_constructor, 194 ngmn_rcvmsg, 195 ngmn_shutdown, 196 ngmn_newhook, 197 NULL, 198 ngmn_connect, 199 ngmn_rcvdata, 200 ngmn_rcvdata, 201 ngmn_disconnect, 202 NULL 203}; 204 205static MALLOC_DEFINE(M_MN, "mn", "Mx driver related"); 206 207#define NIQB 64 208 209struct schan { 210 enum {DOWN, UP} state; 211 struct softc *sc; 212 int chan; 213 u_int32_t ts; 214 char name[8]; 215 struct trxd *r1, *rl; 216 struct trxd *x1, *xl; 217 hook_p hook; 218 219 time_t last_recv; 220 time_t last_rxerr; 221 time_t last_xmit; 222 223 u_long rx_error; 224 225 u_long short_error; 226 u_long crc_error; 227 u_long dribble_error; 228 u_long long_error; 229 u_long abort_error; 230 u_long overflow_error; 231 232 int last_error; 233 int prev_error; 234 235 u_long tx_pending; 236 u_long tx_limit; 237}; 238 239struct softc { 240 int unit; 241 device_t dev; 242 struct resource *irq; 243 void *intrhand; 244 void *m0v, *m1v; 245 vm_offset_t m0p, m1p; 246 struct m32xreg *m32x; 247 struct f54wreg *f54w; 248 struct f54rreg *f54r; 249 struct m32_mem m32_mem; 250 u_int32_t tiqb[NIQB]; 251 u_int32_t riqb[NIQB]; 252 u_int32_t piqb[NIQB]; 253 u_int32_t ltiqb[NIQB]; 254 u_int32_t lriqb[NIQB]; 255 char name[8]; 256 u_int32_t falc_irq, falc_state, framer_state; 257 struct schan *ch[M32_CHAN]; 258 char nodename[NG_NODELEN + 1]; 259 node_p node; 260 261 u_long cnt_fec; 262 u_long cnt_cvc; 263 u_long cnt_cec1; 264 u_long cnt_ebc; 265 u_long cnt_cec2; 266 u_long cnt_cec3; 267 u_long cnt_rbc; 268}; 269 270static int 271ngmn_constructor(node_p *nodep) 272{ 273 274 return (EINVAL); 275} 276 277static int 278ngmn_shutdown(node_p nodep) 279{ 280 281 return (EINVAL); 282} 283 284static int 285ngmn_rcvmsg(node_p node, struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp, hook_p lasthook) 286{ 287 struct softc *sc; 288 struct schan *sch; 289 char *arg; 290 int pos, i; 291 292 sc = node->private; 293 294 if (msg->header.typecookie != NGM_GENERIC_COOKIE || 295 msg->header.cmd != NGM_TEXT_STATUS) { 296 if (resp) 297 *resp = NULL; 298 FREE(msg, M_NETGRAPH); 299 return (EINVAL); 300 } 301 NG_MKRESPONSE(*resp, msg, sizeof(struct ng_mesg) + NG_TEXTRESPONSE, 302 M_NOWAIT); 303 if (*resp == NULL) { 304 FREE(msg, M_NETGRAPH); 305 return (ENOMEM); 306 } 307 arg = (char *)(*resp)->data; 308 pos = 0; 309 pos += sprintf(pos + arg,"Framer status %b;\n", sc->framer_state, "\20" 310 "\40LOS\37AIS\36LFA\35RRA" 311 "\34AUXP\33NMF\32LMFA\31frs0.0" 312 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 313 "\24TS16LFA\23frs1.2\22XLS\21XLO" 314 "\20RS1\17rsw.6\16RRA\15RY0" 315 "\14RY1\13RY2\12RY3\11RY4" 316 "\10SI1\7SI2\6rsp.5\5rsp.4" 317 "\4rsp.3\3RSIF\2RS13\1RS15"); 318 pos += sprintf(pos + arg," Framing errors: %lu", sc->cnt_fec); 319 pos += sprintf(pos + arg," Code Violations: %lu\n", sc->cnt_cvc); 320 321 pos += sprintf(pos + arg," Falc State %b;\n", sc->falc_state, "\20" 322 "\40LOS\37AIS\36LFA\35RRA" 323 "\34AUXP\33NMF\32LMFA\31frs0.0" 324 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 325 "\24TS16LFA\23frs1.2\22XLS\21XLO" 326 "\20RS1\17rsw.6\16RRA\15RY0" 327 "\14RY1\13RY2\12RY3\11RY4" 328 "\10SI1\7SI2\6rsp.5\5rsp.4" 329 "\4rsp.3\3RSIF\2RS13\1RS15"); 330 pos += sprintf(pos + arg, " Falc IRQ %b\n", sc->falc_irq, "\20" 331 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 332 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 333 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 334 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 335 for (i = 0; i < M32_CHAN; i++) { 336 if (!sc->ch[i]) 337 continue; 338 sch = sc->ch[i]; 339 340 pos += sprintf(arg + pos, " Chan %d <%s> ", 341 i, sch->hook->name); 342 343 pos += sprintf(arg + pos, " Last Rx: "); 344 if (sch->last_recv) 345 pos += sprintf(arg + pos, "%lu s", time_second - sch->last_recv); 346 else 347 pos += sprintf(arg + pos, "never"); 348 349 pos += sprintf(arg + pos, ", last RxErr: "); 350 if (sch->last_rxerr) 351 pos += sprintf(arg + pos, "%lu s", time_second - sch->last_rxerr); 352 else 353 pos += sprintf(arg + pos, "never"); 354 355 pos += sprintf(arg + pos, ", last Tx: "); 356 if (sch->last_xmit) 357 pos += sprintf(arg + pos, "%lu s\n", time_second - sch->last_xmit); 358 else 359 pos += sprintf(arg + pos, "never\n"); 360 361 pos += sprintf(arg + pos, " RX error(s) %lu", sch->rx_error); 362 pos += sprintf(arg + pos, " Short: %lu", sch->short_error); 363 pos += sprintf(arg + pos, " CRC: %lu", sch->crc_error); 364 pos += sprintf(arg + pos, " Mod8: %lu", sch->dribble_error); 365 pos += sprintf(arg + pos, " Long: %lu", sch->long_error); 366 pos += sprintf(arg + pos, " Abort: %lu", sch->abort_error); 367 pos += sprintf(arg + pos, " Overflow: %lu\n", sch->overflow_error); 368 369 pos += sprintf(arg + pos, " Last error: %b Prev error: %b\n", 370 sch->last_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN", 371 sch->prev_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN"); 372 pos += sprintf(arg + pos, " Xmit bytes pending %ld\n", 373 sch->tx_pending); 374 } 375 (*resp)->header.arglen = pos + 1; 376 FREE(msg, M_NETGRAPH); 377 return (0); 378} 379 380static int 381ngmn_newhook(node_p node, hook_p hook, const char *name) 382{ 383 u_int32_t ts, chan; 384 struct softc *sc; 385 int nbit; 386 387 sc = node->private; 388 389 if (name[0] != 't' || name[1] != 's') 390 return (EINVAL); 391 392 ts = mn_parse_ts(name + 2, &nbit); 393 if (ts == 0) 394 return (EINVAL); 395 chan = ffs(ts) - 1; 396 if (!sc->ch[chan]) 397 mn_create_channel(sc, chan); 398 else if (sc->ch[chan]->state == UP) 399 return (EBUSY); 400 sc->ch[chan]->ts = ts; 401 sc->ch[chan]->hook = hook; 402 sc->ch[chan]->tx_limit = nbit * 8; 403 hook->private = sc->ch[chan]; 404 return(0); 405} 406 407 408static struct trxd *mn_desc_free; 409 410static struct trxd * 411mn_alloc_desc(void) 412{ 413 struct trxd *dp; 414 415 dp = mn_desc_free; 416 if (dp) 417 mn_desc_free = dp->vnext; 418 else 419 dp = (struct trxd *)malloc(sizeof *dp, M_MN, M_NOWAIT); 420 return (dp); 421} 422 423static void 424mn_free_desc(struct trxd *dp) 425{ 426 dp->vnext = mn_desc_free; 427 mn_desc_free = dp; 428} 429 430static u_int32_t 431mn_parse_ts(const char *s, int *nbit) 432{ 433 unsigned r; 434 int i, j; 435 char *p; 436 437 r = 0; 438 j = 0; 439 *nbit = 0; 440 while(*s) { 441 i = strtol(s, &p, 0); 442 if (i < 1 || i > 31) 443 return (0); 444 while (j && j < i) { 445 r |= 1 << j++; 446 (*nbit)++; 447 } 448 j = 0; 449 r |= 1 << i; 450 (*nbit)++; 451 if (*p == ',') { 452 s = p + 1; 453 continue; 454 } else if (*p == '-') { 455 j = i; 456 s = p + 1; 457 continue; 458 } else if (!*p) { 459 break; 460 } else { 461 return (0); 462 } 463 } 464 return (r); 465} 466 467#ifdef notyet 468static void 469mn_fmt_ts(char *p, u_int32_t ts) 470{ 471 char *s; 472 int j; 473 474 s = ""; 475 ts &= 0xfffffffe; 476 for (j = 1; j < 32; j++) { 477 if (!(ts & (1 << j))) 478 continue; 479 sprintf(p, "%s%d", s, j); 480 p += strlen(p); 481 s = ","; 482 if (!(ts & (1 << (j+1)))) 483 continue; 484 for (; j < 32; j++) 485 if (!(ts & (1 << (j+1)))) 486 break; 487 sprintf(p, "-%d", j); 488 p += strlen(p); 489 s = ","; 490 } 491} 492#endif /* notyet */ 493 494/* 495 * OUTPUT 496 */ 497 498static int 499ngmn_rcvdata(hook_p hook, struct mbuf *m, meta_p meta, 500 struct mbuf **ret_m, meta_p *ret_meta) 501{ 502 struct mbuf *m2; 503 struct trxd *dp, *dp2; 504 struct schan *sch; 505 struct softc *sc; 506 int chan, pitch, len; 507 508 sch = hook->private; 509 sc = sch->sc; 510 chan = sch->chan; 511 512 if (sch->state != UP) { 513 NG_FREE_DATA(m, meta); 514 return (0); 515 } 516 if (sch->tx_pending + m->m_pkthdr.len > sch->tx_limit * mn_maxlatency) { 517 NG_FREE_DATA(m, meta); 518 return (0); 519 } 520 NG_FREE_META(meta); 521 pitch = 0; 522 m2 = m; 523 dp2 = sc->ch[chan]->xl; 524 len = m->m_pkthdr.len; 525 while (len) { 526 dp = mn_alloc_desc(); 527 if (!dp) { 528 pitch++; 529 m_freem(m); 530 sc->ch[chan]->xl = dp2; 531 dp = dp2->vnext; 532 while (dp) { 533 dp2 = dp->vnext; 534 mn_free_desc(dp); 535 dp = dp2; 536 } 537 sc->ch[chan]->xl->vnext = 0; 538 break; 539 } 540 dp->data = vtophys(m2->m_data); 541 dp->flags = m2->m_len << 16; 542 dp->flags += 1; 543 len -= m2->m_len; 544 dp->next = vtophys(dp); 545 dp->vnext = 0; 546 sc->ch[chan]->xl->next = vtophys(dp); 547 sc->ch[chan]->xl->vnext = dp; 548 sc->ch[chan]->xl = dp; 549 if (!len) { 550 dp->m = m; 551 dp->flags |= 0xc0000000; 552 dp2->flags &= ~0x40000000; 553 } else { 554 dp->m = 0; 555 m2 = m2->m_next; 556 } 557 } 558 if (pitch) 559 printf("%s%d: Short on mem, pitched %d packets\n", 560 sc->name, chan, pitch); 561 else { 562#if 0 563 printf("%d = %d + %d (%p)\n", 564 sch->tx_pending + m->m_pkthdr.len, 565 sch->tx_pending , m->m_pkthdr.len, m); 566#endif 567 sch->tx_pending += m->m_pkthdr.len; 568 } 569 return (0); 570} 571 572/* 573 * OPEN 574 */ 575static int 576ngmn_connect(hook_p hook) 577{ 578 int i, nts, chan; 579 struct trxd *dp, *dp2; 580 struct mbuf *m; 581 struct softc *sc; 582 struct schan *sch; 583 u_int32_t u; 584 585 sch = hook->private; 586 chan = sch->chan; 587 sc = sch->sc; 588 589 if (sch->state == UP) 590 return (0); 591 sch->state = UP; 592 593 /* Count and configure the timeslots for this channel */ 594 for (nts = i = 0; i < 32; i++) 595 if (sch->ts & (1 << i)) { 596 sc->m32_mem.ts[i] = 0x00ff00ff | 597 (chan << 24) | (chan << 8); 598 nts++; 599 } 600 601 /* Init the receiver & xmitter to HDLC */ 602 sc->m32_mem.cs[chan].flags = 0x80e90006; 603 /* Allocate two buffers per timeslot */ 604 sc->m32_mem.cs[chan].itbs = nts * 2; 605 606 /* Setup a transmit chain with one descriptor */ 607 /* XXX: we actually send a 1 byte packet */ 608 dp = mn_alloc_desc(); 609 MGETHDR(m, M_WAIT, MT_DATA); 610 m->m_pkthdr.len = 0; 611 dp->m = m; 612 dp->flags = 0xc0000000 + (1 << 16); 613 dp->next = vtophys(dp); 614 dp->vnext = 0; 615 dp->data = vtophys(sc->name); 616 sc->m32_mem.cs[chan].tdesc = vtophys(dp); 617 sc->ch[chan]->x1 = dp; 618 sc->ch[chan]->xl = dp; 619 620 /* Setup a receive chain with 5 + NTS descriptors */ 621 622 dp = mn_alloc_desc(); 623 MGETHDR(m, M_WAIT, MT_DATA); 624 MCLGET(m, M_WAIT); 625 dp->m = m; 626 dp->data = vtophys(m->m_data); 627 dp->flags = 0x40000000; 628 dp->flags += 1600 << 16; 629 dp->next = vtophys(dp); 630 dp->vnext = 0; 631 sc->ch[chan]->rl = dp; 632 633 for (i = 0; i < (nts + 10); i++) { 634 dp2 = dp; 635 dp = mn_alloc_desc(); 636 MGETHDR(m, M_WAIT, MT_DATA); 637 MCLGET(m, M_WAIT); 638 dp->m = m; 639 dp->data = vtophys(m->m_data); 640 dp->flags = 0x00000000; 641 dp->flags += 1600 << 16; 642 dp->next = vtophys(dp2); 643 dp->vnext = dp2; 644 } 645 sc->m32_mem.cs[chan].rdesc = vtophys(dp); 646 sc->ch[chan]->r1 = dp; 647 648 /* Initialize this channel */ 649 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 650 sc->m32x->cmd = 0x1; 651 DELAY(1000); 652 u = sc->m32x->stat; 653 if (!(u & 1)) 654 printf("%s: init chan %d stat %08x\n", sc->name, chan, u); 655 sc->m32x->stat = 1; 656 657 return (0); 658} 659 660/* 661 * CLOSE 662 */ 663static int 664ngmn_disconnect(hook_p hook) 665{ 666 int chan, i; 667 struct softc *sc; 668 struct schan *sch; 669 struct trxd *dp, *dp2; 670 u_int32_t u; 671 672 sch = hook->private; 673 chan = sch->chan; 674 sc = sch->sc; 675 676 if (sch->state == DOWN) 677 return (0); 678 sch->state = DOWN; 679 680 /* Set receiver & transmitter off */ 681 sc->m32_mem.cs[chan].flags = 0x80920006; 682 sc->m32_mem.cs[chan].itbs = 0; 683 684 /* free the timeslots */ 685 for (i = 0; i < 32; i++) 686 if (sc->ch[chan]->ts & (1 << i)) 687 sc->m32_mem.ts[i] = 0x20002000; 688 689 /* Initialize this channel */ 690 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 691 sc->m32x->cmd = 0x1; 692 DELAY(30); 693 u = sc->m32x->stat; 694 if (!(u & 1)) 695 printf("%s: zap chan %d stat %08x\n", sc->name, chan, u); 696 sc->m32x->stat = 1; 697 698 /* Free all receive descriptors and mbufs */ 699 for (dp = sc->ch[chan]->r1; dp ; dp = dp2) { 700 if (dp->m) 701 m_freem(dp->m); 702 sc->ch[chan]->r1 = dp2 = dp->vnext; 703 mn_free_desc(dp); 704 } 705 706 /* Free all transmit descriptors and mbufs */ 707 for (dp = sc->ch[chan]->x1; dp ; dp = dp2) { 708 if (dp->m) { 709 sc->ch[chan]->tx_pending -= dp->m->m_pkthdr.len; 710 m_freem(dp->m); 711 } 712 sc->ch[chan]->x1 = dp2 = dp->vnext; 713 mn_free_desc(dp); 714 } 715 return(0); 716} 717 718/* 719 * Create a new channel. 720 */ 721static void 722mn_create_channel(struct softc *sc, int chan) 723{ 724 struct schan *sch; 725 726 sch = sc->ch[chan] = (struct schan *)malloc(sizeof *sc->ch[chan], 727 M_MN, M_WAITOK); 728 bzero(sch, sizeof *sch); 729 sch->sc = sc; 730 sch->state = DOWN; 731 sch->chan = chan; 732 sprintf(sch->name, "%s%d", sc->name, chan); 733 return; 734} 735 736#ifdef notyet 737/* 738 * Dump Munich32x state 739 */ 740static void 741m32_dump(struct softc *sc) 742{ 743 u_int32_t *tp4; 744 int i, j; 745 746 printf("mn%d: MUNICH32X dump\n", sc->unit); 747 tp4 = (u_int32_t *)sc->m0v; 748 for(j = 0; j < 64; j += 8) { 749 printf("%02x", j * sizeof *tp4); 750 for(i = 0; i < 8; i++) 751 printf(" %08x", tp4[i+j]); 752 printf("\n"); 753 } 754 for(j = 0; j < M32_CHAN; j++) { 755 if (!sc->ch[j]) 756 continue; 757 printf("CH%d: state %d ts %08x", 758 j, sc->ch[j]->state, sc->ch[j]->ts); 759 printf(" %08x %08x %08x %08x %08x %08x\n", 760 sc->m32_mem.cs[j].flags, 761 sc->m32_mem.cs[j].rdesc, 762 sc->m32_mem.cs[j].tdesc, 763 sc->m32_mem.cs[j].itbs, 764 sc->m32_mem.crxd[j], 765 sc->m32_mem.ctxd[j] ); 766 } 767} 768 769/* 770 * Dump Falch54 state 771 */ 772static void 773f54_dump(struct softc *sc) 774{ 775 u_int8_t *tp1; 776 int i, j; 777 778 printf("%s: FALC54 dump\n", sc->name); 779 tp1 = (u_int8_t *)sc->m1v; 780 for(j = 0; j < 128; j += 16) { 781 printf("%s: %02x |", sc->name, j * sizeof *tp1); 782 for(i = 0; i < 16; i++) 783 printf(" %02x", tp1[i+j]); 784 printf("\n"); 785 } 786} 787#endif /* notyet */ 788 789/* 790 * Init Munich32x 791 */ 792static void 793m32_init(struct softc *sc) 794{ 795 796 sc->m32x->conf = 0x00000000; 797 sc->m32x->mode1 = 0x81048000 + 1600; /* XXX: temp */ 798#if 1 799 sc->m32x->mode2 = 0x00000081; 800 sc->m32x->txpoll = 0xffffffff; 801#else 802 sc->m32x->mode2 = 0x00000101; 803#endif 804 sc->m32x->lconf = 0x6060009B; 805 sc->m32x->imask = 0x00000000; 806} 807 808/* 809 * Init the Falc54 810 */ 811static void 812f54_init(struct softc *sc) 813{ 814 sc->f54w->ipc = 0x07; 815 816 sc->f54w->xpm0 = 0xbd; 817 sc->f54w->xpm1 = 0x03; 818 sc->f54w->xpm2 = 0x00; 819 820 sc->f54w->imr0 = 0x18; /* RMB, CASC */ 821 sc->f54w->imr1 = 0x08; /* XMB */ 822 sc->f54w->imr2 = 0x00; 823 sc->f54w->imr3 = 0x38; /* LMFA16, AIS16, RA16 */ 824 sc->f54w->imr4 = 0x00; 825 826 sc->f54w->fmr0 = 0xf0; /* X: HDB3, R: HDB3 */ 827 sc->f54w->fmr1 = 0x0e; /* Send CRC4, 2Mbit, ECM */ 828 sc->f54w->fmr2 = 0x03; /* Auto Rem-Alarm, Auto resync */ 829 830 sc->f54w->lim1 = 0xb0; /* XCLK=8kHz, .62V threshold */ 831 sc->f54w->pcd = 0x0a; 832 sc->f54w->pcr = 0x15; 833 sc->f54w->xsw = 0x9f; /* fmr4 */ 834 sc->f54w->xsp = 0x1c; /* fmr5 */ 835 sc->f54w->xc0 = 0x07; 836 sc->f54w->xc1 = 0x3d; 837 sc->f54w->rc0 = 0x05; 838 sc->f54w->rc1 = 0x00; 839 sc->f54w->cmdr = 0x51; 840} 841 842static int 843mn_reset(struct softc *sc) 844{ 845 u_int32_t u; 846 int i; 847 848 sc->m32x->ccba = vtophys(&sc->m32_mem.csa); 849 sc->m32_mem.csa = vtophys(&sc->m32_mem.ccb); 850 851 bzero(sc->tiqb, sizeof sc->tiqb); 852 sc->m32x->tiqba = vtophys(&sc->tiqb); 853 sc->m32x->tiql = NIQB / 16 - 1; 854 855 bzero(sc->riqb, sizeof sc->riqb); 856 sc->m32x->riqba = vtophys(&sc->riqb); 857 sc->m32x->riql = NIQB / 16 - 1; 858 859 bzero(sc->ltiqb, sizeof sc->ltiqb); 860 sc->m32x->ltiqba = vtophys(&sc->ltiqb); 861 sc->m32x->ltiql = NIQB / 16 - 1; 862 863 bzero(sc->lriqb, sizeof sc->lriqb); 864 sc->m32x->lriqba = vtophys(&sc->lriqb); 865 sc->m32x->lriql = NIQB / 16 - 1; 866 867 bzero(sc->piqb, sizeof sc->piqb); 868 sc->m32x->piqba = vtophys(&sc->piqb); 869 sc->m32x->piql = NIQB / 16 - 1; 870 871 m32_init(sc); 872 f54_init(sc); 873 874 u = sc->m32x->stat; 875 sc->m32x->stat = u; 876 sc->m32_mem.ccb = 0x4; 877 sc->m32x->cmd = 0x1; 878 DELAY(1000); 879 u = sc->m32x->stat; 880 sc->m32x->stat = u; 881 882 /* set all timeslots to known state */ 883 for (i = 0; i < 32; i++) 884 sc->m32_mem.ts[i] = 0x20002000; 885 886 if (!(u & 1)) { 887 printf( 888"mn%d: WARNING: Controller failed the PCI bus-master test.\n" 889"mn%d: WARNING: Use a PCI slot which can support bus-master cards.\n", 890 sc->unit, sc->unit); 891 return (0); 892 } 893 return (1); 894} 895 896/* 897 * FALC54 interrupt handling 898 */ 899static void 900f54_intr(struct softc *sc) 901{ 902 unsigned g, u, s; 903 904 g = sc->f54r->gis; 905 u = sc->f54r->isr0 << 24; 906 u |= sc->f54r->isr1 << 16; 907 u |= sc->f54r->isr2 << 8; 908 u |= sc->f54r->isr3; 909 sc->falc_irq = u; 910 /* don't chat about the 1 sec heart beat */ 911 if (u & ~0x40) { 912#if 0 913 printf("%s*: FALC54 IRQ GIS:%02x %b\n", sc->name, g, u, "\20" 914 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 915 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 916 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 917 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 918#endif 919 s = sc->f54r->frs0 << 24; 920 s |= sc->f54r->frs1 << 16; 921 s |= sc->f54r->rsw << 8; 922 s |= sc->f54r->rsp; 923 sc->falc_state = s; 924 925 s &= ~0x01844038; /* undefined or static bits */ 926 s &= ~0x00009fc7; /* bits we don't care about */ 927 s &= ~0x00780000; /* XXX: TS16 related */ 928 s &= ~0x06000000; /* XXX: Multiframe related */ 929#if 0 930 printf("%s*: FALC54 Status %b\n", sc->name, s, "\20" 931 "\40LOS\37AIS\36LFA\35RRA\34AUXP\33NMF\32LMFA\31frs0.0" 932 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS\24TS16LFA\23frs1.2\22XLS\21XLO" 933 "\20RS1\17rsw.6\16RRA\15RY0\14RY1\13RY2\12RY3\11RY4" 934 "\10SI1\7SI2\6rsp.5\5rsp.4\4rsp.3\3RSIF\2RS13\1RS15"); 935#endif 936 if (s != sc->framer_state) { 937#if 0 938 for (i = 0; i < M32_CHAN; i++) { 939 if (!sc->ch[i]) 940 continue; 941 sp = &sc->ch[i]->ifsppp; 942 if (!(sp->pp_if.if_flags & IFF_UP)) 943 continue; 944 if (s) 945 timeout((timeout_t *)sp->pp_down, sp, 1 * hz); 946 else 947 timeout((timeout_t *)sp->pp_up, sp, 1 * hz); 948 } 949#endif 950 sc->framer_state = s; 951 } 952 } 953 /* Once per second check error counters */ 954 /* XXX: not clear if this is actually ok */ 955 if (!(u & 0x40)) 956 return; 957 sc->cnt_fec += sc->f54r->fec; 958 sc->cnt_cvc += sc->f54r->cvc; 959 sc->cnt_cec1 += sc->f54r->cec1; 960 sc->cnt_ebc += sc->f54r->ebc; 961 sc->cnt_cec2 += sc->f54r->cec2; 962 sc->cnt_cec3 += sc->f54r->cec3; 963 sc->cnt_rbc += sc->f54r->rbc; 964} 965 966/* 967 * Transmit interrupt for one channel 968 */ 969static void 970mn_tx_intr(struct softc *sc, u_int32_t vector) 971{ 972 u_int32_t chan; 973 struct trxd *dp; 974 struct mbuf *m; 975 976 chan = vector & 0x1f; 977 if (!sc->ch[chan]) 978 return; 979 if (sc->ch[chan]->state != UP) { 980 printf("%s: tx_intr when not UP\n", sc->name); 981 return; 982 } 983 for (;;) { 984 dp = sc->ch[chan]->x1; 985 if (vtophys(dp) == sc->m32_mem.ctxd[chan]) 986 return; 987 m = dp->m; 988 if (m) { 989#if 0 990 printf("%d = %d - %d (%p)\n", 991 sc->ch[chan]->tx_pending - m->m_pkthdr.len, 992 sc->ch[chan]->tx_pending , m->m_pkthdr.len, m); 993#endif 994 sc->ch[chan]->tx_pending -= m->m_pkthdr.len; 995 m_freem(m); 996 } 997 sc->ch[chan]->last_xmit = time_second; 998 sc->ch[chan]->x1 = dp->vnext; 999 mn_free_desc(dp); 1000 } 1001} 1002 1003/* 1004 * Receive interrupt for one channel 1005 */ 1006static void 1007mn_rx_intr(struct softc *sc, u_int32_t vector) 1008{ 1009 u_int32_t chan, err; 1010 struct trxd *dp; 1011 struct mbuf *m; 1012 struct schan *sch; 1013 1014 chan = vector & 0x1f; 1015 if (!sc->ch[chan]) 1016 return; 1017 sch = sc->ch[chan]; 1018 if (sch->state != UP) { 1019 printf("%s: rx_intr when not UP\n", sc->name); 1020 return; 1021 } 1022 vector &= ~0x1f; 1023 if (vector == 0x30000b00) 1024 sch->rx_error++; 1025 for (;;) { 1026 dp = sch->r1; 1027 if (vtophys(dp) == sc->m32_mem.crxd[chan]) 1028 return; 1029 m = dp->m; 1030 dp->m = 0; 1031 m->m_pkthdr.len = m->m_len = (dp->status >> 16) & 0x1fff; 1032 err = (dp->status >> 8) & 0xff; 1033 if (!err) { 1034 ng_queue_data(sch->hook, m, NULL); 1035 sch->last_recv = time_second; 1036 m = 0; 1037 /* we could be down by now... */ 1038 if (sch->state != UP) 1039 return; 1040 } else if (err & 0x40) { 1041 sch->short_error++; 1042 } else if (err & 0x10) { 1043 sch->crc_error++; 1044 } else if (err & 0x08) { 1045 sch->dribble_error++; 1046 } else if (err & 0x04) { 1047 sch->long_error++; 1048 } else if (err & 0x02) { 1049 sch->abort_error++; 1050 } else if (err & 0x01) { 1051 sch->overflow_error++; 1052 } 1053 if (err) { 1054 sch->last_rxerr = time_second; 1055 sch->prev_error = sch->last_error; 1056 sch->last_error = err; 1057 } 1058 1059 sc->ch[chan]->r1 = dp->vnext; 1060 1061 /* Replenish desc + mbuf supplies */ 1062 if (!m) { 1063 MGETHDR(m, M_DONTWAIT, MT_DATA); 1064 if (m == NULL) { 1065 mn_free_desc(dp); 1066 return; 1067 } 1068 MCLGET(m, M_DONTWAIT); 1069 if((m->m_flags & M_EXT) == 0) { 1070 mn_free_desc(dp); 1071 return; 1072 } 1073 } 1074 dp->m = m; 1075 dp->data = vtophys(m->m_data); 1076 dp->flags = 0x40000000; 1077 dp->flags += 1600 << 16; 1078 dp->next = vtophys(dp); 1079 dp->vnext = 0; 1080 sc->ch[chan]->rl->next = vtophys(dp); 1081 sc->ch[chan]->rl->vnext = dp; 1082 sc->ch[chan]->rl->flags &= ~0x40000000; 1083 sc->ch[chan]->rl = dp; 1084 } 1085} 1086 1087 1088/* 1089 * Interupt handler 1090 */ 1091 1092static void 1093mn_intr(void *xsc) 1094{ 1095 struct softc *sc; 1096 u_int32_t stat, lstat, u; 1097 int i, j; 1098 1099 sc = xsc; 1100 stat = sc->m32x->stat; 1101 lstat = sc->m32x->lstat; 1102#if 0 1103 if (!stat && !(lstat & 2)) 1104 return; 1105#endif 1106 1107 if (stat & ~0xc200) { 1108 printf("%s: I stat=%08x lstat=%08x\n", sc->name, stat, lstat); 1109 } 1110 1111 if ((stat & 0x200) || (lstat & 2)) 1112 f54_intr(sc); 1113 1114 for (j = i = 0; i < 64; i ++) { 1115 u = sc->riqb[i]; 1116 if (u) { 1117 sc->riqb[i] = 0; 1118 mn_rx_intr(sc, u); 1119 if ((u & ~0x1f) == 0x30000800 || (u & ~0x1f) == 0x30000b00) 1120 continue; 1121 u &= ~0x30000400; /* bits we don't care about */ 1122 if ((u & ~0x1f) == 0x00000900) 1123 continue; 1124 if (!(u & ~0x1f)) 1125 continue; 1126 if (!j) 1127 printf("%s*: RIQB:", sc->name); 1128 printf(" [%d]=%08x", i, u); 1129 j++; 1130 } 1131 } 1132 if (j) 1133 printf("\n"); 1134 1135 for (j = i = 0; i < 64; i ++) { 1136 u = sc->tiqb[i]; 1137 if (u) { 1138 sc->tiqb[i] = 0; 1139 mn_tx_intr(sc, u); 1140 if ((u & ~0x1f) == 0x20000800) 1141 continue; 1142 u &= ~0x20000000; /* bits we don't care about */ 1143 if (!u) 1144 continue; 1145 if (!j) 1146 printf("%s*: TIQB:", sc->name); 1147 printf(" [%d]=%08x", i, u); 1148 j++; 1149 } 1150 } 1151 if (j) 1152 printf("\n"); 1153 sc->m32x->stat = stat; 1154} 1155 1156static void 1157mn_timeout(void *xsc) 1158{ 1159 static int round = 0; 1160 struct softc *sc; 1161 1162 mn_intr(xsc); 1163 sc = xsc; 1164 timeout(mn_timeout, xsc, 10 * hz); 1165 round++; 1166 if (round == 2) { 1167 sc->m32_mem.ccb = 0x00008004; 1168 sc->m32x->cmd = 0x1; 1169 } else if (round > 2) { 1170 printf("%s: timeout\n", sc->name); 1171 } 1172} 1173 1174/* 1175 * PCI initialization stuff 1176 */ 1177 1178static int 1179mn_probe (device_t self) 1180{ 1181 u_int id = pci_get_devid(self); 1182 1183 if (sizeof (struct m32xreg) != 256) { 1184 printf("MN: sizeof(struct m32xreg) = %d, should have been 256\n", sizeof (struct m32xreg)); 1185 return (ENXIO); 1186 } 1187 if (sizeof (struct f54rreg) != 128) { 1188 printf("MN: sizeof(struct f54rreg) = %d, should have been 128\n", sizeof (struct f54rreg)); 1189 return (ENXIO); 1190 } 1191 if (sizeof (struct f54wreg) != 128) { 1192 printf("MN: sizeof(struct f54wreg) = %d, should have been 128\n", sizeof (struct f54wreg)); 1193 return (ENXIO); 1194 } 1195 1196 if (id != 0x2101110a) 1197 return (ENXIO); 1198 1199 device_set_desc_copy(self, "Munich32X E1/T1 HDLC Controller"); 1200 return (0); 1201} 1202 1203static int 1204mn_attach (device_t self) 1205{ 1206 struct softc *sc; 1207 u_int32_t u; 1208 u_int32_t ver; 1209 static int once; 1210 int rid, error; 1211 struct resource *res; 1212 1213 if (!once) { 1214 if (ng_newtype(&mntypestruct)) 1215 printf("ng_newtype failed\n"); 1216 once++; 1217 } 1218 1219 sc = (struct softc *)malloc(sizeof *sc, M_MN, M_WAITOK); 1220 bzero(sc, sizeof *sc); 1221 device_set_softc(self, sc); 1222 1223 sc->dev = self; 1224 sc->unit = device_get_unit(self); 1225 sprintf(sc->name, "mn%d", sc->unit); 1226 1227 rid = PCIR_MAPS; 1228 res = bus_alloc_resource(self, SYS_RES_MEMORY, &rid, 1229 0, ~0, 1, RF_ACTIVE); 1230 if (res == NULL) { 1231 device_printf(self, "Could not map memory\n"); 1232 return ENXIO; 1233 } 1234 sc->m0v = rman_get_virtual(res); 1235 sc->m0p = rman_get_start(res); 1236 1237 rid = PCIR_MAPS + 4; 1238 res = bus_alloc_resource(self, SYS_RES_MEMORY, &rid, 1239 0, ~0, 1, RF_ACTIVE); 1240 if (res == NULL) { 1241 device_printf(self, "Could not map memory\n"); 1242 return ENXIO; 1243 } 1244 sc->m1v = rman_get_virtual(res); 1245 sc->m1p = rman_get_start(res); 1246 1247 /* Allocate interrupt */ 1248 rid = 0; 1249 sc->irq = bus_alloc_resource(self, SYS_RES_IRQ, &rid, 0, ~0, 1250 1, RF_SHAREABLE | RF_ACTIVE); 1251 1252 if (sc->irq == NULL) { 1253 printf("couldn't map interrupt\n"); 1254 return(ENXIO); 1255 } 1256 1257 error = bus_setup_intr(self, sc->irq, INTR_TYPE_NET, mn_intr, sc, &sc->intrhand); 1258 1259 if (error) { 1260 printf("couldn't set up irq\n"); 1261 return(ENXIO); 1262 } 1263 1264 u = pci_read_config(self, PCIR_COMMAND, 1); 1265 printf("%x\n", u); 1266 pci_write_config(self, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN, 1); 1267#if 0 1268 pci_write_config(self, PCIR_COMMAND, 0x02800046, 4); 1269#endif 1270 u = pci_read_config(self, PCIR_COMMAND, 1); 1271 printf("%x\n", u); 1272 1273 ver = pci_read_config(self, PCI_CLASS_REG, 4); 1274 1275 sc->m32x = (struct m32xreg *) sc->m0v; 1276 sc->f54w = (struct f54wreg *) sc->m1v; 1277 sc->f54r = (struct f54rreg *) sc->m1v; 1278 1279 /* We must reset before poking at FALC54 registers */ 1280 u = mn_reset(sc); 1281 if (!u) 1282 return (0); 1283 1284 printf("mn%d: Munich32X", sc->unit); 1285 switch (ver & 0xff) { 1286 case 0x13: 1287 printf(" Rev 2.2"); 1288 break; 1289 default: 1290 printf(" Rev 0x%x\n", ver & 0xff); 1291 } 1292 printf(", Falc54"); 1293 switch (sc->f54r->vstr) { 1294 case 0: 1295 printf(" Rev < 1.3\n"); 1296 break; 1297 case 1: 1298 printf(" Rev 1.3\n"); 1299 break; 1300 case 2: 1301 printf(" Rev 1.4\n"); 1302 break; 1303 case 0x10: 1304 printf("-LH Rev 1.1\n"); 1305 break; 1306 case 0x13: 1307 printf("-LH Rev 1.3\n"); 1308 break; 1309 default: 1310 printf(" Rev 0x%x\n", sc->f54r->vstr); 1311 } 1312 1313 if (ng_make_node_common(&mntypestruct, &sc->node) != 0) { 1314 printf("ng_make_node_common failed\n"); 1315 return (0); 1316 } 1317 sc->node->private = sc; 1318 sprintf(sc->nodename, "%s%d", NG_MN_NODE_TYPE, sc->unit); 1319 if (ng_name_node(sc->node, sc->nodename)) { 1320 ng_rmnode(sc->node); 1321 ng_unref(sc->node); 1322 return (0); 1323 } 1324 1325 return (0); 1326} 1327 1328 1329static device_method_t mn_methods[] = { 1330 /* Device interface */ 1331 DEVMETHOD(device_probe, mn_probe), 1332 DEVMETHOD(device_attach, mn_attach), 1333 DEVMETHOD(device_suspend, bus_generic_suspend), 1334 DEVMETHOD(device_resume, bus_generic_resume), 1335 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1336 1337 {0, 0} 1338}; 1339 1340static driver_t mn_driver = { 1341 "mn", 1342 mn_methods, 1343 0 1344}; 1345 1346static devclass_t mn_devclass; 1347 1348DRIVER_MODULE(mn, pci, mn_driver, mn_devclass, 0, 0); 1349