if_mn.c revision 62467
1/* 2 * ---------------------------------------------------------------------------- 3 * "THE BEER-WARE LICENSE" (Revision 42): 4 * <phk@FreeBSD.org> wrote this file. As long as you retain this notice you 5 * can do whatever you want with this stuff. If we meet some day, and you think 6 * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp 7 * ---------------------------------------------------------------------------- 8 * 9 * $Id: if_mn.c,v 1.1 1999/02/01 13:06:40 phk Exp $ 10 * 11 * Driver for Siemens reference design card "Easy321-R1". 12 * 13 * This card contains a FALC54 E1/T1 framer and a MUNICH32X 32-channel HDLC 14 * controller. 15 * 16 * The driver supports E1 mode with up to 31 channels. We send CRC4 but don't 17 * check it coming in. 18 * 19 * The FALC54 and MUNICH32X have far too many registers and weird modes for 20 * comfort, so I have not bothered typing it all into a "fooreg.h" file, 21 * you will (badly!) need the documentation anyway if you want to mess with 22 * this gadget. 23 * 24 * $FreeBSD: head/sys/pci/if_mn.c 62467 2000-07-03 13:08:56Z phk $ 25 */ 26 27/* 28 * Stuff to describe the MUNIC32X and FALC54 chips. 29 */ 30 31#define M32_CHAN 32 /* We have 32 channels */ 32#define M32_TS 32 /* We have 32 timeslots */ 33 34#define NG_MN_NODE_TYPE "mn" 35 36#ifdef _KERNEL 37#define PPP_HEADER_LEN 4 /* XXX: should live in some header somewhere */ 38 39#include <sys/param.h> 40#include <sys/systm.h> 41#include <sys/mbuf.h> 42#include <sys/kernel.h> 43#include <sys/sysctl.h> 44#include <sys/malloc.h> 45#include <sys/socket.h> 46#include <sys/sockio.h> 47#include <pci/pcireg.h> 48#include <pci/pcivar.h> 49#include <vm/vm.h> 50#include <vm/pmap.h> 51#include <machine/clock.h> 52 53#include <netgraph/ng_message.h> 54#include <netgraph/ng_sample.h> 55#include <netgraph/netgraph.h> 56 57#ifndef COMPAT_OLDPCI 58#error "The mn device requires the old pci compatibility shims" 59#endif 60 61static int mn_maxlatency = 1000; 62SYSCTL_INT(_debug, OID_AUTO, mn_maxlatency, CTLFLAG_RW, 63 &mn_maxlatency, 0, 64 "The number of milliseconds a packet is allowed to spend in the output queue. " 65 "If the output queue is longer than this number of milliseconds when the packet " 66 "arrives for output, the packet will be dropped." 67); 68 69#ifndef NMN 70/* Most machines don't support more than 4 busmaster PCI slots, if even that many */ 71#define NMN 4 72#endif 73 74/* From: PEB 20321 data sheet, p187, table 22 */ 75struct m32xreg { 76 u_int32_t conf, cmd, stat, imask; 77 u_int32_t fill10, piqba, piql, fill1c; 78 u_int32_t mode1, mode2, ccba, txpoll; 79 u_int32_t tiqba, tiql, riqba, riql; 80 u_int32_t lconf, lccba, fill48, ltran; 81 u_int32_t ltiqba, ltiql, lriqba, lriql; 82 u_int32_t lreg0, lreg1, lreg2, lreg3; 83 u_int32_t lreg4, lreg5, lre6, lstat; 84 u_int32_t gpdir, gpdata, gpod, fill8c; 85 u_int32_t ssccon, sscbr, ssctb, sscrb; 86 u_int32_t ssccse, sscim, fillab, fillac; 87 u_int32_t iomcon1, iomcon2, iomstat, fillbc; 88 u_int32_t iomcit0, iomcit1, iomcir0, iomcir1; 89 u_int32_t iomtmo, iomrmo, filld8, filldc; 90 u_int32_t mbcmd, mbdata1, mbdata2, mbdata3; 91 u_int32_t mbdata4, mbdata5, mbdata6, mbdata7; 92}; 93 94/* From: PEB 2254 data sheet, p80, table 10 */ 95struct f54wreg { 96 u_int16_t xfifo; 97 u_int8_t cmdr, mode, rah1, rah2, ral1, ral2; 98 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 99 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 100 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 101 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 102 u_int8_t test1, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr3; 103 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 104 u_int8_t lim2, fill39[7]; 105 u_int8_t fill40[8]; 106 u_int8_t fill48[8]; 107 u_int8_t fill50[8]; 108 u_int8_t fill58[8]; 109 u_int8_t dec, fill61, test2, fill63[5]; 110 u_int8_t fill68[8]; 111 u_int8_t xs[16]; 112}; 113 114/* From: PEB 2254 data sheet, p117, table 10 */ 115struct f54rreg { 116 u_int16_t rfifo; 117 u_int8_t fill2, mode, rah1, rah2, ral1, ral2; 118 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 119 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 120 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 121 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 122 u_int8_t test, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr13; 123 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 124 u_int8_t lim2, fill39[7]; 125 u_int8_t fill40[8]; 126 u_int8_t fill48[4], frs0, frs1, rsw, rsp; 127 u_int16_t fec, cvc, cec1, ebc; 128 u_int16_t cec2, cec3; 129 u_int8_t rsa4, rsa5, rsa6, rsa7; 130 u_int8_t rsa8, rsa6s, tsr0, tsr1, sis, rsis; 131 u_int16_t rbc; 132 u_int8_t isr0, isr1, isr2, isr3, fill6c, fill6d, gis, vstr; 133 u_int8_t rs[16]; 134}; 135 136/* Transmit & receive descriptors */ 137struct trxd { 138 u_int32_t flags; 139 vm_offset_t next; 140 vm_offset_t data; 141 u_int32_t status; /* only used for receive */ 142 struct mbuf *m; /* software use only */ 143 struct trxd *vnext; /* software use only */ 144}; 145 146/* Channel specification */ 147struct cspec { 148 u_int32_t flags; 149 vm_offset_t rdesc; 150 vm_offset_t tdesc; 151 u_int32_t itbs; 152}; 153 154struct m32_mem { 155 vm_offset_t csa; 156 u_int32_t ccb; 157 u_int32_t reserve1[2]; 158 u_int32_t ts[M32_TS]; 159 struct cspec cs[M32_CHAN]; 160 vm_offset_t crxd[M32_CHAN]; 161 vm_offset_t ctxd[M32_CHAN]; 162}; 163 164struct softc; 165struct sockaddr; 166struct rtentry; 167 168static const char* mn_probe (pcici_t tag, pcidi_t type); 169static void mn_attach (pcici_t tag, int unit); 170static u_long mn_count; 171static void mn_create_channel(struct softc *sc, int chan); 172static int mn_reset(struct softc *sc); 173static struct trxd * mn_alloc_desc(void); 174static void mn_free_desc(struct trxd *dp); 175static void mn_intr(void *xsc); 176static u_int32_t mn_parse_ts(const char *s, int *nbit); 177#ifdef notyet 178static void m32_dump(struct softc *sc); 179static void f54_dump(struct softc *sc); 180static void mn_fmt_ts(char *p, u_int32_t ts); 181#endif /* notyet */ 182 183static ng_constructor_t ngmn_constructor; 184static ng_rcvmsg_t ngmn_rcvmsg; 185static ng_shutdown_t ngmn_shutdown; 186static ng_newhook_t ngmn_newhook; 187static ng_connect_t ngmn_connect; 188static ng_rcvdata_t ngmn_rcvdata; 189static ng_disconnect_t ngmn_disconnect; 190 191static struct ng_type mntypestruct = { 192 NG_VERSION, 193 NG_MN_NODE_TYPE, 194 NULL, 195 ngmn_constructor, 196 ngmn_rcvmsg, 197 ngmn_shutdown, 198 ngmn_newhook, 199 NULL, 200 ngmn_connect, 201 ngmn_rcvdata, 202 ngmn_rcvdata, 203 ngmn_disconnect, 204 NULL 205}; 206 207static MALLOC_DEFINE(M_MN, "mn", "Mx driver related"); 208 209#define NIQB 64 210 211struct softc; 212 213struct schan { 214 enum {DOWN, UP} state; 215 struct softc *sc; 216 int chan; 217 u_int32_t ts; 218 char name[8]; 219 struct trxd *r1, *rl; 220 struct trxd *x1, *xl; 221 hook_p hook; 222 223 time_t last_recv; 224 time_t last_rxerr; 225 time_t last_xmit; 226 227 u_long rx_error; 228 229 u_long short_error; 230 u_long crc_error; 231 u_long dribble_error; 232 u_long long_error; 233 u_long abort_error; 234 u_long overflow_error; 235 236 int last_error; 237 int prev_error; 238 239 u_long tx_pending; 240 u_long tx_limit; 241}; 242 243static struct softc { 244 int unit; 245 pcici_t tag; 246 vm_offset_t m0v, m0p, m1v, m1p; 247 struct m32xreg *m32x; 248 struct f54wreg *f54w; 249 struct f54rreg *f54r; 250 struct m32_mem m32_mem; 251 u_int32_t tiqb[NIQB]; 252 u_int32_t riqb[NIQB]; 253 u_int32_t piqb[NIQB]; 254 u_int32_t ltiqb[NIQB]; 255 u_int32_t lriqb[NIQB]; 256 char name[8]; 257 u_int32_t falc_irq, falc_state, framer_state; 258 struct schan *ch[M32_CHAN]; 259 char nodename[NG_NODELEN + 1]; 260 node_p node; 261 262 u_long cnt_fec; 263 u_long cnt_cvc; 264 u_long cnt_cec1; 265 u_long cnt_ebc; 266 u_long cnt_cec2; 267 u_long cnt_cec3; 268 u_long cnt_rbc; 269} *softc[NMN]; 270 271static int 272ngmn_constructor(node_p *nodep) 273{ 274 275 return (EINVAL); 276} 277 278static int 279ngmn_shutdown(node_p nodep) 280{ 281 282 return (EINVAL); 283} 284 285static int 286ngmn_rcvmsg(node_p node, struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp, hook_p lasthook) 287{ 288 struct softc *sc; 289 struct schan *sch; 290 char *arg; 291 int pos, i; 292 293 sc = node->private; 294 295 if (msg->header.typecookie != NGM_GENERIC_COOKIE || 296 msg->header.cmd != NGM_TEXT_STATUS) { 297 if (resp) 298 *resp = NULL; 299 FREE(msg, M_NETGRAPH); 300 return (EINVAL); 301 } 302 NG_MKRESPONSE(*resp, msg, sizeof(struct ng_mesg) + NG_TEXTRESPONSE, 303 M_NOWAIT); 304 if (*resp == NULL) { 305 FREE(msg, M_NETGRAPH); 306 return (ENOMEM); 307 } 308 arg = (char *)(*resp)->data; 309 pos = 0; 310 pos += sprintf(pos + arg,"Framer status %b;\n", sc->framer_state, "\20" 311 "\40LOS\37AIS\36LFA\35RRA" 312 "\34AUXP\33NMF\32LMFA\31frs0.0" 313 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 314 "\24TS16LFA\23frs1.2\22XLS\21XLO" 315 "\20RS1\17rsw.6\16RRA\15RY0" 316 "\14RY1\13RY2\12RY3\11RY4" 317 "\10SI1\7SI2\6rsp.5\5rsp.4" 318 "\4rsp.3\3RSIF\2RS13\1RS15"); 319 pos += sprintf(pos + arg," Framing errors: %lu", sc->cnt_fec); 320 pos += sprintf(pos + arg," Code Violations: %lu\n", sc->cnt_cvc); 321 322 pos += sprintf(pos + arg," Falc State %b;\n", sc->falc_state, "\20" 323 "\40LOS\37AIS\36LFA\35RRA" 324 "\34AUXP\33NMF\32LMFA\31frs0.0" 325 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 326 "\24TS16LFA\23frs1.2\22XLS\21XLO" 327 "\20RS1\17rsw.6\16RRA\15RY0" 328 "\14RY1\13RY2\12RY3\11RY4" 329 "\10SI1\7SI2\6rsp.5\5rsp.4" 330 "\4rsp.3\3RSIF\2RS13\1RS15"); 331 pos += sprintf(pos + arg, " Falc IRQ %b\n", sc->falc_irq, "\20" 332 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 333 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 334 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 335 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 336 for (i = 0; i < M32_CHAN; i++) { 337 if (!sc->ch[i]) 338 continue; 339 sch = sc->ch[i]; 340 341 pos += sprintf(arg + pos, " Chan %d <%s> ", 342 i, sch->hook->name); 343 344 pos += sprintf(arg + pos, " Last Rx: "); 345 if (sch->last_recv) 346 pos += sprintf(arg + pos, "%lu s", time_second - sch->last_recv); 347 else 348 pos += sprintf(arg + pos, "never"); 349 350 pos += sprintf(arg + pos, ", last RxErr: "); 351 if (sch->last_rxerr) 352 pos += sprintf(arg + pos, "%lu s", time_second - sch->last_rxerr); 353 else 354 pos += sprintf(arg + pos, "never"); 355 356 pos += sprintf(arg + pos, ", last Tx: "); 357 if (sch->last_xmit) 358 pos += sprintf(arg + pos, "%lu s\n", time_second - sch->last_xmit); 359 else 360 pos += sprintf(arg + pos, "never\n"); 361 362 pos += sprintf(arg + pos, " RX error(s) %lu", sch->rx_error); 363 pos += sprintf(arg + pos, " Short: %lu", sch->short_error); 364 pos += sprintf(arg + pos, " CRC: %lu", sch->crc_error); 365 pos += sprintf(arg + pos, " Mod8: %lu", sch->dribble_error); 366 pos += sprintf(arg + pos, " Long: %lu", sch->long_error); 367 pos += sprintf(arg + pos, " Abort: %lu", sch->abort_error); 368 pos += sprintf(arg + pos, " Overflow: %lu\n", sch->overflow_error); 369 370 pos += sprintf(arg + pos, " Last error: %b Prev error: %b\n", 371 sch->last_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN", 372 sch->prev_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN"); 373 pos += sprintf(arg + pos, " Xmit bytes pending %ld\n", 374 sch->tx_pending); 375 } 376 (*resp)->header.arglen = pos + 1; 377 FREE(msg, M_NETGRAPH); 378 return (0); 379} 380 381static int 382ngmn_newhook(node_p node, hook_p hook, const char *name) 383{ 384 u_int32_t ts, chan; 385 struct softc *sc; 386 int nbit; 387 388 sc = node->private; 389 390 if (name[0] != 't' || name[1] != 's') 391 return (EINVAL); 392 393 ts = mn_parse_ts(name + 2, &nbit); 394 if (ts == 0) 395 return (EINVAL); 396 chan = ffs(ts) - 1; 397 if (!sc->ch[chan]) 398 mn_create_channel(sc, chan); 399 else if (sc->ch[chan]->state == UP) 400 return (EBUSY); 401 sc->ch[chan]->ts = ts; 402 sc->ch[chan]->hook = hook; 403 sc->ch[chan]->tx_limit = nbit * 8; 404 hook->private = sc->ch[chan]; 405 return(0); 406} 407 408 409static struct trxd *mn_desc_free; 410 411static struct trxd * 412mn_alloc_desc(void) 413{ 414 struct trxd *dp; 415 416 dp = mn_desc_free; 417 if (dp) 418 mn_desc_free = dp->vnext; 419 else 420 dp = (struct trxd *)malloc(sizeof *dp, M_MN, M_NOWAIT); 421 return (dp); 422} 423 424static void 425mn_free_desc(struct trxd *dp) 426{ 427 dp->vnext = mn_desc_free; 428 mn_desc_free = dp; 429} 430 431static u_int32_t 432mn_parse_ts(const char *s, int *nbit) 433{ 434 unsigned r; 435 int i, j; 436 char *p; 437 438 r = 0; 439 j = 0; 440 *nbit = 0; 441 while(*s) { 442 i = strtol(s, &p, 0); 443 if (i < 1 || i > 31) 444 return (0); 445 while (j && j < i) { 446 r |= 1 << j++; 447 (*nbit)++; 448 } 449 j = 0; 450 r |= 1 << i; 451 (*nbit)++; 452 if (*p == ',') { 453 s = p + 1; 454 continue; 455 } else if (*p == '-') { 456 j = i; 457 s = p + 1; 458 continue; 459 } else if (!*p) { 460 break; 461 } else { 462 return (0); 463 } 464 } 465 return (r); 466} 467 468#ifdef notyet 469static void 470mn_fmt_ts(char *p, u_int32_t ts) 471{ 472 char *s; 473 int j; 474 475 s = ""; 476 ts &= 0xfffffffe; 477 for (j = 1; j < 32; j++) { 478 if (!(ts & (1 << j))) 479 continue; 480 sprintf(p, "%s%d", s, j); 481 p += strlen(p); 482 s = ","; 483 if (!(ts & (1 << (j+1)))) 484 continue; 485 for (; j < 32; j++) 486 if (!(ts & (1 << (j+1)))) 487 break; 488 sprintf(p, "-%d", j); 489 p += strlen(p); 490 s = ","; 491 } 492} 493#endif /* notyet */ 494 495/* 496 * OUTPUT 497 */ 498 499static int 500ngmn_rcvdata(hook_p hook, struct mbuf *m, meta_p meta, 501 struct mbuf **ret_m, meta_p *ret_meta) 502{ 503 struct mbuf *m2; 504 struct trxd *dp, *dp2; 505 struct schan *sch; 506 struct softc *sc; 507 int chan, pitch, len; 508 509 sch = hook->private; 510 sc = sch->sc; 511 chan = sch->chan; 512 513 if (sch->state != UP) { 514 NG_FREE_DATA(m, meta); 515 return (0); 516 } 517 if (sch->tx_pending + m->m_pkthdr.len > sch->tx_limit * mn_maxlatency) { 518 NG_FREE_DATA(m, meta); 519 return (0); 520 } 521 NG_FREE_META(meta); 522 pitch = 0; 523 m2 = m; 524 dp2 = sc->ch[chan]->xl; 525 len = m->m_pkthdr.len; 526 while (len) { 527 dp = mn_alloc_desc(); 528 if (!dp) { 529 pitch++; 530 m_freem(m); 531 sc->ch[chan]->xl = dp2; 532 dp = dp2->vnext; 533 while (dp) { 534 dp2 = dp->vnext; 535 mn_free_desc(dp); 536 dp = dp2; 537 } 538 sc->ch[chan]->xl->vnext = 0; 539 break; 540 } 541 dp->data = vtophys(m2->m_data); 542 dp->flags = m2->m_len << 16; 543 dp->flags += 1; 544 len -= m2->m_len; 545 dp->next = vtophys(dp); 546 dp->vnext = 0; 547 sc->ch[chan]->xl->next = vtophys(dp); 548 sc->ch[chan]->xl->vnext = dp; 549 sc->ch[chan]->xl = dp; 550 if (!len) { 551 dp->m = m; 552 dp->flags |= 0xc0000000; 553 dp2->flags &= ~0x40000000; 554 } else { 555 dp->m = 0; 556 m2 = m2->m_next; 557 } 558 } 559 if (pitch) 560 printf("%s%d: Short on mem, pitched %d packets\n", 561 sc->name, chan, pitch); 562 else { 563#if 0 564 printf("%d = %d + %d (%p)\n", 565 sch->tx_pending + m->m_pkthdr.len, 566 sch->tx_pending , m->m_pkthdr.len, m); 567#endif 568 sch->tx_pending += m->m_pkthdr.len; 569 } 570 return (0); 571} 572 573/* 574 * OPEN 575 */ 576static int 577ngmn_connect(hook_p hook) 578{ 579 int i, nts, chan; 580 struct trxd *dp, *dp2; 581 struct mbuf *m; 582 struct softc *sc; 583 struct schan *sch; 584 u_int32_t u; 585 586 sch = hook->private; 587 chan = sch->chan; 588 sc = sch->sc; 589 590 if (sch->state == UP) 591 return (0); 592 sch->state = UP; 593 594 /* Count and configure the timeslots for this channel */ 595 for (nts = i = 0; i < 32; i++) 596 if (sch->ts & (1 << i)) { 597 sc->m32_mem.ts[i] = 0x00ff00ff | 598 (chan << 24) | (chan << 8); 599 nts++; 600 } 601 602 /* Init the receiver & xmitter to HDLC */ 603 sc->m32_mem.cs[chan].flags = 0x80e90006; 604 /* Allocate two buffers per timeslot */ 605 sc->m32_mem.cs[chan].itbs = nts * 2; 606 607 /* Setup a transmit chain with one descriptor */ 608 /* XXX: we actually send a 1 byte packet */ 609 dp = mn_alloc_desc(); 610 MGETHDR(m, M_WAIT, MT_DATA); 611 m->m_pkthdr.len = 0; 612 dp->m = m; 613 dp->flags = 0xc0000000 + (1 << 16); 614 dp->next = vtophys(dp); 615 dp->vnext = 0; 616 dp->data = vtophys(sc->name); 617 sc->m32_mem.cs[chan].tdesc = vtophys(dp); 618 sc->ch[chan]->x1 = dp; 619 sc->ch[chan]->xl = dp; 620 621 /* Setup a receive chain with 5 + NTS descriptors */ 622 623 dp = mn_alloc_desc(); 624 MGETHDR(m, M_WAIT, MT_DATA); 625 MCLGET(m, M_WAIT); 626 dp->m = m; 627 dp->data = vtophys(m->m_data); 628 dp->flags = 0x40000000; 629 dp->flags += 1600 << 16; 630 dp->next = vtophys(dp); 631 dp->vnext = 0; 632 sc->ch[chan]->rl = dp; 633 634 for (i = 0; i < (nts + 10); i++) { 635 dp2 = dp; 636 dp = mn_alloc_desc(); 637 MGETHDR(m, M_WAIT, MT_DATA); 638 MCLGET(m, M_WAIT); 639 dp->m = m; 640 dp->data = vtophys(m->m_data); 641 dp->flags = 0x00000000; 642 dp->flags += 1600 << 16; 643 dp->next = vtophys(dp2); 644 dp->vnext = dp2; 645 } 646 sc->m32_mem.cs[chan].rdesc = vtophys(dp); 647 sc->ch[chan]->r1 = dp; 648 649 /* Initialize this channel */ 650 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 651 sc->m32x->cmd = 0x1; 652 DELAY(1000); 653 u = sc->m32x->stat; 654 if (!(u & 1)) 655 printf("%s: init chan %d stat %08x\n", sc->name, chan, u); 656 sc->m32x->stat = 1; 657 658 return (0); 659} 660 661/* 662 * CLOSE 663 */ 664static int 665ngmn_disconnect(hook_p hook) 666{ 667 int chan, i; 668 struct softc *sc; 669 struct schan *sch; 670 struct trxd *dp, *dp2; 671 u_int32_t u; 672 673 sch = hook->private; 674 chan = sch->chan; 675 sc = sch->sc; 676 677 if (sch->state == DOWN) 678 return (0); 679 sch->state = DOWN; 680 681 /* Set receiver & transmitter off */ 682 sc->m32_mem.cs[chan].flags = 0x80920006; 683 sc->m32_mem.cs[chan].itbs = 0; 684 685 /* free the timeslots */ 686 for (i = 0; i < 32; i++) 687 if (sc->ch[chan]->ts & (1 << i)) 688 sc->m32_mem.ts[i] = 0x20002000; 689 690 /* Initialize this channel */ 691 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 692 sc->m32x->cmd = 0x1; 693 DELAY(30); 694 u = sc->m32x->stat; 695 if (!(u & 1)) 696 printf("%s: zap chan %d stat %08x\n", sc->name, chan, u); 697 sc->m32x->stat = 1; 698 699 /* Free all receive descriptors and mbufs */ 700 for (dp = sc->ch[chan]->r1; dp ; dp = dp2) { 701 if (dp->m) 702 m_freem(dp->m); 703 sc->ch[chan]->r1 = dp2 = dp->vnext; 704 mn_free_desc(dp); 705 } 706 707 /* Free all transmit descriptors and mbufs */ 708 for (dp = sc->ch[chan]->x1; dp ; dp = dp2) { 709 if (dp->m) { 710 sc->ch[chan]->tx_pending -= dp->m->m_pkthdr.len; 711 m_freem(dp->m); 712 } 713 sc->ch[chan]->x1 = dp2 = dp->vnext; 714 mn_free_desc(dp); 715 } 716 return(0); 717} 718 719/* 720 * Create a new channel. 721 */ 722static void 723mn_create_channel(struct softc *sc, int chan) 724{ 725 struct schan *sch; 726 727 sch = sc->ch[chan] = (struct schan *)malloc(sizeof *sc->ch[chan], 728 M_MN, M_WAITOK); 729 bzero(sch, sizeof *sch); 730 sch->sc = sc; 731 sch->state = DOWN; 732 sch->chan = chan; 733 sprintf(sch->name, "%s%d", sc->name, chan); 734 return; 735} 736 737#ifdef notyet 738/* 739 * Dump Munich32x state 740 */ 741static void 742m32_dump(struct softc *sc) 743{ 744 u_int32_t *tp4; 745 int i, j; 746 747 printf("mn%d: MUNICH32X dump\n", sc->unit); 748 tp4 = (u_int32_t *)sc->m0v; 749 for(j = 0; j < 64; j += 8) { 750 printf("%02x", j * sizeof *tp4); 751 for(i = 0; i < 8; i++) 752 printf(" %08x", tp4[i+j]); 753 printf("\n"); 754 } 755 for(j = 0; j < M32_CHAN; j++) { 756 if (!sc->ch[j]) 757 continue; 758 printf("CH%d: state %d ts %08x", 759 j, sc->ch[j]->state, sc->ch[j]->ts); 760 printf(" %08x %08x %08x %08x %08x %08x\n", 761 sc->m32_mem.cs[j].flags, 762 sc->m32_mem.cs[j].rdesc, 763 sc->m32_mem.cs[j].tdesc, 764 sc->m32_mem.cs[j].itbs, 765 sc->m32_mem.crxd[j], 766 sc->m32_mem.ctxd[j] ); 767 } 768} 769 770/* 771 * Dump Falch54 state 772 */ 773static void 774f54_dump(struct softc *sc) 775{ 776 u_int8_t *tp1; 777 int i, j; 778 779 printf("%s: FALC54 dump\n", sc->name); 780 tp1 = (u_int8_t *)sc->m1v; 781 for(j = 0; j < 128; j += 16) { 782 printf("%s: %02x |", sc->name, j * sizeof *tp1); 783 for(i = 0; i < 16; i++) 784 printf(" %02x", tp1[i+j]); 785 printf("\n"); 786 } 787} 788#endif /* notyet */ 789 790/* 791 * Init Munich32x 792 */ 793static void 794m32_init(struct softc *sc) 795{ 796 797 sc->m32x->conf = 0x00000000; 798 sc->m32x->mode1 = 0x81048000 + 1600; /* XXX: temp */ 799#if 1 800 sc->m32x->mode2 = 0x00000081; 801 sc->m32x->txpoll = 0xffffffff; 802#else 803 sc->m32x->mode2 = 0x00000101; 804#endif 805 sc->m32x->lconf = 0x6060009B; 806 sc->m32x->imask = 0x00000000; 807} 808 809/* 810 * Init the Falc54 811 */ 812static void 813f54_init(struct softc *sc) 814{ 815 sc->f54w->ipc = 0x07; 816 817 sc->f54w->xpm0 = 0xbd; 818 sc->f54w->xpm1 = 0x03; 819 sc->f54w->xpm2 = 0x00; 820 821 sc->f54w->imr0 = 0x18; /* RMB, CASC */ 822 sc->f54w->imr1 = 0x08; /* XMB */ 823 sc->f54w->imr2 = 0x00; 824 sc->f54w->imr3 = 0x38; /* LMFA16, AIS16, RA16 */ 825 sc->f54w->imr4 = 0x00; 826 827 sc->f54w->fmr0 = 0xf0; /* X: HDB3, R: HDB3 */ 828 sc->f54w->fmr1 = 0x0e; /* Send CRC4, 2Mbit, ECM */ 829 sc->f54w->fmr2 = 0x03; /* Auto Rem-Alarm, Auto resync */ 830 831 sc->f54w->lim1 = 0xb0; /* XCLK=8kHz, .62V threshold */ 832 sc->f54w->pcd = 0x0a; 833 sc->f54w->pcr = 0x15; 834 sc->f54w->xsw = 0x9f; /* fmr4 */ 835 sc->f54w->xsp = 0x1c; /* fmr5 */ 836 sc->f54w->xc0 = 0x07; 837 sc->f54w->xc1 = 0x3d; 838 sc->f54w->rc0 = 0x05; 839 sc->f54w->rc1 = 0x00; 840 sc->f54w->cmdr = 0x51; 841} 842 843static int 844mn_reset(struct softc *sc) 845{ 846 u_int32_t u; 847 int i; 848 849 sc->m32x->ccba = vtophys(&sc->m32_mem.csa); 850 sc->m32_mem.csa = vtophys(&sc->m32_mem.ccb); 851 852 bzero(sc->tiqb, sizeof sc->tiqb); 853 sc->m32x->tiqba = vtophys(&sc->tiqb); 854 sc->m32x->tiql = NIQB / 16 - 1; 855 856 bzero(sc->riqb, sizeof sc->riqb); 857 sc->m32x->riqba = vtophys(&sc->riqb); 858 sc->m32x->riql = NIQB / 16 - 1; 859 860 bzero(sc->ltiqb, sizeof sc->ltiqb); 861 sc->m32x->ltiqba = vtophys(&sc->ltiqb); 862 sc->m32x->ltiql = NIQB / 16 - 1; 863 864 bzero(sc->lriqb, sizeof sc->lriqb); 865 sc->m32x->lriqba = vtophys(&sc->lriqb); 866 sc->m32x->lriql = NIQB / 16 - 1; 867 868 bzero(sc->piqb, sizeof sc->piqb); 869 sc->m32x->piqba = vtophys(&sc->piqb); 870 sc->m32x->piql = NIQB / 16 - 1; 871 872 m32_init(sc); 873 f54_init(sc); 874 875 u = sc->m32x->stat; 876 sc->m32x->stat = u; 877 sc->m32_mem.ccb = 0x4; 878 sc->m32x->cmd = 0x1; 879 DELAY(1000); 880 u = sc->m32x->stat; 881 sc->m32x->stat = u; 882 883 /* set all timeslots to known state */ 884 for (i = 0; i < 32; i++) 885 sc->m32_mem.ts[i] = 0x20002000; 886 887 if (!(u & 1)) { 888 printf( 889"mn%d: WARNING: Controller failed the PCI bus-master test.\n" 890"mn%d: WARNING: Use a PCI slot which can support bus-master cards.\n", 891 sc->unit, sc->unit); 892 return (0); 893 } 894 return (1); 895} 896 897/* 898 * FALC54 interrupt handling 899 */ 900static void 901f54_intr(struct softc *sc) 902{ 903 unsigned g, u, s; 904 905 g = sc->f54r->gis; 906 u = sc->f54r->isr0 << 24; 907 u |= sc->f54r->isr1 << 16; 908 u |= sc->f54r->isr2 << 8; 909 u |= sc->f54r->isr3; 910 sc->falc_irq = u; 911 /* don't chat about the 1 sec heart beat */ 912 if (u & ~0x40) { 913#if 0 914 printf("%s*: FALC54 IRQ GIS:%02x %b\n", sc->name, g, u, "\20" 915 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 916 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 917 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 918 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 919#endif 920 s = sc->f54r->frs0 << 24; 921 s |= sc->f54r->frs1 << 16; 922 s |= sc->f54r->rsw << 8; 923 s |= sc->f54r->rsp; 924 sc->falc_state = s; 925 926 s &= ~0x01844038; /* undefined or static bits */ 927 s &= ~0x00009fc7; /* bits we don't care about */ 928 s &= ~0x00780000; /* XXX: TS16 related */ 929 s &= ~0x06000000; /* XXX: Multiframe related */ 930#if 0 931 printf("%s*: FALC54 Status %b\n", sc->name, s, "\20" 932 "\40LOS\37AIS\36LFA\35RRA\34AUXP\33NMF\32LMFA\31frs0.0" 933 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS\24TS16LFA\23frs1.2\22XLS\21XLO" 934 "\20RS1\17rsw.6\16RRA\15RY0\14RY1\13RY2\12RY3\11RY4" 935 "\10SI1\7SI2\6rsp.5\5rsp.4\4rsp.3\3RSIF\2RS13\1RS15"); 936#endif 937 if (s != sc->framer_state) { 938#if 0 939 for (i = 0; i < M32_CHAN; i++) { 940 if (!sc->ch[i]) 941 continue; 942 sp = &sc->ch[i]->ifsppp; 943 if (!(sp->pp_if.if_flags & IFF_UP)) 944 continue; 945 if (s) 946 timeout((timeout_t *)sp->pp_down, sp, 1 * hz); 947 else 948 timeout((timeout_t *)sp->pp_up, sp, 1 * hz); 949 } 950#endif 951 sc->framer_state = s; 952 } 953 } 954 /* Once per second check error counters */ 955 /* XXX: not clear if this is actually ok */ 956 if (!(u & 0x40)) 957 return; 958 sc->cnt_fec += sc->f54r->fec; 959 sc->cnt_cvc += sc->f54r->cvc; 960 sc->cnt_cec1 += sc->f54r->cec1; 961 sc->cnt_ebc += sc->f54r->ebc; 962 sc->cnt_cec2 += sc->f54r->cec2; 963 sc->cnt_cec3 += sc->f54r->cec3; 964 sc->cnt_rbc += sc->f54r->rbc; 965} 966 967/* 968 * Transmit interrupt for one channel 969 */ 970static void 971mn_tx_intr(struct softc *sc, u_int32_t vector) 972{ 973 u_int32_t chan; 974 struct trxd *dp; 975 struct mbuf *m; 976 977 chan = vector & 0x1f; 978 if (!sc->ch[chan]) 979 return; 980 if (sc->ch[chan]->state != UP) { 981 printf("%s: tx_intr when not UP\n", sc->name); 982 return; 983 } 984 for (;;) { 985 dp = sc->ch[chan]->x1; 986 if (vtophys(dp) == sc->m32_mem.ctxd[chan]) 987 return; 988 m = dp->m; 989 if (m) { 990#if 0 991 printf("%d = %d - %d (%p)\n", 992 sc->ch[chan]->tx_pending - m->m_pkthdr.len, 993 sc->ch[chan]->tx_pending , m->m_pkthdr.len, m); 994#endif 995 sc->ch[chan]->tx_pending -= m->m_pkthdr.len; 996 m_freem(m); 997 } 998 sc->ch[chan]->last_xmit = time_second; 999 sc->ch[chan]->x1 = dp->vnext; 1000 mn_free_desc(dp); 1001 } 1002} 1003 1004/* 1005 * Receive interrupt for one channel 1006 */ 1007static void 1008mn_rx_intr(struct softc *sc, u_int32_t vector) 1009{ 1010 u_int32_t chan, err; 1011 struct trxd *dp; 1012 struct mbuf *m; 1013 struct schan *sch; 1014 1015 chan = vector & 0x1f; 1016 if (!sc->ch[chan]) 1017 return; 1018 sch = sc->ch[chan]; 1019 if (sch->state != UP) { 1020 printf("%s: rx_intr when not UP\n", sc->name); 1021 return; 1022 } 1023 vector &= ~0x1f; 1024 if (vector == 0x30000b00) 1025 sch->rx_error++; 1026 for (;;) { 1027 dp = sch->r1; 1028 if (vtophys(dp) == sc->m32_mem.crxd[chan]) 1029 return; 1030 m = dp->m; 1031 dp->m = 0; 1032 m->m_pkthdr.len = m->m_len = (dp->status >> 16) & 0x1fff; 1033 err = (dp->status >> 8) & 0xff; 1034 if (!err) { 1035 ng_queue_data(sch->hook, m, NULL); 1036 sch->last_recv = time_second; 1037 m = 0; 1038 /* we could be down by now... */ 1039 if (sch->state != UP) 1040 return; 1041 } else if (err & 0x40) { 1042 sch->short_error++; 1043 } else if (err & 0x10) { 1044 sch->crc_error++; 1045 } else if (err & 0x08) { 1046 sch->dribble_error++; 1047 } else if (err & 0x04) { 1048 sch->long_error++; 1049 } else if (err & 0x02) { 1050 sch->abort_error++; 1051 } else if (err & 0x01) { 1052 sch->overflow_error++; 1053 } 1054 if (err) { 1055 sch->last_rxerr = time_second; 1056 sch->prev_error = sch->last_error; 1057 sch->last_error = err; 1058 } 1059 1060 sc->ch[chan]->r1 = dp->vnext; 1061 1062 /* Replenish desc + mbuf supplies */ 1063 if (!m) { 1064 MGETHDR(m, M_DONTWAIT, MT_DATA); 1065 if (m == NULL) { 1066 mn_free_desc(dp); 1067 return; 1068 } 1069 MCLGET(m, M_DONTWAIT); 1070 if((m->m_flags & M_EXT) == 0) { 1071 mn_free_desc(dp); 1072 return; 1073 } 1074 } 1075 dp->m = m; 1076 dp->data = vtophys(m->m_data); 1077 dp->flags = 0x40000000; 1078 dp->flags += 1600 << 16; 1079 dp->next = vtophys(dp); 1080 dp->vnext = 0; 1081 sc->ch[chan]->rl->next = vtophys(dp); 1082 sc->ch[chan]->rl->vnext = dp; 1083 sc->ch[chan]->rl->flags &= ~0x40000000; 1084 sc->ch[chan]->rl = dp; 1085 } 1086} 1087 1088 1089/* 1090 * Interupt handler 1091 */ 1092 1093static void 1094mn_intr(void *xsc) 1095{ 1096 struct softc *sc; 1097 u_int32_t stat, lstat, u; 1098 int i, j; 1099 1100 sc = xsc; 1101 stat = sc->m32x->stat; 1102 lstat = sc->m32x->lstat; 1103#if 0 1104 if (!stat && !(lstat & 2)) 1105 return; 1106#endif 1107 1108 if (stat & ~0xc200) { 1109 printf("%s: I stat=%08x lstat=%08x\n", sc->name, stat, lstat); 1110 } 1111 1112 if ((stat & 0x200) || (lstat & 2)) 1113 f54_intr(sc); 1114 1115 for (j = i = 0; i < 64; i ++) { 1116 u = sc->riqb[i]; 1117 if (u) { 1118 sc->riqb[i] = 0; 1119 mn_rx_intr(sc, u); 1120 if ((u & ~0x1f) == 0x30000800 || (u & ~0x1f) == 0x30000b00) 1121 continue; 1122 u &= ~0x30000400; /* bits we don't care about */ 1123 if ((u & ~0x1f) == 0x00000900) 1124 continue; 1125 if (!(u & ~0x1f)) 1126 continue; 1127 if (!j) 1128 printf("%s*: RIQB:", sc->name); 1129 printf(" [%d]=%08x", i, u); 1130 j++; 1131 } 1132 } 1133 if (j) 1134 printf("\n"); 1135 1136 for (j = i = 0; i < 64; i ++) { 1137 u = sc->tiqb[i]; 1138 if (u) { 1139 sc->tiqb[i] = 0; 1140 mn_tx_intr(sc, u); 1141 if ((u & ~0x1f) == 0x20000800) 1142 continue; 1143 u &= ~0x20000000; /* bits we don't care about */ 1144 if (!u) 1145 continue; 1146 if (!j) 1147 printf("%s*: TIQB:", sc->name); 1148 printf(" [%d]=%08x", i, u); 1149 j++; 1150 } 1151 } 1152 if (j) 1153 printf("\n"); 1154 sc->m32x->stat = stat; 1155} 1156 1157static void 1158mn_timeout(void *xsc) 1159{ 1160 static int round = 0; 1161 struct softc *sc; 1162 1163 mn_intr(xsc); 1164 sc = xsc; 1165 timeout(mn_timeout, xsc, 10 * hz); 1166 round++; 1167 if (round == 2) { 1168 sc->m32_mem.ccb = 0x00008004; 1169 sc->m32x->cmd = 0x1; 1170 } else if (round > 2) { 1171 printf("%s: timeout\n", sc->name); 1172 } 1173} 1174 1175/* 1176 * PCI initialization stuff 1177 */ 1178 1179static struct pci_device mn_device = { 1180 "mn", 1181 mn_probe, 1182 mn_attach, 1183 &mn_count, 1184 NULL 1185}; 1186 1187#ifdef COMPAT_PCI_DRIVER 1188COMPAT_PCI_DRIVER(ti, mn_device); 1189#else 1190DATA_SET(pcidevice_set, mn_device); 1191#endif /* COMPAT_PCI_DRIVER */ 1192 1193static const char* 1194mn_probe (pcici_t tag, pcidi_t typea) 1195{ 1196 u_int id = pci_conf_read(tag, PCI_ID_REG); 1197 1198 if (sizeof (struct m32xreg) != 256) { 1199 printf("MN: sizeof(struct m32xreg) = %d, should have been 256\n", sizeof (struct m32xreg)); 1200 return (0); 1201 } 1202 if (sizeof (struct f54rreg) != 128) { 1203 printf("MN: sizeof(struct f54rreg) = %d, should have been 128\n", sizeof (struct f54rreg)); 1204 return (0); 1205 } 1206 if (sizeof (struct f54wreg) != 128) { 1207 printf("MN: sizeof(struct f54wreg) = %d, should have been 128\n", sizeof (struct f54wreg)); 1208 return (0); 1209 } 1210 1211 if (id == 0x2101110a) 1212 return "Munich32X E1/T1 HDLC Controller"; 1213 1214 return 0; 1215} 1216 1217static void 1218mn_attach (pcici_t tag, int unit) 1219{ 1220 struct softc *sc; 1221 u_int32_t u; 1222 u_int32_t pci_class; 1223 static int once; 1224 1225 if (!once) { 1226 if (ng_newtype(&mntypestruct)) 1227 printf("ng_newtype failed\n"); 1228 once++; 1229 } 1230 1231 sc = (struct softc *)malloc(sizeof *sc, M_MN, M_WAITOK); 1232 softc[unit] = sc; 1233 bzero(sc, sizeof *sc); 1234 1235 sc->tag = tag; 1236 sc->unit = unit; 1237 sprintf(sc->name, "mn%d", unit); 1238 1239 if (!pci_map_int(tag, mn_intr, sc, &net_imask)) { 1240 printf("mn%d: could not map interrupt\n", sc->unit); 1241 return; 1242 } 1243 pci_map_mem(tag, PCI_MAP_REG_START, &sc->m0v, &sc->m0p); 1244 pci_map_mem(tag, PCI_MAP_REG_START + 4, &sc->m1v, &sc->m1p); 1245 1246 u = pci_conf_read(tag, PCIR_COMMAND); 1247 pci_conf_write(tag, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); 1248 pci_conf_write(tag, PCIR_COMMAND, 0x02800046); 1249 1250 pci_class = pci_conf_read(tag, PCI_CLASS_REG); 1251 1252 sc->m32x = (struct m32xreg *) sc->m0v; 1253 sc->f54w = (struct f54wreg *) sc->m1v; 1254 sc->f54r = (struct f54rreg *) sc->m1v; 1255 1256 /* We must reset before poking at FALC54 registers */ 1257 u = mn_reset(sc); 1258 if (!u) 1259 return; 1260 1261 printf("mn%d: Munich32X", sc->unit); 1262 switch (pci_class & 0xff) { 1263 case 0x13: 1264 printf(" Rev 2.2"); 1265 break; 1266 default: 1267 printf(" Rev 0x%x\n", pci_class & 0xff); 1268 } 1269 printf(", Falc54"); 1270 switch (sc->f54r->vstr) { 1271 case 0: 1272 printf(" Rev < 1.3\n"); 1273 break; 1274 case 1: 1275 printf(" Rev 1.3\n"); 1276 break; 1277 case 2: 1278 printf(" Rev 1.4\n"); 1279 break; 1280 case 0x10: 1281 printf("-LH Rev 1.1\n"); 1282 break; 1283 case 0x13: 1284 printf("-LH Rev 1.3\n"); 1285 break; 1286 default: 1287 printf(" Rev 0x%x\n", sc->f54r->vstr); 1288 } 1289 1290 if (ng_make_node_common(&mntypestruct, &sc->node) != 0) { 1291 printf("ng_make_node_common failed\n"); 1292 return; 1293 } 1294 sc->node->private = sc; 1295 sprintf(sc->nodename, "%s%d", NG_MN_NODE_TYPE, sc->unit); 1296 if (ng_name_node(sc->node, sc->nodename)) { 1297 ng_rmnode(sc->node); 1298 ng_unref(sc->node); 1299 return; 1300 } 1301 1302 return; 1303} 1304#endif /* _KERNEL */ 1305