if_mn.c revision 58700
1/* 2 * ---------------------------------------------------------------------------- 3 * "THE BEER-WARE LICENSE" (Revision 42): 4 * <phk@FreeBSD.org> wrote this file. As long as you retain this notice you 5 * can do whatever you want with this stuff. If we meet some day, and you think 6 * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp 7 * ---------------------------------------------------------------------------- 8 * 9 * $Id: if_mn.c,v 1.1 1999/02/01 13:06:40 phk Exp $ 10 * 11 * Driver for Siemens reference design card "Easy321-R1". 12 * 13 * This card contains a FALC54 E1/T1 framer and a MUNICH32X 32-channel HDLC 14 * controller. 15 * 16 * The driver supports E1 mode with up to 31 channels. We send CRC4 but don't 17 * check it coming in. 18 * 19 * The FALC54 and MUNICH32X have far too many registers and weird modes for 20 * comfort, so I have not bothered typing it all into a "fooreg.h" file, 21 * you will (badly!) need the documentation anyway if you want to mess with 22 * this gadget. 23 * 24 * $FreeBSD: head/sys/pci/if_mn.c 58700 2000-03-27 20:05:04Z phk $ 25 */ 26 27#ifndef COMPAT_OLDPCI 28#error "The mn device requires the old pci compatibility shims" 29#endif 30 31/* 32 * Stuff to describe the MUNIC32X and FALC54 chips. 33 */ 34 35#define M32_CHAN 32 /* We have 32 channels */ 36#define M32_TS 32 /* We have 32 timeslots */ 37 38#define NG_MN_NODE_TYPE "mn" 39 40#ifdef _KERNEL 41#define PPP_HEADER_LEN 4 /* XXX: should live in some header somewhere */ 42 43#include <sys/param.h> 44#include <sys/systm.h> 45#include <sys/conf.h> 46#include <sys/mbuf.h> 47#include <sys/kernel.h> 48#include <sys/sysctl.h> 49#include <sys/malloc.h> 50#include <sys/socket.h> 51#include <sys/sockio.h> 52#include <pci/pcireg.h> 53#include <pci/pcivar.h> 54#include <vm/vm.h> 55#include <vm/pmap.h> 56#include <machine/clock.h> 57 58#include <netgraph/ng_message.h> 59#include <netgraph/ng_sample.h> 60#include <netgraph/netgraph.h> 61 62static int mn_maxlatency = 1000; 63SYSCTL_INT(_debug, OID_AUTO, mn_maxlatency, CTLFLAG_RW, 64 &mn_maxlatency, 0, 65 "The number of milliseconds a packet is allowed to spend in the output queue. " 66 "If the output queue is longer than this number of milliseconds when the packet " 67 "arrives for output, the packet will be dropped." 68); 69 70#ifndef NMN 71/* Most machines don't support more than 4 busmaster PCI slots, if even that many */ 72#define NMN 4 73#endif 74 75/* From: PEB 20321 data sheet, p187, table 22 */ 76struct m32xreg { 77 u_int32_t conf, cmd, stat, imask; 78 u_int32_t fill10, piqba, piql, fill1c; 79 u_int32_t mode1, mode2, ccba, txpoll; 80 u_int32_t tiqba, tiql, riqba, riql; 81 u_int32_t lconf, lccba, fill48, ltran; 82 u_int32_t ltiqba, ltiql, lriqba, lriql; 83 u_int32_t lreg0, lreg1, lreg2, lreg3; 84 u_int32_t lreg4, lreg5, lre6, lstat; 85 u_int32_t gpdir, gpdata, gpod, fill8c; 86 u_int32_t ssccon, sscbr, ssctb, sscrb; 87 u_int32_t ssccse, sscim, fillab, fillac; 88 u_int32_t iomcon1, iomcon2, iomstat, fillbc; 89 u_int32_t iomcit0, iomcit1, iomcir0, iomcir1; 90 u_int32_t iomtmo, iomrmo, filld8, filldc; 91 u_int32_t mbcmd, mbdata1, mbdata2, mbdata3; 92 u_int32_t mbdata4, mbdata5, mbdata6, mbdata7; 93}; 94 95/* From: PEB 2254 data sheet, p80, table 10 */ 96struct f54wreg { 97 u_int16_t xfifo; 98 u_int8_t cmdr, mode, rah1, rah2, ral1, ral2; 99 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 100 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 101 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 102 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 103 u_int8_t test1, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr3; 104 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 105 u_int8_t lim2, fill39[7]; 106 u_int8_t fill40[8]; 107 u_int8_t fill48[8]; 108 u_int8_t fill50[8]; 109 u_int8_t fill58[8]; 110 u_int8_t dec, fill61, test2, fill63[5]; 111 u_int8_t fill68[8]; 112 u_int8_t xs[16]; 113}; 114 115/* From: PEB 2254 data sheet, p117, table 10 */ 116struct f54rreg { 117 u_int16_t rfifo; 118 u_int8_t fill2, mode, rah1, rah2, ral1, ral2; 119 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 120 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 121 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 122 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 123 u_int8_t test, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr13; 124 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 125 u_int8_t lim2, fill39[7]; 126 u_int8_t fill40[8]; 127 u_int8_t fill48[4], frs0, frs1, rsw, rsp; 128 u_int16_t fec, cvc, cec1, ebc; 129 u_int16_t cec2, cec3; 130 u_int8_t rsa4, rsa5, rsa6, rsa7; 131 u_int8_t rsa8, rsa6s, tsr0, tsr1, sis, rsis; 132 u_int16_t rbc; 133 u_int8_t isr0, isr1, isr2, isr3, fill6c, fill6d, gis, vstr; 134 u_int8_t rs[16]; 135}; 136 137/* Transmit & receive descriptors */ 138struct trxd { 139 u_int32_t flags; 140 vm_offset_t next; 141 vm_offset_t data; 142 u_int32_t status; /* only used for receive */ 143 struct mbuf *m; /* software use only */ 144 struct trxd *vnext; /* software use only */ 145}; 146 147/* Channel specification */ 148struct cspec { 149 u_int32_t flags; 150 vm_offset_t rdesc; 151 vm_offset_t tdesc; 152 u_int32_t itbs; 153}; 154 155struct m32_mem { 156 vm_offset_t csa; 157 u_int32_t ccb; 158 u_int32_t reserve1[2]; 159 u_int32_t ts[M32_TS]; 160 struct cspec cs[M32_CHAN]; 161 vm_offset_t crxd[M32_CHAN]; 162 vm_offset_t ctxd[M32_CHAN]; 163}; 164 165struct softc; 166struct sockaddr; 167struct rtentry; 168 169static const char* mn_probe (pcici_t tag, pcidi_t type); 170static void mn_attach (pcici_t tag, int unit); 171static u_long mn_count; 172static void mn_create_channel(struct softc *sc, int chan); 173static int mn_reset(struct softc *sc); 174static struct trxd * mn_alloc_desc(void); 175static void mn_free_desc(struct trxd *dp); 176static void mn_intr(void *xsc); 177static u_int32_t mn_parse_ts(const char *s, int *nbit); 178#ifdef notyet 179static void m32_dump(struct softc *sc); 180static void f54_dump(struct softc *sc); 181static void mn_fmt_ts(char *p, u_int32_t ts); 182#endif /* notyet */ 183 184static ng_constructor_t ngmn_constructor; 185static ng_rcvmsg_t ngmn_rcvmsg; 186static ng_shutdown_t ngmn_shutdown; 187static ng_newhook_t ngmn_newhook; 188static ng_connect_t ngmn_connect; 189static ng_rcvdata_t ngmn_rcvdata; 190static ng_disconnect_t ngmn_disconnect; 191 192static struct ng_type mntypestruct = { 193 NG_VERSION, 194 NG_MN_NODE_TYPE, 195 NULL, 196 ngmn_constructor, 197 ngmn_rcvmsg, 198 ngmn_shutdown, 199 ngmn_newhook, 200 NULL, 201 ngmn_connect, 202 ngmn_rcvdata, 203 ngmn_rcvdata, 204 ngmn_disconnect, 205 NULL 206}; 207 208static MALLOC_DEFINE(M_MN, "mn", "Mx driver related"); 209 210#define NIQB 64 211 212struct softc; 213 214struct schan { 215 enum {DOWN, UP} state; 216 struct softc *sc; 217 int chan; 218 u_int32_t ts; 219 char name[8]; 220 struct trxd *r1, *rl; 221 struct trxd *x1, *xl; 222 hook_p hook; 223 224 time_t last_recv; 225 time_t last_rxerr; 226 time_t last_xmit; 227 228 u_long rx_error; 229 230 u_long short_error; 231 u_long crc_error; 232 u_long dribble_error; 233 u_long long_error; 234 u_long abort_error; 235 u_long overflow_error; 236 237 int last_error; 238 int prev_error; 239 240 u_long tx_pending; 241 u_long tx_limit; 242}; 243 244static struct softc { 245 int unit; 246 pcici_t tag; 247 vm_offset_t m0v, m0p, m1v, m1p; 248 struct m32xreg *m32x; 249 struct f54wreg *f54w; 250 struct f54rreg *f54r; 251 struct m32_mem m32_mem; 252 u_int32_t tiqb[NIQB]; 253 u_int32_t riqb[NIQB]; 254 u_int32_t piqb[NIQB]; 255 u_int32_t ltiqb[NIQB]; 256 u_int32_t lriqb[NIQB]; 257 char name[8]; 258 u_int32_t falc_irq, falc_state, framer_state; 259 struct schan *ch[M32_CHAN]; 260 char nodename[NG_NODELEN + 1]; 261 node_p node; 262 263 u_long cnt_fec; 264 u_long cnt_cvc; 265 u_long cnt_cec1; 266 u_long cnt_ebc; 267 u_long cnt_cec2; 268 u_long cnt_cec3; 269 u_long cnt_rbc; 270} *softc[NMN]; 271 272static int 273ngmn_constructor(node_p *nodep) 274{ 275 276 return (EINVAL); 277} 278 279static int 280ngmn_shutdown(node_p nodep) 281{ 282 283 return (EINVAL); 284} 285 286static int 287ngmn_rcvmsg(node_p node, struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp) 288{ 289 struct softc *sc; 290 struct schan *sch; 291 char *arg; 292 int pos, i; 293 294 sc = node->private; 295 296 if (msg->header.typecookie != NGM_GENERIC_COOKIE || 297 msg->header.cmd != NGM_TEXT_STATUS) { 298 if (resp) 299 *resp = NULL; 300 FREE(msg, M_NETGRAPH); 301 return (EINVAL); 302 } 303 NG_MKRESPONSE(*resp, msg, sizeof(struct ng_mesg) + NG_TEXTRESPONSE, 304 M_NOWAIT); 305 if (*resp == NULL) { 306 FREE(msg, M_NETGRAPH); 307 return (ENOMEM); 308 } 309 arg = (char *)(*resp)->data; 310 pos = 0; 311 pos += sprintf(pos + arg,"Framer status %b;\n", sc->framer_state, "\20" 312 "\40LOS\37AIS\36LFA\35RRA" 313 "\34AUXP\33NMF\32LMFA\31frs0.0" 314 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 315 "\24TS16LFA\23frs1.2\22XLS\21XLO" 316 "\20RS1\17rsw.6\16RRA\15RY0" 317 "\14RY1\13RY2\12RY3\11RY4" 318 "\10SI1\7SI2\6rsp.5\5rsp.4" 319 "\4rsp.3\3RSIF\2RS13\1RS15"); 320 pos += sprintf(pos + arg," Framing errors: %lu", sc->cnt_fec); 321 pos += sprintf(pos + arg," Code Violations: %lu\n", sc->cnt_cvc); 322 323 pos += sprintf(pos + arg," Falc State %b;\n", sc->falc_state, "\20" 324 "\40LOS\37AIS\36LFA\35RRA" 325 "\34AUXP\33NMF\32LMFA\31frs0.0" 326 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 327 "\24TS16LFA\23frs1.2\22XLS\21XLO" 328 "\20RS1\17rsw.6\16RRA\15RY0" 329 "\14RY1\13RY2\12RY3\11RY4" 330 "\10SI1\7SI2\6rsp.5\5rsp.4" 331 "\4rsp.3\3RSIF\2RS13\1RS15"); 332 pos += sprintf(pos + arg, " Falc IRQ %b\n", sc->falc_irq, "\20" 333 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 334 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 335 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 336 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 337 for (i = 0; i < M32_CHAN; i++) { 338 if (!sc->ch[i]) 339 continue; 340 sch = sc->ch[i]; 341 342 pos += sprintf(arg + pos, " Chan %d <%s> ", 343 i, sch->hook->name); 344 345 pos += sprintf(arg + pos, " Last Rx: "); 346 if (sch->last_recv) 347 pos += sprintf(arg + pos, "%lu s", time_second - sch->last_recv); 348 else 349 pos += sprintf(arg + pos, "never"); 350 351 pos += sprintf(arg + pos, ", last RxErr: "); 352 if (sch->last_rxerr) 353 pos += sprintf(arg + pos, "%lu s", time_second - sch->last_rxerr); 354 else 355 pos += sprintf(arg + pos, "never"); 356 357 pos += sprintf(arg + pos, ", last Tx: "); 358 if (sch->last_xmit) 359 pos += sprintf(arg + pos, "%lu s\n", time_second - sch->last_xmit); 360 else 361 pos += sprintf(arg + pos, "never\n"); 362 363 pos += sprintf(arg + pos, " RX error(s) %lu", sch->rx_error); 364 pos += sprintf(arg + pos, " Short: %lu", sch->short_error); 365 pos += sprintf(arg + pos, " CRC: %lu", sch->crc_error); 366 pos += sprintf(arg + pos, " Mod8: %lu", sch->dribble_error); 367 pos += sprintf(arg + pos, " Long: %lu", sch->long_error); 368 pos += sprintf(arg + pos, " Abort: %lu", sch->abort_error); 369 pos += sprintf(arg + pos, " Overflow: %lu\n", sch->overflow_error); 370 371 pos += sprintf(arg + pos, " Last error: %b Prev error: %b\n", 372 sch->last_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN", 373 sch->prev_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN"); 374 pos += sprintf(arg + pos, " Xmit bytes pending %ld\n", 375 sch->tx_pending); 376 } 377 (*resp)->header.arglen = pos + 1; 378 FREE(msg, M_NETGRAPH); 379 return (0); 380} 381 382static int 383ngmn_newhook(node_p node, hook_p hook, const char *name) 384{ 385 u_int32_t ts, chan; 386 struct softc *sc; 387 int nbit; 388 389 sc = node->private; 390 391 if (name[0] != 't' || name[1] != 's') 392 return (EINVAL); 393 394 ts = mn_parse_ts(name + 2, &nbit); 395 if (ts == 0) 396 return (EINVAL); 397 chan = ffs(ts) - 1; 398 if (!sc->ch[chan]) 399 mn_create_channel(sc, chan); 400 else if (sc->ch[chan]->state == UP) 401 return (EBUSY); 402 sc->ch[chan]->ts = ts; 403 sc->ch[chan]->hook = hook; 404 sc->ch[chan]->tx_limit = nbit * 8; 405 hook->private = sc->ch[chan]; 406 return(0); 407} 408 409 410static struct trxd *mn_desc_free; 411 412static struct trxd * 413mn_alloc_desc(void) 414{ 415 struct trxd *dp; 416 417 dp = mn_desc_free; 418 if (dp) 419 mn_desc_free = dp->vnext; 420 else 421 dp = (struct trxd *)malloc(sizeof *dp, M_MN, M_NOWAIT); 422 return (dp); 423} 424 425static void 426mn_free_desc(struct trxd *dp) 427{ 428 dp->vnext = mn_desc_free; 429 mn_desc_free = dp; 430} 431 432static u_int32_t 433mn_parse_ts(const char *s, int *nbit) 434{ 435 unsigned r; 436 int i, j; 437 char *p; 438 439 r = 0; 440 j = 0; 441 *nbit = 0; 442 while(*s) { 443 i = strtol(s, &p, 0); 444 if (i < 1 || i > 31) 445 return (0); 446 while (j && j < i) { 447 r |= 1 << j++; 448 (*nbit)++; 449 } 450 j = 0; 451 r |= 1 << i; 452 (*nbit)++; 453 if (*p == ',') { 454 s = p + 1; 455 continue; 456 } else if (*p == '-') { 457 j = i; 458 s = p + 1; 459 continue; 460 } else if (!*p) { 461 break; 462 } else { 463 return (0); 464 } 465 } 466 return (r); 467} 468 469#ifdef notyet 470static void 471mn_fmt_ts(char *p, u_int32_t ts) 472{ 473 char *s; 474 int j; 475 476 s = ""; 477 ts &= 0xfffffffe; 478 for (j = 1; j < 32; j++) { 479 if (!(ts & (1 << j))) 480 continue; 481 sprintf(p, "%s%d", s, j); 482 p += strlen(p); 483 s = ","; 484 if (!(ts & (1 << (j+1)))) 485 continue; 486 for (; j < 32; j++) 487 if (!(ts & (1 << (j+1)))) 488 break; 489 sprintf(p, "-%d", j); 490 p += strlen(p); 491 s = ","; 492 } 493} 494#endif /* notyet */ 495 496/* 497 * OUTPUT 498 */ 499 500static int 501ngmn_rcvdata(hook_p hook, struct mbuf *m, meta_p meta) 502{ 503 struct mbuf *m2; 504 struct trxd *dp, *dp2; 505 struct schan *sch; 506 struct softc *sc; 507 int chan, pitch, len; 508 509 sch = hook->private; 510 sc = sch->sc; 511 chan = sch->chan; 512 513 if (sch->state != UP) { 514 NG_FREE_DATA(m, meta); 515 return (0); 516 } 517 if (sch->tx_pending + m->m_pkthdr.len > sch->tx_limit * mn_maxlatency) { 518 NG_FREE_DATA(m, meta); 519 return (0); 520 } 521 NG_FREE_META(meta); 522 pitch = 0; 523 m2 = m; 524 dp2 = sc->ch[chan]->xl; 525 len = m->m_pkthdr.len; 526 while (len) { 527 dp = mn_alloc_desc(); 528 if (!dp) { 529 pitch++; 530 m_freem(m); 531 sc->ch[chan]->xl = dp2; 532 dp = dp2->vnext; 533 while (dp) { 534 dp2 = dp->vnext; 535 mn_free_desc(dp); 536 dp = dp2; 537 } 538 sc->ch[chan]->xl->vnext = 0; 539 break; 540 } 541 dp->data = vtophys(m2->m_data); 542 dp->flags = m2->m_len << 16; 543 dp->flags += 1; 544 len -= m2->m_len; 545 dp->next = vtophys(dp); 546 dp->vnext = 0; 547 sc->ch[chan]->xl->next = vtophys(dp); 548 sc->ch[chan]->xl->vnext = dp; 549 sc->ch[chan]->xl = dp; 550 if (!len) { 551 dp->m = m; 552 dp->flags |= 0xc0000000; 553 dp2->flags &= ~0x40000000; 554 } else { 555 dp->m = 0; 556 m2 = m2->m_next; 557 } 558 } 559 if (pitch) 560 printf("%s%d: Short on mem, pitched %d packets\n", 561 sc->name, chan, pitch); 562 else { 563#if 0 564 printf("%d = %d + %d (%p)\n", 565 sch->tx_pending + m->m_pkthdr.len, 566 sch->tx_pending , m->m_pkthdr.len, m); 567#endif 568 sch->tx_pending += m->m_pkthdr.len; 569 } 570 return (0); 571} 572 573/* 574 * OPEN 575 */ 576static int 577ngmn_connect(hook_p hook) 578{ 579 int i, nts, chan; 580 struct trxd *dp, *dp2; 581 struct mbuf *m; 582 struct softc *sc; 583 struct schan *sch; 584 u_int32_t u; 585 586 sch = hook->private; 587 chan = sch->chan; 588 sc = sch->sc; 589 590 if (sch->state == UP) 591 return (0); 592 sch->state = UP; 593 594 /* Count and configure the timeslots for this channel */ 595 for (nts = i = 0; i < 32; i++) 596 if (sch->ts & (1 << i)) { 597 sc->m32_mem.ts[i] = 0x00ff00ff | 598 (chan << 24) | (chan << 8); 599 nts++; 600 } 601 602 /* Init the receiver & xmitter to HDLC */ 603 sc->m32_mem.cs[chan].flags = 0x80e90006; 604 /* Allocate two buffers per timeslot */ 605 sc->m32_mem.cs[chan].itbs = nts * 2; 606 607 /* Setup a transmit chain with one descriptor */ 608 /* XXX: we actually send a 1 byte packet */ 609 dp = mn_alloc_desc(); 610 MGETHDR(m, M_WAIT, MT_DATA); 611 m->m_pkthdr.len = 0; 612 dp->m = m; 613 dp->flags = 0xc0000000 + (1 << 16); 614 dp->next = vtophys(dp); 615 dp->vnext = 0; 616 dp->data = vtophys(sc->name); 617 sc->m32_mem.cs[chan].tdesc = vtophys(dp); 618 sc->ch[chan]->x1 = dp; 619 sc->ch[chan]->xl = dp; 620 621 /* Setup a receive chain with 5 + NTS descriptors */ 622 623 dp = mn_alloc_desc(); 624 MGETHDR(m, M_WAIT, MT_DATA); 625 MCLGET(m, M_WAIT); 626 dp->m = m; 627 dp->data = vtophys(m->m_data); 628 dp->flags = 0x40000000; 629 dp->flags += 1600 << 16; 630 dp->next = vtophys(dp); 631 dp->vnext = 0; 632 sc->ch[chan]->rl = dp; 633 634 for (i = 0; i < (nts + 10); i++) { 635 dp2 = dp; 636 dp = mn_alloc_desc(); 637 MGETHDR(m, M_WAIT, MT_DATA); 638 MCLGET(m, M_WAIT); 639 dp->m = m; 640 dp->data = vtophys(m->m_data); 641 dp->flags = 0x00000000; 642 dp->flags += 1600 << 16; 643 dp->next = vtophys(dp2); 644 dp->vnext = dp2; 645 } 646 sc->m32_mem.cs[chan].rdesc = vtophys(dp); 647 sc->ch[chan]->r1 = dp; 648 649 /* Initialize this channel */ 650 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 651 sc->m32x->cmd = 0x1; 652 DELAY(1000); 653 u = sc->m32x->stat; 654 if (!(u & 1)) 655 printf("%s: init chan %d stat %08x\n", sc->name, chan, u); 656 sc->m32x->stat = 1; 657 658 return (0); 659} 660 661/* 662 * CLOSE 663 */ 664static int 665ngmn_disconnect(hook_p hook) 666{ 667 int chan, i; 668 struct softc *sc; 669 struct schan *sch; 670 struct trxd *dp, *dp2; 671 u_int32_t u; 672 673 sch = hook->private; 674 chan = sch->chan; 675 sc = sch->sc; 676 677 if (sch->state == DOWN) 678 return (0); 679 sch->state = DOWN; 680 681 /* Set receiver & transmitter off */ 682 sc->m32_mem.cs[chan].flags = 0x80920006; 683 sc->m32_mem.cs[chan].itbs = 0; 684 685 /* free the timeslots */ 686 for (i = 0; i < 32; i++) 687 if (sc->ch[chan]->ts & (1 << i)) 688 sc->m32_mem.ts[i] = 0x20002000; 689 690 /* Initialize this channel */ 691 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 692 sc->m32x->cmd = 0x1; 693 DELAY(30); 694 u = sc->m32x->stat; 695 if (!(u & 1)) 696 printf("%s: zap chan %d stat %08x\n", sc->name, chan, u); 697 sc->m32x->stat = 1; 698 699 /* Free all receive descriptors and mbufs */ 700 for (dp = sc->ch[chan]->r1; dp ; dp = dp2) { 701 if (dp->m) 702 m_freem(dp->m); 703 sc->ch[chan]->r1 = dp2 = dp->vnext; 704 mn_free_desc(dp); 705 } 706 707 /* Free all transmit descriptors and mbufs */ 708 for (dp = sc->ch[chan]->x1; dp ; dp = dp2) { 709 if (dp->m) 710 m_freem(dp->m); 711 sc->ch[chan]->x1 = dp2 = dp->vnext; 712 mn_free_desc(dp); 713 } 714 return(0); 715} 716 717/* 718 * Create a new channel. 719 */ 720static void 721mn_create_channel(struct softc *sc, int chan) 722{ 723 struct schan *sch; 724 725 sch = sc->ch[chan] = (struct schan *)malloc(sizeof *sc->ch[chan], 726 M_MN, M_WAITOK); 727 bzero(sch, sizeof *sch); 728 sch->sc = sc; 729 sch->state = DOWN; 730 sch->chan = chan; 731 sprintf(sch->name, "%s%d", sc->name, chan); 732 return; 733} 734 735#ifdef notyet 736/* 737 * Dump Munich32x state 738 */ 739static void 740m32_dump(struct softc *sc) 741{ 742 u_int32_t *tp4; 743 int i, j; 744 745 printf("mn%d: MUNICH32X dump\n", sc->unit); 746 tp4 = (u_int32_t *)sc->m0v; 747 for(j = 0; j < 64; j += 8) { 748 printf("%02x", j * sizeof *tp4); 749 for(i = 0; i < 8; i++) 750 printf(" %08x", tp4[i+j]); 751 printf("\n"); 752 } 753 for(j = 0; j < M32_CHAN; j++) { 754 if (!sc->ch[j]) 755 continue; 756 printf("CH%d: state %d ts %08x", 757 j, sc->ch[j]->state, sc->ch[j]->ts); 758 printf(" %08x %08x %08x %08x %08x %08x\n", 759 sc->m32_mem.cs[j].flags, 760 sc->m32_mem.cs[j].rdesc, 761 sc->m32_mem.cs[j].tdesc, 762 sc->m32_mem.cs[j].itbs, 763 sc->m32_mem.crxd[j], 764 sc->m32_mem.ctxd[j] ); 765 } 766} 767 768/* 769 * Dump Falch54 state 770 */ 771static void 772f54_dump(struct softc *sc) 773{ 774 u_int8_t *tp1; 775 int i, j; 776 777 printf("%s: FALC54 dump\n", sc->name); 778 tp1 = (u_int8_t *)sc->m1v; 779 for(j = 0; j < 128; j += 16) { 780 printf("%s: %02x |", sc->name, j * sizeof *tp1); 781 for(i = 0; i < 16; i++) 782 printf(" %02x", tp1[i+j]); 783 printf("\n"); 784 } 785} 786#endif /* notyet */ 787 788/* 789 * Init Munich32x 790 */ 791static void 792m32_init(struct softc *sc) 793{ 794 795 sc->m32x->conf = 0x00000000; 796 sc->m32x->mode1 = 0x81048000 + 1600; /* XXX: temp */ 797#if 1 798 sc->m32x->mode2 = 0x00000081; 799 sc->m32x->txpoll = 0xffffffff; 800#else 801 sc->m32x->mode2 = 0x00000101; 802#endif 803 sc->m32x->lconf = 0x6060009B; 804 sc->m32x->imask = 0x00000000; 805} 806 807/* 808 * Init the Falc54 809 */ 810static void 811f54_init(struct softc *sc) 812{ 813 sc->f54w->ipc = 0x07; 814 815 sc->f54w->xpm0 = 0xbd; 816 sc->f54w->xpm1 = 0x03; 817 sc->f54w->xpm2 = 0x00; 818 819 sc->f54w->imr0 = 0x18; /* RMB, CASC */ 820 sc->f54w->imr1 = 0x08; /* XMB */ 821 sc->f54w->imr2 = 0x00; 822 sc->f54w->imr3 = 0x38; /* LMFA16, AIS16, RA16 */ 823 sc->f54w->imr4 = 0x00; 824 825 sc->f54w->fmr0 = 0xf0; /* X: HDB3, R: HDB3 */ 826 sc->f54w->fmr1 = 0x0e; /* Send CRC4, 2Mbit, ECM */ 827 sc->f54w->fmr2 = 0x03; /* Auto Rem-Alarm, Auto resync */ 828 829 sc->f54w->lim1 = 0xb0; /* XCLK=8kHz, .62V threshold */ 830 sc->f54w->pcd = 0x0a; 831 sc->f54w->pcr = 0x15; 832 sc->f54w->xsw = 0x9f; /* fmr4 */ 833 sc->f54w->xsp = 0x1c; /* fmr5 */ 834 sc->f54w->xc0 = 0x07; 835 sc->f54w->xc1 = 0x3d; 836 sc->f54w->rc0 = 0x05; 837 sc->f54w->rc1 = 0x00; 838 sc->f54w->cmdr = 0x51; 839} 840 841static int 842mn_reset(struct softc *sc) 843{ 844 u_int32_t u; 845 int i; 846 847 sc->m32x->ccba = vtophys(&sc->m32_mem.csa); 848 sc->m32_mem.csa = vtophys(&sc->m32_mem.ccb); 849 850 bzero(sc->tiqb, sizeof sc->tiqb); 851 sc->m32x->tiqba = vtophys(&sc->tiqb); 852 sc->m32x->tiql = NIQB / 16 - 1; 853 854 bzero(sc->riqb, sizeof sc->riqb); 855 sc->m32x->riqba = vtophys(&sc->riqb); 856 sc->m32x->riql = NIQB / 16 - 1; 857 858 bzero(sc->ltiqb, sizeof sc->ltiqb); 859 sc->m32x->ltiqba = vtophys(&sc->ltiqb); 860 sc->m32x->ltiql = NIQB / 16 - 1; 861 862 bzero(sc->lriqb, sizeof sc->lriqb); 863 sc->m32x->lriqba = vtophys(&sc->lriqb); 864 sc->m32x->lriql = NIQB / 16 - 1; 865 866 bzero(sc->piqb, sizeof sc->piqb); 867 sc->m32x->piqba = vtophys(&sc->piqb); 868 sc->m32x->piql = NIQB / 16 - 1; 869 870 m32_init(sc); 871 f54_init(sc); 872 873 u = sc->m32x->stat; 874 sc->m32x->stat = u; 875 sc->m32_mem.ccb = 0x4; 876 sc->m32x->cmd = 0x1; 877 DELAY(1000); 878 u = sc->m32x->stat; 879 sc->m32x->stat = u; 880 881 /* set all timeslots to known state */ 882 for (i = 0; i < 32; i++) 883 sc->m32_mem.ts[i] = 0x20002000; 884 885 if (!(u & 1)) { 886 printf( 887"mn%d: WARNING: Controller failed the PCI bus-master test.\n" 888"mn%d: WARNING: Use a PCI slot which can support bus-master cards.\n", 889 sc->unit, sc->unit); 890 return (0); 891 } 892 return (1); 893} 894 895/* 896 * FALC54 interrupt handling 897 */ 898static void 899f54_intr(struct softc *sc) 900{ 901 unsigned g, u, s; 902 903 g = sc->f54r->gis; 904 u = sc->f54r->isr0 << 24; 905 u |= sc->f54r->isr1 << 16; 906 u |= sc->f54r->isr2 << 8; 907 u |= sc->f54r->isr3; 908 sc->falc_irq = u; 909 /* don't chat about the 1 sec heart beat */ 910 if (u & ~0x40) { 911#if 0 912 printf("%s*: FALC54 IRQ GIS:%02x %b\n", sc->name, g, u, "\20" 913 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 914 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 915 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 916 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 917#endif 918 s = sc->f54r->frs0 << 24; 919 s |= sc->f54r->frs1 << 16; 920 s |= sc->f54r->rsw << 8; 921 s |= sc->f54r->rsp; 922 sc->falc_state = s; 923 924 s &= ~0x01844038; /* undefined or static bits */ 925 s &= ~0x00009fc7; /* bits we don't care about */ 926 s &= ~0x00780000; /* XXX: TS16 related */ 927 s &= ~0x06000000; /* XXX: Multiframe related */ 928#if 0 929 printf("%s*: FALC54 Status %b\n", sc->name, s, "\20" 930 "\40LOS\37AIS\36LFA\35RRA\34AUXP\33NMF\32LMFA\31frs0.0" 931 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS\24TS16LFA\23frs1.2\22XLS\21XLO" 932 "\20RS1\17rsw.6\16RRA\15RY0\14RY1\13RY2\12RY3\11RY4" 933 "\10SI1\7SI2\6rsp.5\5rsp.4\4rsp.3\3RSIF\2RS13\1RS15"); 934#endif 935 if (s != sc->framer_state) { 936#if 0 937 for (i = 0; i < M32_CHAN; i++) { 938 if (!sc->ch[i]) 939 continue; 940 sp = &sc->ch[i]->ifsppp; 941 if (!(sp->pp_if.if_flags & IFF_UP)) 942 continue; 943 if (s) 944 timeout((timeout_t *)sp->pp_down, sp, 1 * hz); 945 else 946 timeout((timeout_t *)sp->pp_up, sp, 1 * hz); 947 } 948#endif 949 sc->framer_state = s; 950 } 951 } 952 /* Once per second check error counters */ 953 /* XXX: not clear if this is actually ok */ 954 if (!(u & 0x40)) 955 return; 956 sc->cnt_fec += sc->f54r->fec; 957 sc->cnt_cvc += sc->f54r->cvc; 958 sc->cnt_cec1 += sc->f54r->cec1; 959 sc->cnt_ebc += sc->f54r->ebc; 960 sc->cnt_cec2 += sc->f54r->cec2; 961 sc->cnt_cec3 += sc->f54r->cec3; 962 sc->cnt_rbc += sc->f54r->rbc; 963} 964 965/* 966 * Transmit interrupt for one channel 967 */ 968static void 969mn_tx_intr(struct softc *sc, u_int32_t vector) 970{ 971 u_int32_t chan; 972 struct trxd *dp; 973 struct mbuf *m; 974 975 chan = vector & 0x1f; 976 if (!sc->ch[chan]) 977 return; 978 if (sc->ch[chan]->state != UP) { 979 printf("%s: tx_intr when not UP\n", sc->name); 980 return; 981 } 982 for (;;) { 983 dp = sc->ch[chan]->x1; 984 if (vtophys(dp) == sc->m32_mem.ctxd[chan]) 985 return; 986 m = dp->m; 987 if (m) { 988#if 0 989 printf("%d = %d - %d (%p)\n", 990 sc->ch[chan]->tx_pending - m->m_pkthdr.len, 991 sc->ch[chan]->tx_pending , m->m_pkthdr.len, m); 992#endif 993 sc->ch[chan]->tx_pending -= m->m_pkthdr.len; 994 m_freem(m); 995 } 996 sc->ch[chan]->last_xmit = time_second; 997 sc->ch[chan]->x1 = dp->vnext; 998 mn_free_desc(dp); 999 } 1000} 1001 1002/* 1003 * Receive interrupt for one channel 1004 */ 1005static void 1006mn_rx_intr(struct softc *sc, u_int32_t vector) 1007{ 1008 u_int32_t chan, err; 1009 struct trxd *dp; 1010 struct mbuf *m; 1011 struct schan *sch; 1012 1013 chan = vector & 0x1f; 1014 if (!sc->ch[chan]) 1015 return; 1016 sch = sc->ch[chan]; 1017 if (sch->state != UP) { 1018 printf("%s: rx_intr when not UP\n", sc->name); 1019 return; 1020 } 1021 vector &= ~0x1f; 1022 if (vector == 0x30000b00) 1023 sch->rx_error++; 1024 for (;;) { 1025 dp = sch->r1; 1026 if (vtophys(dp) == sc->m32_mem.crxd[chan]) 1027 return; 1028 m = dp->m; 1029 dp->m = 0; 1030 m->m_pkthdr.len = m->m_len = (dp->status >> 16) & 0x1fff; 1031 err = (dp->status >> 8) & 0xff; 1032 if (!err) { 1033 ng_queue_data(sch->hook, m, NULL); 1034 sch->last_recv = time_second; 1035 m = 0; 1036 /* we could be down by now... */ 1037 if (sch->state != UP) 1038 return; 1039 } else if (err & 0x40) { 1040 sch->short_error++; 1041 } else if (err & 0x10) { 1042 sch->crc_error++; 1043 } else if (err & 0x08) { 1044 sch->dribble_error++; 1045 } else if (err & 0x04) { 1046 sch->long_error++; 1047 } else if (err & 0x02) { 1048 sch->abort_error++; 1049 } else if (err & 0x01) { 1050 sch->overflow_error++; 1051 } 1052 if (err) { 1053 sch->last_rxerr = time_second; 1054 sch->prev_error = sch->last_error; 1055 sch->last_error = err; 1056 } 1057 1058 sc->ch[chan]->r1 = dp->vnext; 1059 1060 /* Replenish desc + mbuf supplies */ 1061 if (!m) { 1062 MGETHDR(m, M_DONTWAIT, MT_DATA); 1063 if (m == NULL) { 1064 mn_free_desc(dp); 1065 return; 1066 } 1067 MCLGET(m, M_DONTWAIT); 1068 if((m->m_flags & M_EXT) == 0) { 1069 mn_free_desc(dp); 1070 return; 1071 } 1072 } 1073 dp->m = m; 1074 dp->data = vtophys(m->m_data); 1075 dp->flags = 0x40000000; 1076 dp->flags += 1600 << 16; 1077 dp->next = vtophys(dp); 1078 dp->vnext = 0; 1079 sc->ch[chan]->rl->next = vtophys(dp); 1080 sc->ch[chan]->rl->vnext = dp; 1081 sc->ch[chan]->rl->flags &= ~0x40000000; 1082 sc->ch[chan]->rl = dp; 1083 } 1084} 1085 1086 1087/* 1088 * Interupt handler 1089 */ 1090 1091static void 1092mn_intr(void *xsc) 1093{ 1094 struct softc *sc; 1095 u_int32_t stat, lstat, u; 1096 int i, j; 1097 1098 sc = xsc; 1099 stat = sc->m32x->stat; 1100 lstat = sc->m32x->lstat; 1101#if 0 1102 if (!stat && !(lstat & 2)) 1103 return; 1104#endif 1105 1106 if (stat & ~0xc200) { 1107 printf("%s: I stat=%08x lstat=%08x\n", sc->name, stat, lstat); 1108 } 1109 1110 if ((stat & 0x200) || (lstat & 2)) 1111 f54_intr(sc); 1112 1113 for (j = i = 0; i < 64; i ++) { 1114 u = sc->riqb[i]; 1115 if (u) { 1116 sc->riqb[i] = 0; 1117 mn_rx_intr(sc, u); 1118 if ((u & ~0x1f) == 0x30000800 || (u & ~0x1f) == 0x30000b00) 1119 continue; 1120 u &= ~0x30000400; /* bits we don't care about */ 1121 if ((u & ~0x1f) == 0x00000900) 1122 continue; 1123 if (!(u & ~0x1f)) 1124 continue; 1125 if (!j) 1126 printf("%s*: RIQB:", sc->name); 1127 printf(" [%d]=%08x", i, u); 1128 j++; 1129 } 1130 } 1131 if (j) 1132 printf("\n"); 1133 1134 for (j = i = 0; i < 64; i ++) { 1135 u = sc->tiqb[i]; 1136 if (u) { 1137 sc->tiqb[i] = 0; 1138 mn_tx_intr(sc, u); 1139 if ((u & ~0x1f) == 0x20000800) 1140 continue; 1141 u &= ~0x20000000; /* bits we don't care about */ 1142 if (!u) 1143 continue; 1144 if (!j) 1145 printf("%s*: TIQB:", sc->name); 1146 printf(" [%d]=%08x", i, u); 1147 j++; 1148 } 1149 } 1150 if (j) 1151 printf("\n"); 1152 sc->m32x->stat = stat; 1153} 1154 1155static void 1156mn_timeout(void *xsc) 1157{ 1158 static int round = 0; 1159 struct softc *sc; 1160 1161 mn_intr(xsc); 1162 sc = xsc; 1163 timeout(mn_timeout, xsc, 10 * hz); 1164 round++; 1165 if (round == 2) { 1166 sc->m32_mem.ccb = 0x00008004; 1167 sc->m32x->cmd = 0x1; 1168 } else if (round > 2) { 1169 printf("%s: timeout\n", sc->name); 1170 } 1171} 1172 1173/* 1174 * PCI initialization stuff 1175 */ 1176 1177static struct pci_device mn_device = { 1178 "mn", 1179 mn_probe, 1180 mn_attach, 1181 &mn_count, 1182 NULL 1183}; 1184 1185#ifdef COMPAT_PCI_DRIVER 1186COMPAT_PCI_DRIVER(ti, mn_device); 1187#else 1188DATA_SET(pcidevice_set, mn_device); 1189#endif /* COMPAT_PCI_DRIVER */ 1190 1191static const char* 1192mn_probe (pcici_t tag, pcidi_t typea) 1193{ 1194 u_int id = pci_conf_read(tag, PCI_ID_REG); 1195 1196 if (sizeof (struct m32xreg) != 256) { 1197 printf("MN: sizeof(struct m32xreg) = %d, should have been 256\n", sizeof (struct m32xreg)); 1198 return (0); 1199 } 1200 if (sizeof (struct f54rreg) != 128) { 1201 printf("MN: sizeof(struct f54rreg) = %d, should have been 128\n", sizeof (struct f54rreg)); 1202 return (0); 1203 } 1204 if (sizeof (struct f54wreg) != 128) { 1205 printf("MN: sizeof(struct f54wreg) = %d, should have been 128\n", sizeof (struct f54wreg)); 1206 return (0); 1207 } 1208 1209 if (id == 0x2101110a) 1210 return "Munich32X E1/T1 HDLC Controller"; 1211 1212 return 0; 1213} 1214 1215static void 1216mn_attach (pcici_t tag, int unit) 1217{ 1218 struct softc *sc; 1219 u_int32_t u; 1220 u_int32_t pci_class; 1221 static int once; 1222 1223 if (!once) { 1224 if (ng_newtype(&mntypestruct)) 1225 printf("ng_newtype failed\n"); 1226 once++; 1227 } 1228 1229 sc = (struct softc *)malloc(sizeof *sc, M_MN, M_WAITOK); 1230 softc[unit] = sc; 1231 bzero(sc, sizeof *sc); 1232 1233 sc->tag = tag; 1234 sc->unit = unit; 1235 sprintf(sc->name, "mn%d", unit); 1236 1237 if (!pci_map_int(tag, mn_intr, sc, &net_imask)) { 1238 printf("mn%d: could not map interrupt\n", sc->unit); 1239 return; 1240 } 1241 pci_map_mem(tag, PCI_MAP_REG_START, &sc->m0v, &sc->m0p); 1242 pci_map_mem(tag, PCI_MAP_REG_START + 4, &sc->m1v, &sc->m1p); 1243 1244 u = pci_conf_read(tag, PCIR_COMMAND); 1245 pci_conf_write(tag, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); 1246 pci_conf_write(tag, PCIR_COMMAND, 0x02800046); 1247 1248 pci_class = pci_conf_read(tag, PCI_CLASS_REG); 1249 1250 sc->m32x = (struct m32xreg *) sc->m0v; 1251 sc->f54w = (struct f54wreg *) sc->m1v; 1252 sc->f54r = (struct f54rreg *) sc->m1v; 1253 1254 /* We must reset before poking at FALC54 registers */ 1255 u = mn_reset(sc); 1256 if (!u) 1257 return; 1258 1259 printf("mn%d: Munich32X", sc->unit); 1260 switch (pci_class & 0xff) { 1261 case 0x13: 1262 printf(" Rev 2.2"); 1263 break; 1264 default: 1265 printf(" Rev 0x%x\n", pci_class & 0xff); 1266 } 1267 printf(", Falc54"); 1268 switch (sc->f54r->vstr) { 1269 case 0: 1270 printf(" Rev < 1.3\n"); 1271 break; 1272 case 1: 1273 printf(" Rev 1.3\n"); 1274 break; 1275 case 2: 1276 printf(" Rev 1.4\n"); 1277 break; 1278 case 0x10: 1279 printf("-LH Rev 1.1\n"); 1280 break; 1281 case 0x13: 1282 printf("-LH Rev 1.3\n"); 1283 break; 1284 default: 1285 printf(" Rev 0x%x\n", sc->f54r->vstr); 1286 } 1287 1288 if (ng_make_node_common(&mntypestruct, &sc->node) != 0) { 1289 printf("ng_make_node_common failed\n"); 1290 return; 1291 } 1292 sc->node->private = sc; 1293 sprintf(sc->nodename, "%s%d", NG_MN_NODE_TYPE, sc->unit); 1294 if (ng_name_node(sc->node, sc->nodename)) { 1295 ng_rmnode(sc->node); 1296 ng_unref(sc->node); 1297 return; 1298 } 1299 1300 return; 1301} 1302#endif /* _KERNEL */ 1303