if_mn.c revision 58695
1/* 2 * ---------------------------------------------------------------------------- 3 * "THE BEER-WARE LICENSE" (Revision 42): 4 * <phk@FreeBSD.org> wrote this file. As long as you retain this notice you 5 * can do whatever you want with this stuff. If we meet some day, and you think 6 * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp 7 * ---------------------------------------------------------------------------- 8 * 9 * $Id: if_mn.c,v 1.1 1999/02/01 13:06:40 phk Exp $ 10 * 11 * Driver for Siemens reference design card "Easy321-R1". 12 * 13 * This card contains a FALC54 E1/T1 framer and a MUNICH32X 32-channel HDLC 14 * controller. 15 * 16 * The driver supports E1 mode with up to 31 channels. We send CRC4 but don't 17 * check it coming in. 18 * 19 * The FALC54 and MUNICH32X have far too many registers and weird modes for 20 * comfort, so I have not bothered typing it all into a "fooreg.h" file, 21 * you will (badly!) need the documentation anyway if you want to mess with 22 * this gadget. 23 * 24 * $FreeBSD: head/sys/pci/if_mn.c 58695 2000-03-27 18:32:45Z imp $ 25 */ 26 27#ifndef COMPAT_OLDPCI 28#error "The mn device requires the old pci compatibility shims" 29#endif 30 31/* 32 * Stuff to describe the MUNIC32X and FALC54 chips. 33 */ 34 35#define M32_CHAN 32 /* We have 32 channels */ 36#define M32_TS 32 /* We have 32 timeslots */ 37 38#define NG_MN_NODE_TYPE "mn" 39 40#ifdef _KERNEL 41#define PPP_HEADER_LEN 4 /* XXX: should live in some header somewhere */ 42 43#include <sys/param.h> 44#include <sys/systm.h> 45#include <sys/conf.h> 46#include <sys/mbuf.h> 47#include <sys/kernel.h> 48#include <sys/sysctl.h> 49#include <sys/malloc.h> 50#include <sys/socket.h> 51#include <sys/sockio.h> 52#include <pci/pcireg.h> 53#include <pci/pcivar.h> 54#include <vm/vm.h> 55#include <vm/pmap.h> 56#include <machine/clock.h> 57 58#include <netgraph/ng_message.h> 59#include <netgraph/ng_sample.h> 60#include <netgraph/netgraph.h> 61 62static int mn_maxlatency = 1000; 63SYSCTL_INT(_debug, OID_AUTO, mn_maxlatency, CTLFLAG_RW, 64 &mn_maxlatency, 0, 65 "The number of milliseconds a packet is allowed to spend in the output queue. " 66 "If the output queue is longer than this number of milliseconds when the packet " 67 "arrives for output, the packet will be dropped." 68); 69 70#ifndef NMN 71/* Most machines don't support more than 4 busmaster PCI slots, if even that many */ 72#define NMN 4 73#endif 74 75/* From: PEB 20321 data sheet, p187, table 22 */ 76struct m32xreg { 77 u_int32_t conf, cmd, stat, imask; 78 u_int32_t fill10, piqba, piql, fill1c; 79 u_int32_t mode1, mode2, ccba, txpoll; 80 u_int32_t tiqba, tiql, riqba, riql; 81 u_int32_t lconf, lccba, fill48, ltran; 82 u_int32_t ltiqba, ltiql, lriqba, lriql; 83 u_int32_t lreg0, lreg1, lreg2, lreg3; 84 u_int32_t lreg4, lreg5, lre6, lstat; 85 u_int32_t gpdir, gpdata, gpod, fill8c; 86 u_int32_t ssccon, sscbr, ssctb, sscrb; 87 u_int32_t ssccse, sscim, fillab, fillac; 88 u_int32_t iomcon1, iomcon2, iomstat, fillbc; 89 u_int32_t iomcit0, iomcit1, iomcir0, iomcir1; 90 u_int32_t iomtmo, iomrmo, filld8, filldc; 91 u_int32_t mbcmd, mbdata1, mbdata2, mbdata3; 92 u_int32_t mbdata4, mbdata5, mbdata6, mbdata7; 93}; 94 95/* From: PEB 2254 data sheet, p80, table 10 */ 96struct f54wreg { 97 u_int16_t xfifo; 98 u_int8_t cmdr, mode, rah1, rah2, ral1, ral2; 99 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 100 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 101 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 102 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 103 u_int8_t test1, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr3; 104 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 105 u_int8_t lim2, fill39[7]; 106 u_int8_t fill40[8]; 107 u_int8_t fill48[8]; 108 u_int8_t fill50[8]; 109 u_int8_t fill58[8]; 110 u_int8_t dec, fill61, test2, fill63[5]; 111 u_int8_t fill68[8]; 112 u_int8_t xs[16]; 113}; 114 115/* From: PEB 2254 data sheet, p117, table 10 */ 116struct f54rreg { 117 u_int16_t rfifo; 118 u_int8_t fill2, mode, rah1, rah2, ral1, ral2; 119 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 120 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 121 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 122 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 123 u_int8_t test, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr13; 124 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 125 u_int8_t lim2, fill39[7]; 126 u_int8_t fill40[8]; 127 u_int8_t fill48[4], frs0, frs1, rsw, rsp; 128 u_int16_t fec, cvc, cec1, ebc; 129 u_int16_t cec2, cec3; 130 u_int8_t rsa4, rsa5, rsa6, rsa7; 131 u_int8_t rsa8, rsa6s, tsr0, tsr1, sis, rsis; 132 u_int16_t rbc; 133 u_int8_t isr0, isr1, isr2, isr3, fill6c, fill6d, gis, vstr; 134 u_int8_t rs[16]; 135}; 136 137/* Transmit & receive descriptors */ 138struct trxd { 139 u_int32_t flags; 140 vm_offset_t next; 141 vm_offset_t data; 142 u_int32_t status; /* only used for receive */ 143 struct mbuf *m; /* software use only */ 144 struct trxd *vnext; /* software use only */ 145}; 146 147/* Channel specification */ 148struct cspec { 149 u_int32_t flags; 150 vm_offset_t rdesc; 151 vm_offset_t tdesc; 152 u_int32_t itbs; 153}; 154 155struct m32_mem { 156 vm_offset_t csa; 157 u_int32_t ccb; 158 u_int32_t reserve1[2]; 159 u_int32_t ts[M32_TS]; 160 struct cspec cs[M32_CHAN]; 161 vm_offset_t crxd[M32_CHAN]; 162 vm_offset_t ctxd[M32_CHAN]; 163}; 164 165struct softc; 166struct sockaddr; 167struct rtentry; 168 169static const char* mn_probe (pcici_t tag, pcidi_t type); 170static void mn_attach (pcici_t tag, int unit); 171static u_long mn_count; 172static void mn_create_channel(struct softc *sc, int chan); 173static int mn_reset(struct softc *sc); 174static struct trxd * mn_alloc_desc(void); 175static void mn_free_desc(struct trxd *dp); 176static void mn_intr(void *xsc); 177static u_int32_t mn_parse_ts(const char *s, int *nbit); 178#ifdef notyet 179static void m32_dump(struct softc *sc); 180static void f54_dump(struct softc *sc); 181static void mn_fmt_ts(char *p, u_int32_t ts); 182#endif /* notyet */ 183 184static ng_constructor_t ngmn_constructor; 185static ng_rcvmsg_t ngmn_rcvmsg; 186static ng_shutdown_t ngmn_shutdown; 187static ng_newhook_t ngmn_newhook; 188static ng_connect_t ngmn_connect; 189static ng_rcvdata_t ngmn_rcvdata; 190static ng_disconnect_t ngmn_disconnect; 191 192static struct ng_type mntypestruct = { 193 NG_VERSION, 194 NG_MN_NODE_TYPE, 195 NULL, 196 ngmn_constructor, 197 ngmn_rcvmsg, 198 ngmn_shutdown, 199 ngmn_newhook, 200 NULL, 201 ngmn_connect, 202 ngmn_rcvdata, 203 ngmn_rcvdata, 204 ngmn_disconnect, 205 NULL 206}; 207 208static MALLOC_DEFINE(M_MN, "mn", "Mx driver related"); 209 210#define NIQB 64 211 212struct softc; 213 214struct schan { 215 enum {DOWN, UP} state; 216 struct softc *sc; 217 int chan; 218 u_int32_t ts; 219 char name[8]; 220 struct trxd *r1, *rl; 221 struct trxd *x1, *xl; 222 hook_p hook; 223 224 time_t last_recv; 225 time_t last_rxerr; 226 time_t last_xmit; 227 228 u_long rx_error; 229 230 u_long short_error; 231 u_long crc_error; 232 u_long dribble_error; 233 u_long long_error; 234 u_long abort_error; 235 u_long overflow_error; 236 237 int last_error; 238 int prev_error; 239 240 u_long tx_pending; 241 u_long tx_limit; 242}; 243 244static struct softc { 245 int unit; 246 pcici_t tag; 247 vm_offset_t m0v, m0p, m1v, m1p; 248 struct m32xreg *m32x; 249 struct f54wreg *f54w; 250 struct f54rreg *f54r; 251 struct m32_mem m32_mem; 252 u_int32_t tiqb[NIQB]; 253 u_int32_t riqb[NIQB]; 254 u_int32_t piqb[NIQB]; 255 u_int32_t ltiqb[NIQB]; 256 u_int32_t lriqb[NIQB]; 257 char name[8]; 258 u_int32_t falc_irq, falc_state, framer_state; 259 struct schan *ch[M32_CHAN]; 260 char nodename[NG_NODELEN + 1]; 261 node_p node; 262 263 u_long cnt_fec; 264 u_long cnt_cvc; 265 u_long cnt_cec1; 266 u_long cnt_ebc; 267 u_long cnt_cec2; 268 u_long cnt_cec3; 269 u_long cnt_rbc; 270} *softc[NMN]; 271 272static int 273ngmn_constructor(node_p *nodep) 274{ 275 276 return (EINVAL); 277} 278 279static int 280ngmn_shutdown(node_p nodep) 281{ 282 283 return (EINVAL); 284} 285 286static int 287ngmn_rcvmsg(node_p node, struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp) 288{ 289 struct softc *sc; 290 struct schan *sch; 291 char *arg; 292 int pos, i; 293 294 sc = node->private; 295 296 if (msg->header.typecookie != NGM_GENERIC_COOKIE || 297 msg->header.cmd != NGM_TEXT_STATUS) { 298 if (resp) 299 *resp = NULL; 300 FREE(msg, M_NETGRAPH); 301 return (EINVAL); 302 } 303 NG_MKRESPONSE(*resp, msg, sizeof(struct ng_mesg) + NG_TEXTRESPONSE, 304 M_NOWAIT); 305 if (*resp == NULL) { 306 FREE(msg, M_NETGRAPH); 307 return (ENOMEM); 308 } 309 arg = (char *)(*resp)->data; 310 pos = 0; 311 pos += sprintf(pos + arg,"Framer status %b;\n", sc->framer_state, "\20" 312 "\40LOS\37AIS\36LFA\35RRA" 313 "\34AUXP\33NMF\32LMFA\31frs0.0" 314 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 315 "\24TS16LFA\23frs1.2\22XLS\21XLO" 316 "\20RS1\17rsw.6\16RRA\15RY0" 317 "\14RY1\13RY2\12RY3\11RY4" 318 "\10SI1\7SI2\6rsp.5\5rsp.4" 319 "\4rsp.3\3RSIF\2RS13\1RS15"); 320 pos += sprintf(pos + arg," Framing errors: %lu", sc->cnt_fec); 321 pos += sprintf(pos + arg," Code Violations: %lu\n", sc->cnt_cvc); 322 323 pos += sprintf(pos + arg," Falc State %b;\n", sc->falc_state, "\20" 324 "\40LOS\37AIS\36LFA\35RRA" 325 "\34AUXP\33NMF\32LMFA\31frs0.0" 326 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 327 "\24TS16LFA\23frs1.2\22XLS\21XLO" 328 "\20RS1\17rsw.6\16RRA\15RY0" 329 "\14RY1\13RY2\12RY3\11RY4" 330 "\10SI1\7SI2\6rsp.5\5rsp.4" 331 "\4rsp.3\3RSIF\2RS13\1RS15"); 332 pos += sprintf(pos + arg, " Falc IRQ %b\n", sc->falc_irq, "\20" 333 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 334 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 335 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 336 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 337 for (i = 0; i < M32_CHAN; i++) { 338 if (!sc->ch[i]) 339 continue; 340 sch = sc->ch[i]; 341 342 pos += sprintf(arg + pos, " Chan %d <%s> ", 343 i, sch->hook->name); 344 345 pos += sprintf(arg + pos, " Last Rx: "); 346 if (sch->last_recv) 347 pos += sprintf(arg + pos, "%lu s", time_second - sch->last_recv); 348 else 349 pos += sprintf(arg + pos, "never"); 350 351 pos += sprintf(arg + pos, ", last RxErr: "); 352 if (sch->last_rxerr) 353 pos += sprintf(arg + pos, "%lu s", time_second - sch->last_rxerr); 354 else 355 pos += sprintf(arg + pos, "never"); 356 357 pos += sprintf(arg + pos, ", last Tx: "); 358 if (sch->last_xmit) 359 pos += sprintf(arg + pos, "%lu s\n", time_second - sch->last_xmit); 360 else 361 pos += sprintf(arg + pos, "never\n"); 362 363 pos += sprintf(arg + pos, " RX error(s) %lu", sch->rx_error); 364 pos += sprintf(arg + pos, " Short: %lu", sch->short_error); 365 pos += sprintf(arg + pos, " CRC: %lu", sch->crc_error); 366 pos += sprintf(arg + pos, " Mod8: %lu", sch->dribble_error); 367 pos += sprintf(arg + pos, " Long: %lu", sch->long_error); 368 pos += sprintf(arg + pos, " Abort: %lu", sch->abort_error); 369 pos += sprintf(arg + pos, " Overflow: %lu\n", sch->overflow_error); 370 371 pos += sprintf(arg + pos, " Last error: %b Prev error: %b\n", 372 sch->last_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN", 373 sch->prev_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN"); 374 pos += sprintf(arg + pos, " Xmit bytes pending %ld\n", 375 sch->tx_pending); 376 } 377 (*resp)->header.arglen = pos + 1; 378 FREE(msg, M_NETGRAPH); 379 return (0); 380} 381 382static int 383ngmn_newhook(node_p node, hook_p hook, const char *name) 384{ 385 u_int32_t ts, chan; 386 struct softc *sc; 387 int nbit; 388 389 sc = node->private; 390 391 if (name[0] != 't' || name[1] != 's') 392 return (EINVAL); 393 394 ts = mn_parse_ts(name + 2, &nbit); 395 if (ts == 0) 396 return (EINVAL); 397 chan = ffs(ts) - 1; 398 if (sc->ch[chan]) 399 return (EBUSY); 400 mn_create_channel(sc, chan); 401 sc->ch[chan]->ts = ts; 402 sc->ch[chan]->hook = hook; 403 sc->ch[chan]->tx_limit = nbit * 8; 404 hook->private = sc->ch[chan]; 405 return(0); 406} 407 408 409static struct trxd *mn_desc_free; 410 411static struct trxd * 412mn_alloc_desc(void) 413{ 414 struct trxd *dp; 415 416 dp = mn_desc_free; 417 if (dp) 418 mn_desc_free = dp->vnext; 419 else 420 dp = (struct trxd *)malloc(sizeof *dp, M_MN, M_NOWAIT); 421 return (dp); 422} 423 424static void 425mn_free_desc(struct trxd *dp) 426{ 427 dp->vnext = mn_desc_free; 428 mn_desc_free = dp; 429} 430 431static u_int32_t 432mn_parse_ts(const char *s, int *nbit) 433{ 434 unsigned r; 435 int i, j; 436 char *p; 437 438 r = 0; 439 j = 0; 440 *nbit = 0; 441 while(*s) { 442 i = strtol(s, &p, 0); 443 if (i < 1 || i > 31) 444 return (0); 445 while (j && j < i) { 446 r |= 1 << j++; 447 (*nbit)++; 448 } 449 j = 0; 450 r |= 1 << i; 451 (*nbit)++; 452 if (*p == ',') { 453 s = p + 1; 454 continue; 455 } else if (*p == '-') { 456 j = i; 457 s = p + 1; 458 continue; 459 } else if (!*p) { 460 break; 461 } else { 462 return (0); 463 } 464 } 465 return (r); 466} 467 468#ifdef notyet 469static void 470mn_fmt_ts(char *p, u_int32_t ts) 471{ 472 char *s; 473 int j; 474 475 s = ""; 476 ts &= 0xfffffffe; 477 for (j = 1; j < 32; j++) { 478 if (!(ts & (1 << j))) 479 continue; 480 sprintf(p, "%s%d", s, j); 481 p += strlen(p); 482 s = ","; 483 if (!(ts & (1 << (j+1)))) 484 continue; 485 for (; j < 32; j++) 486 if (!(ts & (1 << (j+1)))) 487 break; 488 sprintf(p, "-%d", j); 489 p += strlen(p); 490 s = ","; 491 } 492} 493#endif /* notyet */ 494 495/* 496 * OUTPUT 497 */ 498 499static int 500ngmn_rcvdata(hook_p hook, struct mbuf *m, meta_p meta) 501{ 502 struct mbuf *m2; 503 struct trxd *dp, *dp2; 504 struct schan *sch; 505 struct softc *sc; 506 int chan, pitch, len; 507 508 sch = hook->private; 509 sc = sch->sc; 510 chan = sch->chan; 511 512 if (sch->state != UP) { 513 NG_FREE_DATA(m, meta); 514 printf("D1\n"); 515 return (0); 516 } 517 if (sch->tx_pending + m->m_pkthdr.len > sch->tx_limit * mn_maxlatency) { 518 NG_FREE_DATA(m, meta); 519 printf("D2\n"); 520 return (0); 521 } 522 NG_FREE_META(meta); 523 pitch = 0; 524 m2 = m; 525 dp2 = sc->ch[chan]->xl; 526 len = m->m_pkthdr.len; 527 while (len) { 528 dp = mn_alloc_desc(); 529 if (!dp) { 530 pitch++; 531 m_freem(m); 532 sc->ch[chan]->xl = dp2; 533 dp = dp2->vnext; 534 while (dp) { 535 dp2 = dp->vnext; 536 mn_free_desc(dp); 537 dp = dp2; 538 } 539 sc->ch[chan]->xl->vnext = 0; 540 break; 541 } 542 dp->data = vtophys(m2->m_data); 543 dp->flags = m2->m_len << 16; 544 dp->flags += 1; 545 len -= m2->m_len; 546 dp->next = vtophys(dp); 547 dp->vnext = 0; 548 sc->ch[chan]->xl->next = vtophys(dp); 549 sc->ch[chan]->xl->vnext = dp; 550 sc->ch[chan]->xl = dp; 551 if (!len) { 552 dp->m = m; 553 dp->flags |= 0xc0000000; 554 dp2->flags &= ~0x40000000; 555 } else { 556 dp->m = 0; 557 m2 = m2->m_next; 558 } 559 } 560 if (pitch) 561 printf("%s%d: Short on mem, pitched %d packets\n", 562 sc->name, chan, pitch); 563 else { 564#if 0 565 printf("%d = %d + %d (%p)\n", 566 sch->tx_pending + m->m_pkthdr.len, 567 sch->tx_pending , m->m_pkthdr.len, m); 568#endif 569 sch->tx_pending += m->m_pkthdr.len; 570 } 571 return (0); 572} 573 574/* 575 * OPEN 576 */ 577static int 578ngmn_connect(hook_p hook) 579{ 580 int i, nts, chan; 581 struct trxd *dp, *dp2; 582 struct mbuf *m; 583 struct softc *sc; 584 struct schan *sch; 585 u_int32_t u; 586 587 sch = hook->private; 588 chan = sch->chan; 589 sc = sch->sc; 590 591 if (sch->state == UP) 592 return (0); 593 sch->state = UP; 594 595 /* Count and configure the timeslots for this channel */ 596 for (nts = i = 0; i < 32; i++) 597 if (sch->ts & (1 << i)) { 598 sc->m32_mem.ts[i] = 0x00ff00ff | 599 (chan << 24) | (chan << 8); 600 nts++; 601 } 602 603 /* Init the receiver & xmitter to HDLC */ 604 sc->m32_mem.cs[chan].flags = 0x80e90006; 605 /* Allocate two buffers per timeslot */ 606 sc->m32_mem.cs[chan].itbs = nts * 2; 607 608 /* Setup a transmit chain with one descriptor */ 609 /* XXX: we actually send a 1 byte packet */ 610 dp = mn_alloc_desc(); 611 MGETHDR(m, M_WAIT, MT_DATA); 612 m->m_pkthdr.len = 0; 613 dp->m = m; 614 dp->flags = 0xc0000000 + (1 << 16); 615 dp->next = vtophys(dp); 616 dp->vnext = 0; 617 dp->data = vtophys(sc->name); 618 sc->m32_mem.cs[chan].tdesc = vtophys(dp); 619 sc->ch[chan]->x1 = dp; 620 sc->ch[chan]->xl = dp; 621 622 /* Setup a receive chain with 5 + NTS descriptors */ 623 624 dp = mn_alloc_desc(); 625 MGETHDR(m, M_WAIT, MT_DATA); 626 MCLGET(m, M_WAIT); 627 dp->m = m; 628 dp->data = vtophys(m->m_data); 629 dp->flags = 0x40000000; 630 dp->flags += 1600 << 16; 631 dp->next = vtophys(dp); 632 dp->vnext = 0; 633 sc->ch[chan]->rl = dp; 634 635 for (i = 0; i < (nts + 10); i++) { 636 dp2 = dp; 637 dp = mn_alloc_desc(); 638 MGETHDR(m, M_WAIT, MT_DATA); 639 MCLGET(m, M_WAIT); 640 dp->m = m; 641 dp->data = vtophys(m->m_data); 642 dp->flags = 0x00000000; 643 dp->flags += 1600 << 16; 644 dp->next = vtophys(dp2); 645 dp->vnext = dp2; 646 } 647 sc->m32_mem.cs[chan].rdesc = vtophys(dp); 648 sc->ch[chan]->r1 = dp; 649 650 /* Initialize this channel */ 651 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 652 sc->m32x->cmd = 0x1; 653 DELAY(1000); 654 u = sc->m32x->stat; 655 if (!(u & 1)) 656 printf("%s: init chan %d stat %08x\n", sc->name, chan, u); 657 sc->m32x->stat = 1; 658 659 return (0); 660} 661 662/* 663 * CLOSE 664 */ 665static int 666ngmn_disconnect(hook_p hook) 667{ 668 int chan, i; 669 struct softc *sc; 670 struct schan *sch; 671 struct trxd *dp, *dp2; 672 u_int32_t u; 673 674 sch = hook->private; 675 chan = sch->chan; 676 sc = sch->sc; 677 678 if (sch->state == DOWN) 679 return (0); 680 sch->state = DOWN; 681 682 /* Set receiver & transmitter off */ 683 sc->m32_mem.cs[chan].flags = 0x80920006; 684 sc->m32_mem.cs[chan].itbs = 0; 685 686 /* free the timeslots */ 687 for (i = 0; i < 32; i++) 688 if (sc->ch[chan]->ts & (1 << i)) 689 sc->m32_mem.ts[i] = 0x20002000; 690 691 /* Initialize this channel */ 692 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 693 sc->m32x->cmd = 0x1; 694 DELAY(30); 695 u = sc->m32x->stat; 696 if (!(u & 1)) 697 printf("%s: zap chan %d stat %08x\n", sc->name, chan, u); 698 sc->m32x->stat = 1; 699 700 /* Free all receive descriptors and mbufs */ 701 for (dp = sc->ch[chan]->r1; dp ; dp = dp2) { 702 if (dp->m) 703 m_freem(dp->m); 704 sc->ch[chan]->r1 = dp2 = dp->vnext; 705 mn_free_desc(dp); 706 } 707 708 /* Free all transmit descriptors and mbufs */ 709 for (dp = sc->ch[chan]->x1; dp ; dp = dp2) { 710 if (dp->m) 711 m_freem(dp->m); 712 sc->ch[chan]->x1 = dp2 = dp->vnext; 713 mn_free_desc(dp); 714 } 715 return(0); 716} 717 718/* 719 * Create a new channel. 720 */ 721static void 722mn_create_channel(struct softc *sc, int chan) 723{ 724 struct schan *sch; 725 726 sch = sc->ch[chan] = (struct schan *)malloc(sizeof *sc->ch[chan], 727 M_MN, M_WAITOK); 728 bzero(sch, sizeof *sch); 729 sch->sc = sc; 730 sch->state = DOWN; 731 sch->chan = chan; 732 sprintf(sch->name, "%s%d", sc->name, chan); 733 return; 734} 735 736#ifdef notyet 737/* 738 * Dump Munich32x state 739 */ 740static void 741m32_dump(struct softc *sc) 742{ 743 u_int32_t *tp4; 744 int i, j; 745 746 printf("mn%d: MUNICH32X dump\n", sc->unit); 747 tp4 = (u_int32_t *)sc->m0v; 748 for(j = 0; j < 64; j += 8) { 749 printf("%02x", j * sizeof *tp4); 750 for(i = 0; i < 8; i++) 751 printf(" %08x", tp4[i+j]); 752 printf("\n"); 753 } 754 for(j = 0; j < M32_CHAN; j++) { 755 if (!sc->ch[j]) 756 continue; 757 printf("CH%d: state %d ts %08x", 758 j, sc->ch[j]->state, sc->ch[j]->ts); 759 printf(" %08x %08x %08x %08x %08x %08x\n", 760 sc->m32_mem.cs[j].flags, 761 sc->m32_mem.cs[j].rdesc, 762 sc->m32_mem.cs[j].tdesc, 763 sc->m32_mem.cs[j].itbs, 764 sc->m32_mem.crxd[j], 765 sc->m32_mem.ctxd[j] ); 766 } 767} 768 769/* 770 * Dump Falch54 state 771 */ 772static void 773f54_dump(struct softc *sc) 774{ 775 u_int8_t *tp1; 776 int i, j; 777 778 printf("%s: FALC54 dump\n", sc->name); 779 tp1 = (u_int8_t *)sc->m1v; 780 for(j = 0; j < 128; j += 16) { 781 printf("%s: %02x |", sc->name, j * sizeof *tp1); 782 for(i = 0; i < 16; i++) 783 printf(" %02x", tp1[i+j]); 784 printf("\n"); 785 } 786} 787#endif /* notyet */ 788 789/* 790 * Init Munich32x 791 */ 792static void 793m32_init(struct softc *sc) 794{ 795 796 sc->m32x->conf = 0x00000000; 797 sc->m32x->mode1 = 0x81048000 + 1600; /* XXX: temp */ 798#if 1 799 sc->m32x->mode2 = 0x00000081; 800 sc->m32x->txpoll = 0xffffffff; 801#else 802 sc->m32x->mode2 = 0x00000101; 803#endif 804 sc->m32x->lconf = 0x6060009B; 805 sc->m32x->imask = 0x00000000; 806} 807 808/* 809 * Init the Falc54 810 */ 811static void 812f54_init(struct softc *sc) 813{ 814 sc->f54w->ipc = 0x07; 815 816 sc->f54w->xpm0 = 0xbd; 817 sc->f54w->xpm1 = 0x03; 818 sc->f54w->xpm2 = 0x00; 819 820 sc->f54w->imr0 = 0x18; /* RMB, CASC */ 821 sc->f54w->imr1 = 0x08; /* XMB */ 822 sc->f54w->imr2 = 0x00; 823 sc->f54w->imr3 = 0x38; /* LMFA16, AIS16, RA16 */ 824 sc->f54w->imr4 = 0x00; 825 826 sc->f54w->fmr0 = 0xf0; /* X: HDB3, R: HDB3 */ 827 sc->f54w->fmr1 = 0x0e; /* Send CRC4, 2Mbit, ECM */ 828 sc->f54w->fmr2 = 0x03; /* Auto Rem-Alarm, Auto resync */ 829 830 sc->f54w->lim1 = 0xb0; /* XCLK=8kHz, .62V threshold */ 831 sc->f54w->pcd = 0x0a; 832 sc->f54w->pcr = 0x15; 833 sc->f54w->xsw = 0x9f; /* fmr4 */ 834 sc->f54w->xsp = 0x1c; /* fmr5 */ 835 sc->f54w->xc0 = 0x07; 836 sc->f54w->xc1 = 0x3d; 837 sc->f54w->rc0 = 0x05; 838 sc->f54w->rc1 = 0x00; 839 sc->f54w->cmdr = 0x51; 840} 841 842static int 843mn_reset(struct softc *sc) 844{ 845 u_int32_t u; 846 int i; 847 848 sc->m32x->ccba = vtophys(&sc->m32_mem.csa); 849 sc->m32_mem.csa = vtophys(&sc->m32_mem.ccb); 850 851 bzero(sc->tiqb, sizeof sc->tiqb); 852 sc->m32x->tiqba = vtophys(&sc->tiqb); 853 sc->m32x->tiql = NIQB / 16 - 1; 854 855 bzero(sc->riqb, sizeof sc->riqb); 856 sc->m32x->riqba = vtophys(&sc->riqb); 857 sc->m32x->riql = NIQB / 16 - 1; 858 859 bzero(sc->ltiqb, sizeof sc->ltiqb); 860 sc->m32x->ltiqba = vtophys(&sc->ltiqb); 861 sc->m32x->ltiql = NIQB / 16 - 1; 862 863 bzero(sc->lriqb, sizeof sc->lriqb); 864 sc->m32x->lriqba = vtophys(&sc->lriqb); 865 sc->m32x->lriql = NIQB / 16 - 1; 866 867 bzero(sc->piqb, sizeof sc->piqb); 868 sc->m32x->piqba = vtophys(&sc->piqb); 869 sc->m32x->piql = NIQB / 16 - 1; 870 871 m32_init(sc); 872 f54_init(sc); 873 874 u = sc->m32x->stat; 875 sc->m32x->stat = u; 876 sc->m32_mem.ccb = 0x4; 877 sc->m32x->cmd = 0x1; 878 DELAY(1000); 879 u = sc->m32x->stat; 880 sc->m32x->stat = u; 881 882 /* set all timeslots to known state */ 883 for (i = 0; i < 32; i++) 884 sc->m32_mem.ts[i] = 0x20002000; 885 886 if (!(u & 1)) { 887 printf( 888"mn%d: WARNING: Controller failed the PCI bus-master test.\n" 889"mn%d: WARNING: Use a PCI slot which can support bus-master cards.\n", 890 sc->unit, sc->unit); 891 return (0); 892 } 893 return (1); 894} 895 896/* 897 * FALC54 interrupt handling 898 */ 899static void 900f54_intr(struct softc *sc) 901{ 902 unsigned g, u, s; 903 904 g = sc->f54r->gis; 905 u = sc->f54r->isr0 << 24; 906 u |= sc->f54r->isr1 << 16; 907 u |= sc->f54r->isr2 << 8; 908 u |= sc->f54r->isr3; 909 sc->falc_irq = u; 910 /* don't chat about the 1 sec heart beat */ 911 if (u & ~0x40) { 912#if 0 913 printf("%s*: FALC54 IRQ GIS:%02x %b\n", sc->name, g, u, "\20" 914 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 915 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 916 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 917 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 918#endif 919 s = sc->f54r->frs0 << 24; 920 s |= sc->f54r->frs1 << 16; 921 s |= sc->f54r->rsw << 8; 922 s |= sc->f54r->rsp; 923 sc->falc_state = s; 924 925 s &= ~0x01844038; /* undefined or static bits */ 926 s &= ~0x00009fc7; /* bits we don't care about */ 927 s &= ~0x00780000; /* XXX: TS16 related */ 928 s &= ~0x06000000; /* XXX: Multiframe related */ 929#if 0 930 printf("%s*: FALC54 Status %b\n", sc->name, s, "\20" 931 "\40LOS\37AIS\36LFA\35RRA\34AUXP\33NMF\32LMFA\31frs0.0" 932 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS\24TS16LFA\23frs1.2\22XLS\21XLO" 933 "\20RS1\17rsw.6\16RRA\15RY0\14RY1\13RY2\12RY3\11RY4" 934 "\10SI1\7SI2\6rsp.5\5rsp.4\4rsp.3\3RSIF\2RS13\1RS15"); 935#endif 936 if (s != sc->framer_state) { 937#if 0 938 for (i = 0; i < M32_CHAN; i++) { 939 if (!sc->ch[i]) 940 continue; 941 sp = &sc->ch[i]->ifsppp; 942 if (!(sp->pp_if.if_flags & IFF_UP)) 943 continue; 944 if (s) 945 timeout((timeout_t *)sp->pp_down, sp, 1 * hz); 946 else 947 timeout((timeout_t *)sp->pp_up, sp, 1 * hz); 948 } 949#endif 950 sc->framer_state = s; 951 } 952 } 953 /* Once per second check error counters */ 954 /* XXX: not clear if this is actually ok */ 955 if (!(u & 0x40)) 956 return; 957 sc->cnt_fec += sc->f54r->fec; 958 sc->cnt_cvc += sc->f54r->cvc; 959 sc->cnt_cec1 += sc->f54r->cec1; 960 sc->cnt_ebc += sc->f54r->ebc; 961 sc->cnt_cec2 += sc->f54r->cec2; 962 sc->cnt_cec3 += sc->f54r->cec3; 963 sc->cnt_rbc += sc->f54r->rbc; 964} 965 966/* 967 * Transmit interrupt for one channel 968 */ 969static void 970mn_tx_intr(struct softc *sc, u_int32_t vector) 971{ 972 u_int32_t chan; 973 struct trxd *dp; 974 struct mbuf *m; 975 976 chan = vector & 0x1f; 977 if (!sc->ch[chan]) 978 return; 979 if (sc->ch[chan]->state != UP) { 980 printf("%s: tx_intr when not UP\n", sc->name); 981 return; 982 } 983 for (;;) { 984 dp = sc->ch[chan]->x1; 985 if (vtophys(dp) == sc->m32_mem.ctxd[chan]) 986 return; 987 m = dp->m; 988 if (m) { 989#if 0 990 printf("%d = %d - %d (%p)\n", 991 sc->ch[chan]->tx_pending - m->m_pkthdr.len, 992 sc->ch[chan]->tx_pending , m->m_pkthdr.len, m); 993#endif 994 sc->ch[chan]->tx_pending -= m->m_pkthdr.len; 995 m_freem(m); 996 } 997 sc->ch[chan]->last_xmit = time_second; 998 sc->ch[chan]->x1 = dp->vnext; 999 mn_free_desc(dp); 1000 } 1001} 1002 1003/* 1004 * Receive interrupt for one channel 1005 */ 1006static void 1007mn_rx_intr(struct softc *sc, u_int32_t vector) 1008{ 1009 u_int32_t chan, err; 1010 struct trxd *dp; 1011 struct mbuf *m; 1012 struct schan *sch; 1013 1014 chan = vector & 0x1f; 1015 if (!sc->ch[chan]) 1016 return; 1017 sch = sc->ch[chan]; 1018 if (sch->state != UP) { 1019 printf("%s: rx_intr when not UP\n", sc->name); 1020 return; 1021 } 1022 vector &= ~0x1f; 1023 if (vector == 0x30000b00) 1024 sch->rx_error++; 1025 for (;;) { 1026 dp = sch->r1; 1027 if (vtophys(dp) == sc->m32_mem.crxd[chan]) 1028 return; 1029 m = dp->m; 1030 dp->m = 0; 1031 m->m_pkthdr.len = m->m_len = (dp->status >> 16) & 0x1fff; 1032 err = (dp->status >> 8) & 0xff; 1033 if (!err) { 1034 ng_queue_data(sch->hook, m, NULL); 1035 sch->last_recv = time_second; 1036 m = 0; 1037 /* we could be down by now... */ 1038 if (sch->state != UP) 1039 return; 1040 } else if (err & 0x40) { 1041 sch->short_error++; 1042 } else if (err & 0x10) { 1043 sch->crc_error++; 1044 } else if (err & 0x08) { 1045 sch->dribble_error++; 1046 } else if (err & 0x04) { 1047 sch->long_error++; 1048 } else if (err & 0x02) { 1049 sch->abort_error++; 1050 } else if (err & 0x01) { 1051 sch->overflow_error++; 1052 } 1053 if (err) { 1054 sch->last_rxerr = time_second; 1055 sch->prev_error = sch->last_error; 1056 sch->last_error = err; 1057 } 1058 1059 sc->ch[chan]->r1 = dp->vnext; 1060 1061 /* Replenish desc + mbuf supplies */ 1062 if (!m) { 1063 MGETHDR(m, M_DONTWAIT, MT_DATA); 1064 if (m == NULL) { 1065 mn_free_desc(dp); 1066 return; 1067 } 1068 MCLGET(m, M_DONTWAIT); 1069 if((m->m_flags & M_EXT) == 0) { 1070 mn_free_desc(dp); 1071 return; 1072 } 1073 } 1074 dp->m = m; 1075 dp->data = vtophys(m->m_data); 1076 dp->flags = 0x40000000; 1077 dp->flags += 1600 << 16; 1078 dp->next = vtophys(dp); 1079 dp->vnext = 0; 1080 sc->ch[chan]->rl->next = vtophys(dp); 1081 sc->ch[chan]->rl->vnext = dp; 1082 sc->ch[chan]->rl->flags &= ~0x40000000; 1083 sc->ch[chan]->rl = dp; 1084 } 1085} 1086 1087 1088/* 1089 * Interupt handler 1090 */ 1091 1092static void 1093mn_intr(void *xsc) 1094{ 1095 struct softc *sc; 1096 u_int32_t stat, lstat, u; 1097 int i, j; 1098 1099 sc = xsc; 1100 stat = sc->m32x->stat; 1101 lstat = sc->m32x->lstat; 1102#if 0 1103 if (!stat && !(lstat & 2)) 1104 return; 1105#endif 1106 1107 if (stat & ~0xc200) { 1108 printf("%s: I stat=%08x lstat=%08x\n", sc->name, stat, lstat); 1109 } 1110 1111 if ((stat & 0x200) || (lstat & 2)) 1112 f54_intr(sc); 1113 1114 for (j = i = 0; i < 64; i ++) { 1115 u = sc->riqb[i]; 1116 if (u) { 1117 sc->riqb[i] = 0; 1118 mn_rx_intr(sc, u); 1119 if ((u & ~0x1f) == 0x30000800 || (u & ~0x1f) == 0x30000b00) 1120 continue; 1121 u &= ~0x30000400; /* bits we don't care about */ 1122 if ((u & ~0x1f) == 0x00000900) 1123 continue; 1124 if (!(u & ~0x1f)) 1125 continue; 1126 if (!j) 1127 printf("%s*: RIQB:", sc->name); 1128 printf(" [%d]=%08x", i, u); 1129 j++; 1130 } 1131 } 1132 if (j) 1133 printf("\n"); 1134 1135 for (j = i = 0; i < 64; i ++) { 1136 u = sc->tiqb[i]; 1137 if (u) { 1138 sc->tiqb[i] = 0; 1139 mn_tx_intr(sc, u); 1140 if ((u & ~0x1f) == 0x20000800) 1141 continue; 1142 u &= ~0x20000000; /* bits we don't care about */ 1143 if (!u) 1144 continue; 1145 if (!j) 1146 printf("%s*: TIQB:", sc->name); 1147 printf(" [%d]=%08x", i, u); 1148 j++; 1149 } 1150 } 1151 if (j) 1152 printf("\n"); 1153 sc->m32x->stat = stat; 1154} 1155 1156static void 1157mn_timeout(void *xsc) 1158{ 1159 static int round = 0; 1160 struct softc *sc; 1161 1162 mn_intr(xsc); 1163 sc = xsc; 1164 timeout(mn_timeout, xsc, 10 * hz); 1165 round++; 1166 if (round == 2) { 1167 sc->m32_mem.ccb = 0x00008004; 1168 sc->m32x->cmd = 0x1; 1169 } else if (round > 2) { 1170 printf("%s: timeout\n", sc->name); 1171 } 1172} 1173 1174/* 1175 * PCI initialization stuff 1176 */ 1177 1178static struct pci_device mn_device = { 1179 "mn", 1180 mn_probe, 1181 mn_attach, 1182 &mn_count, 1183 NULL 1184}; 1185 1186#ifdef COMPAT_PCI_DRIVER 1187COMPAT_PCI_DRIVER(ti, mn_device); 1188#else 1189DATA_SET(pcidevice_set, mn_device); 1190#endif /* COMPAT_PCI_DRIVER */ 1191 1192static const char* 1193mn_probe (pcici_t tag, pcidi_t typea) 1194{ 1195 u_int id = pci_conf_read(tag, PCI_ID_REG); 1196 1197 if (sizeof (struct m32xreg) != 256) { 1198 printf("MN: sizeof(struct m32xreg) = %d, should have been 256\n", sizeof (struct m32xreg)); 1199 return (0); 1200 } 1201 if (sizeof (struct f54rreg) != 128) { 1202 printf("MN: sizeof(struct f54rreg) = %d, should have been 128\n", sizeof (struct f54rreg)); 1203 return (0); 1204 } 1205 if (sizeof (struct f54wreg) != 128) { 1206 printf("MN: sizeof(struct f54wreg) = %d, should have been 128\n", sizeof (struct f54wreg)); 1207 return (0); 1208 } 1209 1210 if (id == 0x2101110a) 1211 return "Munich32X E1/T1 HDLC Controller"; 1212 1213 return 0; 1214} 1215 1216static void 1217mn_attach (pcici_t tag, int unit) 1218{ 1219 struct softc *sc; 1220 u_int32_t u; 1221 u_int32_t pci_class; 1222 static int once; 1223 1224 if (!once) { 1225 if (ng_newtype(&mntypestruct)) 1226 printf("ng_newtype failed\n"); 1227 once++; 1228 } 1229 1230 sc = (struct softc *)malloc(sizeof *sc, M_MN, M_WAITOK); 1231 softc[unit] = sc; 1232 bzero(sc, sizeof *sc); 1233 1234 sc->tag = tag; 1235 sc->unit = unit; 1236 sprintf(sc->name, "mn%d", unit); 1237 1238 if (!pci_map_int(tag, mn_intr, sc, &net_imask)) { 1239 printf("mn%d: could not map interrupt\n", sc->unit); 1240 return; 1241 } 1242 pci_map_mem(tag, PCI_MAP_REG_START, &sc->m0v, &sc->m0p); 1243 pci_map_mem(tag, PCI_MAP_REG_START + 4, &sc->m1v, &sc->m1p); 1244 1245 u = pci_conf_read(tag, PCIR_COMMAND); 1246 pci_conf_write(tag, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); 1247 pci_conf_write(tag, PCIR_COMMAND, 0x02800046); 1248 1249 pci_class = pci_conf_read(tag, PCI_CLASS_REG); 1250 1251 sc->m32x = (struct m32xreg *) sc->m0v; 1252 sc->f54w = (struct f54wreg *) sc->m1v; 1253 sc->f54r = (struct f54rreg *) sc->m1v; 1254 1255 /* We must reset before poking at FALC54 registers */ 1256 u = mn_reset(sc); 1257 if (!u) 1258 return; 1259 1260 printf("mn%d: Munich32X", sc->unit); 1261 switch (pci_class & 0xff) { 1262 case 0x13: 1263 printf(" Rev 2.2"); 1264 break; 1265 default: 1266 printf(" Rev 0x%x\n", pci_class & 0xff); 1267 } 1268 printf(", Falc54"); 1269 switch (sc->f54r->vstr) { 1270 case 0: 1271 printf(" Rev < 1.3\n"); 1272 break; 1273 case 1: 1274 printf(" Rev 1.3\n"); 1275 break; 1276 case 2: 1277 printf(" Rev 1.4\n"); 1278 break; 1279 case 0x10: 1280 printf("-LH Rev 1.1\n"); 1281 break; 1282 case 0x13: 1283 printf("-LH Rev 1.3\n"); 1284 break; 1285 default: 1286 printf(" Rev 0x%x\n", sc->f54r->vstr); 1287 } 1288 1289 if (ng_make_node_common(&mntypestruct, &sc->node) != 0) { 1290 printf("ng_make_node_common failed\n"); 1291 return; 1292 } 1293 sc->node->private = sc; 1294 sprintf(sc->nodename, "%s%d", NG_MN_NODE_TYPE, sc->unit); 1295 if (ng_name_node(sc->node, sc->nodename)) { 1296 ng_rmnode(sc->node); 1297 ng_unref(sc->node); 1298 return; 1299 } 1300 1301 return; 1302} 1303#endif /* _KERNEL */ 1304