if_mn.c revision 57678 
1/*
2 * ----------------------------------------------------------------------------
3 * "THE BEER-WARE LICENSE" (Revision 42):
4 * <phk@FreeBSD.org> wrote this file.  As long as you retain this notice you
5 * can do whatever you want with this stuff. If we meet some day, and you think
6 * this stuff is worth it, you can buy me a beer in return.   Poul-Henning Kamp
7 * ----------------------------------------------------------------------------
8 *
9 * $Id: if_mn.c,v 1.1 1999/02/01 13:06:40 phk Exp $
10 *
11 * Driver for Siemens reference design card "Easy321-R1".
12 *
13 * This card contains a FALC54 E1/T1 framer and a MUNICH32X 32-channel HDLC
14 * controller.
15 *
16 * The driver supports E1 mode with up to 31 channels.  We send CRC4 but don't
17 * check it coming in.
18 *
19 * The FALC54 and MUNICH32X have far too many registers and weird modes for
20 * comfort, so I have not bothered typing it all into a "fooreg.h" file,
21 * you will (badly!) need the documentation anyway if you want to mess with
22 * this gadget.
23 *
24 * $FreeBSD: head/sys/pci/if_mn.c 57678 2000-03-01 21:04:54Z phk $
25 */
26
27/*
28 * Stuff to describe the MUNIC32X and FALC54 chips.
29 */
30
31#define M32_CHAN	32	/* We have 32 channels */
32#define M32_TS		32	/* We have 32 timeslots */
33
34#define NG_MN_NODE_TYPE	"mn"
35
36#ifdef _KERNEL
37#define PPP_HEADER_LEN       4 	/* XXX: should live in some header somewhere */
38
39#include <sys/param.h>
40#include <sys/systm.h>
41#include <sys/conf.h>
42#include <sys/mbuf.h>
43#include <sys/kernel.h>
44#include <sys/sysctl.h>
45#include <sys/malloc.h>
46#include <sys/socket.h>
47#include <sys/sockio.h>
48#include <pci/pcireg.h>
49#include <pci/pcivar.h>
50#include <vm/vm.h>
51#include <vm/pmap.h>
52#include <machine/clock.h>
53
54#include <netgraph/ng_message.h>
55#include <netgraph/ng_sample.h>
56#include <netgraph/netgraph.h>
57
58static int mn_maxlatency = 1000;
59SYSCTL_INT(_debug, OID_AUTO, mn_maxlatency, CTLFLAG_RW,
60    &mn_maxlatency, 0,
61	"The number of milliseconds a packet is allowed to spend in the output queue.  "
62	"If the output queue is longer than this number of milliseconds when the packet "
63	"arrives for output, the packet will be dropped."
64);
65
66#ifndef NMN
67/* Most machines don't support more than 4 busmaster PCI slots, if even that many */
68#define NMN	4
69#endif
70
71/* From: PEB 20321 data sheet, p187, table 22 */
72struct m32xreg {
73	u_int32_t conf,    cmd,     stat,    imask;
74	u_int32_t fill10,  piqba,   piql,    fill1c;
75	u_int32_t mode1,   mode2,   ccba,    txpoll;
76	u_int32_t tiqba,   tiql,    riqba,   riql;
77	u_int32_t lconf,   lccba,   fill48,  ltran;
78	u_int32_t ltiqba,  ltiql,   lriqba,  lriql;
79	u_int32_t lreg0,   lreg1,   lreg2,   lreg3;
80	u_int32_t lreg4,   lreg5,   lre6,    lstat;
81	u_int32_t gpdir,   gpdata,  gpod,    fill8c;
82	u_int32_t ssccon,  sscbr,   ssctb,   sscrb;
83	u_int32_t ssccse,  sscim,   fillab,  fillac;
84	u_int32_t iomcon1, iomcon2, iomstat, fillbc;
85	u_int32_t iomcit0, iomcit1, iomcir0, iomcir1;
86	u_int32_t iomtmo,  iomrmo,  filld8,  filldc;
87	u_int32_t mbcmd,   mbdata1, mbdata2, mbdata3;
88	u_int32_t mbdata4, mbdata5, mbdata6, mbdata7;
89};
90
91/* From: PEB 2254 data sheet, p80, table 10 */
92struct f54wreg {
93	u_int16_t xfifo;
94	u_int8_t                  cmdr,   mode,   rah1,   rah2,   ral1,   ral2;
95	u_int8_t  ipc,    ccr1,   ccr3,   pre,    rtr1,   rtr2,   rtr3,   rtr4;
96	u_int8_t  ttr1,   ttr2,   ttr3,   ttr4,   imr0,   imr1,   imr2,   imr3;
97	u_int8_t  imr4,   fill19, fmr0,   fmr1,   fmr2,   loop,   xsw,    xsp;
98	u_int8_t  xc0,    xc1,    rc0,    rc1,    xpm0,   xpm1,   xpm2,   tswm;
99	u_int8_t  test1,  idle,   xsa4,   xsa5,   xsa6,   xsa7,   xsa8,   fmr3;
100	u_int8_t  icb1,   icb2,   icb3,   icb4,   lim0,   lim1,   pcd,    pcr;
101	u_int8_t  lim2,   fill39[7];
102	u_int8_t  fill40[8];
103	u_int8_t  fill48[8];
104	u_int8_t  fill50[8];
105	u_int8_t  fill58[8];
106	u_int8_t  dec,    fill61, test2,  fill63[5];
107	u_int8_t  fill68[8];
108	u_int8_t  xs[16];
109};
110
111/* From: PEB 2254 data sheet, p117, table 10 */
112struct f54rreg {
113	u_int16_t rfifo;
114	u_int8_t                  fill2,  mode,   rah1,   rah2,   ral1,   ral2;
115	u_int8_t  ipc,    ccr1,   ccr3,   pre,    rtr1,   rtr2,   rtr3,   rtr4;
116	u_int8_t  ttr1,   ttr2,   ttr3,   ttr4,   imr0,   imr1,   imr2,   imr3;
117	u_int8_t  imr4,   fill19, fmr0,   fmr1,   fmr2,   loop,   xsw,    xsp;
118	u_int8_t  xc0,    xc1,    rc0,    rc1,    xpm0,   xpm1,   xpm2,   tswm;
119	u_int8_t  test,   idle,   xsa4,   xsa5,   xsa6,   xsa7,   xsa8,   fmr13;
120	u_int8_t  icb1,   icb2,   icb3,   icb4,   lim0,   lim1,   pcd,    pcr;
121	u_int8_t  lim2,   fill39[7];
122	u_int8_t  fill40[8];
123	u_int8_t  fill48[4],                      frs0,   frs1,   rsw,    rsp;
124	u_int16_t fec,            cvc,            cec1,           ebc;
125	u_int16_t cec2,           cec3;
126	u_int8_t                                  rsa4,   rsa5,   rsa6,   rsa7;
127	u_int8_t  rsa8,   rsa6s,  tsr0,   tsr1,   sis,    rsis;
128	u_int16_t                                                 rbc;
129	u_int8_t  isr0,   isr1,   isr2,   isr3,   fill6c, fill6d, gis,    vstr;
130	u_int8_t  rs[16];
131};
132
133/* Transmit & receive descriptors */
134struct trxd {
135	u_int32_t	flags;
136	vm_offset_t	next;
137	vm_offset_t	data;
138	u_int32_t	status;	/* only used for receive */
139	struct mbuf	*m;	/* software use only */
140	struct trxd	*vnext;	/* software use only */
141};
142
143/* Channel specification */
144struct cspec {
145	u_int32_t	flags;
146	vm_offset_t	rdesc;
147	vm_offset_t	tdesc;
148	u_int32_t	itbs;
149};
150
151struct m32_mem {
152	vm_offset_t	csa;
153	u_int32_t	ccb;
154	u_int32_t	reserve1[2];
155	u_int32_t	ts[M32_TS];
156	struct cspec	cs[M32_CHAN];
157	vm_offset_t	crxd[M32_CHAN];
158	vm_offset_t	ctxd[M32_CHAN];
159};
160
161struct softc;
162struct sockaddr;
163struct rtentry;
164
165static	const char*	mn_probe  (pcici_t tag, pcidi_t type);
166static	void	mn_attach (pcici_t tag, int unit);
167static	u_long	mn_count;
168static	void	mn_create_channel(struct softc *sc, int chan);
169static	int	mn_reset(struct softc *sc);
170static	struct trxd * mn_alloc_desc(void);
171static	void	mn_free_desc(struct trxd *dp);
172static	void	mn_intr(void *xsc);
173static	u_int32_t mn_parse_ts(const char *s, int *nbit);
174#ifdef notyet
175static	void	m32_dump(struct softc *sc);
176static	void	f54_dump(struct softc *sc);
177static	void	mn_fmt_ts(char *p, u_int32_t ts);
178#endif /* notyet */
179
180static	ng_constructor_t ngmn_constructor;
181static	ng_rcvmsg_t ngmn_rcvmsg;
182static	ng_shutdown_t ngmn_shutdown;
183static	ng_newhook_t ngmn_newhook;
184static	ng_connect_t ngmn_connect;
185static	ng_rcvdata_t ngmn_rcvdata;
186static	ng_disconnect_t ngmn_disconnect;
187
188static struct ng_type mntypestruct = {
189	NG_VERSION,
190	NG_MN_NODE_TYPE,
191	NULL,
192	ngmn_constructor,
193	ngmn_rcvmsg,
194	ngmn_shutdown,
195	ngmn_newhook,
196	NULL,
197	ngmn_connect,
198	ngmn_rcvdata,
199	ngmn_rcvdata,
200	ngmn_disconnect,
201	NULL
202};
203
204static MALLOC_DEFINE(M_MN, "mn", "Mx driver related");
205
206#define NIQB	64
207
208struct softc;
209
210struct schan {
211	enum {DOWN, UP} state;
212	struct softc	*sc;
213	int		chan;
214	u_int32_t	ts;
215	char		name[8];
216	struct trxd	*r1, *rl;
217	struct trxd	*x1, *xl;
218	hook_p		hook;
219
220	time_t		last_recv;
221	time_t		last_rxerr;
222	time_t		last_xmit;
223
224	u_long		rx_error;
225
226	u_long		short_error;
227	u_long		crc_error;
228	u_long		dribble_error;
229	u_long		long_error;
230	u_long		abort_error;
231	u_long		overflow_error;
232
233	int		last_error;
234	int		prev_error;
235
236	u_long		tx_pending;
237	u_long		tx_limit;
238};
239
240static struct softc {
241	int	unit;
242	pcici_t tag;
243	vm_offset_t	m0v, m0p, m1v, m1p;
244	struct m32xreg	*m32x;
245	struct f54wreg	*f54w;
246	struct f54rreg	*f54r;
247	struct m32_mem	m32_mem;
248	u_int32_t	tiqb[NIQB];
249	u_int32_t	riqb[NIQB];
250	u_int32_t	piqb[NIQB];
251	u_int32_t	ltiqb[NIQB];
252	u_int32_t	lriqb[NIQB];
253	char		name[8];
254	u_int32_t	falc_irq, falc_state, framer_state;
255	struct schan *ch[M32_CHAN];
256	char	nodename[NG_NODELEN + 1];
257	node_p	node;
258
259	u_long		cnt_fec;
260	u_long		cnt_cvc;
261	u_long		cnt_cec1;
262	u_long		cnt_ebc;
263	u_long		cnt_cec2;
264	u_long		cnt_cec3;
265	u_long		cnt_rbc;
266} *softc[NMN];
267
268static int
269ngmn_constructor(node_p *nodep)
270{
271
272	return (EINVAL);
273}
274
275static int
276ngmn_shutdown(node_p nodep)
277{
278
279	return (EINVAL);
280}
281
282static int
283ngmn_rcvmsg(node_p node, struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp)
284{
285	struct softc *sc;
286	struct schan *sch;
287	char *arg;
288	int pos, i;
289
290	sc = node->private;
291
292	if (msg->header.typecookie != NGM_GENERIC_COOKIE ||
293	    msg->header.cmd != NGM_TEXT_STATUS) {
294		if (resp)
295			*resp = NULL;
296		FREE(msg, M_NETGRAPH);
297		return (EINVAL);
298	}
299	NG_MKRESPONSE(*resp, msg, sizeof(struct ng_mesg) + NG_TEXTRESPONSE,
300	    M_NOWAIT);
301	if (*resp == NULL) {
302		FREE(msg, M_NETGRAPH);
303		return (ENOMEM);
304	}
305	arg = (char *)(*resp)->data;
306	pos = 0;
307	pos += sprintf(pos + arg,"Framer status %b;\n", sc->framer_state, "\20"
308	    "\40LOS\37AIS\36LFA\35RRA"
309	    "\34AUXP\33NMF\32LMFA\31frs0.0"
310	    "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS"
311	    "\24TS16LFA\23frs1.2\22XLS\21XLO"
312	    "\20RS1\17rsw.6\16RRA\15RY0"
313	    "\14RY1\13RY2\12RY3\11RY4"
314	    "\10SI1\7SI2\6rsp.5\5rsp.4"
315	    "\4rsp.3\3RSIF\2RS13\1RS15");
316	pos += sprintf(pos + arg,"    Framing errors: %lu", sc->cnt_fec);
317	pos += sprintf(pos + arg,"  Code Violations: %lu\n", sc->cnt_cvc);
318
319	pos += sprintf(pos + arg,"    Falc State %b;\n", sc->falc_state, "\20"
320	    "\40LOS\37AIS\36LFA\35RRA"
321	    "\34AUXP\33NMF\32LMFA\31frs0.0"
322	    "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS"
323	    "\24TS16LFA\23frs1.2\22XLS\21XLO"
324	    "\20RS1\17rsw.6\16RRA\15RY0"
325	    "\14RY1\13RY2\12RY3\11RY4"
326	    "\10SI1\7SI2\6rsp.5\5rsp.4"
327	    "\4rsp.3\3RSIF\2RS13\1RS15");
328	pos += sprintf(pos + arg, "    Falc IRQ %b\n", sc->falc_irq, "\20"
329	    "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF"
330	    "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR"
331	    "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA"
332	    "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP");
333	for (i = 0; i < M32_CHAN; i++) {
334		if (!sc->ch[i])
335			continue;
336		sch = sc->ch[i];
337
338		pos += sprintf(arg + pos, "  Chan %d <%s> ",
339		    i, sch->hook->name);
340
341		pos += sprintf(arg + pos, "  Last Rx: ");
342		if (sch->last_recv)
343			pos += sprintf(arg + pos, "%lu s", time_second - sch->last_recv);
344		else
345			pos += sprintf(arg + pos, "never");
346
347		pos += sprintf(arg + pos, ", last RxErr: ");
348		if (sch->last_rxerr)
349			pos += sprintf(arg + pos, "%lu s", time_second - sch->last_rxerr);
350		else
351			pos += sprintf(arg + pos, "never");
352
353		pos += sprintf(arg + pos, ", last Tx: ");
354		if (sch->last_xmit)
355			pos += sprintf(arg + pos, "%lu s\n", time_second - sch->last_xmit);
356		else
357			pos += sprintf(arg + pos, "never\n");
358
359		pos += sprintf(arg + pos, "    RX error(s) %lu", sch->rx_error);
360		pos += sprintf(arg + pos, " Short: %lu", sch->short_error);
361		pos += sprintf(arg + pos, " CRC: %lu", sch->crc_error);
362		pos += sprintf(arg + pos, " Mod8: %lu", sch->dribble_error);
363		pos += sprintf(arg + pos, " Long: %lu", sch->long_error);
364		pos += sprintf(arg + pos, " Abort: %lu", sch->abort_error);
365		pos += sprintf(arg + pos, " Overflow: %lu\n", sch->overflow_error);
366
367		pos += sprintf(arg + pos, "    Last error: %b  Prev error: %b\n",
368		    sch->last_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN",
369		    sch->prev_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN");
370		pos += sprintf(arg + pos, "    Xmit bytes pending %ld\n",
371		    sch->tx_pending);
372	}
373	(*resp)->header.arglen = pos + 1;
374	FREE(msg, M_NETGRAPH);
375	return (0);
376}
377
378static int
379ngmn_newhook(node_p node, hook_p hook, const char *name)
380{
381	u_int32_t ts, chan;
382	struct softc *sc;
383	int nbit;
384
385	sc = node->private;
386
387	if (name[0] != 't' || name[1] != 's')
388		return (EINVAL);
389
390	ts = mn_parse_ts(name + 2, &nbit);
391	if (ts == 0)
392		return (EINVAL);
393	chan = ffs(ts) - 1;
394	if (sc->ch[chan])
395		return (EBUSY);
396	mn_create_channel(sc, chan);
397	sc->ch[chan]->ts = ts;
398	sc->ch[chan]->hook = hook;
399	sc->ch[chan]->tx_limit = nbit * 8;
400	hook->private = sc->ch[chan];
401	return(0);
402}
403
404
405static struct trxd *mn_desc_free;
406
407static struct trxd *
408mn_alloc_desc(void)
409{
410	struct trxd *dp;
411
412	dp = mn_desc_free;
413	if (dp)
414		mn_desc_free = dp->vnext;
415	else
416		dp = (struct trxd *)malloc(sizeof *dp, M_MN, M_NOWAIT);
417	return (dp);
418}
419
420static void
421mn_free_desc(struct trxd *dp)
422{
423	dp->vnext =  mn_desc_free;
424	mn_desc_free = dp;
425}
426
427static u_int32_t
428mn_parse_ts(const char *s, int *nbit)
429{
430	unsigned r;
431	int i, j;
432	char *p;
433
434	r = 0;
435	j = 0;
436	*nbit = 0;
437	while(*s) {
438		i = strtol(s, &p, 0);
439		if (i < 1 || i > 31)
440			return (0);
441		while (j && j < i) {
442			r |= 1 << j++;
443			(*nbit)++;
444		}
445		j = 0;
446		r |= 1 << i;
447		(*nbit)++;
448		if (*p == ',') {
449			s = p + 1;
450			continue;
451		} else if (*p == '-') {
452			j = i;
453			s = p + 1;
454			continue;
455		} else if (!*p) {
456			break;
457		} else {
458			return (0);
459		}
460	}
461	return (r);
462}
463
464#ifdef notyet
465static void
466mn_fmt_ts(char *p, u_int32_t ts)
467{
468	char *s;
469	int j;
470
471	s = "";
472	ts &= 0xfffffffe;
473	for (j = 1; j < 32; j++) {
474		if (!(ts & (1 << j)))
475			continue;
476		sprintf(p, "%s%d", s, j);
477		p += strlen(p);
478		s = ",";
479		if (!(ts & (1 << (j+1))))
480			continue;
481		for (; j < 32; j++)
482			if (!(ts & (1 << (j+1))))
483				break;
484		sprintf(p, "-%d", j);
485		p += strlen(p);
486		s = ",";
487	}
488}
489#endif /* notyet */
490
491/*
492 * OUTPUT
493 */
494
495static int
496ngmn_rcvdata(hook_p hook, struct mbuf *m, meta_p meta)
497{
498	struct mbuf  *m2;
499	struct trxd *dp, *dp2;
500	struct schan *sch;
501	struct softc *sc;
502	int chan, pitch, len;
503
504	sch = hook->private;
505	sc = sch->sc;
506	chan = sch->chan;
507
508	if (sch->state != UP) {
509		NG_FREE_DATA(m, meta);
510		printf("D1\n");
511		return (0);
512	}
513	if (sch->tx_pending + m->m_pkthdr.len > sch->tx_limit * mn_maxlatency) {
514		NG_FREE_DATA(m, meta);
515		printf("D2\n");
516		return (0);
517	}
518	NG_FREE_META(meta);
519	pitch = 0;
520	m2 = m;
521	dp2 = sc->ch[chan]->xl;
522	len = m->m_pkthdr.len;
523	while (len) {
524		dp = mn_alloc_desc();
525		if (!dp) {
526			pitch++;
527			m_freem(m);
528			sc->ch[chan]->xl = dp2;
529			dp = dp2->vnext;
530			while (dp) {
531				dp2 = dp->vnext;
532				mn_free_desc(dp);
533				dp = dp2;
534			}
535			sc->ch[chan]->xl->vnext = 0;
536			break;
537		}
538		dp->data = vtophys(m2->m_data);
539		dp->flags = m2->m_len << 16;
540		dp->flags += 1;
541		len -= m2->m_len;
542		dp->next = vtophys(dp);
543		dp->vnext = 0;
544		sc->ch[chan]->xl->next = vtophys(dp);
545		sc->ch[chan]->xl->vnext = dp;
546		sc->ch[chan]->xl = dp;
547		if (!len) {
548			dp->m = m;
549			dp->flags |= 0xc0000000;
550			dp2->flags &= ~0x40000000;
551		} else {
552			dp->m = 0;
553			m2 = m2->m_next;
554		}
555	}
556	if (pitch)
557		printf("%s%d: Short on mem, pitched %d packets\n",
558		    sc->name, chan, pitch);
559	else {
560#if 0
561		printf("%d = %d + %d (%p)\n",
562		    sch->tx_pending + m->m_pkthdr.len,
563		    sch->tx_pending , m->m_pkthdr.len, m);
564#endif
565		sch->tx_pending += m->m_pkthdr.len;
566	}
567	return (0);
568}
569
570/*
571 * OPEN
572 */
573static int
574ngmn_connect(hook_p hook)
575{
576	int i, nts, chan;
577	struct trxd *dp, *dp2;
578	struct mbuf *m;
579	struct softc *sc;
580	struct schan *sch;
581	u_int32_t u;
582
583	sch = hook->private;
584	chan = sch->chan;
585	sc = sch->sc;
586
587	if (sch->state == UP)
588		return (0);
589	sch->state = UP;
590
591	/* Count and configure the timeslots for this channel */
592	for (nts = i = 0; i < 32; i++)
593		if (sch->ts & (1 << i)) {
594			sc->m32_mem.ts[i] = 0x00ff00ff |
595				(chan << 24) | (chan << 8);
596			nts++;
597		}
598
599	/* Init the receiver & xmitter to HDLC */
600	sc->m32_mem.cs[chan].flags = 0x80e90006;
601	/* Allocate two buffers per timeslot */
602	sc->m32_mem.cs[chan].itbs = nts * 2;
603
604	/* Setup a transmit chain with one descriptor */
605	/* XXX: we actually send a 1 byte packet */
606	dp = mn_alloc_desc();
607	MGETHDR(m, M_WAIT, MT_DATA);
608	m->m_pkthdr.len = 0;
609	dp->m = m;
610	dp->flags = 0xc0000000 + (1 << 16);
611	dp->next = vtophys(dp);
612	dp->vnext = 0;
613	dp->data = vtophys(sc->name);
614	sc->m32_mem.cs[chan].tdesc = vtophys(dp);
615	sc->ch[chan]->x1 = dp;
616	sc->ch[chan]->xl = dp;
617
618	/* Setup a receive chain with 5 + NTS descriptors */
619
620	dp = mn_alloc_desc();
621	MGETHDR(m, M_WAIT, MT_DATA);
622	MCLGET(m, M_WAIT);
623	dp->m = m;
624	dp->data = vtophys(m->m_data);
625	dp->flags = 0x40000000;
626	dp->flags += 1600 << 16;
627	dp->next = vtophys(dp);
628	dp->vnext = 0;
629	sc->ch[chan]->rl = dp;
630
631	for (i = 0; i < (nts + 10); i++) {
632		dp2 = dp;
633		dp = mn_alloc_desc();
634		MGETHDR(m, M_WAIT, MT_DATA);
635		MCLGET(m, M_WAIT);
636		dp->m = m;
637		dp->data = vtophys(m->m_data);
638		dp->flags = 0x00000000;
639		dp->flags += 1600 << 16;
640		dp->next = vtophys(dp2);
641		dp->vnext = dp2;
642	}
643	sc->m32_mem.cs[chan].rdesc = vtophys(dp);
644	sc->ch[chan]->r1 = dp;
645
646	/* Initialize this channel */
647	sc->m32_mem.ccb = 0x00008000 + (chan << 8);
648	sc->m32x->cmd = 0x1;
649	DELAY(1000);
650	u = sc->m32x->stat;
651	if (!(u & 1))
652		printf("%s: init chan %d stat %08x\n", sc->name, chan, u);
653	sc->m32x->stat = 1;
654
655	return (0);
656}
657
658/*
659 * CLOSE
660 */
661static int
662ngmn_disconnect(hook_p hook)
663{
664	int chan, i;
665	struct softc *sc;
666	struct schan *sch;
667	struct trxd *dp, *dp2;
668	u_int32_t u;
669
670	sch = hook->private;
671	chan = sch->chan;
672	sc = sch->sc;
673
674	if (sch->state == DOWN)
675		return (0);
676	sch->state = DOWN;
677
678	/* Set receiver & transmitter off */
679	sc->m32_mem.cs[chan].flags = 0x80920006;
680	sc->m32_mem.cs[chan].itbs = 0;
681
682	/* free the timeslots */
683	for (i = 0; i < 32; i++)
684		if (sc->ch[chan]->ts & (1 << i))
685			sc->m32_mem.ts[i] = 0x20002000;
686
687	/* Initialize this channel */
688	sc->m32_mem.ccb = 0x00008000 + (chan << 8);
689	sc->m32x->cmd = 0x1;
690	DELAY(30);
691	u = sc->m32x->stat;
692	if (!(u & 1))
693		printf("%s: zap chan %d stat %08x\n", sc->name, chan, u);
694	sc->m32x->stat = 1;
695
696	/* Free all receive descriptors and mbufs */
697	for (dp = sc->ch[chan]->r1; dp ; dp = dp2) {
698		if (dp->m)
699			m_freem(dp->m);
700		sc->ch[chan]->r1 = dp2 = dp->vnext;
701		mn_free_desc(dp);
702	}
703
704	/* Free all transmit descriptors and mbufs */
705	for (dp = sc->ch[chan]->x1; dp ; dp = dp2) {
706		if (dp->m)
707			m_freem(dp->m);
708		sc->ch[chan]->x1 = dp2 = dp->vnext;
709		mn_free_desc(dp);
710	}
711	return(0);
712}
713
714/*
715 * Create a new channel.
716 */
717static void
718mn_create_channel(struct softc *sc, int chan)
719{
720	struct schan *sch;
721
722	sch = sc->ch[chan] = (struct schan *)malloc(sizeof *sc->ch[chan],
723	    M_MN, M_WAITOK);
724	bzero(sch, sizeof *sch);
725	sch->sc = sc;
726	sch->state = DOWN;
727	sch->chan = chan;
728	sprintf(sch->name, "%s%d", sc->name, chan);
729	return;
730}
731
732#ifdef notyet
733/*
734 * Dump Munich32x state
735 */
736static void
737m32_dump(struct softc *sc)
738{
739	u_int32_t *tp4;
740	int i, j;
741
742	printf("mn%d: MUNICH32X dump\n", sc->unit);
743	tp4 = (u_int32_t *)sc->m0v;
744	for(j = 0; j < 64; j += 8) {
745		printf("%02x", j * sizeof *tp4);
746		for(i = 0; i < 8; i++)
747			printf(" %08x", tp4[i+j]);
748		printf("\n");
749	}
750	for(j = 0; j < M32_CHAN; j++) {
751		if (!sc->ch[j])
752			continue;
753		printf("CH%d: state %d ts %08x",
754			j, sc->ch[j]->state, sc->ch[j]->ts);
755		printf("  %08x %08x %08x %08x %08x %08x\n",
756			sc->m32_mem.cs[j].flags,
757			sc->m32_mem.cs[j].rdesc,
758			sc->m32_mem.cs[j].tdesc,
759			sc->m32_mem.cs[j].itbs,
760			sc->m32_mem.crxd[j],
761			sc->m32_mem.ctxd[j] );
762	}
763}
764
765/*
766 * Dump Falch54 state
767 */
768static void
769f54_dump(struct softc *sc)
770{
771	u_int8_t *tp1;
772	int i, j;
773
774	printf("%s: FALC54 dump\n", sc->name);
775	tp1 = (u_int8_t *)sc->m1v;
776	for(j = 0; j < 128; j += 16) {
777		printf("%s: %02x |", sc->name, j * sizeof *tp1);
778		for(i = 0; i < 16; i++)
779			printf(" %02x", tp1[i+j]);
780		printf("\n");
781	}
782}
783#endif /* notyet */
784
785/*
786 * Init Munich32x
787 */
788static void
789m32_init(struct softc *sc)
790{
791
792	sc->m32x->conf =  0x00000000;
793	sc->m32x->mode1 = 0x81048000 + 1600; 	/* XXX: temp */
794#if 1
795	sc->m32x->mode2 = 0x00000081;
796	sc->m32x->txpoll = 0xffffffff;
797#else
798	sc->m32x->mode2 = 0x00000101;
799#endif
800	sc->m32x->lconf = 0x6060009B;
801	sc->m32x->imask = 0x00000000;
802}
803
804/*
805 * Init the Falc54
806 */
807static void
808f54_init(struct softc *sc)
809{
810	sc->f54w->ipc  = 0x07;
811
812	sc->f54w->xpm0 = 0xbd;
813	sc->f54w->xpm1 = 0x03;
814	sc->f54w->xpm2 = 0x00;
815
816	sc->f54w->imr0 = 0x18; /* RMB, CASC */
817	sc->f54w->imr1 = 0x08; /* XMB */
818	sc->f54w->imr2 = 0x00;
819	sc->f54w->imr3 = 0x38; /* LMFA16, AIS16, RA16 */
820	sc->f54w->imr4 = 0x00;
821
822	sc->f54w->fmr0 = 0xf0; /* X: HDB3, R: HDB3 */
823	sc->f54w->fmr1 = 0x0e; /* Send CRC4, 2Mbit, ECM */
824	sc->f54w->fmr2 = 0x03; /* Auto Rem-Alarm, Auto resync */
825
826	sc->f54w->lim1 = 0xb0; /* XCLK=8kHz, .62V threshold */
827	sc->f54w->pcd =  0x0a;
828	sc->f54w->pcr =  0x15;
829	sc->f54w->xsw =  0x9f; /* fmr4 */
830	sc->f54w->xsp =  0x1c; /* fmr5 */
831	sc->f54w->xc0 =  0x07;
832	sc->f54w->xc1 =  0x3d;
833	sc->f54w->rc0 =  0x05;
834	sc->f54w->rc1 =  0x00;
835	sc->f54w->cmdr = 0x51;
836}
837
838static int
839mn_reset(struct softc *sc)
840{
841	u_int32_t u;
842	int i, j;
843
844	u = 0;
845	for(i = 5; i >= 0; i-- ) {
846		sc->m32x->gpdir = i;
847		for (j = 0; j < 8; j ++) {
848			sc->m32x->gpdata = j;
849			u += sc->m32x->gpdata;
850		}
851	}
852	if (u != 0xe4) {
853		printf("mn%d: WARNING: Controller failed to initialize.\n",
854		    sc->unit);
855#if 0
856		return (0);
857#endif
858		printf("mn%d: %x\n", sc->unit, u);
859	}
860
861	sc->m32x->ccba = vtophys(&sc->m32_mem.csa);
862	sc->m32_mem.csa = vtophys(&sc->m32_mem.ccb);
863
864	bzero(sc->tiqb, sizeof sc->tiqb);
865	sc->m32x->tiqba = vtophys(&sc->tiqb);
866	sc->m32x->tiql = NIQB / 16 - 1;
867
868	bzero(sc->riqb, sizeof sc->riqb);
869	sc->m32x->riqba = vtophys(&sc->riqb);
870	sc->m32x->riql = NIQB / 16 - 1;
871
872	bzero(sc->ltiqb, sizeof sc->ltiqb);
873	sc->m32x->ltiqba = vtophys(&sc->ltiqb);
874	sc->m32x->ltiql = NIQB / 16 - 1;
875
876	bzero(sc->lriqb, sizeof sc->lriqb);
877	sc->m32x->lriqba = vtophys(&sc->lriqb);
878	sc->m32x->lriql = NIQB / 16 - 1;
879
880	bzero(sc->piqb, sizeof sc->piqb);
881	sc->m32x->piqba = vtophys(&sc->piqb);
882	sc->m32x->piql = NIQB / 16 - 1;
883
884	m32_init(sc);
885	f54_init(sc);
886
887	u = sc->m32x->stat;
888	sc->m32x->stat = u;
889	sc->m32_mem.ccb = 0x4;
890	sc->m32x->cmd = 0x1;
891	DELAY(1000);
892	u = sc->m32x->stat;
893	sc->m32x->stat = u;
894
895	/* set all timeslots to known state */
896	for (i = 0; i < 32; i++)
897		sc->m32_mem.ts[i] = 0x20002000;
898
899	if (!(u & 1)) {
900		printf(
901"mn%d: WARNING: Controller failed the PCI bus-master test.\n"
902"mn%d: WARNING: Use a PCI slot which can support bus-master cards.\n",
903		    sc->unit, sc->unit);
904		return  (0);
905	}
906	return (1);
907}
908
909/*
910 * FALC54 interrupt handling
911 */
912static void
913f54_intr(struct softc *sc)
914{
915	unsigned g, u, s;
916
917	g = sc->f54r->gis;
918	u = sc->f54r->isr0 << 24;
919	u |= sc->f54r->isr1 << 16;
920	u |= sc->f54r->isr2 <<  8;
921	u |= sc->f54r->isr3;
922	sc->falc_irq = u;
923	/* don't chat about the 1 sec heart beat */
924	if (u & ~0x40) {
925#if 0
926		printf("%s*: FALC54 IRQ GIS:%02x %b\n", sc->name, g, u, "\20"
927		    "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF"
928		    "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR"
929		    "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA"
930		    "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP");
931#endif
932		s = sc->f54r->frs0 << 24;
933		s |= sc->f54r->frs1 << 16;
934		s |= sc->f54r->rsw <<  8;
935		s |= sc->f54r->rsp;
936		sc->falc_state = s;
937
938		s &= ~0x01844038;	/* undefined or static bits */
939		s &= ~0x00009fc7;	/* bits we don't care about */
940		s &= ~0x00780000;	/* XXX: TS16 related */
941		s &= ~0x06000000;	/* XXX: Multiframe related */
942#if 0
943		printf("%s*: FALC54 Status %b\n", sc->name, s, "\20"
944		    "\40LOS\37AIS\36LFA\35RRA\34AUXP\33NMF\32LMFA\31frs0.0"
945		    "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS\24TS16LFA\23frs1.2\22XLS\21XLO"
946		    "\20RS1\17rsw.6\16RRA\15RY0\14RY1\13RY2\12RY3\11RY4"
947		    "\10SI1\7SI2\6rsp.5\5rsp.4\4rsp.3\3RSIF\2RS13\1RS15");
948#endif
949		if (s != sc->framer_state) {
950#if 0
951			for (i = 0; i < M32_CHAN; i++) {
952				if (!sc->ch[i])
953					continue;
954			        sp = &sc->ch[i]->ifsppp;
955				if (!(sp->pp_if.if_flags & IFF_UP))
956					continue;
957				if (s)
958					timeout((timeout_t *)sp->pp_down, sp, 1 * hz);
959				else
960					timeout((timeout_t *)sp->pp_up, sp, 1 * hz);
961			}
962#endif
963			sc->framer_state = s;
964		}
965	}
966	/* Once per second check error counters */
967	/* XXX: not clear if this is actually ok */
968	if (!(u & 0x40))
969		return;
970	sc->cnt_fec  += sc->f54r->fec;
971	sc->cnt_cvc  += sc->f54r->cvc;
972	sc->cnt_cec1 += sc->f54r->cec1;
973	sc->cnt_ebc  += sc->f54r->ebc;
974	sc->cnt_cec2 += sc->f54r->cec2;
975	sc->cnt_cec3 += sc->f54r->cec3;
976	sc->cnt_rbc  += sc->f54r->rbc;
977}
978
979/*
980 * Transmit interrupt for one channel
981 */
982static void
983mn_tx_intr(struct softc *sc, u_int32_t vector)
984{
985	u_int32_t chan;
986	struct trxd *dp;
987	struct mbuf *m;
988
989	chan = vector & 0x1f;
990	if (!sc->ch[chan])
991		return;
992	if (sc->ch[chan]->state != UP) {
993		printf("%s: tx_intr when not UP\n", sc->name);
994		return;
995	}
996	for (;;) {
997		dp = sc->ch[chan]->x1;
998		if (vtophys(dp) == sc->m32_mem.ctxd[chan])
999			return;
1000		m = dp->m;
1001		if (m) {
1002#if 0
1003			printf("%d = %d - %d (%p)\n",
1004			    sc->ch[chan]->tx_pending - m->m_pkthdr.len,
1005			    sc->ch[chan]->tx_pending , m->m_pkthdr.len, m);
1006#endif
1007			sc->ch[chan]->tx_pending -= m->m_pkthdr.len;
1008			m_freem(m);
1009		}
1010		sc->ch[chan]->last_xmit = time_second;
1011		sc->ch[chan]->x1 = dp->vnext;
1012		mn_free_desc(dp);
1013	}
1014}
1015
1016/*
1017 * Receive interrupt for one channel
1018 */
1019static void
1020mn_rx_intr(struct softc *sc, u_int32_t vector)
1021{
1022	u_int32_t chan, err;
1023	struct trxd *dp;
1024	struct mbuf *m;
1025	struct schan *sch;
1026
1027	chan = vector & 0x1f;
1028	if (!sc->ch[chan])
1029		return;
1030	sch = sc->ch[chan];
1031	if (sch->state != UP) {
1032		printf("%s: rx_intr when not UP\n", sc->name);
1033		return;
1034	}
1035	vector &= ~0x1f;
1036	if (vector == 0x30000b00)
1037		sch->rx_error++;
1038	for (;;) {
1039		dp = sch->r1;
1040		if (vtophys(dp) == sc->m32_mem.crxd[chan])
1041			return;
1042		m = dp->m;
1043		dp->m = 0;
1044		m->m_pkthdr.len = m->m_len = (dp->status >> 16) & 0x1fff;
1045		err = (dp->status >> 8) & 0xff;
1046		if (!err) {
1047			ng_queue_data(sch->hook, m, NULL);
1048			sch->last_recv = time_second;
1049			m = 0;
1050			/* we could be down by now... */
1051			if (sch->state != UP)
1052				return;
1053		} else if (err & 0x40) {
1054			sch->short_error++;
1055		} else if (err & 0x10) {
1056			sch->crc_error++;
1057		} else if (err & 0x08) {
1058			sch->dribble_error++;
1059		} else if (err & 0x04) {
1060			sch->long_error++;
1061		} else if (err & 0x02) {
1062			sch->abort_error++;
1063		} else if (err & 0x01) {
1064			sch->overflow_error++;
1065		}
1066		if (err) {
1067			sch->last_rxerr = time_second;
1068			sch->prev_error = sch->last_error;
1069			sch->last_error = err;
1070		}
1071
1072		sc->ch[chan]->r1 = dp->vnext;
1073
1074		/* Replenish desc + mbuf supplies */
1075		if (!m) {
1076			MGETHDR(m, M_DONTWAIT, MT_DATA);
1077			if (m == NULL) {
1078				mn_free_desc(dp);
1079				return;
1080			}
1081			MCLGET(m, M_DONTWAIT);
1082			if((m->m_flags & M_EXT) == 0) {
1083				mn_free_desc(dp);
1084				return;
1085			}
1086		}
1087		dp->m = m;
1088		dp->data = vtophys(m->m_data);
1089		dp->flags = 0x40000000;
1090		dp->flags += 1600 << 16;
1091		dp->next = vtophys(dp);
1092		dp->vnext = 0;
1093		sc->ch[chan]->rl->next = vtophys(dp);
1094		sc->ch[chan]->rl->vnext = dp;
1095		sc->ch[chan]->rl->flags &= ~0x40000000;
1096		sc->ch[chan]->rl = dp;
1097	}
1098}
1099
1100
1101/*
1102 * Interupt handler
1103 */
1104
1105static void
1106mn_intr(void *xsc)
1107{
1108	struct softc *sc;
1109	u_int32_t stat, lstat, u;
1110	int i, j;
1111
1112	sc = xsc;
1113	stat =  sc->m32x->stat;
1114	lstat =  sc->m32x->lstat;
1115#if 0
1116	if (!stat && !(lstat & 2))
1117		return;
1118#endif
1119
1120	if (stat & ~0xc200) {
1121		printf("%s: I stat=%08x lstat=%08x\n", sc->name, stat, lstat);
1122	}
1123
1124	if ((stat & 0x200) || (lstat & 2))
1125		f54_intr(sc);
1126
1127	for (j = i = 0; i < 64; i ++) {
1128		u = sc->riqb[i];
1129		if (u) {
1130			sc->riqb[i] = 0;
1131			mn_rx_intr(sc, u);
1132			if ((u & ~0x1f) == 0x30000800 || (u & ~0x1f) == 0x30000b00)
1133				continue;
1134			u &= ~0x30000400;	/* bits we don't care about */
1135			if ((u & ~0x1f) == 0x00000900)
1136				continue;
1137			if (!(u & ~0x1f))
1138				continue;
1139			if (!j)
1140				printf("%s*: RIQB:", sc->name);
1141			printf(" [%d]=%08x", i, u);
1142			j++;
1143		}
1144	}
1145	if (j)
1146	    printf("\n");
1147
1148	for (j = i = 0; i < 64; i ++) {
1149		u = sc->tiqb[i];
1150		if (u) {
1151			sc->tiqb[i] = 0;
1152			mn_tx_intr(sc, u);
1153			if ((u & ~0x1f) == 0x20000800)
1154				continue;
1155			u &= ~0x20000000;	/* bits we don't care about */
1156			if (!u)
1157				continue;
1158			if (!j)
1159				printf("%s*: TIQB:", sc->name);
1160			printf(" [%d]=%08x", i, u);
1161			j++;
1162		}
1163	}
1164	if (j)
1165		printf("\n");
1166	sc->m32x->stat = stat;
1167}
1168
1169static void
1170mn_timeout(void *xsc)
1171{
1172	static int round = 0;
1173	struct softc *sc;
1174
1175	mn_intr(xsc);
1176	sc = xsc;
1177	timeout(mn_timeout, xsc, 10 * hz);
1178	round++;
1179	if (round == 2) {
1180		sc->m32_mem.ccb = 0x00008004;
1181		sc->m32x->cmd = 0x1;
1182	} else if (round > 2) {
1183		printf("%s: timeout\n", sc->name);
1184	}
1185}
1186
1187/*
1188 * PCI initialization stuff
1189 */
1190
1191static struct pci_device mn_device = {
1192	"mn",
1193	mn_probe,
1194	mn_attach,
1195	&mn_count,
1196	NULL
1197};
1198
1199#ifdef COMPAT_PCI_DRIVER
1200COMPAT_PCI_DRIVER(ti, mn_device);
1201#else
1202DATA_SET(pcidevice_set, mn_device);
1203#endif /* COMPAT_PCI_DRIVER */
1204
1205static const char*
1206mn_probe (pcici_t tag, pcidi_t typea)
1207{
1208	u_int id = pci_conf_read(tag, PCI_ID_REG);
1209
1210	if (sizeof (struct m32xreg) != 256) {
1211		printf("MN: sizeof(struct m32xreg) = %d, should have been 256\n", sizeof (struct m32xreg));
1212		return (0);
1213	}
1214	if (sizeof (struct f54rreg) != 128) {
1215		printf("MN: sizeof(struct f54rreg) = %d, should have been 128\n", sizeof (struct f54rreg));
1216		return (0);
1217	}
1218	if (sizeof (struct f54wreg) != 128) {
1219		printf("MN: sizeof(struct f54wreg) = %d, should have been 128\n", sizeof (struct f54wreg));
1220		return (0);
1221	}
1222
1223	if (id == 0x2101110a)
1224		return "Munich32X E1/T1 HDLC Controller";
1225
1226	return 0;
1227}
1228
1229static void
1230mn_attach (pcici_t tag, int unit)
1231{
1232	struct softc *sc;
1233	u_int32_t u;
1234	u_int32_t pci_class;
1235	static int once;
1236
1237	if (!once) {
1238		if (ng_newtype(&mntypestruct))
1239			printf("ng_newtype failed\n");
1240		once++;
1241	}
1242
1243	sc = (struct softc *)malloc(sizeof *sc, M_MN, M_WAITOK);
1244	softc[unit] = sc;
1245	bzero(sc, sizeof *sc);
1246
1247	sc->tag = tag;
1248	sc->unit = unit;
1249	sprintf(sc->name, "mn%d", unit);
1250
1251	if (!pci_map_int(tag, mn_intr, sc, &net_imask)) {
1252		printf("mn%d: could not map interrupt\n", sc->unit);
1253		return;
1254	}
1255	pci_map_mem(tag, PCI_MAP_REG_START, &sc->m0v, &sc->m0p);
1256	pci_map_mem(tag, PCI_MAP_REG_START + 4, &sc->m1v, &sc->m1p);
1257
1258	u = pci_conf_read(tag, PCIR_COMMAND);
1259	pci_conf_write(tag, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
1260	pci_conf_write(tag, PCIR_COMMAND, 0x02800046);
1261
1262	pci_class = pci_conf_read(tag, PCI_CLASS_REG);
1263
1264	sc->m32x = (struct m32xreg *) sc->m0v;
1265	sc->f54w = (struct f54wreg *) sc->m1v;
1266	sc->f54r = (struct f54rreg *) sc->m1v;
1267
1268	/* We must reset before poking at FALC54 registers */
1269	u = mn_reset(sc);
1270	if (!u)
1271		return;
1272
1273	printf("mn%d: Munich32X", sc->unit);
1274	switch (pci_class & 0xff) {
1275	case 0x13:
1276		printf(" Rev 1.3");
1277		break;
1278	default:
1279		printf(" Rev 0x%x\n", pci_class & 0xff);
1280	}
1281	printf(", Falc54");
1282	switch (sc->f54r->vstr) {
1283	case 0:
1284		printf(" Rev < 1.3\n");
1285		break;
1286	case 1:
1287		printf(" Rev 1.3\n");
1288		break;
1289	case 2:
1290		printf(" Rev 1.4\n");
1291		break;
1292	case 0x10:
1293		printf("-LH Rev 1.1\n");
1294		break;
1295	default:
1296		printf(" Rev 0x%x\n", sc->f54r->vstr);
1297	}
1298
1299	if (ng_make_node_common(&mntypestruct, &sc->node) != 0) {
1300		printf("ng_make_node_common failed\n");
1301		return;
1302	}
1303	sc->node->private = sc;
1304	sprintf(sc->nodename, "%s%d", NG_MN_NODE_TYPE, sc->unit);
1305	if (ng_name_node(sc->node, sc->nodename)) {
1306		ng_rmnode(sc->node);
1307		ng_unref(sc->node);
1308		return;
1309	}
1310
1311	return;
1312}
1313#endif /* _KERNEL */
1314