if_mn.c revision 55088
1/* 2 * ---------------------------------------------------------------------------- 3 * "THE BEER-WARE LICENSE" (Revision 42): 4 * <phk@FreeBSD.org> wrote this file. As long as you retain this notice you 5 * can do whatever you want with this stuff. If we meet some day, and you think 6 * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp 7 * ---------------------------------------------------------------------------- 8 * 9 * $Id: if_mn.c,v 1.1 1999/02/01 13:06:40 phk Exp $ 10 * 11 * Driver for Siemens reference design card "Easy321-R1". 12 * 13 * This card contains a FALC54 E1/T1 framer and a MUNICH32X 32-channel HDLC 14 * controller. 15 * 16 * The driver support E1 mode with up to 31 channels. We send CRC4 but don't 17 * check it coming in. 18 * 19 * The FALC54 and MUNICH32X have far too many registers and weird modes for 20 * comfort, so I have not bothered typing it all into a "fooreg.h" file, 21 * you will (badly!) need the documentation anyway if you want to mess with 22 * this gadget. 23 * 24 * $FreeBSD: head/sys/pci/if_mn.c 55088 1999-12-24 15:16:10Z bde $ 25 */ 26 27/* 28 * Stuff to describe the MUNIC32X and FALC54 chips. 29 */ 30 31#define M32_CHAN 32 /* We have 32 channels */ 32#define M32_TS 32 /* We have 32 timeslots */ 33 34#define NG_MN_NODE_TYPE "mn" 35#define NG_MN_COOKIKE 941432500 36 37#define MN_MAGIC 0x4d6e0000 38 39#define MN_GET (MN_MAGIC | 0x1) 40#define MN_SET (MN_MAGIC | 0x2) 41#define MN_DEBUG (MN_MAGIC | 0x3) 42 43struct mn_control { 44 int cmd; 45 char name[8]; 46 unsigned chan; 47 unsigned ts[M32_CHAN]; 48}; 49 50#ifdef KERNEL 51#define PPP_HEADER_LEN 4 /* XXX: should live in some header somewhere */ 52 53#include <sys/param.h> 54#include <sys/systm.h> 55#include <sys/conf.h> 56#include <sys/mbuf.h> 57#include <sys/kernel.h> 58#include <sys/malloc.h> 59#include <sys/socket.h> 60#include <sys/sockio.h> 61#include <pci/pcireg.h> 62#include <pci/pcivar.h> 63#include <vm/vm.h> 64#include <vm/pmap.h> 65#include <machine/clock.h> 66 67#include <netgraph/ng_message.h> 68#include <netgraph/ng_sample.h> 69#include <netgraph/netgraph.h> 70 71#ifndef NMN 72/* Most machines don't support more than 4 busmaster PCI slots, if even that many */ 73#define NMN 4 74#endif 75 76/* From: PEB 20321 data sheet, p187, table 22 */ 77struct m32xreg { 78 u_int32_t conf, cmd, stat, imask; 79 u_int32_t fill10, piqba, piql, fill1c; 80 u_int32_t mode1, mode2, ccba, txpoll; 81 u_int32_t tiqba, tiql, riqba, riql; 82 u_int32_t lconf, lccba, fill48, ltran; 83 u_int32_t ltiqba, ltiql, lriqba, lriql; 84 u_int32_t lreg0, lreg1, lreg2, lreg3; 85 u_int32_t lreg4, lreg5, lre6, lstat; 86 u_int32_t gpdir, gpdata, gpod, fill8c; 87 u_int32_t ssccon, sscbr, ssctb, sscrb; 88 u_int32_t ssccse, sscim, fillab, fillac; 89 u_int32_t iomcon1, iomcon2, iomstat, fillbc; 90 u_int32_t iomcit0, iomcit1, iomcir0, iomcir1; 91 u_int32_t iomtmo, iomrmo, filld8, filldc; 92 u_int32_t mbcmd, mbdata1, mbdata2, mbdata3; 93 u_int32_t mbdata4, mbdata5, mbdata6, mbdata7; 94}; 95 96/* From: PEB 2254 data sheet, p80, table 10 */ 97struct f54wreg { 98 u_int16_t xfifo; 99 u_int8_t cmdr, mode, rah1, rah2, ral1, ral2; 100 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 101 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 102 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 103 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 104 u_int8_t test1, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr3; 105 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 106 u_int8_t lim2, fill39[7]; 107 u_int8_t fill40[8]; 108 u_int8_t fill48[8]; 109 u_int8_t fill50[8]; 110 u_int8_t fill58[8]; 111 u_int8_t dec, fill61, test2, fill63[5]; 112 u_int8_t fill68[8]; 113 u_int8_t xs[16]; 114}; 115 116/* From: PEB 2254 data sheet, p117, table 10 */ 117struct f54rreg { 118 u_int16_t rfifo; 119 u_int8_t fill2, mode, rah1, rah2, ral1, ral2; 120 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 121 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 122 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 123 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 124 u_int8_t test, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr13; 125 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 126 u_int8_t lim2, fill39[7]; 127 u_int8_t fill40[8]; 128 u_int8_t fill48[4], frs0, frs1, rsw, rsp; 129 u_int16_t fec, cvc, cec1, ebc; 130 u_int16_t cec2, cec3; 131 u_int8_t rsa4, rsa5, rsa6, rsa7; 132 u_int8_t rsa8, rsa6s, tsr0, tsr1, sis, rsis; 133 u_int16_t rbc; 134 u_int8_t isr0, isr1, isr2, isr3, fill6c, fill6d, gis, vstr; 135 u_int8_t rs[16]; 136}; 137 138/* Transmit & receive descriptors */ 139struct trxd { 140 u_int32_t flags; 141 vm_offset_t next; 142 vm_offset_t data; 143 u_int32_t status; /* only used for receive */ 144 struct mbuf *m; /* software use only */ 145 struct trxd *vnext; /* software use only */ 146}; 147 148/* Channel specification */ 149struct cspec { 150 u_int32_t flags; 151 vm_offset_t rdesc; 152 vm_offset_t tdesc; 153 u_int32_t itbs; 154}; 155 156struct m32_mem { 157 vm_offset_t csa; 158 u_int32_t ccb; 159 u_int32_t reserve1[2]; 160 u_int32_t ts[M32_TS]; 161 struct cspec cs[M32_CHAN]; 162 vm_offset_t crxd[M32_CHAN]; 163 vm_offset_t ctxd[M32_CHAN]; 164}; 165 166struct softc; 167struct sockaddr; 168struct rtentry; 169 170static const char* mn_probe (pcici_t tag, pcidi_t type); 171static void mn_attach (pcici_t tag, int unit); 172static u_long mn_count; 173static void mn_create_channel(struct softc *sc, int chan); 174static int mn_reset(struct softc *sc); 175static struct trxd * mn_alloc_desc(void); 176static void mn_free_desc(struct trxd *dp); 177static void mn_intr(void *xsc); 178static u_int32_t mn_parse_ts(const char *s); 179#ifdef notyet 180static void m32_dump(struct softc *sc); 181static void f54_dump(struct softc *sc); 182static void mn_fmt_ts(char *p, u_int32_t ts); 183#endif /* notyet */ 184 185static ng_constructor_t ngmn_constructor; 186static ng_rcvmsg_t ngmn_rcvmsg; 187static ng_shutdown_t ngmn_shutdown; 188static ng_newhook_t ngmn_newhook; 189static ng_connect_t ngmn_connect; 190static ng_rcvdata_t ngmn_rcvdata; 191static ng_disconnect_t ngmn_disconnect; 192 193static struct ng_type mntypestruct = { 194 NG_VERSION, 195 NG_MN_NODE_TYPE, 196 NULL, 197 ngmn_constructor, 198 ngmn_rcvmsg, 199 ngmn_shutdown, 200 ngmn_newhook, 201 NULL, 202 ngmn_connect, 203 ngmn_rcvdata, 204 ngmn_rcvdata, 205 ngmn_disconnect, 206 NULL 207}; 208 209static MALLOC_DEFINE(M_MN, "mn", "Mx driver related"); 210 211#define NIQB 64 212 213struct softc; 214 215struct schan { 216 enum {DOWN, UP} state; 217 struct softc *sc; 218 int chan; 219 u_int32_t ts; 220 char name[8]; 221 struct trxd *r1, *rl; 222 struct trxd *x1, *xl; 223 hook_p hook; 224 225 time_t last_recv; 226 time_t last_rxerr; 227 time_t last_xmit; 228 229 u_long rx_error; 230 231 u_long short_error; 232 u_long crc_error; 233 u_long dribble_error; 234 u_long long_error; 235 u_long abort_error; 236 u_long overflow_error; 237 238 int last_error; 239 int prev_error; 240}; 241 242static struct softc { 243 int unit; 244 pcici_t tag; 245 vm_offset_t m0v, m0p, m1v, m1p; 246 struct m32xreg *m32x; 247 struct f54wreg *f54w; 248 struct f54rreg *f54r; 249 struct m32_mem m32_mem; 250 u_int32_t tiqb[NIQB]; 251 u_int32_t riqb[NIQB]; 252 u_int32_t piqb[NIQB]; 253 u_int32_t ltiqb[NIQB]; 254 u_int32_t lriqb[NIQB]; 255 char name[8]; 256 u_int32_t falc_irq, falc_state, framer_state; 257 struct schan *ch[M32_CHAN]; 258 char nodename[NG_NODELEN + 1]; 259 node_p node; 260 261 u_long cnt_fec; 262 u_long cnt_cvc; 263 u_long cnt_cec1; 264 u_long cnt_ebc; 265 u_long cnt_cec2; 266 u_long cnt_cec3; 267 u_long cnt_rbc; 268} *softc[NMN]; 269 270static int 271ngmn_constructor(node_p *nodep) 272{ 273 274 return (EINVAL); 275} 276 277static int 278ngmn_shutdown(node_p nodep) 279{ 280 281 return (EINVAL); 282} 283 284static int 285ngmn_rcvmsg(node_p node, struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp) 286{ 287 struct softc *sc; 288 struct schan *sch; 289 char *arg; 290 int pos, i; 291 292 sc = node->private; 293 294 if (msg->header.typecookie != NGM_GENERIC_COOKIE || 295 msg->header.cmd != NGM_TEXT_STATUS) { 296 if (resp) 297 *resp = NULL; 298 FREE(msg, M_NETGRAPH); 299 return (EINVAL); 300 } 301 NG_MKRESPONSE(*resp, msg, sizeof(struct ng_mesg) + NG_TEXTRESPONSE, 302 M_NOWAIT); 303 if (*resp == NULL) { 304 FREE(msg, M_NETGRAPH); 305 return (ENOMEM); 306 } 307 arg = (char *)(*resp)->data; 308 pos = 0; 309 pos += sprintf(pos + arg,"Framer status %b;\n", sc->framer_state, "\20" 310 "\40LOS\37AIS\36LFA\35RRA" 311 "\34AUXP\33NMF\32LMFA\31frs0.0" 312 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 313 "\24TS16LFA\23frs1.2\22XLS\21XLO" 314 "\20RS1\17rsw.6\16RRA\15RY0" 315 "\14RY1\13RY2\12RY3\11RY4" 316 "\10SI1\7SI2\6rsp.5\5rsp.4" 317 "\4rsp.3\3RSIF\2RS13\1RS15"); 318 pos += sprintf(pos + arg," Framing errors: %lu", sc->cnt_fec); 319 pos += sprintf(pos + arg," Code Violations: %lu\n", sc->cnt_cvc); 320 321 pos += sprintf(pos + arg," Falc State %b;\n", sc->falc_state, "\20" 322 "\40LOS\37AIS\36LFA\35RRA" 323 "\34AUXP\33NMF\32LMFA\31frs0.0" 324 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 325 "\24TS16LFA\23frs1.2\22XLS\21XLO" 326 "\20RS1\17rsw.6\16RRA\15RY0" 327 "\14RY1\13RY2\12RY3\11RY4" 328 "\10SI1\7SI2\6rsp.5\5rsp.4" 329 "\4rsp.3\3RSIF\2RS13\1RS15"); 330 pos += sprintf(pos + arg, " Falc IRQ %b\n", sc->falc_irq, "\20" 331 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 332 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 333 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 334 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 335 for (i = 0; i < M32_CHAN; i++) { 336 if (!sc->ch[i]) 337 continue; 338 sch = sc->ch[i]; 339 340 pos += sprintf(arg + pos, " Chan %d <%s> ", 341 i, sch->hook->name); 342 343 pos += sprintf(arg + pos, " Last Rx: "); 344 if (sch->last_recv) 345 pos += sprintf(arg + pos, "%lu s", time_second - sch->last_recv); 346 else 347 pos += sprintf(arg + pos, "never"); 348 349 pos += sprintf(arg + pos, ", last RxErr: "); 350 if (sch->last_rxerr) 351 pos += sprintf(arg + pos, "%lu s", time_second - sch->last_rxerr); 352 else 353 pos += sprintf(arg + pos, "never"); 354 355 pos += sprintf(arg + pos, ", last Tx: "); 356 if (sch->last_xmit) 357 pos += sprintf(arg + pos, "%lu s\n", time_second - sch->last_xmit); 358 else 359 pos += sprintf(arg + pos, "never\n"); 360 361 pos += sprintf(arg + pos, " RX error(s) %lu", sch->rx_error); 362 pos += sprintf(arg + pos, " Short: %lu", sch->short_error); 363 pos += sprintf(arg + pos, " CRC: %lu", sch->crc_error); 364 pos += sprintf(arg + pos, " Mod8: %lu", sch->dribble_error); 365 pos += sprintf(arg + pos, " Long: %lu", sch->long_error); 366 pos += sprintf(arg + pos, " Abort: %lu", sch->abort_error); 367 pos += sprintf(arg + pos, " Overflow: %lu\n", sch->overflow_error); 368 369 pos += sprintf(arg + pos, " Last error: %b Prev error: %b\n", 370 sch->last_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN", 371 sch->prev_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN"); 372 } 373 (*resp)->header.arglen = pos + 1; 374 FREE(msg, M_NETGRAPH); 375 return (0); 376} 377 378static int 379ngmn_newhook(node_p node, hook_p hook, const char *name) 380{ 381 u_int32_t ts, chan; 382 struct softc *sc; 383 384 sc = node->private; 385 386 if (name[0] != 't' || name[1] != 's') 387 return (EINVAL); 388 389 ts = mn_parse_ts(name + 2); 390 if (ts == 0) 391 return (EINVAL); 392 chan = ffs(ts) - 1; 393 if (sc->ch[chan]) 394 return (EBUSY); 395 mn_create_channel(sc, chan); /* Create the first channel */ 396 sc->ch[chan]->ts = ts; 397 sc->ch[chan]->hook = hook; 398 hook->private = sc->ch[chan]; 399 return(0); 400} 401 402 403static struct trxd *mn_desc_free; 404 405static struct trxd * 406mn_alloc_desc(void) 407{ 408 struct trxd *dp; 409 410 dp = mn_desc_free; 411 if (dp) 412 mn_desc_free = dp->vnext; 413 else 414 dp = (struct trxd *)malloc(sizeof *dp, M_MN, M_NOWAIT); 415 return (dp); 416} 417 418static void 419mn_free_desc(struct trxd *dp) 420{ 421 dp->vnext = mn_desc_free; 422 mn_desc_free = dp; 423} 424 425static u_int32_t 426mn_parse_ts(const char *s) 427{ 428 unsigned r; 429 int i, j; 430 char *p; 431 432 r = 0; 433 j = 0; 434 while(*s) { 435 i = strtol(s, &p, 0); 436 if (i < 1 || i > 31) 437 return (0); 438 while (j && j < i) { 439 r |= 1 << j++; 440 } 441 j = 0; 442 r |= 1 << i; 443 if (*p == ',') { 444 s = p + 1; 445 continue; 446 } else if (*p == '-') { 447 j = i; 448 s = p + 1; 449 continue; 450 } else if (!*p) { 451 break; 452 } else { 453 return (0); 454 } 455 } 456 return (r); 457} 458 459#ifdef notyet 460static void 461mn_fmt_ts(char *p, u_int32_t ts) 462{ 463 char *s; 464 int j; 465 466 s = ""; 467 ts &= 0xfffffffe; 468 for (j = 1; j < 32; j++) { 469 if (!(ts & (1 << j))) 470 continue; 471 sprintf(p, "%s%d", s, j); 472 p += strlen(p); 473 s = ","; 474 if (!(ts & (1 << (j+1)))) 475 continue; 476 for (; j < 32; j++) 477 if (!(ts & (1 << (j+1)))) 478 break; 479 sprintf(p, "-%d", j); 480 p += strlen(p); 481 s = ","; 482 } 483} 484#endif /* notyet */ 485 486/* 487 * OUTPUT 488 */ 489 490static int 491ngmn_rcvdata(hook_p hook, struct mbuf *m, meta_p meta) 492{ 493 struct mbuf *m2; 494 struct trxd *dp, *dp2; 495 struct schan *sch; 496 struct softc *sc; 497 int chan, pitch, len; 498 499 sch = hook->private; 500 sc = sch->sc; 501 chan = sch->chan; 502 503 if (sc->ch[chan]->state != UP) { 504 NG_FREE_DATA(m, meta); 505 return (0); 506 } 507 NG_FREE_META(meta); 508 pitch = 0; 509 m2 = m; 510 dp2 = sc->ch[chan]->xl; 511 len = m->m_pkthdr.len; 512 while (len) { 513 dp = mn_alloc_desc(); 514 if (!dp) { 515 pitch++; 516 m_freem(m); 517 sc->ch[chan]->xl = dp2; 518 dp = dp2->vnext; 519 while (dp) { 520 dp2 = dp->vnext; 521 mn_free_desc(dp); 522 dp = dp2; 523 } 524 sc->ch[chan]->xl->vnext = 0; 525 break; 526 } 527 dp->data = vtophys(m2->m_data); 528 dp->flags = m2->m_len << 16; 529 dp->flags += 1; 530 len -= m2->m_len; 531 dp->next = vtophys(dp); 532 dp->vnext = 0; 533 sc->ch[chan]->xl->next = vtophys(dp); 534 sc->ch[chan]->xl->vnext = dp; 535 sc->ch[chan]->xl = dp; 536 if (!len) { 537 dp->m = m; 538 dp->flags |= 0xc0000000; 539 dp2->flags &= ~0x40000000; 540 } else { 541 dp->m = 0; 542 m2 = m2->m_next; 543 } 544 } 545 if (pitch) 546 printf("%s%d: Short on mem, pitched %d packets\n", 547 sc->name, chan, pitch); 548 return (0); 549} 550 551/* 552 * OPEN 553 */ 554static int 555ngmn_connect(hook_p hook) 556{ 557 int i, nts, chan; 558 struct trxd *dp, *dp2; 559 struct mbuf *m; 560 struct softc *sc; 561 struct schan *sch; 562 u_int32_t u; 563 564 sch = hook->private; 565 chan = sch->chan; 566 sc = sch->sc; 567 568 printf("%s: OPEN{ state = %d\n", sch->name, sch->state); 569 if (sch->state == UP) 570 return (0); 571 sch->state = UP; 572 573 /* Count and configure the timeslots for this channel */ 574 for (nts = i = 0; i < 32; i++) 575 if (sch->ts & (1 << i)) { 576 sc->m32_mem.ts[i] = 0x00ff00ff | 577 (chan << 24) | (chan << 8); 578 nts++; 579 } 580 581 /* Init the receiver & xmitter to HDLC */ 582 sc->m32_mem.cs[chan].flags = 0x80e90006; 583 /* Allocate two buffers per timeslot */ 584 sc->m32_mem.cs[chan].itbs = nts * 2; 585 586 /* Setup a transmit chain with one descriptor */ 587 /* XXX: we actually send a 1 byte packet */ 588 dp = mn_alloc_desc(); 589 MGETHDR(m, M_WAIT, MT_DATA); 590 dp->m = m; 591 dp->flags = 0xc0000000 + (1 << 16); 592 dp->next = vtophys(dp); 593 dp->vnext = 0; 594 dp->data = vtophys(sc->name); 595 sc->m32_mem.cs[chan].tdesc = vtophys(dp); 596 sc->ch[chan]->x1 = dp; 597 sc->ch[chan]->xl = dp; 598 599 /* Setup a receive chain with 5 + NTS descriptors */ 600 601 dp = mn_alloc_desc(); 602 MGETHDR(m, M_WAIT, MT_DATA); 603 MCLGET(m, M_WAIT); 604 dp->m = m; 605 dp->data = vtophys(m->m_data); 606 dp->flags = 0x40000000; 607 dp->flags += 1600 << 16; 608 dp->next = vtophys(dp); 609 dp->vnext = 0; 610 sc->ch[chan]->rl = dp; 611 612 for (i = 0; i < (nts + 10); i++) { 613 dp2 = dp; 614 dp = mn_alloc_desc(); 615 MGETHDR(m, M_WAIT, MT_DATA); 616 MCLGET(m, M_WAIT); 617 dp->m = m; 618 dp->data = vtophys(m->m_data); 619 dp->flags = 0x00000000; 620 dp->flags += 1600 << 16; 621 dp->next = vtophys(dp2); 622 dp->vnext = dp2; 623 } 624 sc->m32_mem.cs[chan].rdesc = vtophys(dp); 625 sc->ch[chan]->r1 = dp; 626 627 /* Initialize this channel */ 628 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 629 sc->m32x->cmd = 0x1; 630 DELAY(30); 631 u = sc->m32x->stat; 632 if (!(u & 1)) 633 printf("%s: init chan %d stat %08x\n", sc->name, chan, u); 634 sc->m32x->stat = 1; 635 636 printf("%s%d: TLS} state = %d\n", sc->name, chan, sc->ch[chan]->state); 637 return (0); 638} 639 640/* 641 * CLOSE 642 */ 643static int 644ngmn_disconnect(hook_p hook) 645{ 646 int chan, i; 647 struct softc *sc; 648 struct schan *sch; 649 struct trxd *dp, *dp2; 650 u_int32_t u; 651 652 sch = hook->private; 653 chan = sch->chan; 654 sc = sch->sc; 655 656 printf("%s: TLF{ state = %d\n", sch->name, sch->state); 657 if (sch->state == DOWN) 658 return (0); 659 sch->state = DOWN; 660 661 /* Set receiver & transmitter off */ 662 sc->m32_mem.cs[chan].flags = 0x80920006; 663 sc->m32_mem.cs[chan].itbs = 0; 664 665 /* free the timeslots */ 666 for (i = 0; i < 32; i++) 667 if (sc->ch[chan]->ts & (1 << i)) 668 sc->m32_mem.ts[i] = 0x20002000; 669 670 /* Initialize this channel */ 671 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 672 sc->m32x->cmd = 0x1; 673 DELAY(30); 674 u = sc->m32x->stat; 675 if (!(u & 1)) 676 printf("%s: zap chan %d stat %08x\n", sc->name, chan, u); 677 sc->m32x->stat = 1; 678 679 /* Free all receive descriptors and mbufs */ 680 for (dp = sc->ch[chan]->r1; dp ; dp = dp2) { 681 if (dp->m) 682 m_freem(dp->m); 683 sc->ch[chan]->r1 = dp2 = dp->vnext; 684 mn_free_desc(dp); 685 } 686 687 /* Free all transmit descriptors and mbufs */ 688 for (dp = sc->ch[chan]->x1; dp ; dp = dp2) { 689 if (dp->m) 690 m_freem(dp->m); 691 sc->ch[chan]->x1 = dp2 = dp->vnext; 692 mn_free_desc(dp); 693 } 694 printf("%s%d: TLF} state = %d\n", sc->name, chan, sc->ch[chan]->state); 695 return(0); 696} 697 698/* 699 * Create a new channel. 700 */ 701static void 702mn_create_channel(struct softc *sc, int chan) 703{ 704 struct schan *sch; 705 706 sch = sc->ch[chan] = (struct schan *)malloc(sizeof *sc->ch[chan], 707 M_MN, M_WAITOK); 708 bzero(sch, sizeof *sch); 709 sch->sc = sc; 710 sch->state = DOWN; 711 sch->chan = chan; 712 sprintf(sch->name, "%s%d", sc->name, chan); 713 return; 714} 715 716#ifdef notyet 717/* 718 * Dump Munich32x state 719 */ 720static void 721m32_dump(struct softc *sc) 722{ 723 u_int32_t *tp4; 724 int i, j; 725 726 printf("mn%d: MUNICH32X dump\n", sc->unit); 727 tp4 = (u_int32_t *)sc->m0v; 728 for(j = 0; j < 64; j += 8) { 729 printf("%02x", j * sizeof *tp4); 730 for(i = 0; i < 8; i++) 731 printf(" %08x", tp4[i+j]); 732 printf("\n"); 733 } 734 for(j = 0; j < M32_CHAN; j++) { 735 if (!sc->ch[j]) 736 continue; 737 printf("CH%d: state %d ts %08x", 738 j, sc->ch[j]->state, sc->ch[j]->ts); 739 printf(" %08x %08x %08x %08x %08x %08x\n", 740 sc->m32_mem.cs[j].flags, 741 sc->m32_mem.cs[j].rdesc, 742 sc->m32_mem.cs[j].tdesc, 743 sc->m32_mem.cs[j].itbs, 744 sc->m32_mem.crxd[j], 745 sc->m32_mem.ctxd[j] ); 746 } 747} 748 749/* 750 * Dump Falch54 state 751 */ 752static void 753f54_dump(struct softc *sc) 754{ 755 u_int8_t *tp1; 756 int i, j; 757 758 printf("%s: FALC54 dump\n", sc->name); 759 tp1 = (u_int8_t *)sc->m1v; 760 for(j = 0; j < 128; j += 16) { 761 printf("%s: %02x |", sc->name, j * sizeof *tp1); 762 for(i = 0; i < 16; i++) 763 printf(" %02x", tp1[i+j]); 764 printf("\n"); 765 } 766} 767#endif /* notyet */ 768 769/* 770 * Init Munich32x 771 */ 772static void 773m32_init(struct softc *sc) 774{ 775 776 sc->m32x->conf = 0x00000000; 777 sc->m32x->mode1 = 0x81048000 + 1600; /* XXX: temp */ 778#if 1 779 sc->m32x->mode2 = 0x00000081; 780 sc->m32x->txpoll = 0xffffffff; 781#else 782 sc->m32x->mode2 = 0x00000101; 783#endif 784 sc->m32x->lconf = 0x6060009B; 785 sc->m32x->imask = 0x00000000; 786} 787 788/* 789 * Init the Falc54 790 */ 791static void 792f54_init(struct softc *sc) 793{ 794 sc->f54w->ipc = 0x07; 795 796 sc->f54w->xpm0 = 0xbd; 797 sc->f54w->xpm1 = 0x03; 798 sc->f54w->xpm2 = 0x00; 799 800 sc->f54w->imr0 = 0x18; /* RMB, CASC */ 801 sc->f54w->imr1 = 0x08; /* XMB */ 802 sc->f54w->imr2 = 0x00; 803 sc->f54w->imr3 = 0x38; /* LMFA16, AIS16, RA16 */ 804 sc->f54w->imr4 = 0x00; 805 806 sc->f54w->fmr0 = 0xf0; /* X: HDB3, R: HDB3 */ 807 sc->f54w->fmr1 = 0x0e; /* Send CRC4, 2Mbit, ECM */ 808 sc->f54w->fmr2 = 0x03; /* Auto Rem-Alarm, Auto resync */ 809 810 sc->f54w->lim1 = 0xb0; /* XCLK=8kHz, .62V threshold */ 811 sc->f54w->pcd = 0x0a; 812 sc->f54w->pcr = 0x15; 813 sc->f54w->xsw = 0x9f; /* fmr4 */ 814 sc->f54w->xsp = 0x1c; /* fmr5 */ 815 sc->f54w->xc0 = 0x07; 816 sc->f54w->xc1 = 0x3d; 817 sc->f54w->rc0 = 0x05; 818 sc->f54w->rc1 = 0x00; 819 sc->f54w->cmdr = 0x51; 820} 821 822static int 823mn_reset(struct softc *sc) 824{ 825 u_int32_t u; 826 int i, j; 827 828 u = 0; 829 for(i = 5; i >= 0; i-- ) { 830 sc->m32x->gpdir = i; 831 for (j = 0; j < 8; j ++) { 832 sc->m32x->gpdata = j; 833 u += sc->m32x->gpdata; 834 } 835 } 836 if (u != 0xe4) { 837 printf("mn%d: WARNING: Controller failed to initialize.\n", 838 sc->unit); 839#if 0 840 return (0); 841#endif 842 printf("mn%d: %x\n", sc->unit, u); 843 } 844 845 sc->m32x->ccba = vtophys(&sc->m32_mem.csa); 846 sc->m32_mem.csa = vtophys(&sc->m32_mem.ccb); 847 848 bzero(sc->tiqb, sizeof sc->tiqb); 849 sc->m32x->tiqba = vtophys(&sc->tiqb); 850 sc->m32x->tiql = NIQB / 16 - 1; 851 852 bzero(sc->riqb, sizeof sc->riqb); 853 sc->m32x->riqba = vtophys(&sc->riqb); 854 sc->m32x->riql = NIQB / 16 - 1; 855 856 bzero(sc->ltiqb, sizeof sc->ltiqb); 857 sc->m32x->ltiqba = vtophys(&sc->ltiqb); 858 sc->m32x->ltiql = NIQB / 16 - 1; 859 860 bzero(sc->lriqb, sizeof sc->lriqb); 861 sc->m32x->lriqba = vtophys(&sc->lriqb); 862 sc->m32x->lriql = NIQB / 16 - 1; 863 864 bzero(sc->piqb, sizeof sc->piqb); 865 sc->m32x->piqba = vtophys(&sc->piqb); 866 sc->m32x->piql = NIQB / 16 - 1; 867 868 m32_init(sc); 869 f54_init(sc); 870 871 u = sc->m32x->stat; 872 sc->m32x->stat = u; 873 sc->m32_mem.ccb = 0x4; 874 sc->m32x->cmd = 0x1; 875 DELAY(1000); 876 u = sc->m32x->stat; 877 sc->m32x->stat = u; 878 879 /* set all timeslots to known state */ 880 for (i = 0; i < 32; i++) 881 sc->m32_mem.ts[i] = 0x20002000; 882 883 if (!(u & 1)) { 884 printf( 885"mn%d: WARNING: Controller failed the PCI bus-master test.\n" 886"mn%d: WARNING: Use a PCI slot which can support bus-master cards.\n", 887 sc->unit, sc->unit); 888 return (0); 889 } 890 return (1); 891} 892 893/* 894 * FALC54 interrupt handling 895 */ 896static void 897f54_intr(struct softc *sc) 898{ 899 unsigned g, u, s; 900 901 g = sc->f54r->gis; 902 u = sc->f54r->isr0 << 24; 903 u |= sc->f54r->isr1 << 16; 904 u |= sc->f54r->isr2 << 8; 905 u |= sc->f54r->isr3; 906 sc->falc_irq = u; 907 /* don't chat about the 1 sec heart beat */ 908 if (u & ~0x40) { 909#if 0 910 printf("%s*: FALC54 IRQ GIS:%02x %b\n", sc->name, g, u, "\20" 911 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 912 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 913 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 914 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 915#endif 916 s = sc->f54r->frs0 << 24; 917 s |= sc->f54r->frs1 << 16; 918 s |= sc->f54r->rsw << 8; 919 s |= sc->f54r->rsp; 920 sc->falc_state = s; 921 922 s &= ~0x01844038; /* undefined or static bits */ 923 s &= ~0x00009fc7; /* bits we don't care about */ 924 s &= ~0x00780000; /* XXX: TS16 related */ 925 s &= ~0x06000000; /* XXX: Multiframe related */ 926#if 0 927 printf("%s*: FALC54 Status %b\n", sc->name, s, "\20" 928 "\40LOS\37AIS\36LFA\35RRA\34AUXP\33NMF\32LMFA\31frs0.0" 929 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS\24TS16LFA\23frs1.2\22XLS\21XLO" 930 "\20RS1\17rsw.6\16RRA\15RY0\14RY1\13RY2\12RY3\11RY4" 931 "\10SI1\7SI2\6rsp.5\5rsp.4\4rsp.3\3RSIF\2RS13\1RS15"); 932#endif 933 if (s != sc->framer_state) { 934#if 0 935 for (i = 0; i < M32_CHAN; i++) { 936 if (!sc->ch[i]) 937 continue; 938 sp = &sc->ch[i]->ifsppp; 939 if (!(sp->pp_if.if_flags & IFF_UP)) 940 continue; 941 if (s) 942 timeout((timeout_t *)sp->pp_down, sp, 1 * hz); 943 else 944 timeout((timeout_t *)sp->pp_up, sp, 1 * hz); 945 } 946#endif 947 sc->framer_state = s; 948 } 949 } 950 /* Once per second check error counters */ 951 /* XXX: not clear if this is actually ok */ 952 if (!(u & 0x40)) 953 return; 954 sc->cnt_fec += sc->f54r->fec; 955 sc->cnt_cvc += sc->f54r->cvc; 956 sc->cnt_cec1 += sc->f54r->cec1; 957 sc->cnt_ebc += sc->f54r->ebc; 958 sc->cnt_cec2 += sc->f54r->cec2; 959 sc->cnt_cec3 += sc->f54r->cec3; 960 sc->cnt_rbc += sc->f54r->rbc; 961} 962 963/* 964 * Transmit interrupt for one channel 965 */ 966static void 967mn_tx_intr(struct softc *sc, u_int32_t vector) 968{ 969 u_int32_t chan; 970 struct trxd *dp; 971 struct mbuf *m; 972 973 chan = vector & 0x1f; 974 if (!sc->ch[chan]) 975 return; 976 if (sc->ch[chan]->state != UP) { 977 printf("%s: tx_intr when not UP\n", sc->name); 978 return; 979 } 980 for (;;) { 981 dp = sc->ch[chan]->x1; 982 if (vtophys(dp) == sc->m32_mem.ctxd[chan]) 983 return; 984 m = dp->m; 985 if (m) 986 m_freem(m); 987 sc->ch[chan]->last_xmit = time_second; 988 sc->ch[chan]->x1 = dp->vnext; 989 mn_free_desc(dp); 990 } 991} 992 993/* 994 * Receive interrupt for one channel 995 */ 996static void 997mn_rx_intr(struct softc *sc, u_int32_t vector) 998{ 999 u_int32_t chan, err; 1000 struct trxd *dp; 1001 struct mbuf *m; 1002 struct schan *sch; 1003 1004 chan = vector & 0x1f; 1005 if (!sc->ch[chan]) 1006 return; 1007 sch = sc->ch[chan]; 1008 if (sch->state != UP) { 1009 printf("%s: rx_intr when not UP\n", sc->name); 1010 return; 1011 } 1012 vector &= ~0x1f; 1013 if (vector == 0x30000b00) 1014 sch->rx_error++; 1015 for (;;) { 1016 dp = sch->r1; 1017 if (vtophys(dp) == sc->m32_mem.crxd[chan]) 1018 return; 1019 m = dp->m; 1020 dp->m = 0; 1021 m->m_pkthdr.len = m->m_len = (dp->status >> 16) & 0x1fff; 1022 err = (dp->status >> 8) & 0xff; 1023 if (!err) { 1024 ng_queue_data(sch->hook, m, NULL); 1025 sch->last_recv = time_second; 1026 m = 0; 1027 /* we could be down by now... */ 1028 if (sch->state != UP) 1029 return; 1030 } else if (err & 0x40) { 1031 sch->short_error++; 1032 } else if (err & 0x10) { 1033 sch->crc_error++; 1034 } else if (err & 0x08) { 1035 sch->dribble_error++; 1036 } else if (err & 0x04) { 1037 sch->long_error++; 1038 } else if (err & 0x02) { 1039 sch->abort_error++; 1040 } else if (err & 0x01) { 1041 sch->overflow_error++; 1042 } 1043 if (err) { 1044 sch->last_rxerr = time_second; 1045 sch->prev_error = sch->last_error; 1046 sch->last_error = err; 1047 } 1048 1049 sc->ch[chan]->r1 = dp->vnext; 1050 1051 /* Replenish desc + mbuf supplies */ 1052 if (!m) { 1053 MGETHDR(m, M_DONTWAIT, MT_DATA); 1054 if (m == NULL) { 1055 mn_free_desc(dp); 1056 return; 1057 } 1058 MCLGET(m, M_DONTWAIT); 1059 if((m->m_flags & M_EXT) == 0) { 1060 mn_free_desc(dp); 1061 return; 1062 } 1063 } 1064 dp->m = m; 1065 dp->data = vtophys(m->m_data); 1066 dp->flags = 0x40000000; 1067 dp->flags += 1600 << 16; 1068 dp->next = vtophys(dp); 1069 dp->vnext = 0; 1070 sc->ch[chan]->rl->next = vtophys(dp); 1071 sc->ch[chan]->rl->vnext = dp; 1072 sc->ch[chan]->rl->flags &= ~0x40000000; 1073 sc->ch[chan]->rl = dp; 1074 } 1075} 1076 1077 1078/* 1079 * Interupt handler 1080 */ 1081 1082static void 1083mn_intr(void *xsc) 1084{ 1085 struct softc *sc; 1086 u_int32_t stat, lstat, u; 1087 int i, j; 1088 1089 sc = xsc; 1090 stat = sc->m32x->stat; 1091 lstat = sc->m32x->lstat; 1092#if 0 1093 if (!stat && !(lstat & 2)) 1094 return; 1095#endif 1096 1097 if (stat & ~0xc200) { 1098 printf("%s*: I stat=%08x lstat=%08x\n", sc->name, stat, lstat); 1099 } 1100 1101 if ((stat & 0x200) || (lstat & 2)) 1102 f54_intr(sc); 1103 1104 for (j = i = 0; i < 64; i ++) { 1105 u = sc->riqb[i]; 1106 if (u) { 1107 sc->riqb[i] = 0; 1108 mn_rx_intr(sc, u); 1109 if ((u & ~0x1f) == 0x30000800 || (u & ~0x1f) == 0x30000b00) 1110 continue; 1111 u &= ~0x30000400; /* bits we don't care about */ 1112 if ((u & ~0x1f) == 0x00000900) 1113 continue; 1114 if (!(u & ~0x1f)) 1115 continue; 1116 if (!j) 1117 printf("%s*: RIQB:", sc->name); 1118 printf(" [%d]=%08x", i, u); 1119 j++; 1120 } 1121 } 1122 if (j) 1123 printf("\n"); 1124 1125 for (j = i = 0; i < 64; i ++) { 1126 u = sc->tiqb[i]; 1127 if (u) { 1128 sc->tiqb[i] = 0; 1129 mn_tx_intr(sc, u); 1130 if ((u & ~0x1f) == 0x20000800) 1131 continue; 1132 u &= ~0x20000000; /* bits we don't care about */ 1133 if (!u) 1134 continue; 1135 if (!j) 1136 printf("%s*: TIQB:", sc->name); 1137 printf(" [%d]=%08x", i, u); 1138 j++; 1139 } 1140 } 1141 if (j) 1142 printf("\n"); 1143 sc->m32x->stat = stat; 1144} 1145 1146static void 1147mn_timeout(void *xsc) 1148{ 1149 static int round = 0; 1150 struct softc *sc; 1151 1152 mn_intr(xsc); 1153 sc = xsc; 1154 timeout(mn_timeout, xsc, 10 * hz); 1155 round++; 1156 if (round == 2) { 1157 sc->m32_mem.ccb = 0x00008004; 1158 sc->m32x->cmd = 0x1; 1159 } else if (round > 2) { 1160 printf("%s: timeout\n", sc->name); 1161 } 1162} 1163 1164/* 1165 * PCI initialization stuff 1166 */ 1167 1168static struct pci_device mn_device = { 1169 "mn", 1170 mn_probe, 1171 mn_attach, 1172 &mn_count, 1173 NULL 1174}; 1175 1176#ifdef COMPAT_PCI_DRIVER 1177COMPAT_PCI_DRIVER(ti, mn_device); 1178#else 1179DATA_SET(pcidevice_set, mn_device); 1180#endif /* COMPAT_PCI_DRIVER */ 1181 1182static const char* 1183mn_probe (pcici_t tag, pcidi_t typea) 1184{ 1185 u_int id = pci_conf_read(tag, PCI_ID_REG); 1186 1187 if (sizeof (struct m32xreg) != 256) { 1188 printf("MN: sizeof(struct m32xreg) = %d, should have been 256\n", sizeof (struct m32xreg)); 1189 return (0); 1190 } 1191 if (sizeof (struct f54rreg) != 128) { 1192 printf("MN: sizeof(struct f54rreg) = %d, should have been 128\n", sizeof (struct f54rreg)); 1193 return (0); 1194 } 1195 if (sizeof (struct f54wreg) != 128) { 1196 printf("MN: sizeof(struct f54wreg) = %d, should have been 128\n", sizeof (struct f54wreg)); 1197 return (0); 1198 } 1199 1200 if (id == 0x2101110a) 1201 return "Munich32X E1/T1 HDLC Controller"; 1202 1203 return 0; 1204} 1205 1206static void 1207mn_attach (pcici_t tag, int unit) 1208{ 1209 struct softc *sc; 1210 u_int32_t u; 1211 u_int32_t pci_class; 1212 static int once; 1213 1214 if (!once) { 1215 if (ng_newtype(&mntypestruct)) 1216 printf("ng_newtype failed\n"); 1217 once++; 1218 } 1219 1220 sc = (struct softc *)malloc(sizeof *sc, M_MN, M_WAITOK); 1221 softc[unit] = sc; 1222 bzero(sc, sizeof *sc); 1223 1224 sc->tag = tag; 1225 sc->unit = unit; 1226 sprintf(sc->name, "mn%c", 'A' + unit); 1227 1228 if (!pci_map_int(tag, mn_intr, sc, &net_imask)) { 1229 printf("mn%d: could not map interrupt\n", sc->unit); 1230 return; 1231 } 1232 pci_map_mem(tag, PCI_MAP_REG_START, &sc->m0v, &sc->m0p); 1233 pci_map_mem(tag, PCI_MAP_REG_START + 4, &sc->m1v, &sc->m1p); 1234 1235 u = pci_conf_read(tag, PCIR_COMMAND); 1236 pci_conf_write(tag, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); 1237 pci_conf_write(tag, PCIR_COMMAND, 0x02800046); 1238 1239 pci_class = pci_conf_read(tag, PCI_CLASS_REG); 1240 1241 sc->m32x = (struct m32xreg *) sc->m0v; 1242 sc->f54w = (struct f54wreg *) sc->m1v; 1243 sc->f54r = (struct f54rreg *) sc->m1v; 1244 1245 /* We must reset before poking at FALC54 registers */ 1246 u = mn_reset(sc); 1247 if (!u) 1248 return; 1249 1250 printf("mn%d: Munich32X", sc->unit); 1251 switch (pci_class & 0xff) { 1252 case 0x13: 1253 printf(" Rev 1.3"); 1254 break; 1255 default: 1256 printf(" Rev 0x%x\n", pci_class & 0xff); 1257 } 1258 printf(", Falc54"); 1259 switch (sc->f54r->vstr) { 1260 case 0: 1261 printf(" Rev < 1.3\n"); 1262 break; 1263 case 1: 1264 printf(" Rev 1.3\n"); 1265 break; 1266 case 2: 1267 printf(" Rev 1.4\n"); 1268 break; 1269 case 0x10: 1270 printf("-LH Rev 1.1\n"); 1271 break; 1272 default: 1273 printf(" Rev 0x%x\n", sc->f54r->vstr); 1274 } 1275 1276 if (ng_make_node_common(&mntypestruct, &sc->node) != 0) { 1277 printf("ng_make_node_common failed\n"); 1278 return; 1279 } 1280 sc->node->private = sc; 1281 sprintf(sc->nodename, "%s%d", NG_MN_NODE_TYPE, sc->unit); 1282 if (ng_name_node(sc->node, sc->nodename)) { 1283 ng_rmnode(sc->node); 1284 ng_unref(sc->node); 1285 return; 1286 } 1287 1288 return; 1289} 1290#endif /* KERNEL */ 1291