if_mn.c revision 53303
1/* 2 * ---------------------------------------------------------------------------- 3 * "THE BEER-WARE LICENSE" (Revision 42): 4 * <phk@FreeBSD.org> wrote this file. As long as you retain this notice you 5 * can do whatever you want with this stuff. If we meet some day, and you think 6 * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp 7 * ---------------------------------------------------------------------------- 8 * 9 * $Id: if_mn.c,v 1.1 1999/02/01 13:06:40 phk Exp $ 10 * 11 * Driver for Siemens reference design card "Easy321-R1". 12 * 13 * This card contains a FALC54 E1/T1 framer and a MUNICH32X 32-channel HDLC 14 * controller. 15 * 16 * The driver support E1 mode with up to 31 channels. We send CRC4 but don't 17 * check it coming in. 18 * 19 * The FALC54 and MUNICH32X have far too many registers and weird modes for 20 * comfort, so I have not bothered typing it all into a "fooreg.h" file, 21 * you will (badly!) need the documentation anyway if you want to mess with 22 * this gadget. 23 * 24 * $FreeBSD: head/sys/pci/if_mn.c 53303 1999-11-17 21:40:14Z phk $ 25 */ 26 27/* 28 * Stuff to describe the MUNIC32X and FALC54 chips. 29 */ 30 31#define M32_CHAN 32 /* We have 32 channels */ 32#define M32_TS 32 /* We have 32 timeslots */ 33 34#define NG_MN_NODE_TYPE "mn" 35#define NG_MN_COOKIKE 941432500 36 37#define MN_MAGIC 0x4d6e0000 38 39#define MN_GET (MN_MAGIC | 0x1) 40#define MN_SET (MN_MAGIC | 0x2) 41#define MN_DEBUG (MN_MAGIC | 0x3) 42 43struct mn_control { 44 int cmd; 45 char name[8]; 46 unsigned chan; 47 unsigned ts[M32_CHAN]; 48}; 49 50#ifdef KERNEL 51#define PPP_HEADER_LEN 4 /* XXX: should live in some header somewhere */ 52 53#include <sys/param.h> 54#include <sys/systm.h> 55#include <sys/conf.h> 56#include <sys/mbuf.h> 57#include <sys/kernel.h> 58#include <sys/malloc.h> 59#include <sys/socket.h> 60#include <sys/sockio.h> 61#include <pci/pcireg.h> 62#include <pci/pcivar.h> 63#include <vm/vm.h> 64#include <vm/pmap.h> 65#include <machine/clock.h> 66 67#include <netgraph/ng_message.h> 68#include <netgraph/ng_sample.h> 69#include <netgraph/netgraph.h> 70 71#ifndef NMN 72/* Most machines don't support more than 4 busmaster PCI slots, if even that many */ 73#define NMN 4 74#endif 75 76/* From: PEB 20321 data sheet, p187, table 22 */ 77struct m32xreg { 78 u_int32_t conf, cmd, stat, imask; 79 u_int32_t fill10, piqba, piql, fill1c; 80 u_int32_t mode1, mode2, ccba, txpoll; 81 u_int32_t tiqba, tiql, riqba, riql; 82 u_int32_t lconf, lccba, fill48, ltran; 83 u_int32_t ltiqba, ltiql, lriqba, lriql; 84 u_int32_t lreg0, lreg1, lreg2, lreg3; 85 u_int32_t lreg4, lreg5, lre6, lstat; 86 u_int32_t gpdir, gpdata, gpod, fill8c; 87 u_int32_t ssccon, sscbr, ssctb, sscrb; 88 u_int32_t ssccse, sscim, fillab, fillac; 89 u_int32_t iomcon1, iomcon2, iomstat, fillbc; 90 u_int32_t iomcit0, iomcit1, iomcir0, iomcir1; 91 u_int32_t iomtmo, iomrmo, filld8, filldc; 92 u_int32_t mbcmd, mbdata1, mbdata2, mbdata3; 93 u_int32_t mbdata4, mbdata5, mbdata6, mbdata7; 94}; 95 96/* From: PEB 2254 data sheet, p80, table 10 */ 97struct f54wreg { 98 u_int16_t xfifo; 99 u_int8_t cmdr, mode, rah1, rah2, ral1, ral2; 100 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 101 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 102 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 103 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 104 u_int8_t test1, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr3; 105 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 106 u_int8_t lim2, fill39[7]; 107 u_int8_t fill40[8]; 108 u_int8_t fill48[8]; 109 u_int8_t fill50[8]; 110 u_int8_t fill58[8]; 111 u_int8_t dec, fill61, test2, fill63[5]; 112 u_int8_t fill68[8]; 113 u_int8_t xs[16]; 114}; 115 116/* From: PEB 2254 data sheet, p117, table 10 */ 117struct f54rreg { 118 u_int16_t rfifo; 119 u_int8_t fill2, mode, rah1, rah2, ral1, ral2; 120 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 121 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 122 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 123 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 124 u_int8_t test, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr13; 125 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 126 u_int8_t lim2, fill39[7]; 127 u_int8_t fill40[8]; 128 u_int8_t fill48[4], frs0, frs1, rsw, rsp; 129 u_int16_t fec, cvc, cec1, ebc; 130 u_int16_t cec2, cec3; 131 u_int8_t rsa4, rsa5, rsa6, rsa7; 132 u_int8_t rsa8, rsa6s, tsr0, tsr1, sis, rsis; 133 u_int16_t rbc; 134 u_int8_t isr0, isr1, isr2, isr3, fill6c, fill6d, gis, vstr; 135 u_int8_t rs[16]; 136}; 137 138/* Transmit & receive descriptors */ 139struct trxd { 140 u_int32_t flags; 141 vm_offset_t next; 142 vm_offset_t data; 143 u_int32_t status; /* only used for receive */ 144 struct mbuf *m; /* software use only */ 145 struct trxd *vnext; /* software use only */ 146}; 147 148/* Channel specification */ 149struct cspec { 150 u_int32_t flags; 151 vm_offset_t rdesc; 152 vm_offset_t tdesc; 153 u_int32_t itbs; 154}; 155 156struct m32_mem { 157 vm_offset_t csa; 158 u_int32_t ccb; 159 u_int32_t reserve1[2]; 160 u_int32_t ts[M32_TS]; 161 struct cspec cs[M32_CHAN]; 162 vm_offset_t crxd[M32_CHAN]; 163 vm_offset_t ctxd[M32_CHAN]; 164}; 165 166struct softc; 167struct sockaddr; 168struct rtentry; 169 170static const char* mn_probe (pcici_t tag, pcidi_t type); 171static void mn_attach (pcici_t tag, int unit); 172static u_long mn_count; 173static void mn_create_channel(struct softc *sc, int chan); 174static int mn_reset(struct softc *sc); 175static struct trxd * mn_alloc_desc(void); 176static void mn_free_desc(struct trxd *dp); 177static void mn_intr(void *xsc); 178static void m32_dump(struct softc *sc); 179static void f54_dump(struct softc *sc); 180static u_int32_t mn_parse_ts(const char *s); 181static void mn_fmt_ts(char *p, u_int32_t ts); 182 183static ng_constructor_t ngmn_constructor; 184static ng_rcvmsg_t ngmn_rcvmsg; 185static ng_shutdown_t ngmn_shutdown; 186static ng_newhook_t ngmn_newhook; 187static ng_connect_t ngmn_connect; 188static ng_rcvdata_t ngmn_rcvdata; 189static ng_disconnect_t ngmn_disconnect; 190 191static struct ng_type mntypestruct = { 192 NG_VERSION, 193 NG_MN_NODE_TYPE, 194 NULL, 195 ngmn_constructor, 196 ngmn_rcvmsg, 197 ngmn_shutdown, 198 ngmn_newhook, 199 NULL, 200 ngmn_connect, 201 ngmn_rcvdata, 202 ngmn_rcvdata, 203 ngmn_disconnect 204}; 205 206static MALLOC_DEFINE(M_MN, "mn", "Mx driver related"); 207 208#define NIQB 64 209 210struct softc; 211 212struct schan { 213 enum {DOWN, UP} state; 214 struct softc *sc; 215 int chan; 216 u_int32_t ts; 217 char name[8]; 218 struct trxd *r1, *rl; 219 struct trxd *x1, *xl; 220 hook_p hook; 221 222 time_t last_recv; 223 time_t last_rxerr; 224 time_t last_xmit; 225 226 u_long rx_error; 227 228 u_long short_error; 229 u_long crc_error; 230 u_long dribble_error; 231 u_long long_error; 232 u_long abort_error; 233 u_long overflow_error; 234 235 int last_error; 236 int prev_error; 237}; 238 239static struct softc { 240 int unit; 241 pcici_t tag; 242 vm_offset_t m0v, m0p, m1v, m1p; 243 struct m32xreg *m32x; 244 struct f54wreg *f54w; 245 struct f54rreg *f54r; 246 struct m32_mem m32_mem; 247 u_int32_t tiqb[NIQB]; 248 u_int32_t riqb[NIQB]; 249 u_int32_t piqb[NIQB]; 250 u_int32_t ltiqb[NIQB]; 251 u_int32_t lriqb[NIQB]; 252 char name[8]; 253 u_int32_t falc_irq, falc_state, framer_state; 254 struct schan *ch[M32_CHAN]; 255 char nodename[NG_NODELEN + 1]; 256 node_p node; 257 258 u_long cnt_fec; 259 u_long cnt_cvc; 260 u_long cnt_cec1; 261 u_long cnt_ebc; 262 u_long cnt_cec2; 263 u_long cnt_cec3; 264 u_long cnt_rbc; 265} *softc[NMN]; 266 267static int 268ngmn_constructor(node_p *nodep) 269{ 270 271 return (EINVAL); 272} 273 274static int 275ngmn_shutdown(node_p nodep) 276{ 277 278 return (EINVAL); 279} 280 281static int 282ngmn_rcvmsg(node_p node, struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp) 283{ 284 struct softc *sc; 285 struct schan *sch; 286 char *arg; 287 int pos, i; 288 289 sc = node->private; 290 291 if (msg->header.typecookie != NGM_GENERIC_COOKIE || 292 msg->header.cmd != NGM_TEXT_STATUS) { 293 if (resp) 294 *resp = NULL; 295 FREE(msg, M_NETGRAPH); 296 return (EINVAL); 297 } 298 NG_MKRESPONSE(*resp, msg, sizeof(struct ng_mesg) + NG_TEXTRESPONSE, 299 M_NOWAIT); 300 if (*resp == NULL) { 301 FREE(msg, M_NETGRAPH); 302 return (ENOMEM); 303 } 304 arg = (char *)(*resp)->data; 305 pos = 0; 306 pos += sprintf(pos + arg,"Framer status %b;\n", sc->framer_state, "\20" 307 "\40LOS\37AIS\36LFA\35RRA" 308 "\34AUXP\33NMF\32LMFA\31frs0.0" 309 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 310 "\24TS16LFA\23frs1.2\22XLS\21XLO" 311 "\20RS1\17rsw.6\16RRA\15RY0" 312 "\14RY1\13RY2\12RY3\11RY4" 313 "\10SI1\7SI2\6rsp.5\5rsp.4" 314 "\4rsp.3\3RSIF\2RS13\1RS15"); 315 pos += sprintf(pos + arg," Framing errors: %lu", sc->cnt_fec); 316 pos += sprintf(pos + arg," Code Violations: %lu\n", sc->cnt_cvc); 317 318 pos += sprintf(pos + arg," Falc State %b;\n", sc->falc_state, "\20" 319 "\40LOS\37AIS\36LFA\35RRA" 320 "\34AUXP\33NMF\32LMFA\31frs0.0" 321 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 322 "\24TS16LFA\23frs1.2\22XLS\21XLO" 323 "\20RS1\17rsw.6\16RRA\15RY0" 324 "\14RY1\13RY2\12RY3\11RY4" 325 "\10SI1\7SI2\6rsp.5\5rsp.4" 326 "\4rsp.3\3RSIF\2RS13\1RS15"); 327 pos += sprintf(pos + arg, " Falc IRQ %b\n", sc->falc_irq, "\20" 328 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 329 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 330 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 331 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 332 for (i = 0; i < M32_CHAN; i++) { 333 if (!sc->ch[i]) 334 continue; 335 sch = sc->ch[i]; 336 337 pos += sprintf(arg + pos, " Chan %d <%s> ", 338 i, sch->hook->name); 339 340 pos += sprintf(arg + pos, " Last Rx: "); 341 if (sch->last_recv) 342 pos += sprintf(arg + pos, "%lu s", time_second - sch->last_recv); 343 else 344 pos += sprintf(arg + pos, "never"); 345 346 pos += sprintf(arg + pos, ", last RxErr: "); 347 if (sch->last_rxerr) 348 pos += sprintf(arg + pos, "%lu s", time_second - sch->last_rxerr); 349 else 350 pos += sprintf(arg + pos, "never"); 351 352 pos += sprintf(arg + pos, ", last Tx: "); 353 if (sch->last_xmit) 354 pos += sprintf(arg + pos, "%lu s\n", time_second - sch->last_xmit); 355 else 356 pos += sprintf(arg + pos, "never\n"); 357 358 pos += sprintf(arg + pos, " RX error(s) %lu", sch->rx_error); 359 pos += sprintf(arg + pos, " Short: %lu", sch->short_error); 360 pos += sprintf(arg + pos, " CRC: %lu", sch->crc_error); 361 pos += sprintf(arg + pos, " Mod8: %lu", sch->dribble_error); 362 pos += sprintf(arg + pos, " Long: %lu", sch->long_error); 363 pos += sprintf(arg + pos, " Abort: %lu", sch->abort_error); 364 pos += sprintf(arg + pos, " Overflow: %lu\n", sch->overflow_error); 365 366 pos += sprintf(arg + pos, " Last error: %b Prev error: %b\n", 367 sch->last_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN", 368 sch->prev_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN"); 369 } 370 (*resp)->header.arglen = pos + 1; 371 FREE(msg, M_NETGRAPH); 372 return (0); 373} 374 375static int 376ngmn_newhook(node_p node, hook_p hook, const char *name) 377{ 378 u_int32_t ts, chan; 379 struct softc *sc; 380 381 sc = node->private; 382 383 if (name[0] != 't' || name[1] != 's') 384 return (EINVAL); 385 386 ts = mn_parse_ts(name + 2); 387 if (ts == 0) 388 return (EINVAL); 389 chan = ffs(ts) - 1; 390 if (sc->ch[chan]) 391 return (EBUSY); 392 mn_create_channel(sc, chan); /* Create the first channel */ 393 sc->ch[chan]->ts = ts; 394 sc->ch[chan]->hook = hook; 395 hook->private = sc->ch[chan]; 396 return(0); 397} 398 399 400static struct trxd *mn_desc_free; 401 402static struct trxd * 403mn_alloc_desc(void) 404{ 405 struct trxd *dp; 406 407 dp = mn_desc_free; 408 if (dp) 409 mn_desc_free = dp->vnext; 410 else 411 dp = (struct trxd *)malloc(sizeof *dp, M_MN, M_NOWAIT); 412 return (dp); 413} 414 415static void 416mn_free_desc(struct trxd *dp) 417{ 418 dp->vnext = mn_desc_free; 419 mn_desc_free = dp; 420} 421 422static u_int32_t 423mn_parse_ts(const char *s) 424{ 425 unsigned r; 426 int i, j; 427 const char *p; 428 429 r = 0; 430 j = 0; 431 while(*s) { 432 i = strtol(s, &p, 0); 433 if (i < 1 || i > 31) 434 return (0); 435 while (j && j < i) { 436 r |= 1 << j++; 437 } 438 j = 0; 439 r |= 1 << i; 440 if (*p == ',') { 441 s = p + 1; 442 continue; 443 } else if (*p == '-') { 444 j = i; 445 s = p + 1; 446 continue; 447 } else if (!*p) { 448 break; 449 } else { 450 return (0); 451 } 452 } 453 return (r); 454} 455 456static void 457mn_fmt_ts(char *p, u_int32_t ts) 458{ 459 char *s; 460 int j; 461 462 s = ""; 463 ts &= 0xfffffffe; 464 for (j = 1; j < 32; j++) { 465 if (!(ts & (1 << j))) 466 continue; 467 sprintf(p, "%s%d", s, j); 468 p += strlen(p); 469 s = ","; 470 if (!(ts & (1 << (j+1)))) 471 continue; 472 for (; j < 32; j++) 473 if (!(ts & (1 << (j+1)))) 474 break; 475 sprintf(p, "-%d", j); 476 p += strlen(p); 477 s = ","; 478 } 479} 480 481/* 482 * OUTPUT 483 */ 484 485static int 486ngmn_rcvdata(hook_p hook, struct mbuf *m, meta_p meta) 487{ 488 struct mbuf *m2; 489 struct trxd *dp, *dp2; 490 struct schan *sch; 491 struct softc *sc; 492 int chan, pitch, len; 493 494 sch = hook->private; 495 sc = sch->sc; 496 chan = sch->chan; 497 498 if (sc->ch[chan]->state != UP) { 499 NG_FREE_DATA(m, meta); 500 return (0); 501 } 502 NG_FREE_META(meta); 503 pitch = 0; 504 m2 = m; 505 dp2 = sc->ch[chan]->xl; 506 len = m->m_pkthdr.len; 507 while (len) { 508 dp = mn_alloc_desc(); 509 if (!dp) { 510 pitch++; 511 m_freem(m); 512 sc->ch[chan]->xl = dp2; 513 dp = dp2->vnext; 514 while (dp) { 515 dp2 = dp->vnext; 516 mn_free_desc(dp); 517 dp = dp2; 518 } 519 sc->ch[chan]->xl->vnext = 0; 520 break; 521 } 522 dp->data = vtophys(m2->m_data); 523 dp->flags = m2->m_len << 16; 524 dp->flags += 1; 525 len -= m2->m_len; 526 dp->next = vtophys(dp); 527 dp->vnext = 0; 528 sc->ch[chan]->xl->next = vtophys(dp); 529 sc->ch[chan]->xl->vnext = dp; 530 sc->ch[chan]->xl = dp; 531 if (!len) { 532 dp->m = m; 533 dp->flags |= 0xc0000000; 534 dp2->flags &= ~0x40000000; 535 } else { 536 dp->m = 0; 537 m2 = m2->m_next; 538 } 539 } 540 if (pitch) 541 printf("%s%d: Short on mem, pitched %d packets\n", 542 sc->name, chan, pitch); 543 return (0); 544} 545 546/* 547 * OPEN 548 */ 549static int 550ngmn_connect(hook_p hook) 551{ 552 int i, nts, chan; 553 struct trxd *dp, *dp2; 554 struct mbuf *m; 555 struct softc *sc; 556 struct schan *sch; 557 u_int32_t u; 558 559 sch = hook->private; 560 chan = sch->chan; 561 sc = sch->sc; 562 563 printf("%s: OPEN{ state = %d\n", sch->name, sch->state); 564 if (sch->state == UP) 565 return (0); 566 sch->state = UP; 567 568 /* Count and configure the timeslots for this channel */ 569 for (nts = i = 0; i < 32; i++) 570 if (sch->ts & (1 << i)) { 571 sc->m32_mem.ts[i] = 0x00ff00ff | 572 (chan << 24) | (chan << 8); 573 nts++; 574 } 575 576 /* Init the receiver & xmitter to HDLC */ 577 sc->m32_mem.cs[chan].flags = 0x80e90006; 578 /* Allocate two buffers per timeslot */ 579 sc->m32_mem.cs[chan].itbs = nts * 2; 580 581 /* Setup a transmit chain with one descriptor */ 582 /* XXX: we actually send a 1 byte packet */ 583 dp = mn_alloc_desc(); 584 MGETHDR(m, M_WAIT, MT_DATA); 585 dp->m = m; 586 dp->flags = 0xc0000000 + (1 << 16); 587 dp->next = vtophys(dp); 588 dp->vnext = 0; 589 dp->data = vtophys(sc->name); 590 sc->m32_mem.cs[chan].tdesc = vtophys(dp); 591 sc->ch[chan]->x1 = dp; 592 sc->ch[chan]->xl = dp; 593 594 /* Setup a receive chain with 5 + NTS descriptors */ 595 596 dp = mn_alloc_desc(); 597 MGETHDR(m, M_WAIT, MT_DATA); 598 MCLGET(m, M_WAIT); 599 dp->m = m; 600 dp->data = vtophys(m->m_data); 601 dp->flags = 0x40000000; 602 dp->flags += 1600 << 16; 603 dp->next = vtophys(dp); 604 dp->vnext = 0; 605 sc->ch[chan]->rl = dp; 606 607 for (i = 0; i < (nts + 10); i++) { 608 dp2 = dp; 609 dp = mn_alloc_desc(); 610 MGETHDR(m, M_WAIT, MT_DATA); 611 MCLGET(m, M_WAIT); 612 dp->m = m; 613 dp->data = vtophys(m->m_data); 614 dp->flags = 0x00000000; 615 dp->flags += 1600 << 16; 616 dp->next = vtophys(dp2); 617 dp->vnext = dp2; 618 } 619 sc->m32_mem.cs[chan].rdesc = vtophys(dp); 620 sc->ch[chan]->r1 = dp; 621 622 /* Initialize this channel */ 623 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 624 sc->m32x->cmd = 0x1; 625 DELAY(30); 626 u = sc->m32x->stat; 627 if (!(u & 1)) 628 printf("%s: init chan %d stat %08x\n", sc->name, chan, u); 629 sc->m32x->stat = 1; 630 631 printf("%s%d: TLS} state = %d\n", sc->name, chan, sc->ch[chan]->state); 632 return (0); 633} 634 635/* 636 * CLOSE 637 */ 638static int 639ngmn_disconnect(hook_p hook) 640{ 641 int chan, i; 642 struct softc *sc; 643 struct schan *sch; 644 struct trxd *dp, *dp2; 645 u_int32_t u; 646 647 sch = hook->private; 648 chan = sch->chan; 649 sc = sch->sc; 650 651 printf("%s: TLF{ state = %d\n", sch->name, sch->state); 652 if (sch->state == DOWN) 653 return (0); 654 sch->state = DOWN; 655 656 /* Set receiver & transmitter off */ 657 sc->m32_mem.cs[chan].flags = 0x80920006; 658 sc->m32_mem.cs[chan].itbs = 0; 659 660 /* free the timeslots */ 661 for (i = 0; i < 32; i++) 662 if (sc->ch[chan]->ts & (1 << i)) 663 sc->m32_mem.ts[i] = 0x20002000; 664 665 /* Initialize this channel */ 666 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 667 sc->m32x->cmd = 0x1; 668 DELAY(30); 669 u = sc->m32x->stat; 670 if (!(u & 1)) 671 printf("%s: zap chan %d stat %08x\n", sc->name, chan, u); 672 sc->m32x->stat = 1; 673 674 /* Free all receive descriptors and mbufs */ 675 for (dp = sc->ch[chan]->r1; dp ; dp = dp2) { 676 if (dp->m) 677 m_freem(dp->m); 678 sc->ch[chan]->r1 = dp2 = dp->vnext; 679 mn_free_desc(dp); 680 } 681 682 /* Free all transmit descriptors and mbufs */ 683 for (dp = sc->ch[chan]->x1; dp ; dp = dp2) { 684 if (dp->m) 685 m_freem(dp->m); 686 sc->ch[chan]->x1 = dp2 = dp->vnext; 687 mn_free_desc(dp); 688 } 689 printf("%s%d: TLF} state = %d\n", sc->name, chan, sc->ch[chan]->state); 690 return(0); 691} 692 693/* 694 * Create a new channel. 695 */ 696static void 697mn_create_channel(struct softc *sc, int chan) 698{ 699 struct schan *sch; 700 701 sch = sc->ch[chan] = (struct schan *)malloc(sizeof *sc->ch[chan], 702 M_MN, M_WAITOK); 703 bzero(sch, sizeof *sch); 704 sch->sc = sc; 705 sch->state = DOWN; 706 sch->chan = chan; 707 sprintf(sch->name, "%s%d", sc->name, chan); 708 return; 709} 710 711/* 712 * Dump Munich32x state 713 */ 714static void 715m32_dump(struct softc *sc) 716{ 717 u_int32_t *tp4; 718 int i, j; 719 720 printf("mn%d: MUNICH32X dump\n", sc->unit); 721 tp4 = (u_int32_t *)sc->m0v; 722 for(j = 0; j < 64; j += 8) { 723 printf("%02x", j * sizeof *tp4); 724 for(i = 0; i < 8; i++) 725 printf(" %08x", tp4[i+j]); 726 printf("\n"); 727 } 728 for(j = 0; j < M32_CHAN; j++) { 729 if (!sc->ch[j]) 730 continue; 731 printf("CH%d: state %d ts %08x", 732 j, sc->ch[j]->state, sc->ch[j]->ts); 733 printf(" %08x %08x %08x %08x %08x %08x\n", 734 sc->m32_mem.cs[j].flags, 735 sc->m32_mem.cs[j].rdesc, 736 sc->m32_mem.cs[j].tdesc, 737 sc->m32_mem.cs[j].itbs, 738 sc->m32_mem.crxd[j], 739 sc->m32_mem.ctxd[j] ); 740 } 741} 742 743/* 744 * Dump Falch54 state 745 */ 746static void 747f54_dump(struct softc *sc) 748{ 749 u_int8_t *tp1; 750 int i, j; 751 752 printf("%s: FALC54 dump\n", sc->name); 753 tp1 = (u_int8_t *)sc->m1v; 754 for(j = 0; j < 128; j += 16) { 755 printf("%s: %02x |", sc->name, j * sizeof *tp1); 756 for(i = 0; i < 16; i++) 757 printf(" %02x", tp1[i+j]); 758 printf("\n"); 759 } 760} 761 762/* 763 * Init Munich32x 764 */ 765static void 766m32_init(struct softc *sc) 767{ 768 769 sc->m32x->conf = 0x00000000; 770 sc->m32x->mode1 = 0x81048000 + 1600; /* XXX: temp */ 771#if 1 772 sc->m32x->mode2 = 0x00000081; 773 sc->m32x->txpoll = 0xffffffff; 774#else 775 sc->m32x->mode2 = 0x00000101; 776#endif 777 sc->m32x->lconf = 0x6060009B; 778 sc->m32x->imask = 0x00000000; 779} 780 781/* 782 * Init the Falc54 783 */ 784static void 785f54_init(struct softc *sc) 786{ 787 sc->f54w->ipc = 0x07; 788 789 sc->f54w->xpm0 = 0xbd; 790 sc->f54w->xpm1 = 0x03; 791 sc->f54w->xpm2 = 0x00; 792 793 sc->f54w->imr0 = 0x18; /* RMB, CASC */ 794 sc->f54w->imr1 = 0x08; /* XMB */ 795 sc->f54w->imr2 = 0x00; 796 sc->f54w->imr3 = 0x38; /* LMFA16, AIS16, RA16 */ 797 sc->f54w->imr4 = 0x00; 798 799 sc->f54w->fmr0 = 0xf0; /* X: HDB3, R: HDB3 */ 800 sc->f54w->fmr1 = 0x0e; /* Send CRC4, 2Mbit, ECM */ 801 sc->f54w->fmr2 = 0x03; /* Auto Rem-Alarm, Auto resync */ 802 803 sc->f54w->lim1 = 0xb0; /* XCLK=8kHz, .62V threshold */ 804 sc->f54w->pcd = 0x0a; 805 sc->f54w->pcr = 0x15; 806 sc->f54w->xsw = 0x9f; /* fmr4 */ 807 sc->f54w->xsp = 0x1c; /* fmr5 */ 808 sc->f54w->xc0 = 0x07; 809 sc->f54w->xc1 = 0x3d; 810 sc->f54w->rc0 = 0x05; 811 sc->f54w->rc1 = 0x00; 812 sc->f54w->cmdr = 0x51; 813} 814 815static int 816mn_reset(struct softc *sc) 817{ 818 u_int32_t u; 819 int i, j; 820 821 u = 0; 822 for(i = 5; i >= 0; i-- ) { 823 sc->m32x->gpdir = i; 824 for (j = 0; j < 8; j ++) { 825 sc->m32x->gpdata = j; 826 u += sc->m32x->gpdata; 827 } 828 } 829 if (u != 0xe4) { 830 printf("mn%d: WARNING: Controller failed to initialize.\n", 831 sc->unit); 832#if 0 833 return (0); 834#endif 835 printf("mn%d: %x\n", sc->unit, u); 836 } 837 838 sc->m32x->ccba = vtophys(&sc->m32_mem.csa); 839 sc->m32_mem.csa = vtophys(&sc->m32_mem.ccb); 840 841 bzero(sc->tiqb, sizeof sc->tiqb); 842 sc->m32x->tiqba = vtophys(&sc->tiqb); 843 sc->m32x->tiql = NIQB / 16 - 1; 844 845 bzero(sc->riqb, sizeof sc->riqb); 846 sc->m32x->riqba = vtophys(&sc->riqb); 847 sc->m32x->riql = NIQB / 16 - 1; 848 849 bzero(sc->ltiqb, sizeof sc->ltiqb); 850 sc->m32x->ltiqba = vtophys(&sc->ltiqb); 851 sc->m32x->ltiql = NIQB / 16 - 1; 852 853 bzero(sc->lriqb, sizeof sc->lriqb); 854 sc->m32x->lriqba = vtophys(&sc->lriqb); 855 sc->m32x->lriql = NIQB / 16 - 1; 856 857 bzero(sc->piqb, sizeof sc->piqb); 858 sc->m32x->piqba = vtophys(&sc->piqb); 859 sc->m32x->piql = NIQB / 16 - 1; 860 861 m32_init(sc); 862 f54_init(sc); 863 864 u = sc->m32x->stat; 865 sc->m32x->stat = u; 866 sc->m32_mem.ccb = 0x4; 867 sc->m32x->cmd = 0x1; 868 DELAY(1000); 869 u = sc->m32x->stat; 870 sc->m32x->stat = u; 871 872 /* set all timeslots to known state */ 873 for (i = 0; i < 32; i++) 874 sc->m32_mem.ts[i] = 0x20002000; 875 876 if (!(u & 1)) { 877 printf( 878"mn%d: WARNING: Controller failed the PCI bus-master test.\n" 879"mn%d: WARNING: Use a PCI slot which can support bus-master cards.\n", 880 sc->unit, sc->unit); 881 return (0); 882 } 883 return (1); 884} 885 886/* 887 * FALC54 interrupt handling 888 */ 889static void 890f54_intr(struct softc *sc) 891{ 892 unsigned g, u, s; 893 894 g = sc->f54r->gis; 895 u = sc->f54r->isr0 << 24; 896 u |= sc->f54r->isr1 << 16; 897 u |= sc->f54r->isr2 << 8; 898 u |= sc->f54r->isr3; 899 sc->falc_irq = u; 900 /* don't chat about the 1 sec heart beat */ 901 if (u & ~0x40) { 902#if 0 903 printf("%s*: FALC54 IRQ GIS:%02x %b\n", sc->name, g, u, "\20" 904 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 905 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 906 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 907 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 908#endif 909 s = sc->f54r->frs0 << 24; 910 s |= sc->f54r->frs1 << 16; 911 s |= sc->f54r->rsw << 8; 912 s |= sc->f54r->rsp; 913 sc->falc_state = s; 914 915 s &= ~0x01844038; /* undefined or static bits */ 916 s &= ~0x00009fc7; /* bits we don't care about */ 917 s &= ~0x00780000; /* XXX: TS16 related */ 918 s &= ~0x06000000; /* XXX: Multiframe related */ 919#if 0 920 printf("%s*: FALC54 Status %b\n", sc->name, s, "\20" 921 "\40LOS\37AIS\36LFA\35RRA\34AUXP\33NMF\32LMFA\31frs0.0" 922 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS\24TS16LFA\23frs1.2\22XLS\21XLO" 923 "\20RS1\17rsw.6\16RRA\15RY0\14RY1\13RY2\12RY3\11RY4" 924 "\10SI1\7SI2\6rsp.5\5rsp.4\4rsp.3\3RSIF\2RS13\1RS15"); 925#endif 926 if (s != sc->framer_state) { 927#if 0 928 for (i = 0; i < M32_CHAN; i++) { 929 if (!sc->ch[i]) 930 continue; 931 sp = &sc->ch[i]->ifsppp; 932 if (!(sp->pp_if.if_flags & IFF_UP)) 933 continue; 934 if (s) 935 timeout((timeout_t *)sp->pp_down, sp, 1 * hz); 936 else 937 timeout((timeout_t *)sp->pp_up, sp, 1 * hz); 938 } 939#endif 940 sc->framer_state = s; 941 } 942 } 943 /* Once per second check error counters */ 944 /* XXX: not clear if this is actually ok */ 945 if (!(u & 0x40)) 946 return; 947 sc->cnt_fec += sc->f54r->fec; 948 sc->cnt_cvc += sc->f54r->cvc; 949 sc->cnt_cec1 += sc->f54r->cec1; 950 sc->cnt_ebc += sc->f54r->ebc; 951 sc->cnt_cec2 += sc->f54r->cec2; 952 sc->cnt_cec3 += sc->f54r->cec3; 953 sc->cnt_rbc += sc->f54r->rbc; 954} 955 956/* 957 * Transmit interrupt for one channel 958 */ 959static void 960mn_tx_intr(struct softc *sc, u_int32_t vector) 961{ 962 u_int32_t chan; 963 struct trxd *dp; 964 struct mbuf *m; 965 966 chan = vector & 0x1f; 967 if (!sc->ch[chan]) 968 return; 969 if (sc->ch[chan]->state != UP) { 970 printf("%s: tx_intr when not UP\n", sc->name); 971 return; 972 } 973 for (;;) { 974 dp = sc->ch[chan]->x1; 975 if (vtophys(dp) == sc->m32_mem.ctxd[chan]) 976 return; 977 m = dp->m; 978 if (m) 979 m_freem(m); 980 sc->ch[chan]->last_xmit = time_second; 981 sc->ch[chan]->x1 = dp->vnext; 982 mn_free_desc(dp); 983 } 984} 985 986/* 987 * Receive interrupt for one channel 988 */ 989static void 990mn_rx_intr(struct softc *sc, u_int32_t vector) 991{ 992 u_int32_t chan, err; 993 struct trxd *dp; 994 struct mbuf *m; 995 struct schan *sch; 996 997 chan = vector & 0x1f; 998 if (!sc->ch[chan]) 999 return; 1000 sch = sc->ch[chan]; 1001 if (sch->state != UP) { 1002 printf("%s: rx_intr when not UP\n", sc->name); 1003 return; 1004 } 1005 vector &= ~0x1f; 1006 if (vector == 0x30000b00) 1007 sch->rx_error++; 1008 for (;;) { 1009 dp = sch->r1; 1010 if (vtophys(dp) == sc->m32_mem.crxd[chan]) 1011 return; 1012 m = dp->m; 1013 dp->m = 0; 1014 m->m_pkthdr.len = m->m_len = (dp->status >> 16) & 0x1fff; 1015 err = (dp->status >> 8) & 0xff; 1016 if (!err) { 1017 ng_queue_data(sch->hook, m, NULL); 1018 sch->last_recv = time_second; 1019 m = 0; 1020 /* we could be down by now... */ 1021 if (sch->state != UP) 1022 return; 1023 } else if (err & 0x40) { 1024 sch->short_error++; 1025 } else if (err & 0x10) { 1026 sch->crc_error++; 1027 } else if (err & 0x08) { 1028 sch->dribble_error++; 1029 } else if (err & 0x04) { 1030 sch->long_error++; 1031 } else if (err & 0x02) { 1032 sch->abort_error++; 1033 } else if (err & 0x01) { 1034 sch->overflow_error++; 1035 } 1036 if (err) { 1037 sch->last_rxerr = time_second; 1038 sch->prev_error = sch->last_error; 1039 sch->last_error = err; 1040 } 1041 1042 sc->ch[chan]->r1 = dp->vnext; 1043 1044 /* Replenish desc + mbuf supplies */ 1045 if (!m) { 1046 MGETHDR(m, M_DONTWAIT, MT_DATA); 1047 if (m == NULL) { 1048 mn_free_desc(dp); 1049 return; 1050 } 1051 MCLGET(m, M_DONTWAIT); 1052 if((m->m_flags & M_EXT) == 0) { 1053 mn_free_desc(dp); 1054 return; 1055 } 1056 } 1057 dp->m = m; 1058 dp->data = vtophys(m->m_data); 1059 dp->flags = 0x40000000; 1060 dp->flags += 1600 << 16; 1061 dp->next = vtophys(dp); 1062 dp->vnext = 0; 1063 sc->ch[chan]->rl->next = vtophys(dp); 1064 sc->ch[chan]->rl->vnext = dp; 1065 sc->ch[chan]->rl->flags &= ~0x40000000; 1066 sc->ch[chan]->rl = dp; 1067 } 1068} 1069 1070 1071/* 1072 * Interupt handler 1073 */ 1074 1075static void 1076mn_intr(void *xsc) 1077{ 1078 struct softc *sc; 1079 u_int32_t stat, lstat, u; 1080 int i, j; 1081 1082 sc = xsc; 1083 stat = sc->m32x->stat; 1084 lstat = sc->m32x->lstat; 1085#if 0 1086 if (!stat && !(lstat & 2)) 1087 return; 1088#endif 1089 1090 if (stat & ~0xc200) { 1091 printf("%s*: I stat=%08x lstat=%08x\n", sc->name, stat, lstat); 1092 } 1093 1094 if ((stat & 0x200) || (lstat & 2)) 1095 f54_intr(sc); 1096 1097 for (j = i = 0; i < 64; i ++) { 1098 u = sc->riqb[i]; 1099 if (u) { 1100 sc->riqb[i] = 0; 1101 mn_rx_intr(sc, u); 1102 if ((u & ~0x1f) == 0x30000800 || (u & ~0x1f) == 0x30000b00) 1103 continue; 1104 u &= ~0x30000400; /* bits we don't care about */ 1105 if ((u & ~0x1f) == 0x00000900) 1106 continue; 1107 if (!(u & ~0x1f)) 1108 continue; 1109 if (!j) 1110 printf("%s*: RIQB:", sc->name); 1111 printf(" [%d]=%08x", i, u); 1112 j++; 1113 } 1114 } 1115 if (j) 1116 printf("\n"); 1117 1118 for (j = i = 0; i < 64; i ++) { 1119 u = sc->tiqb[i]; 1120 if (u) { 1121 sc->tiqb[i] = 0; 1122 mn_tx_intr(sc, u); 1123 if ((u & ~0x1f) == 0x20000800) 1124 continue; 1125 u &= ~0x20000000; /* bits we don't care about */ 1126 if (!u) 1127 continue; 1128 if (!j) 1129 printf("%s*: TIQB:", sc->name); 1130 printf(" [%d]=%08x", i, u); 1131 j++; 1132 } 1133 } 1134 if (j) 1135 printf("\n"); 1136 sc->m32x->stat = stat; 1137} 1138 1139static void 1140mn_timeout(void *xsc) 1141{ 1142 static int round = 0; 1143 struct softc *sc; 1144 1145 mn_intr(xsc); 1146 sc = xsc; 1147 timeout(mn_timeout, xsc, 10 * hz); 1148 round++; 1149 if (round == 2) { 1150 sc->m32_mem.ccb = 0x00008004; 1151 sc->m32x->cmd = 0x1; 1152 } else if (round > 2) { 1153 printf("%s: timeout\n", sc->name); 1154 } 1155} 1156 1157/* 1158 * PCI initialization stuff 1159 */ 1160 1161static struct pci_device mn_device = { 1162 "mn", 1163 mn_probe, 1164 mn_attach, 1165 &mn_count, 1166 NULL 1167}; 1168 1169#ifdef COMPAT_PCI_DRIVER 1170COMPAT_PCI_DRIVER(ti, mn_device); 1171#else 1172DATA_SET(pcidevice_set, mn_device); 1173#endif /* COMPAT_PCI_DRIVER */ 1174 1175static const char* 1176mn_probe (pcici_t tag, pcidi_t typea) 1177{ 1178 u_int id = pci_conf_read(tag, PCI_ID_REG); 1179 1180 if (sizeof (struct m32xreg) != 256) { 1181 printf("MN: sizeof(struct m32xreg) = %d, should have been 256\n", sizeof (struct m32xreg)); 1182 return (0); 1183 } 1184 if (sizeof (struct f54rreg) != 128) { 1185 printf("MN: sizeof(struct f54rreg) = %d, should have been 128\n", sizeof (struct f54rreg)); 1186 return (0); 1187 } 1188 if (sizeof (struct f54wreg) != 128) { 1189 printf("MN: sizeof(struct f54wreg) = %d, should have been 128\n", sizeof (struct f54wreg)); 1190 return (0); 1191 } 1192 1193 if (id == 0x2101110a) 1194 return "Munich32X E1/T1 HDLC Controller"; 1195 1196 return 0; 1197} 1198 1199static void 1200mn_attach (pcici_t tag, int unit) 1201{ 1202 struct softc *sc; 1203 u_int32_t u; 1204 u_int32_t pci_class; 1205 static int once; 1206 1207 if (!once) { 1208 if (ng_newtype(&mntypestruct)) 1209 printf("ng_newtype failed\n"); 1210 once++; 1211 } 1212 1213 sc = (struct softc *)malloc(sizeof *sc, M_MN, M_WAITOK); 1214 softc[unit] = sc; 1215 bzero(sc, sizeof *sc); 1216 1217 sc->tag = tag; 1218 sc->unit = unit; 1219 sprintf(sc->name, "mn%c", 'A' + unit); 1220 1221 if (!pci_map_int(tag, mn_intr, sc, &net_imask)) { 1222 printf("mn%d: could not map interrupt\n", sc->unit); 1223 return; 1224 } 1225 pci_map_mem(tag, PCI_MAP_REG_START, &sc->m0v, &sc->m0p); 1226 pci_map_mem(tag, PCI_MAP_REG_START + 4, &sc->m1v, &sc->m1p); 1227 1228 u = pci_conf_read(tag, PCIR_COMMAND); 1229 pci_conf_write(tag, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); 1230 pci_conf_write(tag, PCIR_COMMAND, 0x02800046); 1231 1232 pci_class = pci_conf_read(tag, PCI_CLASS_REG); 1233 1234 sc->m32x = (struct m32xreg *) sc->m0v; 1235 sc->f54w = (struct f54wreg *) sc->m1v; 1236 sc->f54r = (struct f54rreg *) sc->m1v; 1237 1238 /* We must reset before poking at FALC54 registers */ 1239 u = mn_reset(sc); 1240 if (!u) 1241 return; 1242 1243 printf("mn%d: Munich32X", sc->unit); 1244 switch (pci_class & 0xff) { 1245 case 0x13: 1246 printf(" Rev 1.3"); 1247 break; 1248 default: 1249 printf(" Rev 0x%x\n", pci_class & 0xff); 1250 } 1251 printf(", Falc54"); 1252 switch (sc->f54r->vstr) { 1253 case 0: 1254 printf(" Rev < 1.3\n"); 1255 break; 1256 case 1: 1257 printf(" Rev 1.3\n"); 1258 break; 1259 case 2: 1260 printf(" Rev 1.4\n"); 1261 break; 1262 case 0x10: 1263 printf("-LH Rev 1.1\n"); 1264 break; 1265 default: 1266 printf(" Rev 0x%x\n", sc->f54r->vstr); 1267 } 1268 1269 if (ng_make_node_common(&mntypestruct, &sc->node) != 0) { 1270 printf("ng_make_node_common failed\n"); 1271 return; 1272 } 1273 sc->node->private = sc; 1274 sprintf(sc->nodename, "%s%d", NG_MN_NODE_TYPE, sc->unit); 1275 if (ng_name_node(sc->node, sc->nodename)) { 1276 ng_rmnode(sc->node); 1277 ng_unref(sc->node); 1278 return; 1279 } 1280 1281 return; 1282} 1283#endif /* KERNEL */ 1284