if_mn.c revision 52800
1/* 2 * ---------------------------------------------------------------------------- 3 * "THE BEER-WARE LICENSE" (Revision 42): 4 * <phk@FreeBSD.org> wrote this file. As long as you retain this notice you 5 * can do whatever you want with this stuff. If we meet some day, and you think 6 * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp 7 * ---------------------------------------------------------------------------- 8 * 9 * $Id: if_mn.c,v 1.1 1999/02/01 13:06:40 phk Exp $ 10 * 11 * Driver for Siemens reference design card "Easy321-R1". 12 * 13 * This card contains a FALC54 E1/T1 framer and a MUNICH32X 32-channel HDLC 14 * controller. 15 * 16 * The driver support E1 mode with up to 31 channels. We send CRC4 but don't 17 * check it coming in. 18 * 19 * The FALC54 and MUNICH32X have far too many registers and weird modes for 20 * comfort, so I have not bothered typing it all into a "fooreg.h" file, 21 * you will (badly!) need the documentation anyway if you want to mess with 22 * this gadget. 23 * 24 * $FreeBSD: head/sys/pci/if_mn.c 52800 1999-11-02 14:23:14Z phk $ 25 */ 26 27/* 28 * Stuff to describe the MUNIC32X and FALC54 chips. 29 */ 30 31#define M32_CHAN 32 /* We have 32 channels */ 32#define M32_TS 32 /* We have 32 timeslots */ 33 34#define NG_MN_NODE_TYPE "mn" 35#define NG_MN_COOKIKE 941432500 36 37#define MN_MAGIC 0x4d6e0000 38 39#define MN_GET (MN_MAGIC | 0x1) 40#define MN_SET (MN_MAGIC | 0x2) 41#define MN_DEBUG (MN_MAGIC | 0x3) 42 43struct mn_control { 44 int cmd; 45 char name[8]; 46 unsigned chan; 47 unsigned ts[M32_CHAN]; 48}; 49 50#ifdef KERNEL 51#define PPP_HEADER_LEN 4 /* XXX: should live in some header somewhere */ 52 53#include <sys/param.h> 54#include <sys/systm.h> 55#include <sys/conf.h> 56#include <sys/mbuf.h> 57#include <sys/kernel.h> 58#include <sys/malloc.h> 59#include <sys/socket.h> 60#include <sys/sockio.h> 61#include <pci/pcireg.h> 62#include <pci/pcivar.h> 63#include <vm/vm.h> 64#include <vm/pmap.h> 65#include <machine/clock.h> 66 67#include <net/if.h> 68#include <net/if_sync.h> 69 70#include <netgraph/ng_message.h> 71#include <netgraph/ng_sample.h> 72#include <netgraph/netgraph.h> 73 74#ifndef NMN 75/* Most machines don't support more than 4 busmaster PCI slots, if even that many */ 76#define NMN 4 77#endif 78 79/* From: PEB 20321 data sheet, p187, table 22 */ 80struct m32xreg { 81 u_int32_t conf, cmd, stat, imask; 82 u_int32_t fill10, piqba, piql, fill1c; 83 u_int32_t mode1, mode2, ccba, txpoll; 84 u_int32_t tiqba, tiql, riqba, riql; 85 u_int32_t lconf, lccba, fill48, ltran; 86 u_int32_t ltiqba, ltiql, lriqba, lriql; 87 u_int32_t lreg0, lreg1, lreg2, lreg3; 88 u_int32_t lreg4, lreg5, lre6, lstat; 89 u_int32_t gpdir, gpdata, gpod, fill8c; 90 u_int32_t ssccon, sscbr, ssctb, sscrb; 91 u_int32_t ssccse, sscim, fillab, fillac; 92 u_int32_t iomcon1, iomcon2, iomstat, fillbc; 93 u_int32_t iomcit0, iomcit1, iomcir0, iomcir1; 94 u_int32_t iomtmo, iomrmo, filld8, filldc; 95 u_int32_t mbcmd, mbdata1, mbdata2, mbdata3; 96 u_int32_t mbdata4, mbdata5, mbdata6, mbdata7; 97}; 98 99/* From: PEB 2254 data sheet, p80, table 10 */ 100struct f54wreg { 101 u_int16_t xfifo; 102 u_int8_t cmdr, mode, rah1, rah2, ral1, ral2; 103 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 104 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 105 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 106 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 107 u_int8_t test1, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr3; 108 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 109 u_int8_t lim2, fill39[7]; 110 u_int8_t fill40[8]; 111 u_int8_t fill48[8]; 112 u_int8_t fill50[8]; 113 u_int8_t fill58[8]; 114 u_int8_t dec, fill61, test2, fill63[5]; 115 u_int8_t fill68[8]; 116 u_int8_t xs[16]; 117}; 118 119/* From: PEB 2254 data sheet, p117, table 10 */ 120struct f54rreg { 121 u_int16_t rfifo; 122 u_int8_t fill2, mode, rah1, rah2, ral1, ral2; 123 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 124 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 125 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 126 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 127 u_int8_t test, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr13; 128 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 129 u_int8_t lim2, fill39[7]; 130 u_int8_t fill40[8]; 131 u_int8_t fill48[4], frs0, frs1, rsw, rsp; 132 u_int16_t fec, cvc, cec1, ebc; 133 u_int16_t cec2, cec3; 134 u_int8_t rsa4, rsa5, rsa6, rsa7; 135 u_int8_t rsa8, rsa6s, tsr0, tsr1, sis, rsis; 136 u_int16_t rbc; 137 u_int8_t isr0, isr1, isr2, isr3, fill6c, fill6d, gis, vstr; 138 u_int8_t rs[16]; 139}; 140 141/* Transmit & receive descriptors */ 142struct trxd { 143 u_int32_t flags; 144 vm_offset_t next; 145 vm_offset_t data; 146 u_int32_t status; /* only used for receive */ 147 struct mbuf *m; /* software use only */ 148 struct trxd *vnext; /* software use only */ 149}; 150 151/* Channel specification */ 152struct cspec { 153 u_int32_t flags; 154 vm_offset_t rdesc; 155 vm_offset_t tdesc; 156 u_int32_t itbs; 157}; 158 159struct m32_mem { 160 vm_offset_t csa; 161 u_int32_t ccb; 162 u_int32_t reserve1[2]; 163 u_int32_t ts[M32_TS]; 164 struct cspec cs[M32_CHAN]; 165 vm_offset_t crxd[M32_CHAN]; 166 vm_offset_t ctxd[M32_CHAN]; 167}; 168 169struct softc; 170struct sockaddr; 171struct rtentry; 172 173static const char* mn_probe (pcici_t tag, pcidi_t type); 174static void mn_attach (pcici_t tag, int unit); 175static u_long mn_count; 176static void mn_create_channel(struct softc *sc, int chan); 177static int mn_reset(struct softc *sc); 178static struct trxd * mn_alloc_desc(void); 179static void mn_free_desc(struct trxd *dp); 180static void mn_intr(void *xsc); 181static void m32_dump(struct softc *sc); 182static void f54_dump(struct softc *sc); 183static u_int32_t mn_parse_ts(const char *s); 184static void mn_fmt_ts(char *p, u_int32_t ts); 185 186static ng_constructor_t ngmn_constructor; 187static ng_rcvmsg_t ngmn_rcvmsg; 188static ng_shutdown_t ngmn_shutdown; 189static ng_newhook_t ngmn_newhook; 190static ng_connect_t ngmn_connect; 191static ng_rcvdata_t ngmn_rcvdata; 192static ng_disconnect_t ngmn_disconnect; 193 194static struct ng_type mntypestruct = { 195 NG_VERSION, 196 NG_MN_NODE_TYPE, 197 NULL, 198 ngmn_constructor, 199 ngmn_rcvmsg, 200 ngmn_shutdown, 201 ngmn_newhook, 202 NULL, 203 ngmn_connect, 204 ngmn_rcvdata, 205 ngmn_rcvdata, 206 ngmn_disconnect 207}; 208 209static MALLOC_DEFINE(M_MN, "mn", "Mx driver related"); 210 211#define NIQB 64 212 213struct softc; 214 215struct schan { 216 enum {DOWN, UP} state; 217 struct softc *sc; 218 int chan; 219 struct if_sync sif; 220 u_int32_t ts; 221 char name[8]; 222 struct trxd *r1, *rl; 223 struct trxd *x1, *xl; 224 hook_p hook; 225 226 time_t last_recv; 227 time_t last_rxerr; 228 time_t last_xmit; 229 230 u_long rx_error; 231 232 u_long short_error; 233 u_long crc_error; 234 u_long dribble_error; 235 u_long long_error; 236 u_long abort_error; 237 u_long overflow_error; 238 239 int last_error; 240 int prev_error; 241}; 242 243static struct softc { 244 int unit; 245 pcici_t tag; 246 vm_offset_t m0v, m0p, m1v, m1p; 247 struct m32xreg *m32x; 248 struct f54wreg *f54w; 249 struct f54rreg *f54r; 250 struct m32_mem m32_mem; 251 u_int32_t tiqb[NIQB]; 252 u_int32_t riqb[NIQB]; 253 u_int32_t piqb[NIQB]; 254 u_int32_t ltiqb[NIQB]; 255 u_int32_t lriqb[NIQB]; 256 char name[8]; 257 u_int32_t falc_irq, falc_state, framer_state; 258 struct schan *ch[M32_CHAN]; 259 char nodename[NG_NODELEN + 1]; 260 node_p node; 261 262 u_long cnt_fec; 263 u_long cnt_cvc; 264 u_long cnt_cec1; 265 u_long cnt_ebc; 266 u_long cnt_cec2; 267 u_long cnt_cec3; 268 u_long cnt_rbc; 269} *softc[NMN]; 270 271static int 272ngmn_constructor(node_p *nodep) 273{ 274 275 return (EINVAL); 276} 277 278static int 279ngmn_shutdown(node_p nodep) 280{ 281 282 return (EINVAL); 283} 284 285static int 286ngmn_rcvmsg(node_p node, struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp) 287{ 288 struct softc *sc; 289 struct schan *sch; 290 char *arg; 291 int pos, i; 292 293 sc = node->private; 294 295 if (msg->header.typecookie != NGM_GENERIC_COOKIE || 296 msg->header.cmd != NGM_TEXT_STATUS) { 297 if (resp) 298 *resp = NULL; 299 FREE(msg, M_NETGRAPH); 300 return (EINVAL); 301 } 302 NG_MKRESPONSE(*resp, msg, sizeof(struct ng_mesg) + NG_TEXTRESPONSE, 303 M_NOWAIT); 304 if (*resp == NULL) { 305 FREE(msg, M_NETGRAPH); 306 return (ENOMEM); 307 } 308 arg = (char *)(*resp)->data; 309 pos = 0; 310 pos += sprintf(pos + arg,"Framer status %b;\n", sc->framer_state, "\20" 311 "\40LOS\37AIS\36LFA\35RRA" 312 "\34AUXP\33NMF\32LMFA\31frs0.0" 313 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 314 "\24TS16LFA\23frs1.2\22XLS\21XLO" 315 "\20RS1\17rsw.6\16RRA\15RY0" 316 "\14RY1\13RY2\12RY3\11RY4" 317 "\10SI1\7SI2\6rsp.5\5rsp.4" 318 "\4rsp.3\3RSIF\2RS13\1RS15"); 319 pos += sprintf(pos + arg," Framing errors: %lu", sc->cnt_fec); 320 pos += sprintf(pos + arg," Code Violations: %lu\n", sc->cnt_cvc); 321 322 pos += sprintf(pos + arg," Falc State %b;\n", sc->falc_state, "\20" 323 "\40LOS\37AIS\36LFA\35RRA" 324 "\34AUXP\33NMF\32LMFA\31frs0.0" 325 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 326 "\24TS16LFA\23frs1.2\22XLS\21XLO" 327 "\20RS1\17rsw.6\16RRA\15RY0" 328 "\14RY1\13RY2\12RY3\11RY4" 329 "\10SI1\7SI2\6rsp.5\5rsp.4" 330 "\4rsp.3\3RSIF\2RS13\1RS15"); 331 pos += sprintf(pos + arg, " Falc IRQ %b\n", sc->falc_irq, "\20" 332 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 333 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 334 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 335 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 336 for (i = 0; i < M32_CHAN; i++) { 337 if (!sc->ch[i]) 338 continue; 339 sch = sc->ch[i]; 340 341 pos += sprintf(arg + pos, " Chan %d <%s> ", 342 i, sch->hook->name); 343 344 pos += sprintf(arg + pos, " Last Rx: "); 345 if (sch->last_recv) 346 pos += sprintf(arg + pos, "%lu s", time_second - sch->last_recv); 347 else 348 pos += sprintf(arg + pos, "never"); 349 350 pos += sprintf(arg + pos, ", last RxErr: "); 351 if (sch->last_rxerr) 352 pos += sprintf(arg + pos, "%lu s", time_second - sch->last_rxerr); 353 else 354 pos += sprintf(arg + pos, "never"); 355 356 pos += sprintf(arg + pos, ", last Tx: "); 357 if (sch->last_xmit) 358 pos += sprintf(arg + pos, "%lu s\n", time_second - sch->last_xmit); 359 else 360 pos += sprintf(arg + pos, "never\n"); 361 362 pos += sprintf(arg + pos, " RX error(s) %lu", sch->rx_error); 363 pos += sprintf(arg + pos, " Short: %lu", sch->short_error); 364 pos += sprintf(arg + pos, " CRC: %lu", sch->crc_error); 365 pos += sprintf(arg + pos, " Mod8: %lu", sch->dribble_error); 366 pos += sprintf(arg + pos, " Long: %lu", sch->long_error); 367 pos += sprintf(arg + pos, " Abort: %lu", sch->abort_error); 368 pos += sprintf(arg + pos, " Overflow: %lu\n", sch->overflow_error); 369 370 pos += sprintf(arg + pos, " Last error: %b Prev error: %b\n", 371 sch->last_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN", 372 sch->prev_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN"); 373 } 374 (*resp)->header.arglen = pos + 1; 375 FREE(msg, M_NETGRAPH); 376 return (0); 377} 378 379static int 380ngmn_newhook(node_p node, hook_p hook, const char *name) 381{ 382 u_int32_t ts, chan; 383 struct softc *sc; 384 385 sc = node->private; 386 387 if (name[0] != 't' || name[1] != 's') 388 return (EINVAL); 389 390 ts = mn_parse_ts(name + 2); 391 if (ts == 0) 392 return (EINVAL); 393 chan = ffs(ts) - 1; 394 if (sc->ch[chan]) 395 return (EBUSY); 396 mn_create_channel(sc, chan); /* Create the first channel */ 397 sc->ch[chan]->ts = ts; 398 sc->ch[chan]->hook = hook; 399 hook->private = sc->ch[chan]; 400 return(0); 401} 402 403 404static struct trxd *mn_desc_free; 405 406static struct trxd * 407mn_alloc_desc(void) 408{ 409 struct trxd *dp; 410 411 dp = mn_desc_free; 412 if (dp) 413 mn_desc_free = dp->vnext; 414 else 415 dp = (struct trxd *)malloc(sizeof *dp, M_MN, M_NOWAIT); 416 return (dp); 417} 418 419static void 420mn_free_desc(struct trxd *dp) 421{ 422 dp->vnext = mn_desc_free; 423 mn_desc_free = dp; 424} 425 426static u_int32_t 427mn_parse_ts(const char *s) 428{ 429 unsigned r; 430 int i, j; 431 const char *p; 432 433 r = 0; 434 j = 0; 435 while(*s) { 436 i = strtol(s, &p, 0); 437 if (i < 1 || i > 31) 438 return (0); 439 while (j && j < i) { 440 r |= 1 << j++; 441 } 442 j = 0; 443 r |= 1 << i; 444 if (*p == ',') { 445 s = p + 1; 446 continue; 447 } else if (*p == '-') { 448 j = i; 449 s = p + 1; 450 continue; 451 } else if (!*p) { 452 break; 453 } else { 454 return (0); 455 } 456 } 457 return (r); 458} 459 460static void 461mn_fmt_ts(char *p, u_int32_t ts) 462{ 463 char *s; 464 int j; 465 466 s = ""; 467 ts &= 0xfffffffe; 468 for (j = 1; j < 32; j++) { 469 if (!(ts & (1 << j))) 470 continue; 471 sprintf(p, "%s%d", s, j); 472 p += strlen(p); 473 s = ","; 474 if (!(ts & (1 << (j+1)))) 475 continue; 476 for (; j < 32; j++) 477 if (!(ts & (1 << (j+1)))) 478 break; 479 sprintf(p, "-%d", j); 480 p += strlen(p); 481 s = ","; 482 } 483} 484 485/* 486 * OUTPUT 487 */ 488 489static int 490ngmn_rcvdata(hook_p hook, struct mbuf *m, meta_p meta) 491{ 492 struct mbuf *m2; 493 struct trxd *dp, *dp2; 494 struct schan *sch; 495 struct softc *sc; 496 int chan, pitch, len; 497 498 sch = hook->private; 499 sc = sch->sc; 500 chan = sch->chan; 501 502 if (sc->ch[chan]->state != UP) { 503 NG_FREE_DATA(m, meta); 504 return (0); 505 } 506 NG_FREE_META(meta); 507 pitch = 0; 508 m2 = m; 509 dp2 = sc->ch[chan]->xl; 510 len = m->m_pkthdr.len; 511 while (len) { 512 dp = mn_alloc_desc(); 513 if (!dp) { 514 pitch++; 515 m_freem(m); 516 sc->ch[chan]->xl = dp2; 517 dp = dp2->vnext; 518 while (dp) { 519 dp2 = dp->vnext; 520 mn_free_desc(dp); 521 dp = dp2; 522 } 523 sc->ch[chan]->xl->vnext = 0; 524 break; 525 } 526 dp->data = vtophys(m2->m_data); 527 dp->flags = m2->m_len << 16; 528 dp->flags += 1; 529 len -= m2->m_len; 530 dp->next = vtophys(dp); 531 dp->vnext = 0; 532 sc->ch[chan]->xl->next = vtophys(dp); 533 sc->ch[chan]->xl->vnext = dp; 534 sc->ch[chan]->xl = dp; 535 if (!len) { 536 dp->m = m; 537 dp->flags |= 0xc0000000; 538 dp2->flags &= ~0x40000000; 539 } else { 540 dp->m = 0; 541 m2 = m2->m_next; 542 } 543 } 544 if (pitch) 545 printf("%s%d: Short on mem, pitched %d packets\n", 546 sc->name, chan, pitch); 547 return (0); 548} 549 550/* 551 * OPEN 552 */ 553static int 554ngmn_connect(hook_p hook) 555{ 556 int i, nts, chan; 557 struct trxd *dp, *dp2; 558 struct mbuf *m; 559 struct softc *sc; 560 struct schan *sch; 561 u_int32_t u; 562 563 sch = hook->private; 564 chan = sch->chan; 565 sc = sch->sc; 566 567 printf("%s: OPEN{ state = %d\n", sch->name, sch->state); 568 if (sch->state == UP) 569 return (0); 570 sch->state = UP; 571 572 /* Count and configure the timeslots for this channel */ 573 for (nts = i = 0; i < 32; i++) 574 if (sch->ts & (1 << i)) { 575 sc->m32_mem.ts[i] = 0x00ff00ff | 576 (chan << 24) | (chan << 8); 577 nts++; 578 } 579 580 /* Init the receiver & xmitter to HDLC */ 581 sc->m32_mem.cs[chan].flags = 0x80e90006; 582 /* Allocate two buffers per timeslot */ 583 sc->m32_mem.cs[chan].itbs = nts * 2; 584 585 /* Setup a transmit chain with one descriptor */ 586 /* XXX: we actually send a 1 byte packet */ 587 dp = mn_alloc_desc(); 588 MGETHDR(m, M_WAIT, MT_DATA); 589 dp->m = m; 590 dp->flags = 0xc0000000 + (1 << 16); 591 dp->next = vtophys(dp); 592 dp->vnext = 0; 593 dp->data = vtophys(sc->name); 594 sc->m32_mem.cs[chan].tdesc = vtophys(dp); 595 sc->ch[chan]->x1 = dp; 596 sc->ch[chan]->xl = dp; 597 598 /* Setup a receive chain with 5 + NTS descriptors */ 599 600 dp = mn_alloc_desc(); 601 MGETHDR(m, M_WAIT, MT_DATA); 602 MCLGET(m, M_WAIT); 603 dp->m = m; 604 dp->data = vtophys(m->m_data); 605 dp->flags = 0x40000000; 606 dp->flags += 1600 << 16; 607 dp->next = vtophys(dp); 608 dp->vnext = 0; 609 sc->ch[chan]->rl = dp; 610 611 for (i = 0; i < (nts + 10); i++) { 612 dp2 = dp; 613 dp = mn_alloc_desc(); 614 MGETHDR(m, M_WAIT, MT_DATA); 615 MCLGET(m, M_WAIT); 616 dp->m = m; 617 dp->data = vtophys(m->m_data); 618 dp->flags = 0x00000000; 619 dp->flags += 1600 << 16; 620 dp->next = vtophys(dp2); 621 dp->vnext = dp2; 622 } 623 sc->m32_mem.cs[chan].rdesc = vtophys(dp); 624 sc->ch[chan]->r1 = dp; 625 626 /* Initialize this channel */ 627 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 628 sc->m32x->cmd = 0x1; 629 DELAY(30); 630 u = sc->m32x->stat; 631 if (!(u & 1)) 632 printf("%s: init chan %d stat %08x\n", sc->name, chan, u); 633 sc->m32x->stat = 1; 634 635 printf("%s%d: TLS} state = %d\n", sc->name, chan, sc->ch[chan]->state); 636 return (0); 637} 638 639/* 640 * CLOSE 641 */ 642static int 643ngmn_disconnect(hook_p hook) 644{ 645 int chan, i; 646 struct softc *sc; 647 struct schan *sch; 648 struct trxd *dp, *dp2; 649 u_int32_t u; 650 651 sch = hook->private; 652 chan = sch->chan; 653 sc = sch->sc; 654 655 printf("%s: TLF{ state = %d\n", sch->name, sch->state); 656 if (sch->state == DOWN) 657 return (0); 658 sch->state = DOWN; 659 660 /* Set receiver & transmitter off */ 661 sc->m32_mem.cs[chan].flags = 0x80920006; 662 sc->m32_mem.cs[chan].itbs = 0; 663 664 /* free the timeslots */ 665 for (i = 0; i < 32; i++) 666 if (sc->ch[chan]->ts & (1 << i)) 667 sc->m32_mem.ts[i] = 0x20002000; 668 669 /* Initialize this channel */ 670 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 671 sc->m32x->cmd = 0x1; 672 DELAY(30); 673 u = sc->m32x->stat; 674 if (!(u & 1)) 675 printf("%s: zap chan %d stat %08x\n", sc->name, chan, u); 676 sc->m32x->stat = 1; 677 678 /* Free all receive descriptors and mbufs */ 679 for (dp = sc->ch[chan]->r1; dp ; dp = dp2) { 680 if (dp->m) 681 m_freem(dp->m); 682 sc->ch[chan]->r1 = dp2 = dp->vnext; 683 mn_free_desc(dp); 684 } 685 686 /* Free all transmit descriptors and mbufs */ 687 for (dp = sc->ch[chan]->x1; dp ; dp = dp2) { 688 if (dp->m) 689 m_freem(dp->m); 690 sc->ch[chan]->x1 = dp2 = dp->vnext; 691 mn_free_desc(dp); 692 } 693 printf("%s%d: TLF} state = %d\n", sc->name, chan, sc->ch[chan]->state); 694 return(0); 695} 696 697/* 698 * Create a new channel. 699 */ 700static void 701mn_create_channel(struct softc *sc, int chan) 702{ 703 struct schan *sch; 704 705 sch = sc->ch[chan] = (struct schan *)malloc(sizeof *sc->ch[chan], 706 M_MN, M_WAITOK); 707 bzero(sch, sizeof *sch); 708 sch->sc = sc; 709 sch->state = DOWN; 710 sch->chan = chan; 711 sprintf(sch->name, "%s%d", sc->name, chan); 712 return; 713} 714 715/* 716 * Dump Munich32x state 717 */ 718static void 719m32_dump(struct softc *sc) 720{ 721 u_int32_t *tp4; 722 int i, j; 723 724 printf("mn%d: MUNICH32X dump\n", sc->unit); 725 tp4 = (u_int32_t *)sc->m0v; 726 for(j = 0; j < 64; j += 8) { 727 printf("%02x", j * sizeof *tp4); 728 for(i = 0; i < 8; i++) 729 printf(" %08x", tp4[i+j]); 730 printf("\n"); 731 } 732 for(j = 0; j < M32_CHAN; j++) { 733 if (!sc->ch[j]) 734 continue; 735 printf("CH%d: state %d ts %08x", 736 j, sc->ch[j]->state, sc->ch[j]->ts); 737 printf(" %08x %08x %08x %08x %08x %08x\n", 738 sc->m32_mem.cs[j].flags, 739 sc->m32_mem.cs[j].rdesc, 740 sc->m32_mem.cs[j].tdesc, 741 sc->m32_mem.cs[j].itbs, 742 sc->m32_mem.crxd[j], 743 sc->m32_mem.ctxd[j] ); 744 } 745} 746 747/* 748 * Dump Falch54 state 749 */ 750static void 751f54_dump(struct softc *sc) 752{ 753 u_int8_t *tp1; 754 int i, j; 755 756 printf("%s: FALC54 dump\n", sc->name); 757 tp1 = (u_int8_t *)sc->m1v; 758 for(j = 0; j < 128; j += 16) { 759 printf("%s: %02x |", sc->name, j * sizeof *tp1); 760 for(i = 0; i < 16; i++) 761 printf(" %02x", tp1[i+j]); 762 printf("\n"); 763 } 764} 765 766/* 767 * Init Munich32x 768 */ 769static void 770m32_init(struct softc *sc) 771{ 772 773 sc->m32x->conf = 0x00000000; 774 sc->m32x->mode1 = 0x81048000 + 1600; /* XXX: temp */ 775#if 1 776 sc->m32x->mode2 = 0x00000081; 777 sc->m32x->txpoll = 0xffffffff; 778#else 779 sc->m32x->mode2 = 0x00000101; 780#endif 781 sc->m32x->lconf = 0x6060009B; 782 sc->m32x->imask = 0x00000000; 783} 784 785/* 786 * Init the Falc54 787 */ 788static void 789f54_init(struct softc *sc) 790{ 791 sc->f54w->ipc = 0x07; 792 793 sc->f54w->xpm0 = 0xbd; 794 sc->f54w->xpm1 = 0x03; 795 sc->f54w->xpm2 = 0x00; 796 797 sc->f54w->imr0 = 0x18; /* RMB, CASC */ 798 sc->f54w->imr1 = 0x08; /* XMB */ 799 sc->f54w->imr2 = 0x00; 800 sc->f54w->imr3 = 0x38; /* LMFA16, AIS16, RA16 */ 801 sc->f54w->imr4 = 0x00; 802 803 sc->f54w->fmr0 = 0xf0; /* X: HDB3, R: HDB3 */ 804 sc->f54w->fmr1 = 0x0e; /* Send CRC4, 2Mbit, ECM */ 805 sc->f54w->fmr2 = 0x03; /* Auto Rem-Alarm, Auto resync */ 806 807 sc->f54w->lim1 = 0xb0; /* XCLK=8kHz, .62V threshold */ 808 sc->f54w->pcd = 0x0a; 809 sc->f54w->pcr = 0x15; 810 sc->f54w->xsw = 0x9f; /* fmr4 */ 811 sc->f54w->xsp = 0x1c; /* fmr5 */ 812 sc->f54w->xc0 = 0x07; 813 sc->f54w->xc1 = 0x3d; 814 sc->f54w->rc0 = 0x05; 815 sc->f54w->rc1 = 0x00; 816 sc->f54w->cmdr = 0x51; 817} 818 819static int 820mn_reset(struct softc *sc) 821{ 822 u_int32_t u; 823 int i, j; 824 825 u = 0; 826 for(i = 5; i >= 0; i-- ) { 827 sc->m32x->gpdir = i; 828 for (j = 0; j < 8; j ++) { 829 sc->m32x->gpdata = j; 830 u += sc->m32x->gpdata; 831 } 832 } 833 if (u != 0xe4) { 834 printf("mn%d: WARNING: Controller failed to initialize.\n", 835 sc->unit); 836#if 0 837 return (0); 838#endif 839 printf("mn%d: %x\n", sc->unit, u); 840 } 841 842 sc->m32x->ccba = vtophys(&sc->m32_mem.csa); 843 sc->m32_mem.csa = vtophys(&sc->m32_mem.ccb); 844 845 bzero(sc->tiqb, sizeof sc->tiqb); 846 sc->m32x->tiqba = vtophys(&sc->tiqb); 847 sc->m32x->tiql = NIQB / 16 - 1; 848 849 bzero(sc->riqb, sizeof sc->riqb); 850 sc->m32x->riqba = vtophys(&sc->riqb); 851 sc->m32x->riql = NIQB / 16 - 1; 852 853 bzero(sc->ltiqb, sizeof sc->ltiqb); 854 sc->m32x->ltiqba = vtophys(&sc->ltiqb); 855 sc->m32x->ltiql = NIQB / 16 - 1; 856 857 bzero(sc->lriqb, sizeof sc->lriqb); 858 sc->m32x->lriqba = vtophys(&sc->lriqb); 859 sc->m32x->lriql = NIQB / 16 - 1; 860 861 bzero(sc->piqb, sizeof sc->piqb); 862 sc->m32x->piqba = vtophys(&sc->piqb); 863 sc->m32x->piql = NIQB / 16 - 1; 864 865 m32_init(sc); 866 f54_init(sc); 867 868 u = sc->m32x->stat; 869 sc->m32x->stat = u; 870 sc->m32_mem.ccb = 0x4; 871 sc->m32x->cmd = 0x1; 872 DELAY(1000); 873 u = sc->m32x->stat; 874 sc->m32x->stat = u; 875 876 /* set all timeslots to known state */ 877 for (i = 0; i < 32; i++) 878 sc->m32_mem.ts[i] = 0x20002000; 879 880 if (!(u & 1)) { 881 printf( 882"mn%d: WARNING: Controller failed the PCI bus-master test.\n" 883"mn%d: WARNING: Use a PCI slot which can support bus-master cards.\n", 884 sc->unit, sc->unit); 885 return (0); 886 } 887 return (1); 888} 889 890/* 891 * FALC54 interrupt handling 892 */ 893static void 894f54_intr(struct softc *sc) 895{ 896 unsigned g, u, s; 897 898 g = sc->f54r->gis; 899 u = sc->f54r->isr0 << 24; 900 u |= sc->f54r->isr1 << 16; 901 u |= sc->f54r->isr2 << 8; 902 u |= sc->f54r->isr3; 903 sc->falc_irq = u; 904 /* don't chat about the 1 sec heart beat */ 905 if (u & ~0x40) { 906#if 0 907 printf("%s*: FALC54 IRQ GIS:%02x %b\n", sc->name, g, u, "\20" 908 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 909 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 910 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 911 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 912#endif 913 s = sc->f54r->frs0 << 24; 914 s |= sc->f54r->frs1 << 16; 915 s |= sc->f54r->rsw << 8; 916 s |= sc->f54r->rsp; 917 sc->falc_state = s; 918 919 s &= ~0x01844038; /* undefined or static bits */ 920 s &= ~0x00009fc7; /* bits we don't care about */ 921 s &= ~0x00780000; /* XXX: TS16 related */ 922 s &= ~0x06000000; /* XXX: Multiframe related */ 923#if 0 924 printf("%s*: FALC54 Status %b\n", sc->name, s, "\20" 925 "\40LOS\37AIS\36LFA\35RRA\34AUXP\33NMF\32LMFA\31frs0.0" 926 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS\24TS16LFA\23frs1.2\22XLS\21XLO" 927 "\20RS1\17rsw.6\16RRA\15RY0\14RY1\13RY2\12RY3\11RY4" 928 "\10SI1\7SI2\6rsp.5\5rsp.4\4rsp.3\3RSIF\2RS13\1RS15"); 929#endif 930 if (s != sc->framer_state) { 931#if 0 932 for (i = 0; i < M32_CHAN; i++) { 933 if (!sc->ch[i]) 934 continue; 935 sp = &sc->ch[i]->ifsppp; 936 if (!(sp->pp_if.if_flags & IFF_UP)) 937 continue; 938 if (s) 939 timeout((timeout_t *)sp->pp_down, sp, 1 * hz); 940 else 941 timeout((timeout_t *)sp->pp_up, sp, 1 * hz); 942 } 943#endif 944 sc->framer_state = s; 945 } 946 } 947 /* Once per second check error counters */ 948 /* XXX: not clear if this is actually ok */ 949 if (!(u & 0x40)) 950 return; 951 sc->cnt_fec += sc->f54r->fec; 952 sc->cnt_cvc += sc->f54r->cvc; 953 sc->cnt_cec1 += sc->f54r->cec1; 954 sc->cnt_ebc += sc->f54r->ebc; 955 sc->cnt_cec2 += sc->f54r->cec2; 956 sc->cnt_cec3 += sc->f54r->cec3; 957 sc->cnt_rbc += sc->f54r->rbc; 958} 959 960/* 961 * Transmit interrupt for one channel 962 */ 963static void 964mn_tx_intr(struct softc *sc, u_int32_t vector) 965{ 966 u_int32_t chan; 967 struct trxd *dp; 968 struct mbuf *m; 969 970 chan = vector & 0x1f; 971 if (!sc->ch[chan]) 972 return; 973 if (sc->ch[chan]->state != UP) { 974 printf("%s: tx_intr when not UP\n", sc->name); 975 return; 976 } 977 for (;;) { 978 dp = sc->ch[chan]->x1; 979 if (vtophys(dp) == sc->m32_mem.ctxd[chan]) 980 return; 981 m = dp->m; 982 if (m) 983 m_freem(m); 984 sc->ch[chan]->last_xmit = time_second; 985 sc->ch[chan]->x1 = dp->vnext; 986 mn_free_desc(dp); 987 } 988} 989 990/* 991 * Receive interrupt for one channel 992 */ 993static void 994mn_rx_intr(struct softc *sc, u_int32_t vector) 995{ 996 u_int32_t chan, err; 997 struct trxd *dp; 998 struct mbuf *m; 999 struct schan *sch; 1000 1001 chan = vector & 0x1f; 1002 if (!sc->ch[chan]) 1003 return; 1004 sch = sc->ch[chan]; 1005 if (sch->state != UP) { 1006 printf("%s: rx_intr when not UP\n", sc->name); 1007 return; 1008 } 1009 vector &= ~0x1f; 1010 if (vector == 0x30000b00) 1011 sch->rx_error++; 1012 for (;;) { 1013 dp = sch->r1; 1014 if (vtophys(dp) == sc->m32_mem.crxd[chan]) 1015 return; 1016 m = dp->m; 1017 dp->m = 0; 1018 m->m_pkthdr.len = m->m_len = (dp->status >> 16) & 0x1fff; 1019 err = (dp->status >> 8) & 0xff; 1020 if (!err) { 1021 ng_queue_data(sch->hook, m, NULL); 1022 sch->last_recv = time_second; 1023 m = 0; 1024 /* we could be down by now... */ 1025 if (sch->state != UP) 1026 return; 1027 } else if (err & 0x40) { 1028 sch->short_error++; 1029 } else if (err & 0x10) { 1030 sch->crc_error++; 1031 } else if (err & 0x08) { 1032 sch->dribble_error++; 1033 } else if (err & 0x04) { 1034 sch->long_error++; 1035 } else if (err & 0x02) { 1036 sch->abort_error++; 1037 } else if (err & 0x01) { 1038 sch->overflow_error++; 1039 } 1040 if (err) { 1041 sch->last_rxerr = time_second; 1042 sch->prev_error = sch->last_error; 1043 sch->last_error = err; 1044 } 1045 1046 sc->ch[chan]->r1 = dp->vnext; 1047 1048 /* Replenish desc + mbuf supplies */ 1049 if (!m) { 1050 MGETHDR(m, M_DONTWAIT, MT_DATA); 1051 if (m == NULL) { 1052 mn_free_desc(dp); 1053 return; 1054 } 1055 MCLGET(m, M_DONTWAIT); 1056 if((m->m_flags & M_EXT) == 0) { 1057 mn_free_desc(dp); 1058 return; 1059 } 1060 } 1061 dp->m = m; 1062 dp->data = vtophys(m->m_data); 1063 dp->flags = 0x40000000; 1064 dp->flags += 1600 << 16; 1065 dp->next = vtophys(dp); 1066 dp->vnext = 0; 1067 sc->ch[chan]->rl->next = vtophys(dp); 1068 sc->ch[chan]->rl->vnext = dp; 1069 sc->ch[chan]->rl->flags &= ~0x40000000; 1070 sc->ch[chan]->rl = dp; 1071 } 1072} 1073 1074 1075/* 1076 * Interupt handler 1077 */ 1078 1079static void 1080mn_intr(void *xsc) 1081{ 1082 struct softc *sc; 1083 u_int32_t stat, lstat, u; 1084 int i, j; 1085 1086 sc = xsc; 1087 stat = sc->m32x->stat; 1088 lstat = sc->m32x->lstat; 1089#if 0 1090 if (!stat && !(lstat & 2)) 1091 return; 1092#endif 1093 1094 if (stat & ~0xc200) { 1095 printf("%s*: I stat=%08x lstat=%08x\n", sc->name, stat, lstat); 1096 } 1097 1098 if ((stat & 0x200) || (lstat & 2)) 1099 f54_intr(sc); 1100 1101 for (j = i = 0; i < 64; i ++) { 1102 u = sc->riqb[i]; 1103 if (u) { 1104 sc->riqb[i] = 0; 1105 mn_rx_intr(sc, u); 1106 if ((u & ~0x1f) == 0x30000800 || (u & ~0x1f) == 0x30000b00) 1107 continue; 1108 u &= ~0x30000400; /* bits we don't care about */ 1109 if ((u & ~0x1f) == 0x00000900) 1110 continue; 1111 if (!(u & ~0x1f)) 1112 continue; 1113 if (!j) 1114 printf("%s*: RIQB:", sc->name); 1115 printf(" [%d]=%08x", i, u); 1116 j++; 1117 } 1118 } 1119 if (j) 1120 printf("\n"); 1121 1122 for (j = i = 0; i < 64; i ++) { 1123 u = sc->tiqb[i]; 1124 if (u) { 1125 sc->tiqb[i] = 0; 1126 mn_tx_intr(sc, u); 1127 if ((u & ~0x1f) == 0x20000800) 1128 continue; 1129 u &= ~0x20000000; /* bits we don't care about */ 1130 if (!u) 1131 continue; 1132 if (!j) 1133 printf("%s*: TIQB:", sc->name); 1134 printf(" [%d]=%08x", i, u); 1135 j++; 1136 } 1137 } 1138 if (j) 1139 printf("\n"); 1140 sc->m32x->stat = stat; 1141} 1142 1143static void 1144mn_timeout(void *xsc) 1145{ 1146 static int round = 0; 1147 struct softc *sc; 1148 1149 mn_intr(xsc); 1150 sc = xsc; 1151 timeout(mn_timeout, xsc, 1000); 1152 round++; 1153 if (round == 2) { 1154 sc->m32_mem.ccb = 0x00008004; 1155 sc->m32x->cmd = 0x1; 1156 } else if (round > 2) { 1157 printf("%s: timeout\n", sc->name); 1158 } 1159} 1160 1161/* 1162 * PCI initialization stuff 1163 */ 1164 1165static struct pci_device mn_device = { 1166 "mn", 1167 mn_probe, 1168 mn_attach, 1169 &mn_count, 1170 NULL 1171}; 1172 1173#ifdef COMPAT_PCI_DRIVER 1174COMPAT_PCI_DRIVER(ti, mn_device); 1175#else 1176DATA_SET(pcidevice_set, mn_device); 1177#endif /* COMPAT_PCI_DRIVER */ 1178 1179static const char* 1180mn_probe (pcici_t tag, pcidi_t typea) 1181{ 1182 u_int id = pci_conf_read(tag, PCI_ID_REG); 1183 1184 if (sizeof (struct m32xreg) != 256) { 1185 printf("MN: sizeof(struct m32xreg) = %d, should have been 256\n", sizeof (struct m32xreg)); 1186 return (0); 1187 } 1188 if (sizeof (struct f54rreg) != 128) { 1189 printf("MN: sizeof(struct f54rreg) = %d, should have been 128\n", sizeof (struct f54rreg)); 1190 return (0); 1191 } 1192 if (sizeof (struct f54wreg) != 128) { 1193 printf("MN: sizeof(struct f54wreg) = %d, should have been 128\n", sizeof (struct f54wreg)); 1194 return (0); 1195 } 1196 1197 if (id == 0x2101110a) 1198 return "Munich32X E1/T1 HDLC Controller"; 1199 1200 return 0; 1201} 1202 1203static void 1204mn_attach (pcici_t tag, int unit) 1205{ 1206 struct softc *sc; 1207 u_int32_t u; 1208 u_int32_t pci_class; 1209 static int once; 1210 1211 if (!once) { 1212 if (ng_newtype(&mntypestruct)) 1213 printf("ng_newtype failed\n"); 1214 once++; 1215 } 1216 1217 sc = (struct softc *)malloc(sizeof *sc, M_MN, M_WAITOK); 1218 softc[unit] = sc; 1219 bzero(sc, sizeof *sc); 1220 1221 sc->tag = tag; 1222 sc->unit = unit; 1223 sprintf(sc->name, "mn%c", 'A' + unit); 1224 1225 if (!pci_map_int(tag, mn_intr, sc, &net_imask)) { 1226 printf("mn%d: could not map interrupt\n", sc->unit); 1227 return; 1228 } 1229 pci_map_mem(tag, PCI_MAP_REG_START, &sc->m0v, &sc->m0p); 1230 pci_map_mem(tag, PCI_MAP_REG_START + 4, &sc->m1v, &sc->m1p); 1231 1232 u = pci_conf_read(tag, PCIR_COMMAND); 1233 pci_conf_write(tag, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); 1234 pci_conf_write(tag, PCIR_COMMAND, 0x02800046); 1235 1236 pci_class = pci_conf_read(tag, PCI_CLASS_REG); 1237 1238 sc->m32x = (struct m32xreg *) sc->m0v; 1239 sc->f54w = (struct f54wreg *) sc->m1v; 1240 sc->f54r = (struct f54rreg *) sc->m1v; 1241 1242 /* We must reset before poking at FALC54 registers */ 1243 u = mn_reset(sc); 1244 if (!u) 1245 return; 1246 1247 printf("mn%d: Munich32X", sc->unit); 1248 switch (pci_class & 0xff) { 1249 case 0x13: 1250 printf(" Rev 1.3"); 1251 break; 1252 default: 1253 printf(" Rev 0x%x\n", pci_class & 0xff); 1254 } 1255 printf(", Falc54"); 1256 switch (sc->f54r->vstr) { 1257 case 0: 1258 printf(" Rev < 1.3\n"); 1259 break; 1260 case 1: 1261 printf(" Rev 1.3\n"); 1262 break; 1263 case 2: 1264 printf(" Rev 1.4\n"); 1265 break; 1266 case 0x10: 1267 printf("-LH Rev 1.1\n"); 1268 break; 1269 default: 1270 printf(" Rev 0x%x\n", sc->f54r->vstr); 1271 } 1272 1273 if (ng_make_node_common(&mntypestruct, &sc->node) != 0) { 1274 printf("ng_make_node_common failed\n"); 1275 return; 1276 } 1277 sc->node->private = sc; 1278 sprintf(sc->nodename, "%s%d", NG_MN_NODE_TYPE, sc->unit); 1279 if (ng_name_node(sc->node, sc->nodename)) { 1280 ng_rmnode(sc->node); 1281 ng_unref(sc->node); 1282 return; 1283 } 1284 1285 return; 1286} 1287#endif /* KERNEL */ 1288