if_mn.c revision 101336
1246149Ssjg/* 2246149Ssjg * ---------------------------------------------------------------------------- 3261212Ssjg * "THE BEER-WARE LICENSE" (Revision 42): 4261212Ssjg * <phk@FreeBSD.org> wrote this file. As long as you retain this notice you 5246149Ssjg * can do whatever you want with this stuff. If we meet some day, and you think 6246149Ssjg * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp 7246149Ssjg * ---------------------------------------------------------------------------- 8246149Ssjg * 9246149Ssjg * $Id: if_mn.c,v 1.1 1999/02/01 13:06:40 phk Exp $ 10246149Ssjg * 11246149Ssjg * Driver for Siemens reference design card "Easy321-R1". 12246149Ssjg * 13246149Ssjg * This card contains a FALC54 E1/T1 framer and a MUNICH32X 32-channel HDLC 14246149Ssjg * controller. 15246149Ssjg * 16246149Ssjg * The driver supports E1 mode with up to 31 channels. We send CRC4 but don't 17246149Ssjg * check it coming in. 18246149Ssjg * 19246149Ssjg * The FALC54 and MUNICH32X have far too many registers and weird modes for 20246149Ssjg * comfort, so I have not bothered typing it all into a "fooreg.h" file, 21246149Ssjg * you will (badly!) need the documentation anyway if you want to mess with 22246149Ssjg * this gadget. 23246149Ssjg * 24246149Ssjg * $FreeBSD: head/sys/pci/if_mn.c 101336 2002-08-04 20:50:50Z phk $ 25246149Ssjg */ 26246149Ssjg 27246149Ssjg/* 28246149Ssjg * Stuff to describe the MUNIC32X and FALC54 chips. 29246149Ssjg */ 30246149Ssjg 31246149Ssjg#define M32_CHAN 32 /* We have 32 channels */ 32246149Ssjg#define M32_TS 32 /* We have 32 timeslots */ 33246149Ssjg 34246149Ssjg#define NG_MN_NODE_TYPE "mn" 35246149Ssjg 36246149Ssjg#include <sys/param.h> 37246149Ssjg#include <sys/kernel.h> 38246149Ssjg#include <sys/sysctl.h> 39246149Ssjg#include <sys/bus.h> 40281812Ssjg#include <sys/mbuf.h> 41246149Ssjg#include <sys/systm.h> 42249033Ssjg#include <sys/malloc.h> 43249033Ssjg 44246149Ssjg#include <pci/pcireg.h> 45246149Ssjg#include <pci/pcivar.h> 46246149Ssjg#include "pci_if.h" 47246149Ssjg 48246149Ssjg#include <machine/bus.h> 49246149Ssjg#include <machine/resource.h> 50246149Ssjg 51246149Ssjg#include <sys/rman.h> 52246149Ssjg 53246149Ssjg#include <vm/vm.h> 54246149Ssjg#include <vm/pmap.h> 55246149Ssjg 56246149Ssjg#include <netgraph/ng_message.h> 57246149Ssjg#include <netgraph/netgraph.h> 58246149Ssjg 59246149Ssjg 60246149Ssjgstatic int mn_maxlatency = 1000; 61246149SsjgSYSCTL_INT(_debug, OID_AUTO, mn_maxlatency, CTLFLAG_RW, 62246149Ssjg &mn_maxlatency, 0, 63246149Ssjg "The number of milliseconds a packet is allowed to spend in the output queue. " 64246149Ssjg "If the output queue is longer than this number of milliseconds when the packet " 65246149Ssjg "arrives for output, the packet will be dropped." 66246149Ssjg); 67246149Ssjg 68246149Ssjg#ifndef NMN 69246149Ssjg/* Most machines don't support more than 4 busmaster PCI slots, if even that many */ 70246149Ssjg#define NMN 4 71246149Ssjg#endif 72246149Ssjg 73246149Ssjg/* From: PEB 20321 data sheet, p187, table 22 */ 74246149Ssjgstruct m32xreg { 75246149Ssjg u_int32_t conf, cmd, stat, imask; 76246149Ssjg u_int32_t fill10, piqba, piql, fill1c; 77246149Ssjg u_int32_t mode1, mode2, ccba, txpoll; 78246149Ssjg u_int32_t tiqba, tiql, riqba, riql; 79246149Ssjg u_int32_t lconf, lccba, fill48, ltran; 80246149Ssjg u_int32_t ltiqba, ltiql, lriqba, lriql; 81246149Ssjg u_int32_t lreg0, lreg1, lreg2, lreg3; 82253883Ssjg u_int32_t lreg4, lreg5, lre6, lstat; 83246149Ssjg u_int32_t gpdir, gpdata, gpod, fill8c; 84246149Ssjg u_int32_t ssccon, sscbr, ssctb, sscrb; 85246149Ssjg u_int32_t ssccse, sscim, fillab, fillac; 86246149Ssjg u_int32_t iomcon1, iomcon2, iomstat, fillbc; 87246149Ssjg u_int32_t iomcit0, iomcit1, iomcir0, iomcir1; 88246149Ssjg u_int32_t iomtmo, iomrmo, filld8, filldc; 89246149Ssjg u_int32_t mbcmd, mbdata1, mbdata2, mbdata3; 90246149Ssjg u_int32_t mbdata4, mbdata5, mbdata6, mbdata7; 91246149Ssjg}; 92246149Ssjg 93246149Ssjg/* From: PEB 2254 data sheet, p80, table 10 */ 94246149Ssjgstruct f54wreg { 95261212Ssjg u_int16_t xfifo; 96246149Ssjg u_int8_t cmdr, mode, rah1, rah2, ral1, ral2; 97246149Ssjg u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 98261212Ssjg u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 99246149Ssjg u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 100246149Ssjg u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 101246149Ssjg u_int8_t test1, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr3; 102261212Ssjg u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 103246149Ssjg u_int8_t lim2, fill39[7]; 104246149Ssjg u_int8_t fill40[8]; 105246149Ssjg u_int8_t fill48[8]; 106246149Ssjg u_int8_t fill50[8]; 107246149Ssjg u_int8_t fill58[8]; 108246149Ssjg u_int8_t dec, fill61, test2, fill63[5]; 109246149Ssjg u_int8_t fill68[8]; 110246149Ssjg u_int8_t xs[16]; 111246149Ssjg}; 112253883Ssjg 113253883Ssjg/* From: PEB 2254 data sheet, p117, table 10 */ 114253883Ssjgstruct f54rreg { 115281812Ssjg u_int16_t rfifo; 116281812Ssjg u_int8_t fill2, mode, rah1, rah2, ral1, ral2; 117253883Ssjg u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 118253883Ssjg u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 119246149Ssjg u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 120246149Ssjg u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 121246149Ssjg u_int8_t test, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr13; 122246149Ssjg u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 123246149Ssjg u_int8_t lim2, fill39[7]; 124246149Ssjg u_int8_t fill40[8]; 125246149Ssjg u_int8_t fill48[4], frs0, frs1, rsw, rsp; 126246149Ssjg u_int16_t fec, cvc, cec1, ebc; 127246149Ssjg u_int16_t cec2, cec3; 128246149Ssjg u_int8_t rsa4, rsa5, rsa6, rsa7; 129246149Ssjg u_int8_t rsa8, rsa6s, tsr0, tsr1, sis, rsis; 130246149Ssjg u_int16_t rbc; 131246149Ssjg u_int8_t isr0, isr1, isr2, isr3, fill6c, fill6d, gis, vstr; 132250837Ssjg u_int8_t rs[16]; 133250837Ssjg}; 134250837Ssjg 135250837Ssjg/* Transmit & receive descriptors */ 136250837Ssjgstruct trxd { 137250837Ssjg u_int32_t flags; 138246149Ssjg vm_offset_t next; 139246149Ssjg vm_offset_t data; 140246149Ssjg u_int32_t status; /* only used for receive */ 141246149Ssjg struct mbuf *m; /* software use only */ 142246149Ssjg struct trxd *vnext; /* software use only */ 143246149Ssjg}; 144246149Ssjg 145246149Ssjg/* Channel specification */ 146281812Ssjgstruct cspec { 147246149Ssjg u_int32_t flags; 148246149Ssjg vm_offset_t rdesc; 149246149Ssjg vm_offset_t tdesc; 150246149Ssjg u_int32_t itbs; 151246149Ssjg}; 152246149Ssjg 153246149Ssjgstruct m32_mem { 154246149Ssjg vm_offset_t csa; 155246149Ssjg u_int32_t ccb; 156246149Ssjg u_int32_t reserve1[2]; 157246149Ssjg u_int32_t ts[M32_TS]; 158246149Ssjg struct cspec cs[M32_CHAN]; 159246149Ssjg vm_offset_t crxd[M32_CHAN]; 160246149Ssjg vm_offset_t ctxd[M32_CHAN]; 161246149Ssjg}; 162246149Ssjg 163246149Ssjgstruct softc; 164249033Ssjgstruct sockaddr; 165246149Ssjgstruct rtentry; 166250837Ssjg 167250837Ssjgstatic int mn_probe (device_t self); 168250837Ssjgstatic int mn_attach (device_t self); 169246149Ssjgstatic void mn_create_channel(struct softc *sc, int chan); 170268437Ssjgstatic int mn_reset(struct softc *sc); 171246149Ssjgstatic struct trxd * mn_alloc_desc(void); 172246149Ssjgstatic void mn_free_desc(struct trxd *dp); 173246149Ssjgstatic void mn_intr(void *xsc); 174246149Ssjgstatic u_int32_t mn_parse_ts(const char *s, int *nbit); 175246149Ssjg#ifdef notyet 176246149Ssjgstatic void m32_dump(struct softc *sc); 177246149Ssjgstatic void f54_dump(struct softc *sc); 178246149Ssjgstatic void mn_fmt_ts(char *p, u_int32_t ts); 179246149Ssjg#endif /* notyet */ 180246149Ssjgstatic void f54_init(struct softc *sc); 181246149Ssjg 182246149Ssjgstatic ng_constructor_t ngmn_constructor; 183281812Ssjgstatic ng_rcvmsg_t ngmn_rcvmsg; 184281812Ssjgstatic ng_shutdown_t ngmn_shutdown; 185281812Ssjgstatic ng_newhook_t ngmn_newhook; 186281812Ssjgstatic ng_connect_t ngmn_connect; 187246149Ssjgstatic ng_rcvdata_t ngmn_rcvdata; 188246149Ssjgstatic ng_disconnect_t ngmn_disconnect; 189246149Ssjg 190246149Ssjgstatic struct ng_type mntypestruct = { 191246149Ssjg NG_ABI_VERSION, 192246149Ssjg NG_MN_NODE_TYPE, 193246149Ssjg NULL, 194246149Ssjg ngmn_constructor, 195246149Ssjg ngmn_rcvmsg, 196246149Ssjg ngmn_shutdown, 197249033Ssjg ngmn_newhook, 198250837Ssjg NULL, 199250837Ssjg ngmn_connect, 200249033Ssjg ngmn_rcvdata, 201249033Ssjg ngmn_disconnect, 202249033Ssjg NULL 203253883Ssjg}; 204249033Ssjg 205246149Ssjgstatic MALLOC_DEFINE(M_MN, "mn", "Mx driver related"); 206246149Ssjg 207246149Ssjg#define NIQB 64 208246149Ssjg 209246149Ssjgstruct schan { 210246149Ssjg enum {DOWN, UP} state; 211246149Ssjg struct softc *sc; 212246149Ssjg int chan; 213246149Ssjg u_int32_t ts; 214246149Ssjg char name[8]; 215246149Ssjg struct trxd *r1, *rl; 216246149Ssjg struct trxd *x1, *xl; 217246149Ssjg hook_p hook; 218246149Ssjg 219246149Ssjg time_t last_recv; 220250837Ssjg time_t last_rxerr; 221249033Ssjg time_t last_xmit; 222250837Ssjg 223250837Ssjg u_long rx_error; 224250837Ssjg 225249033Ssjg u_long short_error; 226246149Ssjg u_long crc_error; 227249033Ssjg u_long dribble_error; 228249033Ssjg u_long long_error; 229249033Ssjg u_long abort_error; 230249033Ssjg u_long overflow_error; 231249033Ssjg 232249033Ssjg int last_error; 233246149Ssjg int prev_error; 234246149Ssjg 235246149Ssjg u_long tx_pending; 236246149Ssjg u_long tx_limit; 237246149Ssjg}; 238246149Ssjg 239246149Ssjgenum framing {WHOKNOWS, E1, E1U, T1, T1U}; 240246149Ssjg 241249033Ssjgstruct softc { 242249033Ssjg int unit; 243249033Ssjg device_t dev; 244281812Ssjg struct resource *irq; 245281812Ssjg void *intrhand; 246281812Ssjg enum framing framing; 247246149Ssjg int nhooks; 248261212Ssjg void *m0v, *m1v; 249261212Ssjg vm_offset_t m0p, m1p; 250261212Ssjg struct m32xreg *m32x; 251281812Ssjg struct f54wreg *f54w; 252246149Ssjg struct f54rreg *f54r; 253246149Ssjg struct m32_mem m32_mem; 254246149Ssjg u_int32_t tiqb[NIQB]; 255246149Ssjg u_int32_t riqb[NIQB]; 256246149Ssjg u_int32_t piqb[NIQB]; 257261212Ssjg u_int32_t ltiqb[NIQB]; 258246149Ssjg u_int32_t lriqb[NIQB]; 259246149Ssjg char name[8]; 260246149Ssjg u_int32_t falc_irq, falc_state, framer_state; 261246149Ssjg struct schan *ch[M32_CHAN]; 262246149Ssjg char nodename[NG_NODELEN + 1]; 263261212Ssjg node_p node; 264246149Ssjg 265246149Ssjg u_long cnt_fec; 266246149Ssjg u_long cnt_cvc; 267249033Ssjg u_long cnt_cec1; 268281812Ssjg u_long cnt_ebc; 269249033Ssjg u_long cnt_cec2; 270246149Ssjg u_long cnt_cec3; 271253883Ssjg u_long cnt_rbc; 272246149Ssjg}; 273246149Ssjg 274246149Ssjgstatic int 275246149Ssjgngmn_constructor(node_p node) 276246149Ssjg{ 277246149Ssjg 278246149Ssjg return (EINVAL); 279246149Ssjg} 280246149Ssjg 281246149Ssjgstatic int 282246149Ssjgngmn_shutdown(node_p nodep) 283246149Ssjg{ 284246149Ssjg 285246149Ssjg return (EINVAL); 286246149Ssjg} 287246149Ssjg 288246149Ssjgstatic void 289246149Ssjgngmn_config(node_p node, char *set, char *ret) 290246149Ssjg{ 291246149Ssjg struct softc *sc; 292246149Ssjg enum framing wframing; 293246149Ssjg 294261212Ssjg sc = NG_NODE_PRIVATE(node); 295246149Ssjg 296246149Ssjg if (set != NULL) { 297246149Ssjg if (!strncmp(set, "line ", 5)) { 298246149Ssjg wframing = sc->framing; 299246149Ssjg if (!strcmp(set, "line e1")) { 300246149Ssjg wframing = E1; 301246149Ssjg } else if (!strcmp(set, "line e1u")) { 302246149Ssjg wframing = E1U; 303246149Ssjg } else { 304246149Ssjg strcat(ret, "ENOGROK\n"); 305261212Ssjg return; 306246149Ssjg } 307246149Ssjg if (wframing == sc->framing) 308268437Ssjg return; 309246149Ssjg if (sc->nhooks > 0) { 310246149Ssjg sprintf(ret, "Cannot change line when %d hooks open\n", sc->nhooks); 311246149Ssjg return; 312261212Ssjg } 313246149Ssjg sc->framing = wframing; 314246149Ssjg#if 1 315246149Ssjg f54_init(sc); 316246149Ssjg#else 317246149Ssjg mn_reset(sc); 318246149Ssjg#endif 319246149Ssjg } else { 320246149Ssjg printf("%s CONFIG SET [%s]\n", sc->nodename, set); 321261212Ssjg strcat(ret, "ENOGROK\n"); 322246149Ssjg return; 323261212Ssjg } 324246149Ssjg } 325246149Ssjg 326250837Ssjg} 327250837Ssjg 328246149Ssjgstatic int 329246149Ssjgngmn_rcvmsg(node_p node, item_p item, hook_p lasthook) 330246149Ssjg{ 331246149Ssjg struct softc *sc; 332246149Ssjg struct ng_mesg *resp = NULL; 333246149Ssjg struct schan *sch; 334246149Ssjg char *s, *r; 335246149Ssjg int pos, i; 336246149Ssjg struct ng_mesg *msg; 337246149Ssjg 338246149Ssjg NGI_GET_MSG(item, msg); 339246149Ssjg sc = NG_NODE_PRIVATE(node); 340246149Ssjg 341246149Ssjg if (msg->header.typecookie != NGM_GENERIC_COOKIE) { 342246149Ssjg NG_FREE_ITEM(item); 343246149Ssjg NG_FREE_MSG(msg); 344246149Ssjg return (EINVAL); 345261212Ssjg } 346246149Ssjg 347246149Ssjg if (msg->header.cmd != NGM_TEXT_CONFIG && 348246149Ssjg msg->header.cmd != NGM_TEXT_STATUS) { 349246149Ssjg NG_FREE_ITEM(item); 350253883Ssjg NG_FREE_MSG(msg); 351253883Ssjg return (EINVAL); 352253883Ssjg } 353253883Ssjg 354253883Ssjg NG_MKRESPONSE(resp, msg, sizeof(struct ng_mesg) + NG_TEXTRESPONSE, 355253883Ssjg M_NOWAIT); 356261212Ssjg if (resp == NULL) { 357253883Ssjg NG_FREE_ITEM(item); 358253883Ssjg NG_FREE_MSG(msg); 359246149Ssjg return (ENOMEM); 360246149Ssjg } 361246149Ssjg 362246149Ssjg if (msg->header.arglen) 363246149Ssjg s = (char *)msg->data; 364246149Ssjg else 365246149Ssjg s = NULL; 366246149Ssjg r = (char *)resp->data; 367246149Ssjg *r = '\0'; 368246149Ssjg 369246149Ssjg if (msg->header.cmd == NGM_TEXT_CONFIG) { 370246149Ssjg ngmn_config(node, s, r); 371246149Ssjg resp->header.arglen = strlen(r) + 1; 372281812Ssjg NG_RESPOND_MSG(i, node, item, resp); 373246149Ssjg FREE(msg, M_NETGRAPH); 374246149Ssjg return (0); 375246149Ssjg } 376281812Ssjg pos = 0; 377281812Ssjg pos += sprintf(pos + r,"Framer status %b;\n", sc->framer_state, "\20" 378281812Ssjg "\40LOS\37AIS\36LFA\35RRA" 379281812Ssjg "\34AUXP\33NMF\32LMFA\31frs0.0" 380281812Ssjg "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 381246149Ssjg "\24TS16LFA\23frs1.2\22XLS\21XLO" 382281812Ssjg "\20RS1\17rsw.6\16RRA\15RY0" 383281812Ssjg "\14RY1\13RY2\12RY3\11RY4" 384246149Ssjg "\10SI1\7SI2\6rsp.5\5rsp.4" 385246149Ssjg "\4rsp.3\3RSIF\2RS13\1RS15"); 386246149Ssjg pos += sprintf(pos + r," Framing errors: %lu", sc->cnt_fec); 387246149Ssjg pos += sprintf(pos + r," Code Violations: %lu\n", sc->cnt_cvc); 388246149Ssjg 389246149Ssjg pos += sprintf(pos + r," Falc State %b;\n", sc->falc_state, "\20" 390246149Ssjg "\40LOS\37AIS\36LFA\35RRA" 391281812Ssjg "\34AUXP\33NMF\32LMFA\31frs0.0" 392246149Ssjg "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 393261212Ssjg "\24TS16LFA\23frs1.2\22XLS\21XLO" 394246149Ssjg "\20RS1\17rsw.6\16RRA\15RY0" 395246149Ssjg "\14RY1\13RY2\12RY3\11RY4" 396246149Ssjg "\10SI1\7SI2\6rsp.5\5rsp.4" 397246149Ssjg "\4rsp.3\3RSIF\2RS13\1RS15"); 398246149Ssjg pos += sprintf(pos + r, " Falc IRQ %b\n", sc->falc_irq, "\20" 399253883Ssjg "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 400246149Ssjg "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 401246149Ssjg "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 402246149Ssjg "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 403246149Ssjg for (i = 0; i < M32_CHAN; i++) { 404246149Ssjg if (!sc->ch[i]) 405253883Ssjg continue; 406246149Ssjg sch = sc->ch[i]; 407246149Ssjg 408246149Ssjg pos += sprintf(r + pos, " Chan %d <%s> ", 409246149Ssjg i, NG_HOOK_NAME(sch->hook)); 410261212Ssjg 411246149Ssjg pos += sprintf(r + pos, " Last Rx: "); 412246149Ssjg if (sch->last_recv) 413246149Ssjg pos += sprintf(r + pos, "%lu s", 414246149Ssjg (unsigned long)(time_second - sch->last_recv)); 415246149Ssjg else 416246149Ssjg pos += sprintf(r + pos, "never"); 417246149Ssjg 418246149Ssjg pos += sprintf(r + pos, ", last RxErr: "); 419246149Ssjg if (sch->last_rxerr) 420246149Ssjg pos += sprintf(r + pos, "%lu s", 421246149Ssjg (unsigned long)(time_second - sch->last_rxerr)); 422246149Ssjg else 423246149Ssjg pos += sprintf(r + pos, "never"); 424281812Ssjg 425246149Ssjg pos += sprintf(r + pos, ", last Tx: "); 426246149Ssjg if (sch->last_xmit) 427261212Ssjg pos += sprintf(r + pos, "%lu s\n", 428246149Ssjg (unsigned long)(time_second - sch->last_xmit)); 429246149Ssjg else 430246149Ssjg pos += sprintf(r + pos, "never\n"); 431246149Ssjg 432246149Ssjg pos += sprintf(r + pos, " RX error(s) %lu", sch->rx_error); 433246149Ssjg pos += sprintf(r + pos, " Short: %lu", sch->short_error); 434281812Ssjg pos += sprintf(r + pos, " CRC: %lu", sch->crc_error); 435246149Ssjg pos += sprintf(r + pos, " Mod8: %lu", sch->dribble_error); 436281812Ssjg pos += sprintf(r + pos, " Long: %lu", sch->long_error); 437246149Ssjg pos += sprintf(r + pos, " Abort: %lu", sch->abort_error); 438246149Ssjg pos += sprintf(r + pos, " Overflow: %lu\n", sch->overflow_error); 439246149Ssjg 440246149Ssjg pos += sprintf(r + pos, " Last error: %b Prev error: %b\n", 441246149Ssjg sch->last_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN", 442246149Ssjg sch->prev_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN"); 443246149Ssjg pos += sprintf(r + pos, " Xmit bytes pending %ld\n", 444246149Ssjg sch->tx_pending); 445246149Ssjg } 446246149Ssjg resp->header.arglen = pos + 1; 447246149Ssjg 448246149Ssjg /* Take care of synchronous response, if any */ 449246149Ssjg NG_RESPOND_MSG(i, node, item, resp); 450281812Ssjg NG_FREE_MSG(msg); 451246149Ssjg return (0); 452261212Ssjg} 453246149Ssjg 454246149Ssjgstatic int 455246149Ssjgngmn_newhook(node_p node, hook_p hook, const char *name) 456246149Ssjg{ 457261212Ssjg u_int32_t ts, chan; 458246149Ssjg struct softc *sc; 459246149Ssjg int nbit; 460246149Ssjg 461281812Ssjg sc = NG_NODE_PRIVATE(node); 462281812Ssjg 463281812Ssjg if (name[0] != 't' || name[1] != 's') 464281812Ssjg return (EINVAL); 465281812Ssjg 466281812Ssjg ts = mn_parse_ts(name + 2, &nbit); 467246149Ssjg printf("%d bits %x\n", nbit, ts); 468281812Ssjg if (sc->framing == E1 && (ts & 1)) 469281812Ssjg return (EINVAL); 470281812Ssjg if (sc->framing == E1U && nbit != 32) 471281812Ssjg return (EINVAL); 472281812Ssjg if (ts == 0) 473281812Ssjg return (EINVAL); 474281812Ssjg if (sc->framing == E1) 475281812Ssjg chan = ffs(ts) - 1; 476281812Ssjg else 477281812Ssjg chan = 1; 478281812Ssjg if (!sc->ch[chan]) 479281812Ssjg mn_create_channel(sc, chan); 480281812Ssjg else if (sc->ch[chan]->state == UP) 481281812Ssjg return (EBUSY); 482281812Ssjg sc->ch[chan]->ts = ts; 483281812Ssjg sc->ch[chan]->hook = hook; 484246149Ssjg sc->ch[chan]->tx_limit = nbit * 8; 485281812Ssjg NG_HOOK_SET_PRIVATE(hook, sc->ch[chan]); 486281812Ssjg sc->nhooks++; 487281812Ssjg return(0); 488281812Ssjg} 489281812Ssjg 490281812Ssjg 491281812Ssjgstatic struct trxd *mn_desc_free; 492281812Ssjg 493281812Ssjgstatic struct trxd * 494281812Ssjgmn_alloc_desc(void) 495281812Ssjg{ 496281812Ssjg struct trxd *dp; 497281812Ssjg 498281812Ssjg dp = mn_desc_free; 499281812Ssjg if (dp) 500281812Ssjg mn_desc_free = dp->vnext; 501281812Ssjg else 502281812Ssjg dp = (struct trxd *)malloc(sizeof *dp, M_MN, M_NOWAIT); 503281812Ssjg return (dp); 504281812Ssjg} 505281812Ssjg 506281812Ssjgstatic void 507281812Ssjgmn_free_desc(struct trxd *dp) 508281812Ssjg{ 509281812Ssjg dp->vnext = mn_desc_free; 510281812Ssjg mn_desc_free = dp; 511281812Ssjg} 512281812Ssjg 513281812Ssjgstatic u_int32_t 514281812Ssjgmn_parse_ts(const char *s, int *nbit) 515281812Ssjg{ 516281812Ssjg unsigned r; 517281812Ssjg int i, j; 518246149Ssjg char *p; 519281812Ssjg 520281812Ssjg r = 0; 521281812Ssjg j = -1; 522281812Ssjg *nbit = 0; 523281812Ssjg while(*s) { 524281812Ssjg i = strtol(s, &p, 0); 525281812Ssjg if (i < 0 || i > 31) 526281812Ssjg return (0); 527281812Ssjg while (j != -1 && j < i) { 528281812Ssjg r |= 1 << j++; 529281812Ssjg (*nbit)++; 530281812Ssjg } 531281812Ssjg j = -1; 532281812Ssjg r |= 1 << i; 533281812Ssjg (*nbit)++; 534281812Ssjg if (*p == ',') { 535281812Ssjg s = p + 1; 536281812Ssjg continue; 537281812Ssjg } else if (*p == '-') { 538281812Ssjg j = i + 1; 539246149Ssjg s = p + 1; 540281812Ssjg continue; 541246149Ssjg } else if (!*p) { 542281812Ssjg break; 543281812Ssjg } else { 544281812Ssjg return (0); 545281812Ssjg } 546281812Ssjg } 547281812Ssjg return (r); 548281812Ssjg} 549281812Ssjg 550281812Ssjg#ifdef notyet 551246149Ssjgstatic void 552246149Ssjgmn_fmt_ts(char *p, u_int32_t ts) 553246149Ssjg{ 554246149Ssjg char *s; 555246149Ssjg int j; 556246149Ssjg 557281812Ssjg s = ""; 558246149Ssjg ts &= 0xffffffff; 559246149Ssjg for (j = 0; j < 32; j++) { 560246149Ssjg if (!(ts & (1 << j))) 561246149Ssjg continue; 562246149Ssjg sprintf(p, "%s%d", s, j); 563281812Ssjg p += strlen(p); 564246149Ssjg s = ","; 565246149Ssjg if (!(ts & (1 << (j+1)))) 566246149Ssjg continue; 567246149Ssjg for (; j < 32; j++) 568281812Ssjg if (!(ts & (1 << (j+1)))) 569246149Ssjg break; 570246149Ssjg sprintf(p, "-%d", j); 571246149Ssjg p += strlen(p); 572250837Ssjg s = ","; 573250837Ssjg } 574246149Ssjg} 575246149Ssjg#endif /* notyet */ 576246149Ssjg 577246149Ssjg/* 578281812Ssjg * OUTPUT 579246149Ssjg */ 580246149Ssjg 581246149Ssjgstatic int 582246149Ssjgngmn_rcvdata(hook_p hook, item_p item) 583246149Ssjg{ 584246149Ssjg struct mbuf *m2; 585246149Ssjg struct trxd *dp, *dp2; 586246149Ssjg struct schan *sch; 587246149Ssjg struct softc *sc; 588246149Ssjg int chan, pitch, len; 589246149Ssjg struct mbuf *m; 590246149Ssjg 591246149Ssjg sch = NG_HOOK_PRIVATE(hook); 592246149Ssjg sc = sch->sc; 593246149Ssjg chan = sch->chan; 594246149Ssjg 595246149Ssjg if (sch->state != UP) { 596281812Ssjg NG_FREE_ITEM(item); 597246149Ssjg return (0); 598246149Ssjg } 599246149Ssjg NGI_GET_M(item, m); 600246149Ssjg if (sch->tx_pending + m->m_pkthdr.len > sch->tx_limit * mn_maxlatency) { 601246149Ssjg NG_FREE_M(m); 602246149Ssjg NG_FREE_ITEM(item); 603250837Ssjg return (0); 604250837Ssjg } 605250837Ssjg NG_FREE_ITEM(item); 606246149Ssjg pitch = 0; 607246149Ssjg m2 = m; 608246149Ssjg dp2 = sc->ch[chan]->xl; 609246149Ssjg len = m->m_pkthdr.len; 610246149Ssjg while (len) { 611246149Ssjg dp = mn_alloc_desc(); 612246149Ssjg if (!dp) { 613246149Ssjg pitch++; 614246149Ssjg m_freem(m); 615246149Ssjg sc->ch[chan]->xl = dp2; 616246149Ssjg dp = dp2->vnext; 617246149Ssjg while (dp) { 618281812Ssjg dp2 = dp->vnext; 619246149Ssjg mn_free_desc(dp); 620250837Ssjg dp = dp2; 621250837Ssjg } 622250837Ssjg sc->ch[chan]->xl->vnext = 0; 623246149Ssjg break; 624246149Ssjg } 625246149Ssjg dp->data = vtophys(m2->m_data); 626246149Ssjg dp->flags = m2->m_len << 16; 627246149Ssjg dp->flags += 1; 628246149Ssjg len -= m2->m_len; 629246149Ssjg dp->next = vtophys(dp); 630246149Ssjg dp->vnext = 0; 631246149Ssjg sc->ch[chan]->xl->next = vtophys(dp); 632246149Ssjg sc->ch[chan]->xl->vnext = dp; 633246149Ssjg sc->ch[chan]->xl = dp; 634246149Ssjg if (!len) { 635246149Ssjg dp->m = m; 636246149Ssjg dp->flags |= 0xc0000000; 637246149Ssjg dp2->flags &= ~0x40000000; 638246149Ssjg } else { 639246149Ssjg dp->m = 0; 640246149Ssjg m2 = m2->m_next; 641246149Ssjg } 642250837Ssjg } 643250837Ssjg if (pitch) 644281812Ssjg printf("%s%d: Short on mem, pitched %d packets\n", 645281812Ssjg sc->name, chan, pitch); 646281812Ssjg else { 647246149Ssjg#if 0 648246149Ssjg printf("%d = %d + %d (%p)\n", 649246149Ssjg sch->tx_pending + m->m_pkthdr.len, 650246149Ssjg sch->tx_pending , m->m_pkthdr.len, m); 651246149Ssjg#endif 652246149Ssjg sch->tx_pending += m->m_pkthdr.len; 653246149Ssjg sc->m32x->txpoll &= ~(1 << chan); 654246149Ssjg } 655246149Ssjg return (0); 656246149Ssjg} 657246149Ssjg 658246149Ssjg/* 659246149Ssjg * OPEN 660246149Ssjg */ 661246149Ssjgstatic int 662246149Ssjgngmn_connect(hook_p hook) 663246149Ssjg{ 664246149Ssjg int i, nts, chan; 665246149Ssjg struct trxd *dp, *dp2; 666246149Ssjg struct mbuf *m; 667246149Ssjg struct softc *sc; 668246149Ssjg struct schan *sch; 669246149Ssjg u_int32_t u; 670246149Ssjg 671246149Ssjg sch = NG_HOOK_PRIVATE(hook); 672246149Ssjg chan = sch->chan; 673246149Ssjg sc = sch->sc; 674246149Ssjg 675246149Ssjg if (sch->state == UP) 676261212Ssjg return (0); 677261212Ssjg sch->state = UP; 678261212Ssjg 679261212Ssjg /* Count and configure the timeslots for this channel */ 680246149Ssjg for (nts = i = 0; i < 32; i++) 681281812Ssjg if (sch->ts & (1 << i)) { 682246149Ssjg sc->m32_mem.ts[i] = 0x00ff00ff | 683253883Ssjg (chan << 24) | (chan << 8); 684281812Ssjg nts++; 685281812Ssjg } 686253883Ssjg 687253883Ssjg /* Init the receiver & xmitter to HDLC */ 688253883Ssjg sc->m32_mem.cs[chan].flags = 0x80e90006; 689253883Ssjg /* Allocate two buffers per timeslot */ 690253883Ssjg if (nts == 32) 691281812Ssjg sc->m32_mem.cs[chan].itbs = 63; 692281812Ssjg else 693253883Ssjg sc->m32_mem.cs[chan].itbs = nts * 2; 694246149Ssjg 695281812Ssjg /* Setup a transmit chain with one descriptor */ 696261212Ssjg /* XXX: we actually send a 1 byte packet */ 697246149Ssjg dp = mn_alloc_desc(); 698261212Ssjg MGETHDR(m, M_TRYWAIT, MT_DATA); 699246149Ssjg if (m == NULL) 700246149Ssjg return ENOBUFS; 701246149Ssjg m->m_pkthdr.len = 0; 702246149Ssjg dp->m = m; 703246149Ssjg dp->flags = 0xc0000000 + (1 << 16); 704246149Ssjg dp->next = vtophys(dp); 705246149Ssjg dp->vnext = 0; 706246149Ssjg dp->data = vtophys(sc->name); 707246149Ssjg sc->m32_mem.cs[chan].tdesc = vtophys(dp); 708246149Ssjg sc->ch[chan]->x1 = dp; 709246149Ssjg sc->ch[chan]->xl = dp; 710246149Ssjg 711261212Ssjg /* Setup a receive chain with 5 + NTS descriptors */ 712246149Ssjg 713246149Ssjg dp = mn_alloc_desc(); 714 m = NULL; 715 MGETHDR(m, M_TRYWAIT, MT_DATA); 716 if (m == NULL) { 717 mn_free_desc(dp); 718 return (ENOBUFS); 719 } 720 MCLGET(m, M_TRYWAIT); 721 if ((m->m_flags & M_EXT) == 0) { 722 mn_free_desc(dp); 723 m_freem(m); 724 return (ENOBUFS); 725 } 726 dp->m = m; 727 dp->data = vtophys(m->m_data); 728 dp->flags = 0x40000000; 729 dp->flags += 1600 << 16; 730 dp->next = vtophys(dp); 731 dp->vnext = 0; 732 sc->ch[chan]->rl = dp; 733 734 for (i = 0; i < (nts + 10); i++) { 735 dp2 = dp; 736 dp = mn_alloc_desc(); 737 m = NULL; 738 MGETHDR(m, M_TRYWAIT, MT_DATA); 739 if (m == NULL) { 740 mn_free_desc(dp); 741 m_freem(m); 742 return (ENOBUFS); 743 } 744 MCLGET(m, M_TRYWAIT); 745 if ((m->m_flags & M_EXT) == 0) { 746 mn_free_desc(dp); 747 m_freem(m); 748 return (ENOBUFS); 749 } 750 dp->m = m; 751 dp->data = vtophys(m->m_data); 752 dp->flags = 0x00000000; 753 dp->flags += 1600 << 16; 754 dp->next = vtophys(dp2); 755 dp->vnext = dp2; 756 } 757 sc->m32_mem.cs[chan].rdesc = vtophys(dp); 758 sc->ch[chan]->r1 = dp; 759 760 /* Initialize this channel */ 761 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 762 sc->m32x->cmd = 0x1; 763 DELAY(1000); 764 u = sc->m32x->stat; 765 if (!(u & 1)) 766 printf("%s: init chan %d stat %08x\n", sc->name, chan, u); 767 sc->m32x->stat = 1; 768 /* probably not at splnet, force outward queueing */ 769 NG_HOOK_FORCE_QUEUE(NG_HOOK_PEER(hook)); 770 771 return (0); 772} 773 774/* 775 * CLOSE 776 */ 777static int 778ngmn_disconnect(hook_p hook) 779{ 780 int chan, i; 781 struct softc *sc; 782 struct schan *sch; 783 struct trxd *dp, *dp2; 784 u_int32_t u; 785 786 sch = NG_HOOK_PRIVATE(hook); 787 chan = sch->chan; 788 sc = sch->sc; 789 790 if (sch->state == DOWN) 791 return (0); 792 sch->state = DOWN; 793 794 /* Set receiver & transmitter off */ 795 sc->m32_mem.cs[chan].flags = 0x80920006; 796 sc->m32_mem.cs[chan].itbs = 0; 797 798 /* free the timeslots */ 799 for (i = 0; i < 32; i++) 800 if (sc->ch[chan]->ts & (1 << i)) 801 sc->m32_mem.ts[i] = 0x20002000; 802 803 /* Initialize this channel */ 804 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 805 sc->m32x->cmd = 0x1; 806 DELAY(30); 807 u = sc->m32x->stat; 808 if (!(u & 1)) 809 printf("%s: zap chan %d stat %08x\n", sc->name, chan, u); 810 sc->m32x->stat = 1; 811 812 /* Free all receive descriptors and mbufs */ 813 for (dp = sc->ch[chan]->r1; dp ; dp = dp2) { 814 if (dp->m) 815 m_freem(dp->m); 816 sc->ch[chan]->r1 = dp2 = dp->vnext; 817 mn_free_desc(dp); 818 } 819 820 /* Free all transmit descriptors and mbufs */ 821 for (dp = sc->ch[chan]->x1; dp ; dp = dp2) { 822 if (dp->m) { 823 sc->ch[chan]->tx_pending -= dp->m->m_pkthdr.len; 824 m_freem(dp->m); 825 } 826 sc->ch[chan]->x1 = dp2 = dp->vnext; 827 mn_free_desc(dp); 828 } 829 sc->nhooks--; 830 return(0); 831} 832 833/* 834 * Create a new channel. 835 */ 836static void 837mn_create_channel(struct softc *sc, int chan) 838{ 839 struct schan *sch; 840 841 sch = sc->ch[chan] = (struct schan *)malloc(sizeof *sc->ch[chan], 842 M_MN, M_WAITOK | M_ZERO); 843 sch->sc = sc; 844 sch->state = DOWN; 845 sch->chan = chan; 846 sprintf(sch->name, "%s%d", sc->name, chan); 847 return; 848} 849 850#ifdef notyet 851/* 852 * Dump Munich32x state 853 */ 854static void 855m32_dump(struct softc *sc) 856{ 857 u_int32_t *tp4; 858 int i, j; 859 860 printf("mn%d: MUNICH32X dump\n", sc->unit); 861 tp4 = (u_int32_t *)sc->m0v; 862 for(j = 0; j < 64; j += 8) { 863 printf("%02x", j * sizeof *tp4); 864 for(i = 0; i < 8; i++) 865 printf(" %08x", tp4[i+j]); 866 printf("\n"); 867 } 868 for(j = 0; j < M32_CHAN; j++) { 869 if (!sc->ch[j]) 870 continue; 871 printf("CH%d: state %d ts %08x", 872 j, sc->ch[j]->state, sc->ch[j]->ts); 873 printf(" %08x %08x %08x %08x %08x %08x\n", 874 sc->m32_mem.cs[j].flags, 875 sc->m32_mem.cs[j].rdesc, 876 sc->m32_mem.cs[j].tdesc, 877 sc->m32_mem.cs[j].itbs, 878 sc->m32_mem.crxd[j], 879 sc->m32_mem.ctxd[j] ); 880 } 881} 882 883/* 884 * Dump Falch54 state 885 */ 886static void 887f54_dump(struct softc *sc) 888{ 889 u_int8_t *tp1; 890 int i, j; 891 892 printf("%s: FALC54 dump\n", sc->name); 893 tp1 = (u_int8_t *)sc->m1v; 894 for(j = 0; j < 128; j += 16) { 895 printf("%s: %02x |", sc->name, j * sizeof *tp1); 896 for(i = 0; i < 16; i++) 897 printf(" %02x", tp1[i+j]); 898 printf("\n"); 899 } 900} 901#endif /* notyet */ 902 903/* 904 * Init Munich32x 905 */ 906static void 907m32_init(struct softc *sc) 908{ 909 910 sc->m32x->conf = 0x00000000; 911 sc->m32x->mode1 = 0x81048000 + 1600; /* XXX: temp */ 912#if 1 913 sc->m32x->mode2 = 0x00000081; 914 sc->m32x->txpoll = 0xffffffff; 915#elif 1 916 sc->m32x->mode2 = 0x00000081; 917 sc->m32x->txpoll = 0xffffffff; 918#else 919 sc->m32x->mode2 = 0x00000101; 920#endif 921 sc->m32x->lconf = 0x6060009B; 922 sc->m32x->imask = 0x00000000; 923} 924 925/* 926 * Init the Falc54 927 */ 928static void 929f54_init(struct softc *sc) 930{ 931 sc->f54w->ipc = 0x07; 932 933 sc->f54w->xpm0 = 0xbd; 934 sc->f54w->xpm1 = 0x03; 935 sc->f54w->xpm2 = 0x00; 936 937 sc->f54w->imr0 = 0x18; /* RMB, CASC */ 938 sc->f54w->imr1 = 0x08; /* XMB */ 939 sc->f54w->imr2 = 0x00; 940 sc->f54w->imr3 = 0x38; /* LMFA16, AIS16, RA16 */ 941 sc->f54w->imr4 = 0x00; 942 943 sc->f54w->fmr0 = 0xf0; /* X: HDB3, R: HDB3 */ 944 sc->f54w->fmr1 = 0x0e; /* Send CRC4, 2Mbit, ECM */ 945 if (sc->framing == E1) 946 sc->f54w->fmr2 = 0x03; /* Auto Rem-Alarm, Auto resync */ 947 else if (sc->framing == E1U) 948 sc->f54w->fmr2 = 0x33; /* dais, rtm, Auto Rem-Alarm, Auto resync */ 949 950 sc->f54w->lim1 = 0xb0; /* XCLK=8kHz, .62V threshold */ 951 sc->f54w->pcd = 0x0a; 952 sc->f54w->pcr = 0x15; 953 sc->f54w->xsw = 0x9f; /* fmr4 */ 954 if (sc->framing == E1) 955 sc->f54w->xsp = 0x1c; /* fmr5 */ 956 else if (sc->framing == E1U) 957 sc->f54w->xsp = 0x3c; /* tt0, fmr5 */ 958 sc->f54w->xc0 = 0x07; 959 sc->f54w->xc1 = 0x3d; 960 sc->f54w->rc0 = 0x05; 961 sc->f54w->rc1 = 0x00; 962 sc->f54w->cmdr = 0x51; 963} 964 965static int 966mn_reset(struct softc *sc) 967{ 968 u_int32_t u; 969 int i; 970 971 sc->m32x->ccba = vtophys(&sc->m32_mem.csa); 972 sc->m32_mem.csa = vtophys(&sc->m32_mem.ccb); 973 974 bzero(sc->tiqb, sizeof sc->tiqb); 975 sc->m32x->tiqba = vtophys(&sc->tiqb); 976 sc->m32x->tiql = NIQB / 16 - 1; 977 978 bzero(sc->riqb, sizeof sc->riqb); 979 sc->m32x->riqba = vtophys(&sc->riqb); 980 sc->m32x->riql = NIQB / 16 - 1; 981 982 bzero(sc->ltiqb, sizeof sc->ltiqb); 983 sc->m32x->ltiqba = vtophys(&sc->ltiqb); 984 sc->m32x->ltiql = NIQB / 16 - 1; 985 986 bzero(sc->lriqb, sizeof sc->lriqb); 987 sc->m32x->lriqba = vtophys(&sc->lriqb); 988 sc->m32x->lriql = NIQB / 16 - 1; 989 990 bzero(sc->piqb, sizeof sc->piqb); 991 sc->m32x->piqba = vtophys(&sc->piqb); 992 sc->m32x->piql = NIQB / 16 - 1; 993 994 m32_init(sc); 995 f54_init(sc); 996 997 u = sc->m32x->stat; 998 sc->m32x->stat = u; 999 sc->m32_mem.ccb = 0x4; 1000 sc->m32x->cmd = 0x1; 1001 DELAY(1000); 1002 u = sc->m32x->stat; 1003 sc->m32x->stat = u; 1004 1005 /* set all timeslots to known state */ 1006 for (i = 0; i < 32; i++) 1007 sc->m32_mem.ts[i] = 0x20002000; 1008 1009 if (!(u & 1)) { 1010 printf( 1011"mn%d: WARNING: Controller failed the PCI bus-master test.\n" 1012"mn%d: WARNING: Use a PCI slot which can support bus-master cards.\n", 1013 sc->unit, sc->unit); 1014 return (0); 1015 } 1016 return (1); 1017} 1018 1019/* 1020 * FALC54 interrupt handling 1021 */ 1022static void 1023f54_intr(struct softc *sc) 1024{ 1025 unsigned g, u, s; 1026 1027 g = sc->f54r->gis; 1028 u = sc->f54r->isr0 << 24; 1029 u |= sc->f54r->isr1 << 16; 1030 u |= sc->f54r->isr2 << 8; 1031 u |= sc->f54r->isr3; 1032 sc->falc_irq = u; 1033 /* don't chat about the 1 sec heart beat */ 1034 if (u & ~0x40) { 1035#if 0 1036 printf("%s*: FALC54 IRQ GIS:%02x %b\n", sc->name, g, u, "\20" 1037 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 1038 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 1039 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 1040 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 1041#endif 1042 s = sc->f54r->frs0 << 24; 1043 s |= sc->f54r->frs1 << 16; 1044 s |= sc->f54r->rsw << 8; 1045 s |= sc->f54r->rsp; 1046 sc->falc_state = s; 1047 1048 s &= ~0x01844038; /* undefined or static bits */ 1049 s &= ~0x00009fc7; /* bits we don't care about */ 1050 s &= ~0x00780000; /* XXX: TS16 related */ 1051 s &= ~0x06000000; /* XXX: Multiframe related */ 1052#if 0 1053 printf("%s*: FALC54 Status %b\n", sc->name, s, "\20" 1054 "\40LOS\37AIS\36LFA\35RRA\34AUXP\33NMF\32LMFA\31frs0.0" 1055 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS\24TS16LFA\23frs1.2\22XLS\21XLO" 1056 "\20RS1\17rsw.6\16RRA\15RY0\14RY1\13RY2\12RY3\11RY4" 1057 "\10SI1\7SI2\6rsp.5\5rsp.4\4rsp.3\3RSIF\2RS13\1RS15"); 1058#endif 1059 if (s != sc->framer_state) { 1060#if 0 1061 for (i = 0; i < M32_CHAN; i++) { 1062 if (!sc->ch[i]) 1063 continue; 1064 sp = &sc->ch[i]->ifsppp; 1065 if (!(sp->pp_if.if_flags & IFF_UP)) 1066 continue; 1067 if (s) 1068 timeout((timeout_t *)sp->pp_down, sp, 1 * hz); 1069 else 1070 timeout((timeout_t *)sp->pp_up, sp, 1 * hz); 1071 } 1072#endif 1073 sc->framer_state = s; 1074 } 1075 } 1076 /* Once per second check error counters */ 1077 /* XXX: not clear if this is actually ok */ 1078 if (!(u & 0x40)) 1079 return; 1080 sc->cnt_fec += sc->f54r->fec; 1081 sc->cnt_cvc += sc->f54r->cvc; 1082 sc->cnt_cec1 += sc->f54r->cec1; 1083 sc->cnt_ebc += sc->f54r->ebc; 1084 sc->cnt_cec2 += sc->f54r->cec2; 1085 sc->cnt_cec3 += sc->f54r->cec3; 1086 sc->cnt_rbc += sc->f54r->rbc; 1087} 1088 1089/* 1090 * Transmit interrupt for one channel 1091 */ 1092static void 1093mn_tx_intr(struct softc *sc, u_int32_t vector) 1094{ 1095 u_int32_t chan; 1096 struct trxd *dp; 1097 struct mbuf *m; 1098 1099 chan = vector & 0x1f; 1100 if (!sc->ch[chan]) 1101 return; 1102 if (sc->ch[chan]->state != UP) { 1103 printf("%s: tx_intr when not UP\n", sc->name); 1104 return; 1105 } 1106 for (;;) { 1107 dp = sc->ch[chan]->x1; 1108 if (vtophys(dp) == sc->m32_mem.ctxd[chan]) 1109 return; 1110 m = dp->m; 1111 if (m) { 1112#if 0 1113 printf("%d = %d - %d (%p)\n", 1114 sc->ch[chan]->tx_pending - m->m_pkthdr.len, 1115 sc->ch[chan]->tx_pending , m->m_pkthdr.len, m); 1116#endif 1117 sc->ch[chan]->tx_pending -= m->m_pkthdr.len; 1118 m_freem(m); 1119 } 1120 sc->ch[chan]->last_xmit = time_second; 1121 sc->ch[chan]->x1 = dp->vnext; 1122 mn_free_desc(dp); 1123 } 1124} 1125 1126/* 1127 * Receive interrupt for one channel 1128 */ 1129static void 1130mn_rx_intr(struct softc *sc, u_int32_t vector) 1131{ 1132 u_int32_t chan, err; 1133 struct trxd *dp; 1134 struct mbuf *m; 1135 struct schan *sch; 1136 1137 chan = vector & 0x1f; 1138 if (!sc->ch[chan]) 1139 return; 1140 sch = sc->ch[chan]; 1141 if (sch->state != UP) { 1142 printf("%s: rx_intr when not UP\n", sc->name); 1143 return; 1144 } 1145 vector &= ~0x1f; 1146 if (vector == 0x30000b00) 1147 sch->rx_error++; 1148 for (;;) { 1149 dp = sch->r1; 1150 if (vtophys(dp) == sc->m32_mem.crxd[chan]) 1151 return; 1152 m = dp->m; 1153 dp->m = 0; 1154 m->m_pkthdr.len = m->m_len = (dp->status >> 16) & 0x1fff; 1155 err = (dp->status >> 8) & 0xff; 1156 if (!err) { 1157 int error; 1158 NG_SEND_DATA_ONLY(error, sch->hook, m); 1159 sch->last_recv = time_second; 1160 /* we could be down by now... */ 1161 if (sch->state != UP) 1162 return; 1163 } else if (err & 0x40) { 1164 sch->short_error++; 1165 } else if (err & 0x10) { 1166 sch->crc_error++; 1167 } else if (err & 0x08) { 1168 sch->dribble_error++; 1169 } else if (err & 0x04) { 1170 sch->long_error++; 1171 } else if (err & 0x02) { 1172 sch->abort_error++; 1173 } else if (err & 0x01) { 1174 sch->overflow_error++; 1175 } 1176 if (err) { 1177 sch->last_rxerr = time_second; 1178 sch->prev_error = sch->last_error; 1179 sch->last_error = err; 1180 } 1181 1182 sc->ch[chan]->r1 = dp->vnext; 1183 1184 /* Replenish desc + mbuf supplies */ 1185 if (!m) { 1186 MGETHDR(m, M_DONTWAIT, MT_DATA); 1187 if (m == NULL) { 1188 mn_free_desc(dp); 1189 return; /* ENOBUFS */ 1190 } 1191 MCLGET(m, M_DONTWAIT); 1192 if((m->m_flags & M_EXT) == 0) { 1193 mn_free_desc(dp); 1194 m_freem(m); 1195 return; /* ENOBUFS */ 1196 } 1197 } 1198 dp->m = m; 1199 dp->data = vtophys(m->m_data); 1200 dp->flags = 0x40000000; 1201 dp->flags += 1600 << 16; 1202 dp->next = vtophys(dp); 1203 dp->vnext = 0; 1204 sc->ch[chan]->rl->next = vtophys(dp); 1205 sc->ch[chan]->rl->vnext = dp; 1206 sc->ch[chan]->rl->flags &= ~0x40000000; 1207 sc->ch[chan]->rl = dp; 1208 } 1209} 1210 1211 1212/* 1213 * Interupt handler 1214 */ 1215 1216static void 1217mn_intr(void *xsc) 1218{ 1219 struct softc *sc; 1220 u_int32_t stat, lstat, u; 1221 int i, j; 1222 1223 sc = xsc; 1224 stat = sc->m32x->stat; 1225 lstat = sc->m32x->lstat; 1226#if 0 1227 if (!stat && !(lstat & 2)) 1228 return; 1229#endif 1230 1231 if (stat & ~0xc200) { 1232 printf("%s: I stat=%08x lstat=%08x\n", sc->name, stat, lstat); 1233 } 1234 1235 if ((stat & 0x200) || (lstat & 2)) 1236 f54_intr(sc); 1237 1238 for (j = i = 0; i < 64; i ++) { 1239 u = sc->riqb[i]; 1240 if (u) { 1241 sc->riqb[i] = 0; 1242 mn_rx_intr(sc, u); 1243 if ((u & ~0x1f) == 0x30000800 || (u & ~0x1f) == 0x30000b00) 1244 continue; 1245 u &= ~0x30000400; /* bits we don't care about */ 1246 if ((u & ~0x1f) == 0x00000900) 1247 continue; 1248 if (!(u & ~0x1f)) 1249 continue; 1250 if (!j) 1251 printf("%s*: RIQB:", sc->name); 1252 printf(" [%d]=%08x", i, u); 1253 j++; 1254 } 1255 } 1256 if (j) 1257 printf("\n"); 1258 1259 for (j = i = 0; i < 64; i ++) { 1260 u = sc->tiqb[i]; 1261 if (u) { 1262 sc->tiqb[i] = 0; 1263 mn_tx_intr(sc, u); 1264 if ((u & ~0x1f) == 0x20000800) 1265 continue; 1266 u &= ~0x20000000; /* bits we don't care about */ 1267 if (!u) 1268 continue; 1269 if (!j) 1270 printf("%s*: TIQB:", sc->name); 1271 printf(" [%d]=%08x", i, u); 1272 j++; 1273 } 1274 } 1275 if (j) 1276 printf("\n"); 1277 sc->m32x->stat = stat; 1278} 1279 1280static void 1281mn_timeout(void *xsc) 1282{ 1283 static int round = 0; 1284 struct softc *sc; 1285 1286 mn_intr(xsc); 1287 sc = xsc; 1288 timeout(mn_timeout, xsc, 10 * hz); 1289 round++; 1290 if (round == 2) { 1291 sc->m32_mem.ccb = 0x00008004; 1292 sc->m32x->cmd = 0x1; 1293 } else if (round > 2) { 1294 printf("%s: timeout\n", sc->name); 1295 } 1296} 1297 1298/* 1299 * PCI initialization stuff 1300 */ 1301 1302static int 1303mn_probe (device_t self) 1304{ 1305 u_int id = pci_get_devid(self); 1306 1307 if (sizeof (struct m32xreg) != 256) { 1308 printf("MN: sizeof(struct m32xreg) = %d, should have been 256\n", sizeof (struct m32xreg)); 1309 return (ENXIO); 1310 } 1311 if (sizeof (struct f54rreg) != 128) { 1312 printf("MN: sizeof(struct f54rreg) = %d, should have been 128\n", sizeof (struct f54rreg)); 1313 return (ENXIO); 1314 } 1315 if (sizeof (struct f54wreg) != 128) { 1316 printf("MN: sizeof(struct f54wreg) = %d, should have been 128\n", sizeof (struct f54wreg)); 1317 return (ENXIO); 1318 } 1319 1320 if (id != 0x2101110a) 1321 return (ENXIO); 1322 1323 device_set_desc_copy(self, "Munich32X E1/T1 HDLC Controller"); 1324 return (0); 1325} 1326 1327static int 1328mn_attach (device_t self) 1329{ 1330 struct softc *sc; 1331 u_int32_t u; 1332 u_int32_t ver; 1333 static int once; 1334 int rid, error; 1335 struct resource *res; 1336 1337 if (!once) { 1338 if (ng_newtype(&mntypestruct)) 1339 printf("ng_newtype failed\n"); 1340 once++; 1341 } 1342 1343 sc = (struct softc *)malloc(sizeof *sc, M_MN, M_WAITOK | M_ZERO); 1344 device_set_softc(self, sc); 1345 1346 sc->dev = self; 1347 sc->unit = device_get_unit(self); 1348 sc->framing = E1; 1349 sprintf(sc->name, "mn%d", sc->unit); 1350 1351 rid = PCIR_MAPS; 1352 res = bus_alloc_resource(self, SYS_RES_MEMORY, &rid, 1353 0, ~0, 1, RF_ACTIVE); 1354 if (res == NULL) { 1355 device_printf(self, "Could not map memory\n"); 1356 return ENXIO; 1357 } 1358 sc->m0v = rman_get_virtual(res); 1359 sc->m0p = rman_get_start(res); 1360 1361 rid = PCIR_MAPS + 4; 1362 res = bus_alloc_resource(self, SYS_RES_MEMORY, &rid, 1363 0, ~0, 1, RF_ACTIVE); 1364 if (res == NULL) { 1365 device_printf(self, "Could not map memory\n"); 1366 return ENXIO; 1367 } 1368 sc->m1v = rman_get_virtual(res); 1369 sc->m1p = rman_get_start(res); 1370 1371 /* Allocate interrupt */ 1372 rid = 0; 1373 sc->irq = bus_alloc_resource(self, SYS_RES_IRQ, &rid, 0, ~0, 1374 1, RF_SHAREABLE | RF_ACTIVE); 1375 1376 if (sc->irq == NULL) { 1377 printf("couldn't map interrupt\n"); 1378 return(ENXIO); 1379 } 1380 1381 error = bus_setup_intr(self, sc->irq, INTR_TYPE_NET, mn_intr, sc, &sc->intrhand); 1382 1383 if (error) { 1384 printf("couldn't set up irq\n"); 1385 return(ENXIO); 1386 } 1387 1388 u = pci_read_config(self, PCIR_COMMAND, 1); 1389 printf("%x\n", u); 1390 pci_write_config(self, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN, 1); 1391#if 0 1392 pci_write_config(self, PCIR_COMMAND, 0x02800046, 4); 1393#endif 1394 u = pci_read_config(self, PCIR_COMMAND, 1); 1395 printf("%x\n", u); 1396 1397 ver = pci_get_revid(self); 1398 1399 sc->m32x = (struct m32xreg *) sc->m0v; 1400 sc->f54w = (struct f54wreg *) sc->m1v; 1401 sc->f54r = (struct f54rreg *) sc->m1v; 1402 1403 /* We must reset before poking at FALC54 registers */ 1404 u = mn_reset(sc); 1405 if (!u) 1406 return (0); 1407 1408 printf("mn%d: Munich32X", sc->unit); 1409 switch (ver) { 1410 case 0x13: 1411 printf(" Rev 2.2"); 1412 break; 1413 default: 1414 printf(" Rev 0x%x\n", ver); 1415 } 1416 printf(", Falc54"); 1417 switch (sc->f54r->vstr) { 1418 case 0: 1419 printf(" Rev < 1.3\n"); 1420 break; 1421 case 1: 1422 printf(" Rev 1.3\n"); 1423 break; 1424 case 2: 1425 printf(" Rev 1.4\n"); 1426 break; 1427 case 0x10: 1428 printf("-LH Rev 1.1\n"); 1429 break; 1430 case 0x13: 1431 printf("-LH Rev 1.3\n"); 1432 break; 1433 default: 1434 printf(" Rev 0x%x\n", sc->f54r->vstr); 1435 } 1436 1437 if (ng_make_node_common(&mntypestruct, &sc->node) != 0) { 1438 printf("ng_make_node_common failed\n"); 1439 return (0); 1440 } 1441 NG_NODE_SET_PRIVATE(sc->node, sc); 1442 sprintf(sc->nodename, "%s%d", NG_MN_NODE_TYPE, sc->unit); 1443 if (ng_name_node(sc->node, sc->nodename)) { 1444 NG_NODE_UNREF(sc->node); 1445 return (0); 1446 } 1447 1448 return (0); 1449} 1450 1451 1452static device_method_t mn_methods[] = { 1453 /* Device interface */ 1454 DEVMETHOD(device_probe, mn_probe), 1455 DEVMETHOD(device_attach, mn_attach), 1456 DEVMETHOD(device_suspend, bus_generic_suspend), 1457 DEVMETHOD(device_resume, bus_generic_resume), 1458 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1459 1460 {0, 0} 1461}; 1462 1463static driver_t mn_driver = { 1464 "mn", 1465 mn_methods, 1466 0 1467}; 1468 1469static devclass_t mn_devclass; 1470 1471DRIVER_MODULE(mn, pci, mn_driver, mn_devclass, 0, 0); 1472