qp.h revision 337115
1/*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: stable/11/sys/dev/mlx5/qp.h 337115 2018-08-02 08:56:27Z hselasky $ 26 */ 27 28#ifndef MLX5_QP_H 29#define MLX5_QP_H 30 31#include <dev/mlx5/driver.h> 32 33#define MLX5_INVALID_LKEY 0x100 34#define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5) 35#define MLX5_DIF_SIZE 8 36#define MLX5_STRIDE_BLOCK_OP 0x400 37#define MLX5_CPY_GRD_MASK 0xc0 38#define MLX5_CPY_APP_MASK 0x30 39#define MLX5_CPY_REF_MASK 0x0f 40#define MLX5_BSF_INC_REFTAG (1 << 6) 41#define MLX5_BSF_INL_VALID (1 << 15) 42#define MLX5_BSF_REFRESH_DIF (1 << 14) 43#define MLX5_BSF_REPEAT_BLOCK (1 << 7) 44#define MLX5_BSF_APPTAG_ESCAPE 0x1 45#define MLX5_BSF_APPREF_ESCAPE 0x2 46#define MLX5_WQE_DS_UNITS 16 47 48enum mlx5_qp_optpar { 49 MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, 50 MLX5_QP_OPTPAR_RRE = 1 << 1, 51 MLX5_QP_OPTPAR_RAE = 1 << 2, 52 MLX5_QP_OPTPAR_RWE = 1 << 3, 53 MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4, 54 MLX5_QP_OPTPAR_Q_KEY = 1 << 5, 55 MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, 56 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, 57 MLX5_QP_OPTPAR_SRA_MAX = 1 << 8, 58 MLX5_QP_OPTPAR_RRA_MAX = 1 << 9, 59 MLX5_QP_OPTPAR_PM_STATE = 1 << 10, 60 MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12, 61 MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13, 62 MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, 63 MLX5_QP_OPTPAR_PRI_PORT = 1 << 16, 64 MLX5_QP_OPTPAR_SRQN = 1 << 18, 65 MLX5_QP_OPTPAR_CQN_RCV = 1 << 19, 66 MLX5_QP_OPTPAR_DC_HS = 1 << 20, 67 MLX5_QP_OPTPAR_DC_KEY = 1 << 21, 68}; 69 70enum mlx5_qp_state { 71 MLX5_QP_STATE_RST = 0, 72 MLX5_QP_STATE_INIT = 1, 73 MLX5_QP_STATE_RTR = 2, 74 MLX5_QP_STATE_RTS = 3, 75 MLX5_QP_STATE_SQER = 4, 76 MLX5_QP_STATE_SQD = 5, 77 MLX5_QP_STATE_ERR = 6, 78 MLX5_QP_STATE_SQ_DRAINING = 7, 79 MLX5_QP_STATE_SUSPENDED = 9, 80 MLX5_QP_NUM_STATE, 81 MLX5_QP_STATE, 82 MLX5_QP_STATE_BAD, 83}; 84 85enum { 86 MLX5_SQ_STATE_NA = MLX5_SQC_STATE_ERR + 1, 87 MLX5_SQ_NUM_STATE = MLX5_SQ_STATE_NA + 1, 88 MLX5_RQ_STATE_NA = MLX5_RQC_STATE_ERR + 1, 89 MLX5_RQ_NUM_STATE = MLX5_RQ_STATE_NA + 1, 90}; 91 92enum { 93 MLX5_QP_ST_RC = 0x0, 94 MLX5_QP_ST_UC = 0x1, 95 MLX5_QP_ST_UD = 0x2, 96 MLX5_QP_ST_XRC = 0x3, 97 MLX5_QP_ST_MLX = 0x4, 98 MLX5_QP_ST_DCI = 0x5, 99 MLX5_QP_ST_DCT = 0x6, 100 MLX5_QP_ST_QP0 = 0x7, 101 MLX5_QP_ST_QP1 = 0x8, 102 MLX5_QP_ST_RAW_ETHERTYPE = 0x9, 103 MLX5_QP_ST_RAW_IPV6 = 0xa, 104 MLX5_QP_ST_SNIFFER = 0xb, 105 MLX5_QP_ST_SYNC_UMR = 0xe, 106 MLX5_QP_ST_PTP_1588 = 0xd, 107 MLX5_QP_ST_REG_UMR = 0xc, 108 MLX5_QP_ST_SW_CNAK = 0x10, 109 MLX5_QP_ST_MAX 110}; 111 112enum { 113 MLX5_NON_ZERO_RQ = 0x0, 114 MLX5_SRQ_RQ = 0x1, 115 MLX5_CRQ_RQ = 0x2, 116 MLX5_ZERO_LEN_RQ = 0x3 117}; 118 119enum { 120 /* params1 */ 121 MLX5_QP_BIT_SRE = 1 << 15, 122 MLX5_QP_BIT_SWE = 1 << 14, 123 MLX5_QP_BIT_SAE = 1 << 13, 124 /* params2 */ 125 MLX5_QP_BIT_RRE = 1 << 15, 126 MLX5_QP_BIT_RWE = 1 << 14, 127 MLX5_QP_BIT_RAE = 1 << 13, 128 MLX5_QP_BIT_RIC = 1 << 4, 129 MLX5_QP_BIT_COLL_SYNC_RQ = 1 << 2, 130 MLX5_QP_BIT_COLL_SYNC_SQ = 1 << 1, 131 MLX5_QP_BIT_COLL_MASTER = 1 << 0 132}; 133 134enum { 135 MLX5_DCT_BIT_RRE = 1 << 19, 136 MLX5_DCT_BIT_RWE = 1 << 18, 137 MLX5_DCT_BIT_RAE = 1 << 17, 138}; 139 140enum { 141 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2, 142 MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2, 143 MLX5_WQE_CTRL_SOLICITED = 1 << 1, 144}; 145 146enum { 147 MLX5_SEND_WQE_DS = 16, 148 MLX5_SEND_WQE_BB = 64, 149}; 150 151#define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS) 152 153enum { 154 MLX5_SEND_WQE_MAX_WQEBBS = 16, 155}; 156 157enum { 158 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27, 159 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, 160 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29, 161 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30, 162 MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31 163}; 164 165enum { 166 MLX5_FENCE_MODE_NONE = 0 << 5, 167 MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5, 168 MLX5_FENCE_MODE_FENCE = 2 << 5, 169 MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5, 170 MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5, 171}; 172 173enum { 174 MLX5_RCV_DBR = 0, 175 MLX5_SND_DBR = 1, 176}; 177 178enum { 179 MLX5_FLAGS_INLINE = 1<<7, 180 MLX5_FLAGS_CHECK_FREE = 1<<5, 181}; 182 183struct mlx5_wqe_fmr_seg { 184 __be32 flags; 185 __be32 mem_key; 186 __be64 buf_list; 187 __be64 start_addr; 188 __be64 reg_len; 189 __be32 offset; 190 __be32 page_size; 191 u32 reserved[2]; 192}; 193 194struct mlx5_wqe_ctrl_seg { 195 __be32 opmod_idx_opcode; 196 __be32 qpn_ds; 197 u8 signature; 198 u8 rsvd[2]; 199 u8 fm_ce_se; 200 __be32 imm; 201}; 202 203#define MLX5_WQE_CTRL_DS_MASK 0x3f 204 205enum { 206 MLX5_MLX_FLAG_MASK_VL15 = 0x40, 207 MLX5_MLX_FLAG_MASK_SLR = 0x20, 208 MLX5_MLX_FLAG_MASK_ICRC = 0x8, 209 MLX5_MLX_FLAG_MASK_FL = 4 210}; 211 212struct mlx5_mlx_seg { 213 __be32 rsvd0; 214 u8 flags; 215 u8 stat_rate_sl; 216 u8 rsvd1[8]; 217 __be16 dlid; 218}; 219 220enum { 221 MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4, 222 MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5, 223 MLX5_ETH_WQE_L3_CSUM = 1 << 6, 224 MLX5_ETH_WQE_L4_CSUM = 1 << 7, 225}; 226 227enum { 228 MLX5_ETH_WQE_SWP_INNER_L3_TYPE = 1 << 0, 229 MLX5_ETH_WQE_SWP_INNER_L4_TYPE = 1 << 1, 230 MLX5_ETH_WQE_SWP_OUTER_L3_TYPE = 1 << 4, 231 MLX5_ETH_WQE_SWP_OUTER_L4_TYPE = 1 << 5, 232}; 233 234struct mlx5_wqe_eth_seg { 235 u8 swp_outer_l4_offset; 236 u8 swp_outer_l3_offset; 237 u8 swp_inner_l4_offset; 238 u8 swp_inner_l3_offset; 239 u8 cs_flags; 240 u8 swp_flags; 241 __be16 mss; 242 __be32 rsvd2; 243 union { 244 struct { 245 __be16 inline_hdr_sz; 246 u8 inline_hdr_start[2]; 247 }; 248 struct { 249 __be16 vlan_cmd; 250 __be16 vlan_hdr; 251 }; 252 }; 253}; 254 255struct mlx5_wqe_xrc_seg { 256 __be32 xrc_srqn; 257 u8 rsvd[12]; 258}; 259 260struct mlx5_wqe_masked_atomic_seg { 261 __be64 swap_add; 262 __be64 compare; 263 __be64 swap_add_mask; 264 __be64 compare_mask; 265}; 266 267struct mlx5_av { 268 union { 269 struct { 270 __be32 qkey; 271 __be32 reserved; 272 } qkey; 273 __be64 dc_key; 274 } key; 275 __be32 dqp_dct; 276 u8 stat_rate_sl; 277 u8 fl_mlid; 278 union { 279 __be16 rlid; 280 __be16 udp_sport; 281 }; 282 u8 reserved0[4]; 283 u8 rmac[6]; 284 u8 tclass; 285 u8 hop_limit; 286 __be32 grh_gid_fl; 287 u8 rgid[16]; 288}; 289 290struct mlx5_wqe_datagram_seg { 291 struct mlx5_av av; 292}; 293 294struct mlx5_wqe_raddr_seg { 295 __be64 raddr; 296 __be32 rkey; 297 u32 reserved; 298}; 299 300struct mlx5_wqe_atomic_seg { 301 __be64 swap_add; 302 __be64 compare; 303}; 304 305struct mlx5_wqe_data_seg { 306 __be32 byte_count; 307 __be32 lkey; 308 __be64 addr; 309}; 310 311struct mlx5_wqe_umr_ctrl_seg { 312 u8 flags; 313 u8 rsvd0[3]; 314 __be16 klm_octowords; 315 __be16 bsf_octowords; 316 __be64 mkey_mask; 317 u8 rsvd1[32]; 318}; 319 320struct mlx5_seg_set_psv { 321 __be32 psv_num; 322 __be16 syndrome; 323 __be16 status; 324 __be32 transient_sig; 325 __be32 ref_tag; 326}; 327 328struct mlx5_seg_get_psv { 329 u8 rsvd[19]; 330 u8 num_psv; 331 __be32 l_key; 332 __be64 va; 333 __be32 psv_index[4]; 334}; 335 336struct mlx5_seg_check_psv { 337 u8 rsvd0[2]; 338 __be16 err_coalescing_op; 339 u8 rsvd1[2]; 340 __be16 xport_err_op; 341 u8 rsvd2[2]; 342 __be16 xport_err_mask; 343 u8 rsvd3[7]; 344 u8 num_psv; 345 __be32 l_key; 346 __be64 va; 347 __be32 psv_index[4]; 348}; 349 350struct mlx5_rwqe_sig { 351 u8 rsvd0[4]; 352 u8 signature; 353 u8 rsvd1[11]; 354}; 355 356struct mlx5_wqe_signature_seg { 357 u8 rsvd0[4]; 358 u8 signature; 359 u8 rsvd1[11]; 360}; 361 362struct mlx5_wqe_inline_seg { 363 __be32 byte_count; 364}; 365 366enum mlx5_sig_type { 367 MLX5_DIF_CRC = 0x1, 368 MLX5_DIF_IPCS = 0x2, 369}; 370 371struct mlx5_bsf_inl { 372 __be16 vld_refresh; 373 __be16 dif_apptag; 374 __be32 dif_reftag; 375 u8 sig_type; 376 u8 rp_inv_seed; 377 u8 rsvd[3]; 378 u8 dif_inc_ref_guard_check; 379 __be16 dif_app_bitmask_check; 380}; 381 382struct mlx5_bsf { 383 struct mlx5_bsf_basic { 384 u8 bsf_size_sbs; 385 u8 check_byte_mask; 386 union { 387 u8 copy_byte_mask; 388 u8 bs_selector; 389 u8 rsvd_wflags; 390 } wire; 391 union { 392 u8 bs_selector; 393 u8 rsvd_mflags; 394 } mem; 395 __be32 raw_data_size; 396 __be32 w_bfs_psv; 397 __be32 m_bfs_psv; 398 } basic; 399 struct mlx5_bsf_ext { 400 __be32 t_init_gen_pro_size; 401 __be32 rsvd_epi_size; 402 __be32 w_tfs_psv; 403 __be32 m_tfs_psv; 404 } ext; 405 struct mlx5_bsf_inl w_inl; 406 struct mlx5_bsf_inl m_inl; 407}; 408 409struct mlx5_klm { 410 __be32 bcount; 411 __be32 key; 412 __be64 va; 413}; 414 415struct mlx5_stride_block_entry { 416 __be16 stride; 417 __be16 bcount; 418 __be32 key; 419 __be64 va; 420}; 421 422struct mlx5_stride_block_ctrl_seg { 423 __be32 bcount_per_cycle; 424 __be32 op; 425 __be32 repeat_count; 426 u16 rsvd; 427 __be16 num_entries; 428}; 429 430enum mlx5_pagefault_flags { 431 MLX5_PFAULT_REQUESTOR = 1 << 0, 432 MLX5_PFAULT_WRITE = 1 << 1, 433 MLX5_PFAULT_RDMA = 1 << 2, 434}; 435 436/* Contains the details of a pagefault. */ 437struct mlx5_pagefault { 438 u32 bytes_committed; 439 u8 event_subtype; 440 enum mlx5_pagefault_flags flags; 441 union { 442 /* Initiator or send message responder pagefault details. */ 443 struct { 444 /* Received packet size, only valid for responders. */ 445 u32 packet_size; 446 /* 447 * WQE index. Refers to either the send queue or 448 * receive queue, according to event_subtype. 449 */ 450 u16 wqe_index; 451 } wqe; 452 /* RDMA responder pagefault details */ 453 struct { 454 u32 r_key; 455 /* 456 * Received packet size, minimal size page fault 457 * resolution required for forward progress. 458 */ 459 u32 packet_size; 460 u32 rdma_op_len; 461 u64 rdma_va; 462 } rdma; 463 }; 464}; 465 466struct mlx5_core_qp { 467 struct mlx5_core_rsc_common common; /* must be first */ 468 void (*event) (struct mlx5_core_qp *, int); 469 int qpn; 470 struct mlx5_rsc_debug *dbg; 471 int pid; 472}; 473 474struct mlx5_qp_path { 475 u8 fl_free_ar; 476 u8 rsvd3; 477 __be16 pkey_index; 478 u8 rsvd0; 479 u8 grh_mlid; 480 __be16 rlid; 481 u8 ackto_lt; 482 u8 mgid_index; 483 u8 static_rate; 484 u8 hop_limit; 485 __be32 tclass_flowlabel; 486 union { 487 u8 rgid[16]; 488 u8 rip[16]; 489 }; 490 u8 f_dscp_ecn_prio; 491 u8 ecn_dscp; 492 __be16 udp_sport; 493 u8 dci_cfi_prio_sl; 494 u8 port; 495 u8 rmac[6]; 496}; 497 498struct mlx5_qp_context { 499 __be32 flags; 500 __be32 flags_pd; 501 u8 mtu_msgmax; 502 u8 rq_size_stride; 503 __be16 sq_crq_size; 504 __be32 qp_counter_set_usr_page; 505 __be32 wire_qpn; 506 __be32 log_pg_sz_remote_qpn; 507 struct mlx5_qp_path pri_path; 508 struct mlx5_qp_path alt_path; 509 __be32 params1; 510 u8 reserved2[4]; 511 __be32 next_send_psn; 512 __be32 cqn_send; 513 __be32 deth_sqpn; 514 u8 reserved3[4]; 515 __be32 last_acked_psn; 516 __be32 ssn; 517 __be32 params2; 518 __be32 rnr_nextrecvpsn; 519 __be32 xrcd; 520 __be32 cqn_recv; 521 __be64 db_rec_addr; 522 __be32 qkey; 523 __be32 rq_type_srqn; 524 __be32 rmsn; 525 __be16 hw_sq_wqe_counter; 526 __be16 sw_sq_wqe_counter; 527 __be16 hw_rcyclic_byte_counter; 528 __be16 hw_rq_counter; 529 __be16 sw_rcyclic_byte_counter; 530 __be16 sw_rq_counter; 531 u8 rsvd0[5]; 532 u8 cgs; 533 u8 cs_req; 534 u8 cs_res; 535 __be64 dc_access_key; 536 u8 rsvd1[24]; 537}; 538 539struct mlx5_dct_context { 540 u8 state; 541 u8 rsvd0[7]; 542 __be32 cqn; 543 __be32 flags; 544 u8 rsvd1; 545 u8 cs_res; 546 u8 min_rnr; 547 u8 rsvd2; 548 __be32 srqn; 549 __be32 pdn; 550 __be32 tclass_flow_label; 551 __be64 access_key; 552 u8 mtu; 553 u8 port; 554 __be16 pkey_index; 555 u8 rsvd4; 556 u8 mgid_index; 557 u8 rsvd5; 558 u8 hop_limit; 559 __be32 access_violations; 560 u8 rsvd[12]; 561}; 562 563static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn) 564{ 565 return radix_tree_lookup(&dev->priv.qp_table.tree, qpn); 566} 567 568static inline struct mlx5_core_mr *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key) 569{ 570 return radix_tree_lookup(&dev->priv.mr_table.tree, key); 571} 572 573int mlx5_core_create_qp(struct mlx5_core_dev *dev, 574 struct mlx5_core_qp *qp, 575 u32 *in, 576 int inlen); 577int mlx5_core_qp_modify(struct mlx5_core_dev *dev, u16 opcode, 578 u32 opt_param_mask, void *qpc, 579 struct mlx5_core_qp *qp); 580int mlx5_core_destroy_qp(struct mlx5_core_dev *dev, 581 struct mlx5_core_qp *qp); 582int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp, 583 u32 *out, int outlen); 584int mlx5_core_dct_query(struct mlx5_core_dev *dev, struct mlx5_core_dct *dct, 585 u32 *out, int outlen); 586int mlx5_core_arm_dct(struct mlx5_core_dev *dev, struct mlx5_core_dct *dct); 587 588int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn); 589int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn); 590int mlx5_core_create_dct(struct mlx5_core_dev *dev, 591 struct mlx5_core_dct *dct, 592 u32 *in); 593int mlx5_core_destroy_dct(struct mlx5_core_dev *dev, 594 struct mlx5_core_dct *dct); 595int mlx5_core_create_rq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen, 596 struct mlx5_core_qp *rq); 597void mlx5_core_destroy_rq_tracked(struct mlx5_core_dev *dev, 598 struct mlx5_core_qp *rq); 599int mlx5_core_create_sq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen, 600 struct mlx5_core_qp *sq); 601void mlx5_core_destroy_sq_tracked(struct mlx5_core_dev *dev, 602 struct mlx5_core_qp *sq); 603void mlx5_init_qp_table(struct mlx5_core_dev *dev); 604void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev); 605int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 606void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 607 608static inline const char *mlx5_qp_type_str(int type) 609{ 610 switch (type) { 611 case MLX5_QP_ST_RC: return "RC"; 612 case MLX5_QP_ST_UC: return "C"; 613 case MLX5_QP_ST_UD: return "UD"; 614 case MLX5_QP_ST_XRC: return "XRC"; 615 case MLX5_QP_ST_MLX: return "MLX"; 616 case MLX5_QP_ST_DCI: return "DCI"; 617 case MLX5_QP_ST_QP0: return "QP0"; 618 case MLX5_QP_ST_QP1: return "QP1"; 619 case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE"; 620 case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6"; 621 case MLX5_QP_ST_SNIFFER: return "SNIFFER"; 622 case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR"; 623 case MLX5_QP_ST_PTP_1588: return "PTP_1588"; 624 case MLX5_QP_ST_REG_UMR: return "REG_UMR"; 625 case MLX5_QP_ST_SW_CNAK: return "DC_CNAK"; 626 default: return "Invalid transport type"; 627 } 628} 629 630static inline const char *mlx5_qp_state_str(int state) 631{ 632 switch (state) { 633 case MLX5_QP_STATE_RST: 634 return "RST"; 635 case MLX5_QP_STATE_INIT: 636 return "INIT"; 637 case MLX5_QP_STATE_RTR: 638 return "RTR"; 639 case MLX5_QP_STATE_RTS: 640 return "RTS"; 641 case MLX5_QP_STATE_SQER: 642 return "SQER"; 643 case MLX5_QP_STATE_SQD: 644 return "SQD"; 645 case MLX5_QP_STATE_ERR: 646 return "ERR"; 647 case MLX5_QP_STATE_SQ_DRAINING: 648 return "SQ_DRAINING"; 649 case MLX5_QP_STATE_SUSPENDED: 650 return "SUSPENDED"; 651 default: return "Invalid QP state"; 652 } 653} 654 655#endif /* MLX5_QP_H */ 656