qp.h revision 331769
1/*- 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: stable/11/sys/dev/mlx5/qp.h 331769 2018-03-30 18:06:29Z hselasky $ 26 */ 27 28#ifndef MLX5_QP_H 29#define MLX5_QP_H 30 31#include <dev/mlx5/driver.h> 32 33#define MLX5_INVALID_LKEY 0x100 34#define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5) 35#define MLX5_DIF_SIZE 8 36#define MLX5_STRIDE_BLOCK_OP 0x400 37#define MLX5_CPY_GRD_MASK 0xc0 38#define MLX5_CPY_APP_MASK 0x30 39#define MLX5_CPY_REF_MASK 0x0f 40#define MLX5_BSF_INC_REFTAG (1 << 6) 41#define MLX5_BSF_INL_VALID (1 << 15) 42#define MLX5_BSF_REFRESH_DIF (1 << 14) 43#define MLX5_BSF_REPEAT_BLOCK (1 << 7) 44#define MLX5_BSF_APPTAG_ESCAPE 0x1 45#define MLX5_BSF_APPREF_ESCAPE 0x2 46#define MLX5_WQE_DS_UNITS 16 47 48enum mlx5_qp_optpar { 49 MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, 50 MLX5_QP_OPTPAR_RRE = 1 << 1, 51 MLX5_QP_OPTPAR_RAE = 1 << 2, 52 MLX5_QP_OPTPAR_RWE = 1 << 3, 53 MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4, 54 MLX5_QP_OPTPAR_Q_KEY = 1 << 5, 55 MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, 56 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, 57 MLX5_QP_OPTPAR_SRA_MAX = 1 << 8, 58 MLX5_QP_OPTPAR_RRA_MAX = 1 << 9, 59 MLX5_QP_OPTPAR_PM_STATE = 1 << 10, 60 MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12, 61 MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13, 62 MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, 63 MLX5_QP_OPTPAR_PRI_PORT = 1 << 16, 64 MLX5_QP_OPTPAR_SRQN = 1 << 18, 65 MLX5_QP_OPTPAR_CQN_RCV = 1 << 19, 66 MLX5_QP_OPTPAR_DC_HS = 1 << 20, 67 MLX5_QP_OPTPAR_DC_KEY = 1 << 21, 68}; 69 70enum mlx5_qp_state { 71 MLX5_QP_STATE_RST = 0, 72 MLX5_QP_STATE_INIT = 1, 73 MLX5_QP_STATE_RTR = 2, 74 MLX5_QP_STATE_RTS = 3, 75 MLX5_QP_STATE_SQER = 4, 76 MLX5_QP_STATE_SQD = 5, 77 MLX5_QP_STATE_ERR = 6, 78 MLX5_QP_STATE_SQ_DRAINING = 7, 79 MLX5_QP_STATE_SUSPENDED = 9, 80 MLX5_QP_NUM_STATE, 81 MLX5_QP_STATE, 82 MLX5_QP_STATE_BAD, 83}; 84 85enum { 86 MLX5_SQ_STATE_NA = MLX5_SQC_STATE_ERR + 1, 87 MLX5_SQ_NUM_STATE = MLX5_SQ_STATE_NA + 1, 88 MLX5_RQ_STATE_NA = MLX5_RQC_STATE_ERR + 1, 89 MLX5_RQ_NUM_STATE = MLX5_RQ_STATE_NA + 1, 90}; 91 92enum { 93 MLX5_QP_ST_RC = 0x0, 94 MLX5_QP_ST_UC = 0x1, 95 MLX5_QP_ST_UD = 0x2, 96 MLX5_QP_ST_XRC = 0x3, 97 MLX5_QP_ST_MLX = 0x4, 98 MLX5_QP_ST_DCI = 0x5, 99 MLX5_QP_ST_DCT = 0x6, 100 MLX5_QP_ST_QP0 = 0x7, 101 MLX5_QP_ST_QP1 = 0x8, 102 MLX5_QP_ST_RAW_ETHERTYPE = 0x9, 103 MLX5_QP_ST_RAW_IPV6 = 0xa, 104 MLX5_QP_ST_SNIFFER = 0xb, 105 MLX5_QP_ST_SYNC_UMR = 0xe, 106 MLX5_QP_ST_PTP_1588 = 0xd, 107 MLX5_QP_ST_REG_UMR = 0xc, 108 MLX5_QP_ST_SW_CNAK = 0x10, 109 MLX5_QP_ST_MAX 110}; 111 112enum { 113 MLX5_NON_ZERO_RQ = 0x0, 114 MLX5_SRQ_RQ = 0x1, 115 MLX5_CRQ_RQ = 0x2, 116 MLX5_ZERO_LEN_RQ = 0x3 117}; 118 119enum { 120 /* params1 */ 121 MLX5_QP_BIT_SRE = 1 << 15, 122 MLX5_QP_BIT_SWE = 1 << 14, 123 MLX5_QP_BIT_SAE = 1 << 13, 124 /* params2 */ 125 MLX5_QP_BIT_RRE = 1 << 15, 126 MLX5_QP_BIT_RWE = 1 << 14, 127 MLX5_QP_BIT_RAE = 1 << 13, 128 MLX5_QP_BIT_RIC = 1 << 4, 129 MLX5_QP_BIT_COLL_SYNC_RQ = 1 << 2, 130 MLX5_QP_BIT_COLL_SYNC_SQ = 1 << 1, 131 MLX5_QP_BIT_COLL_MASTER = 1 << 0 132}; 133 134enum { 135 MLX5_DCT_BIT_RRE = 1 << 19, 136 MLX5_DCT_BIT_RWE = 1 << 18, 137 MLX5_DCT_BIT_RAE = 1 << 17, 138}; 139 140enum { 141 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2, 142 MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2, 143 MLX5_WQE_CTRL_SOLICITED = 1 << 1, 144}; 145 146enum { 147 MLX5_SEND_WQE_DS = 16, 148 MLX5_SEND_WQE_BB = 64, 149}; 150 151#define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS) 152 153enum { 154 MLX5_SEND_WQE_MAX_WQEBBS = 16, 155}; 156 157enum { 158 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27, 159 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, 160 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29, 161 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30, 162 MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31 163}; 164 165enum { 166 MLX5_FENCE_MODE_NONE = 0 << 5, 167 MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5, 168 MLX5_FENCE_MODE_FENCE = 2 << 5, 169 MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5, 170 MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5, 171}; 172 173enum { 174 MLX5_QP_DRAIN_SIGERR = 1 << 26, 175 MLX5_QP_LAT_SENSITIVE = 1 << 28, 176 MLX5_QP_BLOCK_MCAST = 1 << 30, 177 MLX5_QP_ENABLE_SIG = 1 << 31, 178}; 179 180enum { 181 MLX5_RCV_DBR = 0, 182 MLX5_SND_DBR = 1, 183}; 184 185enum { 186 MLX5_FLAGS_INLINE = 1<<7, 187 MLX5_FLAGS_CHECK_FREE = 1<<5, 188}; 189 190struct mlx5_wqe_fmr_seg { 191 __be32 flags; 192 __be32 mem_key; 193 __be64 buf_list; 194 __be64 start_addr; 195 __be64 reg_len; 196 __be32 offset; 197 __be32 page_size; 198 u32 reserved[2]; 199}; 200 201struct mlx5_wqe_ctrl_seg { 202 __be32 opmod_idx_opcode; 203 __be32 qpn_ds; 204 u8 signature; 205 u8 rsvd[2]; 206 u8 fm_ce_se; 207 __be32 imm; 208}; 209 210#define MLX5_WQE_CTRL_DS_MASK 0x3f 211 212enum { 213 MLX5_MLX_FLAG_MASK_VL15 = 0x40, 214 MLX5_MLX_FLAG_MASK_SLR = 0x20, 215 MLX5_MLX_FLAG_MASK_ICRC = 0x8, 216 MLX5_MLX_FLAG_MASK_FL = 4 217}; 218 219struct mlx5_mlx_seg { 220 __be32 rsvd0; 221 u8 flags; 222 u8 stat_rate_sl; 223 u8 rsvd1[8]; 224 __be16 dlid; 225}; 226 227enum { 228 MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4, 229 MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5, 230 MLX5_ETH_WQE_L3_CSUM = 1 << 6, 231 MLX5_ETH_WQE_L4_CSUM = 1 << 7, 232}; 233 234enum { 235 MLX5_ETH_WQE_SWP_INNER_L3_TYPE = 1 << 0, 236 MLX5_ETH_WQE_SWP_INNER_L4_TYPE = 1 << 1, 237 MLX5_ETH_WQE_SWP_OUTER_L3_TYPE = 1 << 4, 238 MLX5_ETH_WQE_SWP_OUTER_L4_TYPE = 1 << 5, 239}; 240 241struct mlx5_wqe_eth_seg { 242 u8 swp_outer_l4_offset; 243 u8 swp_outer_l3_offset; 244 u8 swp_inner_l4_offset; 245 u8 swp_inner_l3_offset; 246 u8 cs_flags; 247 u8 swp_flags; 248 __be16 mss; 249 __be32 rsvd2; 250 __be16 inline_hdr_sz; 251 u8 inline_hdr_start[2]; 252}; 253 254struct mlx5_wqe_xrc_seg { 255 __be32 xrc_srqn; 256 u8 rsvd[12]; 257}; 258 259struct mlx5_wqe_masked_atomic_seg { 260 __be64 swap_add; 261 __be64 compare; 262 __be64 swap_add_mask; 263 __be64 compare_mask; 264}; 265 266struct mlx5_av { 267 union { 268 struct { 269 __be32 qkey; 270 __be32 reserved; 271 } qkey; 272 __be64 dc_key; 273 } key; 274 __be32 dqp_dct; 275 u8 stat_rate_sl; 276 u8 fl_mlid; 277 union { 278 __be16 rlid; 279 __be16 udp_sport; 280 }; 281 u8 reserved0[4]; 282 u8 rmac[6]; 283 u8 tclass; 284 u8 hop_limit; 285 __be32 grh_gid_fl; 286 u8 rgid[16]; 287}; 288 289struct mlx5_wqe_datagram_seg { 290 struct mlx5_av av; 291}; 292 293struct mlx5_wqe_raddr_seg { 294 __be64 raddr; 295 __be32 rkey; 296 u32 reserved; 297}; 298 299struct mlx5_wqe_atomic_seg { 300 __be64 swap_add; 301 __be64 compare; 302}; 303 304struct mlx5_wqe_data_seg { 305 __be32 byte_count; 306 __be32 lkey; 307 __be64 addr; 308}; 309 310struct mlx5_wqe_umr_ctrl_seg { 311 u8 flags; 312 u8 rsvd0[3]; 313 __be16 klm_octowords; 314 __be16 bsf_octowords; 315 __be64 mkey_mask; 316 u8 rsvd1[32]; 317}; 318 319struct mlx5_seg_set_psv { 320 __be32 psv_num; 321 __be16 syndrome; 322 __be16 status; 323 __be32 transient_sig; 324 __be32 ref_tag; 325}; 326 327struct mlx5_seg_get_psv { 328 u8 rsvd[19]; 329 u8 num_psv; 330 __be32 l_key; 331 __be64 va; 332 __be32 psv_index[4]; 333}; 334 335struct mlx5_seg_check_psv { 336 u8 rsvd0[2]; 337 __be16 err_coalescing_op; 338 u8 rsvd1[2]; 339 __be16 xport_err_op; 340 u8 rsvd2[2]; 341 __be16 xport_err_mask; 342 u8 rsvd3[7]; 343 u8 num_psv; 344 __be32 l_key; 345 __be64 va; 346 __be32 psv_index[4]; 347}; 348 349struct mlx5_rwqe_sig { 350 u8 rsvd0[4]; 351 u8 signature; 352 u8 rsvd1[11]; 353}; 354 355struct mlx5_wqe_signature_seg { 356 u8 rsvd0[4]; 357 u8 signature; 358 u8 rsvd1[11]; 359}; 360 361struct mlx5_wqe_inline_seg { 362 __be32 byte_count; 363}; 364 365enum mlx5_sig_type { 366 MLX5_DIF_CRC = 0x1, 367 MLX5_DIF_IPCS = 0x2, 368}; 369 370struct mlx5_bsf_inl { 371 __be16 vld_refresh; 372 __be16 dif_apptag; 373 __be32 dif_reftag; 374 u8 sig_type; 375 u8 rp_inv_seed; 376 u8 rsvd[3]; 377 u8 dif_inc_ref_guard_check; 378 __be16 dif_app_bitmask_check; 379}; 380 381struct mlx5_bsf { 382 struct mlx5_bsf_basic { 383 u8 bsf_size_sbs; 384 u8 check_byte_mask; 385 union { 386 u8 copy_byte_mask; 387 u8 bs_selector; 388 u8 rsvd_wflags; 389 } wire; 390 union { 391 u8 bs_selector; 392 u8 rsvd_mflags; 393 } mem; 394 __be32 raw_data_size; 395 __be32 w_bfs_psv; 396 __be32 m_bfs_psv; 397 } basic; 398 struct mlx5_bsf_ext { 399 __be32 t_init_gen_pro_size; 400 __be32 rsvd_epi_size; 401 __be32 w_tfs_psv; 402 __be32 m_tfs_psv; 403 } ext; 404 struct mlx5_bsf_inl w_inl; 405 struct mlx5_bsf_inl m_inl; 406}; 407 408struct mlx5_klm { 409 __be32 bcount; 410 __be32 key; 411 __be64 va; 412}; 413 414struct mlx5_stride_block_entry { 415 __be16 stride; 416 __be16 bcount; 417 __be32 key; 418 __be64 va; 419}; 420 421struct mlx5_stride_block_ctrl_seg { 422 __be32 bcount_per_cycle; 423 __be32 op; 424 __be32 repeat_count; 425 u16 rsvd; 426 __be16 num_entries; 427}; 428 429enum mlx5_pagefault_flags { 430 MLX5_PFAULT_REQUESTOR = 1 << 0, 431 MLX5_PFAULT_WRITE = 1 << 1, 432 MLX5_PFAULT_RDMA = 1 << 2, 433}; 434 435/* Contains the details of a pagefault. */ 436struct mlx5_pagefault { 437 u32 bytes_committed; 438 u8 event_subtype; 439 enum mlx5_pagefault_flags flags; 440 union { 441 /* Initiator or send message responder pagefault details. */ 442 struct { 443 /* Received packet size, only valid for responders. */ 444 u32 packet_size; 445 /* 446 * WQE index. Refers to either the send queue or 447 * receive queue, according to event_subtype. 448 */ 449 u16 wqe_index; 450 } wqe; 451 /* RDMA responder pagefault details */ 452 struct { 453 u32 r_key; 454 /* 455 * Received packet size, minimal size page fault 456 * resolution required for forward progress. 457 */ 458 u32 packet_size; 459 u32 rdma_op_len; 460 u64 rdma_va; 461 } rdma; 462 }; 463}; 464 465struct mlx5_core_qp { 466 struct mlx5_core_rsc_common common; /* must be first */ 467 void (*event) (struct mlx5_core_qp *, int); 468 int qpn; 469 struct mlx5_rsc_debug *dbg; 470 int pid; 471}; 472 473struct mlx5_qp_path { 474 u8 fl_free_ar; 475 u8 rsvd3; 476 __be16 pkey_index; 477 u8 rsvd0; 478 u8 grh_mlid; 479 __be16 rlid; 480 u8 ackto_lt; 481 u8 mgid_index; 482 u8 static_rate; 483 u8 hop_limit; 484 __be32 tclass_flowlabel; 485 union { 486 u8 rgid[16]; 487 u8 rip[16]; 488 }; 489 u8 f_dscp_ecn_prio; 490 u8 ecn_dscp; 491 __be16 udp_sport; 492 u8 dci_cfi_prio_sl; 493 u8 port; 494 u8 rmac[6]; 495}; 496 497struct mlx5_qp_context { 498 __be32 flags; 499 __be32 flags_pd; 500 u8 mtu_msgmax; 501 u8 rq_size_stride; 502 __be16 sq_crq_size; 503 __be32 qp_counter_set_usr_page; 504 __be32 wire_qpn; 505 __be32 log_pg_sz_remote_qpn; 506 struct mlx5_qp_path pri_path; 507 struct mlx5_qp_path alt_path; 508 __be32 params1; 509 u8 reserved2[4]; 510 __be32 next_send_psn; 511 __be32 cqn_send; 512 __be32 deth_sqpn; 513 u8 reserved3[4]; 514 __be32 last_acked_psn; 515 __be32 ssn; 516 __be32 params2; 517 __be32 rnr_nextrecvpsn; 518 __be32 xrcd; 519 __be32 cqn_recv; 520 __be64 db_rec_addr; 521 __be32 qkey; 522 __be32 rq_type_srqn; 523 __be32 rmsn; 524 __be16 hw_sq_wqe_counter; 525 __be16 sw_sq_wqe_counter; 526 __be16 hw_rcyclic_byte_counter; 527 __be16 hw_rq_counter; 528 __be16 sw_rcyclic_byte_counter; 529 __be16 sw_rq_counter; 530 u8 rsvd0[5]; 531 u8 cgs; 532 u8 cs_req; 533 u8 cs_res; 534 __be64 dc_access_key; 535 u8 rsvd1[24]; 536}; 537 538struct mlx5_create_qp_mbox_in { 539 struct mlx5_inbox_hdr hdr; 540 __be32 input_qpn; 541 u8 rsvd0[4]; 542 __be32 opt_param_mask; 543 u8 rsvd1[4]; 544 struct mlx5_qp_context ctx; 545 u8 rsvd3[16]; 546 __be64 pas[0]; 547}; 548 549struct mlx5_dct_context { 550 u8 state; 551 u8 rsvd0[7]; 552 __be32 cqn; 553 __be32 flags; 554 u8 rsvd1; 555 u8 cs_res; 556 u8 min_rnr; 557 u8 rsvd2; 558 __be32 srqn; 559 __be32 pdn; 560 __be32 tclass_flow_label; 561 __be64 access_key; 562 u8 mtu; 563 u8 port; 564 __be16 pkey_index; 565 u8 rsvd4; 566 u8 mgid_index; 567 u8 rsvd5; 568 u8 hop_limit; 569 __be32 access_violations; 570 u8 rsvd[12]; 571}; 572 573struct mlx5_create_dct_mbox_in { 574 struct mlx5_inbox_hdr hdr; 575 u8 rsvd0[8]; 576 struct mlx5_dct_context context; 577 u8 rsvd[48]; 578}; 579 580struct mlx5_create_dct_mbox_out { 581 struct mlx5_outbox_hdr hdr; 582 __be32 dctn; 583 u8 rsvd0[4]; 584}; 585 586struct mlx5_destroy_dct_mbox_in { 587 struct mlx5_inbox_hdr hdr; 588 __be32 dctn; 589 u8 rsvd0[4]; 590}; 591 592struct mlx5_destroy_dct_mbox_out { 593 struct mlx5_outbox_hdr hdr; 594 u8 rsvd0[8]; 595}; 596 597struct mlx5_drain_dct_mbox_in { 598 struct mlx5_inbox_hdr hdr; 599 __be32 dctn; 600 u8 rsvd0[4]; 601}; 602 603struct mlx5_drain_dct_mbox_out { 604 struct mlx5_outbox_hdr hdr; 605 u8 rsvd0[8]; 606}; 607 608struct mlx5_create_qp_mbox_out { 609 struct mlx5_outbox_hdr hdr; 610 __be32 qpn; 611 u8 rsvd0[4]; 612}; 613 614struct mlx5_destroy_qp_mbox_in { 615 struct mlx5_inbox_hdr hdr; 616 __be32 qpn; 617 u8 rsvd0[4]; 618}; 619 620struct mlx5_destroy_qp_mbox_out { 621 struct mlx5_outbox_hdr hdr; 622 u8 rsvd0[8]; 623}; 624 625struct mlx5_modify_qp_mbox_in { 626 struct mlx5_inbox_hdr hdr; 627 __be32 qpn; 628 u8 rsvd1[4]; 629 __be32 optparam; 630 u8 rsvd0[4]; 631 struct mlx5_qp_context ctx; 632 u8 rsvd2[16]; 633}; 634 635struct mlx5_modify_qp_mbox_out { 636 struct mlx5_outbox_hdr hdr; 637 u8 rsvd0[8]; 638}; 639 640struct mlx5_query_qp_mbox_in { 641 struct mlx5_inbox_hdr hdr; 642 __be32 qpn; 643 u8 rsvd[4]; 644}; 645 646struct mlx5_query_qp_mbox_out { 647 struct mlx5_outbox_hdr hdr; 648 u8 rsvd1[8]; 649 __be32 optparam; 650 u8 rsvd0[4]; 651 struct mlx5_qp_context ctx; 652 u8 rsvd2[16]; 653 __be64 pas[0]; 654}; 655 656struct mlx5_query_dct_mbox_in { 657 struct mlx5_inbox_hdr hdr; 658 __be32 dctn; 659 u8 rsvd[4]; 660}; 661 662struct mlx5_query_dct_mbox_out { 663 struct mlx5_outbox_hdr hdr; 664 u8 rsvd0[8]; 665 struct mlx5_dct_context ctx; 666 u8 rsvd1[48]; 667}; 668 669struct mlx5_arm_dct_mbox_in { 670 struct mlx5_inbox_hdr hdr; 671 __be32 dctn; 672 u8 rsvd[4]; 673}; 674 675struct mlx5_arm_dct_mbox_out { 676 struct mlx5_outbox_hdr hdr; 677 u8 rsvd0[8]; 678}; 679 680struct mlx5_conf_sqp_mbox_in { 681 struct mlx5_inbox_hdr hdr; 682 __be32 qpn; 683 u8 rsvd[3]; 684 u8 type; 685}; 686 687struct mlx5_conf_sqp_mbox_out { 688 struct mlx5_outbox_hdr hdr; 689 u8 rsvd[8]; 690}; 691 692static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn) 693{ 694 return radix_tree_lookup(&dev->priv.qp_table.tree, qpn); 695} 696 697static inline struct mlx5_core_mr *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key) 698{ 699 return radix_tree_lookup(&dev->priv.mr_table.tree, key); 700} 701 702int mlx5_core_create_qp(struct mlx5_core_dev *dev, 703 struct mlx5_core_qp *qp, 704 struct mlx5_create_qp_mbox_in *in, 705 int inlen); 706int mlx5_core_qp_modify(struct mlx5_core_dev *dev, u16 operation, 707 struct mlx5_modify_qp_mbox_in *in, int sqd_event, 708 struct mlx5_core_qp *qp); 709int mlx5_core_destroy_qp(struct mlx5_core_dev *dev, 710 struct mlx5_core_qp *qp); 711int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp, 712 struct mlx5_query_qp_mbox_out *out, int outlen); 713int mlx5_core_dct_query(struct mlx5_core_dev *dev, struct mlx5_core_dct *dct, 714 struct mlx5_query_dct_mbox_out *out); 715int mlx5_core_arm_dct(struct mlx5_core_dev *dev, struct mlx5_core_dct *dct); 716 717int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn); 718int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn); 719int mlx5_core_create_dct(struct mlx5_core_dev *dev, 720 struct mlx5_core_dct *dct, 721 struct mlx5_create_dct_mbox_in *in); 722int mlx5_core_destroy_dct(struct mlx5_core_dev *dev, 723 struct mlx5_core_dct *dct); 724int mlx5_core_create_rq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen, 725 struct mlx5_core_qp *rq); 726void mlx5_core_destroy_rq_tracked(struct mlx5_core_dev *dev, 727 struct mlx5_core_qp *rq); 728int mlx5_core_create_sq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen, 729 struct mlx5_core_qp *sq); 730void mlx5_core_destroy_sq_tracked(struct mlx5_core_dev *dev, 731 struct mlx5_core_qp *sq); 732void mlx5_init_qp_table(struct mlx5_core_dev *dev); 733void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev); 734int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 735void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 736 737static inline const char *mlx5_qp_type_str(int type) 738{ 739 switch (type) { 740 case MLX5_QP_ST_RC: return "RC"; 741 case MLX5_QP_ST_UC: return "C"; 742 case MLX5_QP_ST_UD: return "UD"; 743 case MLX5_QP_ST_XRC: return "XRC"; 744 case MLX5_QP_ST_MLX: return "MLX"; 745 case MLX5_QP_ST_DCI: return "DCI"; 746 case MLX5_QP_ST_QP0: return "QP0"; 747 case MLX5_QP_ST_QP1: return "QP1"; 748 case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE"; 749 case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6"; 750 case MLX5_QP_ST_SNIFFER: return "SNIFFER"; 751 case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR"; 752 case MLX5_QP_ST_PTP_1588: return "PTP_1588"; 753 case MLX5_QP_ST_REG_UMR: return "REG_UMR"; 754 case MLX5_QP_ST_SW_CNAK: return "DC_CNAK"; 755 default: return "Invalid transport type"; 756 } 757} 758 759static inline const char *mlx5_qp_state_str(int state) 760{ 761 switch (state) { 762 case MLX5_QP_STATE_RST: 763 return "RST"; 764 case MLX5_QP_STATE_INIT: 765 return "INIT"; 766 case MLX5_QP_STATE_RTR: 767 return "RTR"; 768 case MLX5_QP_STATE_RTS: 769 return "RTS"; 770 case MLX5_QP_STATE_SQER: 771 return "SQER"; 772 case MLX5_QP_STATE_SQD: 773 return "SQD"; 774 case MLX5_QP_STATE_ERR: 775 return "ERR"; 776 case MLX5_QP_STATE_SQ_DRAINING: 777 return "SQ_DRAINING"; 778 case MLX5_QP_STATE_SUSPENDED: 779 return "SUSPENDED"; 780 default: return "Invalid QP state"; 781 } 782} 783 784#endif /* MLX5_QP_H */ 785