qp.h revision 368220
1290650Shselasky/*- 2337115Shselasky * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3290650Shselasky * 4290650Shselasky * Redistribution and use in source and binary forms, with or without 5290650Shselasky * modification, are permitted provided that the following conditions 6290650Shselasky * are met: 7290650Shselasky * 1. Redistributions of source code must retain the above copyright 8290650Shselasky * notice, this list of conditions and the following disclaimer. 9290650Shselasky * 2. Redistributions in binary form must reproduce the above copyright 10290650Shselasky * notice, this list of conditions and the following disclaimer in the 11290650Shselasky * documentation and/or other materials provided with the distribution. 12290650Shselasky * 13290650Shselasky * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14290650Shselasky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15290650Shselasky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16290650Shselasky * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17290650Shselasky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18290650Shselasky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19290650Shselasky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20290650Shselasky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21290650Shselasky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22290650Shselasky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23290650Shselasky * SUCH DAMAGE. 24290650Shselasky * 25290650Shselasky * $FreeBSD: stable/11/sys/dev/mlx5/qp.h 368220 2020-12-01 12:45:47Z hselasky $ 26290650Shselasky */ 27290650Shselasky 28290650Shselasky#ifndef MLX5_QP_H 29290650Shselasky#define MLX5_QP_H 30290650Shselasky 31290650Shselasky#include <dev/mlx5/driver.h> 32290650Shselasky 33290650Shselasky#define MLX5_INVALID_LKEY 0x100 34290650Shselasky#define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5) 35290650Shselasky#define MLX5_DIF_SIZE 8 36290650Shselasky#define MLX5_STRIDE_BLOCK_OP 0x400 37290650Shselasky#define MLX5_CPY_GRD_MASK 0xc0 38290650Shselasky#define MLX5_CPY_APP_MASK 0x30 39290650Shselasky#define MLX5_CPY_REF_MASK 0x0f 40290650Shselasky#define MLX5_BSF_INC_REFTAG (1 << 6) 41290650Shselasky#define MLX5_BSF_INL_VALID (1 << 15) 42290650Shselasky#define MLX5_BSF_REFRESH_DIF (1 << 14) 43290650Shselasky#define MLX5_BSF_REPEAT_BLOCK (1 << 7) 44290650Shselasky#define MLX5_BSF_APPTAG_ESCAPE 0x1 45290650Shselasky#define MLX5_BSF_APPREF_ESCAPE 0x2 46329204Shselasky#define MLX5_WQE_DS_UNITS 16 47290650Shselasky 48290650Shselaskyenum mlx5_qp_optpar { 49290650Shselasky MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, 50290650Shselasky MLX5_QP_OPTPAR_RRE = 1 << 1, 51290650Shselasky MLX5_QP_OPTPAR_RAE = 1 << 2, 52290650Shselasky MLX5_QP_OPTPAR_RWE = 1 << 3, 53290650Shselasky MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4, 54290650Shselasky MLX5_QP_OPTPAR_Q_KEY = 1 << 5, 55290650Shselasky MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, 56290650Shselasky MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, 57290650Shselasky MLX5_QP_OPTPAR_SRA_MAX = 1 << 8, 58290650Shselasky MLX5_QP_OPTPAR_RRA_MAX = 1 << 9, 59290650Shselasky MLX5_QP_OPTPAR_PM_STATE = 1 << 10, 60290650Shselasky MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12, 61290650Shselasky MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13, 62290650Shselasky MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, 63290650Shselasky MLX5_QP_OPTPAR_PRI_PORT = 1 << 16, 64290650Shselasky MLX5_QP_OPTPAR_SRQN = 1 << 18, 65290650Shselasky MLX5_QP_OPTPAR_CQN_RCV = 1 << 19, 66290650Shselasky MLX5_QP_OPTPAR_DC_HS = 1 << 20, 67290650Shselasky MLX5_QP_OPTPAR_DC_KEY = 1 << 21, 68290650Shselasky}; 69290650Shselasky 70290650Shselaskyenum mlx5_qp_state { 71290650Shselasky MLX5_QP_STATE_RST = 0, 72290650Shselasky MLX5_QP_STATE_INIT = 1, 73290650Shselasky MLX5_QP_STATE_RTR = 2, 74290650Shselasky MLX5_QP_STATE_RTS = 3, 75290650Shselasky MLX5_QP_STATE_SQER = 4, 76290650Shselasky MLX5_QP_STATE_SQD = 5, 77290650Shselasky MLX5_QP_STATE_ERR = 6, 78290650Shselasky MLX5_QP_STATE_SQ_DRAINING = 7, 79290650Shselasky MLX5_QP_STATE_SUSPENDED = 9, 80329204Shselasky MLX5_QP_NUM_STATE, 81329204Shselasky MLX5_QP_STATE, 82329204Shselasky MLX5_QP_STATE_BAD, 83290650Shselasky}; 84290650Shselasky 85290650Shselaskyenum { 86329204Shselasky MLX5_SQ_STATE_NA = MLX5_SQC_STATE_ERR + 1, 87329204Shselasky MLX5_SQ_NUM_STATE = MLX5_SQ_STATE_NA + 1, 88329204Shselasky MLX5_RQ_STATE_NA = MLX5_RQC_STATE_ERR + 1, 89329204Shselasky MLX5_RQ_NUM_STATE = MLX5_RQ_STATE_NA + 1, 90329204Shselasky}; 91329204Shselasky 92329204Shselaskyenum { 93290650Shselasky MLX5_QP_ST_RC = 0x0, 94290650Shselasky MLX5_QP_ST_UC = 0x1, 95290650Shselasky MLX5_QP_ST_UD = 0x2, 96290650Shselasky MLX5_QP_ST_XRC = 0x3, 97290650Shselasky MLX5_QP_ST_MLX = 0x4, 98290650Shselasky MLX5_QP_ST_DCI = 0x5, 99290650Shselasky MLX5_QP_ST_DCT = 0x6, 100290650Shselasky MLX5_QP_ST_QP0 = 0x7, 101290650Shselasky MLX5_QP_ST_QP1 = 0x8, 102290650Shselasky MLX5_QP_ST_RAW_ETHERTYPE = 0x9, 103290650Shselasky MLX5_QP_ST_RAW_IPV6 = 0xa, 104290650Shselasky MLX5_QP_ST_SNIFFER = 0xb, 105290650Shselasky MLX5_QP_ST_SYNC_UMR = 0xe, 106290650Shselasky MLX5_QP_ST_PTP_1588 = 0xd, 107290650Shselasky MLX5_QP_ST_REG_UMR = 0xc, 108306233Shselasky MLX5_QP_ST_SW_CNAK = 0x10, 109290650Shselasky MLX5_QP_ST_MAX 110290650Shselasky}; 111290650Shselasky 112290650Shselaskyenum { 113331769Shselasky MLX5_NON_ZERO_RQ = 0x0, 114331769Shselasky MLX5_SRQ_RQ = 0x1, 115331769Shselasky MLX5_CRQ_RQ = 0x2, 116331769Shselasky MLX5_ZERO_LEN_RQ = 0x3 117290650Shselasky}; 118290650Shselasky 119290650Shselaskyenum { 120290650Shselasky /* params1 */ 121290650Shselasky MLX5_QP_BIT_SRE = 1 << 15, 122290650Shselasky MLX5_QP_BIT_SWE = 1 << 14, 123290650Shselasky MLX5_QP_BIT_SAE = 1 << 13, 124290650Shselasky /* params2 */ 125290650Shselasky MLX5_QP_BIT_RRE = 1 << 15, 126290650Shselasky MLX5_QP_BIT_RWE = 1 << 14, 127290650Shselasky MLX5_QP_BIT_RAE = 1 << 13, 128290650Shselasky MLX5_QP_BIT_RIC = 1 << 4, 129306233Shselasky MLX5_QP_BIT_COLL_SYNC_RQ = 1 << 2, 130306233Shselasky MLX5_QP_BIT_COLL_SYNC_SQ = 1 << 1, 131306233Shselasky MLX5_QP_BIT_COLL_MASTER = 1 << 0 132290650Shselasky}; 133290650Shselasky 134290650Shselaskyenum { 135306233Shselasky MLX5_DCT_BIT_RRE = 1 << 19, 136306233Shselasky MLX5_DCT_BIT_RWE = 1 << 18, 137306233Shselasky MLX5_DCT_BIT_RAE = 1 << 17, 138306233Shselasky}; 139306233Shselasky 140306233Shselaskyenum { 141290650Shselasky MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2, 142290650Shselasky MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2, 143290650Shselasky MLX5_WQE_CTRL_SOLICITED = 1 << 1, 144290650Shselasky}; 145290650Shselasky 146356073Shselasky#define MLX5_SEND_WQE_DS 16 147356073Shselasky#define MLX5_SEND_WQE_BB 64 148290650Shselasky#define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS) 149290650Shselasky 150290650Shselaskyenum { 151290650Shselasky MLX5_SEND_WQE_MAX_WQEBBS = 16, 152290650Shselasky}; 153290650Shselasky 154290650Shselaskyenum { 155290650Shselasky MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27, 156290650Shselasky MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, 157290650Shselasky MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29, 158290650Shselasky MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30, 159290650Shselasky MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31 160290650Shselasky}; 161290650Shselasky 162290650Shselaskyenum { 163290650Shselasky MLX5_FENCE_MODE_NONE = 0 << 5, 164290650Shselasky MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5, 165329204Shselasky MLX5_FENCE_MODE_FENCE = 2 << 5, 166290650Shselasky MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5, 167290650Shselasky MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5, 168290650Shselasky}; 169290650Shselasky 170290650Shselaskyenum { 171290650Shselasky MLX5_RCV_DBR = 0, 172290650Shselasky MLX5_SND_DBR = 1, 173290650Shselasky}; 174290650Shselasky 175290650Shselaskyenum { 176290650Shselasky MLX5_FLAGS_INLINE = 1<<7, 177290650Shselasky MLX5_FLAGS_CHECK_FREE = 1<<5, 178290650Shselasky}; 179290650Shselasky 180290650Shselaskystruct mlx5_wqe_fmr_seg { 181290650Shselasky __be32 flags; 182290650Shselasky __be32 mem_key; 183290650Shselasky __be64 buf_list; 184290650Shselasky __be64 start_addr; 185290650Shselasky __be64 reg_len; 186290650Shselasky __be32 offset; 187290650Shselasky __be32 page_size; 188290650Shselasky u32 reserved[2]; 189290650Shselasky}; 190290650Shselasky 191290650Shselaskystruct mlx5_wqe_ctrl_seg { 192290650Shselasky __be32 opmod_idx_opcode; 193290650Shselasky __be32 qpn_ds; 194290650Shselasky u8 signature; 195290650Shselasky u8 rsvd[2]; 196290650Shselasky u8 fm_ce_se; 197290650Shselasky __be32 imm; 198290650Shselasky}; 199290650Shselasky 200329204Shselasky#define MLX5_WQE_CTRL_DS_MASK 0x3f 201329204Shselasky 202290650Shselaskyenum { 203306233Shselasky MLX5_MLX_FLAG_MASK_VL15 = 0x40, 204306233Shselasky MLX5_MLX_FLAG_MASK_SLR = 0x20, 205306233Shselasky MLX5_MLX_FLAG_MASK_ICRC = 0x8, 206306233Shselasky MLX5_MLX_FLAG_MASK_FL = 4 207306233Shselasky}; 208306233Shselasky 209306233Shselaskystruct mlx5_mlx_seg { 210306233Shselasky __be32 rsvd0; 211306233Shselasky u8 flags; 212306233Shselasky u8 stat_rate_sl; 213306233Shselasky u8 rsvd1[8]; 214306233Shselasky __be16 dlid; 215306233Shselasky}; 216306233Shselasky 217306233Shselaskyenum { 218290650Shselasky MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4, 219290650Shselasky MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5, 220290650Shselasky MLX5_ETH_WQE_L3_CSUM = 1 << 6, 221290650Shselasky MLX5_ETH_WQE_L4_CSUM = 1 << 7, 222290650Shselasky}; 223290650Shselasky 224308678Shselaskyenum { 225329204Shselasky MLX5_ETH_WQE_SWP_INNER_L3_TYPE = 1 << 0, 226329204Shselasky MLX5_ETH_WQE_SWP_INNER_L4_TYPE = 1 << 1, 227329204Shselasky MLX5_ETH_WQE_SWP_OUTER_L3_TYPE = 1 << 4, 228329204Shselasky MLX5_ETH_WQE_SWP_OUTER_L4_TYPE = 1 << 5, 229308678Shselasky}; 230308678Shselasky 231290650Shselaskystruct mlx5_wqe_eth_seg { 232308678Shselasky u8 swp_outer_l4_offset; 233308678Shselasky u8 swp_outer_l3_offset; 234308678Shselasky u8 swp_inner_l4_offset; 235308678Shselasky u8 swp_inner_l3_offset; 236290650Shselasky u8 cs_flags; 237308678Shselasky u8 swp_flags; 238290650Shselasky __be16 mss; 239290650Shselasky __be32 rsvd2; 240337114Shselasky union { 241337114Shselasky struct { 242337114Shselasky __be16 inline_hdr_sz; 243337114Shselasky u8 inline_hdr_start[2]; 244337114Shselasky }; 245337114Shselasky struct { 246337114Shselasky __be16 vlan_cmd; 247337114Shselasky __be16 vlan_hdr; 248337114Shselasky }; 249337114Shselasky }; 250290650Shselasky}; 251290650Shselasky 252290650Shselaskystruct mlx5_wqe_xrc_seg { 253290650Shselasky __be32 xrc_srqn; 254290650Shselasky u8 rsvd[12]; 255290650Shselasky}; 256290650Shselasky 257290650Shselaskystruct mlx5_wqe_masked_atomic_seg { 258290650Shselasky __be64 swap_add; 259290650Shselasky __be64 compare; 260290650Shselasky __be64 swap_add_mask; 261290650Shselasky __be64 compare_mask; 262290650Shselasky}; 263290650Shselasky 264290650Shselaskystruct mlx5_av { 265290650Shselasky union { 266290650Shselasky struct { 267290650Shselasky __be32 qkey; 268290650Shselasky __be32 reserved; 269290650Shselasky } qkey; 270290650Shselasky __be64 dc_key; 271290650Shselasky } key; 272290650Shselasky __be32 dqp_dct; 273290650Shselasky u8 stat_rate_sl; 274290650Shselasky u8 fl_mlid; 275290650Shselasky union { 276290650Shselasky __be16 rlid; 277290650Shselasky __be16 udp_sport; 278290650Shselasky }; 279290650Shselasky u8 reserved0[4]; 280290650Shselasky u8 rmac[6]; 281290650Shselasky u8 tclass; 282290650Shselasky u8 hop_limit; 283290650Shselasky __be32 grh_gid_fl; 284290650Shselasky u8 rgid[16]; 285290650Shselasky}; 286290650Shselasky 287290650Shselaskystruct mlx5_wqe_datagram_seg { 288290650Shselasky struct mlx5_av av; 289290650Shselasky}; 290290650Shselasky 291290650Shselaskystruct mlx5_wqe_raddr_seg { 292290650Shselasky __be64 raddr; 293290650Shselasky __be32 rkey; 294290650Shselasky u32 reserved; 295290650Shselasky}; 296290650Shselasky 297290650Shselaskystruct mlx5_wqe_atomic_seg { 298290650Shselasky __be64 swap_add; 299290650Shselasky __be64 compare; 300290650Shselasky}; 301290650Shselasky 302290650Shselaskystruct mlx5_wqe_data_seg { 303290650Shselasky __be32 byte_count; 304290650Shselasky __be32 lkey; 305290650Shselasky __be64 addr; 306290650Shselasky}; 307290650Shselasky 308290650Shselaskystruct mlx5_wqe_umr_ctrl_seg { 309290650Shselasky u8 flags; 310290650Shselasky u8 rsvd0[3]; 311290650Shselasky __be16 klm_octowords; 312290650Shselasky __be16 bsf_octowords; 313290650Shselasky __be64 mkey_mask; 314290650Shselasky u8 rsvd1[32]; 315290650Shselasky}; 316290650Shselasky 317290650Shselaskystruct mlx5_seg_set_psv { 318290650Shselasky __be32 psv_num; 319290650Shselasky __be16 syndrome; 320290650Shselasky __be16 status; 321290650Shselasky __be32 transient_sig; 322290650Shselasky __be32 ref_tag; 323290650Shselasky}; 324290650Shselasky 325290650Shselaskystruct mlx5_seg_get_psv { 326290650Shselasky u8 rsvd[19]; 327290650Shselasky u8 num_psv; 328290650Shselasky __be32 l_key; 329290650Shselasky __be64 va; 330290650Shselasky __be32 psv_index[4]; 331290650Shselasky}; 332290650Shselasky 333290650Shselaskystruct mlx5_seg_check_psv { 334290650Shselasky u8 rsvd0[2]; 335290650Shselasky __be16 err_coalescing_op; 336290650Shselasky u8 rsvd1[2]; 337290650Shselasky __be16 xport_err_op; 338290650Shselasky u8 rsvd2[2]; 339290650Shselasky __be16 xport_err_mask; 340290650Shselasky u8 rsvd3[7]; 341290650Shselasky u8 num_psv; 342290650Shselasky __be32 l_key; 343290650Shselasky __be64 va; 344290650Shselasky __be32 psv_index[4]; 345290650Shselasky}; 346290650Shselasky 347290650Shselaskystruct mlx5_rwqe_sig { 348290650Shselasky u8 rsvd0[4]; 349290650Shselasky u8 signature; 350290650Shselasky u8 rsvd1[11]; 351290650Shselasky}; 352290650Shselasky 353290650Shselaskystruct mlx5_wqe_signature_seg { 354290650Shselasky u8 rsvd0[4]; 355290650Shselasky u8 signature; 356290650Shselasky u8 rsvd1[11]; 357290650Shselasky}; 358290650Shselasky 359290650Shselaskystruct mlx5_wqe_inline_seg { 360290650Shselasky __be32 byte_count; 361290650Shselasky}; 362290650Shselasky 363290650Shselaskyenum mlx5_sig_type { 364290650Shselasky MLX5_DIF_CRC = 0x1, 365290650Shselasky MLX5_DIF_IPCS = 0x2, 366290650Shselasky}; 367290650Shselasky 368290650Shselaskystruct mlx5_bsf_inl { 369290650Shselasky __be16 vld_refresh; 370290650Shselasky __be16 dif_apptag; 371290650Shselasky __be32 dif_reftag; 372290650Shselasky u8 sig_type; 373290650Shselasky u8 rp_inv_seed; 374290650Shselasky u8 rsvd[3]; 375290650Shselasky u8 dif_inc_ref_guard_check; 376290650Shselasky __be16 dif_app_bitmask_check; 377290650Shselasky}; 378290650Shselasky 379290650Shselaskystruct mlx5_bsf { 380290650Shselasky struct mlx5_bsf_basic { 381290650Shselasky u8 bsf_size_sbs; 382290650Shselasky u8 check_byte_mask; 383290650Shselasky union { 384290650Shselasky u8 copy_byte_mask; 385290650Shselasky u8 bs_selector; 386290650Shselasky u8 rsvd_wflags; 387290650Shselasky } wire; 388290650Shselasky union { 389290650Shselasky u8 bs_selector; 390290650Shselasky u8 rsvd_mflags; 391290650Shselasky } mem; 392290650Shselasky __be32 raw_data_size; 393290650Shselasky __be32 w_bfs_psv; 394290650Shselasky __be32 m_bfs_psv; 395290650Shselasky } basic; 396290650Shselasky struct mlx5_bsf_ext { 397290650Shselasky __be32 t_init_gen_pro_size; 398290650Shselasky __be32 rsvd_epi_size; 399290650Shselasky __be32 w_tfs_psv; 400290650Shselasky __be32 m_tfs_psv; 401290650Shselasky } ext; 402290650Shselasky struct mlx5_bsf_inl w_inl; 403290650Shselasky struct mlx5_bsf_inl m_inl; 404290650Shselasky}; 405290650Shselasky 406290650Shselaskystruct mlx5_klm { 407290650Shselasky __be32 bcount; 408290650Shselasky __be32 key; 409290650Shselasky __be64 va; 410290650Shselasky}; 411290650Shselasky 412290650Shselaskystruct mlx5_stride_block_entry { 413290650Shselasky __be16 stride; 414290650Shselasky __be16 bcount; 415290650Shselasky __be32 key; 416290650Shselasky __be64 va; 417290650Shselasky}; 418290650Shselasky 419290650Shselaskystruct mlx5_stride_block_ctrl_seg { 420290650Shselasky __be32 bcount_per_cycle; 421290650Shselasky __be32 op; 422290650Shselasky __be32 repeat_count; 423290650Shselasky u16 rsvd; 424290650Shselasky __be16 num_entries; 425290650Shselasky}; 426290650Shselasky 427329204Shselaskyenum mlx5_pagefault_flags { 428329204Shselasky MLX5_PFAULT_REQUESTOR = 1 << 0, 429329204Shselasky MLX5_PFAULT_WRITE = 1 << 1, 430329204Shselasky MLX5_PFAULT_RDMA = 1 << 2, 431329204Shselasky}; 432329204Shselasky 433329204Shselasky/* Contains the details of a pagefault. */ 434329204Shselaskystruct mlx5_pagefault { 435329204Shselasky u32 bytes_committed; 436329204Shselasky u8 event_subtype; 437329204Shselasky enum mlx5_pagefault_flags flags; 438329204Shselasky union { 439329204Shselasky /* Initiator or send message responder pagefault details. */ 440329204Shselasky struct { 441329204Shselasky /* Received packet size, only valid for responders. */ 442329204Shselasky u32 packet_size; 443329204Shselasky /* 444329204Shselasky * WQE index. Refers to either the send queue or 445329204Shselasky * receive queue, according to event_subtype. 446329204Shselasky */ 447329204Shselasky u16 wqe_index; 448329204Shselasky } wqe; 449329204Shselasky /* RDMA responder pagefault details */ 450329204Shselasky struct { 451329204Shselasky u32 r_key; 452329204Shselasky /* 453329204Shselasky * Received packet size, minimal size page fault 454329204Shselasky * resolution required for forward progress. 455329204Shselasky */ 456329204Shselasky u32 packet_size; 457329204Shselasky u32 rdma_op_len; 458329204Shselasky u64 rdma_va; 459329204Shselasky } rdma; 460329204Shselasky }; 461329204Shselasky}; 462329204Shselasky 463290650Shselaskystruct mlx5_core_qp { 464290650Shselasky struct mlx5_core_rsc_common common; /* must be first */ 465290650Shselasky void (*event) (struct mlx5_core_qp *, int); 466290650Shselasky int qpn; 467290650Shselasky struct mlx5_rsc_debug *dbg; 468290650Shselasky int pid; 469290650Shselasky}; 470290650Shselasky 471290650Shselaskystruct mlx5_qp_path { 472290650Shselasky u8 fl_free_ar; 473290650Shselasky u8 rsvd3; 474290650Shselasky __be16 pkey_index; 475290650Shselasky u8 rsvd0; 476290650Shselasky u8 grh_mlid; 477290650Shselasky __be16 rlid; 478290650Shselasky u8 ackto_lt; 479290650Shselasky u8 mgid_index; 480290650Shselasky u8 static_rate; 481290650Shselasky u8 hop_limit; 482290650Shselasky __be32 tclass_flowlabel; 483290650Shselasky union { 484290650Shselasky u8 rgid[16]; 485290650Shselasky u8 rip[16]; 486290650Shselasky }; 487290650Shselasky u8 f_dscp_ecn_prio; 488290650Shselasky u8 ecn_dscp; 489290650Shselasky __be16 udp_sport; 490290650Shselasky u8 dci_cfi_prio_sl; 491290650Shselasky u8 port; 492290650Shselasky u8 rmac[6]; 493290650Shselasky}; 494290650Shselasky 495290650Shselaskystruct mlx5_qp_context { 496290650Shselasky __be32 flags; 497290650Shselasky __be32 flags_pd; 498290650Shselasky u8 mtu_msgmax; 499290650Shselasky u8 rq_size_stride; 500290650Shselasky __be16 sq_crq_size; 501290650Shselasky __be32 qp_counter_set_usr_page; 502290650Shselasky __be32 wire_qpn; 503290650Shselasky __be32 log_pg_sz_remote_qpn; 504290650Shselasky struct mlx5_qp_path pri_path; 505290650Shselasky struct mlx5_qp_path alt_path; 506290650Shselasky __be32 params1; 507290650Shselasky u8 reserved2[4]; 508290650Shselasky __be32 next_send_psn; 509290650Shselasky __be32 cqn_send; 510329204Shselasky __be32 deth_sqpn; 511329204Shselasky u8 reserved3[4]; 512290650Shselasky __be32 last_acked_psn; 513290650Shselasky __be32 ssn; 514290650Shselasky __be32 params2; 515290650Shselasky __be32 rnr_nextrecvpsn; 516290650Shselasky __be32 xrcd; 517290650Shselasky __be32 cqn_recv; 518290650Shselasky __be64 db_rec_addr; 519290650Shselasky __be32 qkey; 520290650Shselasky __be32 rq_type_srqn; 521290650Shselasky __be32 rmsn; 522290650Shselasky __be16 hw_sq_wqe_counter; 523290650Shselasky __be16 sw_sq_wqe_counter; 524290650Shselasky __be16 hw_rcyclic_byte_counter; 525290650Shselasky __be16 hw_rq_counter; 526290650Shselasky __be16 sw_rcyclic_byte_counter; 527290650Shselasky __be16 sw_rq_counter; 528290650Shselasky u8 rsvd0[5]; 529290650Shselasky u8 cgs; 530290650Shselasky u8 cs_req; 531290650Shselasky u8 cs_res; 532290650Shselasky __be64 dc_access_key; 533290650Shselasky u8 rsvd1[24]; 534290650Shselasky}; 535290650Shselasky 536306233Shselaskystruct mlx5_dct_context { 537306233Shselasky u8 state; 538306233Shselasky u8 rsvd0[7]; 539306233Shselasky __be32 cqn; 540306233Shselasky __be32 flags; 541306233Shselasky u8 rsvd1; 542306233Shselasky u8 cs_res; 543306233Shselasky u8 min_rnr; 544306233Shselasky u8 rsvd2; 545306233Shselasky __be32 srqn; 546306233Shselasky __be32 pdn; 547306233Shselasky __be32 tclass_flow_label; 548306233Shselasky __be64 access_key; 549306233Shselasky u8 mtu; 550306233Shselasky u8 port; 551306233Shselasky __be16 pkey_index; 552306233Shselasky u8 rsvd4; 553306233Shselasky u8 mgid_index; 554306233Shselasky u8 rsvd5; 555306233Shselasky u8 hop_limit; 556306233Shselasky __be32 access_violations; 557306233Shselasky u8 rsvd[12]; 558306233Shselasky}; 559306233Shselasky 560290650Shselaskystatic inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn) 561290650Shselasky{ 562290650Shselasky return radix_tree_lookup(&dev->priv.qp_table.tree, qpn); 563290650Shselasky} 564290650Shselasky 565290650Shselaskystatic inline struct mlx5_core_mr *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key) 566290650Shselasky{ 567290650Shselasky return radix_tree_lookup(&dev->priv.mr_table.tree, key); 568290650Shselasky} 569290650Shselasky 570290650Shselaskyint mlx5_core_create_qp(struct mlx5_core_dev *dev, 571290650Shselasky struct mlx5_core_qp *qp, 572331807Shselasky u32 *in, 573290650Shselasky int inlen); 574331807Shselaskyint mlx5_core_qp_modify(struct mlx5_core_dev *dev, u16 opcode, 575331807Shselasky u32 opt_param_mask, void *qpc, 576290650Shselasky struct mlx5_core_qp *qp); 577290650Shselaskyint mlx5_core_destroy_qp(struct mlx5_core_dev *dev, 578290650Shselasky struct mlx5_core_qp *qp); 579290650Shselaskyint mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp, 580331807Shselasky u32 *out, int outlen); 581306233Shselaskyint mlx5_core_dct_query(struct mlx5_core_dev *dev, struct mlx5_core_dct *dct, 582331807Shselasky u32 *out, int outlen); 583306233Shselaskyint mlx5_core_arm_dct(struct mlx5_core_dev *dev, struct mlx5_core_dct *dct); 584290650Shselasky 585290650Shselaskyint mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn); 586290650Shselaskyint mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn); 587306233Shselaskyint mlx5_core_create_dct(struct mlx5_core_dev *dev, 588306233Shselasky struct mlx5_core_dct *dct, 589368220Shselasky u32 *in, int inlen, 590368220Shselasky u32 *out, int outlen); 591306233Shselaskyint mlx5_core_destroy_dct(struct mlx5_core_dev *dev, 592306233Shselasky struct mlx5_core_dct *dct); 593306233Shselaskyint mlx5_core_create_rq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen, 594306233Shselasky struct mlx5_core_qp *rq); 595306233Shselaskyvoid mlx5_core_destroy_rq_tracked(struct mlx5_core_dev *dev, 596306233Shselasky struct mlx5_core_qp *rq); 597306233Shselaskyint mlx5_core_create_sq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen, 598306233Shselasky struct mlx5_core_qp *sq); 599306233Shselaskyvoid mlx5_core_destroy_sq_tracked(struct mlx5_core_dev *dev, 600306233Shselasky struct mlx5_core_qp *sq); 601290650Shselaskyvoid mlx5_init_qp_table(struct mlx5_core_dev *dev); 602290650Shselaskyvoid mlx5_cleanup_qp_table(struct mlx5_core_dev *dev); 603290650Shselaskyint mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 604290650Shselaskyvoid mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 605290650Shselasky 606290650Shselaskystatic inline const char *mlx5_qp_type_str(int type) 607290650Shselasky{ 608290650Shselasky switch (type) { 609290650Shselasky case MLX5_QP_ST_RC: return "RC"; 610290650Shselasky case MLX5_QP_ST_UC: return "C"; 611290650Shselasky case MLX5_QP_ST_UD: return "UD"; 612290650Shselasky case MLX5_QP_ST_XRC: return "XRC"; 613290650Shselasky case MLX5_QP_ST_MLX: return "MLX"; 614306233Shselasky case MLX5_QP_ST_DCI: return "DCI"; 615290650Shselasky case MLX5_QP_ST_QP0: return "QP0"; 616290650Shselasky case MLX5_QP_ST_QP1: return "QP1"; 617290650Shselasky case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE"; 618290650Shselasky case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6"; 619290650Shselasky case MLX5_QP_ST_SNIFFER: return "SNIFFER"; 620290650Shselasky case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR"; 621290650Shselasky case MLX5_QP_ST_PTP_1588: return "PTP_1588"; 622290650Shselasky case MLX5_QP_ST_REG_UMR: return "REG_UMR"; 623306233Shselasky case MLX5_QP_ST_SW_CNAK: return "DC_CNAK"; 624290650Shselasky default: return "Invalid transport type"; 625290650Shselasky } 626290650Shselasky} 627290650Shselasky 628290650Shselaskystatic inline const char *mlx5_qp_state_str(int state) 629290650Shselasky{ 630290650Shselasky switch (state) { 631290650Shselasky case MLX5_QP_STATE_RST: 632290650Shselasky return "RST"; 633290650Shselasky case MLX5_QP_STATE_INIT: 634290650Shselasky return "INIT"; 635290650Shselasky case MLX5_QP_STATE_RTR: 636290650Shselasky return "RTR"; 637290650Shselasky case MLX5_QP_STATE_RTS: 638290650Shselasky return "RTS"; 639290650Shselasky case MLX5_QP_STATE_SQER: 640290650Shselasky return "SQER"; 641290650Shselasky case MLX5_QP_STATE_SQD: 642290650Shselasky return "SQD"; 643290650Shselasky case MLX5_QP_STATE_ERR: 644290650Shselasky return "ERR"; 645290650Shselasky case MLX5_QP_STATE_SQ_DRAINING: 646290650Shselasky return "SQ_DRAINING"; 647290650Shselasky case MLX5_QP_STATE_SUSPENDED: 648290650Shselasky return "SUSPENDED"; 649290650Shselasky default: return "Invalid QP state"; 650290650Shselasky } 651290650Shselasky} 652290650Shselasky 653290650Shselasky#endif /* MLX5_QP_H */ 654