port.h revision 341975
1/*-
2 * Copyright (c) 2016-2018, Mellanox Technologies, Ltd.  All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: stable/11/sys/dev/mlx5/port.h 341975 2018-12-12 13:03:51Z hselasky $
26 */
27
28#ifndef __MLX5_PORT_H__
29#define	__MLX5_PORT_H__
30
31#include <dev/mlx5/driver.h>
32
33enum mlx5_beacon_duration {
34	MLX5_BEACON_DURATION_OFF = 0x0,
35	MLX5_BEACON_DURATION_INF = 0xffff,
36};
37
38enum mlx5_module_id {
39	MLX5_MODULE_ID_SFP              = 0x3,
40	MLX5_MODULE_ID_QSFP             = 0xC,
41	MLX5_MODULE_ID_QSFP_PLUS        = 0xD,
42	MLX5_MODULE_ID_QSFP28           = 0x11,
43};
44
45enum mlx5_an_status {
46	MLX5_AN_UNAVAILABLE = 0,
47	MLX5_AN_COMPLETE    = 1,
48	MLX5_AN_FAILED      = 2,
49	MLX5_AN_LINK_UP     = 3,
50	MLX5_AN_LINK_DOWN   = 4,
51};
52
53#define	MLX5_EEPROM_MAX_BYTES			32
54#define	MLX5_EEPROM_IDENTIFIER_BYTE_MASK	0x000000ff
55#define	MLX5_EEPROM_REVISION_ID_BYTE_MASK       0x0000ff00
56#define	MLX5_EEPROM_PAGE_3_VALID_BIT_MASK       0x00040000
57#define	MLX5_I2C_ADDR_LOW		0x50
58#define	MLX5_I2C_ADDR_HIGH		0x51
59#define	MLX5_EEPROM_PAGE_LENGTH		256
60
61enum mlx5e_link_mode {
62	MLX5E_1000BASE_CX_SGMII	 = 0,
63	MLX5E_1000BASE_KX	 = 1,
64	MLX5E_10GBASE_CX4	 = 2,
65	MLX5E_10GBASE_KX4	 = 3,
66	MLX5E_10GBASE_KR	 = 4,
67	MLX5E_20GBASE_KR2	 = 5,
68	MLX5E_40GBASE_CR4	 = 6,
69	MLX5E_40GBASE_KR4	 = 7,
70	MLX5E_56GBASE_R4	 = 8,
71	MLX5E_10GBASE_CR	 = 12,
72	MLX5E_10GBASE_SR	 = 13,
73	MLX5E_10GBASE_ER	 = 14,
74	MLX5E_40GBASE_SR4	 = 15,
75	MLX5E_40GBASE_LR4	 = 16,
76	MLX5E_50GBASE_SR2	 = 18,
77	MLX5E_100GBASE_CR4	 = 20,
78	MLX5E_100GBASE_SR4	 = 21,
79	MLX5E_100GBASE_KR4	 = 22,
80	MLX5E_100GBASE_LR4	 = 23,
81	MLX5E_100BASE_TX	 = 24,
82	MLX5E_1000BASE_T	 = 25,
83	MLX5E_10GBASE_T		 = 26,
84	MLX5E_25GBASE_CR	 = 27,
85	MLX5E_25GBASE_KR	 = 28,
86	MLX5E_25GBASE_SR	 = 29,
87	MLX5E_50GBASE_CR2	 = 30,
88	MLX5E_50GBASE_KR2	 = 31,
89	MLX5E_LINK_MODES_NUMBER,
90};
91
92enum mlx5e_connector_type {
93	MLX5E_PORT_UNKNOWN	= 0,
94	MLX5E_PORT_NONE			= 1,
95	MLX5E_PORT_TP			= 2,
96	MLX5E_PORT_AUI			= 3,
97	MLX5E_PORT_BNC			= 4,
98	MLX5E_PORT_MII			= 5,
99	MLX5E_PORT_FIBRE		= 6,
100	MLX5E_PORT_DA			= 7,
101	MLX5E_PORT_OTHER		= 8,
102	MLX5E_CONNECTOR_TYPE_NUMBER,
103};
104
105enum mlx5_qpts_trust_state {
106	MLX5_QPTS_TRUST_PCP = 1,
107	MLX5_QPTS_TRUST_DSCP = 2,
108	MLX5_QPTS_TRUST_BOTH = 3,
109};
110
111#define	MLX5E_PROT_MASK(link_mode) (1 << (link_mode))
112
113#define	PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF
114#define	PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF
115
116int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
117int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
118			 int ptys_size, int proto_mask, u8 local_port);
119int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
120			      u32 *proto_cap, int proto_mask);
121int mlx5_query_port_autoneg(struct mlx5_core_dev *dev, int proto_mask,
122			    u8 *an_disable_cap, u8 *an_disable_status);
123int mlx5_set_port_autoneg(struct mlx5_core_dev *dev, bool disable,
124			  u32 eth_proto_admin, int proto_mask);
125int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
126				u32 *proto_admin, int proto_mask);
127int mlx5_query_port_eth_proto_oper(struct mlx5_core_dev *dev,
128				   u32 *proto_oper, u8 local_port);
129int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
130			int proto_mask);
131int mlx5_set_port_status(struct mlx5_core_dev *dev,
132			 enum mlx5_port_status status);
133int mlx5_query_port_status(struct mlx5_core_dev *dev, u8 *status);
134int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
135				 enum mlx5_port_status *status);
136int mlx5_set_port_pause_and_pfc(struct mlx5_core_dev *dev, u32 port,
137				u8 rx_pause, u8 tx_pause,
138				u8 pfc_en_rx, u8 pfc_en_tx);
139int mlx5_query_port_pause(struct mlx5_core_dev *dev, u32 port,
140			  u32 *rx_pause, u32 *tx_pause);
141int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx);
142
143int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu);
144int mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu);
145int mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu);
146
147unsigned int mlx5_query_module_status(struct mlx5_core_dev *dev, int module_num);
148int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num);
149int mlx5_query_eeprom(struct mlx5_core_dev *dev, int i2c_addr, int page_num,
150		      int device_addr, int size, int module_num, u32 *data,
151		      int *size_read);
152
153int mlx5_max_tc(struct mlx5_core_dev *mdev);
154int mlx5_query_port_tc_rate_limit(struct mlx5_core_dev *mdev,
155				   u8 *max_bw_value,
156				   u8 *max_bw_units);
157int mlx5_modify_port_tc_rate_limit(struct mlx5_core_dev *mdev,
158				   const u8 *max_bw_value,
159				   const u8 *max_bw_units);
160int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev,
161			    u8 prio, u8 *tc);
162int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, int prio_index,
163			  const u8 prio_tc);
164int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, const u8 *tc_group);
165int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev,
166			     u8 tc, u8 *tc_group);
167int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, const u8 *tc_bw);
168int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *bw_pct);
169
170int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state);
171int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state);
172
173#define	MLX5_MAX_SUPPORTED_DSCP 64
174int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, const u8 *dscp2prio);
175int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio);
176
177int mlx5_query_pddr_range_info(struct mlx5_core_dev *mdev, u8 local_port, u8 *is_er_type);
178
179#endif /* __MLX5_PORT_H__ */
180