mlx5io.h revision 347841 
1/*-
2 * Copyright (c) 2018, Mellanox Technologies, Ltd.  All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: stable/11/sys/dev/mlx5/mlx5io.h 347841 2019-05-16 17:50:52Z hselasky $
26 */
27
28#ifndef _DEV_MLX5_MLX5IO_H_
29#define _DEV_MLX5_MLX5IO_H_
30
31#include <sys/ioccom.h>
32
33struct mlx5_fwdump_reg {
34	uint32_t addr;
35	uint32_t val;
36};
37
38struct mlx5_tool_addr {
39	uint32_t domain;
40	uint8_t bus;
41	uint8_t slot;
42	uint8_t func;
43};
44
45struct mlx5_fwdump_get {
46	struct mlx5_tool_addr devaddr;
47	struct mlx5_fwdump_reg *buf;
48	size_t reg_cnt;
49	size_t reg_filled; /* out */
50};
51
52struct mlx5_fw_update {
53	struct mlx5_tool_addr devaddr;
54	void *img_fw_data;
55	size_t img_fw_data_len;
56};
57
58#define	MLX5_FWDUMP_GET		_IOWR('m', 1, struct mlx5_fwdump_get)
59#define	MLX5_FWDUMP_RESET	_IOW('m', 2, struct mlx5_tool_addr)
60#define	MLX5_FWDUMP_FORCE	_IOW('m', 3, struct mlx5_tool_addr)
61#define	MLX5_FW_UPDATE		_IOW('m', 4, struct mlx5_fw_update)
62
63#ifndef _KERNEL
64#define	MLX5_DEV_PATH	_PATH_DEV"mlx5ctl"
65#endif
66
67enum mlx5_fpga_id {
68	MLX5_FPGA_NEWTON = 0,
69	MLX5_FPGA_EDISON = 1,
70	MLX5_FPGA_MORSE = 2,
71	MLX5_FPGA_MORSEQ = 3,
72};
73
74enum mlx5_fpga_image {
75	MLX5_FPGA_IMAGE_USER = 0,
76	MLX5_FPGA_IMAGE_FACTORY = 1,
77	MLX5_FPGA_IMAGE_FACTORY_FAILOVER = 2,
78	MLX5_FPGA_IMAGE_RESET = 17,
79	MLX5_FPGA_IMAGE_RELOAD = 18,
80};
81
82enum mlx5_fpga_status {
83	MLX5_FPGA_STATUS_SUCCESS = 0,
84	MLX5_FPGA_STATUS_FAILURE = 1,
85	MLX5_FPGA_STATUS_IN_PROGRESS = 2,
86	MLX5_FPGA_STATUS_DISCONNECTED = 3,
87};
88
89struct mlx5_fpga_query {
90	enum mlx5_fpga_image admin_image;
91	enum mlx5_fpga_image oper_image;
92	enum mlx5_fpga_status image_status;
93};
94
95enum mlx5_fpga_tee {
96	MLX5_FPGA_TEE_DISABLE = 0,
97	MLX5_FPGA_TEE_GENERATE_EVENT = 1,
98	MLX5_FPGA_TEE_GENERATE_SINGLE_EVENT = 2,
99};
100
101enum mlx5_fpga_connect {
102	MLX5_FPGA_CONNECT_QUERY = 0,
103	MLX5_FPGA_CONNECT_DISCONNECT = 0x9,
104	MLX5_FPGA_CONNECT_CONNECT = 0xA,
105};
106
107/**
108 * enum mlx5_fpga_access_type - Enumerated the different methods possible for
109 * accessing the device memory address space
110 */
111enum mlx5_fpga_access_type {
112	/** Use the slow CX-FPGA I2C bus*/
113	MLX5_FPGA_ACCESS_TYPE_I2C = 0x0,
114	/** Use the fast 'shell QP' */
115	MLX5_FPGA_ACCESS_TYPE_RDMA,
116	/** Use the fastest available method */
117	MLX5_FPGA_ACCESS_TYPE_DONTCARE,
118	MLX5_FPGA_ACCESS_TYPE_MAX = MLX5_FPGA_ACCESS_TYPE_DONTCARE,
119};
120
121#define MLX5_FPGA_INTERNAL_SENSORS_LOW 63
122#define MLX5_FPGA_INTERNAL_SENSORS_HIGH 63
123
124struct mlx5_fpga_temperature {
125	uint32_t temperature;
126	uint32_t index;
127	uint32_t tee;
128	uint32_t max_temperature;
129	uint32_t temperature_threshold_hi;
130	uint32_t temperature_threshold_lo;
131	uint32_t mte;
132	uint32_t mtr;
133	char sensor_name[16];
134};
135
136#define	MLX5_FPGA_CAP_ARR_SZ 0x40
137
138#define	MLX5_FPGA_ACCESS_TYPE	_IOWINT('m', 0x80)
139#define	MLX5_FPGA_LOAD		_IOWINT('m', 0x81)
140#define	MLX5_FPGA_RESET		_IO('m', 0x82)
141#define	MLX5_FPGA_IMAGE_SEL	_IOWINT('m', 0x83)
142#define	MLX5_FPGA_QUERY		_IOR('m', 0x84, struct mlx5_fpga_query)
143#define	MLX5_FPGA_CAP		_IOR('m', 0x85, uint32_t[MLX5_FPGA_CAP_ARR_SZ])
144#define	MLX5_FPGA_TEMPERATURE	_IOWR('m', 0x86, struct mlx5_fpga_temperature)
145#define	MLX5_FPGA_CONNECT	_IOWR('m', 0x87, enum mlx5_fpga_connect)
146#define	MLX5_FPGA_RELOAD	_IO('m', 0x88)
147
148#define	MLX5_FPGA_TOOLS_NAME_SUFFIX	"_mlx5_fpga_tools"
149
150#endif
151