1330653Shselasky/*- 2330653Shselasky * Copyright (c) 2018, Mellanox Technologies, Ltd. All rights reserved. 3330653Shselasky * 4330653Shselasky * Redistribution and use in source and binary forms, with or without 5330653Shselasky * modification, are permitted provided that the following conditions 6330653Shselasky * are met: 7330653Shselasky * 1. Redistributions of source code must retain the above copyright 8330653Shselasky * notice, this list of conditions and the following disclaimer. 9330653Shselasky * 2. Redistributions in binary form must reproduce the above copyright 10330653Shselasky * notice, this list of conditions and the following disclaimer in the 11330653Shselasky * documentation and/or other materials provided with the distribution. 12330653Shselasky * 13330653Shselasky * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14330653Shselasky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15330653Shselasky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16330653Shselasky * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17330653Shselasky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18330653Shselasky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19330653Shselasky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20330653Shselasky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21330653Shselasky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22330653Shselasky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23330653Shselasky * SUCH DAMAGE. 24330653Shselasky * 25330653Shselasky * $FreeBSD: stable/11/sys/dev/mlx5/mlx5io.h 353240 2019-10-07 09:46:33Z hselasky $ 26330653Shselasky */ 27330653Shselasky 28330653Shselasky#ifndef _DEV_MLX5_MLX5IO_H_ 29330653Shselasky#define _DEV_MLX5_MLX5IO_H_ 30330653Shselasky 31330653Shselasky#include <sys/ioccom.h> 32330653Shselasky 33330653Shselaskystruct mlx5_fwdump_reg { 34330653Shselasky uint32_t addr; 35330653Shselasky uint32_t val; 36330653Shselasky}; 37330653Shselasky 38347840Shselaskystruct mlx5_tool_addr { 39330653Shselasky uint32_t domain; 40330653Shselasky uint8_t bus; 41330653Shselasky uint8_t slot; 42330653Shselasky uint8_t func; 43330653Shselasky}; 44330653Shselasky 45330653Shselaskystruct mlx5_fwdump_get { 46347840Shselasky struct mlx5_tool_addr devaddr; 47330653Shselasky struct mlx5_fwdump_reg *buf; 48330653Shselasky size_t reg_cnt; 49330653Shselasky size_t reg_filled; /* out */ 50330653Shselasky}; 51330653Shselasky 52347841Shselaskystruct mlx5_fw_update { 53347841Shselasky struct mlx5_tool_addr devaddr; 54347841Shselasky void *img_fw_data; 55347841Shselasky size_t img_fw_data_len; 56347841Shselasky}; 57347841Shselasky 58353240Shselaskystruct mlx5_eeprom_get { 59353240Shselasky struct mlx5_tool_addr devaddr; 60353240Shselasky uint32_t *eeprom_info_buf; 61353240Shselasky uint8_t eeprom_info_page_valid; 62353240Shselasky size_t eeprom_info_out_len; 63353240Shselasky}; 64353240Shselasky 65330653Shselasky#define MLX5_FWDUMP_GET _IOWR('m', 1, struct mlx5_fwdump_get) 66347840Shselasky#define MLX5_FWDUMP_RESET _IOW('m', 2, struct mlx5_tool_addr) 67347840Shselasky#define MLX5_FWDUMP_FORCE _IOW('m', 3, struct mlx5_tool_addr) 68347841Shselasky#define MLX5_FW_UPDATE _IOW('m', 4, struct mlx5_fw_update) 69347869Shselasky#define MLX5_FW_RESET _IOW('m', 5, struct mlx5_tool_addr) 70353240Shselasky#define MLX5_EEPROM_GET _IOWR('m', 6, struct mlx5_eeprom_get) 71330653Shselasky 72330653Shselasky#ifndef _KERNEL 73330653Shselasky#define MLX5_DEV_PATH _PATH_DEV"mlx5ctl" 74330653Shselasky#endif 75330653Shselasky 76341958Shselaskyenum mlx5_fpga_id { 77341958Shselasky MLX5_FPGA_NEWTON = 0, 78341958Shselasky MLX5_FPGA_EDISON = 1, 79341958Shselasky MLX5_FPGA_MORSE = 2, 80341962Shselasky MLX5_FPGA_MORSEQ = 3, 81341958Shselasky}; 82341958Shselasky 83341958Shselaskyenum mlx5_fpga_image { 84341958Shselasky MLX5_FPGA_IMAGE_USER = 0, 85341958Shselasky MLX5_FPGA_IMAGE_FACTORY = 1, 86341958Shselasky MLX5_FPGA_IMAGE_FACTORY_FAILOVER = 2, 87347797Shselasky MLX5_FPGA_IMAGE_RESET = 17, 88347797Shselasky MLX5_FPGA_IMAGE_RELOAD = 18, 89341958Shselasky}; 90341958Shselasky 91341958Shselaskyenum mlx5_fpga_status { 92341958Shselasky MLX5_FPGA_STATUS_SUCCESS = 0, 93341958Shselasky MLX5_FPGA_STATUS_FAILURE = 1, 94341958Shselasky MLX5_FPGA_STATUS_IN_PROGRESS = 2, 95341958Shselasky MLX5_FPGA_STATUS_DISCONNECTED = 3, 96341958Shselasky}; 97341958Shselasky 98341958Shselaskystruct mlx5_fpga_query { 99341958Shselasky enum mlx5_fpga_image admin_image; 100341958Shselasky enum mlx5_fpga_image oper_image; 101341958Shselasky enum mlx5_fpga_status image_status; 102341958Shselasky}; 103341958Shselasky 104341964Shselaskyenum mlx5_fpga_tee { 105341964Shselasky MLX5_FPGA_TEE_DISABLE = 0, 106341964Shselasky MLX5_FPGA_TEE_GENERATE_EVENT = 1, 107341964Shselasky MLX5_FPGA_TEE_GENERATE_SINGLE_EVENT = 2, 108341964Shselasky}; 109341964Shselasky 110341966Shselaskyenum mlx5_fpga_connect { 111341966Shselasky MLX5_FPGA_CONNECT_QUERY = 0, 112341966Shselasky MLX5_FPGA_CONNECT_DISCONNECT = 0x9, 113341966Shselasky MLX5_FPGA_CONNECT_CONNECT = 0xA, 114341966Shselasky}; 115341966Shselasky 116341958Shselasky/** 117341958Shselasky * enum mlx5_fpga_access_type - Enumerated the different methods possible for 118341958Shselasky * accessing the device memory address space 119341958Shselasky */ 120341958Shselaskyenum mlx5_fpga_access_type { 121341958Shselasky /** Use the slow CX-FPGA I2C bus*/ 122341958Shselasky MLX5_FPGA_ACCESS_TYPE_I2C = 0x0, 123341958Shselasky /** Use the fast 'shell QP' */ 124341958Shselasky MLX5_FPGA_ACCESS_TYPE_RDMA, 125341958Shselasky /** Use the fastest available method */ 126341958Shselasky MLX5_FPGA_ACCESS_TYPE_DONTCARE, 127341958Shselasky MLX5_FPGA_ACCESS_TYPE_MAX = MLX5_FPGA_ACCESS_TYPE_DONTCARE, 128341958Shselasky}; 129341958Shselasky 130341964Shselasky#define MLX5_FPGA_INTERNAL_SENSORS_LOW 63 131341964Shselasky#define MLX5_FPGA_INTERNAL_SENSORS_HIGH 63 132341964Shselasky 133341964Shselaskystruct mlx5_fpga_temperature { 134341964Shselasky uint32_t temperature; 135341964Shselasky uint32_t index; 136341964Shselasky uint32_t tee; 137341964Shselasky uint32_t max_temperature; 138341964Shselasky uint32_t temperature_threshold_hi; 139341964Shselasky uint32_t temperature_threshold_lo; 140341964Shselasky uint32_t mte; 141341964Shselasky uint32_t mtr; 142341964Shselasky char sensor_name[16]; 143341964Shselasky}; 144341964Shselasky 145341960Shselasky#define MLX5_FPGA_CAP_ARR_SZ 0x40 146341960Shselasky 147341960Shselasky#define MLX5_FPGA_ACCESS_TYPE _IOWINT('m', 0x80) 148341960Shselasky#define MLX5_FPGA_LOAD _IOWINT('m', 0x81) 149341960Shselasky#define MLX5_FPGA_RESET _IO('m', 0x82) 150341960Shselasky#define MLX5_FPGA_IMAGE_SEL _IOWINT('m', 0x83) 151341960Shselasky#define MLX5_FPGA_QUERY _IOR('m', 0x84, struct mlx5_fpga_query) 152341960Shselasky#define MLX5_FPGA_CAP _IOR('m', 0x85, uint32_t[MLX5_FPGA_CAP_ARR_SZ]) 153341964Shselasky#define MLX5_FPGA_TEMPERATURE _IOWR('m', 0x86, struct mlx5_fpga_temperature) 154341966Shselasky#define MLX5_FPGA_CONNECT _IOWR('m', 0x87, enum mlx5_fpga_connect) 155347797Shselasky#define MLX5_FPGA_RELOAD _IO('m', 0x88) 156341960Shselasky 157341960Shselasky#define MLX5_FPGA_TOOLS_NAME_SUFFIX "_mlx5_fpga_tools" 158341960Shselasky 159330653Shselasky#endif 160