mlx5_ifc.h revision 361171 
1/*-
2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd.  All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_ifc.h 361171 2020-05-18 09:04:24Z hselasky $
26 */
27
28#ifndef MLX5_IFC_H
29#define MLX5_IFC_H
30
31#include <dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h>
32
33enum {
34	MLX5_EVENT_TYPE_COMP                                       = 0x0,
35	MLX5_EVENT_TYPE_PATH_MIG                                   = 0x1,
36	MLX5_EVENT_TYPE_COMM_EST                                   = 0x2,
37	MLX5_EVENT_TYPE_SQ_DRAINED                                 = 0x3,
38	MLX5_EVENT_TYPE_SRQ_LAST_WQE                               = 0x13,
39	MLX5_EVENT_TYPE_SRQ_RQ_LIMIT                               = 0x14,
40	MLX5_EVENT_TYPE_DCT_DRAINED                                = 0x1c,
41	MLX5_EVENT_TYPE_DCT_KEY_VIOLATION                          = 0x1d,
42	MLX5_EVENT_TYPE_CQ_ERROR                                   = 0x4,
43	MLX5_EVENT_TYPE_WQ_CATAS_ERROR                             = 0x5,
44	MLX5_EVENT_TYPE_PATH_MIG_FAILED                            = 0x7,
45	MLX5_EVENT_TYPE_PAGE_FAULT                                 = 0xc,
46	MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR                         = 0x10,
47	MLX5_EVENT_TYPE_WQ_ACCESS_ERROR                            = 0x11,
48	MLX5_EVENT_TYPE_SRQ_CATAS_ERROR                            = 0x12,
49	MLX5_EVENT_TYPE_INTERNAL_ERROR                             = 0x8,
50	MLX5_EVENT_TYPE_PORT_CHANGE                                = 0x9,
51	MLX5_EVENT_TYPE_GPIO_EVENT                                 = 0x15,
52	MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT                   = 0x16,
53	MLX5_EVENT_TYPE_TEMP_WARN_EVENT                            = 0x17,
54	MLX5_EVENT_TYPE_REMOTE_CONFIG                              = 0x19,
55	MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT                   = 0x1e,
56	MLX5_EVENT_TYPE_CODING_PPS_EVENT                           = 0x25,
57	MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT          = 0x22,
58	MLX5_EVENT_TYPE_DB_BF_CONGESTION                           = 0x1a,
59	MLX5_EVENT_TYPE_STALL_EVENT                                = 0x1b,
60	MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT                = 0x1f,
61	MLX5_EVENT_TYPE_CMD                                        = 0xa,
62	MLX5_EVENT_TYPE_PAGE_REQUEST                               = 0xb,
63	MLX5_EVENT_TYPE_NIC_VPORT_CHANGE                           = 0xd,
64	MLX5_EVENT_TYPE_FPGA_ERROR                                 = 0x20,
65	MLX5_EVENT_TYPE_FPGA_QP_ERROR                              = 0x21,
66};
67
68enum {
69	MLX5_MODIFY_TIR_BITMASK_LRO                                = 0x0,
70	MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE                     = 0x1,
71	MLX5_MODIFY_TIR_BITMASK_HASH                               = 0x2,
72	MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN                = 0x3,
73	MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN                         = 0x4
74};
75
76enum {
77	MLX5_MODIFY_RQT_BITMASK_RQN_LIST          = 0x1,
78};
79
80enum {
81	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
82	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
83};
84
85enum {
86	MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
87	MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
88	MLX5_CMD_OP_INIT_HCA                      = 0x102,
89	MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
90	MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
91	MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
92	MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
93	MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
94	MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
95	MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
96	MLX5_CMD_OP_SET_ISSI                      = 0x10b,
97	MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
98	MLX5_CMD_OP_QUERY_OTHER_HCA_CAP           = 0x10e,
99	MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP          = 0x10f,
100	MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
101	MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
102	MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
103	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
104	MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
105	MLX5_CMD_OP_CREATE_EQ                     = 0x301,
106	MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
107	MLX5_CMD_OP_QUERY_EQ                      = 0x303,
108	MLX5_CMD_OP_GEN_EQE                       = 0x304,
109	MLX5_CMD_OP_CREATE_CQ                     = 0x400,
110	MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
111	MLX5_CMD_OP_QUERY_CQ                      = 0x402,
112	MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
113	MLX5_CMD_OP_CREATE_QP                     = 0x500,
114	MLX5_CMD_OP_DESTROY_QP                    = 0x501,
115	MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
116	MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
117	MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
118	MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
119	MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
120	MLX5_CMD_OP_2ERR_QP                       = 0x507,
121	MLX5_CMD_OP_2RST_QP                       = 0x50a,
122	MLX5_CMD_OP_QUERY_QP                      = 0x50b,
123	MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
124	MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
125	MLX5_CMD_OP_CREATE_PSV                    = 0x600,
126	MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
127	MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
128	MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
129	MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
130	MLX5_CMD_OP_ARM_RQ                        = 0x703,
131	MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
132	MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
133	MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
134	MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
135	MLX5_CMD_OP_CREATE_DCT                    = 0x710,
136	MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
137	MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
138	MLX5_CMD_OP_QUERY_DCT                     = 0x713,
139	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
140	MLX5_CMD_OP_SET_DC_CNAK_TRACE             = 0x715,
141	MLX5_CMD_OP_QUERY_DC_CNAK_TRACE           = 0x716,
142	MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
143	MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
144	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
145	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
146	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
147	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
148	MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
149	MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
150	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
151	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
152	MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
153	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
154	MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
155	MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
156	MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
157	MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
158	MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
159	MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
160	MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
161	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT     = 0x782,
162	MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT    = 0x783,
163	MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT      = 0x784,
164	MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT     = 0x785,
165	MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
166	MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
167	MLX5_CMD_OP_ALLOC_PD                      = 0x800,
168	MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
169	MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
170	MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
171	MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
172	MLX5_CMD_OP_ACCESS_REG                    = 0x805,
173	MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
174	MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
175	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
176	MLX5_CMD_OP_MAD_IFC                       = 0x50d,
177	MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
178	MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
179	MLX5_CMD_OP_NOP                           = 0x80d,
180	MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
181	MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
182	MLX5_CMD_OP_SET_BURST_SIZE                = 0x812,
183	MLX5_CMD_OP_QUERY_BURST_SIZE              = 0x813,
184	MLX5_CMD_OP_ACTIVATE_TRACER               = 0x814,
185	MLX5_CMD_OP_DEACTIVATE_TRACER             = 0x815,
186	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
187	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
188	MLX5_CMD_OP_SET_DIAGNOSTICS               = 0x820,
189	MLX5_CMD_OP_QUERY_DIAGNOSTICS             = 0x821,
190	MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
191	MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
192	MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
193	MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
194	MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
195	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
196	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
197	MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
198	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
199	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
200	MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
201	MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
202	MLX5_CMD_OP_CREATE_LAG                    = 0x840,
203	MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
204	MLX5_CMD_OP_QUERY_LAG                     = 0x842,
205	MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
206	MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
207	MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
208	MLX5_CMD_OP_CREATE_TIR                    = 0x900,
209	MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
210	MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
211	MLX5_CMD_OP_QUERY_TIR                     = 0x903,
212	MLX5_CMD_OP_CREATE_SQ                     = 0x904,
213	MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
214	MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
215	MLX5_CMD_OP_QUERY_SQ                      = 0x907,
216	MLX5_CMD_OP_CREATE_RQ                     = 0x908,
217	MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
218	MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
219	MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
220	MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
221	MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
222	MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
223	MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
224	MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
225	MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS       = 0x911,
226	MLX5_CMD_OP_CREATE_TIS                    = 0x912,
227	MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
228	MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
229	MLX5_CMD_OP_QUERY_TIS                     = 0x915,
230	MLX5_CMD_OP_CREATE_RQT                    = 0x916,
231	MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
232	MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
233	MLX5_CMD_OP_QUERY_RQT                     = 0x919,
234	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
235	MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
236	MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
237	MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
238	MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
239	MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
240	MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
241	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
242	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
243	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
244	MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
245	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
246	MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
247	MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
248	MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
249	MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
250	MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
251	MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
252	MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
253	MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
254	MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
255};
256
257enum {
258	MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO     = 0x8007,
259	MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY         = 0x8400,
260	MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER          = 0x9001,
261	MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC        = 0x9003,
262	MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC          = 0x9004,
263	MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL            = 0x9005,
264	MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL              = 0x9006,
265	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT                = 0x9007,
266	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008,
267	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS   = 0x9009,
268	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT           = 0x900a,
269	MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD         = 0xf004
270};
271
272struct mlx5_ifc_flow_table_fields_supported_bits {
273	u8         outer_dmac[0x1];
274	u8         outer_smac[0x1];
275	u8         outer_ether_type[0x1];
276	u8         reserved_0[0x1];
277	u8         outer_first_prio[0x1];
278	u8         outer_first_cfi[0x1];
279	u8         outer_first_vid[0x1];
280	u8         reserved_1[0x1];
281	u8         outer_second_prio[0x1];
282	u8         outer_second_cfi[0x1];
283	u8         outer_second_vid[0x1];
284	u8         outer_ipv6_flow_label[0x1];
285	u8         outer_sip[0x1];
286	u8         outer_dip[0x1];
287	u8         outer_frag[0x1];
288	u8         outer_ip_protocol[0x1];
289	u8         outer_ip_ecn[0x1];
290	u8         outer_ip_dscp[0x1];
291	u8         outer_udp_sport[0x1];
292	u8         outer_udp_dport[0x1];
293	u8         outer_tcp_sport[0x1];
294	u8         outer_tcp_dport[0x1];
295	u8         outer_tcp_flags[0x1];
296	u8         outer_gre_protocol[0x1];
297	u8         outer_gre_key[0x1];
298	u8         outer_vxlan_vni[0x1];
299	u8         outer_geneve_vni[0x1];
300	u8         outer_geneve_oam[0x1];
301	u8         outer_geneve_protocol_type[0x1];
302	u8         outer_geneve_opt_len[0x1];
303	u8         reserved_2[0x1];
304	u8         source_eswitch_port[0x1];
305
306	u8         inner_dmac[0x1];
307	u8         inner_smac[0x1];
308	u8         inner_ether_type[0x1];
309	u8         reserved_3[0x1];
310	u8         inner_first_prio[0x1];
311	u8         inner_first_cfi[0x1];
312	u8         inner_first_vid[0x1];
313	u8         reserved_4[0x1];
314	u8         inner_second_prio[0x1];
315	u8         inner_second_cfi[0x1];
316	u8         inner_second_vid[0x1];
317	u8         inner_ipv6_flow_label[0x1];
318	u8         inner_sip[0x1];
319	u8         inner_dip[0x1];
320	u8         inner_frag[0x1];
321	u8         inner_ip_protocol[0x1];
322	u8         inner_ip_ecn[0x1];
323	u8         inner_ip_dscp[0x1];
324	u8         inner_udp_sport[0x1];
325	u8         inner_udp_dport[0x1];
326	u8         inner_tcp_sport[0x1];
327	u8         inner_tcp_dport[0x1];
328	u8         inner_tcp_flags[0x1];
329	u8         reserved_5[0x9];
330
331	u8         reserved_6[0x1a];
332	u8         bth_dst_qp[0x1];
333	u8         reserved_7[0x4];
334	u8         source_sqn[0x1];
335
336	u8         reserved_8[0x20];
337};
338
339struct mlx5_ifc_eth_discard_cntrs_grp_bits {
340	u8         ingress_general_high[0x20];
341
342	u8         ingress_general_low[0x20];
343
344	u8         ingress_policy_engine_high[0x20];
345
346	u8         ingress_policy_engine_low[0x20];
347
348	u8         ingress_vlan_membership_high[0x20];
349
350	u8         ingress_vlan_membership_low[0x20];
351
352	u8         ingress_tag_frame_type_high[0x20];
353
354	u8         ingress_tag_frame_type_low[0x20];
355
356	u8         egress_vlan_membership_high[0x20];
357
358	u8         egress_vlan_membership_low[0x20];
359
360	u8         loopback_filter_high[0x20];
361
362	u8         loopback_filter_low[0x20];
363
364	u8         egress_general_high[0x20];
365
366	u8         egress_general_low[0x20];
367
368	u8         reserved_at_1c0[0x40];
369
370	u8         egress_hoq_high[0x20];
371
372	u8         egress_hoq_low[0x20];
373
374	u8         port_isolation_high[0x20];
375
376	u8         port_isolation_low[0x20];
377
378	u8         egress_policy_engine_high[0x20];
379
380	u8         egress_policy_engine_low[0x20];
381
382	u8         ingress_tx_link_down_high[0x20];
383
384	u8         ingress_tx_link_down_low[0x20];
385
386	u8         egress_stp_filter_high[0x20];
387
388	u8         egress_stp_filter_low[0x20];
389
390	u8         egress_hoq_stall_high[0x20];
391
392	u8         egress_hoq_stall_low[0x20];
393
394	u8         reserved_at_340[0x440];
395};
396struct mlx5_ifc_flow_table_prop_layout_bits {
397	u8         ft_support[0x1];
398	u8         flow_tag[0x1];
399	u8         flow_counter[0x1];
400	u8         flow_modify_en[0x1];
401	u8         modify_root[0x1];
402	u8         identified_miss_table[0x1];
403	u8         flow_table_modify[0x1];
404	u8         encap[0x1];
405	u8         decap[0x1];
406	u8         reset_root_to_default[0x1];
407	u8         reserved_at_a[0x16];
408
409	u8         reserved_at_20[0x2];
410	u8         log_max_ft_size[0x6];
411	u8         reserved_at_28[0x10];
412	u8         max_ft_level[0x8];
413
414	u8         reserved_at_40[0x20];
415
416	u8         reserved_at_60[0x18];
417	u8         log_max_ft_num[0x8];
418
419	u8         reserved_at_80[0x10];
420	u8         log_max_flow_counter[0x8];
421	u8         log_max_destination[0x8];
422
423	u8         reserved_at_a0[0x18];
424	u8         log_max_flow[0x8];
425
426	u8         reserved_at_c0[0x40];
427
428	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
429
430	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
431};
432
433struct mlx5_ifc_odp_per_transport_service_cap_bits {
434	u8         send[0x1];
435	u8         receive[0x1];
436	u8         write[0x1];
437	u8         read[0x1];
438	u8         atomic[0x1];
439	u8         srq_receive[0x1];
440	u8         reserved_0[0x1a];
441};
442
443struct mlx5_ifc_flow_counter_list_bits {
444	u8         reserved_0[0x10];
445	u8         flow_counter_id[0x10];
446
447	u8         reserved_1[0x20];
448};
449
450enum {
451	MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT                    = 0x0,
452	MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE               = 0x1,
453	MLX5_FLOW_CONTEXT_DEST_TYPE_TIR                      = 0x2,
454	MLX5_FLOW_CONTEXT_DEST_TYPE_QP                       = 0x3,
455};
456
457struct mlx5_ifc_dest_format_struct_bits {
458	u8         destination_type[0x8];
459	u8         destination_id[0x18];
460
461	u8         reserved_0[0x20];
462};
463
464struct mlx5_ifc_ipv4_layout_bits {
465	u8         reserved_at_0[0x60];
466
467	u8         ipv4[0x20];
468};
469
470struct mlx5_ifc_ipv6_layout_bits {
471	u8         ipv6[16][0x8];
472};
473
474union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
475	struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
476	struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
477	u8         reserved_at_0[0x80];
478};
479
480struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
481	u8         smac_47_16[0x20];
482
483	u8         smac_15_0[0x10];
484	u8         ethertype[0x10];
485
486	u8         dmac_47_16[0x20];
487
488	u8         dmac_15_0[0x10];
489	u8         first_prio[0x3];
490	u8         first_cfi[0x1];
491	u8         first_vid[0xc];
492
493	u8         ip_protocol[0x8];
494	u8         ip_dscp[0x6];
495	u8         ip_ecn[0x2];
496	u8         cvlan_tag[0x1];
497	u8         svlan_tag[0x1];
498	u8         frag[0x1];
499	u8         reserved_1[0x4];
500	u8         tcp_flags[0x9];
501
502	u8         tcp_sport[0x10];
503	u8         tcp_dport[0x10];
504
505	u8         reserved_2[0x20];
506
507	u8         udp_sport[0x10];
508	u8         udp_dport[0x10];
509
510	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
511
512	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
513};
514
515struct mlx5_ifc_fte_match_set_misc_bits {
516	u8         reserved_0[0x8];
517	u8         source_sqn[0x18];
518
519	u8         reserved_1[0x10];
520	u8         source_port[0x10];
521
522	u8         outer_second_prio[0x3];
523	u8         outer_second_cfi[0x1];
524	u8         outer_second_vid[0xc];
525	u8         inner_second_prio[0x3];
526	u8         inner_second_cfi[0x1];
527	u8         inner_second_vid[0xc];
528
529	u8         outer_second_vlan_tag[0x1];
530	u8         inner_second_vlan_tag[0x1];
531	u8         reserved_2[0xe];
532	u8         gre_protocol[0x10];
533
534	u8         gre_key_h[0x18];
535	u8         gre_key_l[0x8];
536
537	u8         vxlan_vni[0x18];
538	u8         reserved_3[0x8];
539
540	u8         geneve_vni[0x18];
541	u8         reserved4[0x7];
542	u8         geneve_oam[0x1];
543
544	u8         reserved_5[0xc];
545	u8         outer_ipv6_flow_label[0x14];
546
547	u8         reserved_6[0xc];
548	u8         inner_ipv6_flow_label[0x14];
549
550	u8         reserved_7[0xa];
551	u8         geneve_opt_len[0x6];
552	u8         geneve_protocol_type[0x10];
553
554	u8         reserved_8[0x8];
555	u8         bth_dst_qp[0x18];
556
557	u8         reserved_9[0xa0];
558};
559
560struct mlx5_ifc_cmd_pas_bits {
561	u8         pa_h[0x20];
562
563	u8         pa_l[0x14];
564	u8         reserved_0[0xc];
565};
566
567struct mlx5_ifc_uint64_bits {
568	u8         hi[0x20];
569
570	u8         lo[0x20];
571};
572
573struct mlx5_ifc_application_prio_entry_bits {
574	u8         reserved_0[0x8];
575	u8         priority[0x3];
576	u8         reserved_1[0x2];
577	u8         sel[0x3];
578	u8         protocol_id[0x10];
579};
580
581struct mlx5_ifc_nodnic_ring_doorbell_bits {
582	u8         reserved_0[0x8];
583	u8         ring_pi[0x10];
584	u8         reserved_1[0x8];
585};
586
587enum {
588	MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
589	MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
590	MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
591	MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
592	MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
593	MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
594	MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
595	MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
596	MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
597	MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
598};
599
600struct mlx5_ifc_ads_bits {
601	u8         fl[0x1];
602	u8         free_ar[0x1];
603	u8         reserved_0[0xe];
604	u8         pkey_index[0x10];
605
606	u8         reserved_1[0x8];
607	u8         grh[0x1];
608	u8         mlid[0x7];
609	u8         rlid[0x10];
610
611	u8         ack_timeout[0x5];
612	u8         reserved_2[0x3];
613	u8         src_addr_index[0x8];
614	u8         log_rtm[0x4];
615	u8         stat_rate[0x4];
616	u8         hop_limit[0x8];
617
618	u8         reserved_3[0x4];
619	u8         tclass[0x8];
620	u8         flow_label[0x14];
621
622	u8         rgid_rip[16][0x8];
623
624	u8         reserved_4[0x4];
625	u8         f_dscp[0x1];
626	u8         f_ecn[0x1];
627	u8         reserved_5[0x1];
628	u8         f_eth_prio[0x1];
629	u8         ecn[0x2];
630	u8         dscp[0x6];
631	u8         udp_sport[0x10];
632
633	u8         dei_cfi[0x1];
634	u8         eth_prio[0x3];
635	u8         sl[0x4];
636	u8         port[0x8];
637	u8         rmac_47_32[0x10];
638
639	u8         rmac_31_0[0x20];
640};
641
642struct mlx5_ifc_diagnostic_counter_cap_bits {
643	u8         sync[0x1];
644	u8         reserved_0[0xf];
645	u8         counter_id[0x10];
646};
647
648struct mlx5_ifc_debug_cap_bits {
649	u8         reserved_0[0x18];
650	u8         log_max_samples[0x8];
651
652	u8         single[0x1];
653	u8         repetitive[0x1];
654	u8         health_mon_rx_activity[0x1];
655	u8         reserved_1[0x15];
656	u8         log_min_sample_period[0x8];
657
658	u8         reserved_2[0x1c0];
659
660	struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0];
661};
662
663struct mlx5_ifc_qos_cap_bits {
664	u8         packet_pacing[0x1];
665	u8         esw_scheduling[0x1];
666	u8         esw_bw_share[0x1];
667	u8         esw_rate_limit[0x1];
668	u8         hll[0x1];
669	u8         packet_pacing_burst_bound[0x1];
670	u8         reserved_at_6[0x1a];
671
672	u8         reserved_at_20[0x20];
673
674	u8         packet_pacing_max_rate[0x20];
675
676	u8         packet_pacing_min_rate[0x20];
677
678	u8         reserved_at_80[0x10];
679	u8         packet_pacing_rate_table_size[0x10];
680
681	u8         esw_element_type[0x10];
682	u8         esw_tsar_type[0x10];
683
684	u8         reserved_at_c0[0x10];
685	u8         max_qos_para_vport[0x10];
686
687	u8         max_tsar_bw_share[0x20];
688
689	u8         reserved_at_100[0x700];
690};
691
692struct mlx5_ifc_snapshot_cap_bits {
693	u8         reserved_0[0x1d];
694	u8         suspend_qp_uc[0x1];
695	u8         suspend_qp_ud[0x1];
696	u8         suspend_qp_rc[0x1];
697
698	u8         reserved_1[0x1c];
699	u8         restore_pd[0x1];
700	u8         restore_uar[0x1];
701	u8         restore_mkey[0x1];
702	u8         restore_qp[0x1];
703
704	u8         reserved_2[0x1e];
705	u8         named_mkey[0x1];
706	u8         named_qp[0x1];
707
708	u8         reserved_3[0x7a0];
709};
710
711struct mlx5_ifc_e_switch_cap_bits {
712	u8         vport_svlan_strip[0x1];
713	u8         vport_cvlan_strip[0x1];
714	u8         vport_svlan_insert[0x1];
715	u8         vport_cvlan_insert_if_not_exist[0x1];
716	u8         vport_cvlan_insert_overwrite[0x1];
717
718	u8         reserved_0[0x19];
719
720	u8         nic_vport_node_guid_modify[0x1];
721	u8         nic_vport_port_guid_modify[0x1];
722
723	u8         reserved_1[0x7e0];
724};
725
726struct mlx5_ifc_flow_table_eswitch_cap_bits {
727	u8         reserved_0[0x200];
728
729	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
730
731	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
732
733	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
734
735	u8         reserved_1[0x7800];
736};
737
738struct mlx5_ifc_flow_table_nic_cap_bits {
739	u8         nic_rx_multi_path_tirs[0x1];
740	u8         nic_rx_multi_path_tirs_fts[0x1];
741	u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
742	u8         reserved_at_3[0x1fd];
743
744	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
745
746	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
747
748	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
749
750	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
751
752	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
753
754	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
755
756	u8         reserved_1[0x7200];
757};
758
759enum {
760	MLX5_ACCESS_REG_SUMMARY_CTRL_ID_PDDR                   = 0x5031,
761};
762
763struct mlx5_ifc_pddr_module_info_bits {
764	u8         cable_technology[0x8];
765	u8         cable_breakout[0x8];
766	u8         ext_ethernet_compliance_code[0x8];
767	u8         ethernet_compliance_code[0x8];
768
769	u8         cable_type[0x4];
770	u8         cable_vendor[0x4];
771	u8         cable_length[0x8];
772	u8         cable_identifier[0x8];
773	u8         cable_power_class[0x8];
774
775	u8         reserved_at_40[0x8];
776	u8         cable_rx_amp[0x8];
777	u8         cable_rx_emphasis[0x8];
778	u8         cable_tx_equalization[0x8];
779
780	u8         reserved_at_60[0x8];
781	u8         cable_attenuation_12g[0x8];
782	u8         cable_attenuation_7g[0x8];
783	u8         cable_attenuation_5g[0x8];
784
785	u8         reserved_at_80[0x8];
786	u8         rx_cdr_cap[0x4];
787	u8         tx_cdr_cap[0x4];
788	u8         reserved_at_90[0x4];
789	u8         rx_cdr_state[0x4];
790	u8         reserved_at_98[0x4];
791	u8         tx_cdr_state[0x4];
792
793	u8         vendor_name[16][0x8];
794
795	u8         vendor_pn[16][0x8];
796
797	u8         vendor_rev[0x20];
798
799	u8         fw_version[0x20];
800
801	u8         vendor_sn[16][0x8];
802
803	u8         temperature[0x10];
804	u8         voltage[0x10];
805
806	u8         rx_power_lane0[0x10];
807	u8         rx_power_lane1[0x10];
808
809	u8         rx_power_lane2[0x10];
810	u8         rx_power_lane3[0x10];
811
812	u8         reserved_at_2c0[0x40];
813
814	u8         tx_power_lane0[0x10];
815	u8         tx_power_lane1[0x10];
816
817	u8         tx_power_lane2[0x10];
818	u8         tx_power_lane3[0x10];
819
820	u8         reserved_at_340[0x40];
821
822	u8         tx_bias_lane0[0x10];
823	u8         tx_bias_lane1[0x10];
824
825	u8         tx_bias_lane2[0x10];
826	u8         tx_bias_lane3[0x10];
827
828	u8         reserved_at_3c0[0x40];
829
830	u8         temperature_high_th[0x10];
831	u8         temperature_low_th[0x10];
832
833	u8         voltage_high_th[0x10];
834	u8         voltage_low_th[0x10];
835
836	u8         rx_power_high_th[0x10];
837	u8         rx_power_low_th[0x10];
838
839	u8         tx_power_high_th[0x10];
840	u8         tx_power_low_th[0x10];
841
842	u8         tx_bias_high_th[0x10];
843	u8         tx_bias_low_th[0x10];
844
845	u8         reserved_at_4a0[0x10];
846	u8         wavelength[0x10];
847
848	u8         reserved_at_4c0[0x300];
849};
850
851union mlx5_ifc_pddr_operation_info_page_pddr_phy_info_page_pddr_troubleshooting_page_pddr_module_info_auto_bits {
852	struct mlx5_ifc_pddr_module_info_bits pddr_module_info;
853	u8         reserved_at_0[0x7c0];
854};
855
856struct mlx5_ifc_pddr_reg_bits {
857	u8         reserved_at_0[0x8];
858	u8         local_port[0x8];
859	u8         pnat[0x2];
860	u8         reserved_at_12[0xe];
861
862	u8         reserved_at_20[0x18];
863	u8         page_select[0x8];
864
865	union mlx5_ifc_pddr_operation_info_page_pddr_phy_info_page_pddr_troubleshooting_page_pddr_module_info_auto_bits page_data;
866};
867
868struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
869	u8         csum_cap[0x1];
870	u8         vlan_cap[0x1];
871	u8         lro_cap[0x1];
872	u8         lro_psh_flag[0x1];
873	u8         lro_time_stamp[0x1];
874	u8         lro_max_msg_sz_mode[0x2];
875	u8         wqe_vlan_insert[0x1];
876	u8         self_lb_en_modifiable[0x1];
877	u8         self_lb_mc[0x1];
878	u8         self_lb_uc[0x1];
879	u8         max_lso_cap[0x5];
880	u8         multi_pkt_send_wqe[0x2];
881	u8         wqe_inline_mode[0x2];
882	u8         rss_ind_tbl_cap[0x4];
883	u8         scatter_fcs[0x1];
884	u8         reserved_1[0x2];
885	u8         tunnel_lso_const_out_ip_id[0x1];
886	u8         tunnel_lro_gre[0x1];
887	u8         tunnel_lro_vxlan[0x1];
888	u8         tunnel_statless_gre[0x1];
889	u8         tunnel_stateless_vxlan[0x1];
890
891	u8         swp[0x1];
892	u8         swp_csum[0x1];
893	u8         swp_lso[0x1];
894	u8         reserved_2[0x1b];
895	u8         max_geneve_opt_len[0x1];
896	u8         tunnel_stateless_geneve_rx[0x1];
897
898	u8         reserved_3[0x10];
899	u8         lro_min_mss_size[0x10];
900
901	u8         reserved_4[0x120];
902
903	u8         lro_timer_supported_periods[4][0x20];
904
905	u8         reserved_5[0x600];
906};
907
908enum {
909	MLX5_ROCE_CAP_L3_TYPE_GRH   = 0x1,
910	MLX5_ROCE_CAP_L3_TYPE_IPV4  = 0x2,
911	MLX5_ROCE_CAP_L3_TYPE_IPV6  = 0x4,
912};
913
914struct mlx5_ifc_roce_cap_bits {
915	u8         roce_apm[0x1];
916	u8         rts2rts_primary_eth_prio[0x1];
917	u8         roce_rx_allow_untagged[0x1];
918	u8         rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1];
919
920	u8         reserved_0[0x1c];
921
922	u8         reserved_1[0x60];
923
924	u8         reserved_2[0xc];
925	u8         l3_type[0x4];
926	u8         reserved_3[0x8];
927	u8         roce_version[0x8];
928
929	u8         reserved_4[0x10];
930	u8         r_roce_dest_udp_port[0x10];
931
932	u8         r_roce_max_src_udp_port[0x10];
933	u8         r_roce_min_src_udp_port[0x10];
934
935	u8         reserved_5[0x10];
936	u8         roce_address_table_size[0x10];
937
938	u8         reserved_6[0x700];
939};
940
941enum {
942	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x1,
943	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
944	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
945	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
946	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
947	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
948	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
949	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
950	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
951};
952
953enum {
954	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
955	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
956	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
957	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
958	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
959	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
960	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
961	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
962	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
963};
964
965struct mlx5_ifc_atomic_caps_bits {
966	u8         reserved_0[0x40];
967
968	u8         atomic_req_8B_endianess_mode[0x2];
969	u8         reserved_1[0x4];
970	u8         supported_atomic_req_8B_endianess_mode_1[0x1];
971
972	u8         reserved_2[0x19];
973
974	u8         reserved_3[0x20];
975
976	u8         reserved_4[0x10];
977	u8         atomic_operations[0x10];
978
979	u8         reserved_5[0x10];
980	u8         atomic_size_qp[0x10];
981
982	u8         reserved_6[0x10];
983	u8         atomic_size_dc[0x10];
984
985	u8         reserved_7[0x720];
986};
987
988struct mlx5_ifc_odp_cap_bits {
989	u8         reserved_0[0x40];
990
991	u8         sig[0x1];
992	u8         reserved_1[0x1f];
993
994	u8         reserved_2[0x20];
995
996	struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
997
998	struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
999
1000	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1001
1002	struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1003
1004	struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1005
1006	u8         reserved_3[0x6e0];
1007};
1008
1009enum {
1010	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1011	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1012	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1013	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1014	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1015};
1016
1017enum {
1018	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1019	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1020	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1021	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1022	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1023	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1024};
1025
1026enum {
1027	MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1028	MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1029};
1030
1031enum {
1032	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1033	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1034	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1035};
1036
1037struct mlx5_ifc_cmd_hca_cap_bits {
1038	u8         reserved_0[0x80];
1039
1040	u8         log_max_srq_sz[0x8];
1041	u8         log_max_qp_sz[0x8];
1042	u8         reserved_1[0xb];
1043	u8         log_max_qp[0x5];
1044
1045	u8         reserved_2[0xb];
1046	u8         log_max_srq[0x5];
1047	u8         reserved_3[0x10];
1048
1049	u8         reserved_4[0x8];
1050	u8         log_max_cq_sz[0x8];
1051	u8         reserved_5[0xb];
1052	u8         log_max_cq[0x5];
1053
1054	u8         log_max_eq_sz[0x8];
1055	u8         relaxed_ordering_write[1];
1056	u8         reserved_6[0x1];
1057	u8         log_max_mkey[0x6];
1058	u8         reserved_7[0xb];
1059	u8         fast_teardown[0x1];
1060	u8         log_max_eq[0x4];
1061
1062	u8         max_indirection[0x8];
1063	u8         reserved_8[0x1];
1064	u8         log_max_mrw_sz[0x7];
1065	u8	   force_teardown[0x1];
1066	u8         reserved_9[0x1];
1067	u8         log_max_bsf_list_size[0x6];
1068	u8         reserved_10[0x2];
1069	u8         log_max_klm_list_size[0x6];
1070
1071	u8         reserved_11[0xa];
1072	u8         log_max_ra_req_dc[0x6];
1073	u8         reserved_12[0xa];
1074	u8         log_max_ra_res_dc[0x6];
1075
1076	u8         reserved_13[0xa];
1077	u8         log_max_ra_req_qp[0x6];
1078	u8         reserved_14[0xa];
1079	u8         log_max_ra_res_qp[0x6];
1080
1081	u8         pad_cap[0x1];
1082	u8         cc_query_allowed[0x1];
1083	u8         cc_modify_allowed[0x1];
1084	u8         start_pad[0x1];
1085	u8         cache_line_128byte[0x1];
1086	u8         reserved_at_165[0xa];
1087	u8         qcam_reg[0x1];
1088	u8         gid_table_size[0x10];
1089
1090	u8         out_of_seq_cnt[0x1];
1091	u8         vport_counters[0x1];
1092	u8         retransmission_q_counters[0x1];
1093	u8         debug[0x1];
1094	u8         modify_rq_counters_set_id[0x1];
1095	u8         rq_delay_drop[0x1];
1096	u8         max_qp_cnt[0xa];
1097	u8         pkey_table_size[0x10];
1098
1099	u8         vport_group_manager[0x1];
1100	u8         vhca_group_manager[0x1];
1101	u8         ib_virt[0x1];
1102	u8         eth_virt[0x1];
1103	u8         reserved_17[0x1];
1104	u8         ets[0x1];
1105	u8         nic_flow_table[0x1];
1106	u8         eswitch_flow_table[0x1];
1107	u8         reserved_18[0x1];
1108	u8         mcam_reg[0x1];
1109	u8         pcam_reg[0x1];
1110	u8         local_ca_ack_delay[0x5];
1111	u8         port_module_event[0x1];
1112	u8         reserved_19[0x5];
1113	u8         port_type[0x2];
1114	u8         num_ports[0x8];
1115
1116	u8         snapshot[0x1];
1117	u8         reserved_20[0x2];
1118	u8         log_max_msg[0x5];
1119	u8         reserved_21[0x4];
1120	u8         max_tc[0x4];
1121	u8         temp_warn_event[0x1];
1122	u8         dcbx[0x1];
1123	u8         general_notification_event[0x1];
1124	u8         reserved_at_1d3[0x2];
1125	u8         fpga[0x1];
1126	u8         rol_s[0x1];
1127	u8         rol_g[0x1];
1128	u8         reserved_23[0x1];
1129	u8         wol_s[0x1];
1130	u8         wol_g[0x1];
1131	u8         wol_a[0x1];
1132	u8         wol_b[0x1];
1133	u8         wol_m[0x1];
1134	u8         wol_u[0x1];
1135	u8         wol_p[0x1];
1136
1137	u8         stat_rate_support[0x10];
1138	u8         reserved_24[0xc];
1139	u8         cqe_version[0x4];
1140
1141	u8         compact_address_vector[0x1];
1142	u8         striding_rq[0x1];
1143	u8         reserved_25[0x1];
1144	u8         ipoib_enhanced_offloads[0x1];
1145	u8         ipoib_ipoib_offloads[0x1];
1146	u8         reserved_26[0x8];
1147	u8         dc_connect_qp[0x1];
1148	u8         dc_cnak_trace[0x1];
1149	u8         drain_sigerr[0x1];
1150	u8         cmdif_checksum[0x2];
1151	u8         sigerr_cqe[0x1];
1152	u8         reserved_27[0x1];
1153	u8         wq_signature[0x1];
1154	u8         sctr_data_cqe[0x1];
1155	u8         reserved_28[0x1];
1156	u8         sho[0x1];
1157	u8         tph[0x1];
1158	u8         rf[0x1];
1159	u8         dct[0x1];
1160	u8         qos[0x1];
1161	u8         eth_net_offloads[0x1];
1162	u8         roce[0x1];
1163	u8         atomic[0x1];
1164	u8         reserved_30[0x1];
1165
1166	u8         cq_oi[0x1];
1167	u8         cq_resize[0x1];
1168	u8         cq_moderation[0x1];
1169	u8         cq_period_mode_modify[0x1];
1170	u8         cq_invalidate[0x1];
1171	u8         reserved_at_225[0x1];
1172	u8         cq_eq_remap[0x1];
1173	u8         pg[0x1];
1174	u8         block_lb_mc[0x1];
1175	u8         exponential_backoff[0x1];
1176	u8         scqe_break_moderation[0x1];
1177	u8         cq_period_start_from_cqe[0x1];
1178	u8         cd[0x1];
1179	u8         atm[0x1];
1180	u8         apm[0x1];
1181	u8	   imaicl[0x1];
1182	u8         reserved_32[0x6];
1183	u8         qkv[0x1];
1184	u8         pkv[0x1];
1185	u8	   set_deth_sqpn[0x1];
1186	u8         reserved_33[0x3];
1187	u8         xrc[0x1];
1188	u8         ud[0x1];
1189	u8         uc[0x1];
1190	u8         rc[0x1];
1191
1192	u8         reserved_34[0xa];
1193	u8         uar_sz[0x6];
1194	u8         reserved_35[0x8];
1195	u8         log_pg_sz[0x8];
1196
1197	u8         bf[0x1];
1198	u8         driver_version[0x1];
1199	u8         pad_tx_eth_packet[0x1];
1200	u8         reserved_36[0x8];
1201	u8         log_bf_reg_size[0x5];
1202	u8         reserved_37[0x10];
1203
1204	u8         num_of_diagnostic_counters[0x10];
1205	u8         max_wqe_sz_sq[0x10];
1206
1207	u8         reserved_38[0x10];
1208	u8         max_wqe_sz_rq[0x10];
1209
1210	u8         reserved_39[0x10];
1211	u8         max_wqe_sz_sq_dc[0x10];
1212
1213	u8         reserved_40[0x7];
1214	u8         max_qp_mcg[0x19];
1215
1216	u8         reserved_41[0x18];
1217	u8         log_max_mcg[0x8];
1218
1219	u8         reserved_42[0x3];
1220	u8         log_max_transport_domain[0x5];
1221	u8         reserved_43[0x3];
1222	u8         log_max_pd[0x5];
1223	u8         reserved_44[0xb];
1224	u8         log_max_xrcd[0x5];
1225
1226	u8         nic_receive_steering_discard[0x1];
1227	u8	   reserved_45[0x7];
1228	u8         log_max_flow_counter_bulk[0x8];
1229	u8         max_flow_counter[0x10];
1230
1231	u8         reserved_46[0x3];
1232	u8         log_max_rq[0x5];
1233	u8         reserved_47[0x3];
1234	u8         log_max_sq[0x5];
1235	u8         reserved_48[0x3];
1236	u8         log_max_tir[0x5];
1237	u8         reserved_49[0x3];
1238	u8         log_max_tis[0x5];
1239
1240	u8         basic_cyclic_rcv_wqe[0x1];
1241	u8         reserved_50[0x2];
1242	u8         log_max_rmp[0x5];
1243	u8         reserved_51[0x3];
1244	u8         log_max_rqt[0x5];
1245	u8         reserved_52[0x3];
1246	u8         log_max_rqt_size[0x5];
1247	u8         reserved_53[0x3];
1248	u8         log_max_tis_per_sq[0x5];
1249
1250	u8         reserved_54[0x3];
1251	u8         log_max_stride_sz_rq[0x5];
1252	u8         reserved_55[0x3];
1253	u8         log_min_stride_sz_rq[0x5];
1254	u8         reserved_56[0x3];
1255	u8         log_max_stride_sz_sq[0x5];
1256	u8         reserved_57[0x3];
1257	u8         log_min_stride_sz_sq[0x5];
1258
1259	u8         reserved_58[0x1b];
1260	u8         log_max_wq_sz[0x5];
1261
1262	u8         nic_vport_change_event[0x1];
1263	u8         disable_local_lb[0x1];
1264	u8         reserved_59[0x9];
1265	u8         log_max_vlan_list[0x5];
1266	u8         reserved_60[0x3];
1267	u8         log_max_current_mc_list[0x5];
1268	u8         reserved_61[0x3];
1269	u8         log_max_current_uc_list[0x5];
1270
1271	u8         reserved_62[0x80];
1272
1273	u8         reserved_63[0x3];
1274	u8         log_max_l2_table[0x5];
1275	u8         reserved_64[0x8];
1276	u8         log_uar_page_sz[0x10];
1277
1278	u8         reserved_65[0x20];
1279
1280	u8         device_frequency_mhz[0x20];
1281
1282	u8         device_frequency_khz[0x20];
1283
1284	u8         reserved_66[0x80];
1285
1286	u8         log_max_atomic_size_qp[0x8];
1287	u8         reserved_67[0x10];
1288	u8         log_max_atomic_size_dc[0x8];
1289
1290	u8         reserved_68[0x1f];
1291	u8         cqe_compression[0x1];
1292
1293	u8         cqe_compression_timeout[0x10];
1294	u8         cqe_compression_max_num[0x10];
1295
1296	u8         reserved_69[0x220];
1297};
1298
1299enum mlx5_flow_destination_type {
1300	MLX5_FLOW_DESTINATION_TYPE_VPORT	= 0x0,
1301	MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE	= 0x1,
1302	MLX5_FLOW_DESTINATION_TYPE_TIR		= 0x2,
1303};
1304
1305union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1306	struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1307	struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1308	u8         reserved_0[0x40];
1309};
1310
1311struct mlx5_ifc_fte_match_param_bits {
1312	struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1313
1314	struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1315
1316	struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1317
1318	u8         reserved_0[0xa00];
1319};
1320
1321enum {
1322	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1323	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1324	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1325	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1326	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1327};
1328
1329struct mlx5_ifc_rx_hash_field_select_bits {
1330	u8         l3_prot_type[0x1];
1331	u8         l4_prot_type[0x1];
1332	u8         selected_fields[0x1e];
1333};
1334
1335enum {
1336	MLX5_WQ_TYPE_LINKED_LIST                 = 0x0,
1337	MLX5_WQ_TYPE_CYCLIC                      = 0x1,
1338	MLX5_WQ_TYPE_STRQ_LINKED_LIST            = 0x2,
1339	MLX5_WQ_TYPE_STRQ_CYCLIC                 = 0x3,
1340};
1341
1342enum rq_type {
1343	RQ_TYPE_NONE,
1344	RQ_TYPE_STRIDE,
1345};
1346
1347enum {
1348	MLX5_WQ_END_PAD_MODE_NONE               = 0x0,
1349	MLX5_WQ_END_PAD_MODE_ALIGN              = 0x1,
1350};
1351
1352struct mlx5_ifc_wq_bits {
1353	u8         wq_type[0x4];
1354	u8         wq_signature[0x1];
1355	u8         end_padding_mode[0x2];
1356	u8         cd_slave[0x1];
1357	u8         reserved_0[0x18];
1358
1359	u8         hds_skip_first_sge[0x1];
1360	u8         log2_hds_buf_size[0x3];
1361	u8         reserved_1[0x7];
1362	u8         page_offset[0x5];
1363	u8         lwm[0x10];
1364
1365	u8         reserved_2[0x8];
1366	u8         pd[0x18];
1367
1368	u8         reserved_3[0x8];
1369	u8         uar_page[0x18];
1370
1371	u8         dbr_addr[0x40];
1372
1373	u8         hw_counter[0x20];
1374
1375	u8         sw_counter[0x20];
1376
1377	u8         reserved_4[0xc];
1378	u8         log_wq_stride[0x4];
1379	u8         reserved_5[0x3];
1380	u8         log_wq_pg_sz[0x5];
1381	u8         reserved_6[0x3];
1382	u8         log_wq_sz[0x5];
1383
1384	u8         reserved_7[0x15];
1385	u8         single_wqe_log_num_of_strides[0x3];
1386	u8         two_byte_shift_en[0x1];
1387	u8         reserved_8[0x4];
1388	u8         single_stride_log_num_of_bytes[0x3];
1389
1390	u8         reserved_9[0x4c0];
1391
1392	struct mlx5_ifc_cmd_pas_bits pas[0];
1393};
1394
1395struct mlx5_ifc_rq_num_bits {
1396	u8         reserved_0[0x8];
1397	u8         rq_num[0x18];
1398};
1399
1400struct mlx5_ifc_mac_address_layout_bits {
1401	u8         reserved_0[0x10];
1402	u8         mac_addr_47_32[0x10];
1403
1404	u8         mac_addr_31_0[0x20];
1405};
1406
1407struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1408	u8         reserved_0[0xa0];
1409
1410	u8         min_time_between_cnps[0x20];
1411
1412	u8         reserved_1[0x12];
1413	u8         cnp_dscp[0x6];
1414	u8         reserved_2[0x4];
1415	u8         cnp_prio_mode[0x1];
1416	u8         cnp_802p_prio[0x3];
1417
1418	u8         reserved_3[0x720];
1419};
1420
1421struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1422	u8         reserved_0[0x60];
1423
1424	u8         reserved_1[0x4];
1425	u8         clamp_tgt_rate[0x1];
1426	u8         reserved_2[0x3];
1427	u8         clamp_tgt_rate_after_time_inc[0x1];
1428	u8         reserved_3[0x17];
1429
1430	u8         reserved_4[0x20];
1431
1432	u8         rpg_time_reset[0x20];
1433
1434	u8         rpg_byte_reset[0x20];
1435
1436	u8         rpg_threshold[0x20];
1437
1438	u8         rpg_max_rate[0x20];
1439
1440	u8         rpg_ai_rate[0x20];
1441
1442	u8         rpg_hai_rate[0x20];
1443
1444	u8         rpg_gd[0x20];
1445
1446	u8         rpg_min_dec_fac[0x20];
1447
1448	u8         rpg_min_rate[0x20];
1449
1450	u8         reserved_5[0xe0];
1451
1452	u8         rate_to_set_on_first_cnp[0x20];
1453
1454	u8         dce_tcp_g[0x20];
1455
1456	u8         dce_tcp_rtt[0x20];
1457
1458	u8         rate_reduce_monitor_period[0x20];
1459
1460	u8         reserved_6[0x20];
1461
1462	u8         initial_alpha_value[0x20];
1463
1464	u8         reserved_7[0x4a0];
1465};
1466
1467struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1468	u8         reserved_0[0x80];
1469
1470	u8         rppp_max_rps[0x20];
1471
1472	u8         rpg_time_reset[0x20];
1473
1474	u8         rpg_byte_reset[0x20];
1475
1476	u8         rpg_threshold[0x20];
1477
1478	u8         rpg_max_rate[0x20];
1479
1480	u8         rpg_ai_rate[0x20];
1481
1482	u8         rpg_hai_rate[0x20];
1483
1484	u8         rpg_gd[0x20];
1485
1486	u8         rpg_min_dec_fac[0x20];
1487
1488	u8         rpg_min_rate[0x20];
1489
1490	u8         reserved_1[0x640];
1491};
1492
1493enum {
1494	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1495	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1496	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1497};
1498
1499struct mlx5_ifc_resize_field_select_bits {
1500	u8         resize_field_select[0x20];
1501};
1502
1503enum {
1504	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1505	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1506	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1507	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1508	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE  = 0x10,
1509	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS          = 0x20,
1510};
1511
1512struct mlx5_ifc_modify_field_select_bits {
1513	u8         modify_field_select[0x20];
1514};
1515
1516struct mlx5_ifc_field_select_r_roce_np_bits {
1517	u8         field_select_r_roce_np[0x20];
1518};
1519
1520enum {
1521	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE                 = 0x2,
1522	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC  = 0x4,
1523	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET                 = 0x8,
1524	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET                 = 0x10,
1525	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD                  = 0x20,
1526	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE                   = 0x40,
1527	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE                    = 0x80,
1528	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE                   = 0x100,
1529	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC                = 0x200,
1530	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE                   = 0x400,
1531	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP       = 0x800,
1532	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G                      = 0x1000,
1533	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT                    = 0x2000,
1534	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD     = 0x4000,
1535	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE            = 0x8000,
1536};
1537
1538struct mlx5_ifc_field_select_r_roce_rp_bits {
1539	u8         field_select_r_roce_rp[0x20];
1540};
1541
1542enum {
1543	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1544	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1545	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1546	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1547	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1548	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1549	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1550	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1551	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1552	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1553};
1554
1555struct mlx5_ifc_field_select_802_1qau_rp_bits {
1556	u8         field_select_8021qaurp[0x20];
1557};
1558
1559struct mlx5_ifc_pptb_reg_bits {
1560	u8         reserved_at_0[0x2];
1561	u8         mm[0x2];
1562	u8         reserved_at_4[0x4];
1563	u8         local_port[0x8];
1564	u8         reserved_at_10[0x6];
1565	u8         cm[0x1];
1566	u8         um[0x1];
1567	u8         pm[0x8];
1568
1569	u8         prio_x_buff[0x20];
1570
1571	u8         pm_msb[0x8];
1572	u8         reserved_at_48[0x10];
1573	u8         ctrl_buff[0x4];
1574	u8         untagged_buff[0x4];
1575};
1576
1577struct mlx5_ifc_dcbx_app_reg_bits {
1578	u8         reserved_0[0x8];
1579	u8         port_number[0x8];
1580	u8         reserved_1[0x10];
1581
1582	u8         reserved_2[0x1a];
1583	u8         num_app_prio[0x6];
1584
1585	u8         reserved_3[0x40];
1586
1587	struct mlx5_ifc_application_prio_entry_bits app_prio[0];
1588};
1589
1590struct mlx5_ifc_dcbx_param_reg_bits {
1591	u8         dcbx_cee_cap[0x1];
1592	u8         dcbx_ieee_cap[0x1];
1593	u8         dcbx_standby_cap[0x1];
1594	u8         reserved_0[0x5];
1595	u8         port_number[0x8];
1596	u8         reserved_1[0xa];
1597	u8         max_application_table_size[0x6];
1598
1599	u8         reserved_2[0x15];
1600	u8         version_oper[0x3];
1601	u8         reserved_3[0x5];
1602	u8         version_admin[0x3];
1603
1604	u8         willing_admin[0x1];
1605	u8         reserved_4[0x3];
1606	u8         pfc_cap_oper[0x4];
1607	u8         reserved_5[0x4];
1608	u8         pfc_cap_admin[0x4];
1609	u8         reserved_6[0x4];
1610	u8         num_of_tc_oper[0x4];
1611	u8         reserved_7[0x4];
1612	u8         num_of_tc_admin[0x4];
1613
1614	u8         remote_willing[0x1];
1615	u8         reserved_8[0x3];
1616	u8         remote_pfc_cap[0x4];
1617	u8         reserved_9[0x14];
1618	u8         remote_num_of_tc[0x4];
1619
1620	u8         reserved_10[0x18];
1621	u8         error[0x8];
1622
1623	u8         reserved_11[0x160];
1624};
1625
1626struct mlx5_ifc_qhll_bits {
1627	u8         reserved_at_0[0x8];
1628	u8         local_port[0x8];
1629	u8         reserved_at_10[0x10];
1630
1631	u8         reserved_at_20[0x1b];
1632	u8         hll_time[0x5];
1633
1634	u8         stall_en[0x1];
1635	u8         reserved_at_41[0x1c];
1636	u8         stall_cnt[0x3];
1637};
1638
1639struct mlx5_ifc_qetcr_reg_bits {
1640	u8         operation_type[0x2];
1641	u8         cap_local_admin[0x1];
1642	u8         cap_remote_admin[0x1];
1643	u8         reserved_0[0x4];
1644	u8         port_number[0x8];
1645	u8         reserved_1[0x10];
1646
1647	u8         reserved_2[0x20];
1648
1649	u8         tc[8][0x40];
1650
1651	u8         global_configuration[0x40];
1652};
1653
1654struct mlx5_ifc_nodnic_ring_config_reg_bits {
1655	u8         queue_address_63_32[0x20];
1656
1657	u8         queue_address_31_12[0x14];
1658	u8         reserved_0[0x6];
1659	u8         log_size[0x6];
1660
1661	struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell;
1662
1663	u8         reserved_1[0x8];
1664	u8         queue_number[0x18];
1665
1666	u8         q_key[0x20];
1667
1668	u8         reserved_2[0x10];
1669	u8         pkey_index[0x10];
1670
1671	u8         reserved_3[0x40];
1672};
1673
1674struct mlx5_ifc_nodnic_cq_arming_word_bits {
1675	u8         reserved_0[0x8];
1676	u8         cq_ci[0x10];
1677	u8         reserved_1[0x8];
1678};
1679
1680enum {
1681	MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND  = 0x0,
1682	MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET    = 0x1,
1683};
1684
1685enum {
1686	MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN        = 0x0,
1687	MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE  = 0x1,
1688	MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED       = 0x2,
1689	MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE      = 0x3,
1690};
1691
1692struct mlx5_ifc_nodnic_event_word_bits {
1693	u8         driver_reset_needed[0x1];
1694	u8         port_management_change_event[0x1];
1695	u8         reserved_0[0x19];
1696	u8         link_type[0x1];
1697	u8         port_state[0x4];
1698};
1699
1700struct mlx5_ifc_nic_vport_change_event_bits {
1701	u8         reserved_0[0x10];
1702	u8         vport_num[0x10];
1703
1704	u8         reserved_1[0xc0];
1705};
1706
1707struct mlx5_ifc_pages_req_event_bits {
1708	u8         reserved_0[0x10];
1709	u8         function_id[0x10];
1710
1711	u8         num_pages[0x20];
1712
1713	u8         reserved_1[0xa0];
1714};
1715
1716struct mlx5_ifc_cmd_inter_comp_event_bits {
1717	u8         command_completion_vector[0x20];
1718
1719	u8         reserved_0[0xc0];
1720};
1721
1722struct mlx5_ifc_stall_vl_event_bits {
1723	u8         reserved_0[0x18];
1724	u8         port_num[0x1];
1725	u8         reserved_1[0x3];
1726	u8         vl[0x4];
1727
1728	u8         reserved_2[0xa0];
1729};
1730
1731struct mlx5_ifc_db_bf_congestion_event_bits {
1732	u8         event_subtype[0x8];
1733	u8         reserved_0[0x8];
1734	u8         congestion_level[0x8];
1735	u8         reserved_1[0x8];
1736
1737	u8         reserved_2[0xa0];
1738};
1739
1740struct mlx5_ifc_gpio_event_bits {
1741	u8         reserved_0[0x60];
1742
1743	u8         gpio_event_hi[0x20];
1744
1745	u8         gpio_event_lo[0x20];
1746
1747	u8         reserved_1[0x40];
1748};
1749
1750struct mlx5_ifc_port_state_change_event_bits {
1751	u8         reserved_0[0x40];
1752
1753	u8         port_num[0x4];
1754	u8         reserved_1[0x1c];
1755
1756	u8         reserved_2[0x80];
1757};
1758
1759struct mlx5_ifc_dropped_packet_logged_bits {
1760	u8         reserved_0[0xe0];
1761};
1762
1763enum {
1764	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1765	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1766};
1767
1768struct mlx5_ifc_cq_error_bits {
1769	u8         reserved_0[0x8];
1770	u8         cqn[0x18];
1771
1772	u8         reserved_1[0x20];
1773
1774	u8         reserved_2[0x18];
1775	u8         syndrome[0x8];
1776
1777	u8         reserved_3[0x80];
1778};
1779
1780struct mlx5_ifc_rdma_page_fault_event_bits {
1781	u8         bytes_commited[0x20];
1782
1783	u8         r_key[0x20];
1784
1785	u8         reserved_0[0x10];
1786	u8         packet_len[0x10];
1787
1788	u8         rdma_op_len[0x20];
1789
1790	u8         rdma_va[0x40];
1791
1792	u8         reserved_1[0x5];
1793	u8         rdma[0x1];
1794	u8         write[0x1];
1795	u8         requestor[0x1];
1796	u8         qp_number[0x18];
1797};
1798
1799struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1800	u8         bytes_committed[0x20];
1801
1802	u8         reserved_0[0x10];
1803	u8         wqe_index[0x10];
1804
1805	u8         reserved_1[0x10];
1806	u8         len[0x10];
1807
1808	u8         reserved_2[0x60];
1809
1810	u8         reserved_3[0x5];
1811	u8         rdma[0x1];
1812	u8         write_read[0x1];
1813	u8         requestor[0x1];
1814	u8         qpn[0x18];
1815};
1816
1817enum {
1818	MLX5_QP_EVENTS_TYPE_QP  = 0x0,
1819	MLX5_QP_EVENTS_TYPE_RQ  = 0x1,
1820	MLX5_QP_EVENTS_TYPE_SQ  = 0x2,
1821};
1822
1823struct mlx5_ifc_qp_events_bits {
1824	u8         reserved_0[0xa0];
1825
1826	u8         type[0x8];
1827	u8         reserved_1[0x18];
1828
1829	u8         reserved_2[0x8];
1830	u8         qpn_rqn_sqn[0x18];
1831};
1832
1833struct mlx5_ifc_dct_events_bits {
1834	u8         reserved_0[0xc0];
1835
1836	u8         reserved_1[0x8];
1837	u8         dct_number[0x18];
1838};
1839
1840struct mlx5_ifc_comp_event_bits {
1841	u8         reserved_0[0xc0];
1842
1843	u8         reserved_1[0x8];
1844	u8         cq_number[0x18];
1845};
1846
1847struct mlx5_ifc_fw_version_bits {
1848	u8         major[0x10];
1849	u8         reserved_0[0x10];
1850
1851	u8         minor[0x10];
1852	u8         subminor[0x10];
1853
1854	u8         second[0x8];
1855	u8         minute[0x8];
1856	u8         hour[0x8];
1857	u8         reserved_1[0x8];
1858
1859	u8         year[0x10];
1860	u8         month[0x8];
1861	u8         day[0x8];
1862};
1863
1864enum {
1865	MLX5_QPC_STATE_RST        = 0x0,
1866	MLX5_QPC_STATE_INIT       = 0x1,
1867	MLX5_QPC_STATE_RTR        = 0x2,
1868	MLX5_QPC_STATE_RTS        = 0x3,
1869	MLX5_QPC_STATE_SQER       = 0x4,
1870	MLX5_QPC_STATE_SQD        = 0x5,
1871	MLX5_QPC_STATE_ERR        = 0x6,
1872	MLX5_QPC_STATE_SUSPENDED  = 0x9,
1873};
1874
1875enum {
1876	MLX5_QPC_ST_RC            = 0x0,
1877	MLX5_QPC_ST_UC            = 0x1,
1878	MLX5_QPC_ST_UD            = 0x2,
1879	MLX5_QPC_ST_XRC           = 0x3,
1880	MLX5_QPC_ST_DCI           = 0x5,
1881	MLX5_QPC_ST_QP0           = 0x7,
1882	MLX5_QPC_ST_QP1           = 0x8,
1883	MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1884	MLX5_QPC_ST_REG_UMR       = 0xc,
1885};
1886
1887enum {
1888	MLX5_QP_PM_ARMED            = 0x0,
1889	MLX5_QP_PM_REARM            = 0x1,
1890	MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1891	MLX5_QP_PM_MIGRATED         = 0x3,
1892};
1893
1894enum {
1895	MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1896	MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1897};
1898
1899enum {
1900	MLX5_QPC_MTU_256_BYTES        = 0x1,
1901	MLX5_QPC_MTU_512_BYTES        = 0x2,
1902	MLX5_QPC_MTU_1K_BYTES         = 0x3,
1903	MLX5_QPC_MTU_2K_BYTES         = 0x4,
1904	MLX5_QPC_MTU_4K_BYTES         = 0x5,
1905	MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1906};
1907
1908enum {
1909	MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1910	MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1911	MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1912	MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1913	MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1914	MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1915	MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1916	MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1917};
1918
1919enum {
1920	MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1921	MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1922	MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1923};
1924
1925enum {
1926	MLX5_QPC_CS_RES_DISABLE    = 0x0,
1927	MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1928	MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1929};
1930
1931struct mlx5_ifc_qpc_bits {
1932	u8         state[0x4];
1933	u8         lag_tx_port_affinity[0x4];
1934	u8         st[0x8];
1935	u8         reserved_1[0x3];
1936	u8         pm_state[0x2];
1937	u8         reserved_2[0x7];
1938	u8         end_padding_mode[0x2];
1939	u8         reserved_3[0x2];
1940
1941	u8         wq_signature[0x1];
1942	u8         block_lb_mc[0x1];
1943	u8         atomic_like_write_en[0x1];
1944	u8         latency_sensitive[0x1];
1945	u8         reserved_4[0x1];
1946	u8         drain_sigerr[0x1];
1947	u8         reserved_5[0x2];
1948	u8         pd[0x18];
1949
1950	u8         mtu[0x3];
1951	u8         log_msg_max[0x5];
1952	u8         reserved_6[0x1];
1953	u8         log_rq_size[0x4];
1954	u8         log_rq_stride[0x3];
1955	u8         no_sq[0x1];
1956	u8         log_sq_size[0x4];
1957	u8         reserved_7[0x6];
1958	u8         rlky[0x1];
1959	u8         ulp_stateless_offload_mode[0x4];
1960
1961	u8         counter_set_id[0x8];
1962	u8         uar_page[0x18];
1963
1964	u8         reserved_8[0x8];
1965	u8         user_index[0x18];
1966
1967	u8         reserved_9[0x3];
1968	u8         log_page_size[0x5];
1969	u8         remote_qpn[0x18];
1970
1971	struct mlx5_ifc_ads_bits primary_address_path;
1972
1973	struct mlx5_ifc_ads_bits secondary_address_path;
1974
1975	u8         log_ack_req_freq[0x4];
1976	u8         reserved_10[0x4];
1977	u8         log_sra_max[0x3];
1978	u8         reserved_11[0x2];
1979	u8         retry_count[0x3];
1980	u8         rnr_retry[0x3];
1981	u8         reserved_12[0x1];
1982	u8         fre[0x1];
1983	u8         cur_rnr_retry[0x3];
1984	u8         cur_retry_count[0x3];
1985	u8         reserved_13[0x5];
1986
1987	u8         reserved_14[0x20];
1988
1989	u8         reserved_15[0x8];
1990	u8         next_send_psn[0x18];
1991
1992	u8         reserved_16[0x8];
1993	u8         cqn_snd[0x18];
1994
1995	u8         reserved_at_400[0x8];
1996
1997	u8         deth_sqpn[0x18];
1998	u8         reserved_17[0x20];
1999
2000	u8         reserved_18[0x8];
2001	u8         last_acked_psn[0x18];
2002
2003	u8         reserved_19[0x8];
2004	u8         ssn[0x18];
2005
2006	u8         reserved_20[0x8];
2007	u8         log_rra_max[0x3];
2008	u8         reserved_21[0x1];
2009	u8         atomic_mode[0x4];
2010	u8         rre[0x1];
2011	u8         rwe[0x1];
2012	u8         rae[0x1];
2013	u8         reserved_22[0x1];
2014	u8         page_offset[0x6];
2015	u8         reserved_23[0x3];
2016	u8         cd_slave_receive[0x1];
2017	u8         cd_slave_send[0x1];
2018	u8         cd_master[0x1];
2019
2020	u8         reserved_24[0x3];
2021	u8         min_rnr_nak[0x5];
2022	u8         next_rcv_psn[0x18];
2023
2024	u8         reserved_25[0x8];
2025	u8         xrcd[0x18];
2026
2027	u8         reserved_26[0x8];
2028	u8         cqn_rcv[0x18];
2029
2030	u8         dbr_addr[0x40];
2031
2032	u8         q_key[0x20];
2033
2034	u8         reserved_27[0x5];
2035	u8         rq_type[0x3];
2036	u8         srqn_rmpn[0x18];
2037
2038	u8         reserved_28[0x8];
2039	u8         rmsn[0x18];
2040
2041	u8         hw_sq_wqebb_counter[0x10];
2042	u8         sw_sq_wqebb_counter[0x10];
2043
2044	u8         hw_rq_counter[0x20];
2045
2046	u8         sw_rq_counter[0x20];
2047
2048	u8         reserved_29[0x20];
2049
2050	u8         reserved_30[0xf];
2051	u8         cgs[0x1];
2052	u8         cs_req[0x8];
2053	u8         cs_res[0x8];
2054
2055	u8         dc_access_key[0x40];
2056
2057	u8         rdma_active[0x1];
2058	u8         comm_est[0x1];
2059	u8         suspended[0x1];
2060	u8         reserved_31[0x5];
2061	u8         send_msg_psn[0x18];
2062
2063	u8         reserved_32[0x8];
2064	u8         rcv_msg_psn[0x18];
2065
2066	u8         rdma_va[0x40];
2067
2068	u8         rdma_key[0x20];
2069
2070	u8         reserved_33[0x20];
2071};
2072
2073struct mlx5_ifc_roce_addr_layout_bits {
2074	u8         source_l3_address[16][0x8];
2075
2076	u8         reserved_0[0x3];
2077	u8         vlan_valid[0x1];
2078	u8         vlan_id[0xc];
2079	u8         source_mac_47_32[0x10];
2080
2081	u8         source_mac_31_0[0x20];
2082
2083	u8         reserved_1[0x14];
2084	u8         roce_l3_type[0x4];
2085	u8         roce_version[0x8];
2086
2087	u8         reserved_2[0x20];
2088};
2089
2090struct mlx5_ifc_rdbc_bits {
2091	u8         reserved_0[0x1c];
2092	u8         type[0x4];
2093
2094	u8         reserved_1[0x20];
2095
2096	u8         reserved_2[0x8];
2097	u8         psn[0x18];
2098
2099	u8         rkey[0x20];
2100
2101	u8         address[0x40];
2102
2103	u8         byte_count[0x20];
2104
2105	u8         reserved_3[0x20];
2106
2107	u8         atomic_resp[32][0x8];
2108};
2109
2110enum {
2111	MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2112	MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2113	MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2114	MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2115};
2116
2117struct mlx5_ifc_flow_context_bits {
2118	u8         reserved_0[0x20];
2119
2120	u8         group_id[0x20];
2121
2122	u8         reserved_1[0x8];
2123	u8         flow_tag[0x18];
2124
2125	u8         reserved_2[0x10];
2126	u8         action[0x10];
2127
2128	u8         reserved_3[0x8];
2129	u8         destination_list_size[0x18];
2130
2131	u8         reserved_4[0x8];
2132	u8         flow_counter_list_size[0x18];
2133
2134	u8         reserved_5[0x140];
2135
2136	struct mlx5_ifc_fte_match_param_bits match_value;
2137
2138	u8         reserved_6[0x600];
2139
2140	union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2141};
2142
2143enum {
2144	MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2145	MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2146};
2147
2148struct mlx5_ifc_xrc_srqc_bits {
2149	u8         state[0x4];
2150	u8         log_xrc_srq_size[0x4];
2151	u8         reserved_0[0x18];
2152
2153	u8         wq_signature[0x1];
2154	u8         cont_srq[0x1];
2155	u8         reserved_1[0x1];
2156	u8         rlky[0x1];
2157	u8         basic_cyclic_rcv_wqe[0x1];
2158	u8         log_rq_stride[0x3];
2159	u8         xrcd[0x18];
2160
2161	u8         page_offset[0x6];
2162	u8         reserved_2[0x2];
2163	u8         cqn[0x18];
2164
2165	u8         reserved_3[0x20];
2166
2167	u8         reserved_4[0x2];
2168	u8         log_page_size[0x6];
2169	u8         user_index[0x18];
2170
2171	u8         reserved_5[0x20];
2172
2173	u8         reserved_6[0x8];
2174	u8         pd[0x18];
2175
2176	u8         lwm[0x10];
2177	u8         wqe_cnt[0x10];
2178
2179	u8         reserved_7[0x40];
2180
2181	u8         db_record_addr_h[0x20];
2182
2183	u8         db_record_addr_l[0x1e];
2184	u8         reserved_8[0x2];
2185
2186	u8         reserved_9[0x80];
2187};
2188
2189struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2190	u8         counter_error_queues[0x20];
2191
2192	u8         total_error_queues[0x20];
2193
2194	u8         send_queue_priority_update_flow[0x20];
2195
2196	u8         reserved_at_60[0x20];
2197
2198	u8         nic_receive_steering_discard[0x40];
2199
2200	u8         receive_discard_vport_down[0x40];
2201
2202	u8         transmit_discard_vport_down[0x40];
2203
2204	u8         reserved_at_140[0xec0];
2205};
2206
2207struct mlx5_ifc_traffic_counter_bits {
2208	u8         packets[0x40];
2209
2210	u8         octets[0x40];
2211};
2212
2213struct mlx5_ifc_tisc_bits {
2214	u8         strict_lag_tx_port_affinity[0x1];
2215	u8         reserved_at_1[0x3];
2216	u8         lag_tx_port_affinity[0x04];
2217
2218	u8         reserved_at_8[0x4];
2219	u8         prio[0x4];
2220	u8         reserved_1[0x10];
2221
2222	u8         reserved_2[0x100];
2223
2224	u8         reserved_3[0x8];
2225	u8         transport_domain[0x18];
2226
2227	u8         reserved_4[0x8];
2228	u8         underlay_qpn[0x18];
2229
2230	u8         reserved_5[0x3a0];
2231};
2232
2233enum {
2234	MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2235	MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2236};
2237
2238enum {
2239	MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2240	MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2241};
2242
2243enum {
2244	MLX5_TIRC_RX_HASH_FN_HASH_NONE           = 0x0,
2245	MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8  = 0x1,
2246	MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ       = 0x2,
2247};
2248
2249enum {
2250	MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST    = 0x1,
2251	MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST  = 0x2,
2252};
2253
2254struct mlx5_ifc_tirc_bits {
2255	u8         reserved_0[0x20];
2256
2257	u8         disp_type[0x4];
2258	u8         reserved_1[0x1c];
2259
2260	u8         reserved_2[0x40];
2261
2262	u8         reserved_3[0x4];
2263	u8         lro_timeout_period_usecs[0x10];
2264	u8         lro_enable_mask[0x4];
2265	u8         lro_max_msg_sz[0x8];
2266
2267	u8         reserved_4[0x40];
2268
2269	u8         reserved_5[0x8];
2270	u8         inline_rqn[0x18];
2271
2272	u8         rx_hash_symmetric[0x1];
2273	u8         reserved_6[0x1];
2274	u8         tunneled_offload_en[0x1];
2275	u8         reserved_7[0x5];
2276	u8         indirect_table[0x18];
2277
2278	u8         rx_hash_fn[0x4];
2279	u8         reserved_8[0x2];
2280	u8         self_lb_en[0x2];
2281	u8         transport_domain[0x18];
2282
2283	u8         rx_hash_toeplitz_key[10][0x20];
2284
2285	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2286
2287	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2288
2289	u8         reserved_9[0x4c0];
2290};
2291
2292enum {
2293	MLX5_SRQC_STATE_GOOD   = 0x0,
2294	MLX5_SRQC_STATE_ERROR  = 0x1,
2295};
2296
2297struct mlx5_ifc_srqc_bits {
2298	u8         state[0x4];
2299	u8         log_srq_size[0x4];
2300	u8         reserved_0[0x18];
2301
2302	u8         wq_signature[0x1];
2303	u8         cont_srq[0x1];
2304	u8         reserved_1[0x1];
2305	u8         rlky[0x1];
2306	u8         reserved_2[0x1];
2307	u8         log_rq_stride[0x3];
2308	u8         xrcd[0x18];
2309
2310	u8         page_offset[0x6];
2311	u8         reserved_3[0x2];
2312	u8         cqn[0x18];
2313
2314	u8         reserved_4[0x20];
2315
2316	u8         reserved_5[0x2];
2317	u8         log_page_size[0x6];
2318	u8         reserved_6[0x18];
2319
2320	u8         reserved_7[0x20];
2321
2322	u8         reserved_8[0x8];
2323	u8         pd[0x18];
2324
2325	u8         lwm[0x10];
2326	u8         wqe_cnt[0x10];
2327
2328	u8         reserved_9[0x40];
2329
2330	u8	   dbr_addr[0x40];
2331
2332	u8	   reserved_10[0x80];
2333};
2334
2335enum {
2336	MLX5_SQC_STATE_RST  = 0x0,
2337	MLX5_SQC_STATE_RDY  = 0x1,
2338	MLX5_SQC_STATE_ERR  = 0x3,
2339};
2340
2341struct mlx5_ifc_sqc_bits {
2342	u8         rlkey[0x1];
2343	u8         cd_master[0x1];
2344	u8         fre[0x1];
2345	u8         flush_in_error_en[0x1];
2346	u8         allow_multi_pkt_send_wqe[0x1];
2347	u8         min_wqe_inline_mode[0x3];
2348	u8         state[0x4];
2349	u8         reg_umr[0x1];
2350	u8         allow_swp[0x1];
2351	u8         reserved_0[0x12];
2352
2353	u8         reserved_1[0x8];
2354	u8         user_index[0x18];
2355
2356	u8         reserved_2[0x8];
2357	u8         cqn[0x18];
2358
2359	u8         reserved_3[0x80];
2360
2361	u8         qos_para_vport_number[0x10];
2362	u8         packet_pacing_rate_limit_index[0x10];
2363
2364	u8         tis_lst_sz[0x10];
2365	u8         reserved_4[0x10];
2366
2367	u8         reserved_5[0x40];
2368
2369	u8         reserved_6[0x8];
2370	u8         tis_num_0[0x18];
2371
2372	struct mlx5_ifc_wq_bits wq;
2373};
2374
2375enum {
2376	MLX5_TSAR_TYPE_DWRR = 0,
2377	MLX5_TSAR_TYPE_ROUND_ROUBIN = 1,
2378	MLX5_TSAR_TYPE_ETS = 2
2379};
2380
2381struct mlx5_ifc_tsar_element_attributes_bits {
2382	u8         reserved_0[0x8];
2383	u8         tsar_type[0x8];
2384	u8	   reserved_1[0x10];
2385};
2386
2387struct mlx5_ifc_vport_element_attributes_bits {
2388	u8         reserved_0[0x10];
2389	u8         vport_number[0x10];
2390};
2391
2392struct mlx5_ifc_vport_tc_element_attributes_bits {
2393	u8         traffic_class[0x10];
2394	u8         vport_number[0x10];
2395};
2396
2397struct mlx5_ifc_para_vport_tc_element_attributes_bits {
2398	u8         reserved_0[0x0C];
2399	u8         traffic_class[0x04];
2400	u8         qos_para_vport_number[0x10];
2401};
2402
2403enum {
2404	MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR           = 0x0,
2405	MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT          = 0x1,
2406	MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC       = 0x2,
2407	MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC  = 0x3,
2408};
2409
2410struct mlx5_ifc_scheduling_context_bits {
2411	u8         element_type[0x8];
2412	u8         reserved_at_8[0x18];
2413
2414	u8         element_attributes[0x20];
2415
2416	u8         parent_element_id[0x20];
2417
2418	u8         reserved_at_60[0x40];
2419
2420	u8         bw_share[0x20];
2421
2422	u8         max_average_bw[0x20];
2423
2424	u8         reserved_at_e0[0x120];
2425};
2426
2427struct mlx5_ifc_rqtc_bits {
2428	u8         reserved_0[0xa0];
2429
2430	u8         reserved_1[0x10];
2431	u8         rqt_max_size[0x10];
2432
2433	u8         reserved_2[0x10];
2434	u8         rqt_actual_size[0x10];
2435
2436	u8         reserved_3[0x6a0];
2437
2438	struct mlx5_ifc_rq_num_bits rq_num[0];
2439};
2440
2441enum {
2442	MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE      = 0x0,
2443	MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP         = 0x1,
2444};
2445
2446enum {
2447	MLX5_RQC_STATE_RST  = 0x0,
2448	MLX5_RQC_STATE_RDY  = 0x1,
2449	MLX5_RQC_STATE_ERR  = 0x3,
2450};
2451
2452enum {
2453	MLX5_RQC_DROPLESS_MODE_DISABLE        = 0x0,
2454	MLX5_RQC_DROPLESS_MODE_ENABLE         = 0x1,
2455};
2456
2457struct mlx5_ifc_rqc_bits {
2458	u8         rlkey[0x1];
2459	u8         delay_drop_en[0x1];
2460	u8         scatter_fcs[0x1];
2461	u8         vlan_strip_disable[0x1];
2462	u8         mem_rq_type[0x4];
2463	u8         state[0x4];
2464	u8         reserved_1[0x1];
2465	u8         flush_in_error_en[0x1];
2466	u8         reserved_2[0x12];
2467
2468	u8         reserved_3[0x8];
2469	u8         user_index[0x18];
2470
2471	u8         reserved_4[0x8];
2472	u8         cqn[0x18];
2473
2474	u8         counter_set_id[0x8];
2475	u8         reserved_5[0x18];
2476
2477	u8         reserved_6[0x8];
2478	u8         rmpn[0x18];
2479
2480	u8         reserved_7[0xe0];
2481
2482	struct mlx5_ifc_wq_bits wq;
2483};
2484
2485enum {
2486	MLX5_RMPC_STATE_RDY  = 0x1,
2487	MLX5_RMPC_STATE_ERR  = 0x3,
2488};
2489
2490struct mlx5_ifc_rmpc_bits {
2491	u8         reserved_0[0x8];
2492	u8         state[0x4];
2493	u8         reserved_1[0x14];
2494
2495	u8         basic_cyclic_rcv_wqe[0x1];
2496	u8         reserved_2[0x1f];
2497
2498	u8         reserved_3[0x140];
2499
2500	struct mlx5_ifc_wq_bits wq;
2501};
2502
2503enum {
2504	MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS  = 0x0,
2505	MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS  = 0x1,
2506	MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST               = 0x2,
2507};
2508
2509struct mlx5_ifc_nic_vport_context_bits {
2510	u8         reserved_0[0x5];
2511	u8         min_wqe_inline_mode[0x3];
2512	u8         reserved_1[0x15];
2513	u8         disable_mc_local_lb[0x1];
2514	u8         disable_uc_local_lb[0x1];
2515	u8         roce_en[0x1];
2516
2517	u8         arm_change_event[0x1];
2518	u8         reserved_2[0x1a];
2519	u8         event_on_mtu[0x1];
2520	u8         event_on_promisc_change[0x1];
2521	u8         event_on_vlan_change[0x1];
2522	u8         event_on_mc_address_change[0x1];
2523	u8         event_on_uc_address_change[0x1];
2524
2525	u8         reserved_3[0xe0];
2526
2527	u8         reserved_4[0x10];
2528	u8         mtu[0x10];
2529
2530	u8         system_image_guid[0x40];
2531
2532	u8         port_guid[0x40];
2533
2534	u8         node_guid[0x40];
2535
2536	u8         reserved_5[0x140];
2537
2538	u8         qkey_violation_counter[0x10];
2539	u8         reserved_6[0x10];
2540
2541	u8         reserved_7[0x420];
2542
2543	u8         promisc_uc[0x1];
2544	u8         promisc_mc[0x1];
2545	u8         promisc_all[0x1];
2546	u8         reserved_8[0x2];
2547	u8         allowed_list_type[0x3];
2548	u8         reserved_9[0xc];
2549	u8         allowed_list_size[0xc];
2550
2551	struct mlx5_ifc_mac_address_layout_bits permanent_address;
2552
2553	u8         reserved_10[0x20];
2554
2555	u8         current_uc_mac_address[0][0x40];
2556};
2557
2558enum {
2559	MLX5_ACCESS_MODE_PA        = 0x0,
2560	MLX5_ACCESS_MODE_MTT       = 0x1,
2561	MLX5_ACCESS_MODE_KLM       = 0x2,
2562};
2563
2564struct mlx5_ifc_mkc_bits {
2565	u8         reserved_at_0[0x1];
2566	u8         free[0x1];
2567	u8         reserved_at_2[0x1];
2568	u8         access_mode_4_2[0x3];
2569	u8         reserved_at_6[0x7];
2570	u8         relaxed_ordering_write[0x1];
2571	u8         reserved_at_e[0x1];
2572	u8         small_fence_on_rdma_read_response[0x1];
2573	u8         umr_en[0x1];
2574	u8         a[0x1];
2575	u8         rw[0x1];
2576	u8         rr[0x1];
2577	u8         lw[0x1];
2578	u8         lr[0x1];
2579	u8         access_mode[0x2];
2580	u8         reserved_2[0x8];
2581
2582	u8         qpn[0x18];
2583	u8         mkey_7_0[0x8];
2584
2585	u8         reserved_3[0x20];
2586
2587	u8         length64[0x1];
2588	u8         bsf_en[0x1];
2589	u8         sync_umr[0x1];
2590	u8         reserved_4[0x2];
2591	u8         expected_sigerr_count[0x1];
2592	u8         reserved_5[0x1];
2593	u8         en_rinval[0x1];
2594	u8         pd[0x18];
2595
2596	u8         start_addr[0x40];
2597
2598	u8         len[0x40];
2599
2600	u8         bsf_octword_size[0x20];
2601
2602	u8         reserved_6[0x80];
2603
2604	u8         translations_octword_size[0x20];
2605
2606	u8         reserved_7[0x1b];
2607	u8         log_page_size[0x5];
2608
2609	u8         reserved_8[0x20];
2610};
2611
2612struct mlx5_ifc_pkey_bits {
2613	u8         reserved_0[0x10];
2614	u8         pkey[0x10];
2615};
2616
2617struct mlx5_ifc_array128_auto_bits {
2618	u8         array128_auto[16][0x8];
2619};
2620
2621enum {
2622	MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID           = 0x0,
2623	MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID           = 0x1,
2624	MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY  = 0x2,
2625};
2626
2627enum {
2628	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP                      = 0x1,
2629	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING                    = 0x2,
2630	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED                   = 0x3,
2631	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING  = 0x4,
2632	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP                     = 0x5,
2633	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY          = 0x6,
2634	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST                    = 0x7,
2635};
2636
2637enum {
2638	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN    = 0x0,
2639	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP      = 0x1,
2640	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW  = 0x2,
2641};
2642
2643enum {
2644	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN    = 0x1,
2645	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT    = 0x2,
2646	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM     = 0x3,
2647	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE  = 0x4,
2648};
2649
2650enum {
2651	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN    = 0x1,
2652	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT    = 0x2,
2653	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM     = 0x3,
2654	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE  = 0x4,
2655};
2656
2657struct mlx5_ifc_hca_vport_context_bits {
2658	u8         field_select[0x20];
2659
2660	u8         reserved_0[0xe0];
2661
2662	u8         sm_virt_aware[0x1];
2663	u8         has_smi[0x1];
2664	u8         has_raw[0x1];
2665	u8         grh_required[0x1];
2666	u8         reserved_1[0x1];
2667	u8         min_wqe_inline_mode[0x3];
2668	u8         reserved_2[0x8];
2669	u8         port_physical_state[0x4];
2670	u8         vport_state_policy[0x4];
2671	u8         port_state[0x4];
2672	u8         vport_state[0x4];
2673
2674	u8         reserved_3[0x20];
2675
2676	u8         system_image_guid[0x40];
2677
2678	u8         port_guid[0x40];
2679
2680	u8         node_guid[0x40];
2681
2682	u8         cap_mask1[0x20];
2683
2684	u8         cap_mask1_field_select[0x20];
2685
2686	u8         cap_mask2[0x20];
2687
2688	u8         cap_mask2_field_select[0x20];
2689
2690	u8         reserved_4[0x80];
2691
2692	u8         lid[0x10];
2693	u8         reserved_5[0x4];
2694	u8         init_type_reply[0x4];
2695	u8         lmc[0x3];
2696	u8         subnet_timeout[0x5];
2697
2698	u8         sm_lid[0x10];
2699	u8         sm_sl[0x4];
2700	u8         reserved_6[0xc];
2701
2702	u8         qkey_violation_counter[0x10];
2703	u8         pkey_violation_counter[0x10];
2704
2705	u8         reserved_7[0xca0];
2706};
2707
2708union mlx5_ifc_hca_cap_union_bits {
2709	struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2710	struct mlx5_ifc_odp_cap_bits odp_cap;
2711	struct mlx5_ifc_atomic_caps_bits atomic_caps;
2712	struct mlx5_ifc_roce_cap_bits roce_cap;
2713	struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2714	struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2715	struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2716	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2717	struct mlx5_ifc_snapshot_cap_bits snapshot_cap;
2718	struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap;
2719	struct mlx5_ifc_qos_cap_bits qos_cap;
2720	u8         reserved_0[0x8000];
2721};
2722
2723enum {
2724	MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0,
2725	MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1,
2726};
2727
2728struct mlx5_ifc_flow_table_context_bits {
2729	u8         encap_en[0x1];
2730	u8         decap_en[0x1];
2731	u8         reserved_at_2[0x2];
2732	u8         table_miss_action[0x4];
2733	u8         level[0x8];
2734	u8         reserved_at_10[0x8];
2735	u8         log_size[0x8];
2736
2737	u8         reserved_at_20[0x8];
2738	u8         table_miss_id[0x18];
2739
2740	u8         reserved_at_40[0x8];
2741	u8         lag_master_next_table_id[0x18];
2742
2743	u8         reserved_at_60[0xe0];
2744};
2745
2746struct mlx5_ifc_esw_vport_context_bits {
2747	u8         reserved_0[0x3];
2748	u8         vport_svlan_strip[0x1];
2749	u8         vport_cvlan_strip[0x1];
2750	u8         vport_svlan_insert[0x1];
2751	u8         vport_cvlan_insert[0x2];
2752	u8         reserved_1[0x18];
2753
2754	u8         reserved_2[0x20];
2755
2756	u8         svlan_cfi[0x1];
2757	u8         svlan_pcp[0x3];
2758	u8         svlan_id[0xc];
2759	u8         cvlan_cfi[0x1];
2760	u8         cvlan_pcp[0x3];
2761	u8         cvlan_id[0xc];
2762
2763	u8         reserved_3[0x7a0];
2764};
2765
2766enum {
2767	MLX5_EQC_STATUS_OK                = 0x0,
2768	MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2769};
2770
2771enum {
2772	MLX5_EQ_STATE_ARMED = 0x9,
2773	MLX5_EQ_STATE_FIRED = 0xa,
2774};
2775
2776struct mlx5_ifc_eqc_bits {
2777	u8         status[0x4];
2778	u8         reserved_0[0x9];
2779	u8         ec[0x1];
2780	u8         oi[0x1];
2781	u8         reserved_1[0x5];
2782	u8         st[0x4];
2783	u8         reserved_2[0x8];
2784
2785	u8         reserved_3[0x20];
2786
2787	u8         reserved_4[0x14];
2788	u8         page_offset[0x6];
2789	u8         reserved_5[0x6];
2790
2791	u8         reserved_6[0x3];
2792	u8         log_eq_size[0x5];
2793	u8         uar_page[0x18];
2794
2795	u8         reserved_7[0x20];
2796
2797	u8         reserved_8[0x18];
2798	u8         intr[0x8];
2799
2800	u8         reserved_9[0x3];
2801	u8         log_page_size[0x5];
2802	u8         reserved_10[0x18];
2803
2804	u8         reserved_11[0x60];
2805
2806	u8         reserved_12[0x8];
2807	u8         consumer_counter[0x18];
2808
2809	u8         reserved_13[0x8];
2810	u8         producer_counter[0x18];
2811
2812	u8         reserved_14[0x80];
2813};
2814
2815enum {
2816	MLX5_DCTC_STATE_ACTIVE    = 0x0,
2817	MLX5_DCTC_STATE_DRAINING  = 0x1,
2818	MLX5_DCTC_STATE_DRAINED   = 0x2,
2819};
2820
2821enum {
2822	MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2823	MLX5_DCTC_CS_RES_NA         = 0x1,
2824	MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2825};
2826
2827enum {
2828	MLX5_DCTC_MTU_256_BYTES  = 0x1,
2829	MLX5_DCTC_MTU_512_BYTES  = 0x2,
2830	MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2831	MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2832	MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2833};
2834
2835struct mlx5_ifc_dctc_bits {
2836	u8         reserved_0[0x4];
2837	u8         state[0x4];
2838	u8         reserved_1[0x18];
2839
2840	u8         reserved_2[0x8];
2841	u8         user_index[0x18];
2842
2843	u8         reserved_3[0x8];
2844	u8         cqn[0x18];
2845
2846	u8         counter_set_id[0x8];
2847	u8         atomic_mode[0x4];
2848	u8         rre[0x1];
2849	u8         rwe[0x1];
2850	u8         rae[0x1];
2851	u8         atomic_like_write_en[0x1];
2852	u8         latency_sensitive[0x1];
2853	u8         rlky[0x1];
2854	u8         reserved_4[0xe];
2855
2856	u8         reserved_5[0x8];
2857	u8         cs_res[0x8];
2858	u8         reserved_6[0x3];
2859	u8         min_rnr_nak[0x5];
2860	u8         reserved_7[0x8];
2861
2862	u8         reserved_8[0x8];
2863	u8         srqn[0x18];
2864
2865	u8         reserved_9[0x8];
2866	u8         pd[0x18];
2867
2868	u8         tclass[0x8];
2869	u8         reserved_10[0x4];
2870	u8         flow_label[0x14];
2871
2872	u8         dc_access_key[0x40];
2873
2874	u8         reserved_11[0x5];
2875	u8         mtu[0x3];
2876	u8         port[0x8];
2877	u8         pkey_index[0x10];
2878
2879	u8         reserved_12[0x8];
2880	u8         my_addr_index[0x8];
2881	u8         reserved_13[0x8];
2882	u8         hop_limit[0x8];
2883
2884	u8         dc_access_key_violation_count[0x20];
2885
2886	u8         reserved_14[0x14];
2887	u8         dei_cfi[0x1];
2888	u8         eth_prio[0x3];
2889	u8         ecn[0x2];
2890	u8         dscp[0x6];
2891
2892	u8         reserved_15[0x40];
2893};
2894
2895enum {
2896	MLX5_CQC_STATUS_OK             = 0x0,
2897	MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2898	MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2899};
2900
2901enum {
2902	CQE_SIZE_64                = 0x0,
2903	CQE_SIZE_128               = 0x1,
2904};
2905
2906enum {
2907	MLX5_CQ_PERIOD_MODE_START_FROM_EQE  = 0x0,
2908	MLX5_CQ_PERIOD_MODE_START_FROM_CQE  = 0x1,
2909};
2910
2911enum {
2912	MLX5_CQ_STATE_SOLICITED_ARMED                     = 0x6,
2913	MLX5_CQ_STATE_ARMED                               = 0x9,
2914	MLX5_CQ_STATE_FIRED                               = 0xa,
2915};
2916
2917struct mlx5_ifc_cqc_bits {
2918	u8         status[0x4];
2919	u8         reserved_0[0x4];
2920	u8         cqe_sz[0x3];
2921	u8         cc[0x1];
2922	u8         reserved_1[0x1];
2923	u8         scqe_break_moderation_en[0x1];
2924	u8         oi[0x1];
2925	u8         cq_period_mode[0x2];
2926	u8         cqe_compression_en[0x1];
2927	u8         mini_cqe_res_format[0x2];
2928	u8         st[0x4];
2929	u8         reserved_2[0x8];
2930
2931	u8         reserved_3[0x20];
2932
2933	u8         reserved_4[0x14];
2934	u8         page_offset[0x6];
2935	u8         reserved_5[0x6];
2936
2937	u8         reserved_6[0x3];
2938	u8         log_cq_size[0x5];
2939	u8         uar_page[0x18];
2940
2941	u8         reserved_7[0x4];
2942	u8         cq_period[0xc];
2943	u8         cq_max_count[0x10];
2944
2945	u8         reserved_8[0x18];
2946	u8         c_eqn[0x8];
2947
2948	u8         reserved_9[0x3];
2949	u8         log_page_size[0x5];
2950	u8         reserved_10[0x18];
2951
2952	u8         reserved_11[0x20];
2953
2954	u8         reserved_12[0x8];
2955	u8         last_notified_index[0x18];
2956
2957	u8         reserved_13[0x8];
2958	u8         last_solicit_index[0x18];
2959
2960	u8         reserved_14[0x8];
2961	u8         consumer_counter[0x18];
2962
2963	u8         reserved_15[0x8];
2964	u8         producer_counter[0x18];
2965
2966	u8         reserved_16[0x40];
2967
2968	u8         dbr_addr[0x40];
2969};
2970
2971union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2972	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2973	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2974	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2975	u8         reserved_0[0x800];
2976};
2977
2978struct mlx5_ifc_query_adapter_param_block_bits {
2979	u8         reserved_0[0xc0];
2980
2981	u8         reserved_1[0x8];
2982	u8         ieee_vendor_id[0x18];
2983
2984	u8         reserved_2[0x10];
2985	u8         vsd_vendor_id[0x10];
2986
2987	u8         vsd[208][0x8];
2988
2989	u8         vsd_contd_psid[16][0x8];
2990};
2991
2992union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2993	struct mlx5_ifc_modify_field_select_bits modify_field_select;
2994	struct mlx5_ifc_resize_field_select_bits resize_field_select;
2995	u8         reserved_0[0x20];
2996};
2997
2998union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2999	struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3000	struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3001	struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3002	u8         reserved_0[0x20];
3003};
3004
3005struct mlx5_ifc_bufferx_reg_bits {
3006	u8         reserved_0[0x6];
3007	u8         lossy[0x1];
3008	u8         epsb[0x1];
3009	u8         reserved_1[0xc];
3010	u8         size[0xc];
3011
3012	u8         xoff_threshold[0x10];
3013	u8         xon_threshold[0x10];
3014};
3015
3016struct mlx5_ifc_config_item_bits {
3017	u8         valid[0x2];
3018	u8         reserved_0[0x2];
3019	u8         header_type[0x2];
3020	u8         reserved_1[0x2];
3021	u8         default_location[0x1];
3022	u8         reserved_2[0x7];
3023	u8         version[0x4];
3024	u8         reserved_3[0x3];
3025	u8         length[0x9];
3026
3027	u8         type[0x20];
3028
3029	u8         reserved_4[0x10];
3030	u8         crc16[0x10];
3031};
3032
3033struct mlx5_ifc_nodnic_port_config_reg_bits {
3034	struct mlx5_ifc_nodnic_event_word_bits event;
3035
3036	u8         network_en[0x1];
3037	u8         dma_en[0x1];
3038	u8         promisc_en[0x1];
3039	u8         promisc_multicast_en[0x1];
3040	u8         reserved_0[0x17];
3041	u8         receive_filter_en[0x5];
3042
3043	u8         reserved_1[0x10];
3044	u8         mac_47_32[0x10];
3045
3046	u8         mac_31_0[0x20];
3047
3048	u8         receive_filters_mgid_mac[64][0x8];
3049
3050	u8         gid[16][0x8];
3051
3052	u8         reserved_2[0x10];
3053	u8         lid[0x10];
3054
3055	u8         reserved_3[0xc];
3056	u8         sm_sl[0x4];
3057	u8         sm_lid[0x10];
3058
3059	u8         completion_address_63_32[0x20];
3060
3061	u8         completion_address_31_12[0x14];
3062	u8         reserved_4[0x6];
3063	u8         log_cq_size[0x6];
3064
3065	u8         working_buffer_address_63_32[0x20];
3066
3067	u8         working_buffer_address_31_12[0x14];
3068	u8         reserved_5[0xc];
3069
3070	struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq;
3071
3072	u8         pkey_index[0x10];
3073	u8         pkey[0x10];
3074
3075	struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0;
3076
3077	struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1;
3078
3079	struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0;
3080
3081	struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1;
3082
3083	u8         reserved_6[0x400];
3084};
3085
3086union mlx5_ifc_event_auto_bits {
3087	struct mlx5_ifc_comp_event_bits comp_event;
3088	struct mlx5_ifc_dct_events_bits dct_events;
3089	struct mlx5_ifc_qp_events_bits qp_events;
3090	struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3091	struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3092	struct mlx5_ifc_cq_error_bits cq_error;
3093	struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3094	struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3095	struct mlx5_ifc_gpio_event_bits gpio_event;
3096	struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3097	struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3098	struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3099	struct mlx5_ifc_pages_req_event_bits pages_req_event;
3100	struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event;
3101	u8         reserved_0[0xe0];
3102};
3103
3104struct mlx5_ifc_health_buffer_bits {
3105	u8         reserved_0[0x100];
3106
3107	u8         assert_existptr[0x20];
3108
3109	u8         assert_callra[0x20];
3110
3111	u8         reserved_1[0x40];
3112
3113	u8         fw_version[0x20];
3114
3115	u8         hw_id[0x20];
3116
3117	u8         reserved_2[0x20];
3118
3119	u8         irisc_index[0x8];
3120	u8         synd[0x8];
3121	u8         ext_synd[0x10];
3122};
3123
3124struct mlx5_ifc_register_loopback_control_bits {
3125	u8         no_lb[0x1];
3126	u8         reserved_0[0x7];
3127	u8         port[0x8];
3128	u8         reserved_1[0x10];
3129
3130	u8         reserved_2[0x60];
3131};
3132
3133struct mlx5_ifc_lrh_bits {
3134	u8	vl[4];
3135	u8	lver[4];
3136	u8	sl[4];
3137	u8	reserved2[2];
3138	u8	lnh[2];
3139	u8	dlid[16];
3140	u8	reserved5[5];
3141	u8	pkt_len[11];
3142	u8	slid[16];
3143};
3144
3145struct mlx5_ifc_icmd_set_wol_rol_out_bits {
3146	u8         reserved_0[0x40];
3147
3148	u8         reserved_1[0x10];
3149	u8         rol_mode[0x8];
3150	u8         wol_mode[0x8];
3151};
3152
3153struct mlx5_ifc_icmd_set_wol_rol_in_bits {
3154	u8         reserved_0[0x40];
3155
3156	u8         rol_mode_valid[0x1];
3157	u8         wol_mode_valid[0x1];
3158	u8         reserved_1[0xe];
3159	u8         rol_mode[0x8];
3160	u8         wol_mode[0x8];
3161
3162	u8         reserved_2[0x7a0];
3163};
3164
3165struct mlx5_ifc_icmd_set_virtual_mac_in_bits {
3166	u8         virtual_mac_en[0x1];
3167	u8         mac_aux_v[0x1];
3168	u8         reserved_0[0x1e];
3169
3170	u8         reserved_1[0x40];
3171
3172	struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3173
3174	u8         reserved_2[0x760];
3175};
3176
3177struct mlx5_ifc_icmd_query_virtual_mac_out_bits {
3178	u8         virtual_mac_en[0x1];
3179	u8         mac_aux_v[0x1];
3180	u8         reserved_0[0x1e];
3181
3182	struct mlx5_ifc_mac_address_layout_bits permanent_mac;
3183
3184	struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3185
3186	u8         reserved_1[0x760];
3187};
3188
3189struct mlx5_ifc_icmd_query_fw_info_out_bits {
3190	struct mlx5_ifc_fw_version_bits fw_version;
3191
3192	u8         reserved_0[0x10];
3193	u8         hash_signature[0x10];
3194
3195	u8         psid[16][0x8];
3196
3197	u8         reserved_1[0x6e0];
3198};
3199
3200struct mlx5_ifc_icmd_query_cap_in_bits {
3201	u8         reserved_0[0x10];
3202	u8         capability_group[0x10];
3203};
3204
3205struct mlx5_ifc_icmd_query_cap_general_bits {
3206	u8         nv_access[0x1];
3207	u8         fw_info_psid[0x1];
3208	u8         reserved_0[0x1e];
3209
3210	u8         reserved_1[0x16];
3211	u8         rol_s[0x1];
3212	u8         rol_g[0x1];
3213	u8         reserved_2[0x1];
3214	u8         wol_s[0x1];
3215	u8         wol_g[0x1];
3216	u8         wol_a[0x1];
3217	u8         wol_b[0x1];
3218	u8         wol_m[0x1];
3219	u8         wol_u[0x1];
3220	u8         wol_p[0x1];
3221};
3222
3223struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits {
3224	u8         status[0x8];
3225	u8         reserved_0[0x18];
3226
3227	u8         reserved_1[0x7e0];
3228};
3229
3230struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits {
3231	u8         status[0x8];
3232	u8         reserved_0[0x18];
3233
3234	u8         reserved_1[0x7e0];
3235};
3236
3237struct mlx5_ifc_icmd_ocbb_init_in_bits {
3238	u8         address_hi[0x20];
3239
3240	u8         address_lo[0x20];
3241
3242	u8         reserved_0[0x7c0];
3243};
3244
3245struct mlx5_ifc_icmd_init_ocsd_in_bits {
3246	u8         reserved_0[0x20];
3247
3248	u8         address_hi[0x20];
3249
3250	u8         address_lo[0x20];
3251
3252	u8         reserved_1[0x7a0];
3253};
3254
3255struct mlx5_ifc_icmd_access_reg_out_bits {
3256	u8         reserved_0[0x11];
3257	u8         status[0x7];
3258	u8         reserved_1[0x8];
3259
3260	u8         register_id[0x10];
3261	u8         reserved_2[0x10];
3262
3263	u8         reserved_3[0x40];
3264
3265	u8         reserved_4[0x5];
3266	u8         len[0xb];
3267	u8         reserved_5[0x10];
3268
3269	u8         register_data[0][0x20];
3270};
3271
3272enum {
3273	MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY  = 0x1,
3274	MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE  = 0x2,
3275};
3276
3277struct mlx5_ifc_icmd_access_reg_in_bits {
3278	u8         constant_1[0x5];
3279	u8         constant_2[0xb];
3280	u8         reserved_0[0x10];
3281
3282	u8         register_id[0x10];
3283	u8         reserved_1[0x1];
3284	u8         method[0x7];
3285	u8         constant_3[0x8];
3286
3287	u8         reserved_2[0x40];
3288
3289	u8         constant_4[0x5];
3290	u8         len[0xb];
3291	u8         reserved_3[0x10];
3292
3293	u8         register_data[0][0x20];
3294};
3295
3296enum {
3297	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3298	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3299};
3300
3301struct mlx5_ifc_teardown_hca_out_bits {
3302	u8         status[0x8];
3303	u8         reserved_0[0x18];
3304
3305	u8         syndrome[0x20];
3306
3307	u8         reserved_1[0x3f];
3308
3309	u8	   state[0x1];
3310};
3311
3312enum {
3313	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3314	MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3315	MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3316};
3317
3318struct mlx5_ifc_teardown_hca_in_bits {
3319	u8         opcode[0x10];
3320	u8         reserved_0[0x10];
3321
3322	u8         reserved_1[0x10];
3323	u8         op_mod[0x10];
3324
3325	u8         reserved_2[0x10];
3326	u8         profile[0x10];
3327
3328	u8         reserved_3[0x20];
3329};
3330
3331struct mlx5_ifc_set_delay_drop_params_out_bits {
3332	u8         status[0x8];
3333	u8         reserved_at_8[0x18];
3334
3335	u8         syndrome[0x20];
3336
3337	u8         reserved_at_40[0x40];
3338};
3339
3340struct mlx5_ifc_set_delay_drop_params_in_bits {
3341	u8         opcode[0x10];
3342	u8         reserved_at_10[0x10];
3343
3344	u8         reserved_at_20[0x10];
3345	u8         op_mod[0x10];
3346
3347	u8         reserved_at_40[0x20];
3348
3349	u8         reserved_at_60[0x10];
3350	u8         delay_drop_timeout[0x10];
3351};
3352
3353struct mlx5_ifc_query_delay_drop_params_out_bits {
3354	u8         status[0x8];
3355	u8         reserved_at_8[0x18];
3356
3357	u8         syndrome[0x20];
3358
3359	u8         reserved_at_40[0x20];
3360
3361	u8         reserved_at_60[0x10];
3362	u8         delay_drop_timeout[0x10];
3363};
3364
3365struct mlx5_ifc_query_delay_drop_params_in_bits {
3366	u8         opcode[0x10];
3367	u8         reserved_at_10[0x10];
3368
3369	u8         reserved_at_20[0x10];
3370	u8         op_mod[0x10];
3371
3372	u8         reserved_at_40[0x40];
3373};
3374
3375struct mlx5_ifc_suspend_qp_out_bits {
3376	u8         status[0x8];
3377	u8         reserved_0[0x18];
3378
3379	u8         syndrome[0x20];
3380
3381	u8         reserved_1[0x40];
3382};
3383
3384struct mlx5_ifc_suspend_qp_in_bits {
3385	u8         opcode[0x10];
3386	u8         reserved_0[0x10];
3387
3388	u8         reserved_1[0x10];
3389	u8         op_mod[0x10];
3390
3391	u8         reserved_2[0x8];
3392	u8         qpn[0x18];
3393
3394	u8         reserved_3[0x20];
3395};
3396
3397struct mlx5_ifc_sqerr2rts_qp_out_bits {
3398	u8         status[0x8];
3399	u8         reserved_0[0x18];
3400
3401	u8         syndrome[0x20];
3402
3403	u8         reserved_1[0x40];
3404};
3405
3406struct mlx5_ifc_sqerr2rts_qp_in_bits {
3407	u8         opcode[0x10];
3408	u8         reserved_0[0x10];
3409
3410	u8         reserved_1[0x10];
3411	u8         op_mod[0x10];
3412
3413	u8         reserved_2[0x8];
3414	u8         qpn[0x18];
3415
3416	u8         reserved_3[0x20];
3417
3418	u8         opt_param_mask[0x20];
3419
3420	u8         reserved_4[0x20];
3421
3422	struct mlx5_ifc_qpc_bits qpc;
3423
3424	u8         reserved_5[0x80];
3425};
3426
3427struct mlx5_ifc_sqd2rts_qp_out_bits {
3428	u8         status[0x8];
3429	u8         reserved_0[0x18];
3430
3431	u8         syndrome[0x20];
3432
3433	u8         reserved_1[0x40];
3434};
3435
3436struct mlx5_ifc_sqd2rts_qp_in_bits {
3437	u8         opcode[0x10];
3438	u8         reserved_0[0x10];
3439
3440	u8         reserved_1[0x10];
3441	u8         op_mod[0x10];
3442
3443	u8         reserved_2[0x8];
3444	u8         qpn[0x18];
3445
3446	u8         reserved_3[0x20];
3447
3448	u8         opt_param_mask[0x20];
3449
3450	u8         reserved_4[0x20];
3451
3452	struct mlx5_ifc_qpc_bits qpc;
3453
3454	u8         reserved_5[0x80];
3455};
3456
3457struct mlx5_ifc_set_wol_rol_out_bits {
3458	u8         status[0x8];
3459	u8         reserved_0[0x18];
3460
3461	u8         syndrome[0x20];
3462
3463	u8         reserved_1[0x40];
3464};
3465
3466struct mlx5_ifc_set_wol_rol_in_bits {
3467	u8         opcode[0x10];
3468	u8         reserved_0[0x10];
3469
3470	u8         reserved_1[0x10];
3471	u8         op_mod[0x10];
3472
3473	u8         rol_mode_valid[0x1];
3474	u8         wol_mode_valid[0x1];
3475	u8         reserved_2[0xe];
3476	u8         rol_mode[0x8];
3477	u8         wol_mode[0x8];
3478
3479	u8         reserved_3[0x20];
3480};
3481
3482struct mlx5_ifc_set_roce_address_out_bits {
3483	u8         status[0x8];
3484	u8         reserved_0[0x18];
3485
3486	u8         syndrome[0x20];
3487
3488	u8         reserved_1[0x40];
3489};
3490
3491struct mlx5_ifc_set_roce_address_in_bits {
3492	u8         opcode[0x10];
3493	u8         reserved_0[0x10];
3494
3495	u8         reserved_1[0x10];
3496	u8         op_mod[0x10];
3497
3498	u8         roce_address_index[0x10];
3499	u8         reserved_2[0x10];
3500
3501	u8         reserved_3[0x20];
3502
3503	struct mlx5_ifc_roce_addr_layout_bits roce_address;
3504};
3505
3506struct mlx5_ifc_set_rdb_out_bits {
3507	u8         status[0x8];
3508	u8         reserved_0[0x18];
3509
3510	u8         syndrome[0x20];
3511
3512	u8         reserved_1[0x40];
3513};
3514
3515struct mlx5_ifc_set_rdb_in_bits {
3516	u8         opcode[0x10];
3517	u8         reserved_0[0x10];
3518
3519	u8         reserved_1[0x10];
3520	u8         op_mod[0x10];
3521
3522	u8         reserved_2[0x8];
3523	u8         qpn[0x18];
3524
3525	u8         reserved_3[0x18];
3526	u8         rdb_list_size[0x8];
3527
3528	struct mlx5_ifc_rdbc_bits rdb_context[0];
3529};
3530
3531struct mlx5_ifc_set_mad_demux_out_bits {
3532	u8         status[0x8];
3533	u8         reserved_0[0x18];
3534
3535	u8         syndrome[0x20];
3536
3537	u8         reserved_1[0x40];
3538};
3539
3540enum {
3541	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3542	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3543};
3544
3545struct mlx5_ifc_set_mad_demux_in_bits {
3546	u8         opcode[0x10];
3547	u8         reserved_0[0x10];
3548
3549	u8         reserved_1[0x10];
3550	u8         op_mod[0x10];
3551
3552	u8         reserved_2[0x20];
3553
3554	u8         reserved_3[0x6];
3555	u8         demux_mode[0x2];
3556	u8         reserved_4[0x18];
3557};
3558
3559struct mlx5_ifc_set_l2_table_entry_out_bits {
3560	u8         status[0x8];
3561	u8         reserved_0[0x18];
3562
3563	u8         syndrome[0x20];
3564
3565	u8         reserved_1[0x40];
3566};
3567
3568struct mlx5_ifc_set_l2_table_entry_in_bits {
3569	u8         opcode[0x10];
3570	u8         reserved_0[0x10];
3571
3572	u8         reserved_1[0x10];
3573	u8         op_mod[0x10];
3574
3575	u8         reserved_2[0x60];
3576
3577	u8         reserved_3[0x8];
3578	u8         table_index[0x18];
3579
3580	u8         reserved_4[0x20];
3581
3582	u8         reserved_5[0x13];
3583	u8         vlan_valid[0x1];
3584	u8         vlan[0xc];
3585
3586	struct mlx5_ifc_mac_address_layout_bits mac_address;
3587
3588	u8         reserved_6[0xc0];
3589};
3590
3591struct mlx5_ifc_set_issi_out_bits {
3592	u8         status[0x8];
3593	u8         reserved_0[0x18];
3594
3595	u8         syndrome[0x20];
3596
3597	u8         reserved_1[0x40];
3598};
3599
3600struct mlx5_ifc_set_issi_in_bits {
3601	u8         opcode[0x10];
3602	u8         reserved_0[0x10];
3603
3604	u8         reserved_1[0x10];
3605	u8         op_mod[0x10];
3606
3607	u8         reserved_2[0x10];
3608	u8         current_issi[0x10];
3609
3610	u8         reserved_3[0x20];
3611};
3612
3613struct mlx5_ifc_set_hca_cap_out_bits {
3614	u8         status[0x8];
3615	u8         reserved_0[0x18];
3616
3617	u8         syndrome[0x20];
3618
3619	u8         reserved_1[0x40];
3620};
3621
3622struct mlx5_ifc_set_hca_cap_in_bits {
3623	u8         opcode[0x10];
3624	u8         reserved_0[0x10];
3625
3626	u8         reserved_1[0x10];
3627	u8         op_mod[0x10];
3628
3629	u8         reserved_2[0x40];
3630
3631	union mlx5_ifc_hca_cap_union_bits capability;
3632};
3633
3634enum {
3635	MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION			= 0x0,
3636	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG		= 0x1,
3637	MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST	= 0x2,
3638	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS		= 0x3
3639};
3640
3641struct mlx5_ifc_set_flow_table_root_out_bits {
3642	u8         status[0x8];
3643	u8         reserved_0[0x18];
3644
3645	u8         syndrome[0x20];
3646
3647	u8         reserved_1[0x40];
3648};
3649
3650struct mlx5_ifc_set_flow_table_root_in_bits {
3651	u8         opcode[0x10];
3652	u8         reserved_0[0x10];
3653
3654	u8         reserved_1[0x10];
3655	u8         op_mod[0x10];
3656
3657	u8         other_vport[0x1];
3658	u8         reserved_2[0xf];
3659	u8         vport_number[0x10];
3660
3661	u8         reserved_3[0x20];
3662
3663	u8         table_type[0x8];
3664	u8         reserved_4[0x18];
3665
3666	u8         reserved_5[0x8];
3667	u8         table_id[0x18];
3668
3669	u8         reserved_6[0x8];
3670	u8         underlay_qpn[0x18];
3671
3672	u8         reserved_7[0x120];
3673};
3674
3675struct mlx5_ifc_set_fte_out_bits {
3676	u8         status[0x8];
3677	u8         reserved_0[0x18];
3678
3679	u8         syndrome[0x20];
3680
3681	u8         reserved_1[0x40];
3682};
3683
3684struct mlx5_ifc_set_fte_in_bits {
3685	u8         opcode[0x10];
3686	u8         reserved_0[0x10];
3687
3688	u8         reserved_1[0x10];
3689	u8         op_mod[0x10];
3690
3691	u8         other_vport[0x1];
3692	u8         reserved_2[0xf];
3693	u8         vport_number[0x10];
3694
3695	u8         reserved_3[0x20];
3696
3697	u8         table_type[0x8];
3698	u8         reserved_4[0x18];
3699
3700	u8         reserved_5[0x8];
3701	u8         table_id[0x18];
3702
3703	u8         reserved_6[0x18];
3704	u8         modify_enable_mask[0x8];
3705
3706	u8         reserved_7[0x20];
3707
3708	u8         flow_index[0x20];
3709
3710	u8         reserved_8[0xe0];
3711
3712	struct mlx5_ifc_flow_context_bits flow_context;
3713};
3714
3715struct mlx5_ifc_set_driver_version_out_bits {
3716	u8         status[0x8];
3717	u8         reserved_0[0x18];
3718
3719	u8         syndrome[0x20];
3720
3721	u8         reserved_1[0x40];
3722};
3723
3724struct mlx5_ifc_set_driver_version_in_bits {
3725	u8         opcode[0x10];
3726	u8         reserved_0[0x10];
3727
3728	u8         reserved_1[0x10];
3729	u8         op_mod[0x10];
3730
3731	u8         reserved_2[0x40];
3732
3733	u8         driver_version[64][0x8];
3734};
3735
3736struct mlx5_ifc_set_dc_cnak_trace_out_bits {
3737	u8         status[0x8];
3738	u8         reserved_0[0x18];
3739
3740	u8         syndrome[0x20];
3741
3742	u8         reserved_1[0x40];
3743};
3744
3745struct mlx5_ifc_set_dc_cnak_trace_in_bits {
3746	u8         opcode[0x10];
3747	u8         reserved_0[0x10];
3748
3749	u8         reserved_1[0x10];
3750	u8         op_mod[0x10];
3751
3752	u8         enable[0x1];
3753	u8         reserved_2[0x1f];
3754
3755	u8         reserved_3[0x160];
3756
3757	struct mlx5_ifc_cmd_pas_bits pas;
3758};
3759
3760struct mlx5_ifc_set_burst_size_out_bits {
3761	u8         status[0x8];
3762	u8         reserved_0[0x18];
3763
3764	u8         syndrome[0x20];
3765
3766	u8         reserved_1[0x40];
3767};
3768
3769struct mlx5_ifc_set_burst_size_in_bits {
3770	u8         opcode[0x10];
3771	u8         reserved_0[0x10];
3772
3773	u8         reserved_1[0x10];
3774	u8         op_mod[0x10];
3775
3776	u8         reserved_2[0x20];
3777
3778	u8         reserved_3[0x9];
3779	u8         device_burst_size[0x17];
3780};
3781
3782struct mlx5_ifc_rts2rts_qp_out_bits {
3783	u8         status[0x8];
3784	u8         reserved_0[0x18];
3785
3786	u8         syndrome[0x20];
3787
3788	u8         reserved_1[0x40];
3789};
3790
3791struct mlx5_ifc_rts2rts_qp_in_bits {
3792	u8         opcode[0x10];
3793	u8         reserved_0[0x10];
3794
3795	u8         reserved_1[0x10];
3796	u8         op_mod[0x10];
3797
3798	u8         reserved_2[0x8];
3799	u8         qpn[0x18];
3800
3801	u8         reserved_3[0x20];
3802
3803	u8         opt_param_mask[0x20];
3804
3805	u8         reserved_4[0x20];
3806
3807	struct mlx5_ifc_qpc_bits qpc;
3808
3809	u8         reserved_5[0x80];
3810};
3811
3812struct mlx5_ifc_rtr2rts_qp_out_bits {
3813	u8         status[0x8];
3814	u8         reserved_0[0x18];
3815
3816	u8         syndrome[0x20];
3817
3818	u8         reserved_1[0x40];
3819};
3820
3821struct mlx5_ifc_rtr2rts_qp_in_bits {
3822	u8         opcode[0x10];
3823	u8         reserved_0[0x10];
3824
3825	u8         reserved_1[0x10];
3826	u8         op_mod[0x10];
3827
3828	u8         reserved_2[0x8];
3829	u8         qpn[0x18];
3830
3831	u8         reserved_3[0x20];
3832
3833	u8         opt_param_mask[0x20];
3834
3835	u8         reserved_4[0x20];
3836
3837	struct mlx5_ifc_qpc_bits qpc;
3838
3839	u8         reserved_5[0x80];
3840};
3841
3842struct mlx5_ifc_rst2init_qp_out_bits {
3843	u8         status[0x8];
3844	u8         reserved_0[0x18];
3845
3846	u8         syndrome[0x20];
3847
3848	u8         reserved_1[0x40];
3849};
3850
3851struct mlx5_ifc_rst2init_qp_in_bits {
3852	u8         opcode[0x10];
3853	u8         reserved_0[0x10];
3854
3855	u8         reserved_1[0x10];
3856	u8         op_mod[0x10];
3857
3858	u8         reserved_2[0x8];
3859	u8         qpn[0x18];
3860
3861	u8         reserved_3[0x20];
3862
3863	u8         opt_param_mask[0x20];
3864
3865	u8         reserved_4[0x20];
3866
3867	struct mlx5_ifc_qpc_bits qpc;
3868
3869	u8         reserved_5[0x80];
3870};
3871
3872struct mlx5_ifc_resume_qp_out_bits {
3873	u8         status[0x8];
3874	u8         reserved_0[0x18];
3875
3876	u8         syndrome[0x20];
3877
3878	u8         reserved_1[0x40];
3879};
3880
3881struct mlx5_ifc_resume_qp_in_bits {
3882	u8         opcode[0x10];
3883	u8         reserved_0[0x10];
3884
3885	u8         reserved_1[0x10];
3886	u8         op_mod[0x10];
3887
3888	u8         reserved_2[0x8];
3889	u8         qpn[0x18];
3890
3891	u8         reserved_3[0x20];
3892};
3893
3894struct mlx5_ifc_query_xrc_srq_out_bits {
3895	u8         status[0x8];
3896	u8         reserved_0[0x18];
3897
3898	u8         syndrome[0x20];
3899
3900	u8         reserved_1[0x40];
3901
3902	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3903
3904	u8         reserved_2[0x600];
3905
3906	u8         pas[0][0x40];
3907};
3908
3909struct mlx5_ifc_query_xrc_srq_in_bits {
3910	u8         opcode[0x10];
3911	u8         reserved_0[0x10];
3912
3913	u8         reserved_1[0x10];
3914	u8         op_mod[0x10];
3915
3916	u8         reserved_2[0x8];
3917	u8         xrc_srqn[0x18];
3918
3919	u8         reserved_3[0x20];
3920};
3921
3922struct mlx5_ifc_query_wol_rol_out_bits {
3923	u8         status[0x8];
3924	u8         reserved_0[0x18];
3925
3926	u8         syndrome[0x20];
3927
3928	u8         reserved_1[0x10];
3929	u8         rol_mode[0x8];
3930	u8         wol_mode[0x8];
3931
3932	u8         reserved_2[0x20];
3933};
3934
3935struct mlx5_ifc_query_wol_rol_in_bits {
3936	u8         opcode[0x10];
3937	u8         reserved_0[0x10];
3938
3939	u8         reserved_1[0x10];
3940	u8         op_mod[0x10];
3941
3942	u8         reserved_2[0x40];
3943};
3944
3945enum {
3946	MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3947	MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3948};
3949
3950struct mlx5_ifc_query_vport_state_out_bits {
3951	u8         status[0x8];
3952	u8         reserved_0[0x18];
3953
3954	u8         syndrome[0x20];
3955
3956	u8         reserved_1[0x20];
3957
3958	u8         reserved_2[0x18];
3959	u8         admin_state[0x4];
3960	u8         state[0x4];
3961};
3962
3963enum {
3964	MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3965	MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3966	MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK      = 0x2,
3967};
3968
3969struct mlx5_ifc_query_vport_state_in_bits {
3970	u8         opcode[0x10];
3971	u8         reserved_0[0x10];
3972
3973	u8         reserved_1[0x10];
3974	u8         op_mod[0x10];
3975
3976	u8         other_vport[0x1];
3977	u8         reserved_2[0xf];
3978	u8         vport_number[0x10];
3979
3980	u8         reserved_3[0x20];
3981};
3982
3983struct mlx5_ifc_query_vnic_env_out_bits {
3984	u8         status[0x8];
3985	u8         reserved_at_8[0x18];
3986
3987	u8         syndrome[0x20];
3988
3989	u8         reserved_at_40[0x40];
3990
3991	struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
3992};
3993
3994enum {
3995	MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
3996};
3997
3998struct mlx5_ifc_query_vnic_env_in_bits {
3999	u8         opcode[0x10];
4000	u8         reserved_at_10[0x10];
4001
4002	u8         reserved_at_20[0x10];
4003	u8         op_mod[0x10];
4004
4005	u8         other_vport[0x1];
4006	u8         reserved_at_41[0xf];
4007	u8         vport_number[0x10];
4008
4009	u8         reserved_at_60[0x20];
4010};
4011
4012struct mlx5_ifc_query_vport_counter_out_bits {
4013	u8         status[0x8];
4014	u8         reserved_0[0x18];
4015
4016	u8         syndrome[0x20];
4017
4018	u8         reserved_1[0x40];
4019
4020	struct mlx5_ifc_traffic_counter_bits received_errors;
4021
4022	struct mlx5_ifc_traffic_counter_bits transmit_errors;
4023
4024	struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4025
4026	struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4027
4028	struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4029
4030	struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4031
4032	struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4033
4034	struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4035
4036	struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4037
4038	struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4039
4040	struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4041
4042	struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4043
4044	u8         reserved_2[0xa00];
4045};
4046
4047enum {
4048	MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
4049};
4050
4051struct mlx5_ifc_query_vport_counter_in_bits {
4052	u8         opcode[0x10];
4053	u8         reserved_0[0x10];
4054
4055	u8         reserved_1[0x10];
4056	u8         op_mod[0x10];
4057
4058	u8         other_vport[0x1];
4059	u8         reserved_2[0xb];
4060	u8         port_num[0x4];
4061	u8         vport_number[0x10];
4062
4063	u8         reserved_3[0x60];
4064
4065	u8         clear[0x1];
4066	u8         reserved_4[0x1f];
4067
4068	u8         reserved_5[0x20];
4069};
4070
4071struct mlx5_ifc_query_tis_out_bits {
4072	u8         status[0x8];
4073	u8         reserved_0[0x18];
4074
4075	u8         syndrome[0x20];
4076
4077	u8         reserved_1[0x40];
4078
4079	struct mlx5_ifc_tisc_bits tis_context;
4080};
4081
4082struct mlx5_ifc_query_tis_in_bits {
4083	u8         opcode[0x10];
4084	u8         reserved_0[0x10];
4085
4086	u8         reserved_1[0x10];
4087	u8         op_mod[0x10];
4088
4089	u8         reserved_2[0x8];
4090	u8         tisn[0x18];
4091
4092	u8         reserved_3[0x20];
4093};
4094
4095struct mlx5_ifc_query_tir_out_bits {
4096	u8         status[0x8];
4097	u8         reserved_0[0x18];
4098
4099	u8         syndrome[0x20];
4100
4101	u8         reserved_1[0xc0];
4102
4103	struct mlx5_ifc_tirc_bits tir_context;
4104};
4105
4106struct mlx5_ifc_query_tir_in_bits {
4107	u8         opcode[0x10];
4108	u8         reserved_0[0x10];
4109
4110	u8         reserved_1[0x10];
4111	u8         op_mod[0x10];
4112
4113	u8         reserved_2[0x8];
4114	u8         tirn[0x18];
4115
4116	u8         reserved_3[0x20];
4117};
4118
4119struct mlx5_ifc_query_srq_out_bits {
4120	u8         status[0x8];
4121	u8         reserved_0[0x18];
4122
4123	u8         syndrome[0x20];
4124
4125	u8         reserved_1[0x40];
4126
4127	struct mlx5_ifc_srqc_bits srq_context_entry;
4128
4129	u8         reserved_2[0x600];
4130
4131	u8         pas[0][0x40];
4132};
4133
4134struct mlx5_ifc_query_srq_in_bits {
4135	u8         opcode[0x10];
4136	u8         reserved_0[0x10];
4137
4138	u8         reserved_1[0x10];
4139	u8         op_mod[0x10];
4140
4141	u8         reserved_2[0x8];
4142	u8         srqn[0x18];
4143
4144	u8         reserved_3[0x20];
4145};
4146
4147struct mlx5_ifc_query_sq_out_bits {
4148	u8         status[0x8];
4149	u8         reserved_0[0x18];
4150
4151	u8         syndrome[0x20];
4152
4153	u8         reserved_1[0xc0];
4154
4155	struct mlx5_ifc_sqc_bits sq_context;
4156};
4157
4158struct mlx5_ifc_query_sq_in_bits {
4159	u8         opcode[0x10];
4160	u8         reserved_0[0x10];
4161
4162	u8         reserved_1[0x10];
4163	u8         op_mod[0x10];
4164
4165	u8         reserved_2[0x8];
4166	u8         sqn[0x18];
4167
4168	u8         reserved_3[0x20];
4169};
4170
4171struct mlx5_ifc_query_special_contexts_out_bits {
4172	u8         status[0x8];
4173	u8         reserved_0[0x18];
4174
4175	u8         syndrome[0x20];
4176
4177	u8	   dump_fill_mkey[0x20];
4178
4179	u8         resd_lkey[0x20];
4180};
4181
4182struct mlx5_ifc_query_special_contexts_in_bits {
4183	u8         opcode[0x10];
4184	u8         reserved_0[0x10];
4185
4186	u8         reserved_1[0x10];
4187	u8         op_mod[0x10];
4188
4189	u8         reserved_2[0x40];
4190};
4191
4192struct mlx5_ifc_query_scheduling_element_out_bits {
4193	u8         status[0x8];
4194	u8         reserved_at_8[0x18];
4195
4196	u8         syndrome[0x20];
4197
4198	u8         reserved_at_40[0xc0];
4199
4200	struct mlx5_ifc_scheduling_context_bits scheduling_context;
4201
4202	u8         reserved_at_300[0x100];
4203};
4204
4205enum {
4206	MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2,
4207};
4208
4209struct mlx5_ifc_query_scheduling_element_in_bits {
4210	u8         opcode[0x10];
4211	u8         reserved_at_10[0x10];
4212
4213	u8         reserved_at_20[0x10];
4214	u8         op_mod[0x10];
4215
4216	u8         scheduling_hierarchy[0x8];
4217	u8         reserved_at_48[0x18];
4218
4219	u8         scheduling_element_id[0x20];
4220
4221	u8         reserved_at_80[0x180];
4222};
4223
4224struct mlx5_ifc_query_rqt_out_bits {
4225	u8         status[0x8];
4226	u8         reserved_0[0x18];
4227
4228	u8         syndrome[0x20];
4229
4230	u8         reserved_1[0xc0];
4231
4232	struct mlx5_ifc_rqtc_bits rqt_context;
4233};
4234
4235struct mlx5_ifc_query_rqt_in_bits {
4236	u8         opcode[0x10];
4237	u8         reserved_0[0x10];
4238
4239	u8         reserved_1[0x10];
4240	u8         op_mod[0x10];
4241
4242	u8         reserved_2[0x8];
4243	u8         rqtn[0x18];
4244
4245	u8         reserved_3[0x20];
4246};
4247
4248struct mlx5_ifc_query_rq_out_bits {
4249	u8         status[0x8];
4250	u8         reserved_0[0x18];
4251
4252	u8         syndrome[0x20];
4253
4254	u8         reserved_1[0xc0];
4255
4256	struct mlx5_ifc_rqc_bits rq_context;
4257};
4258
4259struct mlx5_ifc_query_rq_in_bits {
4260	u8         opcode[0x10];
4261	u8         reserved_0[0x10];
4262
4263	u8         reserved_1[0x10];
4264	u8         op_mod[0x10];
4265
4266	u8         reserved_2[0x8];
4267	u8         rqn[0x18];
4268
4269	u8         reserved_3[0x20];
4270};
4271
4272struct mlx5_ifc_query_roce_address_out_bits {
4273	u8         status[0x8];
4274	u8         reserved_0[0x18];
4275
4276	u8         syndrome[0x20];
4277
4278	u8         reserved_1[0x40];
4279
4280	struct mlx5_ifc_roce_addr_layout_bits roce_address;
4281};
4282
4283struct mlx5_ifc_query_roce_address_in_bits {
4284	u8         opcode[0x10];
4285	u8         reserved_0[0x10];
4286
4287	u8         reserved_1[0x10];
4288	u8         op_mod[0x10];
4289
4290	u8         roce_address_index[0x10];
4291	u8         reserved_2[0x10];
4292
4293	u8         reserved_3[0x20];
4294};
4295
4296struct mlx5_ifc_query_rmp_out_bits {
4297	u8         status[0x8];
4298	u8         reserved_0[0x18];
4299
4300	u8         syndrome[0x20];
4301
4302	u8         reserved_1[0xc0];
4303
4304	struct mlx5_ifc_rmpc_bits rmp_context;
4305};
4306
4307struct mlx5_ifc_query_rmp_in_bits {
4308	u8         opcode[0x10];
4309	u8         reserved_0[0x10];
4310
4311	u8         reserved_1[0x10];
4312	u8         op_mod[0x10];
4313
4314	u8         reserved_2[0x8];
4315	u8         rmpn[0x18];
4316
4317	u8         reserved_3[0x20];
4318};
4319
4320struct mlx5_ifc_query_rdb_out_bits {
4321	u8         status[0x8];
4322	u8         reserved_0[0x18];
4323
4324	u8         syndrome[0x20];
4325
4326	u8         reserved_1[0x20];
4327
4328	u8         reserved_2[0x18];
4329	u8         rdb_list_size[0x8];
4330
4331	struct mlx5_ifc_rdbc_bits rdb_context[0];
4332};
4333
4334struct mlx5_ifc_query_rdb_in_bits {
4335	u8         opcode[0x10];
4336	u8         reserved_0[0x10];
4337
4338	u8         reserved_1[0x10];
4339	u8         op_mod[0x10];
4340
4341	u8         reserved_2[0x8];
4342	u8         qpn[0x18];
4343
4344	u8         reserved_3[0x20];
4345};
4346
4347struct mlx5_ifc_query_qp_out_bits {
4348	u8         status[0x8];
4349	u8         reserved_0[0x18];
4350
4351	u8         syndrome[0x20];
4352
4353	u8         reserved_1[0x40];
4354
4355	u8         opt_param_mask[0x20];
4356
4357	u8         reserved_2[0x20];
4358
4359	struct mlx5_ifc_qpc_bits qpc;
4360
4361	u8         reserved_3[0x80];
4362
4363	u8         pas[0][0x40];
4364};
4365
4366struct mlx5_ifc_query_qp_in_bits {
4367	u8         opcode[0x10];
4368	u8         reserved_0[0x10];
4369
4370	u8         reserved_1[0x10];
4371	u8         op_mod[0x10];
4372
4373	u8         reserved_2[0x8];
4374	u8         qpn[0x18];
4375
4376	u8         reserved_3[0x20];
4377};
4378
4379struct mlx5_ifc_query_q_counter_out_bits {
4380	u8         status[0x8];
4381	u8         reserved_0[0x18];
4382
4383	u8         syndrome[0x20];
4384
4385	u8         reserved_1[0x40];
4386
4387	u8         rx_write_requests[0x20];
4388
4389	u8         reserved_2[0x20];
4390
4391	u8         rx_read_requests[0x20];
4392
4393	u8         reserved_3[0x20];
4394
4395	u8         rx_atomic_requests[0x20];
4396
4397	u8         reserved_4[0x20];
4398
4399	u8         rx_dct_connect[0x20];
4400
4401	u8         reserved_5[0x20];
4402
4403	u8         out_of_buffer[0x20];
4404
4405	u8         reserved_7[0x20];
4406
4407	u8         out_of_sequence[0x20];
4408
4409	u8         reserved_8[0x20];
4410
4411	u8         duplicate_request[0x20];
4412
4413	u8         reserved_9[0x20];
4414
4415	u8         rnr_nak_retry_err[0x20];
4416
4417	u8         reserved_10[0x20];
4418
4419	u8         packet_seq_err[0x20];
4420
4421	u8         reserved_11[0x20];
4422
4423	u8         implied_nak_seq_err[0x20];
4424
4425	u8         reserved_12[0x20];
4426
4427	u8         local_ack_timeout_err[0x20];
4428
4429	u8         reserved_13[0x20];
4430
4431	u8         resp_rnr_nak[0x20];
4432
4433	u8         reserved_14[0x20];
4434
4435	u8         req_rnr_retries_exceeded[0x20];
4436
4437	u8         reserved_15[0x460];
4438};
4439
4440struct mlx5_ifc_query_q_counter_in_bits {
4441	u8         opcode[0x10];
4442	u8         reserved_0[0x10];
4443
4444	u8         reserved_1[0x10];
4445	u8         op_mod[0x10];
4446
4447	u8         reserved_2[0x80];
4448
4449	u8         clear[0x1];
4450	u8         reserved_3[0x1f];
4451
4452	u8         reserved_4[0x18];
4453	u8         counter_set_id[0x8];
4454};
4455
4456struct mlx5_ifc_query_pages_out_bits {
4457	u8         status[0x8];
4458	u8         reserved_0[0x18];
4459
4460	u8         syndrome[0x20];
4461
4462	u8         reserved_1[0x10];
4463	u8         function_id[0x10];
4464
4465	u8         num_pages[0x20];
4466};
4467
4468enum {
4469	MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES	  = 0x1,
4470	MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES	  = 0x2,
4471	MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4472};
4473
4474struct mlx5_ifc_query_pages_in_bits {
4475	u8         opcode[0x10];
4476	u8         reserved_0[0x10];
4477
4478	u8         reserved_1[0x10];
4479	u8         op_mod[0x10];
4480
4481	u8         reserved_2[0x10];
4482	u8         function_id[0x10];
4483
4484	u8         reserved_3[0x20];
4485};
4486
4487struct mlx5_ifc_query_nic_vport_context_out_bits {
4488	u8         status[0x8];
4489	u8         reserved_0[0x18];
4490
4491	u8         syndrome[0x20];
4492
4493	u8         reserved_1[0x40];
4494
4495	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4496};
4497
4498struct mlx5_ifc_query_nic_vport_context_in_bits {
4499	u8         opcode[0x10];
4500	u8         reserved_0[0x10];
4501
4502	u8         reserved_1[0x10];
4503	u8         op_mod[0x10];
4504
4505	u8         other_vport[0x1];
4506	u8         reserved_2[0xf];
4507	u8         vport_number[0x10];
4508
4509	u8         reserved_3[0x5];
4510	u8         allowed_list_type[0x3];
4511	u8         reserved_4[0x18];
4512};
4513
4514struct mlx5_ifc_query_mkey_out_bits {
4515	u8         status[0x8];
4516	u8         reserved_0[0x18];
4517
4518	u8         syndrome[0x20];
4519
4520	u8         reserved_1[0x40];
4521
4522	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4523
4524	u8         reserved_2[0x600];
4525
4526	u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4527
4528	u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4529};
4530
4531struct mlx5_ifc_query_mkey_in_bits {
4532	u8         opcode[0x10];
4533	u8         reserved_0[0x10];
4534
4535	u8         reserved_1[0x10];
4536	u8         op_mod[0x10];
4537
4538	u8         reserved_2[0x8];
4539	u8         mkey_index[0x18];
4540
4541	u8         pg_access[0x1];
4542	u8         reserved_3[0x1f];
4543};
4544
4545struct mlx5_ifc_query_mad_demux_out_bits {
4546	u8         status[0x8];
4547	u8         reserved_0[0x18];
4548
4549	u8         syndrome[0x20];
4550
4551	u8         reserved_1[0x40];
4552
4553	u8         mad_dumux_parameters_block[0x20];
4554};
4555
4556struct mlx5_ifc_query_mad_demux_in_bits {
4557	u8         opcode[0x10];
4558	u8         reserved_0[0x10];
4559
4560	u8         reserved_1[0x10];
4561	u8         op_mod[0x10];
4562
4563	u8         reserved_2[0x40];
4564};
4565
4566struct mlx5_ifc_query_l2_table_entry_out_bits {
4567	u8         status[0x8];
4568	u8         reserved_0[0x18];
4569
4570	u8         syndrome[0x20];
4571
4572	u8         reserved_1[0xa0];
4573
4574	u8         reserved_2[0x13];
4575	u8         vlan_valid[0x1];
4576	u8         vlan[0xc];
4577
4578	struct mlx5_ifc_mac_address_layout_bits mac_address;
4579
4580	u8         reserved_3[0xc0];
4581};
4582
4583struct mlx5_ifc_query_l2_table_entry_in_bits {
4584	u8         opcode[0x10];
4585	u8         reserved_0[0x10];
4586
4587	u8         reserved_1[0x10];
4588	u8         op_mod[0x10];
4589
4590	u8         reserved_2[0x60];
4591
4592	u8         reserved_3[0x8];
4593	u8         table_index[0x18];
4594
4595	u8         reserved_4[0x140];
4596};
4597
4598struct mlx5_ifc_query_issi_out_bits {
4599	u8         status[0x8];
4600	u8         reserved_0[0x18];
4601
4602	u8         syndrome[0x20];
4603
4604	u8         reserved_1[0x10];
4605	u8         current_issi[0x10];
4606
4607	u8         reserved_2[0xa0];
4608
4609	u8         supported_issi_reserved[76][0x8];
4610	u8         supported_issi_dw0[0x20];
4611};
4612
4613struct mlx5_ifc_query_issi_in_bits {
4614	u8         opcode[0x10];
4615	u8         reserved_0[0x10];
4616
4617	u8         reserved_1[0x10];
4618	u8         op_mod[0x10];
4619
4620	u8         reserved_2[0x40];
4621};
4622
4623struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4624	u8         status[0x8];
4625	u8         reserved_0[0x18];
4626
4627	u8         syndrome[0x20];
4628
4629	u8         reserved_1[0x40];
4630
4631	struct mlx5_ifc_pkey_bits pkey[0];
4632};
4633
4634struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4635	u8         opcode[0x10];
4636	u8         reserved_0[0x10];
4637
4638	u8         reserved_1[0x10];
4639	u8         op_mod[0x10];
4640
4641	u8         other_vport[0x1];
4642	u8         reserved_2[0xb];
4643	u8         port_num[0x4];
4644	u8         vport_number[0x10];
4645
4646	u8         reserved_3[0x10];
4647	u8         pkey_index[0x10];
4648};
4649
4650struct mlx5_ifc_query_hca_vport_gid_out_bits {
4651	u8         status[0x8];
4652	u8         reserved_0[0x18];
4653
4654	u8         syndrome[0x20];
4655
4656	u8         reserved_1[0x20];
4657
4658	u8         gids_num[0x10];
4659	u8         reserved_2[0x10];
4660
4661	struct mlx5_ifc_array128_auto_bits gid[0];
4662};
4663
4664struct mlx5_ifc_query_hca_vport_gid_in_bits {
4665	u8         opcode[0x10];
4666	u8         reserved_0[0x10];
4667
4668	u8         reserved_1[0x10];
4669	u8         op_mod[0x10];
4670
4671	u8         other_vport[0x1];
4672	u8         reserved_2[0xb];
4673	u8         port_num[0x4];
4674	u8         vport_number[0x10];
4675
4676	u8         reserved_3[0x10];
4677	u8         gid_index[0x10];
4678};
4679
4680struct mlx5_ifc_query_hca_vport_context_out_bits {
4681	u8         status[0x8];
4682	u8         reserved_0[0x18];
4683
4684	u8         syndrome[0x20];
4685
4686	u8         reserved_1[0x40];
4687
4688	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4689};
4690
4691struct mlx5_ifc_query_hca_vport_context_in_bits {
4692	u8         opcode[0x10];
4693	u8         reserved_0[0x10];
4694
4695	u8         reserved_1[0x10];
4696	u8         op_mod[0x10];
4697
4698	u8         other_vport[0x1];
4699	u8         reserved_2[0xb];
4700	u8         port_num[0x4];
4701	u8         vport_number[0x10];
4702
4703	u8         reserved_3[0x20];
4704};
4705
4706struct mlx5_ifc_query_hca_cap_out_bits {
4707	u8         status[0x8];
4708	u8         reserved_0[0x18];
4709
4710	u8         syndrome[0x20];
4711
4712	u8         reserved_1[0x40];
4713
4714	union mlx5_ifc_hca_cap_union_bits capability;
4715};
4716
4717struct mlx5_ifc_query_hca_cap_in_bits {
4718	u8         opcode[0x10];
4719	u8         reserved_0[0x10];
4720
4721	u8         reserved_1[0x10];
4722	u8         op_mod[0x10];
4723
4724	u8         reserved_2[0x40];
4725};
4726
4727struct mlx5_ifc_query_flow_table_out_bits {
4728	u8         status[0x8];
4729	u8         reserved_at_8[0x18];
4730
4731	u8         syndrome[0x20];
4732
4733	u8         reserved_at_40[0x80];
4734
4735	struct mlx5_ifc_flow_table_context_bits flow_table_context;
4736};
4737
4738struct mlx5_ifc_query_flow_table_in_bits {
4739	u8         opcode[0x10];
4740	u8         reserved_0[0x10];
4741
4742	u8         reserved_1[0x10];
4743	u8         op_mod[0x10];
4744
4745	u8         other_vport[0x1];
4746	u8         reserved_2[0xf];
4747	u8         vport_number[0x10];
4748
4749	u8         reserved_3[0x20];
4750
4751	u8         table_type[0x8];
4752	u8         reserved_4[0x18];
4753
4754	u8         reserved_5[0x8];
4755	u8         table_id[0x18];
4756
4757	u8         reserved_6[0x140];
4758};
4759
4760struct mlx5_ifc_query_fte_out_bits {
4761	u8         status[0x8];
4762	u8         reserved_0[0x18];
4763
4764	u8         syndrome[0x20];
4765
4766	u8         reserved_1[0x1c0];
4767
4768	struct mlx5_ifc_flow_context_bits flow_context;
4769};
4770
4771struct mlx5_ifc_query_fte_in_bits {
4772	u8         opcode[0x10];
4773	u8         reserved_0[0x10];
4774
4775	u8         reserved_1[0x10];
4776	u8         op_mod[0x10];
4777
4778	u8         other_vport[0x1];
4779	u8         reserved_2[0xf];
4780	u8         vport_number[0x10];
4781
4782	u8         reserved_3[0x20];
4783
4784	u8         table_type[0x8];
4785	u8         reserved_4[0x18];
4786
4787	u8         reserved_5[0x8];
4788	u8         table_id[0x18];
4789
4790	u8         reserved_6[0x40];
4791
4792	u8         flow_index[0x20];
4793
4794	u8         reserved_7[0xe0];
4795};
4796
4797enum {
4798	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4799	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4800	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4801};
4802
4803struct mlx5_ifc_query_flow_group_out_bits {
4804	u8         status[0x8];
4805	u8         reserved_0[0x18];
4806
4807	u8         syndrome[0x20];
4808
4809	u8         reserved_1[0xa0];
4810
4811	u8         start_flow_index[0x20];
4812
4813	u8         reserved_2[0x20];
4814
4815	u8         end_flow_index[0x20];
4816
4817	u8         reserved_3[0xa0];
4818
4819	u8         reserved_4[0x18];
4820	u8         match_criteria_enable[0x8];
4821
4822	struct mlx5_ifc_fte_match_param_bits match_criteria;
4823
4824	u8         reserved_5[0xe00];
4825};
4826
4827struct mlx5_ifc_query_flow_group_in_bits {
4828	u8         opcode[0x10];
4829	u8         reserved_0[0x10];
4830
4831	u8         reserved_1[0x10];
4832	u8         op_mod[0x10];
4833
4834	u8         other_vport[0x1];
4835	u8         reserved_2[0xf];
4836	u8         vport_number[0x10];
4837
4838	u8         reserved_3[0x20];
4839
4840	u8         table_type[0x8];
4841	u8         reserved_4[0x18];
4842
4843	u8         reserved_5[0x8];
4844	u8         table_id[0x18];
4845
4846	u8         group_id[0x20];
4847
4848	u8         reserved_6[0x120];
4849};
4850
4851struct mlx5_ifc_query_flow_counter_out_bits {
4852	u8         status[0x8];
4853	u8         reserved_at_8[0x18];
4854
4855	u8         syndrome[0x20];
4856
4857	u8         reserved_at_40[0x40];
4858
4859	struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4860};
4861
4862struct mlx5_ifc_query_flow_counter_in_bits {
4863	u8         opcode[0x10];
4864	u8         reserved_at_10[0x10];
4865
4866	u8         reserved_at_20[0x10];
4867	u8         op_mod[0x10];
4868
4869	u8         reserved_at_40[0x80];
4870
4871	u8         clear[0x1];
4872	u8         reserved_at_c1[0xf];
4873	u8         num_of_counters[0x10];
4874
4875	u8         reserved_at_e0[0x10];
4876	u8         flow_counter_id[0x10];
4877};
4878
4879struct mlx5_ifc_query_esw_vport_context_out_bits {
4880	u8         status[0x8];
4881	u8         reserved_0[0x18];
4882
4883	u8         syndrome[0x20];
4884
4885	u8         reserved_1[0x40];
4886
4887	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4888};
4889
4890struct mlx5_ifc_query_esw_vport_context_in_bits {
4891	u8         opcode[0x10];
4892	u8         reserved_0[0x10];
4893
4894	u8         reserved_1[0x10];
4895	u8         op_mod[0x10];
4896
4897	u8         other_vport[0x1];
4898	u8         reserved_2[0xf];
4899	u8         vport_number[0x10];
4900
4901	u8         reserved_3[0x20];
4902};
4903
4904struct mlx5_ifc_query_eq_out_bits {
4905	u8         status[0x8];
4906	u8         reserved_0[0x18];
4907
4908	u8         syndrome[0x20];
4909
4910	u8         reserved_1[0x40];
4911
4912	struct mlx5_ifc_eqc_bits eq_context_entry;
4913
4914	u8         reserved_2[0x40];
4915
4916	u8         event_bitmask[0x40];
4917
4918	u8         reserved_3[0x580];
4919
4920	u8         pas[0][0x40];
4921};
4922
4923struct mlx5_ifc_query_eq_in_bits {
4924	u8         opcode[0x10];
4925	u8         reserved_0[0x10];
4926
4927	u8         reserved_1[0x10];
4928	u8         op_mod[0x10];
4929
4930	u8         reserved_2[0x18];
4931	u8         eq_number[0x8];
4932
4933	u8         reserved_3[0x20];
4934};
4935
4936struct mlx5_ifc_query_dct_out_bits {
4937	u8         status[0x8];
4938	u8         reserved_0[0x18];
4939
4940	u8         syndrome[0x20];
4941
4942	u8         reserved_1[0x40];
4943
4944	struct mlx5_ifc_dctc_bits dct_context_entry;
4945
4946	u8         reserved_2[0x180];
4947};
4948
4949struct mlx5_ifc_query_dct_in_bits {
4950	u8         opcode[0x10];
4951	u8         reserved_0[0x10];
4952
4953	u8         reserved_1[0x10];
4954	u8         op_mod[0x10];
4955
4956	u8         reserved_2[0x8];
4957	u8         dctn[0x18];
4958
4959	u8         reserved_3[0x20];
4960};
4961
4962struct mlx5_ifc_query_dc_cnak_trace_out_bits {
4963	u8         status[0x8];
4964	u8         reserved_0[0x18];
4965
4966	u8         syndrome[0x20];
4967
4968	u8         enable[0x1];
4969	u8         reserved_1[0x1f];
4970
4971	u8         reserved_2[0x160];
4972
4973	struct mlx5_ifc_cmd_pas_bits pas;
4974};
4975
4976struct mlx5_ifc_query_dc_cnak_trace_in_bits {
4977	u8         opcode[0x10];
4978	u8         reserved_0[0x10];
4979
4980	u8         reserved_1[0x10];
4981	u8         op_mod[0x10];
4982
4983	u8         reserved_2[0x40];
4984};
4985
4986struct mlx5_ifc_query_cq_out_bits {
4987	u8         status[0x8];
4988	u8         reserved_0[0x18];
4989
4990	u8         syndrome[0x20];
4991
4992	u8         reserved_1[0x40];
4993
4994	struct mlx5_ifc_cqc_bits cq_context;
4995
4996	u8         reserved_2[0x600];
4997
4998	u8         pas[0][0x40];
4999};
5000
5001struct mlx5_ifc_query_cq_in_bits {
5002	u8         opcode[0x10];
5003	u8         reserved_0[0x10];
5004
5005	u8         reserved_1[0x10];
5006	u8         op_mod[0x10];
5007
5008	u8         reserved_2[0x8];
5009	u8         cqn[0x18];
5010
5011	u8         reserved_3[0x20];
5012};
5013
5014struct mlx5_ifc_query_cong_status_out_bits {
5015	u8         status[0x8];
5016	u8         reserved_0[0x18];
5017
5018	u8         syndrome[0x20];
5019
5020	u8         reserved_1[0x20];
5021
5022	u8         enable[0x1];
5023	u8         tag_enable[0x1];
5024	u8         reserved_2[0x1e];
5025};
5026
5027struct mlx5_ifc_query_cong_status_in_bits {
5028	u8         opcode[0x10];
5029	u8         reserved_0[0x10];
5030
5031	u8         reserved_1[0x10];
5032	u8         op_mod[0x10];
5033
5034	u8         reserved_2[0x18];
5035	u8         priority[0x4];
5036	u8         cong_protocol[0x4];
5037
5038	u8         reserved_3[0x20];
5039};
5040
5041struct mlx5_ifc_query_cong_statistics_out_bits {
5042	u8         status[0x8];
5043	u8         reserved_0[0x18];
5044
5045	u8         syndrome[0x20];
5046
5047	u8         reserved_1[0x40];
5048
5049	u8         rp_cur_flows[0x20];
5050
5051	u8         sum_flows[0x20];
5052
5053	u8         rp_cnp_ignored_high[0x20];
5054
5055	u8         rp_cnp_ignored_low[0x20];
5056
5057	u8         rp_cnp_handled_high[0x20];
5058
5059	u8         rp_cnp_handled_low[0x20];
5060
5061	u8         reserved_2[0x100];
5062
5063	u8         time_stamp_high[0x20];
5064
5065	u8         time_stamp_low[0x20];
5066
5067	u8         accumulators_period[0x20];
5068
5069	u8         np_ecn_marked_roce_packets_high[0x20];
5070
5071	u8         np_ecn_marked_roce_packets_low[0x20];
5072
5073	u8         np_cnp_sent_high[0x20];
5074
5075	u8         np_cnp_sent_low[0x20];
5076
5077	u8         reserved_3[0x560];
5078};
5079
5080struct mlx5_ifc_query_cong_statistics_in_bits {
5081	u8         opcode[0x10];
5082	u8         reserved_0[0x10];
5083
5084	u8         reserved_1[0x10];
5085	u8         op_mod[0x10];
5086
5087	u8         clear[0x1];
5088	u8         reserved_2[0x1f];
5089
5090	u8         reserved_3[0x20];
5091};
5092
5093struct mlx5_ifc_query_cong_params_out_bits {
5094	u8         status[0x8];
5095	u8         reserved_0[0x18];
5096
5097	u8         syndrome[0x20];
5098
5099	u8         reserved_1[0x40];
5100
5101	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5102};
5103
5104struct mlx5_ifc_query_cong_params_in_bits {
5105	u8         opcode[0x10];
5106	u8         reserved_0[0x10];
5107
5108	u8         reserved_1[0x10];
5109	u8         op_mod[0x10];
5110
5111	u8         reserved_2[0x1c];
5112	u8         cong_protocol[0x4];
5113
5114	u8         reserved_3[0x20];
5115};
5116
5117struct mlx5_ifc_query_burst_size_out_bits {
5118	u8         status[0x8];
5119	u8         reserved_0[0x18];
5120
5121	u8         syndrome[0x20];
5122
5123	u8         reserved_1[0x20];
5124
5125	u8         reserved_2[0x9];
5126	u8         device_burst_size[0x17];
5127};
5128
5129struct mlx5_ifc_query_burst_size_in_bits {
5130	u8         opcode[0x10];
5131	u8         reserved_0[0x10];
5132
5133	u8         reserved_1[0x10];
5134	u8         op_mod[0x10];
5135
5136	u8         reserved_2[0x40];
5137};
5138
5139struct mlx5_ifc_query_adapter_out_bits {
5140	u8         status[0x8];
5141	u8         reserved_0[0x18];
5142
5143	u8         syndrome[0x20];
5144
5145	u8         reserved_1[0x40];
5146
5147	struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5148};
5149
5150struct mlx5_ifc_query_adapter_in_bits {
5151	u8         opcode[0x10];
5152	u8         reserved_0[0x10];
5153
5154	u8         reserved_1[0x10];
5155	u8         op_mod[0x10];
5156
5157	u8         reserved_2[0x40];
5158};
5159
5160struct mlx5_ifc_qp_2rst_out_bits {
5161	u8         status[0x8];
5162	u8         reserved_0[0x18];
5163
5164	u8         syndrome[0x20];
5165
5166	u8         reserved_1[0x40];
5167};
5168
5169struct mlx5_ifc_qp_2rst_in_bits {
5170	u8         opcode[0x10];
5171	u8         reserved_0[0x10];
5172
5173	u8         reserved_1[0x10];
5174	u8         op_mod[0x10];
5175
5176	u8         reserved_2[0x8];
5177	u8         qpn[0x18];
5178
5179	u8         reserved_3[0x20];
5180};
5181
5182struct mlx5_ifc_qp_2err_out_bits {
5183	u8         status[0x8];
5184	u8         reserved_0[0x18];
5185
5186	u8         syndrome[0x20];
5187
5188	u8         reserved_1[0x40];
5189};
5190
5191struct mlx5_ifc_qp_2err_in_bits {
5192	u8         opcode[0x10];
5193	u8         reserved_0[0x10];
5194
5195	u8         reserved_1[0x10];
5196	u8         op_mod[0x10];
5197
5198	u8         reserved_2[0x8];
5199	u8         qpn[0x18];
5200
5201	u8         reserved_3[0x20];
5202};
5203
5204struct mlx5_ifc_para_vport_element_bits {
5205	u8         reserved_at_0[0xc];
5206	u8         traffic_class[0x4];
5207	u8         qos_para_vport_number[0x10];
5208};
5209
5210struct mlx5_ifc_page_fault_resume_out_bits {
5211	u8         status[0x8];
5212	u8         reserved_0[0x18];
5213
5214	u8         syndrome[0x20];
5215
5216	u8         reserved_1[0x40];
5217};
5218
5219struct mlx5_ifc_page_fault_resume_in_bits {
5220	u8         opcode[0x10];
5221	u8         reserved_0[0x10];
5222
5223	u8         reserved_1[0x10];
5224	u8         op_mod[0x10];
5225
5226	u8         error[0x1];
5227	u8         reserved_2[0x4];
5228	u8         rdma[0x1];
5229	u8         read_write[0x1];
5230	u8         req_res[0x1];
5231	u8         qpn[0x18];
5232
5233	u8         reserved_3[0x20];
5234};
5235
5236struct mlx5_ifc_nop_out_bits {
5237	u8         status[0x8];
5238	u8         reserved_0[0x18];
5239
5240	u8         syndrome[0x20];
5241
5242	u8         reserved_1[0x40];
5243};
5244
5245struct mlx5_ifc_nop_in_bits {
5246	u8         opcode[0x10];
5247	u8         reserved_0[0x10];
5248
5249	u8         reserved_1[0x10];
5250	u8         op_mod[0x10];
5251
5252	u8         reserved_2[0x40];
5253};
5254
5255struct mlx5_ifc_modify_vport_state_out_bits {
5256	u8         status[0x8];
5257	u8         reserved_0[0x18];
5258
5259	u8         syndrome[0x20];
5260
5261	u8         reserved_1[0x40];
5262};
5263
5264enum {
5265	MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT  = 0x0,
5266	MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT  = 0x1,
5267	MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK     = 0x2,
5268};
5269
5270enum {
5271	MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN    = 0x0,
5272	MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP      = 0x1,
5273	MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW  = 0x2,
5274};
5275
5276struct mlx5_ifc_modify_vport_state_in_bits {
5277	u8         opcode[0x10];
5278	u8         reserved_0[0x10];
5279
5280	u8         reserved_1[0x10];
5281	u8         op_mod[0x10];
5282
5283	u8         other_vport[0x1];
5284	u8         reserved_2[0xf];
5285	u8         vport_number[0x10];
5286
5287	u8         reserved_3[0x18];
5288	u8         admin_state[0x4];
5289	u8         reserved_4[0x4];
5290};
5291
5292struct mlx5_ifc_modify_tis_out_bits {
5293	u8         status[0x8];
5294	u8         reserved_0[0x18];
5295
5296	u8         syndrome[0x20];
5297
5298	u8         reserved_1[0x40];
5299};
5300
5301struct mlx5_ifc_modify_tis_bitmask_bits {
5302	u8         reserved_at_0[0x20];
5303
5304	u8         reserved_at_20[0x1d];
5305	u8         lag_tx_port_affinity[0x1];
5306	u8         strict_lag_tx_port_affinity[0x1];
5307	u8         prio[0x1];
5308};
5309
5310struct mlx5_ifc_modify_tis_in_bits {
5311	u8         opcode[0x10];
5312	u8         reserved_0[0x10];
5313
5314	u8         reserved_1[0x10];
5315	u8         op_mod[0x10];
5316
5317	u8         reserved_2[0x8];
5318	u8         tisn[0x18];
5319
5320	u8         reserved_3[0x20];
5321
5322	struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5323
5324	u8         reserved_4[0x40];
5325
5326	struct mlx5_ifc_tisc_bits ctx;
5327};
5328
5329struct mlx5_ifc_modify_tir_out_bits {
5330	u8         status[0x8];
5331	u8         reserved_0[0x18];
5332
5333	u8         syndrome[0x20];
5334
5335	u8         reserved_1[0x40];
5336};
5337
5338enum
5339{
5340	MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0,
5341	MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER =		0x1 << 1
5342};
5343
5344struct mlx5_ifc_modify_tir_in_bits {
5345	u8         opcode[0x10];
5346	u8         reserved_0[0x10];
5347
5348	u8         reserved_1[0x10];
5349	u8         op_mod[0x10];
5350
5351	u8         reserved_2[0x8];
5352	u8         tirn[0x18];
5353
5354	u8         reserved_3[0x20];
5355
5356	u8         modify_bitmask[0x40];
5357
5358	u8         reserved_4[0x40];
5359
5360	struct mlx5_ifc_tirc_bits tir_context;
5361};
5362
5363struct mlx5_ifc_modify_sq_out_bits {
5364	u8         status[0x8];
5365	u8         reserved_0[0x18];
5366
5367	u8         syndrome[0x20];
5368
5369	u8         reserved_1[0x40];
5370};
5371
5372struct mlx5_ifc_modify_sq_in_bits {
5373	u8         opcode[0x10];
5374	u8         reserved_0[0x10];
5375
5376	u8         reserved_1[0x10];
5377	u8         op_mod[0x10];
5378
5379	u8         sq_state[0x4];
5380	u8         reserved_2[0x4];
5381	u8         sqn[0x18];
5382
5383	u8         reserved_3[0x20];
5384
5385	u8         modify_bitmask[0x40];
5386
5387	u8         reserved_4[0x40];
5388
5389	struct mlx5_ifc_sqc_bits ctx;
5390};
5391
5392struct mlx5_ifc_modify_scheduling_element_out_bits {
5393	u8         status[0x8];
5394	u8         reserved_at_8[0x18];
5395
5396	u8         syndrome[0x20];
5397
5398	u8         reserved_at_40[0x1c0];
5399};
5400
5401enum {
5402	MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
5403};
5404
5405enum {
5406	MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE        = 0x1,
5407	MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW  = 0x2,
5408};
5409
5410struct mlx5_ifc_modify_scheduling_element_in_bits {
5411	u8         opcode[0x10];
5412	u8         reserved_at_10[0x10];
5413
5414	u8         reserved_at_20[0x10];
5415	u8         op_mod[0x10];
5416
5417	u8         scheduling_hierarchy[0x8];
5418	u8         reserved_at_48[0x18];
5419
5420	u8         scheduling_element_id[0x20];
5421
5422	u8         reserved_at_80[0x20];
5423
5424	u8         modify_bitmask[0x20];
5425
5426	u8         reserved_at_c0[0x40];
5427
5428	struct mlx5_ifc_scheduling_context_bits scheduling_context;
5429
5430	u8         reserved_at_300[0x100];
5431};
5432
5433struct mlx5_ifc_modify_rqt_out_bits {
5434	u8         status[0x8];
5435	u8         reserved_0[0x18];
5436
5437	u8         syndrome[0x20];
5438
5439	u8         reserved_1[0x40];
5440};
5441
5442struct mlx5_ifc_modify_rqt_in_bits {
5443	u8         opcode[0x10];
5444	u8         reserved_0[0x10];
5445
5446	u8         reserved_1[0x10];
5447	u8         op_mod[0x10];
5448
5449	u8         reserved_2[0x8];
5450	u8         rqtn[0x18];
5451
5452	u8         reserved_3[0x20];
5453
5454	u8         modify_bitmask[0x40];
5455
5456	u8         reserved_4[0x40];
5457
5458	struct mlx5_ifc_rqtc_bits ctx;
5459};
5460
5461struct mlx5_ifc_modify_rq_out_bits {
5462	u8         status[0x8];
5463	u8         reserved_0[0x18];
5464
5465	u8         syndrome[0x20];
5466
5467	u8         reserved_1[0x40];
5468};
5469
5470enum {
5471	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5472	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
5473};
5474
5475struct mlx5_ifc_modify_rq_in_bits {
5476	u8         opcode[0x10];
5477	u8         reserved_0[0x10];
5478
5479	u8         reserved_1[0x10];
5480	u8         op_mod[0x10];
5481
5482	u8         rq_state[0x4];
5483	u8         reserved_2[0x4];
5484	u8         rqn[0x18];
5485
5486	u8         reserved_3[0x20];
5487
5488	u8         modify_bitmask[0x40];
5489
5490	u8         reserved_4[0x40];
5491
5492	struct mlx5_ifc_rqc_bits ctx;
5493};
5494
5495struct mlx5_ifc_modify_rmp_out_bits {
5496	u8         status[0x8];
5497	u8         reserved_0[0x18];
5498
5499	u8         syndrome[0x20];
5500
5501	u8         reserved_1[0x40];
5502};
5503
5504struct mlx5_ifc_rmp_bitmask_bits {
5505	u8	   reserved[0x20];
5506
5507	u8         reserved1[0x1f];
5508	u8         lwm[0x1];
5509};
5510
5511struct mlx5_ifc_modify_rmp_in_bits {
5512	u8         opcode[0x10];
5513	u8         reserved_0[0x10];
5514
5515	u8         reserved_1[0x10];
5516	u8         op_mod[0x10];
5517
5518	u8         rmp_state[0x4];
5519	u8         reserved_2[0x4];
5520	u8         rmpn[0x18];
5521
5522	u8         reserved_3[0x20];
5523
5524	struct mlx5_ifc_rmp_bitmask_bits bitmask;
5525
5526	u8         reserved_4[0x40];
5527
5528	struct mlx5_ifc_rmpc_bits ctx;
5529};
5530
5531struct mlx5_ifc_modify_nic_vport_context_out_bits {
5532	u8         status[0x8];
5533	u8         reserved_0[0x18];
5534
5535	u8         syndrome[0x20];
5536
5537	u8         reserved_1[0x40];
5538};
5539
5540struct mlx5_ifc_modify_nic_vport_field_select_bits {
5541	u8         reserved_0[0x14];
5542	u8         disable_uc_local_lb[0x1];
5543	u8         disable_mc_local_lb[0x1];
5544	u8         node_guid[0x1];
5545	u8         port_guid[0x1];
5546	u8         min_wqe_inline_mode[0x1];
5547	u8         mtu[0x1];
5548	u8         change_event[0x1];
5549	u8         promisc[0x1];
5550	u8         permanent_address[0x1];
5551	u8         addresses_list[0x1];
5552	u8         roce_en[0x1];
5553	u8         reserved_1[0x1];
5554};
5555
5556struct mlx5_ifc_modify_nic_vport_context_in_bits {
5557	u8         opcode[0x10];
5558	u8         reserved_0[0x10];
5559
5560	u8         reserved_1[0x10];
5561	u8         op_mod[0x10];
5562
5563	u8         other_vport[0x1];
5564	u8         reserved_2[0xf];
5565	u8         vport_number[0x10];
5566
5567	struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5568
5569	u8         reserved_3[0x780];
5570
5571	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5572};
5573
5574struct mlx5_ifc_modify_hca_vport_context_out_bits {
5575	u8         status[0x8];
5576	u8         reserved_0[0x18];
5577
5578	u8         syndrome[0x20];
5579
5580	u8         reserved_1[0x40];
5581};
5582
5583struct mlx5_ifc_grh_bits {
5584	u8	ip_version[4];
5585	u8	traffic_class[8];
5586	u8	flow_label[20];
5587	u8	payload_length[16];
5588	u8	next_header[8];
5589	u8	hop_limit[8];
5590	u8	sgid[128];
5591	u8	dgid[128];
5592};
5593
5594struct mlx5_ifc_bth_bits {
5595	u8	opcode[8];
5596	u8	se[1];
5597	u8	migreq[1];
5598	u8	pad_count[2];
5599	u8	tver[4];
5600	u8	p_key[16];
5601	u8	reserved8[8];
5602	u8	dest_qp[24];
5603	u8	ack_req[1];
5604	u8	reserved7[7];
5605	u8	psn[24];
5606};
5607
5608struct mlx5_ifc_aeth_bits {
5609	u8	syndrome[8];
5610	u8	msn[24];
5611};
5612
5613struct mlx5_ifc_dceth_bits {
5614	u8	reserved0[8];
5615	u8	session_id[24];
5616	u8	reserved1[8];
5617	u8	dci_dct[24];
5618};
5619
5620struct mlx5_ifc_modify_hca_vport_context_in_bits {
5621	u8         opcode[0x10];
5622	u8         reserved_0[0x10];
5623
5624	u8         reserved_1[0x10];
5625	u8         op_mod[0x10];
5626
5627	u8         other_vport[0x1];
5628	u8         reserved_2[0xb];
5629	u8         port_num[0x4];
5630	u8         vport_number[0x10];
5631
5632	u8         reserved_3[0x20];
5633
5634	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5635};
5636
5637struct mlx5_ifc_modify_flow_table_out_bits {
5638	u8         status[0x8];
5639	u8         reserved_at_8[0x18];
5640
5641	u8         syndrome[0x20];
5642
5643	u8         reserved_at_40[0x40];
5644};
5645
5646enum {
5647	MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1,
5648	MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000,
5649};
5650
5651struct mlx5_ifc_modify_flow_table_in_bits {
5652	u8         opcode[0x10];
5653	u8         reserved_at_10[0x10];
5654
5655	u8         reserved_at_20[0x10];
5656	u8         op_mod[0x10];
5657
5658	u8         other_vport[0x1];
5659	u8         reserved_at_41[0xf];
5660	u8         vport_number[0x10];
5661
5662	u8         reserved_at_60[0x10];
5663	u8         modify_field_select[0x10];
5664
5665	u8         table_type[0x8];
5666	u8         reserved_at_88[0x18];
5667
5668	u8         reserved_at_a0[0x8];
5669	u8         table_id[0x18];
5670
5671	struct mlx5_ifc_flow_table_context_bits flow_table_context;
5672};
5673
5674struct mlx5_ifc_modify_esw_vport_context_out_bits {
5675	u8         status[0x8];
5676	u8         reserved_0[0x18];
5677
5678	u8         syndrome[0x20];
5679
5680	u8         reserved_1[0x40];
5681};
5682
5683struct mlx5_ifc_esw_vport_context_fields_select_bits {
5684	u8         reserved[0x1c];
5685	u8         vport_cvlan_insert[0x1];
5686	u8         vport_svlan_insert[0x1];
5687	u8         vport_cvlan_strip[0x1];
5688	u8         vport_svlan_strip[0x1];
5689};
5690
5691struct mlx5_ifc_modify_esw_vport_context_in_bits {
5692	u8         opcode[0x10];
5693	u8         reserved_0[0x10];
5694
5695	u8         reserved_1[0x10];
5696	u8         op_mod[0x10];
5697
5698	u8         other_vport[0x1];
5699	u8         reserved_2[0xf];
5700	u8         vport_number[0x10];
5701
5702	struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5703
5704	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5705};
5706
5707struct mlx5_ifc_modify_cq_out_bits {
5708	u8         status[0x8];
5709	u8         reserved_0[0x18];
5710
5711	u8         syndrome[0x20];
5712
5713	u8         reserved_1[0x40];
5714};
5715
5716enum {
5717	MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5718	MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5719};
5720
5721struct mlx5_ifc_modify_cq_in_bits {
5722	u8         opcode[0x10];
5723	u8         reserved_0[0x10];
5724
5725	u8         reserved_1[0x10];
5726	u8         op_mod[0x10];
5727
5728	u8         reserved_2[0x8];
5729	u8         cqn[0x18];
5730
5731	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5732
5733	struct mlx5_ifc_cqc_bits cq_context;
5734
5735	u8         reserved_3[0x600];
5736
5737	u8         pas[0][0x40];
5738};
5739
5740struct mlx5_ifc_modify_cong_status_out_bits {
5741	u8         status[0x8];
5742	u8         reserved_0[0x18];
5743
5744	u8         syndrome[0x20];
5745
5746	u8         reserved_1[0x40];
5747};
5748
5749struct mlx5_ifc_modify_cong_status_in_bits {
5750	u8         opcode[0x10];
5751	u8         reserved_0[0x10];
5752
5753	u8         reserved_1[0x10];
5754	u8         op_mod[0x10];
5755
5756	u8         reserved_2[0x18];
5757	u8         priority[0x4];
5758	u8         cong_protocol[0x4];
5759
5760	u8         enable[0x1];
5761	u8         tag_enable[0x1];
5762	u8         reserved_3[0x1e];
5763};
5764
5765struct mlx5_ifc_modify_cong_params_out_bits {
5766	u8         status[0x8];
5767	u8         reserved_0[0x18];
5768
5769	u8         syndrome[0x20];
5770
5771	u8         reserved_1[0x40];
5772};
5773
5774struct mlx5_ifc_modify_cong_params_in_bits {
5775	u8         opcode[0x10];
5776	u8         reserved_0[0x10];
5777
5778	u8         reserved_1[0x10];
5779	u8         op_mod[0x10];
5780
5781	u8         reserved_2[0x1c];
5782	u8         cong_protocol[0x4];
5783
5784	union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5785
5786	u8         reserved_3[0x80];
5787
5788	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5789};
5790
5791struct mlx5_ifc_manage_pages_out_bits {
5792	u8         status[0x8];
5793	u8         reserved_0[0x18];
5794
5795	u8         syndrome[0x20];
5796
5797	u8         output_num_entries[0x20];
5798
5799	u8         reserved_1[0x20];
5800
5801	u8         pas[0][0x40];
5802};
5803
5804enum {
5805	MLX5_PAGES_CANT_GIVE                            = 0x0,
5806	MLX5_PAGES_GIVE                                 = 0x1,
5807	MLX5_PAGES_TAKE                                 = 0x2,
5808};
5809
5810struct mlx5_ifc_manage_pages_in_bits {
5811	u8         opcode[0x10];
5812	u8         reserved_0[0x10];
5813
5814	u8         reserved_1[0x10];
5815	u8         op_mod[0x10];
5816
5817	u8         reserved_2[0x10];
5818	u8         function_id[0x10];
5819
5820	u8         input_num_entries[0x20];
5821
5822	u8         pas[0][0x40];
5823};
5824
5825struct mlx5_ifc_mad_ifc_out_bits {
5826	u8         status[0x8];
5827	u8         reserved_0[0x18];
5828
5829	u8         syndrome[0x20];
5830
5831	u8         reserved_1[0x40];
5832
5833	u8         response_mad_packet[256][0x8];
5834};
5835
5836struct mlx5_ifc_mad_ifc_in_bits {
5837	u8         opcode[0x10];
5838	u8         reserved_0[0x10];
5839
5840	u8         reserved_1[0x10];
5841	u8         op_mod[0x10];
5842
5843	u8         remote_lid[0x10];
5844	u8         reserved_2[0x8];
5845	u8         port[0x8];
5846
5847	u8         reserved_3[0x20];
5848
5849	u8         mad[256][0x8];
5850};
5851
5852struct mlx5_ifc_init_hca_out_bits {
5853	u8         status[0x8];
5854	u8         reserved_0[0x18];
5855
5856	u8         syndrome[0x20];
5857
5858	u8         reserved_1[0x40];
5859};
5860
5861enum {
5862	MLX5_INIT_HCA_IN_OP_MOD_INIT      = 0x0,
5863	MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT  = 0x1,
5864};
5865
5866struct mlx5_ifc_init_hca_in_bits {
5867	u8         opcode[0x10];
5868	u8         reserved_0[0x10];
5869
5870	u8         reserved_1[0x10];
5871	u8         op_mod[0x10];
5872
5873	u8         reserved_2[0x40];
5874};
5875
5876struct mlx5_ifc_init2rtr_qp_out_bits {
5877	u8         status[0x8];
5878	u8         reserved_0[0x18];
5879
5880	u8         syndrome[0x20];
5881
5882	u8         reserved_1[0x40];
5883};
5884
5885struct mlx5_ifc_init2rtr_qp_in_bits {
5886	u8         opcode[0x10];
5887	u8         reserved_0[0x10];
5888
5889	u8         reserved_1[0x10];
5890	u8         op_mod[0x10];
5891
5892	u8         reserved_2[0x8];
5893	u8         qpn[0x18];
5894
5895	u8         reserved_3[0x20];
5896
5897	u8         opt_param_mask[0x20];
5898
5899	u8         reserved_4[0x20];
5900
5901	struct mlx5_ifc_qpc_bits qpc;
5902
5903	u8         reserved_5[0x80];
5904};
5905
5906struct mlx5_ifc_init2init_qp_out_bits {
5907	u8         status[0x8];
5908	u8         reserved_0[0x18];
5909
5910	u8         syndrome[0x20];
5911
5912	u8         reserved_1[0x40];
5913};
5914
5915struct mlx5_ifc_init2init_qp_in_bits {
5916	u8         opcode[0x10];
5917	u8         reserved_0[0x10];
5918
5919	u8         reserved_1[0x10];
5920	u8         op_mod[0x10];
5921
5922	u8         reserved_2[0x8];
5923	u8         qpn[0x18];
5924
5925	u8         reserved_3[0x20];
5926
5927	u8         opt_param_mask[0x20];
5928
5929	u8         reserved_4[0x20];
5930
5931	struct mlx5_ifc_qpc_bits qpc;
5932
5933	u8         reserved_5[0x80];
5934};
5935
5936struct mlx5_ifc_get_dropped_packet_log_out_bits {
5937	u8         status[0x8];
5938	u8         reserved_0[0x18];
5939
5940	u8         syndrome[0x20];
5941
5942	u8         reserved_1[0x40];
5943
5944	u8         packet_headers_log[128][0x8];
5945
5946	u8         packet_syndrome[64][0x8];
5947};
5948
5949struct mlx5_ifc_get_dropped_packet_log_in_bits {
5950	u8         opcode[0x10];
5951	u8         reserved_0[0x10];
5952
5953	u8         reserved_1[0x10];
5954	u8         op_mod[0x10];
5955
5956	u8         reserved_2[0x40];
5957};
5958
5959struct mlx5_ifc_gen_eqe_in_bits {
5960	u8         opcode[0x10];
5961	u8         reserved_0[0x10];
5962
5963	u8         reserved_1[0x10];
5964	u8         op_mod[0x10];
5965
5966	u8         reserved_2[0x18];
5967	u8         eq_number[0x8];
5968
5969	u8         reserved_3[0x20];
5970
5971	u8         eqe[64][0x8];
5972};
5973
5974struct mlx5_ifc_gen_eq_out_bits {
5975	u8         status[0x8];
5976	u8         reserved_0[0x18];
5977
5978	u8         syndrome[0x20];
5979
5980	u8         reserved_1[0x40];
5981};
5982
5983struct mlx5_ifc_enable_hca_out_bits {
5984	u8         status[0x8];
5985	u8         reserved_0[0x18];
5986
5987	u8         syndrome[0x20];
5988
5989	u8         reserved_1[0x20];
5990};
5991
5992struct mlx5_ifc_enable_hca_in_bits {
5993	u8         opcode[0x10];
5994	u8         reserved_0[0x10];
5995
5996	u8         reserved_1[0x10];
5997	u8         op_mod[0x10];
5998
5999	u8         reserved_2[0x10];
6000	u8         function_id[0x10];
6001
6002	u8         reserved_3[0x20];
6003};
6004
6005struct mlx5_ifc_drain_dct_out_bits {
6006	u8         status[0x8];
6007	u8         reserved_0[0x18];
6008
6009	u8         syndrome[0x20];
6010
6011	u8         reserved_1[0x40];
6012};
6013
6014struct mlx5_ifc_drain_dct_in_bits {
6015	u8         opcode[0x10];
6016	u8         reserved_0[0x10];
6017
6018	u8         reserved_1[0x10];
6019	u8         op_mod[0x10];
6020
6021	u8         reserved_2[0x8];
6022	u8         dctn[0x18];
6023
6024	u8         reserved_3[0x20];
6025};
6026
6027struct mlx5_ifc_disable_hca_out_bits {
6028	u8         status[0x8];
6029	u8         reserved_0[0x18];
6030
6031	u8         syndrome[0x20];
6032
6033	u8         reserved_1[0x20];
6034};
6035
6036struct mlx5_ifc_disable_hca_in_bits {
6037	u8         opcode[0x10];
6038	u8         reserved_0[0x10];
6039
6040	u8         reserved_1[0x10];
6041	u8         op_mod[0x10];
6042
6043	u8         reserved_2[0x10];
6044	u8         function_id[0x10];
6045
6046	u8         reserved_3[0x20];
6047};
6048
6049struct mlx5_ifc_detach_from_mcg_out_bits {
6050	u8         status[0x8];
6051	u8         reserved_0[0x18];
6052
6053	u8         syndrome[0x20];
6054
6055	u8         reserved_1[0x40];
6056};
6057
6058struct mlx5_ifc_detach_from_mcg_in_bits {
6059	u8         opcode[0x10];
6060	u8         reserved_0[0x10];
6061
6062	u8         reserved_1[0x10];
6063	u8         op_mod[0x10];
6064
6065	u8         reserved_2[0x8];
6066	u8         qpn[0x18];
6067
6068	u8         reserved_3[0x20];
6069
6070	u8         multicast_gid[16][0x8];
6071};
6072
6073struct mlx5_ifc_destroy_xrc_srq_out_bits {
6074	u8         status[0x8];
6075	u8         reserved_0[0x18];
6076
6077	u8         syndrome[0x20];
6078
6079	u8         reserved_1[0x40];
6080};
6081
6082struct mlx5_ifc_destroy_xrc_srq_in_bits {
6083	u8         opcode[0x10];
6084	u8         reserved_0[0x10];
6085
6086	u8         reserved_1[0x10];
6087	u8         op_mod[0x10];
6088
6089	u8         reserved_2[0x8];
6090	u8         xrc_srqn[0x18];
6091
6092	u8         reserved_3[0x20];
6093};
6094
6095struct mlx5_ifc_destroy_tis_out_bits {
6096	u8         status[0x8];
6097	u8         reserved_0[0x18];
6098
6099	u8         syndrome[0x20];
6100
6101	u8         reserved_1[0x40];
6102};
6103
6104struct mlx5_ifc_destroy_tis_in_bits {
6105	u8         opcode[0x10];
6106	u8         reserved_0[0x10];
6107
6108	u8         reserved_1[0x10];
6109	u8         op_mod[0x10];
6110
6111	u8         reserved_2[0x8];
6112	u8         tisn[0x18];
6113
6114	u8         reserved_3[0x20];
6115};
6116
6117struct mlx5_ifc_destroy_tir_out_bits {
6118	u8         status[0x8];
6119	u8         reserved_0[0x18];
6120
6121	u8         syndrome[0x20];
6122
6123	u8         reserved_1[0x40];
6124};
6125
6126struct mlx5_ifc_destroy_tir_in_bits {
6127	u8         opcode[0x10];
6128	u8         reserved_0[0x10];
6129
6130	u8         reserved_1[0x10];
6131	u8         op_mod[0x10];
6132
6133	u8         reserved_2[0x8];
6134	u8         tirn[0x18];
6135
6136	u8         reserved_3[0x20];
6137};
6138
6139struct mlx5_ifc_destroy_srq_out_bits {
6140	u8         status[0x8];
6141	u8         reserved_0[0x18];
6142
6143	u8         syndrome[0x20];
6144
6145	u8         reserved_1[0x40];
6146};
6147
6148struct mlx5_ifc_destroy_srq_in_bits {
6149	u8         opcode[0x10];
6150	u8         reserved_0[0x10];
6151
6152	u8         reserved_1[0x10];
6153	u8         op_mod[0x10];
6154
6155	u8         reserved_2[0x8];
6156	u8         srqn[0x18];
6157
6158	u8         reserved_3[0x20];
6159};
6160
6161struct mlx5_ifc_destroy_sq_out_bits {
6162	u8         status[0x8];
6163	u8         reserved_0[0x18];
6164
6165	u8         syndrome[0x20];
6166
6167	u8         reserved_1[0x40];
6168};
6169
6170struct mlx5_ifc_destroy_sq_in_bits {
6171	u8         opcode[0x10];
6172	u8         reserved_0[0x10];
6173
6174	u8         reserved_1[0x10];
6175	u8         op_mod[0x10];
6176
6177	u8         reserved_2[0x8];
6178	u8         sqn[0x18];
6179
6180	u8         reserved_3[0x20];
6181};
6182
6183struct mlx5_ifc_destroy_scheduling_element_out_bits {
6184	u8         status[0x8];
6185	u8         reserved_at_8[0x18];
6186
6187	u8         syndrome[0x20];
6188
6189	u8         reserved_at_40[0x1c0];
6190};
6191
6192enum {
6193	MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
6194};
6195
6196struct mlx5_ifc_destroy_scheduling_element_in_bits {
6197	u8         opcode[0x10];
6198	u8         reserved_at_10[0x10];
6199
6200	u8         reserved_at_20[0x10];
6201	u8         op_mod[0x10];
6202
6203	u8         scheduling_hierarchy[0x8];
6204	u8         reserved_at_48[0x18];
6205
6206	u8         scheduling_element_id[0x20];
6207
6208	u8         reserved_at_80[0x180];
6209};
6210
6211struct mlx5_ifc_destroy_rqt_out_bits {
6212	u8         status[0x8];
6213	u8         reserved_0[0x18];
6214
6215	u8         syndrome[0x20];
6216
6217	u8         reserved_1[0x40];
6218};
6219
6220struct mlx5_ifc_destroy_rqt_in_bits {
6221	u8         opcode[0x10];
6222	u8         reserved_0[0x10];
6223
6224	u8         reserved_1[0x10];
6225	u8         op_mod[0x10];
6226
6227	u8         reserved_2[0x8];
6228	u8         rqtn[0x18];
6229
6230	u8         reserved_3[0x20];
6231};
6232
6233struct mlx5_ifc_destroy_rq_out_bits {
6234	u8         status[0x8];
6235	u8         reserved_0[0x18];
6236
6237	u8         syndrome[0x20];
6238
6239	u8         reserved_1[0x40];
6240};
6241
6242struct mlx5_ifc_destroy_rq_in_bits {
6243	u8         opcode[0x10];
6244	u8         reserved_0[0x10];
6245
6246	u8         reserved_1[0x10];
6247	u8         op_mod[0x10];
6248
6249	u8         reserved_2[0x8];
6250	u8         rqn[0x18];
6251
6252	u8         reserved_3[0x20];
6253};
6254
6255struct mlx5_ifc_destroy_rmp_out_bits {
6256	u8         status[0x8];
6257	u8         reserved_0[0x18];
6258
6259	u8         syndrome[0x20];
6260
6261	u8         reserved_1[0x40];
6262};
6263
6264struct mlx5_ifc_destroy_rmp_in_bits {
6265	u8         opcode[0x10];
6266	u8         reserved_0[0x10];
6267
6268	u8         reserved_1[0x10];
6269	u8         op_mod[0x10];
6270
6271	u8         reserved_2[0x8];
6272	u8         rmpn[0x18];
6273
6274	u8         reserved_3[0x20];
6275};
6276
6277struct mlx5_ifc_destroy_qp_out_bits {
6278	u8         status[0x8];
6279	u8         reserved_0[0x18];
6280
6281	u8         syndrome[0x20];
6282
6283	u8         reserved_1[0x40];
6284};
6285
6286struct mlx5_ifc_destroy_qp_in_bits {
6287	u8         opcode[0x10];
6288	u8         reserved_0[0x10];
6289
6290	u8         reserved_1[0x10];
6291	u8         op_mod[0x10];
6292
6293	u8         reserved_2[0x8];
6294	u8         qpn[0x18];
6295
6296	u8         reserved_3[0x20];
6297};
6298
6299struct mlx5_ifc_destroy_qos_para_vport_out_bits {
6300	u8         status[0x8];
6301	u8         reserved_at_8[0x18];
6302
6303	u8         syndrome[0x20];
6304
6305	u8         reserved_at_40[0x1c0];
6306};
6307
6308struct mlx5_ifc_destroy_qos_para_vport_in_bits {
6309	u8         opcode[0x10];
6310	u8         reserved_at_10[0x10];
6311
6312	u8         reserved_at_20[0x10];
6313	u8         op_mod[0x10];
6314
6315	u8         reserved_at_40[0x20];
6316
6317	u8         reserved_at_60[0x10];
6318	u8         qos_para_vport_number[0x10];
6319
6320	u8         reserved_at_80[0x180];
6321};
6322
6323struct mlx5_ifc_destroy_psv_out_bits {
6324	u8         status[0x8];
6325	u8         reserved_0[0x18];
6326
6327	u8         syndrome[0x20];
6328
6329	u8         reserved_1[0x40];
6330};
6331
6332struct mlx5_ifc_destroy_psv_in_bits {
6333	u8         opcode[0x10];
6334	u8         reserved_0[0x10];
6335
6336	u8         reserved_1[0x10];
6337	u8         op_mod[0x10];
6338
6339	u8         reserved_2[0x8];
6340	u8         psvn[0x18];
6341
6342	u8         reserved_3[0x20];
6343};
6344
6345struct mlx5_ifc_destroy_mkey_out_bits {
6346	u8         status[0x8];
6347	u8         reserved_0[0x18];
6348
6349	u8         syndrome[0x20];
6350
6351	u8         reserved_1[0x40];
6352};
6353
6354struct mlx5_ifc_destroy_mkey_in_bits {
6355	u8         opcode[0x10];
6356	u8         reserved_0[0x10];
6357
6358	u8         reserved_1[0x10];
6359	u8         op_mod[0x10];
6360
6361	u8         reserved_2[0x8];
6362	u8         mkey_index[0x18];
6363
6364	u8         reserved_3[0x20];
6365};
6366
6367struct mlx5_ifc_destroy_flow_table_out_bits {
6368	u8         status[0x8];
6369	u8         reserved_0[0x18];
6370
6371	u8         syndrome[0x20];
6372
6373	u8         reserved_1[0x40];
6374};
6375
6376struct mlx5_ifc_destroy_flow_table_in_bits {
6377	u8         opcode[0x10];
6378	u8         reserved_0[0x10];
6379
6380	u8         reserved_1[0x10];
6381	u8         op_mod[0x10];
6382
6383	u8         other_vport[0x1];
6384	u8         reserved_2[0xf];
6385	u8         vport_number[0x10];
6386
6387	u8         reserved_3[0x20];
6388
6389	u8         table_type[0x8];
6390	u8         reserved_4[0x18];
6391
6392	u8         reserved_5[0x8];
6393	u8         table_id[0x18];
6394
6395	u8         reserved_6[0x140];
6396};
6397
6398struct mlx5_ifc_destroy_flow_group_out_bits {
6399	u8         status[0x8];
6400	u8         reserved_0[0x18];
6401
6402	u8         syndrome[0x20];
6403
6404	u8         reserved_1[0x40];
6405};
6406
6407struct mlx5_ifc_destroy_flow_group_in_bits {
6408	u8         opcode[0x10];
6409	u8         reserved_0[0x10];
6410
6411	u8         reserved_1[0x10];
6412	u8         op_mod[0x10];
6413
6414	u8         other_vport[0x1];
6415	u8         reserved_2[0xf];
6416	u8         vport_number[0x10];
6417
6418	u8         reserved_3[0x20];
6419
6420	u8         table_type[0x8];
6421	u8         reserved_4[0x18];
6422
6423	u8         reserved_5[0x8];
6424	u8         table_id[0x18];
6425
6426	u8         group_id[0x20];
6427
6428	u8         reserved_6[0x120];
6429};
6430
6431struct mlx5_ifc_destroy_eq_out_bits {
6432	u8         status[0x8];
6433	u8         reserved_0[0x18];
6434
6435	u8         syndrome[0x20];
6436
6437	u8         reserved_1[0x40];
6438};
6439
6440struct mlx5_ifc_destroy_eq_in_bits {
6441	u8         opcode[0x10];
6442	u8         reserved_0[0x10];
6443
6444	u8         reserved_1[0x10];
6445	u8         op_mod[0x10];
6446
6447	u8         reserved_2[0x18];
6448	u8         eq_number[0x8];
6449
6450	u8         reserved_3[0x20];
6451};
6452
6453struct mlx5_ifc_destroy_dct_out_bits {
6454	u8         status[0x8];
6455	u8         reserved_0[0x18];
6456
6457	u8         syndrome[0x20];
6458
6459	u8         reserved_1[0x40];
6460};
6461
6462struct mlx5_ifc_destroy_dct_in_bits {
6463	u8         opcode[0x10];
6464	u8         reserved_0[0x10];
6465
6466	u8         reserved_1[0x10];
6467	u8         op_mod[0x10];
6468
6469	u8         reserved_2[0x8];
6470	u8         dctn[0x18];
6471
6472	u8         reserved_3[0x20];
6473};
6474
6475struct mlx5_ifc_destroy_cq_out_bits {
6476	u8         status[0x8];
6477	u8         reserved_0[0x18];
6478
6479	u8         syndrome[0x20];
6480
6481	u8         reserved_1[0x40];
6482};
6483
6484struct mlx5_ifc_destroy_cq_in_bits {
6485	u8         opcode[0x10];
6486	u8         reserved_0[0x10];
6487
6488	u8         reserved_1[0x10];
6489	u8         op_mod[0x10];
6490
6491	u8         reserved_2[0x8];
6492	u8         cqn[0x18];
6493
6494	u8         reserved_3[0x20];
6495};
6496
6497struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6498	u8         status[0x8];
6499	u8         reserved_0[0x18];
6500
6501	u8         syndrome[0x20];
6502
6503	u8         reserved_1[0x40];
6504};
6505
6506struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6507	u8         opcode[0x10];
6508	u8         reserved_0[0x10];
6509
6510	u8         reserved_1[0x10];
6511	u8         op_mod[0x10];
6512
6513	u8         reserved_2[0x20];
6514
6515	u8         reserved_3[0x10];
6516	u8         vxlan_udp_port[0x10];
6517};
6518
6519struct mlx5_ifc_delete_l2_table_entry_out_bits {
6520	u8         status[0x8];
6521	u8         reserved_0[0x18];
6522
6523	u8         syndrome[0x20];
6524
6525	u8         reserved_1[0x40];
6526};
6527
6528struct mlx5_ifc_delete_l2_table_entry_in_bits {
6529	u8         opcode[0x10];
6530	u8         reserved_0[0x10];
6531
6532	u8         reserved_1[0x10];
6533	u8         op_mod[0x10];
6534
6535	u8         reserved_2[0x60];
6536
6537	u8         reserved_3[0x8];
6538	u8         table_index[0x18];
6539
6540	u8         reserved_4[0x140];
6541};
6542
6543struct mlx5_ifc_delete_fte_out_bits {
6544	u8         status[0x8];
6545	u8         reserved_0[0x18];
6546
6547	u8         syndrome[0x20];
6548
6549	u8         reserved_1[0x40];
6550};
6551
6552struct mlx5_ifc_delete_fte_in_bits {
6553	u8         opcode[0x10];
6554	u8         reserved_0[0x10];
6555
6556	u8         reserved_1[0x10];
6557	u8         op_mod[0x10];
6558
6559	u8         other_vport[0x1];
6560	u8         reserved_2[0xf];
6561	u8         vport_number[0x10];
6562
6563	u8         reserved_3[0x20];
6564
6565	u8         table_type[0x8];
6566	u8         reserved_4[0x18];
6567
6568	u8         reserved_5[0x8];
6569	u8         table_id[0x18];
6570
6571	u8         reserved_6[0x40];
6572
6573	u8         flow_index[0x20];
6574
6575	u8         reserved_7[0xe0];
6576};
6577
6578struct mlx5_ifc_dealloc_xrcd_out_bits {
6579	u8         status[0x8];
6580	u8         reserved_0[0x18];
6581
6582	u8         syndrome[0x20];
6583
6584	u8         reserved_1[0x40];
6585};
6586
6587struct mlx5_ifc_dealloc_xrcd_in_bits {
6588	u8         opcode[0x10];
6589	u8         reserved_0[0x10];
6590
6591	u8         reserved_1[0x10];
6592	u8         op_mod[0x10];
6593
6594	u8         reserved_2[0x8];
6595	u8         xrcd[0x18];
6596
6597	u8         reserved_3[0x20];
6598};
6599
6600struct mlx5_ifc_dealloc_uar_out_bits {
6601	u8         status[0x8];
6602	u8         reserved_0[0x18];
6603
6604	u8         syndrome[0x20];
6605
6606	u8         reserved_1[0x40];
6607};
6608
6609struct mlx5_ifc_dealloc_uar_in_bits {
6610	u8         opcode[0x10];
6611	u8         reserved_0[0x10];
6612
6613	u8         reserved_1[0x10];
6614	u8         op_mod[0x10];
6615
6616	u8         reserved_2[0x8];
6617	u8         uar[0x18];
6618
6619	u8         reserved_3[0x20];
6620};
6621
6622struct mlx5_ifc_dealloc_transport_domain_out_bits {
6623	u8         status[0x8];
6624	u8         reserved_0[0x18];
6625
6626	u8         syndrome[0x20];
6627
6628	u8         reserved_1[0x40];
6629};
6630
6631struct mlx5_ifc_dealloc_transport_domain_in_bits {
6632	u8         opcode[0x10];
6633	u8         reserved_0[0x10];
6634
6635	u8         reserved_1[0x10];
6636	u8         op_mod[0x10];
6637
6638	u8         reserved_2[0x8];
6639	u8         transport_domain[0x18];
6640
6641	u8         reserved_3[0x20];
6642};
6643
6644struct mlx5_ifc_dealloc_q_counter_out_bits {
6645	u8         status[0x8];
6646	u8         reserved_0[0x18];
6647
6648	u8         syndrome[0x20];
6649
6650	u8         reserved_1[0x40];
6651};
6652
6653struct mlx5_ifc_counter_id_bits {
6654	u8         reserved[0x10];
6655	u8         counter_id[0x10];
6656};
6657
6658struct mlx5_ifc_diagnostic_params_context_bits {
6659	u8         num_of_counters[0x10];
6660	u8         reserved_2[0x8];
6661	u8         log_num_of_samples[0x8];
6662
6663	u8         single[0x1];
6664	u8         repetitive[0x1];
6665	u8         sync[0x1];
6666	u8         clear[0x1];
6667	u8         on_demand[0x1];
6668	u8         enable[0x1];
6669	u8         reserved_3[0x12];
6670	u8         log_sample_period[0x8];
6671
6672	u8         reserved_4[0x80];
6673
6674	struct mlx5_ifc_counter_id_bits counter_id[0];
6675};
6676
6677struct mlx5_ifc_set_diagnostic_params_in_bits {
6678	u8         opcode[0x10];
6679	u8         reserved_0[0x10];
6680
6681	u8         reserved_1[0x10];
6682	u8         op_mod[0x10];
6683
6684	struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx;
6685};
6686
6687struct mlx5_ifc_set_diagnostic_params_out_bits {
6688	u8         status[0x8];
6689	u8         reserved_0[0x18];
6690
6691	u8         syndrome[0x20];
6692
6693	u8         reserved_1[0x40];
6694};
6695
6696struct mlx5_ifc_query_diagnostic_counters_in_bits {
6697	u8         opcode[0x10];
6698	u8         reserved_0[0x10];
6699
6700	u8         reserved_1[0x10];
6701	u8         op_mod[0x10];
6702
6703	u8         num_of_samples[0x10];
6704	u8         sample_index[0x10];
6705
6706	u8         reserved_2[0x20];
6707};
6708
6709struct mlx5_ifc_diagnostic_counter_bits {
6710	u8         counter_id[0x10];
6711	u8         sample_id[0x10];
6712
6713	u8         time_stamp_31_0[0x20];
6714
6715	u8         counter_value_h[0x20];
6716
6717	u8         counter_value_l[0x20];
6718};
6719
6720struct mlx5_ifc_query_diagnostic_counters_out_bits {
6721	u8         status[0x8];
6722	u8         reserved_0[0x18];
6723
6724	u8         syndrome[0x20];
6725
6726	u8         reserved_1[0x40];
6727
6728	struct mlx5_ifc_diagnostic_counter_bits diag_counter[0];
6729};
6730
6731struct mlx5_ifc_dealloc_q_counter_in_bits {
6732	u8         opcode[0x10];
6733	u8         reserved_0[0x10];
6734
6735	u8         reserved_1[0x10];
6736	u8         op_mod[0x10];
6737
6738	u8         reserved_2[0x18];
6739	u8         counter_set_id[0x8];
6740
6741	u8         reserved_3[0x20];
6742};
6743
6744struct mlx5_ifc_dealloc_pd_out_bits {
6745	u8         status[0x8];
6746	u8         reserved_0[0x18];
6747
6748	u8         syndrome[0x20];
6749
6750	u8         reserved_1[0x40];
6751};
6752
6753struct mlx5_ifc_dealloc_pd_in_bits {
6754	u8         opcode[0x10];
6755	u8         reserved_0[0x10];
6756
6757	u8         reserved_1[0x10];
6758	u8         op_mod[0x10];
6759
6760	u8         reserved_2[0x8];
6761	u8         pd[0x18];
6762
6763	u8         reserved_3[0x20];
6764};
6765
6766struct mlx5_ifc_dealloc_flow_counter_out_bits {
6767	u8         status[0x8];
6768	u8         reserved_0[0x18];
6769
6770	u8         syndrome[0x20];
6771
6772	u8         reserved_1[0x40];
6773};
6774
6775struct mlx5_ifc_dealloc_flow_counter_in_bits {
6776	u8         opcode[0x10];
6777	u8         reserved_0[0x10];
6778
6779	u8         reserved_1[0x10];
6780	u8         op_mod[0x10];
6781
6782	u8         reserved_2[0x10];
6783	u8         flow_counter_id[0x10];
6784
6785	u8         reserved_3[0x20];
6786};
6787
6788struct mlx5_ifc_deactivate_tracer_out_bits {
6789	u8         status[0x8];
6790	u8         reserved_0[0x18];
6791
6792	u8         syndrome[0x20];
6793
6794	u8         reserved_1[0x40];
6795};
6796
6797struct mlx5_ifc_deactivate_tracer_in_bits {
6798	u8         opcode[0x10];
6799	u8         reserved_0[0x10];
6800
6801	u8         reserved_1[0x10];
6802	u8         op_mod[0x10];
6803
6804	u8         mkey[0x20];
6805
6806	u8         reserved_2[0x20];
6807};
6808
6809struct mlx5_ifc_create_xrc_srq_out_bits {
6810	u8         status[0x8];
6811	u8         reserved_0[0x18];
6812
6813	u8         syndrome[0x20];
6814
6815	u8         reserved_1[0x8];
6816	u8         xrc_srqn[0x18];
6817
6818	u8         reserved_2[0x20];
6819};
6820
6821struct mlx5_ifc_create_xrc_srq_in_bits {
6822	u8         opcode[0x10];
6823	u8         reserved_0[0x10];
6824
6825	u8         reserved_1[0x10];
6826	u8         op_mod[0x10];
6827
6828	u8         reserved_2[0x40];
6829
6830	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6831
6832	u8         reserved_3[0x600];
6833
6834	u8         pas[0][0x40];
6835};
6836
6837struct mlx5_ifc_create_tis_out_bits {
6838	u8         status[0x8];
6839	u8         reserved_0[0x18];
6840
6841	u8         syndrome[0x20];
6842
6843	u8         reserved_1[0x8];
6844	u8         tisn[0x18];
6845
6846	u8         reserved_2[0x20];
6847};
6848
6849struct mlx5_ifc_create_tis_in_bits {
6850	u8         opcode[0x10];
6851	u8         reserved_0[0x10];
6852
6853	u8         reserved_1[0x10];
6854	u8         op_mod[0x10];
6855
6856	u8         reserved_2[0xc0];
6857
6858	struct mlx5_ifc_tisc_bits ctx;
6859};
6860
6861struct mlx5_ifc_create_tir_out_bits {
6862	u8         status[0x8];
6863	u8         reserved_0[0x18];
6864
6865	u8         syndrome[0x20];
6866
6867	u8         reserved_1[0x8];
6868	u8         tirn[0x18];
6869
6870	u8         reserved_2[0x20];
6871};
6872
6873struct mlx5_ifc_create_tir_in_bits {
6874	u8         opcode[0x10];
6875	u8         reserved_0[0x10];
6876
6877	u8         reserved_1[0x10];
6878	u8         op_mod[0x10];
6879
6880	u8         reserved_2[0xc0];
6881
6882	struct mlx5_ifc_tirc_bits tir_context;
6883};
6884
6885struct mlx5_ifc_create_srq_out_bits {
6886	u8         status[0x8];
6887	u8         reserved_0[0x18];
6888
6889	u8         syndrome[0x20];
6890
6891	u8         reserved_1[0x8];
6892	u8         srqn[0x18];
6893
6894	u8         reserved_2[0x20];
6895};
6896
6897struct mlx5_ifc_create_srq_in_bits {
6898	u8         opcode[0x10];
6899	u8         reserved_0[0x10];
6900
6901	u8         reserved_1[0x10];
6902	u8         op_mod[0x10];
6903
6904	u8         reserved_2[0x40];
6905
6906	struct mlx5_ifc_srqc_bits srq_context_entry;
6907
6908	u8         reserved_3[0x600];
6909
6910	u8         pas[0][0x40];
6911};
6912
6913struct mlx5_ifc_create_sq_out_bits {
6914	u8         status[0x8];
6915	u8         reserved_0[0x18];
6916
6917	u8         syndrome[0x20];
6918
6919	u8         reserved_1[0x8];
6920	u8         sqn[0x18];
6921
6922	u8         reserved_2[0x20];
6923};
6924
6925struct mlx5_ifc_create_sq_in_bits {
6926	u8         opcode[0x10];
6927	u8         reserved_0[0x10];
6928
6929	u8         reserved_1[0x10];
6930	u8         op_mod[0x10];
6931
6932	u8         reserved_2[0xc0];
6933
6934	struct mlx5_ifc_sqc_bits ctx;
6935};
6936
6937struct mlx5_ifc_create_scheduling_element_out_bits {
6938	u8         status[0x8];
6939	u8         reserved_at_8[0x18];
6940
6941	u8         syndrome[0x20];
6942
6943	u8         reserved_at_40[0x40];
6944
6945	u8         scheduling_element_id[0x20];
6946
6947	u8         reserved_at_a0[0x160];
6948};
6949
6950enum {
6951	MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
6952};
6953
6954struct mlx5_ifc_create_scheduling_element_in_bits {
6955	u8         opcode[0x10];
6956	u8         reserved_at_10[0x10];
6957
6958	u8         reserved_at_20[0x10];
6959	u8         op_mod[0x10];
6960
6961	u8         scheduling_hierarchy[0x8];
6962	u8         reserved_at_48[0x18];
6963
6964	u8         reserved_at_60[0xa0];
6965
6966	struct mlx5_ifc_scheduling_context_bits scheduling_context;
6967
6968	u8         reserved_at_300[0x100];
6969};
6970
6971struct mlx5_ifc_create_rqt_out_bits {
6972	u8         status[0x8];
6973	u8         reserved_0[0x18];
6974
6975	u8         syndrome[0x20];
6976
6977	u8         reserved_1[0x8];
6978	u8         rqtn[0x18];
6979
6980	u8         reserved_2[0x20];
6981};
6982
6983struct mlx5_ifc_create_rqt_in_bits {
6984	u8         opcode[0x10];
6985	u8         reserved_0[0x10];
6986
6987	u8         reserved_1[0x10];
6988	u8         op_mod[0x10];
6989
6990	u8         reserved_2[0xc0];
6991
6992	struct mlx5_ifc_rqtc_bits rqt_context;
6993};
6994
6995struct mlx5_ifc_create_rq_out_bits {
6996	u8         status[0x8];
6997	u8         reserved_0[0x18];
6998
6999	u8         syndrome[0x20];
7000
7001	u8         reserved_1[0x8];
7002	u8         rqn[0x18];
7003
7004	u8         reserved_2[0x20];
7005};
7006
7007struct mlx5_ifc_create_rq_in_bits {
7008	u8         opcode[0x10];
7009	u8         reserved_0[0x10];
7010
7011	u8         reserved_1[0x10];
7012	u8         op_mod[0x10];
7013
7014	u8         reserved_2[0xc0];
7015
7016	struct mlx5_ifc_rqc_bits ctx;
7017};
7018
7019struct mlx5_ifc_create_rmp_out_bits {
7020	u8         status[0x8];
7021	u8         reserved_0[0x18];
7022
7023	u8         syndrome[0x20];
7024
7025	u8         reserved_1[0x8];
7026	u8         rmpn[0x18];
7027
7028	u8         reserved_2[0x20];
7029};
7030
7031struct mlx5_ifc_create_rmp_in_bits {
7032	u8         opcode[0x10];
7033	u8         reserved_0[0x10];
7034
7035	u8         reserved_1[0x10];
7036	u8         op_mod[0x10];
7037
7038	u8         reserved_2[0xc0];
7039
7040	struct mlx5_ifc_rmpc_bits ctx;
7041};
7042
7043struct mlx5_ifc_create_qp_out_bits {
7044	u8         status[0x8];
7045	u8         reserved_0[0x18];
7046
7047	u8         syndrome[0x20];
7048
7049	u8         reserved_1[0x8];
7050	u8         qpn[0x18];
7051
7052	u8         reserved_2[0x20];
7053};
7054
7055struct mlx5_ifc_create_qp_in_bits {
7056	u8         opcode[0x10];
7057	u8         reserved_0[0x10];
7058
7059	u8         reserved_1[0x10];
7060	u8         op_mod[0x10];
7061
7062	u8         reserved_2[0x8];
7063	u8         input_qpn[0x18];
7064
7065	u8         reserved_3[0x20];
7066
7067	u8         opt_param_mask[0x20];
7068
7069	u8         reserved_4[0x20];
7070
7071	struct mlx5_ifc_qpc_bits qpc;
7072
7073	u8         reserved_5[0x80];
7074
7075	u8         pas[0][0x40];
7076};
7077
7078struct mlx5_ifc_create_qos_para_vport_out_bits {
7079	u8         status[0x8];
7080	u8         reserved_at_8[0x18];
7081
7082	u8         syndrome[0x20];
7083
7084	u8         reserved_at_40[0x20];
7085
7086	u8         reserved_at_60[0x10];
7087	u8         qos_para_vport_number[0x10];
7088
7089	u8         reserved_at_80[0x180];
7090};
7091
7092struct mlx5_ifc_create_qos_para_vport_in_bits {
7093	u8         opcode[0x10];
7094	u8         reserved_at_10[0x10];
7095
7096	u8         reserved_at_20[0x10];
7097	u8         op_mod[0x10];
7098
7099	u8         reserved_at_40[0x1c0];
7100};
7101
7102struct mlx5_ifc_create_psv_out_bits {
7103	u8         status[0x8];
7104	u8         reserved_0[0x18];
7105
7106	u8         syndrome[0x20];
7107
7108	u8         reserved_1[0x40];
7109
7110	u8         reserved_2[0x8];
7111	u8         psv0_index[0x18];
7112
7113	u8         reserved_3[0x8];
7114	u8         psv1_index[0x18];
7115
7116	u8         reserved_4[0x8];
7117	u8         psv2_index[0x18];
7118
7119	u8         reserved_5[0x8];
7120	u8         psv3_index[0x18];
7121};
7122
7123struct mlx5_ifc_create_psv_in_bits {
7124	u8         opcode[0x10];
7125	u8         reserved_0[0x10];
7126
7127	u8         reserved_1[0x10];
7128	u8         op_mod[0x10];
7129
7130	u8         num_psv[0x4];
7131	u8         reserved_2[0x4];
7132	u8         pd[0x18];
7133
7134	u8         reserved_3[0x20];
7135};
7136
7137struct mlx5_ifc_create_mkey_out_bits {
7138	u8         status[0x8];
7139	u8         reserved_0[0x18];
7140
7141	u8         syndrome[0x20];
7142
7143	u8         reserved_1[0x8];
7144	u8         mkey_index[0x18];
7145
7146	u8         reserved_2[0x20];
7147};
7148
7149struct mlx5_ifc_create_mkey_in_bits {
7150	u8         opcode[0x10];
7151	u8         reserved_0[0x10];
7152
7153	u8         reserved_1[0x10];
7154	u8         op_mod[0x10];
7155
7156	u8         reserved_2[0x20];
7157
7158	u8         pg_access[0x1];
7159	u8         reserved_3[0x1f];
7160
7161	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7162
7163	u8         reserved_4[0x80];
7164
7165	u8         translations_octword_actual_size[0x20];
7166
7167	u8         reserved_5[0x560];
7168
7169	u8         klm_pas_mtt[0][0x20];
7170};
7171
7172struct mlx5_ifc_create_flow_table_out_bits {
7173	u8         status[0x8];
7174	u8         reserved_0[0x18];
7175
7176	u8         syndrome[0x20];
7177
7178	u8         reserved_1[0x8];
7179	u8         table_id[0x18];
7180
7181	u8         reserved_2[0x20];
7182};
7183
7184struct mlx5_ifc_create_flow_table_in_bits {
7185	u8         opcode[0x10];
7186	u8         reserved_at_10[0x10];
7187
7188	u8         reserved_at_20[0x10];
7189	u8         op_mod[0x10];
7190
7191	u8         other_vport[0x1];
7192	u8         reserved_at_41[0xf];
7193	u8         vport_number[0x10];
7194
7195	u8         reserved_at_60[0x20];
7196
7197	u8         table_type[0x8];
7198	u8         reserved_at_88[0x18];
7199
7200	u8         reserved_at_a0[0x20];
7201
7202	struct mlx5_ifc_flow_table_context_bits flow_table_context;
7203};
7204
7205struct mlx5_ifc_create_flow_group_out_bits {
7206	u8         status[0x8];
7207	u8         reserved_0[0x18];
7208
7209	u8         syndrome[0x20];
7210
7211	u8         reserved_1[0x8];
7212	u8         group_id[0x18];
7213
7214	u8         reserved_2[0x20];
7215};
7216
7217enum {
7218	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
7219	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
7220	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
7221};
7222
7223struct mlx5_ifc_create_flow_group_in_bits {
7224	u8         opcode[0x10];
7225	u8         reserved_0[0x10];
7226
7227	u8         reserved_1[0x10];
7228	u8         op_mod[0x10];
7229
7230	u8         other_vport[0x1];
7231	u8         reserved_2[0xf];
7232	u8         vport_number[0x10];
7233
7234	u8         reserved_3[0x20];
7235
7236	u8         table_type[0x8];
7237	u8         reserved_4[0x18];
7238
7239	u8         reserved_5[0x8];
7240	u8         table_id[0x18];
7241
7242	u8         reserved_6[0x20];
7243
7244	u8         start_flow_index[0x20];
7245
7246	u8         reserved_7[0x20];
7247
7248	u8         end_flow_index[0x20];
7249
7250	u8         reserved_8[0xa0];
7251
7252	u8         reserved_9[0x18];
7253	u8         match_criteria_enable[0x8];
7254
7255	struct mlx5_ifc_fte_match_param_bits match_criteria;
7256
7257	u8         reserved_10[0xe00];
7258};
7259
7260struct mlx5_ifc_create_eq_out_bits {
7261	u8         status[0x8];
7262	u8         reserved_0[0x18];
7263
7264	u8         syndrome[0x20];
7265
7266	u8         reserved_1[0x18];
7267	u8         eq_number[0x8];
7268
7269	u8         reserved_2[0x20];
7270};
7271
7272struct mlx5_ifc_create_eq_in_bits {
7273	u8         opcode[0x10];
7274	u8         reserved_0[0x10];
7275
7276	u8         reserved_1[0x10];
7277	u8         op_mod[0x10];
7278
7279	u8         reserved_2[0x40];
7280
7281	struct mlx5_ifc_eqc_bits eq_context_entry;
7282
7283	u8         reserved_3[0x40];
7284
7285	u8         event_bitmask[0x40];
7286
7287	u8         reserved_4[0x580];
7288
7289	u8         pas[0][0x40];
7290};
7291
7292struct mlx5_ifc_create_dct_out_bits {
7293	u8         status[0x8];
7294	u8         reserved_0[0x18];
7295
7296	u8         syndrome[0x20];
7297
7298	u8         reserved_1[0x8];
7299	u8         dctn[0x18];
7300
7301	u8         reserved_2[0x20];
7302};
7303
7304struct mlx5_ifc_create_dct_in_bits {
7305	u8         opcode[0x10];
7306	u8         reserved_0[0x10];
7307
7308	u8         reserved_1[0x10];
7309	u8         op_mod[0x10];
7310
7311	u8         reserved_2[0x40];
7312
7313	struct mlx5_ifc_dctc_bits dct_context_entry;
7314
7315	u8         reserved_3[0x180];
7316};
7317
7318struct mlx5_ifc_create_cq_out_bits {
7319	u8         status[0x8];
7320	u8         reserved_0[0x18];
7321
7322	u8         syndrome[0x20];
7323
7324	u8         reserved_1[0x8];
7325	u8         cqn[0x18];
7326
7327	u8         reserved_2[0x20];
7328};
7329
7330struct mlx5_ifc_create_cq_in_bits {
7331	u8         opcode[0x10];
7332	u8         reserved_0[0x10];
7333
7334	u8         reserved_1[0x10];
7335	u8         op_mod[0x10];
7336
7337	u8         reserved_2[0x40];
7338
7339	struct mlx5_ifc_cqc_bits cq_context;
7340
7341	u8         reserved_3[0x600];
7342
7343	u8         pas[0][0x40];
7344};
7345
7346struct mlx5_ifc_config_int_moderation_out_bits {
7347	u8         status[0x8];
7348	u8         reserved_0[0x18];
7349
7350	u8         syndrome[0x20];
7351
7352	u8         reserved_1[0x4];
7353	u8         min_delay[0xc];
7354	u8         int_vector[0x10];
7355
7356	u8         reserved_2[0x20];
7357};
7358
7359enum {
7360	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7361	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7362};
7363
7364struct mlx5_ifc_config_int_moderation_in_bits {
7365	u8         opcode[0x10];
7366	u8         reserved_0[0x10];
7367
7368	u8         reserved_1[0x10];
7369	u8         op_mod[0x10];
7370
7371	u8         reserved_2[0x4];
7372	u8         min_delay[0xc];
7373	u8         int_vector[0x10];
7374
7375	u8         reserved_3[0x20];
7376};
7377
7378struct mlx5_ifc_attach_to_mcg_out_bits {
7379	u8         status[0x8];
7380	u8         reserved_0[0x18];
7381
7382	u8         syndrome[0x20];
7383
7384	u8         reserved_1[0x40];
7385};
7386
7387struct mlx5_ifc_attach_to_mcg_in_bits {
7388	u8         opcode[0x10];
7389	u8         reserved_0[0x10];
7390
7391	u8         reserved_1[0x10];
7392	u8         op_mod[0x10];
7393
7394	u8         reserved_2[0x8];
7395	u8         qpn[0x18];
7396
7397	u8         reserved_3[0x20];
7398
7399	u8         multicast_gid[16][0x8];
7400};
7401
7402struct mlx5_ifc_arm_xrc_srq_out_bits {
7403	u8         status[0x8];
7404	u8         reserved_0[0x18];
7405
7406	u8         syndrome[0x20];
7407
7408	u8         reserved_1[0x40];
7409};
7410
7411enum {
7412	MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7413};
7414
7415struct mlx5_ifc_arm_xrc_srq_in_bits {
7416	u8         opcode[0x10];
7417	u8         reserved_0[0x10];
7418
7419	u8         reserved_1[0x10];
7420	u8         op_mod[0x10];
7421
7422	u8         reserved_2[0x8];
7423	u8         xrc_srqn[0x18];
7424
7425	u8         reserved_3[0x10];
7426	u8         lwm[0x10];
7427};
7428
7429struct mlx5_ifc_arm_rq_out_bits {
7430	u8         status[0x8];
7431	u8         reserved_0[0x18];
7432
7433	u8         syndrome[0x20];
7434
7435	u8         reserved_1[0x40];
7436};
7437
7438enum {
7439	MLX5_ARM_RQ_IN_OP_MOD_SRQ  = 0x1,
7440};
7441
7442struct mlx5_ifc_arm_rq_in_bits {
7443	u8         opcode[0x10];
7444	u8         reserved_0[0x10];
7445
7446	u8         reserved_1[0x10];
7447	u8         op_mod[0x10];
7448
7449	u8         reserved_2[0x8];
7450	u8         srq_number[0x18];
7451
7452	u8         reserved_3[0x10];
7453	u8         lwm[0x10];
7454};
7455
7456struct mlx5_ifc_arm_dct_out_bits {
7457	u8         status[0x8];
7458	u8         reserved_0[0x18];
7459
7460	u8         syndrome[0x20];
7461
7462	u8         reserved_1[0x40];
7463};
7464
7465struct mlx5_ifc_arm_dct_in_bits {
7466	u8         opcode[0x10];
7467	u8         reserved_0[0x10];
7468
7469	u8         reserved_1[0x10];
7470	u8         op_mod[0x10];
7471
7472	u8         reserved_2[0x8];
7473	u8         dctn[0x18];
7474
7475	u8         reserved_3[0x20];
7476};
7477
7478struct mlx5_ifc_alloc_xrcd_out_bits {
7479	u8         status[0x8];
7480	u8         reserved_0[0x18];
7481
7482	u8         syndrome[0x20];
7483
7484	u8         reserved_1[0x8];
7485	u8         xrcd[0x18];
7486
7487	u8         reserved_2[0x20];
7488};
7489
7490struct mlx5_ifc_alloc_xrcd_in_bits {
7491	u8         opcode[0x10];
7492	u8         reserved_0[0x10];
7493
7494	u8         reserved_1[0x10];
7495	u8         op_mod[0x10];
7496
7497	u8         reserved_2[0x40];
7498};
7499
7500struct mlx5_ifc_alloc_uar_out_bits {
7501	u8         status[0x8];
7502	u8         reserved_0[0x18];
7503
7504	u8         syndrome[0x20];
7505
7506	u8         reserved_1[0x8];
7507	u8         uar[0x18];
7508
7509	u8         reserved_2[0x20];
7510};
7511
7512struct mlx5_ifc_alloc_uar_in_bits {
7513	u8         opcode[0x10];
7514	u8         reserved_0[0x10];
7515
7516	u8         reserved_1[0x10];
7517	u8         op_mod[0x10];
7518
7519	u8         reserved_2[0x40];
7520};
7521
7522struct mlx5_ifc_alloc_transport_domain_out_bits {
7523	u8         status[0x8];
7524	u8         reserved_0[0x18];
7525
7526	u8         syndrome[0x20];
7527
7528	u8         reserved_1[0x8];
7529	u8         transport_domain[0x18];
7530
7531	u8         reserved_2[0x20];
7532};
7533
7534struct mlx5_ifc_alloc_transport_domain_in_bits {
7535	u8         opcode[0x10];
7536	u8         reserved_0[0x10];
7537
7538	u8         reserved_1[0x10];
7539	u8         op_mod[0x10];
7540
7541	u8         reserved_2[0x40];
7542};
7543
7544struct mlx5_ifc_alloc_q_counter_out_bits {
7545	u8         status[0x8];
7546	u8         reserved_0[0x18];
7547
7548	u8         syndrome[0x20];
7549
7550	u8         reserved_1[0x18];
7551	u8         counter_set_id[0x8];
7552
7553	u8         reserved_2[0x20];
7554};
7555
7556struct mlx5_ifc_alloc_q_counter_in_bits {
7557	u8         opcode[0x10];
7558	u8         reserved_0[0x10];
7559
7560	u8         reserved_1[0x10];
7561	u8         op_mod[0x10];
7562
7563	u8         reserved_2[0x40];
7564};
7565
7566struct mlx5_ifc_alloc_pd_out_bits {
7567	u8         status[0x8];
7568	u8         reserved_0[0x18];
7569
7570	u8         syndrome[0x20];
7571
7572	u8         reserved_1[0x8];
7573	u8         pd[0x18];
7574
7575	u8         reserved_2[0x20];
7576};
7577
7578struct mlx5_ifc_alloc_pd_in_bits {
7579	u8         opcode[0x10];
7580	u8         reserved_0[0x10];
7581
7582	u8         reserved_1[0x10];
7583	u8         op_mod[0x10];
7584
7585	u8         reserved_2[0x40];
7586};
7587
7588struct mlx5_ifc_alloc_flow_counter_out_bits {
7589	u8         status[0x8];
7590	u8         reserved_0[0x18];
7591
7592	u8         syndrome[0x20];
7593
7594	u8         reserved_1[0x10];
7595	u8         flow_counter_id[0x10];
7596
7597	u8         reserved_2[0x20];
7598};
7599
7600struct mlx5_ifc_alloc_flow_counter_in_bits {
7601	u8         opcode[0x10];
7602	u8         reserved_0[0x10];
7603
7604	u8         reserved_1[0x10];
7605	u8         op_mod[0x10];
7606
7607	u8         reserved_2[0x40];
7608};
7609
7610struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7611	u8         status[0x8];
7612	u8         reserved_0[0x18];
7613
7614	u8         syndrome[0x20];
7615
7616	u8         reserved_1[0x40];
7617};
7618
7619struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7620	u8         opcode[0x10];
7621	u8         reserved_0[0x10];
7622
7623	u8         reserved_1[0x10];
7624	u8         op_mod[0x10];
7625
7626	u8         reserved_2[0x20];
7627
7628	u8         reserved_3[0x10];
7629	u8         vxlan_udp_port[0x10];
7630};
7631
7632struct mlx5_ifc_activate_tracer_out_bits {
7633	u8         status[0x8];
7634	u8         reserved_0[0x18];
7635
7636	u8         syndrome[0x20];
7637
7638	u8         reserved_1[0x40];
7639};
7640
7641struct mlx5_ifc_activate_tracer_in_bits {
7642	u8         opcode[0x10];
7643	u8         reserved_0[0x10];
7644
7645	u8         reserved_1[0x10];
7646	u8         op_mod[0x10];
7647
7648	u8         mkey[0x20];
7649
7650	u8         reserved_2[0x20];
7651};
7652
7653struct mlx5_ifc_set_rate_limit_out_bits {
7654	u8         status[0x8];
7655	u8         reserved_at_8[0x18];
7656
7657	u8         syndrome[0x20];
7658
7659	u8         reserved_at_40[0x40];
7660};
7661
7662struct mlx5_ifc_set_rate_limit_in_bits {
7663	u8         opcode[0x10];
7664	u8         reserved_at_10[0x10];
7665
7666	u8         reserved_at_20[0x10];
7667	u8         op_mod[0x10];
7668
7669	u8         reserved_at_40[0x10];
7670	u8         rate_limit_index[0x10];
7671
7672	u8         reserved_at_60[0x20];
7673
7674	u8         rate_limit[0x20];
7675	u8         burst_upper_bound[0x20];
7676};
7677
7678struct mlx5_ifc_access_register_out_bits {
7679	u8         status[0x8];
7680	u8         reserved_0[0x18];
7681
7682	u8         syndrome[0x20];
7683
7684	u8         reserved_1[0x40];
7685
7686	u8         register_data[0][0x20];
7687};
7688
7689enum {
7690	MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7691	MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7692};
7693
7694struct mlx5_ifc_access_register_in_bits {
7695	u8         opcode[0x10];
7696	u8         reserved_0[0x10];
7697
7698	u8         reserved_1[0x10];
7699	u8         op_mod[0x10];
7700
7701	u8         reserved_2[0x10];
7702	u8         register_id[0x10];
7703
7704	u8         argument[0x20];
7705
7706	u8         register_data[0][0x20];
7707};
7708
7709struct mlx5_ifc_sltp_reg_bits {
7710	u8         status[0x4];
7711	u8         version[0x4];
7712	u8         local_port[0x8];
7713	u8         pnat[0x2];
7714	u8         reserved_0[0x2];
7715	u8         lane[0x4];
7716	u8         reserved_1[0x8];
7717
7718	u8         reserved_2[0x20];
7719
7720	u8         reserved_3[0x7];
7721	u8         polarity[0x1];
7722	u8         ob_tap0[0x8];
7723	u8         ob_tap1[0x8];
7724	u8         ob_tap2[0x8];
7725
7726	u8         reserved_4[0xc];
7727	u8         ob_preemp_mode[0x4];
7728	u8         ob_reg[0x8];
7729	u8         ob_bias[0x8];
7730
7731	u8         reserved_5[0x20];
7732};
7733
7734struct mlx5_ifc_slrp_reg_bits {
7735	u8         status[0x4];
7736	u8         version[0x4];
7737	u8         local_port[0x8];
7738	u8         pnat[0x2];
7739	u8         reserved_0[0x2];
7740	u8         lane[0x4];
7741	u8         reserved_1[0x8];
7742
7743	u8         ib_sel[0x2];
7744	u8         reserved_2[0x11];
7745	u8         dp_sel[0x1];
7746	u8         dp90sel[0x4];
7747	u8         mix90phase[0x8];
7748
7749	u8         ffe_tap0[0x8];
7750	u8         ffe_tap1[0x8];
7751	u8         ffe_tap2[0x8];
7752	u8         ffe_tap3[0x8];
7753
7754	u8         ffe_tap4[0x8];
7755	u8         ffe_tap5[0x8];
7756	u8         ffe_tap6[0x8];
7757	u8         ffe_tap7[0x8];
7758
7759	u8         ffe_tap8[0x8];
7760	u8         mixerbias_tap_amp[0x8];
7761	u8         reserved_3[0x7];
7762	u8         ffe_tap_en[0x9];
7763
7764	u8         ffe_tap_offset0[0x8];
7765	u8         ffe_tap_offset1[0x8];
7766	u8         slicer_offset0[0x10];
7767
7768	u8         mixer_offset0[0x10];
7769	u8         mixer_offset1[0x10];
7770
7771	u8         mixerbgn_inp[0x8];
7772	u8         mixerbgn_inn[0x8];
7773	u8         mixerbgn_refp[0x8];
7774	u8         mixerbgn_refn[0x8];
7775
7776	u8         sel_slicer_lctrl_h[0x1];
7777	u8         sel_slicer_lctrl_l[0x1];
7778	u8         reserved_4[0x1];
7779	u8         ref_mixer_vreg[0x5];
7780	u8         slicer_gctrl[0x8];
7781	u8         lctrl_input[0x8];
7782	u8         mixer_offset_cm1[0x8];
7783
7784	u8         common_mode[0x6];
7785	u8         reserved_5[0x1];
7786	u8         mixer_offset_cm0[0x9];
7787	u8         reserved_6[0x7];
7788	u8         slicer_offset_cm[0x9];
7789};
7790
7791struct mlx5_ifc_slrg_reg_bits {
7792	u8         status[0x4];
7793	u8         version[0x4];
7794	u8         local_port[0x8];
7795	u8         pnat[0x2];
7796	u8         reserved_0[0x2];
7797	u8         lane[0x4];
7798	u8         reserved_1[0x8];
7799
7800	u8         time_to_link_up[0x10];
7801	u8         reserved_2[0xc];
7802	u8         grade_lane_speed[0x4];
7803
7804	u8         grade_version[0x8];
7805	u8         grade[0x18];
7806
7807	u8         reserved_3[0x4];
7808	u8         height_grade_type[0x4];
7809	u8         height_grade[0x18];
7810
7811	u8         height_dz[0x10];
7812	u8         height_dv[0x10];
7813
7814	u8         reserved_4[0x10];
7815	u8         height_sigma[0x10];
7816
7817	u8         reserved_5[0x20];
7818
7819	u8         reserved_6[0x4];
7820	u8         phase_grade_type[0x4];
7821	u8         phase_grade[0x18];
7822
7823	u8         reserved_7[0x8];
7824	u8         phase_eo_pos[0x8];
7825	u8         reserved_8[0x8];
7826	u8         phase_eo_neg[0x8];
7827
7828	u8         ffe_set_tested[0x10];
7829	u8         test_errors_per_lane[0x10];
7830};
7831
7832struct mlx5_ifc_pvlc_reg_bits {
7833	u8         reserved_0[0x8];
7834	u8         local_port[0x8];
7835	u8         reserved_1[0x10];
7836
7837	u8         reserved_2[0x1c];
7838	u8         vl_hw_cap[0x4];
7839
7840	u8         reserved_3[0x1c];
7841	u8         vl_admin[0x4];
7842
7843	u8         reserved_4[0x1c];
7844	u8         vl_operational[0x4];
7845};
7846
7847struct mlx5_ifc_pude_reg_bits {
7848	u8         swid[0x8];
7849	u8         local_port[0x8];
7850	u8         reserved_0[0x4];
7851	u8         admin_status[0x4];
7852	u8         reserved_1[0x4];
7853	u8         oper_status[0x4];
7854
7855	u8         reserved_2[0x60];
7856};
7857
7858enum {
7859	MLX5_PTYS_REG_PROTO_MASK_INFINIBAND  = 0x1,
7860	MLX5_PTYS_REG_PROTO_MASK_ETHERNET    = 0x4,
7861};
7862
7863struct mlx5_ifc_ptys_reg_bits {
7864	u8         reserved_0[0x1];
7865	u8         an_disable_admin[0x1];
7866	u8         an_disable_cap[0x1];
7867	u8         reserved_1[0x4];
7868	u8         force_tx_aba_param[0x1];
7869	u8         local_port[0x8];
7870	u8         reserved_2[0xd];
7871	u8         proto_mask[0x3];
7872
7873	u8         an_status[0x4];
7874	u8         reserved_3[0xc];
7875	u8         data_rate_oper[0x10];
7876
7877	u8         ext_eth_proto_capability[0x20];
7878
7879	u8         eth_proto_capability[0x20];
7880
7881	u8         ib_link_width_capability[0x10];
7882	u8         ib_proto_capability[0x10];
7883
7884	u8         ext_eth_proto_admin[0x20];
7885
7886	u8         eth_proto_admin[0x20];
7887
7888	u8         ib_link_width_admin[0x10];
7889	u8         ib_proto_admin[0x10];
7890
7891	u8         ext_eth_proto_oper[0x20];
7892
7893	u8         eth_proto_oper[0x20];
7894
7895	u8         ib_link_width_oper[0x10];
7896	u8         ib_proto_oper[0x10];
7897
7898	u8         reserved_4[0x1c];
7899	u8         connector_type[0x4];
7900
7901	u8         eth_proto_lp_advertise[0x20];
7902
7903	u8         reserved_5[0x60];
7904};
7905
7906struct mlx5_ifc_ptas_reg_bits {
7907	u8         reserved_0[0x20];
7908
7909	u8         algorithm_options[0x10];
7910	u8         reserved_1[0x4];
7911	u8         repetitions_mode[0x4];
7912	u8         num_of_repetitions[0x8];
7913
7914	u8         grade_version[0x8];
7915	u8         height_grade_type[0x4];
7916	u8         phase_grade_type[0x4];
7917	u8         height_grade_weight[0x8];
7918	u8         phase_grade_weight[0x8];
7919
7920	u8         gisim_measure_bits[0x10];
7921	u8         adaptive_tap_measure_bits[0x10];
7922
7923	u8         ber_bath_high_error_threshold[0x10];
7924	u8         ber_bath_mid_error_threshold[0x10];
7925
7926	u8         ber_bath_low_error_threshold[0x10];
7927	u8         one_ratio_high_threshold[0x10];
7928
7929	u8         one_ratio_high_mid_threshold[0x10];
7930	u8         one_ratio_low_mid_threshold[0x10];
7931
7932	u8         one_ratio_low_threshold[0x10];
7933	u8         ndeo_error_threshold[0x10];
7934
7935	u8         mixer_offset_step_size[0x10];
7936	u8         reserved_2[0x8];
7937	u8         mix90_phase_for_voltage_bath[0x8];
7938
7939	u8         mixer_offset_start[0x10];
7940	u8         mixer_offset_end[0x10];
7941
7942	u8         reserved_3[0x15];
7943	u8         ber_test_time[0xb];
7944};
7945
7946struct mlx5_ifc_pspa_reg_bits {
7947	u8         swid[0x8];
7948	u8         local_port[0x8];
7949	u8         sub_port[0x8];
7950	u8         reserved_0[0x8];
7951
7952	u8         reserved_1[0x20];
7953};
7954
7955struct mlx5_ifc_ppsc_reg_bits {
7956	u8         reserved_0[0x8];
7957	u8         local_port[0x8];
7958	u8         reserved_1[0x10];
7959
7960	u8         reserved_2[0x60];
7961
7962	u8         reserved_3[0x1c];
7963	u8         wrps_admin[0x4];
7964
7965	u8         reserved_4[0x1c];
7966	u8         wrps_status[0x4];
7967
7968	u8         up_th_vld[0x1];
7969	u8         down_th_vld[0x1];
7970	u8         reserved_5[0x6];
7971	u8         up_threshold[0x8];
7972	u8         reserved_6[0x8];
7973	u8         down_threshold[0x8];
7974
7975	u8         reserved_7[0x20];
7976
7977	u8         reserved_8[0x1c];
7978	u8         srps_admin[0x4];
7979
7980	u8         reserved_9[0x60];
7981};
7982
7983struct mlx5_ifc_pplr_reg_bits {
7984	u8         reserved_0[0x8];
7985	u8         local_port[0x8];
7986	u8         reserved_1[0x10];
7987
7988	u8         reserved_2[0x8];
7989	u8         lb_cap[0x8];
7990	u8         reserved_3[0x8];
7991	u8         lb_en[0x8];
7992};
7993
7994struct mlx5_ifc_pplm_reg_bits {
7995	u8         reserved_at_0[0x8];
7996	u8	   local_port[0x8];
7997	u8	   reserved_at_10[0x10];
7998
7999	u8	   reserved_at_20[0x20];
8000
8001	u8	   port_profile_mode[0x8];
8002	u8	   static_port_profile[0x8];
8003	u8	   active_port_profile[0x8];
8004	u8	   reserved_at_58[0x8];
8005
8006	u8	   retransmission_active[0x8];
8007	u8	   fec_mode_active[0x18];
8008
8009	u8	   rs_fec_correction_bypass_cap[0x4];
8010	u8	   reserved_at_84[0x8];
8011	u8	   fec_override_cap_56g[0x4];
8012	u8	   fec_override_cap_100g[0x4];
8013	u8	   fec_override_cap_50g[0x4];
8014	u8	   fec_override_cap_25g[0x4];
8015	u8	   fec_override_cap_10g_40g[0x4];
8016
8017	u8	   rs_fec_correction_bypass_admin[0x4];
8018	u8	   reserved_at_a4[0x8];
8019	u8	   fec_override_admin_56g[0x4];
8020	u8	   fec_override_admin_100g[0x4];
8021	u8	   fec_override_admin_50g[0x4];
8022	u8	   fec_override_admin_25g[0x4];
8023	u8	   fec_override_admin_10g_40g[0x4];
8024
8025	u8	   fec_override_cap_400g_8x[0x10];
8026	u8	   fec_override_cap_200g_4x[0x10];
8027	u8	   fec_override_cap_100g_2x[0x10];
8028	u8	   fec_override_cap_50g_1x[0x10];
8029
8030	u8	   fec_override_admin_400g_8x[0x10];
8031	u8	   fec_override_admin_200g_4x[0x10];
8032	u8	   fec_override_admin_100g_2x[0x10];
8033	u8	   fec_override_admin_50g_1x[0x10];
8034
8035	u8	   reserved_at_140[0xC0];
8036};
8037
8038struct mlx5_ifc_ppll_reg_bits {
8039	u8         num_pll_groups[0x8];
8040	u8         pll_group[0x8];
8041	u8         reserved_0[0x4];
8042	u8         num_plls[0x4];
8043	u8         reserved_1[0x8];
8044
8045	u8         reserved_2[0x1f];
8046	u8         ae[0x1];
8047
8048	u8         pll_status[4][0x40];
8049};
8050
8051struct mlx5_ifc_ppad_reg_bits {
8052	u8         reserved_0[0x3];
8053	u8         single_mac[0x1];
8054	u8         reserved_1[0x4];
8055	u8         local_port[0x8];
8056	u8         mac_47_32[0x10];
8057
8058	u8         mac_31_0[0x20];
8059
8060	u8         reserved_2[0x40];
8061};
8062
8063struct mlx5_ifc_pmtu_reg_bits {
8064	u8         reserved_0[0x8];
8065	u8         local_port[0x8];
8066	u8         reserved_1[0x10];
8067
8068	u8         max_mtu[0x10];
8069	u8         reserved_2[0x10];
8070
8071	u8         admin_mtu[0x10];
8072	u8         reserved_3[0x10];
8073
8074	u8         oper_mtu[0x10];
8075	u8         reserved_4[0x10];
8076};
8077
8078struct mlx5_ifc_pmpr_reg_bits {
8079	u8         reserved_0[0x8];
8080	u8         module[0x8];
8081	u8         reserved_1[0x10];
8082
8083	u8         reserved_2[0x18];
8084	u8         attenuation_5g[0x8];
8085
8086	u8         reserved_3[0x18];
8087	u8         attenuation_7g[0x8];
8088
8089	u8         reserved_4[0x18];
8090	u8         attenuation_12g[0x8];
8091};
8092
8093struct mlx5_ifc_pmpe_reg_bits {
8094	u8         reserved_0[0x8];
8095	u8         module[0x8];
8096	u8         reserved_1[0xc];
8097	u8         module_status[0x4];
8098
8099	u8         reserved_2[0x14];
8100	u8         error_type[0x4];
8101	u8         reserved_3[0x8];
8102
8103	u8         reserved_4[0x40];
8104};
8105
8106struct mlx5_ifc_pmpc_reg_bits {
8107	u8         module_state_updated[32][0x8];
8108};
8109
8110struct mlx5_ifc_pmlpn_reg_bits {
8111	u8         reserved_0[0x4];
8112	u8         mlpn_status[0x4];
8113	u8         local_port[0x8];
8114	u8         reserved_1[0x10];
8115
8116	u8         e[0x1];
8117	u8         reserved_2[0x1f];
8118};
8119
8120struct mlx5_ifc_pmlp_reg_bits {
8121	u8         rxtx[0x1];
8122	u8         reserved_0[0x7];
8123	u8         local_port[0x8];
8124	u8         reserved_1[0x8];
8125	u8         width[0x8];
8126
8127	u8         lane0_module_mapping[0x20];
8128
8129	u8         lane1_module_mapping[0x20];
8130
8131	u8         lane2_module_mapping[0x20];
8132
8133	u8         lane3_module_mapping[0x20];
8134
8135	u8         reserved_2[0x160];
8136};
8137
8138struct mlx5_ifc_pmaos_reg_bits {
8139	u8         reserved_0[0x8];
8140	u8         module[0x8];
8141	u8         reserved_1[0x4];
8142	u8         admin_status[0x4];
8143	u8         reserved_2[0x4];
8144	u8         oper_status[0x4];
8145
8146	u8         ase[0x1];
8147	u8         ee[0x1];
8148	u8         reserved_3[0x12];
8149	u8         error_type[0x4];
8150	u8         reserved_4[0x6];
8151	u8         e[0x2];
8152
8153	u8         reserved_5[0x40];
8154};
8155
8156struct mlx5_ifc_plpc_reg_bits {
8157	u8         reserved_0[0x4];
8158	u8         profile_id[0xc];
8159	u8         reserved_1[0x4];
8160	u8         proto_mask[0x4];
8161	u8         reserved_2[0x8];
8162
8163	u8         reserved_3[0x10];
8164	u8         lane_speed[0x10];
8165
8166	u8         reserved_4[0x17];
8167	u8         lpbf[0x1];
8168	u8         fec_mode_policy[0x8];
8169
8170	u8         retransmission_capability[0x8];
8171	u8         fec_mode_capability[0x18];
8172
8173	u8         retransmission_support_admin[0x8];
8174	u8         fec_mode_support_admin[0x18];
8175
8176	u8         retransmission_request_admin[0x8];
8177	u8         fec_mode_request_admin[0x18];
8178
8179	u8         reserved_5[0x80];
8180};
8181
8182struct mlx5_ifc_pll_status_data_bits {
8183	u8         reserved_0[0x1];
8184	u8         lock_cal[0x1];
8185	u8         lock_status[0x2];
8186	u8         reserved_1[0x2];
8187	u8         algo_f_ctrl[0xa];
8188	u8         analog_algo_num_var[0x6];
8189	u8         f_ctrl_measure[0xa];
8190
8191	u8         reserved_2[0x2];
8192	u8         analog_var[0x6];
8193	u8         reserved_3[0x2];
8194	u8         high_var[0x6];
8195	u8         reserved_4[0x2];
8196	u8         low_var[0x6];
8197	u8         reserved_5[0x2];
8198	u8         mid_val[0x6];
8199};
8200
8201struct mlx5_ifc_plib_reg_bits {
8202	u8         reserved_0[0x8];
8203	u8         local_port[0x8];
8204	u8         reserved_1[0x8];
8205	u8         ib_port[0x8];
8206
8207	u8         reserved_2[0x60];
8208};
8209
8210struct mlx5_ifc_plbf_reg_bits {
8211	u8         reserved_0[0x8];
8212	u8         local_port[0x8];
8213	u8         reserved_1[0xd];
8214	u8         lbf_mode[0x3];
8215
8216	u8         reserved_2[0x20];
8217};
8218
8219struct mlx5_ifc_pipg_reg_bits {
8220	u8         reserved_0[0x8];
8221	u8         local_port[0x8];
8222	u8         reserved_1[0x10];
8223
8224	u8         dic[0x1];
8225	u8         reserved_2[0x19];
8226	u8         ipg[0x4];
8227	u8         reserved_3[0x2];
8228};
8229
8230struct mlx5_ifc_pifr_reg_bits {
8231	u8         reserved_0[0x8];
8232	u8         local_port[0x8];
8233	u8         reserved_1[0x10];
8234
8235	u8         reserved_2[0xe0];
8236
8237	u8         port_filter[8][0x20];
8238
8239	u8         port_filter_update_en[8][0x20];
8240};
8241
8242struct mlx5_ifc_phys_layer_cntrs_bits {
8243	u8         time_since_last_clear_high[0x20];
8244
8245	u8         time_since_last_clear_low[0x20];
8246
8247	u8         symbol_errors_high[0x20];
8248
8249	u8         symbol_errors_low[0x20];
8250
8251	u8         sync_headers_errors_high[0x20];
8252
8253	u8         sync_headers_errors_low[0x20];
8254
8255	u8         edpl_bip_errors_lane0_high[0x20];
8256
8257	u8         edpl_bip_errors_lane0_low[0x20];
8258
8259	u8         edpl_bip_errors_lane1_high[0x20];
8260
8261	u8         edpl_bip_errors_lane1_low[0x20];
8262
8263	u8         edpl_bip_errors_lane2_high[0x20];
8264
8265	u8         edpl_bip_errors_lane2_low[0x20];
8266
8267	u8         edpl_bip_errors_lane3_high[0x20];
8268
8269	u8         edpl_bip_errors_lane3_low[0x20];
8270
8271	u8         fc_fec_corrected_blocks_lane0_high[0x20];
8272
8273	u8         fc_fec_corrected_blocks_lane0_low[0x20];
8274
8275	u8         fc_fec_corrected_blocks_lane1_high[0x20];
8276
8277	u8         fc_fec_corrected_blocks_lane1_low[0x20];
8278
8279	u8         fc_fec_corrected_blocks_lane2_high[0x20];
8280
8281	u8         fc_fec_corrected_blocks_lane2_low[0x20];
8282
8283	u8         fc_fec_corrected_blocks_lane3_high[0x20];
8284
8285	u8         fc_fec_corrected_blocks_lane3_low[0x20];
8286
8287	u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
8288
8289	u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
8290
8291	u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
8292
8293	u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
8294
8295	u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
8296
8297	u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
8298
8299	u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
8300
8301	u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
8302
8303	u8         rs_fec_corrected_blocks_high[0x20];
8304
8305	u8         rs_fec_corrected_blocks_low[0x20];
8306
8307	u8         rs_fec_uncorrectable_blocks_high[0x20];
8308
8309	u8         rs_fec_uncorrectable_blocks_low[0x20];
8310
8311	u8         rs_fec_no_errors_blocks_high[0x20];
8312
8313	u8         rs_fec_no_errors_blocks_low[0x20];
8314
8315	u8         rs_fec_single_error_blocks_high[0x20];
8316
8317	u8         rs_fec_single_error_blocks_low[0x20];
8318
8319	u8         rs_fec_corrected_symbols_total_high[0x20];
8320
8321	u8         rs_fec_corrected_symbols_total_low[0x20];
8322
8323	u8         rs_fec_corrected_symbols_lane0_high[0x20];
8324
8325	u8         rs_fec_corrected_symbols_lane0_low[0x20];
8326
8327	u8         rs_fec_corrected_symbols_lane1_high[0x20];
8328
8329	u8         rs_fec_corrected_symbols_lane1_low[0x20];
8330
8331	u8         rs_fec_corrected_symbols_lane2_high[0x20];
8332
8333	u8         rs_fec_corrected_symbols_lane2_low[0x20];
8334
8335	u8         rs_fec_corrected_symbols_lane3_high[0x20];
8336
8337	u8         rs_fec_corrected_symbols_lane3_low[0x20];
8338
8339	u8         link_down_events[0x20];
8340
8341	u8         successful_recovery_events[0x20];
8342
8343	u8         reserved_0[0x180];
8344};
8345
8346struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
8347	u8	   symbol_error_counter[0x10];
8348
8349	u8         link_error_recovery_counter[0x8];
8350
8351	u8         link_downed_counter[0x8];
8352
8353	u8         port_rcv_errors[0x10];
8354
8355	u8         port_rcv_remote_physical_errors[0x10];
8356
8357	u8         port_rcv_switch_relay_errors[0x10];
8358
8359	u8         port_xmit_discards[0x10];
8360
8361	u8         port_xmit_constraint_errors[0x8];
8362
8363	u8         port_rcv_constraint_errors[0x8];
8364
8365	u8         reserved_at_70[0x8];
8366
8367	u8         link_overrun_errors[0x8];
8368
8369	u8	   reserved_at_80[0x10];
8370
8371	u8         vl_15_dropped[0x10];
8372
8373	u8	   reserved_at_a0[0xa0];
8374};
8375
8376struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
8377	u8         time_since_last_clear_high[0x20];
8378
8379	u8         time_since_last_clear_low[0x20];
8380
8381	u8         phy_received_bits_high[0x20];
8382
8383	u8         phy_received_bits_low[0x20];
8384
8385	u8         phy_symbol_errors_high[0x20];
8386
8387	u8         phy_symbol_errors_low[0x20];
8388
8389	u8         phy_corrected_bits_high[0x20];
8390
8391	u8         phy_corrected_bits_low[0x20];
8392
8393	u8         phy_corrected_bits_lane0_high[0x20];
8394
8395	u8         phy_corrected_bits_lane0_low[0x20];
8396
8397	u8         phy_corrected_bits_lane1_high[0x20];
8398
8399	u8         phy_corrected_bits_lane1_low[0x20];
8400
8401	u8         phy_corrected_bits_lane2_high[0x20];
8402
8403	u8         phy_corrected_bits_lane2_low[0x20];
8404
8405	u8         phy_corrected_bits_lane3_high[0x20];
8406
8407	u8         phy_corrected_bits_lane3_low[0x20];
8408
8409	u8         reserved_at_200[0x5c0];
8410};
8411
8412struct mlx5_ifc_infiniband_port_cntrs_bits {
8413	u8         symbol_error_counter[0x10];
8414	u8         link_error_recovery_counter[0x8];
8415	u8         link_downed_counter[0x8];
8416
8417	u8         port_rcv_errors[0x10];
8418	u8         port_rcv_remote_physical_errors[0x10];
8419
8420	u8         port_rcv_switch_relay_errors[0x10];
8421	u8         port_xmit_discards[0x10];
8422
8423	u8         port_xmit_constraint_errors[0x8];
8424	u8         port_rcv_constraint_errors[0x8];
8425	u8         reserved_0[0x8];
8426	u8         local_link_integrity_errors[0x4];
8427	u8         excessive_buffer_overrun_errors[0x4];
8428
8429	u8         reserved_1[0x10];
8430	u8         vl_15_dropped[0x10];
8431
8432	u8         port_xmit_data[0x20];
8433
8434	u8         port_rcv_data[0x20];
8435
8436	u8         port_xmit_pkts[0x20];
8437
8438	u8         port_rcv_pkts[0x20];
8439
8440	u8         port_xmit_wait[0x20];
8441
8442	u8         reserved_2[0x680];
8443};
8444
8445struct mlx5_ifc_phrr_reg_bits {
8446	u8         clr[0x1];
8447	u8         reserved_0[0x7];
8448	u8         local_port[0x8];
8449	u8         reserved_1[0x10];
8450
8451	u8         hist_group[0x8];
8452	u8         reserved_2[0x10];
8453	u8         hist_id[0x8];
8454
8455	u8         reserved_3[0x40];
8456
8457	u8         time_since_last_clear_high[0x20];
8458
8459	u8         time_since_last_clear_low[0x20];
8460
8461	u8         bin[10][0x20];
8462};
8463
8464struct mlx5_ifc_phbr_for_prio_reg_bits {
8465	u8         reserved_0[0x18];
8466	u8         prio[0x8];
8467};
8468
8469struct mlx5_ifc_phbr_for_port_tclass_reg_bits {
8470	u8         reserved_0[0x18];
8471	u8         tclass[0x8];
8472};
8473
8474struct mlx5_ifc_phbr_binding_reg_bits {
8475	u8         opcode[0x4];
8476	u8         reserved_0[0x4];
8477	u8         local_port[0x8];
8478	u8         pnat[0x2];
8479	u8         reserved_1[0xe];
8480
8481	u8         hist_group[0x8];
8482	u8         reserved_2[0x10];
8483	u8         hist_id[0x8];
8484
8485	u8         reserved_3[0x10];
8486	u8         hist_type[0x10];
8487
8488	u8         hist_parameters[0x20];
8489
8490	u8         hist_min_value[0x20];
8491
8492	u8         hist_max_value[0x20];
8493
8494	u8         sample_time[0x20];
8495};
8496
8497enum {
8498	MLX5_PFCC_REG_PPAN_DISABLED  = 0x0,
8499	MLX5_PFCC_REG_PPAN_ENABLED   = 0x1,
8500};
8501
8502struct mlx5_ifc_pfcc_reg_bits {
8503	u8         dcbx_operation_type[0x2];
8504	u8         cap_local_admin[0x1];
8505	u8         cap_remote_admin[0x1];
8506	u8         reserved_0[0x4];
8507	u8         local_port[0x8];
8508	u8         pnat[0x2];
8509	u8         reserved_1[0xc];
8510	u8         shl_cap[0x1];
8511	u8         shl_opr[0x1];
8512
8513	u8         ppan[0x4];
8514	u8         reserved_2[0x4];
8515	u8         prio_mask_tx[0x8];
8516	u8         reserved_3[0x8];
8517	u8         prio_mask_rx[0x8];
8518
8519	u8         pptx[0x1];
8520	u8         aptx[0x1];
8521	u8         reserved_4[0x6];
8522	u8         pfctx[0x8];
8523	u8         reserved_5[0x8];
8524	u8         cbftx[0x8];
8525
8526	u8         pprx[0x1];
8527	u8         aprx[0x1];
8528	u8         reserved_6[0x6];
8529	u8         pfcrx[0x8];
8530	u8         reserved_7[0x8];
8531	u8         cbfrx[0x8];
8532
8533	u8         device_stall_minor_watermark[0x10];
8534	u8         device_stall_critical_watermark[0x10];
8535
8536	u8         reserved_8[0x60];
8537};
8538
8539struct mlx5_ifc_pelc_reg_bits {
8540	u8         op[0x4];
8541	u8         reserved_0[0x4];
8542	u8         local_port[0x8];
8543	u8         reserved_1[0x10];
8544
8545	u8         op_admin[0x8];
8546	u8         op_capability[0x8];
8547	u8         op_request[0x8];
8548	u8         op_active[0x8];
8549
8550	u8         admin[0x40];
8551
8552	u8         capability[0x40];
8553
8554	u8         request[0x40];
8555
8556	u8         active[0x40];
8557
8558	u8         reserved_2[0x80];
8559};
8560
8561struct mlx5_ifc_peir_reg_bits {
8562	u8         reserved_0[0x8];
8563	u8         local_port[0x8];
8564	u8         reserved_1[0x10];
8565
8566	u8         reserved_2[0xc];
8567	u8         error_count[0x4];
8568	u8         reserved_3[0x10];
8569
8570	u8         reserved_4[0xc];
8571	u8         lane[0x4];
8572	u8         reserved_5[0x8];
8573	u8         error_type[0x8];
8574};
8575
8576struct mlx5_ifc_qcam_access_reg_cap_mask {
8577	u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
8578	u8         qpdpm[0x1];
8579	u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
8580	u8         qdpm[0x1];
8581	u8         qpts[0x1];
8582	u8         qcap[0x1];
8583	u8         qcam_access_reg_cap_mask_0[0x1];
8584};
8585
8586struct mlx5_ifc_qcam_qos_feature_cap_mask {
8587	u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
8588	u8         qpts_trust_both[0x1];
8589};
8590
8591struct mlx5_ifc_qcam_reg_bits {
8592	u8         reserved_at_0[0x8];
8593	u8         feature_group[0x8];
8594	u8         reserved_at_10[0x8];
8595	u8         access_reg_group[0x8];
8596	u8         reserved_at_20[0x20];
8597
8598	union {
8599		struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8600		u8  reserved_at_0[0x80];
8601	} qos_access_reg_cap_mask;
8602
8603	u8         reserved_at_c0[0x80];
8604
8605	union {
8606		struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8607		u8  reserved_at_0[0x80];
8608	} qos_feature_cap_mask;
8609
8610	u8         reserved_at_1c0[0x80];
8611};
8612
8613struct mlx5_ifc_pcam_enhanced_features_bits {
8614	u8         reserved_at_0[0x6d];
8615	u8         rx_icrc_encapsulated_counter[0x1];
8616	u8	   reserved_at_6e[0x4];
8617	u8         ptys_extended_ethernet[0x1];
8618	u8	   reserved_at_73[0x3];
8619	u8         pfcc_mask[0x1];
8620	u8         reserved_at_77[0x3];
8621	u8         per_lane_error_counters[0x1];
8622	u8         rx_buffer_fullness_counters[0x1];
8623	u8         ptys_connector_type[0x1];
8624	u8         reserved_at_7d[0x1];
8625	u8         ppcnt_discard_group[0x1];
8626	u8         ppcnt_statistical_group[0x1];
8627};
8628
8629struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8630	u8         port_access_reg_cap_mask_127_to_96[0x20];
8631	u8         port_access_reg_cap_mask_95_to_64[0x20];
8632
8633	u8         port_access_reg_cap_mask_63_to_36[0x1c];
8634	u8         pplm[0x1];
8635	u8         port_access_reg_cap_mask_34_to_32[0x3];
8636
8637	u8         port_access_reg_cap_mask_31_to_13[0x13];
8638	u8         pbmc[0x1];
8639	u8         pptb[0x1];
8640	u8         port_access_reg_cap_mask_10_to_09[0x2];
8641	u8         ppcnt[0x1];
8642	u8         port_access_reg_cap_mask_07_to_00[0x8];
8643};
8644
8645struct mlx5_ifc_pcam_reg_bits {
8646	u8         reserved_at_0[0x8];
8647	u8         feature_group[0x8];
8648	u8         reserved_at_10[0x8];
8649	u8         access_reg_group[0x8];
8650
8651	u8         reserved_at_20[0x20];
8652
8653	union {
8654		struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8655		u8         reserved_at_0[0x80];
8656	} port_access_reg_cap_mask;
8657
8658	u8         reserved_at_c0[0x80];
8659
8660	union {
8661		struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8662		u8         reserved_at_0[0x80];
8663	} feature_cap_mask;
8664
8665	u8         reserved_at_1c0[0xc0];
8666};
8667
8668struct mlx5_ifc_mcam_enhanced_features_bits {
8669	u8         reserved_at_0[0x6e];
8670	u8         pcie_status_and_power[0x1];
8671	u8         reserved_at_111[0x10];
8672	u8         pcie_performance_group[0x1];
8673};
8674
8675struct mlx5_ifc_mcam_access_reg_bits {
8676	u8         reserved_at_0[0x1c];
8677	u8         mcda[0x1];
8678	u8         mcc[0x1];
8679	u8         mcqi[0x1];
8680	u8         reserved_at_1f[0x1];
8681
8682	u8         regs_95_to_64[0x20];
8683	u8         regs_63_to_32[0x20];
8684	u8         regs_31_to_0[0x20];
8685};
8686
8687struct mlx5_ifc_mcam_reg_bits {
8688	u8         reserved_at_0[0x8];
8689	u8         feature_group[0x8];
8690	u8         reserved_at_10[0x8];
8691	u8         access_reg_group[0x8];
8692
8693	u8         reserved_at_20[0x20];
8694
8695	union {
8696		struct mlx5_ifc_mcam_access_reg_bits access_regs;
8697		u8         reserved_at_0[0x80];
8698	} mng_access_reg_cap_mask;
8699
8700	u8         reserved_at_c0[0x80];
8701
8702	union {
8703		struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8704		u8         reserved_at_0[0x80];
8705	} mng_feature_cap_mask;
8706
8707	u8         reserved_at_1c0[0x80];
8708};
8709
8710struct mlx5_ifc_pcap_reg_bits {
8711	u8         reserved_0[0x8];
8712	u8         local_port[0x8];
8713	u8         reserved_1[0x10];
8714
8715	u8         port_capability_mask[4][0x20];
8716};
8717
8718struct mlx5_ifc_pbmc_reg_bits {
8719	u8         reserved_at_0[0x8];
8720	u8         local_port[0x8];
8721	u8         reserved_at_10[0x10];
8722
8723	u8         xoff_timer_value[0x10];
8724	u8         xoff_refresh[0x10];
8725
8726	u8         reserved_at_40[0x9];
8727	u8         fullness_threshold[0x7];
8728	u8         port_buffer_size[0x10];
8729
8730	struct mlx5_ifc_bufferx_reg_bits buffer[10];
8731
8732	u8         reserved_at_2e0[0x40];
8733};
8734
8735struct mlx5_ifc_paos_reg_bits {
8736	u8         swid[0x8];
8737	u8         local_port[0x8];
8738	u8         reserved_0[0x4];
8739	u8         admin_status[0x4];
8740	u8         reserved_1[0x4];
8741	u8         oper_status[0x4];
8742
8743	u8         ase[0x1];
8744	u8         ee[0x1];
8745	u8         reserved_2[0x1c];
8746	u8         e[0x2];
8747
8748	u8         reserved_3[0x40];
8749};
8750
8751struct mlx5_ifc_pamp_reg_bits {
8752	u8         reserved_0[0x8];
8753	u8         opamp_group[0x8];
8754	u8         reserved_1[0xc];
8755	u8         opamp_group_type[0x4];
8756
8757	u8         start_index[0x10];
8758	u8         reserved_2[0x4];
8759	u8         num_of_indices[0xc];
8760
8761	u8         index_data[18][0x10];
8762};
8763
8764struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits {
8765	u8         llr_rx_cells_high[0x20];
8766
8767	u8         llr_rx_cells_low[0x20];
8768
8769	u8         llr_rx_error_high[0x20];
8770
8771	u8         llr_rx_error_low[0x20];
8772
8773	u8         llr_rx_crc_error_high[0x20];
8774
8775	u8         llr_rx_crc_error_low[0x20];
8776
8777	u8         llr_tx_cells_high[0x20];
8778
8779	u8         llr_tx_cells_low[0x20];
8780
8781	u8         llr_tx_ret_cells_high[0x20];
8782
8783	u8         llr_tx_ret_cells_low[0x20];
8784
8785	u8         llr_tx_ret_events_high[0x20];
8786
8787	u8         llr_tx_ret_events_low[0x20];
8788
8789	u8         reserved_0[0x640];
8790};
8791
8792struct mlx5_ifc_mtmp_reg_bits {
8793	u8         i[0x1];
8794	u8         reserved_at_1[0x18];
8795	u8         sensor_index[0x7];
8796
8797	u8         reserved_at_20[0x10];
8798	u8         temperature[0x10];
8799
8800	u8         mte[0x1];
8801	u8         mtr[0x1];
8802	u8         reserved_at_42[0x0e];
8803	u8         max_temperature[0x10];
8804
8805	u8         tee[0x2];
8806	u8         reserved_at_62[0x0e];
8807	u8         temperature_threshold_hi[0x10];
8808
8809	u8         reserved_at_80[0x10];
8810	u8         temperature_threshold_lo[0x10];
8811
8812	u8         reserved_at_100[0x20];
8813
8814	u8         sensor_name[0x40];
8815};
8816
8817struct mlx5_ifc_lane_2_module_mapping_bits {
8818	u8         reserved_0[0x6];
8819	u8         rx_lane[0x2];
8820	u8         reserved_1[0x6];
8821	u8         tx_lane[0x2];
8822	u8         reserved_2[0x8];
8823	u8         module[0x8];
8824};
8825
8826struct mlx5_ifc_eth_per_traffic_class_layout_bits {
8827	u8         transmit_queue_high[0x20];
8828
8829	u8         transmit_queue_low[0x20];
8830
8831	u8         reserved_0[0x780];
8832};
8833
8834struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits {
8835	u8         no_buffer_discard_uc_high[0x20];
8836
8837	u8         no_buffer_discard_uc_low[0x20];
8838
8839	u8         wred_discard_high[0x20];
8840
8841	u8         wred_discard_low[0x20];
8842
8843	u8         reserved_0[0x740];
8844};
8845
8846struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
8847	u8         rx_octets_high[0x20];
8848
8849	u8         rx_octets_low[0x20];
8850
8851	u8         reserved_0[0xc0];
8852
8853	u8         rx_frames_high[0x20];
8854
8855	u8         rx_frames_low[0x20];
8856
8857	u8         tx_octets_high[0x20];
8858
8859	u8         tx_octets_low[0x20];
8860
8861	u8         reserved_1[0xc0];
8862
8863	u8         tx_frames_high[0x20];
8864
8865	u8         tx_frames_low[0x20];
8866
8867	u8         rx_pause_high[0x20];
8868
8869	u8         rx_pause_low[0x20];
8870
8871	u8         rx_pause_duration_high[0x20];
8872
8873	u8         rx_pause_duration_low[0x20];
8874
8875	u8         tx_pause_high[0x20];
8876
8877	u8         tx_pause_low[0x20];
8878
8879	u8         tx_pause_duration_high[0x20];
8880
8881	u8         tx_pause_duration_low[0x20];
8882
8883	u8         rx_pause_transition_high[0x20];
8884
8885	u8         rx_pause_transition_low[0x20];
8886
8887	u8         rx_discards_high[0x20];
8888
8889	u8         rx_discards_low[0x20];
8890
8891	u8         device_stall_minor_watermark_cnt_high[0x20];
8892
8893	u8         device_stall_minor_watermark_cnt_low[0x20];
8894
8895	u8         device_stall_critical_watermark_cnt_high[0x20];
8896
8897	u8         device_stall_critical_watermark_cnt_low[0x20];
8898
8899	u8         reserved_2[0x340];
8900};
8901
8902struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
8903	u8         port_transmit_wait_high[0x20];
8904
8905	u8         port_transmit_wait_low[0x20];
8906
8907	u8         ecn_marked_high[0x20];
8908
8909	u8         ecn_marked_low[0x20];
8910
8911	u8         no_buffer_discard_mc_high[0x20];
8912
8913	u8         no_buffer_discard_mc_low[0x20];
8914
8915	u8         rx_ebp_high[0x20];
8916
8917	u8         rx_ebp_low[0x20];
8918
8919	u8         tx_ebp_high[0x20];
8920
8921	u8         tx_ebp_low[0x20];
8922
8923        u8         rx_buffer_almost_full_high[0x20];
8924
8925        u8         rx_buffer_almost_full_low[0x20];
8926
8927        u8         rx_buffer_full_high[0x20];
8928
8929        u8         rx_buffer_full_low[0x20];
8930
8931        u8         rx_icrc_encapsulated_high[0x20];
8932
8933        u8         rx_icrc_encapsulated_low[0x20];
8934
8935	u8         reserved_0[0x80];
8936
8937        u8         tx_stats_pkts64octets_high[0x20];
8938
8939        u8         tx_stats_pkts64octets_low[0x20];
8940
8941        u8         tx_stats_pkts65to127octets_high[0x20];
8942
8943        u8         tx_stats_pkts65to127octets_low[0x20];
8944
8945        u8         tx_stats_pkts128to255octets_high[0x20];
8946
8947        u8         tx_stats_pkts128to255octets_low[0x20];
8948
8949        u8         tx_stats_pkts256to511octets_high[0x20];
8950
8951        u8         tx_stats_pkts256to511octets_low[0x20];
8952
8953        u8         tx_stats_pkts512to1023octets_high[0x20];
8954
8955        u8         tx_stats_pkts512to1023octets_low[0x20];
8956
8957        u8         tx_stats_pkts1024to1518octets_high[0x20];
8958
8959        u8         tx_stats_pkts1024to1518octets_low[0x20];
8960
8961        u8         tx_stats_pkts1519to2047octets_high[0x20];
8962
8963        u8         tx_stats_pkts1519to2047octets_low[0x20];
8964
8965        u8         tx_stats_pkts2048to4095octets_high[0x20];
8966
8967        u8         tx_stats_pkts2048to4095octets_low[0x20];
8968
8969        u8         tx_stats_pkts4096to8191octets_high[0x20];
8970
8971        u8         tx_stats_pkts4096to8191octets_low[0x20];
8972
8973        u8         tx_stats_pkts8192to10239octets_high[0x20];
8974
8975        u8         tx_stats_pkts8192to10239octets_low[0x20];
8976
8977	u8         reserved_1[0x2C0];
8978};
8979
8980struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
8981	u8         a_frames_transmitted_ok_high[0x20];
8982
8983	u8         a_frames_transmitted_ok_low[0x20];
8984
8985	u8         a_frames_received_ok_high[0x20];
8986
8987	u8         a_frames_received_ok_low[0x20];
8988
8989	u8         a_frame_check_sequence_errors_high[0x20];
8990
8991	u8         a_frame_check_sequence_errors_low[0x20];
8992
8993	u8         a_alignment_errors_high[0x20];
8994
8995	u8         a_alignment_errors_low[0x20];
8996
8997	u8         a_octets_transmitted_ok_high[0x20];
8998
8999	u8         a_octets_transmitted_ok_low[0x20];
9000
9001	u8         a_octets_received_ok_high[0x20];
9002
9003	u8         a_octets_received_ok_low[0x20];
9004
9005	u8         a_multicast_frames_xmitted_ok_high[0x20];
9006
9007	u8         a_multicast_frames_xmitted_ok_low[0x20];
9008
9009	u8         a_broadcast_frames_xmitted_ok_high[0x20];
9010
9011	u8         a_broadcast_frames_xmitted_ok_low[0x20];
9012
9013	u8         a_multicast_frames_received_ok_high[0x20];
9014
9015	u8         a_multicast_frames_received_ok_low[0x20];
9016
9017	u8         a_broadcast_frames_recieved_ok_high[0x20];
9018
9019	u8         a_broadcast_frames_recieved_ok_low[0x20];
9020
9021	u8         a_in_range_length_errors_high[0x20];
9022
9023	u8         a_in_range_length_errors_low[0x20];
9024
9025	u8         a_out_of_range_length_field_high[0x20];
9026
9027	u8         a_out_of_range_length_field_low[0x20];
9028
9029	u8         a_frame_too_long_errors_high[0x20];
9030
9031	u8         a_frame_too_long_errors_low[0x20];
9032
9033	u8         a_symbol_error_during_carrier_high[0x20];
9034
9035	u8         a_symbol_error_during_carrier_low[0x20];
9036
9037	u8         a_mac_control_frames_transmitted_high[0x20];
9038
9039	u8         a_mac_control_frames_transmitted_low[0x20];
9040
9041	u8         a_mac_control_frames_received_high[0x20];
9042
9043	u8         a_mac_control_frames_received_low[0x20];
9044
9045	u8         a_unsupported_opcodes_received_high[0x20];
9046
9047	u8         a_unsupported_opcodes_received_low[0x20];
9048
9049	u8         a_pause_mac_ctrl_frames_received_high[0x20];
9050
9051	u8         a_pause_mac_ctrl_frames_received_low[0x20];
9052
9053	u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
9054
9055	u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
9056
9057	u8         reserved_0[0x300];
9058};
9059
9060struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
9061	u8         dot3stats_alignment_errors_high[0x20];
9062
9063	u8         dot3stats_alignment_errors_low[0x20];
9064
9065	u8         dot3stats_fcs_errors_high[0x20];
9066
9067	u8         dot3stats_fcs_errors_low[0x20];
9068
9069	u8         dot3stats_single_collision_frames_high[0x20];
9070
9071	u8         dot3stats_single_collision_frames_low[0x20];
9072
9073	u8         dot3stats_multiple_collision_frames_high[0x20];
9074
9075	u8         dot3stats_multiple_collision_frames_low[0x20];
9076
9077	u8         dot3stats_sqe_test_errors_high[0x20];
9078
9079	u8         dot3stats_sqe_test_errors_low[0x20];
9080
9081	u8         dot3stats_deferred_transmissions_high[0x20];
9082
9083	u8         dot3stats_deferred_transmissions_low[0x20];
9084
9085	u8         dot3stats_late_collisions_high[0x20];
9086
9087	u8         dot3stats_late_collisions_low[0x20];
9088
9089	u8         dot3stats_excessive_collisions_high[0x20];
9090
9091	u8         dot3stats_excessive_collisions_low[0x20];
9092
9093	u8         dot3stats_internal_mac_transmit_errors_high[0x20];
9094
9095	u8         dot3stats_internal_mac_transmit_errors_low[0x20];
9096
9097	u8         dot3stats_carrier_sense_errors_high[0x20];
9098
9099	u8         dot3stats_carrier_sense_errors_low[0x20];
9100
9101	u8         dot3stats_frame_too_longs_high[0x20];
9102
9103	u8         dot3stats_frame_too_longs_low[0x20];
9104
9105	u8         dot3stats_internal_mac_receive_errors_high[0x20];
9106
9107	u8         dot3stats_internal_mac_receive_errors_low[0x20];
9108
9109	u8         dot3stats_symbol_errors_high[0x20];
9110
9111	u8         dot3stats_symbol_errors_low[0x20];
9112
9113	u8         dot3control_in_unknown_opcodes_high[0x20];
9114
9115	u8         dot3control_in_unknown_opcodes_low[0x20];
9116
9117	u8         dot3in_pause_frames_high[0x20];
9118
9119	u8         dot3in_pause_frames_low[0x20];
9120
9121	u8         dot3out_pause_frames_high[0x20];
9122
9123	u8         dot3out_pause_frames_low[0x20];
9124
9125	u8         reserved_0[0x3c0];
9126};
9127
9128struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
9129	u8         if_in_octets_high[0x20];
9130
9131	u8         if_in_octets_low[0x20];
9132
9133	u8         if_in_ucast_pkts_high[0x20];
9134
9135	u8         if_in_ucast_pkts_low[0x20];
9136
9137	u8         if_in_discards_high[0x20];
9138
9139	u8         if_in_discards_low[0x20];
9140
9141	u8         if_in_errors_high[0x20];
9142
9143	u8         if_in_errors_low[0x20];
9144
9145	u8         if_in_unknown_protos_high[0x20];
9146
9147	u8         if_in_unknown_protos_low[0x20];
9148
9149	u8         if_out_octets_high[0x20];
9150
9151	u8         if_out_octets_low[0x20];
9152
9153	u8         if_out_ucast_pkts_high[0x20];
9154
9155	u8         if_out_ucast_pkts_low[0x20];
9156
9157	u8         if_out_discards_high[0x20];
9158
9159	u8         if_out_discards_low[0x20];
9160
9161	u8         if_out_errors_high[0x20];
9162
9163	u8         if_out_errors_low[0x20];
9164
9165	u8         if_in_multicast_pkts_high[0x20];
9166
9167	u8         if_in_multicast_pkts_low[0x20];
9168
9169	u8         if_in_broadcast_pkts_high[0x20];
9170
9171	u8         if_in_broadcast_pkts_low[0x20];
9172
9173	u8         if_out_multicast_pkts_high[0x20];
9174
9175	u8         if_out_multicast_pkts_low[0x20];
9176
9177	u8         if_out_broadcast_pkts_high[0x20];
9178
9179	u8         if_out_broadcast_pkts_low[0x20];
9180
9181	u8         reserved_0[0x480];
9182};
9183
9184struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
9185	u8         ether_stats_drop_events_high[0x20];
9186
9187	u8         ether_stats_drop_events_low[0x20];
9188
9189	u8         ether_stats_octets_high[0x20];
9190
9191	u8         ether_stats_octets_low[0x20];
9192
9193	u8         ether_stats_pkts_high[0x20];
9194
9195	u8         ether_stats_pkts_low[0x20];
9196
9197	u8         ether_stats_broadcast_pkts_high[0x20];
9198
9199	u8         ether_stats_broadcast_pkts_low[0x20];
9200
9201	u8         ether_stats_multicast_pkts_high[0x20];
9202
9203	u8         ether_stats_multicast_pkts_low[0x20];
9204
9205	u8         ether_stats_crc_align_errors_high[0x20];
9206
9207	u8         ether_stats_crc_align_errors_low[0x20];
9208
9209	u8         ether_stats_undersize_pkts_high[0x20];
9210
9211	u8         ether_stats_undersize_pkts_low[0x20];
9212
9213	u8         ether_stats_oversize_pkts_high[0x20];
9214
9215	u8         ether_stats_oversize_pkts_low[0x20];
9216
9217	u8         ether_stats_fragments_high[0x20];
9218
9219	u8         ether_stats_fragments_low[0x20];
9220
9221	u8         ether_stats_jabbers_high[0x20];
9222
9223	u8         ether_stats_jabbers_low[0x20];
9224
9225	u8         ether_stats_collisions_high[0x20];
9226
9227	u8         ether_stats_collisions_low[0x20];
9228
9229	u8         ether_stats_pkts64octets_high[0x20];
9230
9231	u8         ether_stats_pkts64octets_low[0x20];
9232
9233	u8         ether_stats_pkts65to127octets_high[0x20];
9234
9235	u8         ether_stats_pkts65to127octets_low[0x20];
9236
9237	u8         ether_stats_pkts128to255octets_high[0x20];
9238
9239	u8         ether_stats_pkts128to255octets_low[0x20];
9240
9241	u8         ether_stats_pkts256to511octets_high[0x20];
9242
9243	u8         ether_stats_pkts256to511octets_low[0x20];
9244
9245	u8         ether_stats_pkts512to1023octets_high[0x20];
9246
9247	u8         ether_stats_pkts512to1023octets_low[0x20];
9248
9249	u8         ether_stats_pkts1024to1518octets_high[0x20];
9250
9251	u8         ether_stats_pkts1024to1518octets_low[0x20];
9252
9253	u8         ether_stats_pkts1519to2047octets_high[0x20];
9254
9255	u8         ether_stats_pkts1519to2047octets_low[0x20];
9256
9257	u8         ether_stats_pkts2048to4095octets_high[0x20];
9258
9259	u8         ether_stats_pkts2048to4095octets_low[0x20];
9260
9261	u8         ether_stats_pkts4096to8191octets_high[0x20];
9262
9263	u8         ether_stats_pkts4096to8191octets_low[0x20];
9264
9265	u8         ether_stats_pkts8192to10239octets_high[0x20];
9266
9267	u8         ether_stats_pkts8192to10239octets_low[0x20];
9268
9269	u8         reserved_0[0x280];
9270};
9271
9272struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits {
9273	u8         symbol_error_counter[0x10];
9274	u8         link_error_recovery_counter[0x8];
9275	u8         link_downed_counter[0x8];
9276
9277	u8         port_rcv_errors[0x10];
9278	u8         port_rcv_remote_physical_errors[0x10];
9279
9280	u8         port_rcv_switch_relay_errors[0x10];
9281	u8         port_xmit_discards[0x10];
9282
9283	u8         port_xmit_constraint_errors[0x8];
9284	u8         port_rcv_constraint_errors[0x8];
9285	u8         reserved_0[0x8];
9286	u8         local_link_integrity_errors[0x4];
9287	u8         excessive_buffer_overrun_errors[0x4];
9288
9289	u8         reserved_1[0x10];
9290	u8         vl_15_dropped[0x10];
9291
9292	u8         port_xmit_data[0x20];
9293
9294	u8         port_rcv_data[0x20];
9295
9296	u8         port_xmit_pkts[0x20];
9297
9298	u8         port_rcv_pkts[0x20];
9299
9300	u8         port_xmit_wait[0x20];
9301
9302	u8         reserved_2[0x680];
9303};
9304
9305struct mlx5_ifc_trc_tlb_reg_bits {
9306	u8         reserved_0[0x80];
9307
9308	u8         tlb_addr[0][0x40];
9309};
9310
9311struct mlx5_ifc_trc_read_fifo_reg_bits {
9312	u8         reserved_0[0x10];
9313	u8         requested_event_num[0x10];
9314
9315	u8         reserved_1[0x20];
9316
9317	u8         reserved_2[0x10];
9318	u8         acual_event_num[0x10];
9319
9320	u8         reserved_3[0x20];
9321
9322	u8         event[0][0x40];
9323};
9324
9325struct mlx5_ifc_trc_lock_reg_bits {
9326	u8         reserved_0[0x1f];
9327	u8         lock[0x1];
9328
9329	u8         reserved_1[0x60];
9330};
9331
9332struct mlx5_ifc_trc_filter_reg_bits {
9333	u8         status[0x1];
9334	u8         reserved_0[0xf];
9335	u8         filter_index[0x10];
9336
9337	u8         reserved_1[0x20];
9338
9339	u8         filter_val[0x20];
9340
9341	u8         reserved_2[0x1a0];
9342};
9343
9344struct mlx5_ifc_trc_event_reg_bits {
9345	u8         status[0x1];
9346	u8         reserved_0[0xf];
9347	u8         event_index[0x10];
9348
9349	u8         reserved_1[0x20];
9350
9351	u8         event_id[0x20];
9352
9353	u8         event_selector_val[0x10];
9354	u8         event_selector_size[0x10];
9355
9356	u8         reserved_2[0x180];
9357};
9358
9359struct mlx5_ifc_trc_conf_reg_bits {
9360	u8         limit_en[0x1];
9361	u8         reserved_0[0x3];
9362	u8         dump_mode[0x4];
9363	u8         reserved_1[0x15];
9364	u8         state[0x3];
9365
9366	u8         reserved_2[0x20];
9367
9368	u8         limit_event_index[0x20];
9369
9370	u8         mkey[0x20];
9371
9372	u8         fifo_ready_ev_num[0x20];
9373
9374	u8         reserved_3[0x160];
9375};
9376
9377struct mlx5_ifc_trc_cap_reg_bits {
9378	u8         reserved_0[0x18];
9379	u8         dump_mode[0x8];
9380
9381	u8         reserved_1[0x20];
9382
9383	u8         num_of_events[0x10];
9384	u8         num_of_filters[0x10];
9385
9386	u8         fifo_size[0x20];
9387
9388	u8         tlb_size[0x10];
9389	u8         event_size[0x10];
9390
9391	u8         reserved_2[0x160];
9392};
9393
9394struct mlx5_ifc_set_node_in_bits {
9395	u8         node_description[64][0x8];
9396};
9397
9398struct mlx5_ifc_register_power_settings_bits {
9399	u8         reserved_0[0x18];
9400	u8         power_settings_level[0x8];
9401
9402	u8         reserved_1[0x60];
9403};
9404
9405struct mlx5_ifc_register_host_endianess_bits {
9406	u8         he[0x1];
9407	u8         reserved_0[0x1f];
9408
9409	u8         reserved_1[0x60];
9410};
9411
9412struct mlx5_ifc_register_diag_buffer_ctrl_bits {
9413	u8         physical_address[0x40];
9414};
9415
9416struct mlx5_ifc_qtct_reg_bits {
9417	u8         operation_type[0x2];
9418	u8         cap_local_admin[0x1];
9419	u8         cap_remote_admin[0x1];
9420	u8         reserved_0[0x4];
9421	u8         port_number[0x8];
9422	u8         reserved_1[0xd];
9423	u8         prio[0x3];
9424
9425	u8         reserved_2[0x1d];
9426	u8         tclass[0x3];
9427};
9428
9429struct mlx5_ifc_qpdp_reg_bits {
9430	u8         reserved_0[0x8];
9431	u8         port_number[0x8];
9432	u8         reserved_1[0x10];
9433
9434	u8         reserved_2[0x1d];
9435	u8         pprio[0x3];
9436};
9437
9438struct mlx5_ifc_port_info_ro_fields_param_bits {
9439	u8         reserved_0[0x8];
9440	u8         port[0x8];
9441	u8         max_gid[0x10];
9442
9443	u8         reserved_1[0x20];
9444
9445	u8         port_guid[0x40];
9446};
9447
9448struct mlx5_ifc_nvqc_reg_bits {
9449	u8         type[0x20];
9450
9451	u8         reserved_0[0x18];
9452	u8         version[0x4];
9453	u8         reserved_1[0x2];
9454	u8         support_wr[0x1];
9455	u8         support_rd[0x1];
9456};
9457
9458struct mlx5_ifc_nvia_reg_bits {
9459	u8         reserved_0[0x1d];
9460	u8         target[0x3];
9461
9462	u8         reserved_1[0x20];
9463};
9464
9465struct mlx5_ifc_nvdi_reg_bits {
9466	struct mlx5_ifc_config_item_bits configuration_item_header;
9467};
9468
9469struct mlx5_ifc_nvda_reg_bits {
9470	struct mlx5_ifc_config_item_bits configuration_item_header;
9471
9472	u8         configuration_item_data[0x20];
9473};
9474
9475struct mlx5_ifc_node_info_ro_fields_param_bits {
9476	u8         system_image_guid[0x40];
9477
9478	u8         reserved_0[0x40];
9479
9480	u8         node_guid[0x40];
9481
9482	u8         reserved_1[0x10];
9483	u8         max_pkey[0x10];
9484
9485	u8         reserved_2[0x20];
9486};
9487
9488struct mlx5_ifc_ets_tcn_config_reg_bits {
9489	u8         g[0x1];
9490	u8         b[0x1];
9491	u8         r[0x1];
9492	u8         reserved_0[0x9];
9493	u8         group[0x4];
9494	u8         reserved_1[0x9];
9495	u8         bw_allocation[0x7];
9496
9497	u8         reserved_2[0xc];
9498	u8         max_bw_units[0x4];
9499	u8         reserved_3[0x8];
9500	u8         max_bw_value[0x8];
9501};
9502
9503struct mlx5_ifc_ets_global_config_reg_bits {
9504	u8         reserved_0[0x2];
9505	u8         r[0x1];
9506	u8         reserved_1[0x1d];
9507
9508	u8         reserved_2[0xc];
9509	u8         max_bw_units[0x4];
9510	u8         reserved_3[0x8];
9511	u8         max_bw_value[0x8];
9512};
9513
9514struct mlx5_ifc_qetc_reg_bits {
9515	u8                                         reserved_at_0[0x8];
9516	u8                                         port_number[0x8];
9517	u8                                         reserved_at_10[0x30];
9518
9519	struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
9520	struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9521};
9522
9523struct mlx5_ifc_nodnic_mac_filters_bits {
9524	struct mlx5_ifc_mac_address_layout_bits mac_filter0;
9525
9526	struct mlx5_ifc_mac_address_layout_bits mac_filter1;
9527
9528	struct mlx5_ifc_mac_address_layout_bits mac_filter2;
9529
9530	struct mlx5_ifc_mac_address_layout_bits mac_filter3;
9531
9532	struct mlx5_ifc_mac_address_layout_bits mac_filter4;
9533
9534	u8         reserved_0[0xc0];
9535};
9536
9537struct mlx5_ifc_nodnic_gid_filters_bits {
9538	u8         mgid_filter0[16][0x8];
9539
9540	u8         mgid_filter1[16][0x8];
9541
9542	u8         mgid_filter2[16][0x8];
9543
9544	u8         mgid_filter3[16][0x8];
9545};
9546
9547enum {
9548	MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT  = 0x0,
9549	MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT    = 0x1,
9550};
9551
9552enum {
9553	MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE  = 0x0,
9554	MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE     = 0x1,
9555};
9556
9557struct mlx5_ifc_nodnic_config_reg_bits {
9558	u8         no_dram_nic_revision[0x8];
9559	u8         hardware_format[0x8];
9560	u8         support_receive_filter[0x1];
9561	u8         support_promisc_filter[0x1];
9562	u8         support_promisc_multicast_filter[0x1];
9563	u8         reserved_0[0x2];
9564	u8         log_working_buffer_size[0x3];
9565	u8         log_pkey_table_size[0x4];
9566	u8         reserved_1[0x3];
9567	u8         num_ports[0x1];
9568
9569	u8         reserved_2[0x2];
9570	u8         log_max_ring_size[0x6];
9571	u8         reserved_3[0x18];
9572
9573	u8         lkey[0x20];
9574
9575	u8         cqe_format[0x4];
9576	u8         reserved_4[0x1c];
9577
9578	u8         node_guid[0x40];
9579
9580	u8         reserved_5[0x740];
9581
9582	struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings;
9583
9584	struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings;
9585};
9586
9587struct mlx5_ifc_vlan_layout_bits {
9588	u8         reserved_0[0x14];
9589	u8         vlan[0xc];
9590
9591	u8         reserved_1[0x20];
9592};
9593
9594struct mlx5_ifc_umr_pointer_desc_argument_bits {
9595	u8         reserved_0[0x20];
9596
9597	u8         mkey[0x20];
9598
9599	u8         addressh_63_32[0x20];
9600
9601	u8         addressl_31_0[0x20];
9602};
9603
9604struct mlx5_ifc_ud_adrs_vector_bits {
9605	u8         dc_key[0x40];
9606
9607	u8         ext[0x1];
9608	u8         reserved_0[0x7];
9609	u8         destination_qp_dct[0x18];
9610
9611	u8         static_rate[0x4];
9612	u8         sl_eth_prio[0x4];
9613	u8         fl[0x1];
9614	u8         mlid[0x7];
9615	u8         rlid_udp_sport[0x10];
9616
9617	u8         reserved_1[0x20];
9618
9619	u8         rmac_47_16[0x20];
9620
9621	u8         rmac_15_0[0x10];
9622	u8         tclass[0x8];
9623	u8         hop_limit[0x8];
9624
9625	u8         reserved_2[0x1];
9626	u8         grh[0x1];
9627	u8         reserved_3[0x2];
9628	u8         src_addr_index[0x8];
9629	u8         flow_label[0x14];
9630
9631	u8         rgid_rip[16][0x8];
9632};
9633
9634struct mlx5_ifc_port_module_event_bits {
9635	u8         reserved_0[0x8];
9636	u8         module[0x8];
9637	u8         reserved_1[0xc];
9638	u8         module_status[0x4];
9639
9640	u8         reserved_2[0x14];
9641	u8         error_type[0x4];
9642	u8         reserved_3[0x8];
9643
9644	u8         reserved_4[0xa0];
9645};
9646
9647struct mlx5_ifc_icmd_control_bits {
9648	u8         opcode[0x10];
9649	u8         status[0x8];
9650	u8         reserved_0[0x7];
9651	u8         busy[0x1];
9652};
9653
9654struct mlx5_ifc_eqe_bits {
9655	u8         reserved_0[0x8];
9656	u8         event_type[0x8];
9657	u8         reserved_1[0x8];
9658	u8         event_sub_type[0x8];
9659
9660	u8         reserved_2[0xe0];
9661
9662	union mlx5_ifc_event_auto_bits event_data;
9663
9664	u8         reserved_3[0x10];
9665	u8         signature[0x8];
9666	u8         reserved_4[0x7];
9667	u8         owner[0x1];
9668};
9669
9670enum {
9671	MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
9672};
9673
9674struct mlx5_ifc_cmd_queue_entry_bits {
9675	u8         type[0x8];
9676	u8         reserved_0[0x18];
9677
9678	u8         input_length[0x20];
9679
9680	u8         input_mailbox_pointer_63_32[0x20];
9681
9682	u8         input_mailbox_pointer_31_9[0x17];
9683	u8         reserved_1[0x9];
9684
9685	u8         command_input_inline_data[16][0x8];
9686
9687	u8         command_output_inline_data[16][0x8];
9688
9689	u8         output_mailbox_pointer_63_32[0x20];
9690
9691	u8         output_mailbox_pointer_31_9[0x17];
9692	u8         reserved_2[0x9];
9693
9694	u8         output_length[0x20];
9695
9696	u8         token[0x8];
9697	u8         signature[0x8];
9698	u8         reserved_3[0x8];
9699	u8         status[0x7];
9700	u8         ownership[0x1];
9701};
9702
9703struct mlx5_ifc_cmd_out_bits {
9704	u8         status[0x8];
9705	u8         reserved_0[0x18];
9706
9707	u8         syndrome[0x20];
9708
9709	u8         command_output[0x20];
9710};
9711
9712struct mlx5_ifc_cmd_in_bits {
9713	u8         opcode[0x10];
9714	u8         reserved_0[0x10];
9715
9716	u8         reserved_1[0x10];
9717	u8         op_mod[0x10];
9718
9719	u8         command[0][0x20];
9720};
9721
9722struct mlx5_ifc_cmd_if_box_bits {
9723	u8         mailbox_data[512][0x8];
9724
9725	u8         reserved_0[0x180];
9726
9727	u8         next_pointer_63_32[0x20];
9728
9729	u8         next_pointer_31_10[0x16];
9730	u8         reserved_1[0xa];
9731
9732	u8         block_number[0x20];
9733
9734	u8         reserved_2[0x8];
9735	u8         token[0x8];
9736	u8         ctrl_signature[0x8];
9737	u8         signature[0x8];
9738};
9739
9740struct mlx5_ifc_mtt_bits {
9741	u8         ptag_63_32[0x20];
9742
9743	u8         ptag_31_8[0x18];
9744	u8         reserved_0[0x6];
9745	u8         wr_en[0x1];
9746	u8         rd_en[0x1];
9747};
9748
9749/* Vendor Specific Capabilities, VSC */
9750enum {
9751	MLX5_VSC_DOMAIN_ICMD			= 0x1,
9752	MLX5_VSC_DOMAIN_PROTECTED_CRSPACE	= 0x6,
9753	MLX5_VSC_DOMAIN_SCAN_CRSPACE		= 0x7,
9754	MLX5_VSC_DOMAIN_SEMAPHORES		= 0xA,
9755};
9756
9757struct mlx5_ifc_vendor_specific_cap_bits {
9758	u8         type[0x8];
9759	u8         length[0x8];
9760	u8         next_pointer[0x8];
9761	u8         capability_id[0x8];
9762
9763	u8         status[0x3];
9764	u8         reserved_0[0xd];
9765	u8         space[0x10];
9766
9767	u8         counter[0x20];
9768
9769	u8         semaphore[0x20];
9770
9771	u8         flag[0x1];
9772	u8         reserved_1[0x1];
9773	u8         address[0x1e];
9774
9775	u8         data[0x20];
9776};
9777
9778struct mlx5_ifc_vsc_space_bits {
9779	u8 status[0x3];
9780	u8 reserved0[0xd];
9781	u8 space[0x10];
9782};
9783
9784struct mlx5_ifc_vsc_addr_bits {
9785	u8 flag[0x1];
9786	u8 reserved0[0x1];
9787	u8 address[0x1e];
9788};
9789
9790enum {
9791	MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
9792	MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
9793	MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
9794};
9795
9796enum {
9797	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
9798	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
9799	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
9800};
9801
9802enum {
9803	MLX5_HEALTH_SYNDR_FW_ERR                                      = 0x1,
9804	MLX5_HEALTH_SYNDR_IRISC_ERR                                   = 0x7,
9805	MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR                        = 0x8,
9806	MLX5_HEALTH_SYNDR_CRC_ERR                                     = 0x9,
9807	MLX5_HEALTH_SYNDR_FETCH_PCI_ERR                               = 0xa,
9808	MLX5_HEALTH_SYNDR_HW_FTL_ERR                                  = 0xb,
9809	MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR                        = 0xc,
9810	MLX5_HEALTH_SYNDR_EQ_ERR                                      = 0xd,
9811	MLX5_HEALTH_SYNDR_EQ_INV                                      = 0xe,
9812	MLX5_HEALTH_SYNDR_FFSER_ERR                                   = 0xf,
9813	MLX5_HEALTH_SYNDR_HIGH_TEMP                                   = 0x10,
9814};
9815
9816struct mlx5_ifc_initial_seg_bits {
9817	u8         fw_rev_minor[0x10];
9818	u8         fw_rev_major[0x10];
9819
9820	u8         cmd_interface_rev[0x10];
9821	u8         fw_rev_subminor[0x10];
9822
9823	u8         reserved_0[0x40];
9824
9825	u8         cmdq_phy_addr_63_32[0x20];
9826
9827	u8         cmdq_phy_addr_31_12[0x14];
9828	u8         reserved_1[0x2];
9829	u8         nic_interface[0x2];
9830	u8         log_cmdq_size[0x4];
9831	u8         log_cmdq_stride[0x4];
9832
9833	u8         command_doorbell_vector[0x20];
9834
9835	u8         reserved_2[0xf00];
9836
9837	u8         initializing[0x1];
9838	u8         reserved_3[0x4];
9839	u8         nic_interface_supported[0x3];
9840	u8         reserved_4[0x18];
9841
9842	struct mlx5_ifc_health_buffer_bits health_buffer;
9843
9844	u8         no_dram_nic_offset[0x20];
9845
9846	u8         reserved_5[0x6de0];
9847
9848	u8         internal_timer_h[0x20];
9849
9850	u8         internal_timer_l[0x20];
9851
9852	u8         reserved_6[0x20];
9853
9854	u8         reserved_7[0x1f];
9855	u8         clear_int[0x1];
9856
9857	u8         health_syndrome[0x8];
9858	u8         health_counter[0x18];
9859
9860	u8         reserved_8[0x17fc0];
9861};
9862
9863union mlx5_ifc_icmd_interface_document_bits {
9864	struct mlx5_ifc_fw_version_bits fw_version;
9865	struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in;
9866	struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out;
9867	struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in;
9868	struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in;
9869	struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out;
9870	struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out;
9871	struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general;
9872	struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in;
9873	struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out;
9874	struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out;
9875	struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in;
9876	struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in;
9877	struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out;
9878	u8         reserved_0[0x42c0];
9879};
9880
9881union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
9882	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9883	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9884	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9885	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9886	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9887	struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
9888	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9889	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9890	struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
9891	struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs;
9892	u8         reserved_0[0x7c0];
9893};
9894
9895struct mlx5_ifc_ppcnt_reg_bits {
9896	u8         swid[0x8];
9897	u8         local_port[0x8];
9898	u8         pnat[0x2];
9899	u8         reserved_0[0x8];
9900	u8         grp[0x6];
9901
9902	u8         clr[0x1];
9903	u8         reserved_1[0x1c];
9904	u8         prio_tc[0x3];
9905
9906	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9907};
9908
9909struct mlx5_ifc_pcie_lanes_counters_bits {
9910	u8         life_time_counter_high[0x20];
9911
9912	u8         life_time_counter_low[0x20];
9913
9914	u8         error_counter_lane0[0x20];
9915
9916	u8         error_counter_lane1[0x20];
9917
9918	u8         error_counter_lane2[0x20];
9919
9920	u8         error_counter_lane3[0x20];
9921
9922	u8         error_counter_lane4[0x20];
9923
9924	u8         error_counter_lane5[0x20];
9925
9926	u8         error_counter_lane6[0x20];
9927
9928	u8         error_counter_lane7[0x20];
9929
9930	u8         error_counter_lane8[0x20];
9931
9932	u8         error_counter_lane9[0x20];
9933
9934	u8         error_counter_lane10[0x20];
9935
9936	u8         error_counter_lane11[0x20];
9937
9938	u8         error_counter_lane12[0x20];
9939
9940	u8         error_counter_lane13[0x20];
9941
9942	u8         error_counter_lane14[0x20];
9943
9944	u8         error_counter_lane15[0x20];
9945
9946	u8         reserved_at_240[0x580];
9947};
9948
9949struct mlx5_ifc_pcie_lanes_counters_ext_bits {
9950	u8         reserved_at_0[0x40];
9951
9952	u8         error_counter_lane0[0x20];
9953
9954	u8         error_counter_lane1[0x20];
9955
9956	u8         error_counter_lane2[0x20];
9957
9958	u8         error_counter_lane3[0x20];
9959
9960	u8         error_counter_lane4[0x20];
9961
9962	u8         error_counter_lane5[0x20];
9963
9964	u8         error_counter_lane6[0x20];
9965
9966	u8         error_counter_lane7[0x20];
9967
9968	u8         error_counter_lane8[0x20];
9969
9970	u8         error_counter_lane9[0x20];
9971
9972	u8         error_counter_lane10[0x20];
9973
9974	u8         error_counter_lane11[0x20];
9975
9976	u8         error_counter_lane12[0x20];
9977
9978	u8         error_counter_lane13[0x20];
9979
9980	u8         error_counter_lane14[0x20];
9981
9982	u8         error_counter_lane15[0x20];
9983
9984	u8         reserved_at_240[0x580];
9985};
9986
9987struct mlx5_ifc_pcie_perf_counters_bits {
9988	u8         life_time_counter_high[0x20];
9989
9990	u8         life_time_counter_low[0x20];
9991
9992	u8         rx_errors[0x20];
9993
9994	u8         tx_errors[0x20];
9995
9996	u8         l0_to_recovery_eieos[0x20];
9997
9998	u8         l0_to_recovery_ts[0x20];
9999
10000	u8         l0_to_recovery_framing[0x20];
10001
10002	u8         l0_to_recovery_retrain[0x20];
10003
10004	u8         crc_error_dllp[0x20];
10005
10006	u8         crc_error_tlp[0x20];
10007
10008	u8         tx_overflow_buffer_pkt[0x40];
10009
10010	u8         outbound_stalled_reads[0x20];
10011
10012	u8         outbound_stalled_writes[0x20];
10013
10014	u8         outbound_stalled_reads_events[0x20];
10015
10016	u8         outbound_stalled_writes_events[0x20];
10017
10018	u8         tx_overflow_buffer_marked_pkt[0x40];
10019
10020	u8         reserved_at_240[0x580];
10021};
10022
10023struct mlx5_ifc_pcie_perf_counters_ext_bits {
10024	u8         reserved_at_0[0x40];
10025
10026	u8         rx_errors[0x20];
10027
10028	u8         tx_errors[0x20];
10029
10030	u8         reserved_at_80[0xc0];
10031
10032	u8         tx_overflow_buffer_pkt[0x40];
10033
10034	u8         outbound_stalled_reads[0x20];
10035
10036	u8         outbound_stalled_writes[0x20];
10037
10038	u8         outbound_stalled_reads_events[0x20];
10039
10040	u8         outbound_stalled_writes_events[0x20];
10041
10042	u8         tx_overflow_buffer_marked_pkt[0x40];
10043
10044	u8         reserved_at_240[0x580];
10045};
10046
10047struct mlx5_ifc_pcie_timers_states_bits {
10048	u8         life_time_counter_high[0x20];
10049
10050	u8         life_time_counter_low[0x20];
10051
10052	u8         time_to_boot_image_start[0x20];
10053
10054	u8         time_to_link_image[0x20];
10055
10056	u8         calibration_time[0x20];
10057
10058	u8         time_to_first_perst[0x20];
10059
10060	u8         time_to_detect_state[0x20];
10061
10062	u8         time_to_l0[0x20];
10063
10064	u8         time_to_crs_en[0x20];
10065
10066	u8         time_to_plastic_image_start[0x20];
10067
10068	u8         time_to_iron_image_start[0x20];
10069
10070	u8         perst_handler[0x20];
10071
10072	u8         times_in_l1[0x20];
10073
10074	u8         times_in_l23[0x20];
10075
10076	u8         dl_down[0x20];
10077
10078	u8         config_cycle1usec[0x20];
10079
10080	u8         config_cycle2to7usec[0x20];
10081
10082	u8         config_cycle8to15usec[0x20];
10083
10084	u8         config_cycle16to63usec[0x20];
10085
10086	u8         config_cycle64usec[0x20];
10087
10088	u8         correctable_err_msg_sent[0x20];
10089
10090	u8         non_fatal_err_msg_sent[0x20];
10091
10092	u8         fatal_err_msg_sent[0x20];
10093
10094	u8         reserved_at_2e0[0x4e0];
10095};
10096
10097struct mlx5_ifc_pcie_timers_states_ext_bits {
10098	u8         reserved_at_0[0x40];
10099
10100	u8         time_to_boot_image_start[0x20];
10101
10102	u8         time_to_link_image[0x20];
10103
10104	u8         calibration_time[0x20];
10105
10106	u8         time_to_first_perst[0x20];
10107
10108	u8         time_to_detect_state[0x20];
10109
10110	u8         time_to_l0[0x20];
10111
10112	u8         time_to_crs_en[0x20];
10113
10114	u8         time_to_plastic_image_start[0x20];
10115
10116	u8         time_to_iron_image_start[0x20];
10117
10118	u8         perst_handler[0x20];
10119
10120	u8         times_in_l1[0x20];
10121
10122	u8         times_in_l23[0x20];
10123
10124	u8         dl_down[0x20];
10125
10126	u8         config_cycle1usec[0x20];
10127
10128	u8         config_cycle2to7usec[0x20];
10129
10130	u8         config_cycle8to15usec[0x20];
10131
10132	u8         config_cycle16to63usec[0x20];
10133
10134	u8         config_cycle64usec[0x20];
10135
10136	u8         correctable_err_msg_sent[0x20];
10137
10138	u8         non_fatal_err_msg_sent[0x20];
10139
10140	u8         fatal_err_msg_sent[0x20];
10141
10142	u8         reserved_at_2e0[0x4e0];
10143};
10144
10145union mlx5_ifc_mpcnt_reg_counter_set_auto_bits {
10146	struct mlx5_ifc_pcie_perf_counters_bits pcie_perf_counters;
10147	struct mlx5_ifc_pcie_lanes_counters_bits pcie_lanes_counters;
10148	struct mlx5_ifc_pcie_timers_states_bits pcie_timers_states;
10149	u8         reserved_at_0[0x7c0];
10150};
10151
10152union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits {
10153	struct mlx5_ifc_pcie_perf_counters_ext_bits pcie_perf_counters_ext;
10154	struct mlx5_ifc_pcie_lanes_counters_ext_bits pcie_lanes_counters_ext;
10155	struct mlx5_ifc_pcie_timers_states_ext_bits pcie_timers_states_ext;
10156	u8         reserved_at_0[0x7c0];
10157};
10158
10159struct mlx5_ifc_mpcnt_reg_bits {
10160	u8         reserved_at_0[0x2];
10161	u8         depth[0x6];
10162	u8         pcie_index[0x8];
10163	u8         node[0x8];
10164	u8         reserved_at_18[0x2];
10165	u8         grp[0x6];
10166
10167	u8         clr[0x1];
10168	u8         reserved_at_21[0x1f];
10169
10170	union mlx5_ifc_mpcnt_reg_counter_set_auto_bits counter_set;
10171};
10172
10173struct mlx5_ifc_mpcnt_reg_ext_bits {
10174	u8         reserved_at_0[0x2];
10175	u8         depth[0x6];
10176	u8         pcie_index[0x8];
10177	u8         node[0x8];
10178	u8         reserved_at_18[0x2];
10179	u8         grp[0x6];
10180
10181	u8         clr[0x1];
10182	u8         reserved_at_21[0x1f];
10183
10184	union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits counter_set;
10185};
10186
10187enum {
10188	MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN = 0x9050,
10189	MLX5_MPEIN_PWR_STATUS_INVALID = 0,
10190	MLX5_MPEIN_PWR_STATUS_SUFFICIENT = 1,
10191	MLX5_MPEIN_PWR_STATUS_INSUFFICIENT = 2,
10192};
10193
10194struct mlx5_ifc_mpein_reg_bits {
10195	u8         reserved_at_0[0x2];
10196	u8         depth[0x6];
10197	u8         pcie_index[0x8];
10198	u8         node[0x8];
10199	u8         reserved_at_18[0x8];
10200
10201	u8         capability_mask[0x20];
10202
10203	u8         reserved_at_40[0x8];
10204	u8         link_width_enabled[0x8];
10205	u8         link_speed_enabled[0x10];
10206
10207	u8         lane0_physical_position[0x8];
10208	u8         link_width_active[0x8];
10209	u8         link_speed_active[0x10];
10210
10211	u8         num_of_pfs[0x10];
10212	u8         num_of_vfs[0x10];
10213
10214	u8         bdf0[0x10];
10215	u8         reserved_at_b0[0x10];
10216
10217	u8         max_read_request_size[0x4];
10218	u8         max_payload_size[0x4];
10219	u8         reserved_at_c8[0x5];
10220	u8         pwr_status[0x3];
10221	u8         port_type[0x4];
10222	u8         reserved_at_d4[0xb];
10223	u8         lane_reversal[0x1];
10224
10225	u8         reserved_at_e0[0x14];
10226	u8         pci_power[0xc];
10227
10228	u8         reserved_at_100[0x20];
10229
10230	u8         device_status[0x10];
10231	u8         port_state[0x8];
10232	u8         reserved_at_138[0x8];
10233
10234	u8         reserved_at_140[0x10];
10235	u8         receiver_detect_result[0x10];
10236
10237	u8         reserved_at_160[0x20];
10238};
10239
10240struct mlx5_ifc_mpein_reg_ext_bits {
10241	u8         reserved_at_0[0x2];
10242	u8         depth[0x6];
10243	u8         pcie_index[0x8];
10244	u8         node[0x8];
10245	u8         reserved_at_18[0x8];
10246
10247	u8         reserved_at_20[0x20];
10248
10249	u8         reserved_at_40[0x8];
10250	u8         link_width_enabled[0x8];
10251	u8         link_speed_enabled[0x10];
10252
10253	u8         lane0_physical_position[0x8];
10254	u8         link_width_active[0x8];
10255	u8         link_speed_active[0x10];
10256
10257	u8         num_of_pfs[0x10];
10258	u8         num_of_vfs[0x10];
10259
10260	u8         bdf0[0x10];
10261	u8         reserved_at_b0[0x10];
10262
10263	u8         max_read_request_size[0x4];
10264	u8         max_payload_size[0x4];
10265	u8         reserved_at_c8[0x5];
10266	u8         pwr_status[0x3];
10267	u8         port_type[0x4];
10268	u8         reserved_at_d4[0xb];
10269	u8         lane_reversal[0x1];
10270};
10271
10272struct mlx5_ifc_mcqi_cap_bits {
10273	u8         supported_info_bitmask[0x20];
10274
10275	u8         component_size[0x20];
10276
10277	u8         max_component_size[0x20];
10278
10279	u8         log_mcda_word_size[0x4];
10280	u8         reserved_at_64[0xc];
10281	u8         mcda_max_write_size[0x10];
10282
10283	u8         rd_en[0x1];
10284	u8         reserved_at_81[0x1];
10285	u8         match_chip_id[0x1];
10286	u8         match_psid[0x1];
10287	u8         check_user_timestamp[0x1];
10288	u8         match_base_guid_mac[0x1];
10289	u8         reserved_at_86[0x1a];
10290};
10291
10292struct mlx5_ifc_mcqi_reg_bits {
10293	u8         read_pending_component[0x1];
10294	u8         reserved_at_1[0xf];
10295	u8         component_index[0x10];
10296
10297	u8         reserved_at_20[0x20];
10298
10299	u8         reserved_at_40[0x1b];
10300	u8         info_type[0x5];
10301
10302	u8         info_size[0x20];
10303
10304	u8         offset[0x20];
10305
10306	u8         reserved_at_a0[0x10];
10307	u8         data_size[0x10];
10308
10309	u8         data[0][0x20];
10310};
10311
10312struct mlx5_ifc_mcc_reg_bits {
10313	u8         reserved_at_0[0x4];
10314	u8         time_elapsed_since_last_cmd[0xc];
10315	u8         reserved_at_10[0x8];
10316	u8         instruction[0x8];
10317
10318	u8         reserved_at_20[0x10];
10319	u8         component_index[0x10];
10320
10321	u8         reserved_at_40[0x8];
10322	u8         update_handle[0x18];
10323
10324	u8         handle_owner_type[0x4];
10325	u8         handle_owner_host_id[0x4];
10326	u8         reserved_at_68[0x1];
10327	u8         control_progress[0x7];
10328	u8         error_code[0x8];
10329	u8         reserved_at_78[0x4];
10330	u8         control_state[0x4];
10331
10332	u8         component_size[0x20];
10333
10334	u8         reserved_at_a0[0x60];
10335};
10336
10337struct mlx5_ifc_mcda_reg_bits {
10338	u8         reserved_at_0[0x8];
10339	u8         update_handle[0x18];
10340
10341	u8         offset[0x20];
10342
10343	u8         reserved_at_40[0x10];
10344	u8         size[0x10];
10345
10346	u8         reserved_at_60[0x20];
10347
10348	u8         data[0][0x20];
10349};
10350
10351union mlx5_ifc_ports_control_registers_document_bits {
10352	struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data;
10353	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
10354	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10355	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10356	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10357	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10358	struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
10359	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10360	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
10361	struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout;
10362	struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout;
10363	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
10364	struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date;
10365	struct mlx5_ifc_pamp_reg_bits pamp_reg;
10366	struct mlx5_ifc_paos_reg_bits paos_reg;
10367	struct mlx5_ifc_pbmc_reg_bits pbmc_reg;
10368	struct mlx5_ifc_pcap_reg_bits pcap_reg;
10369	struct mlx5_ifc_peir_reg_bits peir_reg;
10370	struct mlx5_ifc_pelc_reg_bits pelc_reg;
10371	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
10372	struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg;
10373	struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg;
10374	struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg;
10375	struct mlx5_ifc_phrr_reg_bits phrr_reg;
10376	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10377	struct mlx5_ifc_pifr_reg_bits pifr_reg;
10378	struct mlx5_ifc_pipg_reg_bits pipg_reg;
10379	struct mlx5_ifc_plbf_reg_bits plbf_reg;
10380	struct mlx5_ifc_plib_reg_bits plib_reg;
10381	struct mlx5_ifc_pll_status_data_bits pll_status_data;
10382	struct mlx5_ifc_plpc_reg_bits plpc_reg;
10383	struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
10384	struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
10385	struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
10386	struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
10387	struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
10388	struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
10389	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
10390	struct mlx5_ifc_ppad_reg_bits ppad_reg;
10391	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
10392	struct mlx5_ifc_ppll_reg_bits ppll_reg;
10393	struct mlx5_ifc_pplm_reg_bits pplm_reg;
10394	struct mlx5_ifc_pplr_reg_bits pplr_reg;
10395	struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
10396	struct mlx5_ifc_pspa_reg_bits pspa_reg;
10397	struct mlx5_ifc_ptas_reg_bits ptas_reg;
10398	struct mlx5_ifc_ptys_reg_bits ptys_reg;
10399	struct mlx5_ifc_pude_reg_bits pude_reg;
10400	struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
10401	struct mlx5_ifc_slrg_reg_bits slrg_reg;
10402	struct mlx5_ifc_slrp_reg_bits slrp_reg;
10403	struct mlx5_ifc_sltp_reg_bits sltp_reg;
10404	u8         reserved_0[0x7880];
10405};
10406
10407union mlx5_ifc_debug_enhancements_document_bits {
10408	struct mlx5_ifc_health_buffer_bits health_buffer;
10409	u8         reserved_0[0x200];
10410};
10411
10412union mlx5_ifc_no_dram_nic_document_bits {
10413	struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg;
10414	struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word;
10415	struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word;
10416	struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters;
10417	struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters;
10418	struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg;
10419	struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg;
10420	struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell;
10421	u8         reserved_0[0x3160];
10422};
10423
10424union mlx5_ifc_uplink_pci_interface_document_bits {
10425	struct mlx5_ifc_initial_seg_bits initial_seg;
10426	struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap;
10427	u8         reserved_0[0x20120];
10428};
10429
10430struct mlx5_ifc_qpdpm_dscp_reg_bits {
10431	u8         e[0x1];
10432	u8         reserved_at_01[0x0b];
10433	u8         prio[0x04];
10434};
10435
10436struct mlx5_ifc_qpdpm_reg_bits {
10437	u8                                     reserved_at_0[0x8];
10438	u8                                     local_port[0x8];
10439	u8                                     reserved_at_10[0x10];
10440	struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
10441};
10442
10443struct mlx5_ifc_qpts_reg_bits {
10444	u8         reserved_at_0[0x8];
10445	u8         local_port[0x8];
10446	u8         reserved_at_10[0x2d];
10447	u8         trust_state[0x3];
10448};
10449
10450struct mlx5_ifc_mfrl_reg_bits {
10451	u8         reserved_at_0[0x38];
10452	u8         reset_level[0x8];
10453};
10454
10455enum {
10456      MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTCAP	= 0x9009,
10457      MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTECR	= 0x9109,
10458      MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTMP	= 0x900a,
10459      MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTWE	= 0x900b,
10460      MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTBR	= 0x900f,
10461      MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTEWE	= 0x910b,
10462      MLX5_MAX_TEMPERATURE = 16,
10463};
10464
10465struct mlx5_ifc_mtbr_temp_record_bits {
10466	u8         max_temperature[0x10];
10467	u8         temperature[0x10];
10468};
10469
10470struct mlx5_ifc_mtbr_reg_bits {
10471	u8         reserved_at_0[0x14];
10472	u8         base_sensor_index[0xc];
10473
10474	u8         reserved_at_20[0x18];
10475	u8         num_rec[0x8];
10476
10477	u8         reserved_at_40[0x40];
10478
10479	struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE];
10480};
10481
10482struct mlx5_ifc_mtbr_reg_ext_bits {
10483	u8         reserved_at_0[0x14];
10484	u8         base_sensor_index[0xc];
10485
10486	u8         reserved_at_20[0x18];
10487	u8         num_rec[0x8];
10488
10489	u8         reserved_at_40[0x40];
10490
10491    struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE];
10492};
10493
10494struct mlx5_ifc_mtcap_bits {
10495	u8         reserved_at_0[0x19];
10496	u8         sensor_count[0x7];
10497
10498	u8         reserved_at_20[0x19];
10499	u8         internal_sensor_count[0x7];
10500
10501	u8         sensor_map[0x40];
10502};
10503
10504struct mlx5_ifc_mtcap_ext_bits {
10505	u8         reserved_at_0[0x19];
10506	u8         sensor_count[0x7];
10507
10508	u8         reserved_at_20[0x20];
10509
10510	u8         sensor_map[0x40];
10511};
10512
10513struct mlx5_ifc_mtecr_bits {
10514	u8         reserved_at_0[0x4];
10515	u8         last_sensor[0xc];
10516	u8         reserved_at_10[0x4];
10517	u8         sensor_count[0xc];
10518
10519	u8         reserved_at_20[0x19];
10520	u8         internal_sensor_count[0x7];
10521
10522	u8         sensor_map_0[0x20];
10523
10524	u8         reserved_at_60[0x2a0];
10525};
10526
10527struct mlx5_ifc_mtecr_ext_bits {
10528	u8         reserved_at_0[0x4];
10529	u8         last_sensor[0xc];
10530	u8         reserved_at_10[0x4];
10531	u8         sensor_count[0xc];
10532
10533	u8         reserved_at_20[0x20];
10534
10535	u8         sensor_map_0[0x20];
10536
10537	u8         reserved_at_60[0x2a0];
10538};
10539
10540struct mlx5_ifc_mtewe_bits {
10541	u8         reserved_at_0[0x4];
10542	u8         last_sensor[0xc];
10543	u8         reserved_at_10[0x4];
10544	u8         sensor_count[0xc];
10545
10546	u8         sensor_warning_0[0x20];
10547
10548	u8         reserved_at_40[0x2a0];
10549};
10550
10551struct mlx5_ifc_mtewe_ext_bits {
10552	u8         reserved_at_0[0x4];
10553	u8         last_sensor[0xc];
10554	u8         reserved_at_10[0x4];
10555	u8         sensor_count[0xc];
10556
10557	u8         sensor_warning_0[0x20];
10558
10559	u8         reserved_at_40[0x2a0];
10560};
10561
10562struct mlx5_ifc_mtmp_bits {
10563	u8         reserved_at_0[0x14];
10564	u8         sensor_index[0xc];
10565
10566	u8         reserved_at_20[0x10];
10567	u8         temperature[0x10];
10568
10569	u8         mte[0x1];
10570	u8         mtr[0x1];
10571	u8         reserved_at_42[0xe];
10572	u8         max_temperature[0x10];
10573
10574	u8         tee[0x2];
10575	u8         reserved_at_62[0xe];
10576	u8         temperature_threshold_hi[0x10];
10577
10578	u8         reserved_at_80[0x10];
10579	u8         temperature_threshold_lo[0x10];
10580
10581	u8         reserved_at_a0[0x20];
10582
10583	u8         sensor_name_hi[0x20];
10584
10585	u8         sensor_name_lo[0x20];
10586};
10587
10588struct mlx5_ifc_mtmp_ext_bits {
10589	u8         reserved_at_0[0x14];
10590	u8         sensor_index[0xc];
10591
10592	u8         reserved_at_20[0x10];
10593	u8         temperature[0x10];
10594
10595	u8         mte[0x1];
10596	u8         mtr[0x1];
10597	u8         reserved_at_42[0xe];
10598	u8         max_temperature[0x10];
10599
10600	u8         tee[0x2];
10601	u8         reserved_at_62[0xe];
10602	u8         temperature_threshold_hi[0x10];
10603
10604	u8         reserved_at_80[0x10];
10605	u8         temperature_threshold_lo[0x10];
10606
10607	u8         reserved_at_a0[0x20];
10608
10609	u8         sensor_name_hi[0x20];
10610
10611	u8         sensor_name_lo[0x20];
10612};
10613
10614#endif /* MLX5_IFC_H */
10615