mlx5_ifc.h revision 341964
1/*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_ifc.h 341964 2018-12-12 12:53:31Z hselasky $ 26 */ 27 28#ifndef MLX5_IFC_H 29#define MLX5_IFC_H 30 31#include <dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h> 32 33enum { 34 MLX5_EVENT_TYPE_COMP = 0x0, 35 MLX5_EVENT_TYPE_PATH_MIG = 0x1, 36 MLX5_EVENT_TYPE_COMM_EST = 0x2, 37 MLX5_EVENT_TYPE_SQ_DRAINED = 0x3, 38 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 39 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 40 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c, 41 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d, 42 MLX5_EVENT_TYPE_CQ_ERROR = 0x4, 43 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x5, 44 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x7, 45 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 46 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 47 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 48 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 49 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x8, 50 MLX5_EVENT_TYPE_PORT_CHANGE = 0x9, 51 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 52 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT = 0x16, 53 MLX5_EVENT_TYPE_CODING_TEMP_WARNING_EVENT = 0x17, 54 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 55 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT = 0x1e, 56 MLX5_EVENT_TYPE_CODING_PPS_EVENT = 0x25, 57 MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT = 0x22, 58 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 59 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 60 MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 61 MLX5_EVENT_TYPE_CMD = 0xa, 62 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 63 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd, 64 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20, 65 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21, 66}; 67 68enum { 69 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 70 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 71 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 72 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3, 73 MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN = 0x4 74}; 75 76enum { 77 MLX5_MODIFY_RQT_BITMASK_RQN_LIST = 0x1, 78}; 79 80enum { 81 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 82 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 83}; 84 85enum { 86 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 87 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 88 MLX5_CMD_OP_INIT_HCA = 0x102, 89 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 90 MLX5_CMD_OP_ENABLE_HCA = 0x104, 91 MLX5_CMD_OP_DISABLE_HCA = 0x105, 92 MLX5_CMD_OP_QUERY_PAGES = 0x107, 93 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 94 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 95 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 96 MLX5_CMD_OP_SET_ISSI = 0x10b, 97 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 98 MLX5_CMD_OP_QUERY_OTHER_HCA_CAP = 0x10e, 99 MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP = 0x10f, 100 MLX5_CMD_OP_CREATE_MKEY = 0x200, 101 MLX5_CMD_OP_QUERY_MKEY = 0x201, 102 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 103 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 104 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 105 MLX5_CMD_OP_CREATE_EQ = 0x301, 106 MLX5_CMD_OP_DESTROY_EQ = 0x302, 107 MLX5_CMD_OP_QUERY_EQ = 0x303, 108 MLX5_CMD_OP_GEN_EQE = 0x304, 109 MLX5_CMD_OP_CREATE_CQ = 0x400, 110 MLX5_CMD_OP_DESTROY_CQ = 0x401, 111 MLX5_CMD_OP_QUERY_CQ = 0x402, 112 MLX5_CMD_OP_MODIFY_CQ = 0x403, 113 MLX5_CMD_OP_CREATE_QP = 0x500, 114 MLX5_CMD_OP_DESTROY_QP = 0x501, 115 MLX5_CMD_OP_RST2INIT_QP = 0x502, 116 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 117 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 118 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 119 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 120 MLX5_CMD_OP_2ERR_QP = 0x507, 121 MLX5_CMD_OP_2RST_QP = 0x50a, 122 MLX5_CMD_OP_QUERY_QP = 0x50b, 123 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 124 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 125 MLX5_CMD_OP_CREATE_PSV = 0x600, 126 MLX5_CMD_OP_DESTROY_PSV = 0x601, 127 MLX5_CMD_OP_CREATE_SRQ = 0x700, 128 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 129 MLX5_CMD_OP_QUERY_SRQ = 0x702, 130 MLX5_CMD_OP_ARM_RQ = 0x703, 131 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 132 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 133 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 134 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 135 MLX5_CMD_OP_CREATE_DCT = 0x710, 136 MLX5_CMD_OP_DESTROY_DCT = 0x711, 137 MLX5_CMD_OP_DRAIN_DCT = 0x712, 138 MLX5_CMD_OP_QUERY_DCT = 0x713, 139 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 140 MLX5_CMD_OP_SET_DC_CNAK_TRACE = 0x715, 141 MLX5_CMD_OP_QUERY_DC_CNAK_TRACE = 0x716, 142 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 143 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 144 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 145 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 146 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 147 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 148 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 149 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 150 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 151 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 152 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 153 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 154 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 155 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 156 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 157 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 158 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780, 159 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 160 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 161 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 162 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 163 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 164 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 165 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 166 MLX5_CMD_OP_ALLOC_PD = 0x800, 167 MLX5_CMD_OP_DEALLOC_PD = 0x801, 168 MLX5_CMD_OP_ALLOC_UAR = 0x802, 169 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 170 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 171 MLX5_CMD_OP_ACCESS_REG = 0x805, 172 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 173 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 174 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 175 MLX5_CMD_OP_MAD_IFC = 0x50d, 176 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 177 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 178 MLX5_CMD_OP_NOP = 0x80d, 179 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 180 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 181 MLX5_CMD_OP_SET_BURST_SIZE = 0x812, 182 MLX5_CMD_OP_QUERY_BURST_SIZE = 0x813, 183 MLX5_CMD_OP_ACTIVATE_TRACER = 0x814, 184 MLX5_CMD_OP_DEACTIVATE_TRACER = 0x815, 185 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 186 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 187 MLX5_CMD_OP_SET_DIAGNOSTICS = 0x820, 188 MLX5_CMD_OP_QUERY_DIAGNOSTICS = 0x821, 189 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 190 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 191 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 192 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 193 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 194 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 195 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 196 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 197 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 198 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 199 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 200 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 201 MLX5_CMD_OP_CREATE_LAG = 0x840, 202 MLX5_CMD_OP_MODIFY_LAG = 0x841, 203 MLX5_CMD_OP_QUERY_LAG = 0x842, 204 MLX5_CMD_OP_DESTROY_LAG = 0x843, 205 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 206 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 207 MLX5_CMD_OP_CREATE_TIR = 0x900, 208 MLX5_CMD_OP_MODIFY_TIR = 0x901, 209 MLX5_CMD_OP_DESTROY_TIR = 0x902, 210 MLX5_CMD_OP_QUERY_TIR = 0x903, 211 MLX5_CMD_OP_CREATE_SQ = 0x904, 212 MLX5_CMD_OP_MODIFY_SQ = 0x905, 213 MLX5_CMD_OP_DESTROY_SQ = 0x906, 214 MLX5_CMD_OP_QUERY_SQ = 0x907, 215 MLX5_CMD_OP_CREATE_RQ = 0x908, 216 MLX5_CMD_OP_MODIFY_RQ = 0x909, 217 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 218 MLX5_CMD_OP_QUERY_RQ = 0x90b, 219 MLX5_CMD_OP_CREATE_RMP = 0x90c, 220 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 221 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 222 MLX5_CMD_OP_QUERY_RMP = 0x90f, 223 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 224 MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS = 0x911, 225 MLX5_CMD_OP_CREATE_TIS = 0x912, 226 MLX5_CMD_OP_MODIFY_TIS = 0x913, 227 MLX5_CMD_OP_DESTROY_TIS = 0x914, 228 MLX5_CMD_OP_QUERY_TIS = 0x915, 229 MLX5_CMD_OP_CREATE_RQT = 0x916, 230 MLX5_CMD_OP_MODIFY_RQT = 0x917, 231 MLX5_CMD_OP_DESTROY_RQT = 0x918, 232 MLX5_CMD_OP_QUERY_RQT = 0x919, 233 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 234 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 235 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 236 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 237 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 238 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 239 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 240 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 241 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 242 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 243 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 244 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 245 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 246 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 247 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d, 248 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e, 249 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 250 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 251 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 252 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 253 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 254}; 255 256enum { 257 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO = 0x8007, 258 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY = 0x8400, 259 MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER = 0x9001, 260 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC = 0x9003, 261 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC = 0x9004, 262 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL = 0x9005, 263 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL = 0x9006, 264 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT = 0x9007, 265 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008, 266 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS = 0x9009, 267 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT = 0x900a, 268 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD = 0xf004 269}; 270 271struct mlx5_ifc_flow_table_fields_supported_bits { 272 u8 outer_dmac[0x1]; 273 u8 outer_smac[0x1]; 274 u8 outer_ether_type[0x1]; 275 u8 reserved_0[0x1]; 276 u8 outer_first_prio[0x1]; 277 u8 outer_first_cfi[0x1]; 278 u8 outer_first_vid[0x1]; 279 u8 reserved_1[0x1]; 280 u8 outer_second_prio[0x1]; 281 u8 outer_second_cfi[0x1]; 282 u8 outer_second_vid[0x1]; 283 u8 outer_ipv6_flow_label[0x1]; 284 u8 outer_sip[0x1]; 285 u8 outer_dip[0x1]; 286 u8 outer_frag[0x1]; 287 u8 outer_ip_protocol[0x1]; 288 u8 outer_ip_ecn[0x1]; 289 u8 outer_ip_dscp[0x1]; 290 u8 outer_udp_sport[0x1]; 291 u8 outer_udp_dport[0x1]; 292 u8 outer_tcp_sport[0x1]; 293 u8 outer_tcp_dport[0x1]; 294 u8 outer_tcp_flags[0x1]; 295 u8 outer_gre_protocol[0x1]; 296 u8 outer_gre_key[0x1]; 297 u8 outer_vxlan_vni[0x1]; 298 u8 outer_geneve_vni[0x1]; 299 u8 outer_geneve_oam[0x1]; 300 u8 outer_geneve_protocol_type[0x1]; 301 u8 outer_geneve_opt_len[0x1]; 302 u8 reserved_2[0x1]; 303 u8 source_eswitch_port[0x1]; 304 305 u8 inner_dmac[0x1]; 306 u8 inner_smac[0x1]; 307 u8 inner_ether_type[0x1]; 308 u8 reserved_3[0x1]; 309 u8 inner_first_prio[0x1]; 310 u8 inner_first_cfi[0x1]; 311 u8 inner_first_vid[0x1]; 312 u8 reserved_4[0x1]; 313 u8 inner_second_prio[0x1]; 314 u8 inner_second_cfi[0x1]; 315 u8 inner_second_vid[0x1]; 316 u8 inner_ipv6_flow_label[0x1]; 317 u8 inner_sip[0x1]; 318 u8 inner_dip[0x1]; 319 u8 inner_frag[0x1]; 320 u8 inner_ip_protocol[0x1]; 321 u8 inner_ip_ecn[0x1]; 322 u8 inner_ip_dscp[0x1]; 323 u8 inner_udp_sport[0x1]; 324 u8 inner_udp_dport[0x1]; 325 u8 inner_tcp_sport[0x1]; 326 u8 inner_tcp_dport[0x1]; 327 u8 inner_tcp_flags[0x1]; 328 u8 reserved_5[0x9]; 329 330 u8 reserved_6[0x1a]; 331 u8 bth_dst_qp[0x1]; 332 u8 reserved_7[0x4]; 333 u8 source_sqn[0x1]; 334 335 u8 reserved_8[0x20]; 336}; 337 338struct mlx5_ifc_eth_discard_cntrs_grp_bits { 339 u8 ingress_general_high[0x20]; 340 341 u8 ingress_general_low[0x20]; 342 343 u8 ingress_policy_engine_high[0x20]; 344 345 u8 ingress_policy_engine_low[0x20]; 346 347 u8 ingress_vlan_membership_high[0x20]; 348 349 u8 ingress_vlan_membership_low[0x20]; 350 351 u8 ingress_tag_frame_type_high[0x20]; 352 353 u8 ingress_tag_frame_type_low[0x20]; 354 355 u8 egress_vlan_membership_high[0x20]; 356 357 u8 egress_vlan_membership_low[0x20]; 358 359 u8 loopback_filter_high[0x20]; 360 361 u8 loopback_filter_low[0x20]; 362 363 u8 egress_general_high[0x20]; 364 365 u8 egress_general_low[0x20]; 366 367 u8 reserved_at_1c0[0x40]; 368 369 u8 egress_hoq_high[0x20]; 370 371 u8 egress_hoq_low[0x20]; 372 373 u8 port_isolation_high[0x20]; 374 375 u8 port_isolation_low[0x20]; 376 377 u8 egress_policy_engine_high[0x20]; 378 379 u8 egress_policy_engine_low[0x20]; 380 381 u8 ingress_tx_link_down_high[0x20]; 382 383 u8 ingress_tx_link_down_low[0x20]; 384 385 u8 egress_stp_filter_high[0x20]; 386 387 u8 egress_stp_filter_low[0x20]; 388 389 u8 egress_hoq_stall_high[0x20]; 390 391 u8 egress_hoq_stall_low[0x20]; 392 393 u8 reserved_at_340[0x440]; 394}; 395struct mlx5_ifc_flow_table_prop_layout_bits { 396 u8 ft_support[0x1]; 397 u8 flow_tag[0x1]; 398 u8 flow_counter[0x1]; 399 u8 flow_modify_en[0x1]; 400 u8 modify_root[0x1]; 401 u8 identified_miss_table[0x1]; 402 u8 flow_table_modify[0x1]; 403 u8 encap[0x1]; 404 u8 decap[0x1]; 405 u8 reset_root_to_default[0x1]; 406 u8 reserved_at_a[0x16]; 407 408 u8 reserved_at_20[0x2]; 409 u8 log_max_ft_size[0x6]; 410 u8 reserved_at_28[0x10]; 411 u8 max_ft_level[0x8]; 412 413 u8 reserved_at_40[0x20]; 414 415 u8 reserved_at_60[0x18]; 416 u8 log_max_ft_num[0x8]; 417 418 u8 reserved_at_80[0x10]; 419 u8 log_max_flow_counter[0x8]; 420 u8 log_max_destination[0x8]; 421 422 u8 reserved_at_a0[0x18]; 423 u8 log_max_flow[0x8]; 424 425 u8 reserved_at_c0[0x40]; 426 427 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 428 429 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 430}; 431 432struct mlx5_ifc_odp_per_transport_service_cap_bits { 433 u8 send[0x1]; 434 u8 receive[0x1]; 435 u8 write[0x1]; 436 u8 read[0x1]; 437 u8 atomic[0x1]; 438 u8 srq_receive[0x1]; 439 u8 reserved_0[0x1a]; 440}; 441 442struct mlx5_ifc_flow_counter_list_bits { 443 u8 reserved_0[0x10]; 444 u8 flow_counter_id[0x10]; 445 446 u8 reserved_1[0x20]; 447}; 448 449enum { 450 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0x0, 451 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 0x1, 452 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 0x2, 453 MLX5_FLOW_CONTEXT_DEST_TYPE_QP = 0x3, 454}; 455 456struct mlx5_ifc_dest_format_struct_bits { 457 u8 destination_type[0x8]; 458 u8 destination_id[0x18]; 459 460 u8 reserved_0[0x20]; 461}; 462 463struct mlx5_ifc_ipv4_layout_bits { 464 u8 reserved_at_0[0x60]; 465 466 u8 ipv4[0x20]; 467}; 468 469struct mlx5_ifc_ipv6_layout_bits { 470 u8 ipv6[16][0x8]; 471}; 472 473union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 474 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 475 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 476 u8 reserved_at_0[0x80]; 477}; 478 479struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 480 u8 smac_47_16[0x20]; 481 482 u8 smac_15_0[0x10]; 483 u8 ethertype[0x10]; 484 485 u8 dmac_47_16[0x20]; 486 487 u8 dmac_15_0[0x10]; 488 u8 first_prio[0x3]; 489 u8 first_cfi[0x1]; 490 u8 first_vid[0xc]; 491 492 u8 ip_protocol[0x8]; 493 u8 ip_dscp[0x6]; 494 u8 ip_ecn[0x2]; 495 u8 cvlan_tag[0x1]; 496 u8 svlan_tag[0x1]; 497 u8 frag[0x1]; 498 u8 reserved_1[0x4]; 499 u8 tcp_flags[0x9]; 500 501 u8 tcp_sport[0x10]; 502 u8 tcp_dport[0x10]; 503 504 u8 reserved_2[0x20]; 505 506 u8 udp_sport[0x10]; 507 u8 udp_dport[0x10]; 508 509 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 510 511 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 512}; 513 514struct mlx5_ifc_fte_match_set_misc_bits { 515 u8 reserved_0[0x8]; 516 u8 source_sqn[0x18]; 517 518 u8 reserved_1[0x10]; 519 u8 source_port[0x10]; 520 521 u8 outer_second_prio[0x3]; 522 u8 outer_second_cfi[0x1]; 523 u8 outer_second_vid[0xc]; 524 u8 inner_second_prio[0x3]; 525 u8 inner_second_cfi[0x1]; 526 u8 inner_second_vid[0xc]; 527 528 u8 outer_second_vlan_tag[0x1]; 529 u8 inner_second_vlan_tag[0x1]; 530 u8 reserved_2[0xe]; 531 u8 gre_protocol[0x10]; 532 533 u8 gre_key_h[0x18]; 534 u8 gre_key_l[0x8]; 535 536 u8 vxlan_vni[0x18]; 537 u8 reserved_3[0x8]; 538 539 u8 geneve_vni[0x18]; 540 u8 reserved4[0x7]; 541 u8 geneve_oam[0x1]; 542 543 u8 reserved_5[0xc]; 544 u8 outer_ipv6_flow_label[0x14]; 545 546 u8 reserved_6[0xc]; 547 u8 inner_ipv6_flow_label[0x14]; 548 549 u8 reserved_7[0xa]; 550 u8 geneve_opt_len[0x6]; 551 u8 geneve_protocol_type[0x10]; 552 553 u8 reserved_8[0x8]; 554 u8 bth_dst_qp[0x18]; 555 556 u8 reserved_9[0xa0]; 557}; 558 559struct mlx5_ifc_cmd_pas_bits { 560 u8 pa_h[0x20]; 561 562 u8 pa_l[0x14]; 563 u8 reserved_0[0xc]; 564}; 565 566struct mlx5_ifc_uint64_bits { 567 u8 hi[0x20]; 568 569 u8 lo[0x20]; 570}; 571 572struct mlx5_ifc_application_prio_entry_bits { 573 u8 reserved_0[0x8]; 574 u8 priority[0x3]; 575 u8 reserved_1[0x2]; 576 u8 sel[0x3]; 577 u8 protocol_id[0x10]; 578}; 579 580struct mlx5_ifc_nodnic_ring_doorbell_bits { 581 u8 reserved_0[0x8]; 582 u8 ring_pi[0x10]; 583 u8 reserved_1[0x8]; 584}; 585 586enum { 587 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 588 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 589 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 590 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 591 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 592 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 593 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 594 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 595 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 596 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 597}; 598 599struct mlx5_ifc_ads_bits { 600 u8 fl[0x1]; 601 u8 free_ar[0x1]; 602 u8 reserved_0[0xe]; 603 u8 pkey_index[0x10]; 604 605 u8 reserved_1[0x8]; 606 u8 grh[0x1]; 607 u8 mlid[0x7]; 608 u8 rlid[0x10]; 609 610 u8 ack_timeout[0x5]; 611 u8 reserved_2[0x3]; 612 u8 src_addr_index[0x8]; 613 u8 log_rtm[0x4]; 614 u8 stat_rate[0x4]; 615 u8 hop_limit[0x8]; 616 617 u8 reserved_3[0x4]; 618 u8 tclass[0x8]; 619 u8 flow_label[0x14]; 620 621 u8 rgid_rip[16][0x8]; 622 623 u8 reserved_4[0x4]; 624 u8 f_dscp[0x1]; 625 u8 f_ecn[0x1]; 626 u8 reserved_5[0x1]; 627 u8 f_eth_prio[0x1]; 628 u8 ecn[0x2]; 629 u8 dscp[0x6]; 630 u8 udp_sport[0x10]; 631 632 u8 dei_cfi[0x1]; 633 u8 eth_prio[0x3]; 634 u8 sl[0x4]; 635 u8 port[0x8]; 636 u8 rmac_47_32[0x10]; 637 638 u8 rmac_31_0[0x20]; 639}; 640 641struct mlx5_ifc_diagnostic_counter_cap_bits { 642 u8 sync[0x1]; 643 u8 reserved_0[0xf]; 644 u8 counter_id[0x10]; 645}; 646 647struct mlx5_ifc_debug_cap_bits { 648 u8 reserved_0[0x18]; 649 u8 log_max_samples[0x8]; 650 651 u8 single[0x1]; 652 u8 repetitive[0x1]; 653 u8 health_mon_rx_activity[0x1]; 654 u8 reserved_1[0x15]; 655 u8 log_min_sample_period[0x8]; 656 657 u8 reserved_2[0x1c0]; 658 659 struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0]; 660}; 661 662struct mlx5_ifc_qos_cap_bits { 663 u8 packet_pacing[0x1]; 664 u8 esw_scheduling[0x1]; 665 u8 esw_bw_share[0x1]; 666 u8 esw_rate_limit[0x1]; 667 u8 hll[0x1]; 668 u8 packet_pacing_burst_bound[0x1]; 669 u8 reserved_at_6[0x1a]; 670 671 u8 reserved_at_20[0x20]; 672 673 u8 packet_pacing_max_rate[0x20]; 674 675 u8 packet_pacing_min_rate[0x20]; 676 677 u8 reserved_at_80[0x10]; 678 u8 packet_pacing_rate_table_size[0x10]; 679 680 u8 esw_element_type[0x10]; 681 u8 esw_tsar_type[0x10]; 682 683 u8 reserved_at_c0[0x10]; 684 u8 max_qos_para_vport[0x10]; 685 686 u8 max_tsar_bw_share[0x20]; 687 688 u8 reserved_at_100[0x700]; 689}; 690 691struct mlx5_ifc_snapshot_cap_bits { 692 u8 reserved_0[0x1d]; 693 u8 suspend_qp_uc[0x1]; 694 u8 suspend_qp_ud[0x1]; 695 u8 suspend_qp_rc[0x1]; 696 697 u8 reserved_1[0x1c]; 698 u8 restore_pd[0x1]; 699 u8 restore_uar[0x1]; 700 u8 restore_mkey[0x1]; 701 u8 restore_qp[0x1]; 702 703 u8 reserved_2[0x1e]; 704 u8 named_mkey[0x1]; 705 u8 named_qp[0x1]; 706 707 u8 reserved_3[0x7a0]; 708}; 709 710struct mlx5_ifc_e_switch_cap_bits { 711 u8 vport_svlan_strip[0x1]; 712 u8 vport_cvlan_strip[0x1]; 713 u8 vport_svlan_insert[0x1]; 714 u8 vport_cvlan_insert_if_not_exist[0x1]; 715 u8 vport_cvlan_insert_overwrite[0x1]; 716 717 u8 reserved_0[0x19]; 718 719 u8 nic_vport_node_guid_modify[0x1]; 720 u8 nic_vport_port_guid_modify[0x1]; 721 722 u8 reserved_1[0x7e0]; 723}; 724 725struct mlx5_ifc_flow_table_eswitch_cap_bits { 726 u8 reserved_0[0x200]; 727 728 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 729 730 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 731 732 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 733 734 u8 reserved_1[0x7800]; 735}; 736 737struct mlx5_ifc_flow_table_nic_cap_bits { 738 u8 nic_rx_multi_path_tirs[0x1]; 739 u8 nic_rx_multi_path_tirs_fts[0x1]; 740 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 741 u8 reserved_at_3[0x1fd]; 742 743 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 744 745 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 746 747 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 748 749 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 750 751 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 752 753 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 754 755 u8 reserved_1[0x7200]; 756}; 757 758struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 759 u8 csum_cap[0x1]; 760 u8 vlan_cap[0x1]; 761 u8 lro_cap[0x1]; 762 u8 lro_psh_flag[0x1]; 763 u8 lro_time_stamp[0x1]; 764 u8 lro_max_msg_sz_mode[0x2]; 765 u8 wqe_vlan_insert[0x1]; 766 u8 self_lb_en_modifiable[0x1]; 767 u8 self_lb_mc[0x1]; 768 u8 self_lb_uc[0x1]; 769 u8 max_lso_cap[0x5]; 770 u8 multi_pkt_send_wqe[0x2]; 771 u8 wqe_inline_mode[0x2]; 772 u8 rss_ind_tbl_cap[0x4]; 773 u8 scatter_fcs[0x1]; 774 u8 reserved_1[0x2]; 775 u8 tunnel_lso_const_out_ip_id[0x1]; 776 u8 tunnel_lro_gre[0x1]; 777 u8 tunnel_lro_vxlan[0x1]; 778 u8 tunnel_statless_gre[0x1]; 779 u8 tunnel_stateless_vxlan[0x1]; 780 781 u8 swp[0x1]; 782 u8 swp_csum[0x1]; 783 u8 swp_lso[0x1]; 784 u8 reserved_2[0x1b]; 785 u8 max_geneve_opt_len[0x1]; 786 u8 tunnel_stateless_geneve_rx[0x1]; 787 788 u8 reserved_3[0x10]; 789 u8 lro_min_mss_size[0x10]; 790 791 u8 reserved_4[0x120]; 792 793 u8 lro_timer_supported_periods[4][0x20]; 794 795 u8 reserved_5[0x600]; 796}; 797 798enum { 799 MLX5_ROCE_CAP_L3_TYPE_GRH = 0x1, 800 MLX5_ROCE_CAP_L3_TYPE_IPV4 = 0x2, 801 MLX5_ROCE_CAP_L3_TYPE_IPV6 = 0x4, 802}; 803 804struct mlx5_ifc_roce_cap_bits { 805 u8 roce_apm[0x1]; 806 u8 rts2rts_primary_eth_prio[0x1]; 807 u8 roce_rx_allow_untagged[0x1]; 808 u8 rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1]; 809 810 u8 reserved_0[0x1c]; 811 812 u8 reserved_1[0x60]; 813 814 u8 reserved_2[0xc]; 815 u8 l3_type[0x4]; 816 u8 reserved_3[0x8]; 817 u8 roce_version[0x8]; 818 819 u8 reserved_4[0x10]; 820 u8 r_roce_dest_udp_port[0x10]; 821 822 u8 r_roce_max_src_udp_port[0x10]; 823 u8 r_roce_min_src_udp_port[0x10]; 824 825 u8 reserved_5[0x10]; 826 u8 roce_address_table_size[0x10]; 827 828 u8 reserved_6[0x700]; 829}; 830 831enum { 832 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x1, 833 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 834 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 835 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 836 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 837 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 838 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 839 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 840 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 841}; 842 843enum { 844 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 845 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 846 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 847 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 848 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 849 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 850 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 851 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 852 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 853}; 854 855struct mlx5_ifc_atomic_caps_bits { 856 u8 reserved_0[0x40]; 857 858 u8 atomic_req_8B_endianess_mode[0x2]; 859 u8 reserved_1[0x4]; 860 u8 supported_atomic_req_8B_endianess_mode_1[0x1]; 861 862 u8 reserved_2[0x19]; 863 864 u8 reserved_3[0x20]; 865 866 u8 reserved_4[0x10]; 867 u8 atomic_operations[0x10]; 868 869 u8 reserved_5[0x10]; 870 u8 atomic_size_qp[0x10]; 871 872 u8 reserved_6[0x10]; 873 u8 atomic_size_dc[0x10]; 874 875 u8 reserved_7[0x720]; 876}; 877 878struct mlx5_ifc_odp_cap_bits { 879 u8 reserved_0[0x40]; 880 881 u8 sig[0x1]; 882 u8 reserved_1[0x1f]; 883 884 u8 reserved_2[0x20]; 885 886 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 887 888 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 889 890 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 891 892 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 893 894 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 895 896 u8 reserved_3[0x6e0]; 897}; 898 899enum { 900 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 901 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 902 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 903 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 904 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 905}; 906 907enum { 908 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 909 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 910 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 911 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 912 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 913 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 914}; 915 916enum { 917 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 918 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 919}; 920 921enum { 922 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 923 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 924 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 925}; 926 927struct mlx5_ifc_cmd_hca_cap_bits { 928 u8 reserved_0[0x80]; 929 930 u8 log_max_srq_sz[0x8]; 931 u8 log_max_qp_sz[0x8]; 932 u8 reserved_1[0xb]; 933 u8 log_max_qp[0x5]; 934 935 u8 reserved_2[0xb]; 936 u8 log_max_srq[0x5]; 937 u8 reserved_3[0x10]; 938 939 u8 reserved_4[0x8]; 940 u8 log_max_cq_sz[0x8]; 941 u8 reserved_5[0xb]; 942 u8 log_max_cq[0x5]; 943 944 u8 log_max_eq_sz[0x8]; 945 u8 relaxed_ordering_write[1]; 946 u8 reserved_6[0x1]; 947 u8 log_max_mkey[0x6]; 948 u8 reserved_7[0xc]; 949 u8 log_max_eq[0x4]; 950 951 u8 max_indirection[0x8]; 952 u8 reserved_8[0x1]; 953 u8 log_max_mrw_sz[0x7]; 954 u8 force_teardown[0x1]; 955 u8 reserved_9[0x1]; 956 u8 log_max_bsf_list_size[0x6]; 957 u8 reserved_10[0x2]; 958 u8 log_max_klm_list_size[0x6]; 959 960 u8 reserved_11[0xa]; 961 u8 log_max_ra_req_dc[0x6]; 962 u8 reserved_12[0xa]; 963 u8 log_max_ra_res_dc[0x6]; 964 965 u8 reserved_13[0xa]; 966 u8 log_max_ra_req_qp[0x6]; 967 u8 reserved_14[0xa]; 968 u8 log_max_ra_res_qp[0x6]; 969 970 u8 pad_cap[0x1]; 971 u8 cc_query_allowed[0x1]; 972 u8 cc_modify_allowed[0x1]; 973 u8 start_pad[0x1]; 974 u8 cache_line_128byte[0x1]; 975 u8 reserved_at_165[0xa]; 976 u8 qcam_reg[0x1]; 977 u8 gid_table_size[0x10]; 978 979 u8 out_of_seq_cnt[0x1]; 980 u8 vport_counters[0x1]; 981 u8 retransmission_q_counters[0x1]; 982 u8 debug[0x1]; 983 u8 modify_rq_counters_set_id[0x1]; 984 u8 rq_delay_drop[0x1]; 985 u8 max_qp_cnt[0xa]; 986 u8 pkey_table_size[0x10]; 987 988 u8 vport_group_manager[0x1]; 989 u8 vhca_group_manager[0x1]; 990 u8 ib_virt[0x1]; 991 u8 eth_virt[0x1]; 992 u8 reserved_17[0x1]; 993 u8 ets[0x1]; 994 u8 nic_flow_table[0x1]; 995 u8 eswitch_flow_table[0x1]; 996 u8 reserved_18[0x3]; 997 u8 local_ca_ack_delay[0x5]; 998 u8 port_module_event[0x1]; 999 u8 reserved_19[0x5]; 1000 u8 port_type[0x2]; 1001 u8 num_ports[0x8]; 1002 1003 u8 snapshot[0x1]; 1004 u8 reserved_20[0x2]; 1005 u8 log_max_msg[0x5]; 1006 u8 reserved_21[0x4]; 1007 u8 max_tc[0x4]; 1008 u8 temp_warn_event[0x1]; 1009 u8 dcbx[0x1]; 1010 u8 general_notification_event[0x1]; 1011 u8 reserved_at_1d3[0x2]; 1012 u8 fpga[0x1]; 1013 u8 rol_s[0x1]; 1014 u8 rol_g[0x1]; 1015 u8 reserved_23[0x1]; 1016 u8 wol_s[0x1]; 1017 u8 wol_g[0x1]; 1018 u8 wol_a[0x1]; 1019 u8 wol_b[0x1]; 1020 u8 wol_m[0x1]; 1021 u8 wol_u[0x1]; 1022 u8 wol_p[0x1]; 1023 1024 u8 stat_rate_support[0x10]; 1025 u8 reserved_24[0xc]; 1026 u8 cqe_version[0x4]; 1027 1028 u8 compact_address_vector[0x1]; 1029 u8 striding_rq[0x1]; 1030 u8 reserved_25[0x1]; 1031 u8 ipoib_enhanced_offloads[0x1]; 1032 u8 ipoib_ipoib_offloads[0x1]; 1033 u8 reserved_26[0x8]; 1034 u8 dc_connect_qp[0x1]; 1035 u8 dc_cnak_trace[0x1]; 1036 u8 drain_sigerr[0x1]; 1037 u8 cmdif_checksum[0x2]; 1038 u8 sigerr_cqe[0x1]; 1039 u8 reserved_27[0x1]; 1040 u8 wq_signature[0x1]; 1041 u8 sctr_data_cqe[0x1]; 1042 u8 reserved_28[0x1]; 1043 u8 sho[0x1]; 1044 u8 tph[0x1]; 1045 u8 rf[0x1]; 1046 u8 dct[0x1]; 1047 u8 qos[0x1]; 1048 u8 eth_net_offloads[0x1]; 1049 u8 roce[0x1]; 1050 u8 atomic[0x1]; 1051 u8 reserved_30[0x1]; 1052 1053 u8 cq_oi[0x1]; 1054 u8 cq_resize[0x1]; 1055 u8 cq_moderation[0x1]; 1056 u8 cq_period_mode_modify[0x1]; 1057 u8 cq_invalidate[0x1]; 1058 u8 reserved_at_225[0x1]; 1059 u8 cq_eq_remap[0x1]; 1060 u8 pg[0x1]; 1061 u8 block_lb_mc[0x1]; 1062 u8 exponential_backoff[0x1]; 1063 u8 scqe_break_moderation[0x1]; 1064 u8 cq_period_start_from_cqe[0x1]; 1065 u8 cd[0x1]; 1066 u8 atm[0x1]; 1067 u8 apm[0x1]; 1068 u8 imaicl[0x1]; 1069 u8 reserved_32[0x6]; 1070 u8 qkv[0x1]; 1071 u8 pkv[0x1]; 1072 u8 set_deth_sqpn[0x1]; 1073 u8 reserved_33[0x3]; 1074 u8 xrc[0x1]; 1075 u8 ud[0x1]; 1076 u8 uc[0x1]; 1077 u8 rc[0x1]; 1078 1079 u8 reserved_34[0xa]; 1080 u8 uar_sz[0x6]; 1081 u8 reserved_35[0x8]; 1082 u8 log_pg_sz[0x8]; 1083 1084 u8 bf[0x1]; 1085 u8 driver_version[0x1]; 1086 u8 pad_tx_eth_packet[0x1]; 1087 u8 reserved_36[0x8]; 1088 u8 log_bf_reg_size[0x5]; 1089 u8 reserved_37[0x10]; 1090 1091 u8 num_of_diagnostic_counters[0x10]; 1092 u8 max_wqe_sz_sq[0x10]; 1093 1094 u8 reserved_38[0x10]; 1095 u8 max_wqe_sz_rq[0x10]; 1096 1097 u8 reserved_39[0x10]; 1098 u8 max_wqe_sz_sq_dc[0x10]; 1099 1100 u8 reserved_40[0x7]; 1101 u8 max_qp_mcg[0x19]; 1102 1103 u8 reserved_41[0x18]; 1104 u8 log_max_mcg[0x8]; 1105 1106 u8 reserved_42[0x3]; 1107 u8 log_max_transport_domain[0x5]; 1108 u8 reserved_43[0x3]; 1109 u8 log_max_pd[0x5]; 1110 u8 reserved_44[0xb]; 1111 u8 log_max_xrcd[0x5]; 1112 1113 u8 reserved_45[0x10]; 1114 u8 max_flow_counter[0x10]; 1115 1116 u8 reserved_46[0x3]; 1117 u8 log_max_rq[0x5]; 1118 u8 reserved_47[0x3]; 1119 u8 log_max_sq[0x5]; 1120 u8 reserved_48[0x3]; 1121 u8 log_max_tir[0x5]; 1122 u8 reserved_49[0x3]; 1123 u8 log_max_tis[0x5]; 1124 1125 u8 basic_cyclic_rcv_wqe[0x1]; 1126 u8 reserved_50[0x2]; 1127 u8 log_max_rmp[0x5]; 1128 u8 reserved_51[0x3]; 1129 u8 log_max_rqt[0x5]; 1130 u8 reserved_52[0x3]; 1131 u8 log_max_rqt_size[0x5]; 1132 u8 reserved_53[0x3]; 1133 u8 log_max_tis_per_sq[0x5]; 1134 1135 u8 reserved_54[0x3]; 1136 u8 log_max_stride_sz_rq[0x5]; 1137 u8 reserved_55[0x3]; 1138 u8 log_min_stride_sz_rq[0x5]; 1139 u8 reserved_56[0x3]; 1140 u8 log_max_stride_sz_sq[0x5]; 1141 u8 reserved_57[0x3]; 1142 u8 log_min_stride_sz_sq[0x5]; 1143 1144 u8 reserved_58[0x1b]; 1145 u8 log_max_wq_sz[0x5]; 1146 1147 u8 nic_vport_change_event[0x1]; 1148 u8 disable_local_lb[0x1]; 1149 u8 reserved_59[0x9]; 1150 u8 log_max_vlan_list[0x5]; 1151 u8 reserved_60[0x3]; 1152 u8 log_max_current_mc_list[0x5]; 1153 u8 reserved_61[0x3]; 1154 u8 log_max_current_uc_list[0x5]; 1155 1156 u8 reserved_62[0x80]; 1157 1158 u8 reserved_63[0x3]; 1159 u8 log_max_l2_table[0x5]; 1160 u8 reserved_64[0x8]; 1161 u8 log_uar_page_sz[0x10]; 1162 1163 u8 reserved_65[0x20]; 1164 1165 u8 device_frequency_mhz[0x20]; 1166 1167 u8 device_frequency_khz[0x20]; 1168 1169 u8 reserved_66[0x80]; 1170 1171 u8 log_max_atomic_size_qp[0x8]; 1172 u8 reserved_67[0x10]; 1173 u8 log_max_atomic_size_dc[0x8]; 1174 1175 u8 reserved_68[0x1f]; 1176 u8 cqe_compression[0x1]; 1177 1178 u8 cqe_compression_timeout[0x10]; 1179 u8 cqe_compression_max_num[0x10]; 1180 1181 u8 reserved_69[0x220]; 1182}; 1183 1184enum mlx5_flow_destination_type { 1185 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1186 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1187 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1188}; 1189 1190union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1191 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1192 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1193 u8 reserved_0[0x40]; 1194}; 1195 1196struct mlx5_ifc_fte_match_param_bits { 1197 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1198 1199 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1200 1201 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1202 1203 u8 reserved_0[0xa00]; 1204}; 1205 1206enum { 1207 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1208 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1209 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1210 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1211 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1212}; 1213 1214struct mlx5_ifc_rx_hash_field_select_bits { 1215 u8 l3_prot_type[0x1]; 1216 u8 l4_prot_type[0x1]; 1217 u8 selected_fields[0x1e]; 1218}; 1219 1220enum { 1221 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1222 MLX5_WQ_TYPE_CYCLIC = 0x1, 1223 MLX5_WQ_TYPE_STRQ_LINKED_LIST = 0x2, 1224 MLX5_WQ_TYPE_STRQ_CYCLIC = 0x3, 1225}; 1226 1227enum rq_type { 1228 RQ_TYPE_NONE, 1229 RQ_TYPE_STRIDE, 1230}; 1231 1232enum { 1233 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1234 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1235}; 1236 1237struct mlx5_ifc_wq_bits { 1238 u8 wq_type[0x4]; 1239 u8 wq_signature[0x1]; 1240 u8 end_padding_mode[0x2]; 1241 u8 cd_slave[0x1]; 1242 u8 reserved_0[0x18]; 1243 1244 u8 hds_skip_first_sge[0x1]; 1245 u8 log2_hds_buf_size[0x3]; 1246 u8 reserved_1[0x7]; 1247 u8 page_offset[0x5]; 1248 u8 lwm[0x10]; 1249 1250 u8 reserved_2[0x8]; 1251 u8 pd[0x18]; 1252 1253 u8 reserved_3[0x8]; 1254 u8 uar_page[0x18]; 1255 1256 u8 dbr_addr[0x40]; 1257 1258 u8 hw_counter[0x20]; 1259 1260 u8 sw_counter[0x20]; 1261 1262 u8 reserved_4[0xc]; 1263 u8 log_wq_stride[0x4]; 1264 u8 reserved_5[0x3]; 1265 u8 log_wq_pg_sz[0x5]; 1266 u8 reserved_6[0x3]; 1267 u8 log_wq_sz[0x5]; 1268 1269 u8 reserved_7[0x15]; 1270 u8 single_wqe_log_num_of_strides[0x3]; 1271 u8 two_byte_shift_en[0x1]; 1272 u8 reserved_8[0x4]; 1273 u8 single_stride_log_num_of_bytes[0x3]; 1274 1275 u8 reserved_9[0x4c0]; 1276 1277 struct mlx5_ifc_cmd_pas_bits pas[0]; 1278}; 1279 1280struct mlx5_ifc_rq_num_bits { 1281 u8 reserved_0[0x8]; 1282 u8 rq_num[0x18]; 1283}; 1284 1285struct mlx5_ifc_mac_address_layout_bits { 1286 u8 reserved_0[0x10]; 1287 u8 mac_addr_47_32[0x10]; 1288 1289 u8 mac_addr_31_0[0x20]; 1290}; 1291 1292struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1293 u8 reserved_0[0xa0]; 1294 1295 u8 min_time_between_cnps[0x20]; 1296 1297 u8 reserved_1[0x12]; 1298 u8 cnp_dscp[0x6]; 1299 u8 reserved_2[0x4]; 1300 u8 cnp_prio_mode[0x1]; 1301 u8 cnp_802p_prio[0x3]; 1302 1303 u8 reserved_3[0x720]; 1304}; 1305 1306struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1307 u8 reserved_0[0x60]; 1308 1309 u8 reserved_1[0x4]; 1310 u8 clamp_tgt_rate[0x1]; 1311 u8 reserved_2[0x3]; 1312 u8 clamp_tgt_rate_after_time_inc[0x1]; 1313 u8 reserved_3[0x17]; 1314 1315 u8 reserved_4[0x20]; 1316 1317 u8 rpg_time_reset[0x20]; 1318 1319 u8 rpg_byte_reset[0x20]; 1320 1321 u8 rpg_threshold[0x20]; 1322 1323 u8 rpg_max_rate[0x20]; 1324 1325 u8 rpg_ai_rate[0x20]; 1326 1327 u8 rpg_hai_rate[0x20]; 1328 1329 u8 rpg_gd[0x20]; 1330 1331 u8 rpg_min_dec_fac[0x20]; 1332 1333 u8 rpg_min_rate[0x20]; 1334 1335 u8 reserved_5[0xe0]; 1336 1337 u8 rate_to_set_on_first_cnp[0x20]; 1338 1339 u8 dce_tcp_g[0x20]; 1340 1341 u8 dce_tcp_rtt[0x20]; 1342 1343 u8 rate_reduce_monitor_period[0x20]; 1344 1345 u8 reserved_6[0x20]; 1346 1347 u8 initial_alpha_value[0x20]; 1348 1349 u8 reserved_7[0x4a0]; 1350}; 1351 1352struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1353 u8 reserved_0[0x80]; 1354 1355 u8 rppp_max_rps[0x20]; 1356 1357 u8 rpg_time_reset[0x20]; 1358 1359 u8 rpg_byte_reset[0x20]; 1360 1361 u8 rpg_threshold[0x20]; 1362 1363 u8 rpg_max_rate[0x20]; 1364 1365 u8 rpg_ai_rate[0x20]; 1366 1367 u8 rpg_hai_rate[0x20]; 1368 1369 u8 rpg_gd[0x20]; 1370 1371 u8 rpg_min_dec_fac[0x20]; 1372 1373 u8 rpg_min_rate[0x20]; 1374 1375 u8 reserved_1[0x640]; 1376}; 1377 1378enum { 1379 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1380 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1381 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1382}; 1383 1384struct mlx5_ifc_resize_field_select_bits { 1385 u8 resize_field_select[0x20]; 1386}; 1387 1388enum { 1389 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1390 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1391 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1392 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1393 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE = 0x10, 1394 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS = 0x20, 1395}; 1396 1397struct mlx5_ifc_modify_field_select_bits { 1398 u8 modify_field_select[0x20]; 1399}; 1400 1401struct mlx5_ifc_field_select_r_roce_np_bits { 1402 u8 field_select_r_roce_np[0x20]; 1403}; 1404 1405enum { 1406 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE = 0x2, 1407 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC = 0x4, 1408 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET = 0x8, 1409 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET = 0x10, 1410 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD = 0x20, 1411 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE = 0x40, 1412 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE = 0x80, 1413 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE = 0x100, 1414 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC = 0x200, 1415 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE = 0x400, 1416 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP = 0x800, 1417 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G = 0x1000, 1418 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT = 0x2000, 1419 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD = 0x4000, 1420 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE = 0x8000, 1421}; 1422 1423struct mlx5_ifc_field_select_r_roce_rp_bits { 1424 u8 field_select_r_roce_rp[0x20]; 1425}; 1426 1427enum { 1428 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1429 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1430 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1431 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1432 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1433 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1434 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1435 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1436 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1437 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1438}; 1439 1440struct mlx5_ifc_field_select_802_1qau_rp_bits { 1441 u8 field_select_8021qaurp[0x20]; 1442}; 1443 1444struct mlx5_ifc_pptb_reg_bits { 1445 u8 reserved_0[0x2]; 1446 u8 mm[0x2]; 1447 u8 reserved_1[0x4]; 1448 u8 local_port[0x8]; 1449 u8 reserved_2[0x6]; 1450 u8 cm[0x1]; 1451 u8 um[0x1]; 1452 u8 pm[0x8]; 1453 1454 u8 prio7buff[0x4]; 1455 u8 prio6buff[0x4]; 1456 u8 prio5buff[0x4]; 1457 u8 prio4buff[0x4]; 1458 u8 prio3buff[0x4]; 1459 u8 prio2buff[0x4]; 1460 u8 prio1buff[0x4]; 1461 u8 prio0buff[0x4]; 1462 1463 u8 pm_msb[0x8]; 1464 u8 reserved_3[0x10]; 1465 u8 ctrl_buff[0x4]; 1466 u8 untagged_buff[0x4]; 1467}; 1468 1469struct mlx5_ifc_dcbx_app_reg_bits { 1470 u8 reserved_0[0x8]; 1471 u8 port_number[0x8]; 1472 u8 reserved_1[0x10]; 1473 1474 u8 reserved_2[0x1a]; 1475 u8 num_app_prio[0x6]; 1476 1477 u8 reserved_3[0x40]; 1478 1479 struct mlx5_ifc_application_prio_entry_bits app_prio[0]; 1480}; 1481 1482struct mlx5_ifc_dcbx_param_reg_bits { 1483 u8 dcbx_cee_cap[0x1]; 1484 u8 dcbx_ieee_cap[0x1]; 1485 u8 dcbx_standby_cap[0x1]; 1486 u8 reserved_0[0x5]; 1487 u8 port_number[0x8]; 1488 u8 reserved_1[0xa]; 1489 u8 max_application_table_size[0x6]; 1490 1491 u8 reserved_2[0x15]; 1492 u8 version_oper[0x3]; 1493 u8 reserved_3[0x5]; 1494 u8 version_admin[0x3]; 1495 1496 u8 willing_admin[0x1]; 1497 u8 reserved_4[0x3]; 1498 u8 pfc_cap_oper[0x4]; 1499 u8 reserved_5[0x4]; 1500 u8 pfc_cap_admin[0x4]; 1501 u8 reserved_6[0x4]; 1502 u8 num_of_tc_oper[0x4]; 1503 u8 reserved_7[0x4]; 1504 u8 num_of_tc_admin[0x4]; 1505 1506 u8 remote_willing[0x1]; 1507 u8 reserved_8[0x3]; 1508 u8 remote_pfc_cap[0x4]; 1509 u8 reserved_9[0x14]; 1510 u8 remote_num_of_tc[0x4]; 1511 1512 u8 reserved_10[0x18]; 1513 u8 error[0x8]; 1514 1515 u8 reserved_11[0x160]; 1516}; 1517 1518struct mlx5_ifc_qhll_bits { 1519 u8 reserved_at_0[0x8]; 1520 u8 local_port[0x8]; 1521 u8 reserved_at_10[0x10]; 1522 1523 u8 reserved_at_20[0x1b]; 1524 u8 hll_time[0x5]; 1525 1526 u8 stall_en[0x1]; 1527 u8 reserved_at_41[0x1c]; 1528 u8 stall_cnt[0x3]; 1529}; 1530 1531struct mlx5_ifc_qetcr_reg_bits { 1532 u8 operation_type[0x2]; 1533 u8 cap_local_admin[0x1]; 1534 u8 cap_remote_admin[0x1]; 1535 u8 reserved_0[0x4]; 1536 u8 port_number[0x8]; 1537 u8 reserved_1[0x10]; 1538 1539 u8 reserved_2[0x20]; 1540 1541 u8 tc[8][0x40]; 1542 1543 u8 global_configuration[0x40]; 1544}; 1545 1546struct mlx5_ifc_nodnic_ring_config_reg_bits { 1547 u8 queue_address_63_32[0x20]; 1548 1549 u8 queue_address_31_12[0x14]; 1550 u8 reserved_0[0x6]; 1551 u8 log_size[0x6]; 1552 1553 struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell; 1554 1555 u8 reserved_1[0x8]; 1556 u8 queue_number[0x18]; 1557 1558 u8 q_key[0x20]; 1559 1560 u8 reserved_2[0x10]; 1561 u8 pkey_index[0x10]; 1562 1563 u8 reserved_3[0x40]; 1564}; 1565 1566struct mlx5_ifc_nodnic_cq_arming_word_bits { 1567 u8 reserved_0[0x8]; 1568 u8 cq_ci[0x10]; 1569 u8 reserved_1[0x8]; 1570}; 1571 1572enum { 1573 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND = 0x0, 1574 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET = 0x1, 1575}; 1576 1577enum { 1578 MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN = 0x0, 1579 MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE = 0x1, 1580 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED = 0x2, 1581 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE = 0x3, 1582}; 1583 1584struct mlx5_ifc_nodnic_event_word_bits { 1585 u8 driver_reset_needed[0x1]; 1586 u8 port_management_change_event[0x1]; 1587 u8 reserved_0[0x19]; 1588 u8 link_type[0x1]; 1589 u8 port_state[0x4]; 1590}; 1591 1592struct mlx5_ifc_nic_vport_change_event_bits { 1593 u8 reserved_0[0x10]; 1594 u8 vport_num[0x10]; 1595 1596 u8 reserved_1[0xc0]; 1597}; 1598 1599struct mlx5_ifc_pages_req_event_bits { 1600 u8 reserved_0[0x10]; 1601 u8 function_id[0x10]; 1602 1603 u8 num_pages[0x20]; 1604 1605 u8 reserved_1[0xa0]; 1606}; 1607 1608struct mlx5_ifc_cmd_inter_comp_event_bits { 1609 u8 command_completion_vector[0x20]; 1610 1611 u8 reserved_0[0xc0]; 1612}; 1613 1614struct mlx5_ifc_stall_vl_event_bits { 1615 u8 reserved_0[0x18]; 1616 u8 port_num[0x1]; 1617 u8 reserved_1[0x3]; 1618 u8 vl[0x4]; 1619 1620 u8 reserved_2[0xa0]; 1621}; 1622 1623struct mlx5_ifc_db_bf_congestion_event_bits { 1624 u8 event_subtype[0x8]; 1625 u8 reserved_0[0x8]; 1626 u8 congestion_level[0x8]; 1627 u8 reserved_1[0x8]; 1628 1629 u8 reserved_2[0xa0]; 1630}; 1631 1632struct mlx5_ifc_gpio_event_bits { 1633 u8 reserved_0[0x60]; 1634 1635 u8 gpio_event_hi[0x20]; 1636 1637 u8 gpio_event_lo[0x20]; 1638 1639 u8 reserved_1[0x40]; 1640}; 1641 1642struct mlx5_ifc_port_state_change_event_bits { 1643 u8 reserved_0[0x40]; 1644 1645 u8 port_num[0x4]; 1646 u8 reserved_1[0x1c]; 1647 1648 u8 reserved_2[0x80]; 1649}; 1650 1651struct mlx5_ifc_dropped_packet_logged_bits { 1652 u8 reserved_0[0xe0]; 1653}; 1654 1655enum { 1656 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 1657 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 1658}; 1659 1660struct mlx5_ifc_cq_error_bits { 1661 u8 reserved_0[0x8]; 1662 u8 cqn[0x18]; 1663 1664 u8 reserved_1[0x20]; 1665 1666 u8 reserved_2[0x18]; 1667 u8 syndrome[0x8]; 1668 1669 u8 reserved_3[0x80]; 1670}; 1671 1672struct mlx5_ifc_rdma_page_fault_event_bits { 1673 u8 bytes_commited[0x20]; 1674 1675 u8 r_key[0x20]; 1676 1677 u8 reserved_0[0x10]; 1678 u8 packet_len[0x10]; 1679 1680 u8 rdma_op_len[0x20]; 1681 1682 u8 rdma_va[0x40]; 1683 1684 u8 reserved_1[0x5]; 1685 u8 rdma[0x1]; 1686 u8 write[0x1]; 1687 u8 requestor[0x1]; 1688 u8 qp_number[0x18]; 1689}; 1690 1691struct mlx5_ifc_wqe_associated_page_fault_event_bits { 1692 u8 bytes_committed[0x20]; 1693 1694 u8 reserved_0[0x10]; 1695 u8 wqe_index[0x10]; 1696 1697 u8 reserved_1[0x10]; 1698 u8 len[0x10]; 1699 1700 u8 reserved_2[0x60]; 1701 1702 u8 reserved_3[0x5]; 1703 u8 rdma[0x1]; 1704 u8 write_read[0x1]; 1705 u8 requestor[0x1]; 1706 u8 qpn[0x18]; 1707}; 1708 1709enum { 1710 MLX5_QP_EVENTS_TYPE_QP = 0x0, 1711 MLX5_QP_EVENTS_TYPE_RQ = 0x1, 1712 MLX5_QP_EVENTS_TYPE_SQ = 0x2, 1713}; 1714 1715struct mlx5_ifc_qp_events_bits { 1716 u8 reserved_0[0xa0]; 1717 1718 u8 type[0x8]; 1719 u8 reserved_1[0x18]; 1720 1721 u8 reserved_2[0x8]; 1722 u8 qpn_rqn_sqn[0x18]; 1723}; 1724 1725struct mlx5_ifc_dct_events_bits { 1726 u8 reserved_0[0xc0]; 1727 1728 u8 reserved_1[0x8]; 1729 u8 dct_number[0x18]; 1730}; 1731 1732struct mlx5_ifc_comp_event_bits { 1733 u8 reserved_0[0xc0]; 1734 1735 u8 reserved_1[0x8]; 1736 u8 cq_number[0x18]; 1737}; 1738 1739struct mlx5_ifc_fw_version_bits { 1740 u8 major[0x10]; 1741 u8 reserved_0[0x10]; 1742 1743 u8 minor[0x10]; 1744 u8 subminor[0x10]; 1745 1746 u8 second[0x8]; 1747 u8 minute[0x8]; 1748 u8 hour[0x8]; 1749 u8 reserved_1[0x8]; 1750 1751 u8 year[0x10]; 1752 u8 month[0x8]; 1753 u8 day[0x8]; 1754}; 1755 1756enum { 1757 MLX5_QPC_STATE_RST = 0x0, 1758 MLX5_QPC_STATE_INIT = 0x1, 1759 MLX5_QPC_STATE_RTR = 0x2, 1760 MLX5_QPC_STATE_RTS = 0x3, 1761 MLX5_QPC_STATE_SQER = 0x4, 1762 MLX5_QPC_STATE_SQD = 0x5, 1763 MLX5_QPC_STATE_ERR = 0x6, 1764 MLX5_QPC_STATE_SUSPENDED = 0x9, 1765}; 1766 1767enum { 1768 MLX5_QPC_ST_RC = 0x0, 1769 MLX5_QPC_ST_UC = 0x1, 1770 MLX5_QPC_ST_UD = 0x2, 1771 MLX5_QPC_ST_XRC = 0x3, 1772 MLX5_QPC_ST_DCI = 0x5, 1773 MLX5_QPC_ST_QP0 = 0x7, 1774 MLX5_QPC_ST_QP1 = 0x8, 1775 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 1776 MLX5_QPC_ST_REG_UMR = 0xc, 1777}; 1778 1779enum { 1780 MLX5_QP_PM_ARMED = 0x0, 1781 MLX5_QP_PM_REARM = 0x1, 1782 MLX5_QPC_PM_STATE_RESERVED = 0x2, 1783 MLX5_QP_PM_MIGRATED = 0x3, 1784}; 1785 1786enum { 1787 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 1788 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 1789}; 1790 1791enum { 1792 MLX5_QPC_MTU_256_BYTES = 0x1, 1793 MLX5_QPC_MTU_512_BYTES = 0x2, 1794 MLX5_QPC_MTU_1K_BYTES = 0x3, 1795 MLX5_QPC_MTU_2K_BYTES = 0x4, 1796 MLX5_QPC_MTU_4K_BYTES = 0x5, 1797 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 1798}; 1799 1800enum { 1801 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 1802 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 1803 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 1804 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 1805 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 1806 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 1807 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 1808 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 1809}; 1810 1811enum { 1812 MLX5_QPC_CS_REQ_DISABLE = 0x0, 1813 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 1814 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 1815}; 1816 1817enum { 1818 MLX5_QPC_CS_RES_DISABLE = 0x0, 1819 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 1820 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 1821}; 1822 1823struct mlx5_ifc_qpc_bits { 1824 u8 state[0x4]; 1825 u8 lag_tx_port_affinity[0x4]; 1826 u8 st[0x8]; 1827 u8 reserved_1[0x3]; 1828 u8 pm_state[0x2]; 1829 u8 reserved_2[0x7]; 1830 u8 end_padding_mode[0x2]; 1831 u8 reserved_3[0x2]; 1832 1833 u8 wq_signature[0x1]; 1834 u8 block_lb_mc[0x1]; 1835 u8 atomic_like_write_en[0x1]; 1836 u8 latency_sensitive[0x1]; 1837 u8 reserved_4[0x1]; 1838 u8 drain_sigerr[0x1]; 1839 u8 reserved_5[0x2]; 1840 u8 pd[0x18]; 1841 1842 u8 mtu[0x3]; 1843 u8 log_msg_max[0x5]; 1844 u8 reserved_6[0x1]; 1845 u8 log_rq_size[0x4]; 1846 u8 log_rq_stride[0x3]; 1847 u8 no_sq[0x1]; 1848 u8 log_sq_size[0x4]; 1849 u8 reserved_7[0x6]; 1850 u8 rlky[0x1]; 1851 u8 ulp_stateless_offload_mode[0x4]; 1852 1853 u8 counter_set_id[0x8]; 1854 u8 uar_page[0x18]; 1855 1856 u8 reserved_8[0x8]; 1857 u8 user_index[0x18]; 1858 1859 u8 reserved_9[0x3]; 1860 u8 log_page_size[0x5]; 1861 u8 remote_qpn[0x18]; 1862 1863 struct mlx5_ifc_ads_bits primary_address_path; 1864 1865 struct mlx5_ifc_ads_bits secondary_address_path; 1866 1867 u8 log_ack_req_freq[0x4]; 1868 u8 reserved_10[0x4]; 1869 u8 log_sra_max[0x3]; 1870 u8 reserved_11[0x2]; 1871 u8 retry_count[0x3]; 1872 u8 rnr_retry[0x3]; 1873 u8 reserved_12[0x1]; 1874 u8 fre[0x1]; 1875 u8 cur_rnr_retry[0x3]; 1876 u8 cur_retry_count[0x3]; 1877 u8 reserved_13[0x5]; 1878 1879 u8 reserved_14[0x20]; 1880 1881 u8 reserved_15[0x8]; 1882 u8 next_send_psn[0x18]; 1883 1884 u8 reserved_16[0x8]; 1885 u8 cqn_snd[0x18]; 1886 1887 u8 reserved_at_400[0x8]; 1888 1889 u8 deth_sqpn[0x18]; 1890 u8 reserved_17[0x20]; 1891 1892 u8 reserved_18[0x8]; 1893 u8 last_acked_psn[0x18]; 1894 1895 u8 reserved_19[0x8]; 1896 u8 ssn[0x18]; 1897 1898 u8 reserved_20[0x8]; 1899 u8 log_rra_max[0x3]; 1900 u8 reserved_21[0x1]; 1901 u8 atomic_mode[0x4]; 1902 u8 rre[0x1]; 1903 u8 rwe[0x1]; 1904 u8 rae[0x1]; 1905 u8 reserved_22[0x1]; 1906 u8 page_offset[0x6]; 1907 u8 reserved_23[0x3]; 1908 u8 cd_slave_receive[0x1]; 1909 u8 cd_slave_send[0x1]; 1910 u8 cd_master[0x1]; 1911 1912 u8 reserved_24[0x3]; 1913 u8 min_rnr_nak[0x5]; 1914 u8 next_rcv_psn[0x18]; 1915 1916 u8 reserved_25[0x8]; 1917 u8 xrcd[0x18]; 1918 1919 u8 reserved_26[0x8]; 1920 u8 cqn_rcv[0x18]; 1921 1922 u8 dbr_addr[0x40]; 1923 1924 u8 q_key[0x20]; 1925 1926 u8 reserved_27[0x5]; 1927 u8 rq_type[0x3]; 1928 u8 srqn_rmpn[0x18]; 1929 1930 u8 reserved_28[0x8]; 1931 u8 rmsn[0x18]; 1932 1933 u8 hw_sq_wqebb_counter[0x10]; 1934 u8 sw_sq_wqebb_counter[0x10]; 1935 1936 u8 hw_rq_counter[0x20]; 1937 1938 u8 sw_rq_counter[0x20]; 1939 1940 u8 reserved_29[0x20]; 1941 1942 u8 reserved_30[0xf]; 1943 u8 cgs[0x1]; 1944 u8 cs_req[0x8]; 1945 u8 cs_res[0x8]; 1946 1947 u8 dc_access_key[0x40]; 1948 1949 u8 rdma_active[0x1]; 1950 u8 comm_est[0x1]; 1951 u8 suspended[0x1]; 1952 u8 reserved_31[0x5]; 1953 u8 send_msg_psn[0x18]; 1954 1955 u8 reserved_32[0x8]; 1956 u8 rcv_msg_psn[0x18]; 1957 1958 u8 rdma_va[0x40]; 1959 1960 u8 rdma_key[0x20]; 1961 1962 u8 reserved_33[0x20]; 1963}; 1964 1965struct mlx5_ifc_roce_addr_layout_bits { 1966 u8 source_l3_address[16][0x8]; 1967 1968 u8 reserved_0[0x3]; 1969 u8 vlan_valid[0x1]; 1970 u8 vlan_id[0xc]; 1971 u8 source_mac_47_32[0x10]; 1972 1973 u8 source_mac_31_0[0x20]; 1974 1975 u8 reserved_1[0x14]; 1976 u8 roce_l3_type[0x4]; 1977 u8 roce_version[0x8]; 1978 1979 u8 reserved_2[0x20]; 1980}; 1981 1982struct mlx5_ifc_rdbc_bits { 1983 u8 reserved_0[0x1c]; 1984 u8 type[0x4]; 1985 1986 u8 reserved_1[0x20]; 1987 1988 u8 reserved_2[0x8]; 1989 u8 psn[0x18]; 1990 1991 u8 rkey[0x20]; 1992 1993 u8 address[0x40]; 1994 1995 u8 byte_count[0x20]; 1996 1997 u8 reserved_3[0x20]; 1998 1999 u8 atomic_resp[32][0x8]; 2000}; 2001 2002enum { 2003 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2004 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2005 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2006 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2007}; 2008 2009struct mlx5_ifc_flow_context_bits { 2010 u8 reserved_0[0x20]; 2011 2012 u8 group_id[0x20]; 2013 2014 u8 reserved_1[0x8]; 2015 u8 flow_tag[0x18]; 2016 2017 u8 reserved_2[0x10]; 2018 u8 action[0x10]; 2019 2020 u8 reserved_3[0x8]; 2021 u8 destination_list_size[0x18]; 2022 2023 u8 reserved_4[0x8]; 2024 u8 flow_counter_list_size[0x18]; 2025 2026 u8 reserved_5[0x140]; 2027 2028 struct mlx5_ifc_fte_match_param_bits match_value; 2029 2030 u8 reserved_6[0x600]; 2031 2032 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2033}; 2034 2035enum { 2036 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2037 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2038}; 2039 2040struct mlx5_ifc_xrc_srqc_bits { 2041 u8 state[0x4]; 2042 u8 log_xrc_srq_size[0x4]; 2043 u8 reserved_0[0x18]; 2044 2045 u8 wq_signature[0x1]; 2046 u8 cont_srq[0x1]; 2047 u8 reserved_1[0x1]; 2048 u8 rlky[0x1]; 2049 u8 basic_cyclic_rcv_wqe[0x1]; 2050 u8 log_rq_stride[0x3]; 2051 u8 xrcd[0x18]; 2052 2053 u8 page_offset[0x6]; 2054 u8 reserved_2[0x2]; 2055 u8 cqn[0x18]; 2056 2057 u8 reserved_3[0x20]; 2058 2059 u8 reserved_4[0x2]; 2060 u8 log_page_size[0x6]; 2061 u8 user_index[0x18]; 2062 2063 u8 reserved_5[0x20]; 2064 2065 u8 reserved_6[0x8]; 2066 u8 pd[0x18]; 2067 2068 u8 lwm[0x10]; 2069 u8 wqe_cnt[0x10]; 2070 2071 u8 reserved_7[0x40]; 2072 2073 u8 db_record_addr_h[0x20]; 2074 2075 u8 db_record_addr_l[0x1e]; 2076 u8 reserved_8[0x2]; 2077 2078 u8 reserved_9[0x80]; 2079}; 2080 2081struct mlx5_ifc_traffic_counter_bits { 2082 u8 packets[0x40]; 2083 2084 u8 octets[0x40]; 2085}; 2086 2087struct mlx5_ifc_tisc_bits { 2088 u8 strict_lag_tx_port_affinity[0x1]; 2089 u8 reserved_at_1[0x3]; 2090 u8 lag_tx_port_affinity[0x04]; 2091 2092 u8 reserved_at_8[0x4]; 2093 u8 prio[0x4]; 2094 u8 reserved_1[0x10]; 2095 2096 u8 reserved_2[0x100]; 2097 2098 u8 reserved_3[0x8]; 2099 u8 transport_domain[0x18]; 2100 2101 u8 reserved_4[0x8]; 2102 u8 underlay_qpn[0x18]; 2103 2104 u8 reserved_5[0x3a0]; 2105}; 2106 2107enum { 2108 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2109 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2110}; 2111 2112enum { 2113 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2114 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2115}; 2116 2117enum { 2118 MLX5_TIRC_RX_HASH_FN_HASH_NONE = 0x0, 2119 MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8 = 0x1, 2120 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ = 0x2, 2121}; 2122 2123enum { 2124 MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST = 0x1, 2125 MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST = 0x2, 2126}; 2127 2128struct mlx5_ifc_tirc_bits { 2129 u8 reserved_0[0x20]; 2130 2131 u8 disp_type[0x4]; 2132 u8 reserved_1[0x1c]; 2133 2134 u8 reserved_2[0x40]; 2135 2136 u8 reserved_3[0x4]; 2137 u8 lro_timeout_period_usecs[0x10]; 2138 u8 lro_enable_mask[0x4]; 2139 u8 lro_max_msg_sz[0x8]; 2140 2141 u8 reserved_4[0x40]; 2142 2143 u8 reserved_5[0x8]; 2144 u8 inline_rqn[0x18]; 2145 2146 u8 rx_hash_symmetric[0x1]; 2147 u8 reserved_6[0x1]; 2148 u8 tunneled_offload_en[0x1]; 2149 u8 reserved_7[0x5]; 2150 u8 indirect_table[0x18]; 2151 2152 u8 rx_hash_fn[0x4]; 2153 u8 reserved_8[0x2]; 2154 u8 self_lb_en[0x2]; 2155 u8 transport_domain[0x18]; 2156 2157 u8 rx_hash_toeplitz_key[10][0x20]; 2158 2159 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2160 2161 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2162 2163 u8 reserved_9[0x4c0]; 2164}; 2165 2166enum { 2167 MLX5_SRQC_STATE_GOOD = 0x0, 2168 MLX5_SRQC_STATE_ERROR = 0x1, 2169}; 2170 2171struct mlx5_ifc_srqc_bits { 2172 u8 state[0x4]; 2173 u8 log_srq_size[0x4]; 2174 u8 reserved_0[0x18]; 2175 2176 u8 wq_signature[0x1]; 2177 u8 cont_srq[0x1]; 2178 u8 reserved_1[0x1]; 2179 u8 rlky[0x1]; 2180 u8 reserved_2[0x1]; 2181 u8 log_rq_stride[0x3]; 2182 u8 xrcd[0x18]; 2183 2184 u8 page_offset[0x6]; 2185 u8 reserved_3[0x2]; 2186 u8 cqn[0x18]; 2187 2188 u8 reserved_4[0x20]; 2189 2190 u8 reserved_5[0x2]; 2191 u8 log_page_size[0x6]; 2192 u8 reserved_6[0x18]; 2193 2194 u8 reserved_7[0x20]; 2195 2196 u8 reserved_8[0x8]; 2197 u8 pd[0x18]; 2198 2199 u8 lwm[0x10]; 2200 u8 wqe_cnt[0x10]; 2201 2202 u8 reserved_9[0x40]; 2203 2204 u8 dbr_addr[0x40]; 2205 2206 u8 reserved_10[0x80]; 2207}; 2208 2209enum { 2210 MLX5_SQC_STATE_RST = 0x0, 2211 MLX5_SQC_STATE_RDY = 0x1, 2212 MLX5_SQC_STATE_ERR = 0x3, 2213}; 2214 2215struct mlx5_ifc_sqc_bits { 2216 u8 rlkey[0x1]; 2217 u8 cd_master[0x1]; 2218 u8 fre[0x1]; 2219 u8 flush_in_error_en[0x1]; 2220 u8 allow_multi_pkt_send_wqe[0x1]; 2221 u8 min_wqe_inline_mode[0x3]; 2222 u8 state[0x4]; 2223 u8 reg_umr[0x1]; 2224 u8 allow_swp[0x1]; 2225 u8 reserved_0[0x12]; 2226 2227 u8 reserved_1[0x8]; 2228 u8 user_index[0x18]; 2229 2230 u8 reserved_2[0x8]; 2231 u8 cqn[0x18]; 2232 2233 u8 reserved_3[0x80]; 2234 2235 u8 qos_para_vport_number[0x10]; 2236 u8 packet_pacing_rate_limit_index[0x10]; 2237 2238 u8 tis_lst_sz[0x10]; 2239 u8 reserved_4[0x10]; 2240 2241 u8 reserved_5[0x40]; 2242 2243 u8 reserved_6[0x8]; 2244 u8 tis_num_0[0x18]; 2245 2246 struct mlx5_ifc_wq_bits wq; 2247}; 2248 2249enum { 2250 MLX5_TSAR_TYPE_DWRR = 0, 2251 MLX5_TSAR_TYPE_ROUND_ROUBIN = 1, 2252 MLX5_TSAR_TYPE_ETS = 2 2253}; 2254 2255struct mlx5_ifc_tsar_element_attributes_bits { 2256 u8 reserved_0[0x8]; 2257 u8 tsar_type[0x8]; 2258 u8 reserved_1[0x10]; 2259}; 2260 2261struct mlx5_ifc_vport_element_attributes_bits { 2262 u8 reserved_0[0x10]; 2263 u8 vport_number[0x10]; 2264}; 2265 2266struct mlx5_ifc_vport_tc_element_attributes_bits { 2267 u8 traffic_class[0x10]; 2268 u8 vport_number[0x10]; 2269}; 2270 2271struct mlx5_ifc_para_vport_tc_element_attributes_bits { 2272 u8 reserved_0[0x0C]; 2273 u8 traffic_class[0x04]; 2274 u8 qos_para_vport_number[0x10]; 2275}; 2276 2277enum { 2278 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2279 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2280 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2281 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2282}; 2283 2284struct mlx5_ifc_scheduling_context_bits { 2285 u8 element_type[0x8]; 2286 u8 reserved_at_8[0x18]; 2287 2288 u8 element_attributes[0x20]; 2289 2290 u8 parent_element_id[0x20]; 2291 2292 u8 reserved_at_60[0x40]; 2293 2294 u8 bw_share[0x20]; 2295 2296 u8 max_average_bw[0x20]; 2297 2298 u8 reserved_at_e0[0x120]; 2299}; 2300 2301struct mlx5_ifc_rqtc_bits { 2302 u8 reserved_0[0xa0]; 2303 2304 u8 reserved_1[0x10]; 2305 u8 rqt_max_size[0x10]; 2306 2307 u8 reserved_2[0x10]; 2308 u8 rqt_actual_size[0x10]; 2309 2310 u8 reserved_3[0x6a0]; 2311 2312 struct mlx5_ifc_rq_num_bits rq_num[0]; 2313}; 2314 2315enum { 2316 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2317 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2318}; 2319 2320enum { 2321 MLX5_RQC_STATE_RST = 0x0, 2322 MLX5_RQC_STATE_RDY = 0x1, 2323 MLX5_RQC_STATE_ERR = 0x3, 2324}; 2325 2326enum { 2327 MLX5_RQC_DROPLESS_MODE_DISABLE = 0x0, 2328 MLX5_RQC_DROPLESS_MODE_ENABLE = 0x1, 2329}; 2330 2331struct mlx5_ifc_rqc_bits { 2332 u8 rlkey[0x1]; 2333 u8 delay_drop_en[0x1]; 2334 u8 scatter_fcs[0x1]; 2335 u8 vlan_strip_disable[0x1]; 2336 u8 mem_rq_type[0x4]; 2337 u8 state[0x4]; 2338 u8 reserved_1[0x1]; 2339 u8 flush_in_error_en[0x1]; 2340 u8 reserved_2[0x12]; 2341 2342 u8 reserved_3[0x8]; 2343 u8 user_index[0x18]; 2344 2345 u8 reserved_4[0x8]; 2346 u8 cqn[0x18]; 2347 2348 u8 counter_set_id[0x8]; 2349 u8 reserved_5[0x18]; 2350 2351 u8 reserved_6[0x8]; 2352 u8 rmpn[0x18]; 2353 2354 u8 reserved_7[0xe0]; 2355 2356 struct mlx5_ifc_wq_bits wq; 2357}; 2358 2359enum { 2360 MLX5_RMPC_STATE_RDY = 0x1, 2361 MLX5_RMPC_STATE_ERR = 0x3, 2362}; 2363 2364struct mlx5_ifc_rmpc_bits { 2365 u8 reserved_0[0x8]; 2366 u8 state[0x4]; 2367 u8 reserved_1[0x14]; 2368 2369 u8 basic_cyclic_rcv_wqe[0x1]; 2370 u8 reserved_2[0x1f]; 2371 2372 u8 reserved_3[0x140]; 2373 2374 struct mlx5_ifc_wq_bits wq; 2375}; 2376 2377enum { 2378 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0, 2379 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS = 0x1, 2380 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST = 0x2, 2381}; 2382 2383struct mlx5_ifc_nic_vport_context_bits { 2384 u8 reserved_0[0x5]; 2385 u8 min_wqe_inline_mode[0x3]; 2386 u8 reserved_1[0x15]; 2387 u8 disable_mc_local_lb[0x1]; 2388 u8 disable_uc_local_lb[0x1]; 2389 u8 roce_en[0x1]; 2390 2391 u8 arm_change_event[0x1]; 2392 u8 reserved_2[0x1a]; 2393 u8 event_on_mtu[0x1]; 2394 u8 event_on_promisc_change[0x1]; 2395 u8 event_on_vlan_change[0x1]; 2396 u8 event_on_mc_address_change[0x1]; 2397 u8 event_on_uc_address_change[0x1]; 2398 2399 u8 reserved_3[0xe0]; 2400 2401 u8 reserved_4[0x10]; 2402 u8 mtu[0x10]; 2403 2404 u8 system_image_guid[0x40]; 2405 2406 u8 port_guid[0x40]; 2407 2408 u8 node_guid[0x40]; 2409 2410 u8 reserved_5[0x140]; 2411 2412 u8 qkey_violation_counter[0x10]; 2413 u8 reserved_6[0x10]; 2414 2415 u8 reserved_7[0x420]; 2416 2417 u8 promisc_uc[0x1]; 2418 u8 promisc_mc[0x1]; 2419 u8 promisc_all[0x1]; 2420 u8 reserved_8[0x2]; 2421 u8 allowed_list_type[0x3]; 2422 u8 reserved_9[0xc]; 2423 u8 allowed_list_size[0xc]; 2424 2425 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2426 2427 u8 reserved_10[0x20]; 2428 2429 u8 current_uc_mac_address[0][0x40]; 2430}; 2431 2432enum { 2433 MLX5_ACCESS_MODE_PA = 0x0, 2434 MLX5_ACCESS_MODE_MTT = 0x1, 2435 MLX5_ACCESS_MODE_KLM = 0x2, 2436}; 2437 2438struct mlx5_ifc_mkc_bits { 2439 u8 reserved_at_0[0x1]; 2440 u8 free[0x1]; 2441 u8 reserved_at_2[0x1]; 2442 u8 access_mode_4_2[0x3]; 2443 u8 reserved_at_6[0x7]; 2444 u8 relaxed_ordering_write[0x1]; 2445 u8 reserved_at_e[0x1]; 2446 u8 small_fence_on_rdma_read_response[0x1]; 2447 u8 umr_en[0x1]; 2448 u8 a[0x1]; 2449 u8 rw[0x1]; 2450 u8 rr[0x1]; 2451 u8 lw[0x1]; 2452 u8 lr[0x1]; 2453 u8 access_mode[0x2]; 2454 u8 reserved_2[0x8]; 2455 2456 u8 qpn[0x18]; 2457 u8 mkey_7_0[0x8]; 2458 2459 u8 reserved_3[0x20]; 2460 2461 u8 length64[0x1]; 2462 u8 bsf_en[0x1]; 2463 u8 sync_umr[0x1]; 2464 u8 reserved_4[0x2]; 2465 u8 expected_sigerr_count[0x1]; 2466 u8 reserved_5[0x1]; 2467 u8 en_rinval[0x1]; 2468 u8 pd[0x18]; 2469 2470 u8 start_addr[0x40]; 2471 2472 u8 len[0x40]; 2473 2474 u8 bsf_octword_size[0x20]; 2475 2476 u8 reserved_6[0x80]; 2477 2478 u8 translations_octword_size[0x20]; 2479 2480 u8 reserved_7[0x1b]; 2481 u8 log_page_size[0x5]; 2482 2483 u8 reserved_8[0x20]; 2484}; 2485 2486struct mlx5_ifc_pkey_bits { 2487 u8 reserved_0[0x10]; 2488 u8 pkey[0x10]; 2489}; 2490 2491struct mlx5_ifc_array128_auto_bits { 2492 u8 array128_auto[16][0x8]; 2493}; 2494 2495enum { 2496 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID = 0x0, 2497 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID = 0x1, 2498 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY = 0x2, 2499}; 2500 2501enum { 2502 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP = 0x1, 2503 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING = 0x2, 2504 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED = 0x3, 2505 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING = 0x4, 2506 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP = 0x5, 2507 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY = 0x6, 2508 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST = 0x7, 2509}; 2510 2511enum { 2512 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN = 0x0, 2513 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP = 0x1, 2514 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW = 0x2, 2515}; 2516 2517enum { 2518 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN = 0x1, 2519 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT = 0x2, 2520 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM = 0x3, 2521 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE = 0x4, 2522}; 2523 2524enum { 2525 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN = 0x1, 2526 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT = 0x2, 2527 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM = 0x3, 2528 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE = 0x4, 2529}; 2530 2531struct mlx5_ifc_hca_vport_context_bits { 2532 u8 field_select[0x20]; 2533 2534 u8 reserved_0[0xe0]; 2535 2536 u8 sm_virt_aware[0x1]; 2537 u8 has_smi[0x1]; 2538 u8 has_raw[0x1]; 2539 u8 grh_required[0x1]; 2540 u8 reserved_1[0x1]; 2541 u8 min_wqe_inline_mode[0x3]; 2542 u8 reserved_2[0x8]; 2543 u8 port_physical_state[0x4]; 2544 u8 vport_state_policy[0x4]; 2545 u8 port_state[0x4]; 2546 u8 vport_state[0x4]; 2547 2548 u8 reserved_3[0x20]; 2549 2550 u8 system_image_guid[0x40]; 2551 2552 u8 port_guid[0x40]; 2553 2554 u8 node_guid[0x40]; 2555 2556 u8 cap_mask1[0x20]; 2557 2558 u8 cap_mask1_field_select[0x20]; 2559 2560 u8 cap_mask2[0x20]; 2561 2562 u8 cap_mask2_field_select[0x20]; 2563 2564 u8 reserved_4[0x80]; 2565 2566 u8 lid[0x10]; 2567 u8 reserved_5[0x4]; 2568 u8 init_type_reply[0x4]; 2569 u8 lmc[0x3]; 2570 u8 subnet_timeout[0x5]; 2571 2572 u8 sm_lid[0x10]; 2573 u8 sm_sl[0x4]; 2574 u8 reserved_6[0xc]; 2575 2576 u8 qkey_violation_counter[0x10]; 2577 u8 pkey_violation_counter[0x10]; 2578 2579 u8 reserved_7[0xca0]; 2580}; 2581 2582union mlx5_ifc_hca_cap_union_bits { 2583 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2584 struct mlx5_ifc_odp_cap_bits odp_cap; 2585 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2586 struct mlx5_ifc_roce_cap_bits roce_cap; 2587 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2588 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2589 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2590 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2591 struct mlx5_ifc_snapshot_cap_bits snapshot_cap; 2592 struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap; 2593 struct mlx5_ifc_qos_cap_bits qos_cap; 2594 u8 reserved_0[0x8000]; 2595}; 2596 2597enum { 2598 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0, 2599 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1, 2600}; 2601 2602struct mlx5_ifc_flow_table_context_bits { 2603 u8 encap_en[0x1]; 2604 u8 decap_en[0x1]; 2605 u8 reserved_at_2[0x2]; 2606 u8 table_miss_action[0x4]; 2607 u8 level[0x8]; 2608 u8 reserved_at_10[0x8]; 2609 u8 log_size[0x8]; 2610 2611 u8 reserved_at_20[0x8]; 2612 u8 table_miss_id[0x18]; 2613 2614 u8 reserved_at_40[0x8]; 2615 u8 lag_master_next_table_id[0x18]; 2616 2617 u8 reserved_at_60[0xe0]; 2618}; 2619 2620struct mlx5_ifc_esw_vport_context_bits { 2621 u8 reserved_0[0x3]; 2622 u8 vport_svlan_strip[0x1]; 2623 u8 vport_cvlan_strip[0x1]; 2624 u8 vport_svlan_insert[0x1]; 2625 u8 vport_cvlan_insert[0x2]; 2626 u8 reserved_1[0x18]; 2627 2628 u8 reserved_2[0x20]; 2629 2630 u8 svlan_cfi[0x1]; 2631 u8 svlan_pcp[0x3]; 2632 u8 svlan_id[0xc]; 2633 u8 cvlan_cfi[0x1]; 2634 u8 cvlan_pcp[0x3]; 2635 u8 cvlan_id[0xc]; 2636 2637 u8 reserved_3[0x7a0]; 2638}; 2639 2640enum { 2641 MLX5_EQC_STATUS_OK = 0x0, 2642 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2643}; 2644 2645enum { 2646 MLX5_EQ_STATE_ARMED = 0x9, 2647 MLX5_EQ_STATE_FIRED = 0xa, 2648}; 2649 2650struct mlx5_ifc_eqc_bits { 2651 u8 status[0x4]; 2652 u8 reserved_0[0x9]; 2653 u8 ec[0x1]; 2654 u8 oi[0x1]; 2655 u8 reserved_1[0x5]; 2656 u8 st[0x4]; 2657 u8 reserved_2[0x8]; 2658 2659 u8 reserved_3[0x20]; 2660 2661 u8 reserved_4[0x14]; 2662 u8 page_offset[0x6]; 2663 u8 reserved_5[0x6]; 2664 2665 u8 reserved_6[0x3]; 2666 u8 log_eq_size[0x5]; 2667 u8 uar_page[0x18]; 2668 2669 u8 reserved_7[0x20]; 2670 2671 u8 reserved_8[0x18]; 2672 u8 intr[0x8]; 2673 2674 u8 reserved_9[0x3]; 2675 u8 log_page_size[0x5]; 2676 u8 reserved_10[0x18]; 2677 2678 u8 reserved_11[0x60]; 2679 2680 u8 reserved_12[0x8]; 2681 u8 consumer_counter[0x18]; 2682 2683 u8 reserved_13[0x8]; 2684 u8 producer_counter[0x18]; 2685 2686 u8 reserved_14[0x80]; 2687}; 2688 2689enum { 2690 MLX5_DCTC_STATE_ACTIVE = 0x0, 2691 MLX5_DCTC_STATE_DRAINING = 0x1, 2692 MLX5_DCTC_STATE_DRAINED = 0x2, 2693}; 2694 2695enum { 2696 MLX5_DCTC_CS_RES_DISABLE = 0x0, 2697 MLX5_DCTC_CS_RES_NA = 0x1, 2698 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 2699}; 2700 2701enum { 2702 MLX5_DCTC_MTU_256_BYTES = 0x1, 2703 MLX5_DCTC_MTU_512_BYTES = 0x2, 2704 MLX5_DCTC_MTU_1K_BYTES = 0x3, 2705 MLX5_DCTC_MTU_2K_BYTES = 0x4, 2706 MLX5_DCTC_MTU_4K_BYTES = 0x5, 2707}; 2708 2709struct mlx5_ifc_dctc_bits { 2710 u8 reserved_0[0x4]; 2711 u8 state[0x4]; 2712 u8 reserved_1[0x18]; 2713 2714 u8 reserved_2[0x8]; 2715 u8 user_index[0x18]; 2716 2717 u8 reserved_3[0x8]; 2718 u8 cqn[0x18]; 2719 2720 u8 counter_set_id[0x8]; 2721 u8 atomic_mode[0x4]; 2722 u8 rre[0x1]; 2723 u8 rwe[0x1]; 2724 u8 rae[0x1]; 2725 u8 atomic_like_write_en[0x1]; 2726 u8 latency_sensitive[0x1]; 2727 u8 rlky[0x1]; 2728 u8 reserved_4[0xe]; 2729 2730 u8 reserved_5[0x8]; 2731 u8 cs_res[0x8]; 2732 u8 reserved_6[0x3]; 2733 u8 min_rnr_nak[0x5]; 2734 u8 reserved_7[0x8]; 2735 2736 u8 reserved_8[0x8]; 2737 u8 srqn[0x18]; 2738 2739 u8 reserved_9[0x8]; 2740 u8 pd[0x18]; 2741 2742 u8 tclass[0x8]; 2743 u8 reserved_10[0x4]; 2744 u8 flow_label[0x14]; 2745 2746 u8 dc_access_key[0x40]; 2747 2748 u8 reserved_11[0x5]; 2749 u8 mtu[0x3]; 2750 u8 port[0x8]; 2751 u8 pkey_index[0x10]; 2752 2753 u8 reserved_12[0x8]; 2754 u8 my_addr_index[0x8]; 2755 u8 reserved_13[0x8]; 2756 u8 hop_limit[0x8]; 2757 2758 u8 dc_access_key_violation_count[0x20]; 2759 2760 u8 reserved_14[0x14]; 2761 u8 dei_cfi[0x1]; 2762 u8 eth_prio[0x3]; 2763 u8 ecn[0x2]; 2764 u8 dscp[0x6]; 2765 2766 u8 reserved_15[0x40]; 2767}; 2768 2769enum { 2770 MLX5_CQC_STATUS_OK = 0x0, 2771 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 2772 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 2773}; 2774 2775enum { 2776 CQE_SIZE_64 = 0x0, 2777 CQE_SIZE_128 = 0x1, 2778}; 2779 2780enum { 2781 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 2782 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 2783}; 2784 2785enum { 2786 MLX5_CQ_STATE_SOLICITED_ARMED = 0x6, 2787 MLX5_CQ_STATE_ARMED = 0x9, 2788 MLX5_CQ_STATE_FIRED = 0xa, 2789}; 2790 2791struct mlx5_ifc_cqc_bits { 2792 u8 status[0x4]; 2793 u8 reserved_0[0x4]; 2794 u8 cqe_sz[0x3]; 2795 u8 cc[0x1]; 2796 u8 reserved_1[0x1]; 2797 u8 scqe_break_moderation_en[0x1]; 2798 u8 oi[0x1]; 2799 u8 cq_period_mode[0x2]; 2800 u8 cqe_compression_en[0x1]; 2801 u8 mini_cqe_res_format[0x2]; 2802 u8 st[0x4]; 2803 u8 reserved_2[0x8]; 2804 2805 u8 reserved_3[0x20]; 2806 2807 u8 reserved_4[0x14]; 2808 u8 page_offset[0x6]; 2809 u8 reserved_5[0x6]; 2810 2811 u8 reserved_6[0x3]; 2812 u8 log_cq_size[0x5]; 2813 u8 uar_page[0x18]; 2814 2815 u8 reserved_7[0x4]; 2816 u8 cq_period[0xc]; 2817 u8 cq_max_count[0x10]; 2818 2819 u8 reserved_8[0x18]; 2820 u8 c_eqn[0x8]; 2821 2822 u8 reserved_9[0x3]; 2823 u8 log_page_size[0x5]; 2824 u8 reserved_10[0x18]; 2825 2826 u8 reserved_11[0x20]; 2827 2828 u8 reserved_12[0x8]; 2829 u8 last_notified_index[0x18]; 2830 2831 u8 reserved_13[0x8]; 2832 u8 last_solicit_index[0x18]; 2833 2834 u8 reserved_14[0x8]; 2835 u8 consumer_counter[0x18]; 2836 2837 u8 reserved_15[0x8]; 2838 u8 producer_counter[0x18]; 2839 2840 u8 reserved_16[0x40]; 2841 2842 u8 dbr_addr[0x40]; 2843}; 2844 2845union mlx5_ifc_cong_control_roce_ecn_auto_bits { 2846 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 2847 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 2848 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 2849 u8 reserved_0[0x800]; 2850}; 2851 2852struct mlx5_ifc_query_adapter_param_block_bits { 2853 u8 reserved_0[0xc0]; 2854 2855 u8 reserved_1[0x8]; 2856 u8 ieee_vendor_id[0x18]; 2857 2858 u8 reserved_2[0x10]; 2859 u8 vsd_vendor_id[0x10]; 2860 2861 u8 vsd[208][0x8]; 2862 2863 u8 vsd_contd_psid[16][0x8]; 2864}; 2865 2866union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 2867 struct mlx5_ifc_modify_field_select_bits modify_field_select; 2868 struct mlx5_ifc_resize_field_select_bits resize_field_select; 2869 u8 reserved_0[0x20]; 2870}; 2871 2872union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 2873 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 2874 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 2875 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 2876 u8 reserved_0[0x20]; 2877}; 2878 2879struct mlx5_ifc_bufferx_reg_bits { 2880 u8 reserved_0[0x6]; 2881 u8 lossy[0x1]; 2882 u8 epsb[0x1]; 2883 u8 reserved_1[0xc]; 2884 u8 size[0xc]; 2885 2886 u8 xoff_threshold[0x10]; 2887 u8 xon_threshold[0x10]; 2888}; 2889 2890struct mlx5_ifc_config_item_bits { 2891 u8 valid[0x2]; 2892 u8 reserved_0[0x2]; 2893 u8 header_type[0x2]; 2894 u8 reserved_1[0x2]; 2895 u8 default_location[0x1]; 2896 u8 reserved_2[0x7]; 2897 u8 version[0x4]; 2898 u8 reserved_3[0x3]; 2899 u8 length[0x9]; 2900 2901 u8 type[0x20]; 2902 2903 u8 reserved_4[0x10]; 2904 u8 crc16[0x10]; 2905}; 2906 2907struct mlx5_ifc_nodnic_port_config_reg_bits { 2908 struct mlx5_ifc_nodnic_event_word_bits event; 2909 2910 u8 network_en[0x1]; 2911 u8 dma_en[0x1]; 2912 u8 promisc_en[0x1]; 2913 u8 promisc_multicast_en[0x1]; 2914 u8 reserved_0[0x17]; 2915 u8 receive_filter_en[0x5]; 2916 2917 u8 reserved_1[0x10]; 2918 u8 mac_47_32[0x10]; 2919 2920 u8 mac_31_0[0x20]; 2921 2922 u8 receive_filters_mgid_mac[64][0x8]; 2923 2924 u8 gid[16][0x8]; 2925 2926 u8 reserved_2[0x10]; 2927 u8 lid[0x10]; 2928 2929 u8 reserved_3[0xc]; 2930 u8 sm_sl[0x4]; 2931 u8 sm_lid[0x10]; 2932 2933 u8 completion_address_63_32[0x20]; 2934 2935 u8 completion_address_31_12[0x14]; 2936 u8 reserved_4[0x6]; 2937 u8 log_cq_size[0x6]; 2938 2939 u8 working_buffer_address_63_32[0x20]; 2940 2941 u8 working_buffer_address_31_12[0x14]; 2942 u8 reserved_5[0xc]; 2943 2944 struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq; 2945 2946 u8 pkey_index[0x10]; 2947 u8 pkey[0x10]; 2948 2949 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0; 2950 2951 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1; 2952 2953 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0; 2954 2955 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1; 2956 2957 u8 reserved_6[0x400]; 2958}; 2959 2960union mlx5_ifc_event_auto_bits { 2961 struct mlx5_ifc_comp_event_bits comp_event; 2962 struct mlx5_ifc_dct_events_bits dct_events; 2963 struct mlx5_ifc_qp_events_bits qp_events; 2964 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 2965 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 2966 struct mlx5_ifc_cq_error_bits cq_error; 2967 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 2968 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 2969 struct mlx5_ifc_gpio_event_bits gpio_event; 2970 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 2971 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 2972 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 2973 struct mlx5_ifc_pages_req_event_bits pages_req_event; 2974 struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event; 2975 u8 reserved_0[0xe0]; 2976}; 2977 2978struct mlx5_ifc_health_buffer_bits { 2979 u8 reserved_0[0x100]; 2980 2981 u8 assert_existptr[0x20]; 2982 2983 u8 assert_callra[0x20]; 2984 2985 u8 reserved_1[0x40]; 2986 2987 u8 fw_version[0x20]; 2988 2989 u8 hw_id[0x20]; 2990 2991 u8 reserved_2[0x20]; 2992 2993 u8 irisc_index[0x8]; 2994 u8 synd[0x8]; 2995 u8 ext_synd[0x10]; 2996}; 2997 2998struct mlx5_ifc_register_loopback_control_bits { 2999 u8 no_lb[0x1]; 3000 u8 reserved_0[0x7]; 3001 u8 port[0x8]; 3002 u8 reserved_1[0x10]; 3003 3004 u8 reserved_2[0x60]; 3005}; 3006 3007struct mlx5_ifc_lrh_bits { 3008 u8 vl[4]; 3009 u8 lver[4]; 3010 u8 sl[4]; 3011 u8 reserved2[2]; 3012 u8 lnh[2]; 3013 u8 dlid[16]; 3014 u8 reserved5[5]; 3015 u8 pkt_len[11]; 3016 u8 slid[16]; 3017}; 3018 3019struct mlx5_ifc_icmd_set_wol_rol_out_bits { 3020 u8 reserved_0[0x40]; 3021 3022 u8 reserved_1[0x10]; 3023 u8 rol_mode[0x8]; 3024 u8 wol_mode[0x8]; 3025}; 3026 3027struct mlx5_ifc_icmd_set_wol_rol_in_bits { 3028 u8 reserved_0[0x40]; 3029 3030 u8 rol_mode_valid[0x1]; 3031 u8 wol_mode_valid[0x1]; 3032 u8 reserved_1[0xe]; 3033 u8 rol_mode[0x8]; 3034 u8 wol_mode[0x8]; 3035 3036 u8 reserved_2[0x7a0]; 3037}; 3038 3039struct mlx5_ifc_icmd_set_virtual_mac_in_bits { 3040 u8 virtual_mac_en[0x1]; 3041 u8 mac_aux_v[0x1]; 3042 u8 reserved_0[0x1e]; 3043 3044 u8 reserved_1[0x40]; 3045 3046 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3047 3048 u8 reserved_2[0x760]; 3049}; 3050 3051struct mlx5_ifc_icmd_query_virtual_mac_out_bits { 3052 u8 virtual_mac_en[0x1]; 3053 u8 mac_aux_v[0x1]; 3054 u8 reserved_0[0x1e]; 3055 3056 struct mlx5_ifc_mac_address_layout_bits permanent_mac; 3057 3058 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3059 3060 u8 reserved_1[0x760]; 3061}; 3062 3063struct mlx5_ifc_icmd_query_fw_info_out_bits { 3064 struct mlx5_ifc_fw_version_bits fw_version; 3065 3066 u8 reserved_0[0x10]; 3067 u8 hash_signature[0x10]; 3068 3069 u8 psid[16][0x8]; 3070 3071 u8 reserved_1[0x6e0]; 3072}; 3073 3074struct mlx5_ifc_icmd_query_cap_in_bits { 3075 u8 reserved_0[0x10]; 3076 u8 capability_group[0x10]; 3077}; 3078 3079struct mlx5_ifc_icmd_query_cap_general_bits { 3080 u8 nv_access[0x1]; 3081 u8 fw_info_psid[0x1]; 3082 u8 reserved_0[0x1e]; 3083 3084 u8 reserved_1[0x16]; 3085 u8 rol_s[0x1]; 3086 u8 rol_g[0x1]; 3087 u8 reserved_2[0x1]; 3088 u8 wol_s[0x1]; 3089 u8 wol_g[0x1]; 3090 u8 wol_a[0x1]; 3091 u8 wol_b[0x1]; 3092 u8 wol_m[0x1]; 3093 u8 wol_u[0x1]; 3094 u8 wol_p[0x1]; 3095}; 3096 3097struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits { 3098 u8 status[0x8]; 3099 u8 reserved_0[0x18]; 3100 3101 u8 reserved_1[0x7e0]; 3102}; 3103 3104struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits { 3105 u8 status[0x8]; 3106 u8 reserved_0[0x18]; 3107 3108 u8 reserved_1[0x7e0]; 3109}; 3110 3111struct mlx5_ifc_icmd_ocbb_init_in_bits { 3112 u8 address_hi[0x20]; 3113 3114 u8 address_lo[0x20]; 3115 3116 u8 reserved_0[0x7c0]; 3117}; 3118 3119struct mlx5_ifc_icmd_init_ocsd_in_bits { 3120 u8 reserved_0[0x20]; 3121 3122 u8 address_hi[0x20]; 3123 3124 u8 address_lo[0x20]; 3125 3126 u8 reserved_1[0x7a0]; 3127}; 3128 3129struct mlx5_ifc_icmd_access_reg_out_bits { 3130 u8 reserved_0[0x11]; 3131 u8 status[0x7]; 3132 u8 reserved_1[0x8]; 3133 3134 u8 register_id[0x10]; 3135 u8 reserved_2[0x10]; 3136 3137 u8 reserved_3[0x40]; 3138 3139 u8 reserved_4[0x5]; 3140 u8 len[0xb]; 3141 u8 reserved_5[0x10]; 3142 3143 u8 register_data[0][0x20]; 3144}; 3145 3146enum { 3147 MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY = 0x1, 3148 MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE = 0x2, 3149}; 3150 3151struct mlx5_ifc_icmd_access_reg_in_bits { 3152 u8 constant_1[0x5]; 3153 u8 constant_2[0xb]; 3154 u8 reserved_0[0x10]; 3155 3156 u8 register_id[0x10]; 3157 u8 reserved_1[0x1]; 3158 u8 method[0x7]; 3159 u8 constant_3[0x8]; 3160 3161 u8 reserved_2[0x40]; 3162 3163 u8 constant_4[0x5]; 3164 u8 len[0xb]; 3165 u8 reserved_3[0x10]; 3166 3167 u8 register_data[0][0x20]; 3168}; 3169 3170enum { 3171 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3172 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3173}; 3174 3175struct mlx5_ifc_teardown_hca_out_bits { 3176 u8 status[0x8]; 3177 u8 reserved_0[0x18]; 3178 3179 u8 syndrome[0x20]; 3180 3181 u8 reserved_1[0x3f]; 3182 3183 u8 force_state[0x1]; 3184}; 3185 3186enum { 3187 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3188 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3189}; 3190 3191struct mlx5_ifc_teardown_hca_in_bits { 3192 u8 opcode[0x10]; 3193 u8 reserved_0[0x10]; 3194 3195 u8 reserved_1[0x10]; 3196 u8 op_mod[0x10]; 3197 3198 u8 reserved_2[0x10]; 3199 u8 profile[0x10]; 3200 3201 u8 reserved_3[0x20]; 3202}; 3203 3204struct mlx5_ifc_set_delay_drop_params_out_bits { 3205 u8 status[0x8]; 3206 u8 reserved_at_8[0x18]; 3207 3208 u8 syndrome[0x20]; 3209 3210 u8 reserved_at_40[0x40]; 3211}; 3212 3213struct mlx5_ifc_set_delay_drop_params_in_bits { 3214 u8 opcode[0x10]; 3215 u8 reserved_at_10[0x10]; 3216 3217 u8 reserved_at_20[0x10]; 3218 u8 op_mod[0x10]; 3219 3220 u8 reserved_at_40[0x20]; 3221 3222 u8 reserved_at_60[0x10]; 3223 u8 delay_drop_timeout[0x10]; 3224}; 3225 3226struct mlx5_ifc_query_delay_drop_params_out_bits { 3227 u8 status[0x8]; 3228 u8 reserved_at_8[0x18]; 3229 3230 u8 syndrome[0x20]; 3231 3232 u8 reserved_at_40[0x20]; 3233 3234 u8 reserved_at_60[0x10]; 3235 u8 delay_drop_timeout[0x10]; 3236}; 3237 3238struct mlx5_ifc_query_delay_drop_params_in_bits { 3239 u8 opcode[0x10]; 3240 u8 reserved_at_10[0x10]; 3241 3242 u8 reserved_at_20[0x10]; 3243 u8 op_mod[0x10]; 3244 3245 u8 reserved_at_40[0x40]; 3246}; 3247 3248struct mlx5_ifc_suspend_qp_out_bits { 3249 u8 status[0x8]; 3250 u8 reserved_0[0x18]; 3251 3252 u8 syndrome[0x20]; 3253 3254 u8 reserved_1[0x40]; 3255}; 3256 3257struct mlx5_ifc_suspend_qp_in_bits { 3258 u8 opcode[0x10]; 3259 u8 reserved_0[0x10]; 3260 3261 u8 reserved_1[0x10]; 3262 u8 op_mod[0x10]; 3263 3264 u8 reserved_2[0x8]; 3265 u8 qpn[0x18]; 3266 3267 u8 reserved_3[0x20]; 3268}; 3269 3270struct mlx5_ifc_sqerr2rts_qp_out_bits { 3271 u8 status[0x8]; 3272 u8 reserved_0[0x18]; 3273 3274 u8 syndrome[0x20]; 3275 3276 u8 reserved_1[0x40]; 3277}; 3278 3279struct mlx5_ifc_sqerr2rts_qp_in_bits { 3280 u8 opcode[0x10]; 3281 u8 reserved_0[0x10]; 3282 3283 u8 reserved_1[0x10]; 3284 u8 op_mod[0x10]; 3285 3286 u8 reserved_2[0x8]; 3287 u8 qpn[0x18]; 3288 3289 u8 reserved_3[0x20]; 3290 3291 u8 opt_param_mask[0x20]; 3292 3293 u8 reserved_4[0x20]; 3294 3295 struct mlx5_ifc_qpc_bits qpc; 3296 3297 u8 reserved_5[0x80]; 3298}; 3299 3300struct mlx5_ifc_sqd2rts_qp_out_bits { 3301 u8 status[0x8]; 3302 u8 reserved_0[0x18]; 3303 3304 u8 syndrome[0x20]; 3305 3306 u8 reserved_1[0x40]; 3307}; 3308 3309struct mlx5_ifc_sqd2rts_qp_in_bits { 3310 u8 opcode[0x10]; 3311 u8 reserved_0[0x10]; 3312 3313 u8 reserved_1[0x10]; 3314 u8 op_mod[0x10]; 3315 3316 u8 reserved_2[0x8]; 3317 u8 qpn[0x18]; 3318 3319 u8 reserved_3[0x20]; 3320 3321 u8 opt_param_mask[0x20]; 3322 3323 u8 reserved_4[0x20]; 3324 3325 struct mlx5_ifc_qpc_bits qpc; 3326 3327 u8 reserved_5[0x80]; 3328}; 3329 3330struct mlx5_ifc_set_wol_rol_out_bits { 3331 u8 status[0x8]; 3332 u8 reserved_0[0x18]; 3333 3334 u8 syndrome[0x20]; 3335 3336 u8 reserved_1[0x40]; 3337}; 3338 3339struct mlx5_ifc_set_wol_rol_in_bits { 3340 u8 opcode[0x10]; 3341 u8 reserved_0[0x10]; 3342 3343 u8 reserved_1[0x10]; 3344 u8 op_mod[0x10]; 3345 3346 u8 rol_mode_valid[0x1]; 3347 u8 wol_mode_valid[0x1]; 3348 u8 reserved_2[0xe]; 3349 u8 rol_mode[0x8]; 3350 u8 wol_mode[0x8]; 3351 3352 u8 reserved_3[0x20]; 3353}; 3354 3355struct mlx5_ifc_set_roce_address_out_bits { 3356 u8 status[0x8]; 3357 u8 reserved_0[0x18]; 3358 3359 u8 syndrome[0x20]; 3360 3361 u8 reserved_1[0x40]; 3362}; 3363 3364struct mlx5_ifc_set_roce_address_in_bits { 3365 u8 opcode[0x10]; 3366 u8 reserved_0[0x10]; 3367 3368 u8 reserved_1[0x10]; 3369 u8 op_mod[0x10]; 3370 3371 u8 roce_address_index[0x10]; 3372 u8 reserved_2[0x10]; 3373 3374 u8 reserved_3[0x20]; 3375 3376 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3377}; 3378 3379struct mlx5_ifc_set_rdb_out_bits { 3380 u8 status[0x8]; 3381 u8 reserved_0[0x18]; 3382 3383 u8 syndrome[0x20]; 3384 3385 u8 reserved_1[0x40]; 3386}; 3387 3388struct mlx5_ifc_set_rdb_in_bits { 3389 u8 opcode[0x10]; 3390 u8 reserved_0[0x10]; 3391 3392 u8 reserved_1[0x10]; 3393 u8 op_mod[0x10]; 3394 3395 u8 reserved_2[0x8]; 3396 u8 qpn[0x18]; 3397 3398 u8 reserved_3[0x18]; 3399 u8 rdb_list_size[0x8]; 3400 3401 struct mlx5_ifc_rdbc_bits rdb_context[0]; 3402}; 3403 3404struct mlx5_ifc_set_mad_demux_out_bits { 3405 u8 status[0x8]; 3406 u8 reserved_0[0x18]; 3407 3408 u8 syndrome[0x20]; 3409 3410 u8 reserved_1[0x40]; 3411}; 3412 3413enum { 3414 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3415 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3416}; 3417 3418struct mlx5_ifc_set_mad_demux_in_bits { 3419 u8 opcode[0x10]; 3420 u8 reserved_0[0x10]; 3421 3422 u8 reserved_1[0x10]; 3423 u8 op_mod[0x10]; 3424 3425 u8 reserved_2[0x20]; 3426 3427 u8 reserved_3[0x6]; 3428 u8 demux_mode[0x2]; 3429 u8 reserved_4[0x18]; 3430}; 3431 3432struct mlx5_ifc_set_l2_table_entry_out_bits { 3433 u8 status[0x8]; 3434 u8 reserved_0[0x18]; 3435 3436 u8 syndrome[0x20]; 3437 3438 u8 reserved_1[0x40]; 3439}; 3440 3441struct mlx5_ifc_set_l2_table_entry_in_bits { 3442 u8 opcode[0x10]; 3443 u8 reserved_0[0x10]; 3444 3445 u8 reserved_1[0x10]; 3446 u8 op_mod[0x10]; 3447 3448 u8 reserved_2[0x60]; 3449 3450 u8 reserved_3[0x8]; 3451 u8 table_index[0x18]; 3452 3453 u8 reserved_4[0x20]; 3454 3455 u8 reserved_5[0x13]; 3456 u8 vlan_valid[0x1]; 3457 u8 vlan[0xc]; 3458 3459 struct mlx5_ifc_mac_address_layout_bits mac_address; 3460 3461 u8 reserved_6[0xc0]; 3462}; 3463 3464struct mlx5_ifc_set_issi_out_bits { 3465 u8 status[0x8]; 3466 u8 reserved_0[0x18]; 3467 3468 u8 syndrome[0x20]; 3469 3470 u8 reserved_1[0x40]; 3471}; 3472 3473struct mlx5_ifc_set_issi_in_bits { 3474 u8 opcode[0x10]; 3475 u8 reserved_0[0x10]; 3476 3477 u8 reserved_1[0x10]; 3478 u8 op_mod[0x10]; 3479 3480 u8 reserved_2[0x10]; 3481 u8 current_issi[0x10]; 3482 3483 u8 reserved_3[0x20]; 3484}; 3485 3486struct mlx5_ifc_set_hca_cap_out_bits { 3487 u8 status[0x8]; 3488 u8 reserved_0[0x18]; 3489 3490 u8 syndrome[0x20]; 3491 3492 u8 reserved_1[0x40]; 3493}; 3494 3495struct mlx5_ifc_set_hca_cap_in_bits { 3496 u8 opcode[0x10]; 3497 u8 reserved_0[0x10]; 3498 3499 u8 reserved_1[0x10]; 3500 u8 op_mod[0x10]; 3501 3502 u8 reserved_2[0x40]; 3503 3504 union mlx5_ifc_hca_cap_union_bits capability; 3505}; 3506 3507enum { 3508 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3509 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3510 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3511 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3512}; 3513 3514struct mlx5_ifc_set_flow_table_root_out_bits { 3515 u8 status[0x8]; 3516 u8 reserved_0[0x18]; 3517 3518 u8 syndrome[0x20]; 3519 3520 u8 reserved_1[0x40]; 3521}; 3522 3523struct mlx5_ifc_set_flow_table_root_in_bits { 3524 u8 opcode[0x10]; 3525 u8 reserved_0[0x10]; 3526 3527 u8 reserved_1[0x10]; 3528 u8 op_mod[0x10]; 3529 3530 u8 other_vport[0x1]; 3531 u8 reserved_2[0xf]; 3532 u8 vport_number[0x10]; 3533 3534 u8 reserved_3[0x20]; 3535 3536 u8 table_type[0x8]; 3537 u8 reserved_4[0x18]; 3538 3539 u8 reserved_5[0x8]; 3540 u8 table_id[0x18]; 3541 3542 u8 reserved_6[0x8]; 3543 u8 underlay_qpn[0x18]; 3544 3545 u8 reserved_7[0x120]; 3546}; 3547 3548struct mlx5_ifc_set_fte_out_bits { 3549 u8 status[0x8]; 3550 u8 reserved_0[0x18]; 3551 3552 u8 syndrome[0x20]; 3553 3554 u8 reserved_1[0x40]; 3555}; 3556 3557struct mlx5_ifc_set_fte_in_bits { 3558 u8 opcode[0x10]; 3559 u8 reserved_0[0x10]; 3560 3561 u8 reserved_1[0x10]; 3562 u8 op_mod[0x10]; 3563 3564 u8 other_vport[0x1]; 3565 u8 reserved_2[0xf]; 3566 u8 vport_number[0x10]; 3567 3568 u8 reserved_3[0x20]; 3569 3570 u8 table_type[0x8]; 3571 u8 reserved_4[0x18]; 3572 3573 u8 reserved_5[0x8]; 3574 u8 table_id[0x18]; 3575 3576 u8 reserved_6[0x18]; 3577 u8 modify_enable_mask[0x8]; 3578 3579 u8 reserved_7[0x20]; 3580 3581 u8 flow_index[0x20]; 3582 3583 u8 reserved_8[0xe0]; 3584 3585 struct mlx5_ifc_flow_context_bits flow_context; 3586}; 3587 3588struct mlx5_ifc_set_driver_version_out_bits { 3589 u8 status[0x8]; 3590 u8 reserved_0[0x18]; 3591 3592 u8 syndrome[0x20]; 3593 3594 u8 reserved_1[0x40]; 3595}; 3596 3597struct mlx5_ifc_set_driver_version_in_bits { 3598 u8 opcode[0x10]; 3599 u8 reserved_0[0x10]; 3600 3601 u8 reserved_1[0x10]; 3602 u8 op_mod[0x10]; 3603 3604 u8 reserved_2[0x40]; 3605 3606 u8 driver_version[64][0x8]; 3607}; 3608 3609struct mlx5_ifc_set_dc_cnak_trace_out_bits { 3610 u8 status[0x8]; 3611 u8 reserved_0[0x18]; 3612 3613 u8 syndrome[0x20]; 3614 3615 u8 reserved_1[0x40]; 3616}; 3617 3618struct mlx5_ifc_set_dc_cnak_trace_in_bits { 3619 u8 opcode[0x10]; 3620 u8 reserved_0[0x10]; 3621 3622 u8 reserved_1[0x10]; 3623 u8 op_mod[0x10]; 3624 3625 u8 enable[0x1]; 3626 u8 reserved_2[0x1f]; 3627 3628 u8 reserved_3[0x160]; 3629 3630 struct mlx5_ifc_cmd_pas_bits pas; 3631}; 3632 3633struct mlx5_ifc_set_burst_size_out_bits { 3634 u8 status[0x8]; 3635 u8 reserved_0[0x18]; 3636 3637 u8 syndrome[0x20]; 3638 3639 u8 reserved_1[0x40]; 3640}; 3641 3642struct mlx5_ifc_set_burst_size_in_bits { 3643 u8 opcode[0x10]; 3644 u8 reserved_0[0x10]; 3645 3646 u8 reserved_1[0x10]; 3647 u8 op_mod[0x10]; 3648 3649 u8 reserved_2[0x20]; 3650 3651 u8 reserved_3[0x9]; 3652 u8 device_burst_size[0x17]; 3653}; 3654 3655struct mlx5_ifc_rts2rts_qp_out_bits { 3656 u8 status[0x8]; 3657 u8 reserved_0[0x18]; 3658 3659 u8 syndrome[0x20]; 3660 3661 u8 reserved_1[0x40]; 3662}; 3663 3664struct mlx5_ifc_rts2rts_qp_in_bits { 3665 u8 opcode[0x10]; 3666 u8 reserved_0[0x10]; 3667 3668 u8 reserved_1[0x10]; 3669 u8 op_mod[0x10]; 3670 3671 u8 reserved_2[0x8]; 3672 u8 qpn[0x18]; 3673 3674 u8 reserved_3[0x20]; 3675 3676 u8 opt_param_mask[0x20]; 3677 3678 u8 reserved_4[0x20]; 3679 3680 struct mlx5_ifc_qpc_bits qpc; 3681 3682 u8 reserved_5[0x80]; 3683}; 3684 3685struct mlx5_ifc_rtr2rts_qp_out_bits { 3686 u8 status[0x8]; 3687 u8 reserved_0[0x18]; 3688 3689 u8 syndrome[0x20]; 3690 3691 u8 reserved_1[0x40]; 3692}; 3693 3694struct mlx5_ifc_rtr2rts_qp_in_bits { 3695 u8 opcode[0x10]; 3696 u8 reserved_0[0x10]; 3697 3698 u8 reserved_1[0x10]; 3699 u8 op_mod[0x10]; 3700 3701 u8 reserved_2[0x8]; 3702 u8 qpn[0x18]; 3703 3704 u8 reserved_3[0x20]; 3705 3706 u8 opt_param_mask[0x20]; 3707 3708 u8 reserved_4[0x20]; 3709 3710 struct mlx5_ifc_qpc_bits qpc; 3711 3712 u8 reserved_5[0x80]; 3713}; 3714 3715struct mlx5_ifc_rst2init_qp_out_bits { 3716 u8 status[0x8]; 3717 u8 reserved_0[0x18]; 3718 3719 u8 syndrome[0x20]; 3720 3721 u8 reserved_1[0x40]; 3722}; 3723 3724struct mlx5_ifc_rst2init_qp_in_bits { 3725 u8 opcode[0x10]; 3726 u8 reserved_0[0x10]; 3727 3728 u8 reserved_1[0x10]; 3729 u8 op_mod[0x10]; 3730 3731 u8 reserved_2[0x8]; 3732 u8 qpn[0x18]; 3733 3734 u8 reserved_3[0x20]; 3735 3736 u8 opt_param_mask[0x20]; 3737 3738 u8 reserved_4[0x20]; 3739 3740 struct mlx5_ifc_qpc_bits qpc; 3741 3742 u8 reserved_5[0x80]; 3743}; 3744 3745struct mlx5_ifc_resume_qp_out_bits { 3746 u8 status[0x8]; 3747 u8 reserved_0[0x18]; 3748 3749 u8 syndrome[0x20]; 3750 3751 u8 reserved_1[0x40]; 3752}; 3753 3754struct mlx5_ifc_resume_qp_in_bits { 3755 u8 opcode[0x10]; 3756 u8 reserved_0[0x10]; 3757 3758 u8 reserved_1[0x10]; 3759 u8 op_mod[0x10]; 3760 3761 u8 reserved_2[0x8]; 3762 u8 qpn[0x18]; 3763 3764 u8 reserved_3[0x20]; 3765}; 3766 3767struct mlx5_ifc_query_xrc_srq_out_bits { 3768 u8 status[0x8]; 3769 u8 reserved_0[0x18]; 3770 3771 u8 syndrome[0x20]; 3772 3773 u8 reserved_1[0x40]; 3774 3775 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3776 3777 u8 reserved_2[0x600]; 3778 3779 u8 pas[0][0x40]; 3780}; 3781 3782struct mlx5_ifc_query_xrc_srq_in_bits { 3783 u8 opcode[0x10]; 3784 u8 reserved_0[0x10]; 3785 3786 u8 reserved_1[0x10]; 3787 u8 op_mod[0x10]; 3788 3789 u8 reserved_2[0x8]; 3790 u8 xrc_srqn[0x18]; 3791 3792 u8 reserved_3[0x20]; 3793}; 3794 3795struct mlx5_ifc_query_wol_rol_out_bits { 3796 u8 status[0x8]; 3797 u8 reserved_0[0x18]; 3798 3799 u8 syndrome[0x20]; 3800 3801 u8 reserved_1[0x10]; 3802 u8 rol_mode[0x8]; 3803 u8 wol_mode[0x8]; 3804 3805 u8 reserved_2[0x20]; 3806}; 3807 3808struct mlx5_ifc_query_wol_rol_in_bits { 3809 u8 opcode[0x10]; 3810 u8 reserved_0[0x10]; 3811 3812 u8 reserved_1[0x10]; 3813 u8 op_mod[0x10]; 3814 3815 u8 reserved_2[0x40]; 3816}; 3817 3818enum { 3819 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3820 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3821}; 3822 3823struct mlx5_ifc_query_vport_state_out_bits { 3824 u8 status[0x8]; 3825 u8 reserved_0[0x18]; 3826 3827 u8 syndrome[0x20]; 3828 3829 u8 reserved_1[0x20]; 3830 3831 u8 reserved_2[0x18]; 3832 u8 admin_state[0x4]; 3833 u8 state[0x4]; 3834}; 3835 3836enum { 3837 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 3838 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 3839 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 3840}; 3841 3842struct mlx5_ifc_query_vport_state_in_bits { 3843 u8 opcode[0x10]; 3844 u8 reserved_0[0x10]; 3845 3846 u8 reserved_1[0x10]; 3847 u8 op_mod[0x10]; 3848 3849 u8 other_vport[0x1]; 3850 u8 reserved_2[0xf]; 3851 u8 vport_number[0x10]; 3852 3853 u8 reserved_3[0x20]; 3854}; 3855 3856struct mlx5_ifc_query_vport_counter_out_bits { 3857 u8 status[0x8]; 3858 u8 reserved_0[0x18]; 3859 3860 u8 syndrome[0x20]; 3861 3862 u8 reserved_1[0x40]; 3863 3864 struct mlx5_ifc_traffic_counter_bits received_errors; 3865 3866 struct mlx5_ifc_traffic_counter_bits transmit_errors; 3867 3868 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 3869 3870 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 3871 3872 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 3873 3874 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 3875 3876 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 3877 3878 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 3879 3880 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 3881 3882 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 3883 3884 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 3885 3886 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 3887 3888 u8 reserved_2[0xa00]; 3889}; 3890 3891enum { 3892 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 3893}; 3894 3895struct mlx5_ifc_query_vport_counter_in_bits { 3896 u8 opcode[0x10]; 3897 u8 reserved_0[0x10]; 3898 3899 u8 reserved_1[0x10]; 3900 u8 op_mod[0x10]; 3901 3902 u8 other_vport[0x1]; 3903 u8 reserved_2[0xb]; 3904 u8 port_num[0x4]; 3905 u8 vport_number[0x10]; 3906 3907 u8 reserved_3[0x60]; 3908 3909 u8 clear[0x1]; 3910 u8 reserved_4[0x1f]; 3911 3912 u8 reserved_5[0x20]; 3913}; 3914 3915struct mlx5_ifc_query_tis_out_bits { 3916 u8 status[0x8]; 3917 u8 reserved_0[0x18]; 3918 3919 u8 syndrome[0x20]; 3920 3921 u8 reserved_1[0x40]; 3922 3923 struct mlx5_ifc_tisc_bits tis_context; 3924}; 3925 3926struct mlx5_ifc_query_tis_in_bits { 3927 u8 opcode[0x10]; 3928 u8 reserved_0[0x10]; 3929 3930 u8 reserved_1[0x10]; 3931 u8 op_mod[0x10]; 3932 3933 u8 reserved_2[0x8]; 3934 u8 tisn[0x18]; 3935 3936 u8 reserved_3[0x20]; 3937}; 3938 3939struct mlx5_ifc_query_tir_out_bits { 3940 u8 status[0x8]; 3941 u8 reserved_0[0x18]; 3942 3943 u8 syndrome[0x20]; 3944 3945 u8 reserved_1[0xc0]; 3946 3947 struct mlx5_ifc_tirc_bits tir_context; 3948}; 3949 3950struct mlx5_ifc_query_tir_in_bits { 3951 u8 opcode[0x10]; 3952 u8 reserved_0[0x10]; 3953 3954 u8 reserved_1[0x10]; 3955 u8 op_mod[0x10]; 3956 3957 u8 reserved_2[0x8]; 3958 u8 tirn[0x18]; 3959 3960 u8 reserved_3[0x20]; 3961}; 3962 3963struct mlx5_ifc_query_srq_out_bits { 3964 u8 status[0x8]; 3965 u8 reserved_0[0x18]; 3966 3967 u8 syndrome[0x20]; 3968 3969 u8 reserved_1[0x40]; 3970 3971 struct mlx5_ifc_srqc_bits srq_context_entry; 3972 3973 u8 reserved_2[0x600]; 3974 3975 u8 pas[0][0x40]; 3976}; 3977 3978struct mlx5_ifc_query_srq_in_bits { 3979 u8 opcode[0x10]; 3980 u8 reserved_0[0x10]; 3981 3982 u8 reserved_1[0x10]; 3983 u8 op_mod[0x10]; 3984 3985 u8 reserved_2[0x8]; 3986 u8 srqn[0x18]; 3987 3988 u8 reserved_3[0x20]; 3989}; 3990 3991struct mlx5_ifc_query_sq_out_bits { 3992 u8 status[0x8]; 3993 u8 reserved_0[0x18]; 3994 3995 u8 syndrome[0x20]; 3996 3997 u8 reserved_1[0xc0]; 3998 3999 struct mlx5_ifc_sqc_bits sq_context; 4000}; 4001 4002struct mlx5_ifc_query_sq_in_bits { 4003 u8 opcode[0x10]; 4004 u8 reserved_0[0x10]; 4005 4006 u8 reserved_1[0x10]; 4007 u8 op_mod[0x10]; 4008 4009 u8 reserved_2[0x8]; 4010 u8 sqn[0x18]; 4011 4012 u8 reserved_3[0x20]; 4013}; 4014 4015struct mlx5_ifc_query_special_contexts_out_bits { 4016 u8 status[0x8]; 4017 u8 reserved_0[0x18]; 4018 4019 u8 syndrome[0x20]; 4020 4021 u8 dump_fill_mkey[0x20]; 4022 4023 u8 resd_lkey[0x20]; 4024}; 4025 4026struct mlx5_ifc_query_special_contexts_in_bits { 4027 u8 opcode[0x10]; 4028 u8 reserved_0[0x10]; 4029 4030 u8 reserved_1[0x10]; 4031 u8 op_mod[0x10]; 4032 4033 u8 reserved_2[0x40]; 4034}; 4035 4036struct mlx5_ifc_query_scheduling_element_out_bits { 4037 u8 status[0x8]; 4038 u8 reserved_at_8[0x18]; 4039 4040 u8 syndrome[0x20]; 4041 4042 u8 reserved_at_40[0xc0]; 4043 4044 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4045 4046 u8 reserved_at_300[0x100]; 4047}; 4048 4049enum { 4050 MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2, 4051}; 4052 4053struct mlx5_ifc_query_scheduling_element_in_bits { 4054 u8 opcode[0x10]; 4055 u8 reserved_at_10[0x10]; 4056 4057 u8 reserved_at_20[0x10]; 4058 u8 op_mod[0x10]; 4059 4060 u8 scheduling_hierarchy[0x8]; 4061 u8 reserved_at_48[0x18]; 4062 4063 u8 scheduling_element_id[0x20]; 4064 4065 u8 reserved_at_80[0x180]; 4066}; 4067 4068struct mlx5_ifc_query_rqt_out_bits { 4069 u8 status[0x8]; 4070 u8 reserved_0[0x18]; 4071 4072 u8 syndrome[0x20]; 4073 4074 u8 reserved_1[0xc0]; 4075 4076 struct mlx5_ifc_rqtc_bits rqt_context; 4077}; 4078 4079struct mlx5_ifc_query_rqt_in_bits { 4080 u8 opcode[0x10]; 4081 u8 reserved_0[0x10]; 4082 4083 u8 reserved_1[0x10]; 4084 u8 op_mod[0x10]; 4085 4086 u8 reserved_2[0x8]; 4087 u8 rqtn[0x18]; 4088 4089 u8 reserved_3[0x20]; 4090}; 4091 4092struct mlx5_ifc_query_rq_out_bits { 4093 u8 status[0x8]; 4094 u8 reserved_0[0x18]; 4095 4096 u8 syndrome[0x20]; 4097 4098 u8 reserved_1[0xc0]; 4099 4100 struct mlx5_ifc_rqc_bits rq_context; 4101}; 4102 4103struct mlx5_ifc_query_rq_in_bits { 4104 u8 opcode[0x10]; 4105 u8 reserved_0[0x10]; 4106 4107 u8 reserved_1[0x10]; 4108 u8 op_mod[0x10]; 4109 4110 u8 reserved_2[0x8]; 4111 u8 rqn[0x18]; 4112 4113 u8 reserved_3[0x20]; 4114}; 4115 4116struct mlx5_ifc_query_roce_address_out_bits { 4117 u8 status[0x8]; 4118 u8 reserved_0[0x18]; 4119 4120 u8 syndrome[0x20]; 4121 4122 u8 reserved_1[0x40]; 4123 4124 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4125}; 4126 4127struct mlx5_ifc_query_roce_address_in_bits { 4128 u8 opcode[0x10]; 4129 u8 reserved_0[0x10]; 4130 4131 u8 reserved_1[0x10]; 4132 u8 op_mod[0x10]; 4133 4134 u8 roce_address_index[0x10]; 4135 u8 reserved_2[0x10]; 4136 4137 u8 reserved_3[0x20]; 4138}; 4139 4140struct mlx5_ifc_query_rmp_out_bits { 4141 u8 status[0x8]; 4142 u8 reserved_0[0x18]; 4143 4144 u8 syndrome[0x20]; 4145 4146 u8 reserved_1[0xc0]; 4147 4148 struct mlx5_ifc_rmpc_bits rmp_context; 4149}; 4150 4151struct mlx5_ifc_query_rmp_in_bits { 4152 u8 opcode[0x10]; 4153 u8 reserved_0[0x10]; 4154 4155 u8 reserved_1[0x10]; 4156 u8 op_mod[0x10]; 4157 4158 u8 reserved_2[0x8]; 4159 u8 rmpn[0x18]; 4160 4161 u8 reserved_3[0x20]; 4162}; 4163 4164struct mlx5_ifc_query_rdb_out_bits { 4165 u8 status[0x8]; 4166 u8 reserved_0[0x18]; 4167 4168 u8 syndrome[0x20]; 4169 4170 u8 reserved_1[0x20]; 4171 4172 u8 reserved_2[0x18]; 4173 u8 rdb_list_size[0x8]; 4174 4175 struct mlx5_ifc_rdbc_bits rdb_context[0]; 4176}; 4177 4178struct mlx5_ifc_query_rdb_in_bits { 4179 u8 opcode[0x10]; 4180 u8 reserved_0[0x10]; 4181 4182 u8 reserved_1[0x10]; 4183 u8 op_mod[0x10]; 4184 4185 u8 reserved_2[0x8]; 4186 u8 qpn[0x18]; 4187 4188 u8 reserved_3[0x20]; 4189}; 4190 4191struct mlx5_ifc_query_qp_out_bits { 4192 u8 status[0x8]; 4193 u8 reserved_0[0x18]; 4194 4195 u8 syndrome[0x20]; 4196 4197 u8 reserved_1[0x40]; 4198 4199 u8 opt_param_mask[0x20]; 4200 4201 u8 reserved_2[0x20]; 4202 4203 struct mlx5_ifc_qpc_bits qpc; 4204 4205 u8 reserved_3[0x80]; 4206 4207 u8 pas[0][0x40]; 4208}; 4209 4210struct mlx5_ifc_query_qp_in_bits { 4211 u8 opcode[0x10]; 4212 u8 reserved_0[0x10]; 4213 4214 u8 reserved_1[0x10]; 4215 u8 op_mod[0x10]; 4216 4217 u8 reserved_2[0x8]; 4218 u8 qpn[0x18]; 4219 4220 u8 reserved_3[0x20]; 4221}; 4222 4223struct mlx5_ifc_query_q_counter_out_bits { 4224 u8 status[0x8]; 4225 u8 reserved_0[0x18]; 4226 4227 u8 syndrome[0x20]; 4228 4229 u8 reserved_1[0x40]; 4230 4231 u8 rx_write_requests[0x20]; 4232 4233 u8 reserved_2[0x20]; 4234 4235 u8 rx_read_requests[0x20]; 4236 4237 u8 reserved_3[0x20]; 4238 4239 u8 rx_atomic_requests[0x20]; 4240 4241 u8 reserved_4[0x20]; 4242 4243 u8 rx_dct_connect[0x20]; 4244 4245 u8 reserved_5[0x20]; 4246 4247 u8 out_of_buffer[0x20]; 4248 4249 u8 reserved_7[0x20]; 4250 4251 u8 out_of_sequence[0x20]; 4252 4253 u8 reserved_8[0x20]; 4254 4255 u8 duplicate_request[0x20]; 4256 4257 u8 reserved_9[0x20]; 4258 4259 u8 rnr_nak_retry_err[0x20]; 4260 4261 u8 reserved_10[0x20]; 4262 4263 u8 packet_seq_err[0x20]; 4264 4265 u8 reserved_11[0x20]; 4266 4267 u8 implied_nak_seq_err[0x20]; 4268 4269 u8 reserved_12[0x20]; 4270 4271 u8 local_ack_timeout_err[0x20]; 4272 4273 u8 reserved_13[0x20]; 4274 4275 u8 resp_rnr_nak[0x20]; 4276 4277 u8 reserved_14[0x20]; 4278 4279 u8 req_rnr_retries_exceeded[0x20]; 4280 4281 u8 reserved_15[0x460]; 4282}; 4283 4284struct mlx5_ifc_query_q_counter_in_bits { 4285 u8 opcode[0x10]; 4286 u8 reserved_0[0x10]; 4287 4288 u8 reserved_1[0x10]; 4289 u8 op_mod[0x10]; 4290 4291 u8 reserved_2[0x80]; 4292 4293 u8 clear[0x1]; 4294 u8 reserved_3[0x1f]; 4295 4296 u8 reserved_4[0x18]; 4297 u8 counter_set_id[0x8]; 4298}; 4299 4300struct mlx5_ifc_query_pages_out_bits { 4301 u8 status[0x8]; 4302 u8 reserved_0[0x18]; 4303 4304 u8 syndrome[0x20]; 4305 4306 u8 reserved_1[0x10]; 4307 u8 function_id[0x10]; 4308 4309 u8 num_pages[0x20]; 4310}; 4311 4312enum { 4313 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4314 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4315 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4316}; 4317 4318struct mlx5_ifc_query_pages_in_bits { 4319 u8 opcode[0x10]; 4320 u8 reserved_0[0x10]; 4321 4322 u8 reserved_1[0x10]; 4323 u8 op_mod[0x10]; 4324 4325 u8 reserved_2[0x10]; 4326 u8 function_id[0x10]; 4327 4328 u8 reserved_3[0x20]; 4329}; 4330 4331struct mlx5_ifc_query_nic_vport_context_out_bits { 4332 u8 status[0x8]; 4333 u8 reserved_0[0x18]; 4334 4335 u8 syndrome[0x20]; 4336 4337 u8 reserved_1[0x40]; 4338 4339 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4340}; 4341 4342struct mlx5_ifc_query_nic_vport_context_in_bits { 4343 u8 opcode[0x10]; 4344 u8 reserved_0[0x10]; 4345 4346 u8 reserved_1[0x10]; 4347 u8 op_mod[0x10]; 4348 4349 u8 other_vport[0x1]; 4350 u8 reserved_2[0xf]; 4351 u8 vport_number[0x10]; 4352 4353 u8 reserved_3[0x5]; 4354 u8 allowed_list_type[0x3]; 4355 u8 reserved_4[0x18]; 4356}; 4357 4358struct mlx5_ifc_query_mkey_out_bits { 4359 u8 status[0x8]; 4360 u8 reserved_0[0x18]; 4361 4362 u8 syndrome[0x20]; 4363 4364 u8 reserved_1[0x40]; 4365 4366 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4367 4368 u8 reserved_2[0x600]; 4369 4370 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4371 4372 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4373}; 4374 4375struct mlx5_ifc_query_mkey_in_bits { 4376 u8 opcode[0x10]; 4377 u8 reserved_0[0x10]; 4378 4379 u8 reserved_1[0x10]; 4380 u8 op_mod[0x10]; 4381 4382 u8 reserved_2[0x8]; 4383 u8 mkey_index[0x18]; 4384 4385 u8 pg_access[0x1]; 4386 u8 reserved_3[0x1f]; 4387}; 4388 4389struct mlx5_ifc_query_mad_demux_out_bits { 4390 u8 status[0x8]; 4391 u8 reserved_0[0x18]; 4392 4393 u8 syndrome[0x20]; 4394 4395 u8 reserved_1[0x40]; 4396 4397 u8 mad_dumux_parameters_block[0x20]; 4398}; 4399 4400struct mlx5_ifc_query_mad_demux_in_bits { 4401 u8 opcode[0x10]; 4402 u8 reserved_0[0x10]; 4403 4404 u8 reserved_1[0x10]; 4405 u8 op_mod[0x10]; 4406 4407 u8 reserved_2[0x40]; 4408}; 4409 4410struct mlx5_ifc_query_l2_table_entry_out_bits { 4411 u8 status[0x8]; 4412 u8 reserved_0[0x18]; 4413 4414 u8 syndrome[0x20]; 4415 4416 u8 reserved_1[0xa0]; 4417 4418 u8 reserved_2[0x13]; 4419 u8 vlan_valid[0x1]; 4420 u8 vlan[0xc]; 4421 4422 struct mlx5_ifc_mac_address_layout_bits mac_address; 4423 4424 u8 reserved_3[0xc0]; 4425}; 4426 4427struct mlx5_ifc_query_l2_table_entry_in_bits { 4428 u8 opcode[0x10]; 4429 u8 reserved_0[0x10]; 4430 4431 u8 reserved_1[0x10]; 4432 u8 op_mod[0x10]; 4433 4434 u8 reserved_2[0x60]; 4435 4436 u8 reserved_3[0x8]; 4437 u8 table_index[0x18]; 4438 4439 u8 reserved_4[0x140]; 4440}; 4441 4442struct mlx5_ifc_query_issi_out_bits { 4443 u8 status[0x8]; 4444 u8 reserved_0[0x18]; 4445 4446 u8 syndrome[0x20]; 4447 4448 u8 reserved_1[0x10]; 4449 u8 current_issi[0x10]; 4450 4451 u8 reserved_2[0xa0]; 4452 4453 u8 supported_issi_reserved[76][0x8]; 4454 u8 supported_issi_dw0[0x20]; 4455}; 4456 4457struct mlx5_ifc_query_issi_in_bits { 4458 u8 opcode[0x10]; 4459 u8 reserved_0[0x10]; 4460 4461 u8 reserved_1[0x10]; 4462 u8 op_mod[0x10]; 4463 4464 u8 reserved_2[0x40]; 4465}; 4466 4467struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4468 u8 status[0x8]; 4469 u8 reserved_0[0x18]; 4470 4471 u8 syndrome[0x20]; 4472 4473 u8 reserved_1[0x40]; 4474 4475 struct mlx5_ifc_pkey_bits pkey[0]; 4476}; 4477 4478struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4479 u8 opcode[0x10]; 4480 u8 reserved_0[0x10]; 4481 4482 u8 reserved_1[0x10]; 4483 u8 op_mod[0x10]; 4484 4485 u8 other_vport[0x1]; 4486 u8 reserved_2[0xb]; 4487 u8 port_num[0x4]; 4488 u8 vport_number[0x10]; 4489 4490 u8 reserved_3[0x10]; 4491 u8 pkey_index[0x10]; 4492}; 4493 4494struct mlx5_ifc_query_hca_vport_gid_out_bits { 4495 u8 status[0x8]; 4496 u8 reserved_0[0x18]; 4497 4498 u8 syndrome[0x20]; 4499 4500 u8 reserved_1[0x20]; 4501 4502 u8 gids_num[0x10]; 4503 u8 reserved_2[0x10]; 4504 4505 struct mlx5_ifc_array128_auto_bits gid[0]; 4506}; 4507 4508struct mlx5_ifc_query_hca_vport_gid_in_bits { 4509 u8 opcode[0x10]; 4510 u8 reserved_0[0x10]; 4511 4512 u8 reserved_1[0x10]; 4513 u8 op_mod[0x10]; 4514 4515 u8 other_vport[0x1]; 4516 u8 reserved_2[0xb]; 4517 u8 port_num[0x4]; 4518 u8 vport_number[0x10]; 4519 4520 u8 reserved_3[0x10]; 4521 u8 gid_index[0x10]; 4522}; 4523 4524struct mlx5_ifc_query_hca_vport_context_out_bits { 4525 u8 status[0x8]; 4526 u8 reserved_0[0x18]; 4527 4528 u8 syndrome[0x20]; 4529 4530 u8 reserved_1[0x40]; 4531 4532 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4533}; 4534 4535struct mlx5_ifc_query_hca_vport_context_in_bits { 4536 u8 opcode[0x10]; 4537 u8 reserved_0[0x10]; 4538 4539 u8 reserved_1[0x10]; 4540 u8 op_mod[0x10]; 4541 4542 u8 other_vport[0x1]; 4543 u8 reserved_2[0xb]; 4544 u8 port_num[0x4]; 4545 u8 vport_number[0x10]; 4546 4547 u8 reserved_3[0x20]; 4548}; 4549 4550struct mlx5_ifc_query_hca_cap_out_bits { 4551 u8 status[0x8]; 4552 u8 reserved_0[0x18]; 4553 4554 u8 syndrome[0x20]; 4555 4556 u8 reserved_1[0x40]; 4557 4558 union mlx5_ifc_hca_cap_union_bits capability; 4559}; 4560 4561struct mlx5_ifc_query_hca_cap_in_bits { 4562 u8 opcode[0x10]; 4563 u8 reserved_0[0x10]; 4564 4565 u8 reserved_1[0x10]; 4566 u8 op_mod[0x10]; 4567 4568 u8 reserved_2[0x40]; 4569}; 4570 4571struct mlx5_ifc_query_flow_table_out_bits { 4572 u8 status[0x8]; 4573 u8 reserved_at_8[0x18]; 4574 4575 u8 syndrome[0x20]; 4576 4577 u8 reserved_at_40[0x80]; 4578 4579 struct mlx5_ifc_flow_table_context_bits flow_table_context; 4580}; 4581 4582struct mlx5_ifc_query_flow_table_in_bits { 4583 u8 opcode[0x10]; 4584 u8 reserved_0[0x10]; 4585 4586 u8 reserved_1[0x10]; 4587 u8 op_mod[0x10]; 4588 4589 u8 other_vport[0x1]; 4590 u8 reserved_2[0xf]; 4591 u8 vport_number[0x10]; 4592 4593 u8 reserved_3[0x20]; 4594 4595 u8 table_type[0x8]; 4596 u8 reserved_4[0x18]; 4597 4598 u8 reserved_5[0x8]; 4599 u8 table_id[0x18]; 4600 4601 u8 reserved_6[0x140]; 4602}; 4603 4604struct mlx5_ifc_query_fte_out_bits { 4605 u8 status[0x8]; 4606 u8 reserved_0[0x18]; 4607 4608 u8 syndrome[0x20]; 4609 4610 u8 reserved_1[0x1c0]; 4611 4612 struct mlx5_ifc_flow_context_bits flow_context; 4613}; 4614 4615struct mlx5_ifc_query_fte_in_bits { 4616 u8 opcode[0x10]; 4617 u8 reserved_0[0x10]; 4618 4619 u8 reserved_1[0x10]; 4620 u8 op_mod[0x10]; 4621 4622 u8 other_vport[0x1]; 4623 u8 reserved_2[0xf]; 4624 u8 vport_number[0x10]; 4625 4626 u8 reserved_3[0x20]; 4627 4628 u8 table_type[0x8]; 4629 u8 reserved_4[0x18]; 4630 4631 u8 reserved_5[0x8]; 4632 u8 table_id[0x18]; 4633 4634 u8 reserved_6[0x40]; 4635 4636 u8 flow_index[0x20]; 4637 4638 u8 reserved_7[0xe0]; 4639}; 4640 4641enum { 4642 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4643 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4644 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4645}; 4646 4647struct mlx5_ifc_query_flow_group_out_bits { 4648 u8 status[0x8]; 4649 u8 reserved_0[0x18]; 4650 4651 u8 syndrome[0x20]; 4652 4653 u8 reserved_1[0xa0]; 4654 4655 u8 start_flow_index[0x20]; 4656 4657 u8 reserved_2[0x20]; 4658 4659 u8 end_flow_index[0x20]; 4660 4661 u8 reserved_3[0xa0]; 4662 4663 u8 reserved_4[0x18]; 4664 u8 match_criteria_enable[0x8]; 4665 4666 struct mlx5_ifc_fte_match_param_bits match_criteria; 4667 4668 u8 reserved_5[0xe00]; 4669}; 4670 4671struct mlx5_ifc_query_flow_group_in_bits { 4672 u8 opcode[0x10]; 4673 u8 reserved_0[0x10]; 4674 4675 u8 reserved_1[0x10]; 4676 u8 op_mod[0x10]; 4677 4678 u8 other_vport[0x1]; 4679 u8 reserved_2[0xf]; 4680 u8 vport_number[0x10]; 4681 4682 u8 reserved_3[0x20]; 4683 4684 u8 table_type[0x8]; 4685 u8 reserved_4[0x18]; 4686 4687 u8 reserved_5[0x8]; 4688 u8 table_id[0x18]; 4689 4690 u8 group_id[0x20]; 4691 4692 u8 reserved_6[0x120]; 4693}; 4694 4695struct mlx5_ifc_query_flow_counter_out_bits { 4696 u8 status[0x8]; 4697 u8 reserved_at_8[0x18]; 4698 4699 u8 syndrome[0x20]; 4700 4701 u8 reserved_at_40[0x40]; 4702 4703 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4704}; 4705 4706struct mlx5_ifc_query_flow_counter_in_bits { 4707 u8 opcode[0x10]; 4708 u8 reserved_at_10[0x10]; 4709 4710 u8 reserved_at_20[0x10]; 4711 u8 op_mod[0x10]; 4712 4713 u8 reserved_at_40[0x80]; 4714 4715 u8 clear[0x1]; 4716 u8 reserved_at_c1[0xf]; 4717 u8 num_of_counters[0x10]; 4718 4719 u8 reserved_at_e0[0x10]; 4720 u8 flow_counter_id[0x10]; 4721}; 4722 4723struct mlx5_ifc_query_esw_vport_context_out_bits { 4724 u8 status[0x8]; 4725 u8 reserved_0[0x18]; 4726 4727 u8 syndrome[0x20]; 4728 4729 u8 reserved_1[0x40]; 4730 4731 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4732}; 4733 4734struct mlx5_ifc_query_esw_vport_context_in_bits { 4735 u8 opcode[0x10]; 4736 u8 reserved_0[0x10]; 4737 4738 u8 reserved_1[0x10]; 4739 u8 op_mod[0x10]; 4740 4741 u8 other_vport[0x1]; 4742 u8 reserved_2[0xf]; 4743 u8 vport_number[0x10]; 4744 4745 u8 reserved_3[0x20]; 4746}; 4747 4748struct mlx5_ifc_query_eq_out_bits { 4749 u8 status[0x8]; 4750 u8 reserved_0[0x18]; 4751 4752 u8 syndrome[0x20]; 4753 4754 u8 reserved_1[0x40]; 4755 4756 struct mlx5_ifc_eqc_bits eq_context_entry; 4757 4758 u8 reserved_2[0x40]; 4759 4760 u8 event_bitmask[0x40]; 4761 4762 u8 reserved_3[0x580]; 4763 4764 u8 pas[0][0x40]; 4765}; 4766 4767struct mlx5_ifc_query_eq_in_bits { 4768 u8 opcode[0x10]; 4769 u8 reserved_0[0x10]; 4770 4771 u8 reserved_1[0x10]; 4772 u8 op_mod[0x10]; 4773 4774 u8 reserved_2[0x18]; 4775 u8 eq_number[0x8]; 4776 4777 u8 reserved_3[0x20]; 4778}; 4779 4780struct mlx5_ifc_query_dct_out_bits { 4781 u8 status[0x8]; 4782 u8 reserved_0[0x18]; 4783 4784 u8 syndrome[0x20]; 4785 4786 u8 reserved_1[0x40]; 4787 4788 struct mlx5_ifc_dctc_bits dct_context_entry; 4789 4790 u8 reserved_2[0x180]; 4791}; 4792 4793struct mlx5_ifc_query_dct_in_bits { 4794 u8 opcode[0x10]; 4795 u8 reserved_0[0x10]; 4796 4797 u8 reserved_1[0x10]; 4798 u8 op_mod[0x10]; 4799 4800 u8 reserved_2[0x8]; 4801 u8 dctn[0x18]; 4802 4803 u8 reserved_3[0x20]; 4804}; 4805 4806struct mlx5_ifc_query_dc_cnak_trace_out_bits { 4807 u8 status[0x8]; 4808 u8 reserved_0[0x18]; 4809 4810 u8 syndrome[0x20]; 4811 4812 u8 enable[0x1]; 4813 u8 reserved_1[0x1f]; 4814 4815 u8 reserved_2[0x160]; 4816 4817 struct mlx5_ifc_cmd_pas_bits pas; 4818}; 4819 4820struct mlx5_ifc_query_dc_cnak_trace_in_bits { 4821 u8 opcode[0x10]; 4822 u8 reserved_0[0x10]; 4823 4824 u8 reserved_1[0x10]; 4825 u8 op_mod[0x10]; 4826 4827 u8 reserved_2[0x40]; 4828}; 4829 4830struct mlx5_ifc_query_cq_out_bits { 4831 u8 status[0x8]; 4832 u8 reserved_0[0x18]; 4833 4834 u8 syndrome[0x20]; 4835 4836 u8 reserved_1[0x40]; 4837 4838 struct mlx5_ifc_cqc_bits cq_context; 4839 4840 u8 reserved_2[0x600]; 4841 4842 u8 pas[0][0x40]; 4843}; 4844 4845struct mlx5_ifc_query_cq_in_bits { 4846 u8 opcode[0x10]; 4847 u8 reserved_0[0x10]; 4848 4849 u8 reserved_1[0x10]; 4850 u8 op_mod[0x10]; 4851 4852 u8 reserved_2[0x8]; 4853 u8 cqn[0x18]; 4854 4855 u8 reserved_3[0x20]; 4856}; 4857 4858struct mlx5_ifc_query_cong_status_out_bits { 4859 u8 status[0x8]; 4860 u8 reserved_0[0x18]; 4861 4862 u8 syndrome[0x20]; 4863 4864 u8 reserved_1[0x20]; 4865 4866 u8 enable[0x1]; 4867 u8 tag_enable[0x1]; 4868 u8 reserved_2[0x1e]; 4869}; 4870 4871struct mlx5_ifc_query_cong_status_in_bits { 4872 u8 opcode[0x10]; 4873 u8 reserved_0[0x10]; 4874 4875 u8 reserved_1[0x10]; 4876 u8 op_mod[0x10]; 4877 4878 u8 reserved_2[0x18]; 4879 u8 priority[0x4]; 4880 u8 cong_protocol[0x4]; 4881 4882 u8 reserved_3[0x20]; 4883}; 4884 4885struct mlx5_ifc_query_cong_statistics_out_bits { 4886 u8 status[0x8]; 4887 u8 reserved_0[0x18]; 4888 4889 u8 syndrome[0x20]; 4890 4891 u8 reserved_1[0x40]; 4892 4893 u8 rp_cur_flows[0x20]; 4894 4895 u8 sum_flows[0x20]; 4896 4897 u8 rp_cnp_ignored_high[0x20]; 4898 4899 u8 rp_cnp_ignored_low[0x20]; 4900 4901 u8 rp_cnp_handled_high[0x20]; 4902 4903 u8 rp_cnp_handled_low[0x20]; 4904 4905 u8 reserved_2[0x100]; 4906 4907 u8 time_stamp_high[0x20]; 4908 4909 u8 time_stamp_low[0x20]; 4910 4911 u8 accumulators_period[0x20]; 4912 4913 u8 np_ecn_marked_roce_packets_high[0x20]; 4914 4915 u8 np_ecn_marked_roce_packets_low[0x20]; 4916 4917 u8 np_cnp_sent_high[0x20]; 4918 4919 u8 np_cnp_sent_low[0x20]; 4920 4921 u8 reserved_3[0x560]; 4922}; 4923 4924struct mlx5_ifc_query_cong_statistics_in_bits { 4925 u8 opcode[0x10]; 4926 u8 reserved_0[0x10]; 4927 4928 u8 reserved_1[0x10]; 4929 u8 op_mod[0x10]; 4930 4931 u8 clear[0x1]; 4932 u8 reserved_2[0x1f]; 4933 4934 u8 reserved_3[0x20]; 4935}; 4936 4937struct mlx5_ifc_query_cong_params_out_bits { 4938 u8 status[0x8]; 4939 u8 reserved_0[0x18]; 4940 4941 u8 syndrome[0x20]; 4942 4943 u8 reserved_1[0x40]; 4944 4945 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 4946}; 4947 4948struct mlx5_ifc_query_cong_params_in_bits { 4949 u8 opcode[0x10]; 4950 u8 reserved_0[0x10]; 4951 4952 u8 reserved_1[0x10]; 4953 u8 op_mod[0x10]; 4954 4955 u8 reserved_2[0x1c]; 4956 u8 cong_protocol[0x4]; 4957 4958 u8 reserved_3[0x20]; 4959}; 4960 4961struct mlx5_ifc_query_burst_size_out_bits { 4962 u8 status[0x8]; 4963 u8 reserved_0[0x18]; 4964 4965 u8 syndrome[0x20]; 4966 4967 u8 reserved_1[0x20]; 4968 4969 u8 reserved_2[0x9]; 4970 u8 device_burst_size[0x17]; 4971}; 4972 4973struct mlx5_ifc_query_burst_size_in_bits { 4974 u8 opcode[0x10]; 4975 u8 reserved_0[0x10]; 4976 4977 u8 reserved_1[0x10]; 4978 u8 op_mod[0x10]; 4979 4980 u8 reserved_2[0x40]; 4981}; 4982 4983struct mlx5_ifc_query_adapter_out_bits { 4984 u8 status[0x8]; 4985 u8 reserved_0[0x18]; 4986 4987 u8 syndrome[0x20]; 4988 4989 u8 reserved_1[0x40]; 4990 4991 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 4992}; 4993 4994struct mlx5_ifc_query_adapter_in_bits { 4995 u8 opcode[0x10]; 4996 u8 reserved_0[0x10]; 4997 4998 u8 reserved_1[0x10]; 4999 u8 op_mod[0x10]; 5000 5001 u8 reserved_2[0x40]; 5002}; 5003 5004struct mlx5_ifc_qp_2rst_out_bits { 5005 u8 status[0x8]; 5006 u8 reserved_0[0x18]; 5007 5008 u8 syndrome[0x20]; 5009 5010 u8 reserved_1[0x40]; 5011}; 5012 5013struct mlx5_ifc_qp_2rst_in_bits { 5014 u8 opcode[0x10]; 5015 u8 reserved_0[0x10]; 5016 5017 u8 reserved_1[0x10]; 5018 u8 op_mod[0x10]; 5019 5020 u8 reserved_2[0x8]; 5021 u8 qpn[0x18]; 5022 5023 u8 reserved_3[0x20]; 5024}; 5025 5026struct mlx5_ifc_qp_2err_out_bits { 5027 u8 status[0x8]; 5028 u8 reserved_0[0x18]; 5029 5030 u8 syndrome[0x20]; 5031 5032 u8 reserved_1[0x40]; 5033}; 5034 5035struct mlx5_ifc_qp_2err_in_bits { 5036 u8 opcode[0x10]; 5037 u8 reserved_0[0x10]; 5038 5039 u8 reserved_1[0x10]; 5040 u8 op_mod[0x10]; 5041 5042 u8 reserved_2[0x8]; 5043 u8 qpn[0x18]; 5044 5045 u8 reserved_3[0x20]; 5046}; 5047 5048struct mlx5_ifc_para_vport_element_bits { 5049 u8 reserved_at_0[0xc]; 5050 u8 traffic_class[0x4]; 5051 u8 qos_para_vport_number[0x10]; 5052}; 5053 5054struct mlx5_ifc_page_fault_resume_out_bits { 5055 u8 status[0x8]; 5056 u8 reserved_0[0x18]; 5057 5058 u8 syndrome[0x20]; 5059 5060 u8 reserved_1[0x40]; 5061}; 5062 5063struct mlx5_ifc_page_fault_resume_in_bits { 5064 u8 opcode[0x10]; 5065 u8 reserved_0[0x10]; 5066 5067 u8 reserved_1[0x10]; 5068 u8 op_mod[0x10]; 5069 5070 u8 error[0x1]; 5071 u8 reserved_2[0x4]; 5072 u8 rdma[0x1]; 5073 u8 read_write[0x1]; 5074 u8 req_res[0x1]; 5075 u8 qpn[0x18]; 5076 5077 u8 reserved_3[0x20]; 5078}; 5079 5080struct mlx5_ifc_nop_out_bits { 5081 u8 status[0x8]; 5082 u8 reserved_0[0x18]; 5083 5084 u8 syndrome[0x20]; 5085 5086 u8 reserved_1[0x40]; 5087}; 5088 5089struct mlx5_ifc_nop_in_bits { 5090 u8 opcode[0x10]; 5091 u8 reserved_0[0x10]; 5092 5093 u8 reserved_1[0x10]; 5094 u8 op_mod[0x10]; 5095 5096 u8 reserved_2[0x40]; 5097}; 5098 5099struct mlx5_ifc_modify_vport_state_out_bits { 5100 u8 status[0x8]; 5101 u8 reserved_0[0x18]; 5102 5103 u8 syndrome[0x20]; 5104 5105 u8 reserved_1[0x40]; 5106}; 5107 5108enum { 5109 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT = 0x0, 5110 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 5111 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 5112}; 5113 5114enum { 5115 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN = 0x0, 5116 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP = 0x1, 5117 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW = 0x2, 5118}; 5119 5120struct mlx5_ifc_modify_vport_state_in_bits { 5121 u8 opcode[0x10]; 5122 u8 reserved_0[0x10]; 5123 5124 u8 reserved_1[0x10]; 5125 u8 op_mod[0x10]; 5126 5127 u8 other_vport[0x1]; 5128 u8 reserved_2[0xf]; 5129 u8 vport_number[0x10]; 5130 5131 u8 reserved_3[0x18]; 5132 u8 admin_state[0x4]; 5133 u8 reserved_4[0x4]; 5134}; 5135 5136struct mlx5_ifc_modify_tis_out_bits { 5137 u8 status[0x8]; 5138 u8 reserved_0[0x18]; 5139 5140 u8 syndrome[0x20]; 5141 5142 u8 reserved_1[0x40]; 5143}; 5144 5145struct mlx5_ifc_modify_tis_bitmask_bits { 5146 u8 reserved_at_0[0x20]; 5147 5148 u8 reserved_at_20[0x1d]; 5149 u8 lag_tx_port_affinity[0x1]; 5150 u8 strict_lag_tx_port_affinity[0x1]; 5151 u8 prio[0x1]; 5152}; 5153 5154struct mlx5_ifc_modify_tis_in_bits { 5155 u8 opcode[0x10]; 5156 u8 reserved_0[0x10]; 5157 5158 u8 reserved_1[0x10]; 5159 u8 op_mod[0x10]; 5160 5161 u8 reserved_2[0x8]; 5162 u8 tisn[0x18]; 5163 5164 u8 reserved_3[0x20]; 5165 5166 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5167 5168 u8 reserved_4[0x40]; 5169 5170 struct mlx5_ifc_tisc_bits ctx; 5171}; 5172 5173struct mlx5_ifc_modify_tir_out_bits { 5174 u8 status[0x8]; 5175 u8 reserved_0[0x18]; 5176 5177 u8 syndrome[0x20]; 5178 5179 u8 reserved_1[0x40]; 5180}; 5181 5182enum 5183{ 5184 MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0, 5185 MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER = 0x1 << 1 5186}; 5187 5188struct mlx5_ifc_modify_tir_in_bits { 5189 u8 opcode[0x10]; 5190 u8 reserved_0[0x10]; 5191 5192 u8 reserved_1[0x10]; 5193 u8 op_mod[0x10]; 5194 5195 u8 reserved_2[0x8]; 5196 u8 tirn[0x18]; 5197 5198 u8 reserved_3[0x20]; 5199 5200 u8 modify_bitmask[0x40]; 5201 5202 u8 reserved_4[0x40]; 5203 5204 struct mlx5_ifc_tirc_bits tir_context; 5205}; 5206 5207struct mlx5_ifc_modify_sq_out_bits { 5208 u8 status[0x8]; 5209 u8 reserved_0[0x18]; 5210 5211 u8 syndrome[0x20]; 5212 5213 u8 reserved_1[0x40]; 5214}; 5215 5216struct mlx5_ifc_modify_sq_in_bits { 5217 u8 opcode[0x10]; 5218 u8 reserved_0[0x10]; 5219 5220 u8 reserved_1[0x10]; 5221 u8 op_mod[0x10]; 5222 5223 u8 sq_state[0x4]; 5224 u8 reserved_2[0x4]; 5225 u8 sqn[0x18]; 5226 5227 u8 reserved_3[0x20]; 5228 5229 u8 modify_bitmask[0x40]; 5230 5231 u8 reserved_4[0x40]; 5232 5233 struct mlx5_ifc_sqc_bits ctx; 5234}; 5235 5236struct mlx5_ifc_modify_scheduling_element_out_bits { 5237 u8 status[0x8]; 5238 u8 reserved_at_8[0x18]; 5239 5240 u8 syndrome[0x20]; 5241 5242 u8 reserved_at_40[0x1c0]; 5243}; 5244 5245enum { 5246 MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5247}; 5248 5249enum { 5250 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE = 0x1, 5251 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW = 0x2, 5252}; 5253 5254struct mlx5_ifc_modify_scheduling_element_in_bits { 5255 u8 opcode[0x10]; 5256 u8 reserved_at_10[0x10]; 5257 5258 u8 reserved_at_20[0x10]; 5259 u8 op_mod[0x10]; 5260 5261 u8 scheduling_hierarchy[0x8]; 5262 u8 reserved_at_48[0x18]; 5263 5264 u8 scheduling_element_id[0x20]; 5265 5266 u8 reserved_at_80[0x20]; 5267 5268 u8 modify_bitmask[0x20]; 5269 5270 u8 reserved_at_c0[0x40]; 5271 5272 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5273 5274 u8 reserved_at_300[0x100]; 5275}; 5276 5277struct mlx5_ifc_modify_rqt_out_bits { 5278 u8 status[0x8]; 5279 u8 reserved_0[0x18]; 5280 5281 u8 syndrome[0x20]; 5282 5283 u8 reserved_1[0x40]; 5284}; 5285 5286struct mlx5_ifc_modify_rqt_in_bits { 5287 u8 opcode[0x10]; 5288 u8 reserved_0[0x10]; 5289 5290 u8 reserved_1[0x10]; 5291 u8 op_mod[0x10]; 5292 5293 u8 reserved_2[0x8]; 5294 u8 rqtn[0x18]; 5295 5296 u8 reserved_3[0x20]; 5297 5298 u8 modify_bitmask[0x40]; 5299 5300 u8 reserved_4[0x40]; 5301 5302 struct mlx5_ifc_rqtc_bits ctx; 5303}; 5304 5305struct mlx5_ifc_modify_rq_out_bits { 5306 u8 status[0x8]; 5307 u8 reserved_0[0x18]; 5308 5309 u8 syndrome[0x20]; 5310 5311 u8 reserved_1[0x40]; 5312}; 5313 5314enum { 5315 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5316 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3, 5317}; 5318 5319struct mlx5_ifc_modify_rq_in_bits { 5320 u8 opcode[0x10]; 5321 u8 reserved_0[0x10]; 5322 5323 u8 reserved_1[0x10]; 5324 u8 op_mod[0x10]; 5325 5326 u8 rq_state[0x4]; 5327 u8 reserved_2[0x4]; 5328 u8 rqn[0x18]; 5329 5330 u8 reserved_3[0x20]; 5331 5332 u8 modify_bitmask[0x40]; 5333 5334 u8 reserved_4[0x40]; 5335 5336 struct mlx5_ifc_rqc_bits ctx; 5337}; 5338 5339struct mlx5_ifc_modify_rmp_out_bits { 5340 u8 status[0x8]; 5341 u8 reserved_0[0x18]; 5342 5343 u8 syndrome[0x20]; 5344 5345 u8 reserved_1[0x40]; 5346}; 5347 5348struct mlx5_ifc_rmp_bitmask_bits { 5349 u8 reserved[0x20]; 5350 5351 u8 reserved1[0x1f]; 5352 u8 lwm[0x1]; 5353}; 5354 5355struct mlx5_ifc_modify_rmp_in_bits { 5356 u8 opcode[0x10]; 5357 u8 reserved_0[0x10]; 5358 5359 u8 reserved_1[0x10]; 5360 u8 op_mod[0x10]; 5361 5362 u8 rmp_state[0x4]; 5363 u8 reserved_2[0x4]; 5364 u8 rmpn[0x18]; 5365 5366 u8 reserved_3[0x20]; 5367 5368 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5369 5370 u8 reserved_4[0x40]; 5371 5372 struct mlx5_ifc_rmpc_bits ctx; 5373}; 5374 5375struct mlx5_ifc_modify_nic_vport_context_out_bits { 5376 u8 status[0x8]; 5377 u8 reserved_0[0x18]; 5378 5379 u8 syndrome[0x20]; 5380 5381 u8 reserved_1[0x40]; 5382}; 5383 5384struct mlx5_ifc_modify_nic_vport_field_select_bits { 5385 u8 reserved_0[0x14]; 5386 u8 disable_uc_local_lb[0x1]; 5387 u8 disable_mc_local_lb[0x1]; 5388 u8 node_guid[0x1]; 5389 u8 port_guid[0x1]; 5390 u8 min_wqe_inline_mode[0x1]; 5391 u8 mtu[0x1]; 5392 u8 change_event[0x1]; 5393 u8 promisc[0x1]; 5394 u8 permanent_address[0x1]; 5395 u8 addresses_list[0x1]; 5396 u8 roce_en[0x1]; 5397 u8 reserved_1[0x1]; 5398}; 5399 5400struct mlx5_ifc_modify_nic_vport_context_in_bits { 5401 u8 opcode[0x10]; 5402 u8 reserved_0[0x10]; 5403 5404 u8 reserved_1[0x10]; 5405 u8 op_mod[0x10]; 5406 5407 u8 other_vport[0x1]; 5408 u8 reserved_2[0xf]; 5409 u8 vport_number[0x10]; 5410 5411 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5412 5413 u8 reserved_3[0x780]; 5414 5415 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5416}; 5417 5418struct mlx5_ifc_modify_hca_vport_context_out_bits { 5419 u8 status[0x8]; 5420 u8 reserved_0[0x18]; 5421 5422 u8 syndrome[0x20]; 5423 5424 u8 reserved_1[0x40]; 5425}; 5426 5427struct mlx5_ifc_grh_bits { 5428 u8 ip_version[4]; 5429 u8 traffic_class[8]; 5430 u8 flow_label[20]; 5431 u8 payload_length[16]; 5432 u8 next_header[8]; 5433 u8 hop_limit[8]; 5434 u8 sgid[128]; 5435 u8 dgid[128]; 5436}; 5437 5438struct mlx5_ifc_bth_bits { 5439 u8 opcode[8]; 5440 u8 se[1]; 5441 u8 migreq[1]; 5442 u8 pad_count[2]; 5443 u8 tver[4]; 5444 u8 p_key[16]; 5445 u8 reserved8[8]; 5446 u8 dest_qp[24]; 5447 u8 ack_req[1]; 5448 u8 reserved7[7]; 5449 u8 psn[24]; 5450}; 5451 5452struct mlx5_ifc_aeth_bits { 5453 u8 syndrome[8]; 5454 u8 msn[24]; 5455}; 5456 5457struct mlx5_ifc_dceth_bits { 5458 u8 reserved0[8]; 5459 u8 session_id[24]; 5460 u8 reserved1[8]; 5461 u8 dci_dct[24]; 5462}; 5463 5464struct mlx5_ifc_modify_hca_vport_context_in_bits { 5465 u8 opcode[0x10]; 5466 u8 reserved_0[0x10]; 5467 5468 u8 reserved_1[0x10]; 5469 u8 op_mod[0x10]; 5470 5471 u8 other_vport[0x1]; 5472 u8 reserved_2[0xb]; 5473 u8 port_num[0x4]; 5474 u8 vport_number[0x10]; 5475 5476 u8 reserved_3[0x20]; 5477 5478 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5479}; 5480 5481struct mlx5_ifc_modify_flow_table_out_bits { 5482 u8 status[0x8]; 5483 u8 reserved_at_8[0x18]; 5484 5485 u8 syndrome[0x20]; 5486 5487 u8 reserved_at_40[0x40]; 5488}; 5489 5490enum { 5491 MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1, 5492 MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000, 5493}; 5494 5495struct mlx5_ifc_modify_flow_table_in_bits { 5496 u8 opcode[0x10]; 5497 u8 reserved_at_10[0x10]; 5498 5499 u8 reserved_at_20[0x10]; 5500 u8 op_mod[0x10]; 5501 5502 u8 other_vport[0x1]; 5503 u8 reserved_at_41[0xf]; 5504 u8 vport_number[0x10]; 5505 5506 u8 reserved_at_60[0x10]; 5507 u8 modify_field_select[0x10]; 5508 5509 u8 table_type[0x8]; 5510 u8 reserved_at_88[0x18]; 5511 5512 u8 reserved_at_a0[0x8]; 5513 u8 table_id[0x18]; 5514 5515 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5516}; 5517 5518struct mlx5_ifc_modify_esw_vport_context_out_bits { 5519 u8 status[0x8]; 5520 u8 reserved_0[0x18]; 5521 5522 u8 syndrome[0x20]; 5523 5524 u8 reserved_1[0x40]; 5525}; 5526 5527struct mlx5_ifc_esw_vport_context_fields_select_bits { 5528 u8 reserved[0x1c]; 5529 u8 vport_cvlan_insert[0x1]; 5530 u8 vport_svlan_insert[0x1]; 5531 u8 vport_cvlan_strip[0x1]; 5532 u8 vport_svlan_strip[0x1]; 5533}; 5534 5535struct mlx5_ifc_modify_esw_vport_context_in_bits { 5536 u8 opcode[0x10]; 5537 u8 reserved_0[0x10]; 5538 5539 u8 reserved_1[0x10]; 5540 u8 op_mod[0x10]; 5541 5542 u8 other_vport[0x1]; 5543 u8 reserved_2[0xf]; 5544 u8 vport_number[0x10]; 5545 5546 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5547 5548 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5549}; 5550 5551struct mlx5_ifc_modify_cq_out_bits { 5552 u8 status[0x8]; 5553 u8 reserved_0[0x18]; 5554 5555 u8 syndrome[0x20]; 5556 5557 u8 reserved_1[0x40]; 5558}; 5559 5560enum { 5561 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5562 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5563}; 5564 5565struct mlx5_ifc_modify_cq_in_bits { 5566 u8 opcode[0x10]; 5567 u8 reserved_0[0x10]; 5568 5569 u8 reserved_1[0x10]; 5570 u8 op_mod[0x10]; 5571 5572 u8 reserved_2[0x8]; 5573 u8 cqn[0x18]; 5574 5575 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5576 5577 struct mlx5_ifc_cqc_bits cq_context; 5578 5579 u8 reserved_3[0x600]; 5580 5581 u8 pas[0][0x40]; 5582}; 5583 5584struct mlx5_ifc_modify_cong_status_out_bits { 5585 u8 status[0x8]; 5586 u8 reserved_0[0x18]; 5587 5588 u8 syndrome[0x20]; 5589 5590 u8 reserved_1[0x40]; 5591}; 5592 5593struct mlx5_ifc_modify_cong_status_in_bits { 5594 u8 opcode[0x10]; 5595 u8 reserved_0[0x10]; 5596 5597 u8 reserved_1[0x10]; 5598 u8 op_mod[0x10]; 5599 5600 u8 reserved_2[0x18]; 5601 u8 priority[0x4]; 5602 u8 cong_protocol[0x4]; 5603 5604 u8 enable[0x1]; 5605 u8 tag_enable[0x1]; 5606 u8 reserved_3[0x1e]; 5607}; 5608 5609struct mlx5_ifc_modify_cong_params_out_bits { 5610 u8 status[0x8]; 5611 u8 reserved_0[0x18]; 5612 5613 u8 syndrome[0x20]; 5614 5615 u8 reserved_1[0x40]; 5616}; 5617 5618struct mlx5_ifc_modify_cong_params_in_bits { 5619 u8 opcode[0x10]; 5620 u8 reserved_0[0x10]; 5621 5622 u8 reserved_1[0x10]; 5623 u8 op_mod[0x10]; 5624 5625 u8 reserved_2[0x1c]; 5626 u8 cong_protocol[0x4]; 5627 5628 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5629 5630 u8 reserved_3[0x80]; 5631 5632 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5633}; 5634 5635struct mlx5_ifc_manage_pages_out_bits { 5636 u8 status[0x8]; 5637 u8 reserved_0[0x18]; 5638 5639 u8 syndrome[0x20]; 5640 5641 u8 output_num_entries[0x20]; 5642 5643 u8 reserved_1[0x20]; 5644 5645 u8 pas[0][0x40]; 5646}; 5647 5648enum { 5649 MLX5_PAGES_CANT_GIVE = 0x0, 5650 MLX5_PAGES_GIVE = 0x1, 5651 MLX5_PAGES_TAKE = 0x2, 5652}; 5653 5654struct mlx5_ifc_manage_pages_in_bits { 5655 u8 opcode[0x10]; 5656 u8 reserved_0[0x10]; 5657 5658 u8 reserved_1[0x10]; 5659 u8 op_mod[0x10]; 5660 5661 u8 reserved_2[0x10]; 5662 u8 function_id[0x10]; 5663 5664 u8 input_num_entries[0x20]; 5665 5666 u8 pas[0][0x40]; 5667}; 5668 5669struct mlx5_ifc_mad_ifc_out_bits { 5670 u8 status[0x8]; 5671 u8 reserved_0[0x18]; 5672 5673 u8 syndrome[0x20]; 5674 5675 u8 reserved_1[0x40]; 5676 5677 u8 response_mad_packet[256][0x8]; 5678}; 5679 5680struct mlx5_ifc_mad_ifc_in_bits { 5681 u8 opcode[0x10]; 5682 u8 reserved_0[0x10]; 5683 5684 u8 reserved_1[0x10]; 5685 u8 op_mod[0x10]; 5686 5687 u8 remote_lid[0x10]; 5688 u8 reserved_2[0x8]; 5689 u8 port[0x8]; 5690 5691 u8 reserved_3[0x20]; 5692 5693 u8 mad[256][0x8]; 5694}; 5695 5696struct mlx5_ifc_init_hca_out_bits { 5697 u8 status[0x8]; 5698 u8 reserved_0[0x18]; 5699 5700 u8 syndrome[0x20]; 5701 5702 u8 reserved_1[0x40]; 5703}; 5704 5705enum { 5706 MLX5_INIT_HCA_IN_OP_MOD_INIT = 0x0, 5707 MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT = 0x1, 5708}; 5709 5710struct mlx5_ifc_init_hca_in_bits { 5711 u8 opcode[0x10]; 5712 u8 reserved_0[0x10]; 5713 5714 u8 reserved_1[0x10]; 5715 u8 op_mod[0x10]; 5716 5717 u8 reserved_2[0x40]; 5718}; 5719 5720struct mlx5_ifc_init2rtr_qp_out_bits { 5721 u8 status[0x8]; 5722 u8 reserved_0[0x18]; 5723 5724 u8 syndrome[0x20]; 5725 5726 u8 reserved_1[0x40]; 5727}; 5728 5729struct mlx5_ifc_init2rtr_qp_in_bits { 5730 u8 opcode[0x10]; 5731 u8 reserved_0[0x10]; 5732 5733 u8 reserved_1[0x10]; 5734 u8 op_mod[0x10]; 5735 5736 u8 reserved_2[0x8]; 5737 u8 qpn[0x18]; 5738 5739 u8 reserved_3[0x20]; 5740 5741 u8 opt_param_mask[0x20]; 5742 5743 u8 reserved_4[0x20]; 5744 5745 struct mlx5_ifc_qpc_bits qpc; 5746 5747 u8 reserved_5[0x80]; 5748}; 5749 5750struct mlx5_ifc_init2init_qp_out_bits { 5751 u8 status[0x8]; 5752 u8 reserved_0[0x18]; 5753 5754 u8 syndrome[0x20]; 5755 5756 u8 reserved_1[0x40]; 5757}; 5758 5759struct mlx5_ifc_init2init_qp_in_bits { 5760 u8 opcode[0x10]; 5761 u8 reserved_0[0x10]; 5762 5763 u8 reserved_1[0x10]; 5764 u8 op_mod[0x10]; 5765 5766 u8 reserved_2[0x8]; 5767 u8 qpn[0x18]; 5768 5769 u8 reserved_3[0x20]; 5770 5771 u8 opt_param_mask[0x20]; 5772 5773 u8 reserved_4[0x20]; 5774 5775 struct mlx5_ifc_qpc_bits qpc; 5776 5777 u8 reserved_5[0x80]; 5778}; 5779 5780struct mlx5_ifc_get_dropped_packet_log_out_bits { 5781 u8 status[0x8]; 5782 u8 reserved_0[0x18]; 5783 5784 u8 syndrome[0x20]; 5785 5786 u8 reserved_1[0x40]; 5787 5788 u8 packet_headers_log[128][0x8]; 5789 5790 u8 packet_syndrome[64][0x8]; 5791}; 5792 5793struct mlx5_ifc_get_dropped_packet_log_in_bits { 5794 u8 opcode[0x10]; 5795 u8 reserved_0[0x10]; 5796 5797 u8 reserved_1[0x10]; 5798 u8 op_mod[0x10]; 5799 5800 u8 reserved_2[0x40]; 5801}; 5802 5803struct mlx5_ifc_gen_eqe_in_bits { 5804 u8 opcode[0x10]; 5805 u8 reserved_0[0x10]; 5806 5807 u8 reserved_1[0x10]; 5808 u8 op_mod[0x10]; 5809 5810 u8 reserved_2[0x18]; 5811 u8 eq_number[0x8]; 5812 5813 u8 reserved_3[0x20]; 5814 5815 u8 eqe[64][0x8]; 5816}; 5817 5818struct mlx5_ifc_gen_eq_out_bits { 5819 u8 status[0x8]; 5820 u8 reserved_0[0x18]; 5821 5822 u8 syndrome[0x20]; 5823 5824 u8 reserved_1[0x40]; 5825}; 5826 5827struct mlx5_ifc_enable_hca_out_bits { 5828 u8 status[0x8]; 5829 u8 reserved_0[0x18]; 5830 5831 u8 syndrome[0x20]; 5832 5833 u8 reserved_1[0x20]; 5834}; 5835 5836struct mlx5_ifc_enable_hca_in_bits { 5837 u8 opcode[0x10]; 5838 u8 reserved_0[0x10]; 5839 5840 u8 reserved_1[0x10]; 5841 u8 op_mod[0x10]; 5842 5843 u8 reserved_2[0x10]; 5844 u8 function_id[0x10]; 5845 5846 u8 reserved_3[0x20]; 5847}; 5848 5849struct mlx5_ifc_drain_dct_out_bits { 5850 u8 status[0x8]; 5851 u8 reserved_0[0x18]; 5852 5853 u8 syndrome[0x20]; 5854 5855 u8 reserved_1[0x40]; 5856}; 5857 5858struct mlx5_ifc_drain_dct_in_bits { 5859 u8 opcode[0x10]; 5860 u8 reserved_0[0x10]; 5861 5862 u8 reserved_1[0x10]; 5863 u8 op_mod[0x10]; 5864 5865 u8 reserved_2[0x8]; 5866 u8 dctn[0x18]; 5867 5868 u8 reserved_3[0x20]; 5869}; 5870 5871struct mlx5_ifc_disable_hca_out_bits { 5872 u8 status[0x8]; 5873 u8 reserved_0[0x18]; 5874 5875 u8 syndrome[0x20]; 5876 5877 u8 reserved_1[0x20]; 5878}; 5879 5880struct mlx5_ifc_disable_hca_in_bits { 5881 u8 opcode[0x10]; 5882 u8 reserved_0[0x10]; 5883 5884 u8 reserved_1[0x10]; 5885 u8 op_mod[0x10]; 5886 5887 u8 reserved_2[0x10]; 5888 u8 function_id[0x10]; 5889 5890 u8 reserved_3[0x20]; 5891}; 5892 5893struct mlx5_ifc_detach_from_mcg_out_bits { 5894 u8 status[0x8]; 5895 u8 reserved_0[0x18]; 5896 5897 u8 syndrome[0x20]; 5898 5899 u8 reserved_1[0x40]; 5900}; 5901 5902struct mlx5_ifc_detach_from_mcg_in_bits { 5903 u8 opcode[0x10]; 5904 u8 reserved_0[0x10]; 5905 5906 u8 reserved_1[0x10]; 5907 u8 op_mod[0x10]; 5908 5909 u8 reserved_2[0x8]; 5910 u8 qpn[0x18]; 5911 5912 u8 reserved_3[0x20]; 5913 5914 u8 multicast_gid[16][0x8]; 5915}; 5916 5917struct mlx5_ifc_destroy_xrc_srq_out_bits { 5918 u8 status[0x8]; 5919 u8 reserved_0[0x18]; 5920 5921 u8 syndrome[0x20]; 5922 5923 u8 reserved_1[0x40]; 5924}; 5925 5926struct mlx5_ifc_destroy_xrc_srq_in_bits { 5927 u8 opcode[0x10]; 5928 u8 reserved_0[0x10]; 5929 5930 u8 reserved_1[0x10]; 5931 u8 op_mod[0x10]; 5932 5933 u8 reserved_2[0x8]; 5934 u8 xrc_srqn[0x18]; 5935 5936 u8 reserved_3[0x20]; 5937}; 5938 5939struct mlx5_ifc_destroy_tis_out_bits { 5940 u8 status[0x8]; 5941 u8 reserved_0[0x18]; 5942 5943 u8 syndrome[0x20]; 5944 5945 u8 reserved_1[0x40]; 5946}; 5947 5948struct mlx5_ifc_destroy_tis_in_bits { 5949 u8 opcode[0x10]; 5950 u8 reserved_0[0x10]; 5951 5952 u8 reserved_1[0x10]; 5953 u8 op_mod[0x10]; 5954 5955 u8 reserved_2[0x8]; 5956 u8 tisn[0x18]; 5957 5958 u8 reserved_3[0x20]; 5959}; 5960 5961struct mlx5_ifc_destroy_tir_out_bits { 5962 u8 status[0x8]; 5963 u8 reserved_0[0x18]; 5964 5965 u8 syndrome[0x20]; 5966 5967 u8 reserved_1[0x40]; 5968}; 5969 5970struct mlx5_ifc_destroy_tir_in_bits { 5971 u8 opcode[0x10]; 5972 u8 reserved_0[0x10]; 5973 5974 u8 reserved_1[0x10]; 5975 u8 op_mod[0x10]; 5976 5977 u8 reserved_2[0x8]; 5978 u8 tirn[0x18]; 5979 5980 u8 reserved_3[0x20]; 5981}; 5982 5983struct mlx5_ifc_destroy_srq_out_bits { 5984 u8 status[0x8]; 5985 u8 reserved_0[0x18]; 5986 5987 u8 syndrome[0x20]; 5988 5989 u8 reserved_1[0x40]; 5990}; 5991 5992struct mlx5_ifc_destroy_srq_in_bits { 5993 u8 opcode[0x10]; 5994 u8 reserved_0[0x10]; 5995 5996 u8 reserved_1[0x10]; 5997 u8 op_mod[0x10]; 5998 5999 u8 reserved_2[0x8]; 6000 u8 srqn[0x18]; 6001 6002 u8 reserved_3[0x20]; 6003}; 6004 6005struct mlx5_ifc_destroy_sq_out_bits { 6006 u8 status[0x8]; 6007 u8 reserved_0[0x18]; 6008 6009 u8 syndrome[0x20]; 6010 6011 u8 reserved_1[0x40]; 6012}; 6013 6014struct mlx5_ifc_destroy_sq_in_bits { 6015 u8 opcode[0x10]; 6016 u8 reserved_0[0x10]; 6017 6018 u8 reserved_1[0x10]; 6019 u8 op_mod[0x10]; 6020 6021 u8 reserved_2[0x8]; 6022 u8 sqn[0x18]; 6023 6024 u8 reserved_3[0x20]; 6025}; 6026 6027struct mlx5_ifc_destroy_scheduling_element_out_bits { 6028 u8 status[0x8]; 6029 u8 reserved_at_8[0x18]; 6030 6031 u8 syndrome[0x20]; 6032 6033 u8 reserved_at_40[0x1c0]; 6034}; 6035 6036enum { 6037 MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 6038}; 6039 6040struct mlx5_ifc_destroy_scheduling_element_in_bits { 6041 u8 opcode[0x10]; 6042 u8 reserved_at_10[0x10]; 6043 6044 u8 reserved_at_20[0x10]; 6045 u8 op_mod[0x10]; 6046 6047 u8 scheduling_hierarchy[0x8]; 6048 u8 reserved_at_48[0x18]; 6049 6050 u8 scheduling_element_id[0x20]; 6051 6052 u8 reserved_at_80[0x180]; 6053}; 6054 6055struct mlx5_ifc_destroy_rqt_out_bits { 6056 u8 status[0x8]; 6057 u8 reserved_0[0x18]; 6058 6059 u8 syndrome[0x20]; 6060 6061 u8 reserved_1[0x40]; 6062}; 6063 6064struct mlx5_ifc_destroy_rqt_in_bits { 6065 u8 opcode[0x10]; 6066 u8 reserved_0[0x10]; 6067 6068 u8 reserved_1[0x10]; 6069 u8 op_mod[0x10]; 6070 6071 u8 reserved_2[0x8]; 6072 u8 rqtn[0x18]; 6073 6074 u8 reserved_3[0x20]; 6075}; 6076 6077struct mlx5_ifc_destroy_rq_out_bits { 6078 u8 status[0x8]; 6079 u8 reserved_0[0x18]; 6080 6081 u8 syndrome[0x20]; 6082 6083 u8 reserved_1[0x40]; 6084}; 6085 6086struct mlx5_ifc_destroy_rq_in_bits { 6087 u8 opcode[0x10]; 6088 u8 reserved_0[0x10]; 6089 6090 u8 reserved_1[0x10]; 6091 u8 op_mod[0x10]; 6092 6093 u8 reserved_2[0x8]; 6094 u8 rqn[0x18]; 6095 6096 u8 reserved_3[0x20]; 6097}; 6098 6099struct mlx5_ifc_destroy_rmp_out_bits { 6100 u8 status[0x8]; 6101 u8 reserved_0[0x18]; 6102 6103 u8 syndrome[0x20]; 6104 6105 u8 reserved_1[0x40]; 6106}; 6107 6108struct mlx5_ifc_destroy_rmp_in_bits { 6109 u8 opcode[0x10]; 6110 u8 reserved_0[0x10]; 6111 6112 u8 reserved_1[0x10]; 6113 u8 op_mod[0x10]; 6114 6115 u8 reserved_2[0x8]; 6116 u8 rmpn[0x18]; 6117 6118 u8 reserved_3[0x20]; 6119}; 6120 6121struct mlx5_ifc_destroy_qp_out_bits { 6122 u8 status[0x8]; 6123 u8 reserved_0[0x18]; 6124 6125 u8 syndrome[0x20]; 6126 6127 u8 reserved_1[0x40]; 6128}; 6129 6130struct mlx5_ifc_destroy_qp_in_bits { 6131 u8 opcode[0x10]; 6132 u8 reserved_0[0x10]; 6133 6134 u8 reserved_1[0x10]; 6135 u8 op_mod[0x10]; 6136 6137 u8 reserved_2[0x8]; 6138 u8 qpn[0x18]; 6139 6140 u8 reserved_3[0x20]; 6141}; 6142 6143struct mlx5_ifc_destroy_qos_para_vport_out_bits { 6144 u8 status[0x8]; 6145 u8 reserved_at_8[0x18]; 6146 6147 u8 syndrome[0x20]; 6148 6149 u8 reserved_at_40[0x1c0]; 6150}; 6151 6152struct mlx5_ifc_destroy_qos_para_vport_in_bits { 6153 u8 opcode[0x10]; 6154 u8 reserved_at_10[0x10]; 6155 6156 u8 reserved_at_20[0x10]; 6157 u8 op_mod[0x10]; 6158 6159 u8 reserved_at_40[0x20]; 6160 6161 u8 reserved_at_60[0x10]; 6162 u8 qos_para_vport_number[0x10]; 6163 6164 u8 reserved_at_80[0x180]; 6165}; 6166 6167struct mlx5_ifc_destroy_psv_out_bits { 6168 u8 status[0x8]; 6169 u8 reserved_0[0x18]; 6170 6171 u8 syndrome[0x20]; 6172 6173 u8 reserved_1[0x40]; 6174}; 6175 6176struct mlx5_ifc_destroy_psv_in_bits { 6177 u8 opcode[0x10]; 6178 u8 reserved_0[0x10]; 6179 6180 u8 reserved_1[0x10]; 6181 u8 op_mod[0x10]; 6182 6183 u8 reserved_2[0x8]; 6184 u8 psvn[0x18]; 6185 6186 u8 reserved_3[0x20]; 6187}; 6188 6189struct mlx5_ifc_destroy_mkey_out_bits { 6190 u8 status[0x8]; 6191 u8 reserved_0[0x18]; 6192 6193 u8 syndrome[0x20]; 6194 6195 u8 reserved_1[0x40]; 6196}; 6197 6198struct mlx5_ifc_destroy_mkey_in_bits { 6199 u8 opcode[0x10]; 6200 u8 reserved_0[0x10]; 6201 6202 u8 reserved_1[0x10]; 6203 u8 op_mod[0x10]; 6204 6205 u8 reserved_2[0x8]; 6206 u8 mkey_index[0x18]; 6207 6208 u8 reserved_3[0x20]; 6209}; 6210 6211struct mlx5_ifc_destroy_flow_table_out_bits { 6212 u8 status[0x8]; 6213 u8 reserved_0[0x18]; 6214 6215 u8 syndrome[0x20]; 6216 6217 u8 reserved_1[0x40]; 6218}; 6219 6220struct mlx5_ifc_destroy_flow_table_in_bits { 6221 u8 opcode[0x10]; 6222 u8 reserved_0[0x10]; 6223 6224 u8 reserved_1[0x10]; 6225 u8 op_mod[0x10]; 6226 6227 u8 other_vport[0x1]; 6228 u8 reserved_2[0xf]; 6229 u8 vport_number[0x10]; 6230 6231 u8 reserved_3[0x20]; 6232 6233 u8 table_type[0x8]; 6234 u8 reserved_4[0x18]; 6235 6236 u8 reserved_5[0x8]; 6237 u8 table_id[0x18]; 6238 6239 u8 reserved_6[0x140]; 6240}; 6241 6242struct mlx5_ifc_destroy_flow_group_out_bits { 6243 u8 status[0x8]; 6244 u8 reserved_0[0x18]; 6245 6246 u8 syndrome[0x20]; 6247 6248 u8 reserved_1[0x40]; 6249}; 6250 6251struct mlx5_ifc_destroy_flow_group_in_bits { 6252 u8 opcode[0x10]; 6253 u8 reserved_0[0x10]; 6254 6255 u8 reserved_1[0x10]; 6256 u8 op_mod[0x10]; 6257 6258 u8 other_vport[0x1]; 6259 u8 reserved_2[0xf]; 6260 u8 vport_number[0x10]; 6261 6262 u8 reserved_3[0x20]; 6263 6264 u8 table_type[0x8]; 6265 u8 reserved_4[0x18]; 6266 6267 u8 reserved_5[0x8]; 6268 u8 table_id[0x18]; 6269 6270 u8 group_id[0x20]; 6271 6272 u8 reserved_6[0x120]; 6273}; 6274 6275struct mlx5_ifc_destroy_eq_out_bits { 6276 u8 status[0x8]; 6277 u8 reserved_0[0x18]; 6278 6279 u8 syndrome[0x20]; 6280 6281 u8 reserved_1[0x40]; 6282}; 6283 6284struct mlx5_ifc_destroy_eq_in_bits { 6285 u8 opcode[0x10]; 6286 u8 reserved_0[0x10]; 6287 6288 u8 reserved_1[0x10]; 6289 u8 op_mod[0x10]; 6290 6291 u8 reserved_2[0x18]; 6292 u8 eq_number[0x8]; 6293 6294 u8 reserved_3[0x20]; 6295}; 6296 6297struct mlx5_ifc_destroy_dct_out_bits { 6298 u8 status[0x8]; 6299 u8 reserved_0[0x18]; 6300 6301 u8 syndrome[0x20]; 6302 6303 u8 reserved_1[0x40]; 6304}; 6305 6306struct mlx5_ifc_destroy_dct_in_bits { 6307 u8 opcode[0x10]; 6308 u8 reserved_0[0x10]; 6309 6310 u8 reserved_1[0x10]; 6311 u8 op_mod[0x10]; 6312 6313 u8 reserved_2[0x8]; 6314 u8 dctn[0x18]; 6315 6316 u8 reserved_3[0x20]; 6317}; 6318 6319struct mlx5_ifc_destroy_cq_out_bits { 6320 u8 status[0x8]; 6321 u8 reserved_0[0x18]; 6322 6323 u8 syndrome[0x20]; 6324 6325 u8 reserved_1[0x40]; 6326}; 6327 6328struct mlx5_ifc_destroy_cq_in_bits { 6329 u8 opcode[0x10]; 6330 u8 reserved_0[0x10]; 6331 6332 u8 reserved_1[0x10]; 6333 u8 op_mod[0x10]; 6334 6335 u8 reserved_2[0x8]; 6336 u8 cqn[0x18]; 6337 6338 u8 reserved_3[0x20]; 6339}; 6340 6341struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6342 u8 status[0x8]; 6343 u8 reserved_0[0x18]; 6344 6345 u8 syndrome[0x20]; 6346 6347 u8 reserved_1[0x40]; 6348}; 6349 6350struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6351 u8 opcode[0x10]; 6352 u8 reserved_0[0x10]; 6353 6354 u8 reserved_1[0x10]; 6355 u8 op_mod[0x10]; 6356 6357 u8 reserved_2[0x20]; 6358 6359 u8 reserved_3[0x10]; 6360 u8 vxlan_udp_port[0x10]; 6361}; 6362 6363struct mlx5_ifc_delete_l2_table_entry_out_bits { 6364 u8 status[0x8]; 6365 u8 reserved_0[0x18]; 6366 6367 u8 syndrome[0x20]; 6368 6369 u8 reserved_1[0x40]; 6370}; 6371 6372struct mlx5_ifc_delete_l2_table_entry_in_bits { 6373 u8 opcode[0x10]; 6374 u8 reserved_0[0x10]; 6375 6376 u8 reserved_1[0x10]; 6377 u8 op_mod[0x10]; 6378 6379 u8 reserved_2[0x60]; 6380 6381 u8 reserved_3[0x8]; 6382 u8 table_index[0x18]; 6383 6384 u8 reserved_4[0x140]; 6385}; 6386 6387struct mlx5_ifc_delete_fte_out_bits { 6388 u8 status[0x8]; 6389 u8 reserved_0[0x18]; 6390 6391 u8 syndrome[0x20]; 6392 6393 u8 reserved_1[0x40]; 6394}; 6395 6396struct mlx5_ifc_delete_fte_in_bits { 6397 u8 opcode[0x10]; 6398 u8 reserved_0[0x10]; 6399 6400 u8 reserved_1[0x10]; 6401 u8 op_mod[0x10]; 6402 6403 u8 other_vport[0x1]; 6404 u8 reserved_2[0xf]; 6405 u8 vport_number[0x10]; 6406 6407 u8 reserved_3[0x20]; 6408 6409 u8 table_type[0x8]; 6410 u8 reserved_4[0x18]; 6411 6412 u8 reserved_5[0x8]; 6413 u8 table_id[0x18]; 6414 6415 u8 reserved_6[0x40]; 6416 6417 u8 flow_index[0x20]; 6418 6419 u8 reserved_7[0xe0]; 6420}; 6421 6422struct mlx5_ifc_dealloc_xrcd_out_bits { 6423 u8 status[0x8]; 6424 u8 reserved_0[0x18]; 6425 6426 u8 syndrome[0x20]; 6427 6428 u8 reserved_1[0x40]; 6429}; 6430 6431struct mlx5_ifc_dealloc_xrcd_in_bits { 6432 u8 opcode[0x10]; 6433 u8 reserved_0[0x10]; 6434 6435 u8 reserved_1[0x10]; 6436 u8 op_mod[0x10]; 6437 6438 u8 reserved_2[0x8]; 6439 u8 xrcd[0x18]; 6440 6441 u8 reserved_3[0x20]; 6442}; 6443 6444struct mlx5_ifc_dealloc_uar_out_bits { 6445 u8 status[0x8]; 6446 u8 reserved_0[0x18]; 6447 6448 u8 syndrome[0x20]; 6449 6450 u8 reserved_1[0x40]; 6451}; 6452 6453struct mlx5_ifc_dealloc_uar_in_bits { 6454 u8 opcode[0x10]; 6455 u8 reserved_0[0x10]; 6456 6457 u8 reserved_1[0x10]; 6458 u8 op_mod[0x10]; 6459 6460 u8 reserved_2[0x8]; 6461 u8 uar[0x18]; 6462 6463 u8 reserved_3[0x20]; 6464}; 6465 6466struct mlx5_ifc_dealloc_transport_domain_out_bits { 6467 u8 status[0x8]; 6468 u8 reserved_0[0x18]; 6469 6470 u8 syndrome[0x20]; 6471 6472 u8 reserved_1[0x40]; 6473}; 6474 6475struct mlx5_ifc_dealloc_transport_domain_in_bits { 6476 u8 opcode[0x10]; 6477 u8 reserved_0[0x10]; 6478 6479 u8 reserved_1[0x10]; 6480 u8 op_mod[0x10]; 6481 6482 u8 reserved_2[0x8]; 6483 u8 transport_domain[0x18]; 6484 6485 u8 reserved_3[0x20]; 6486}; 6487 6488struct mlx5_ifc_dealloc_q_counter_out_bits { 6489 u8 status[0x8]; 6490 u8 reserved_0[0x18]; 6491 6492 u8 syndrome[0x20]; 6493 6494 u8 reserved_1[0x40]; 6495}; 6496 6497struct mlx5_ifc_counter_id_bits { 6498 u8 reserved[0x10]; 6499 u8 counter_id[0x10]; 6500}; 6501 6502struct mlx5_ifc_diagnostic_params_context_bits { 6503 u8 num_of_counters[0x10]; 6504 u8 reserved_2[0x8]; 6505 u8 log_num_of_samples[0x8]; 6506 6507 u8 single[0x1]; 6508 u8 repetitive[0x1]; 6509 u8 sync[0x1]; 6510 u8 clear[0x1]; 6511 u8 on_demand[0x1]; 6512 u8 enable[0x1]; 6513 u8 reserved_3[0x12]; 6514 u8 log_sample_period[0x8]; 6515 6516 u8 reserved_4[0x80]; 6517 6518 struct mlx5_ifc_counter_id_bits counter_id[0]; 6519}; 6520 6521struct mlx5_ifc_set_diagnostic_params_in_bits { 6522 u8 opcode[0x10]; 6523 u8 reserved_0[0x10]; 6524 6525 u8 reserved_1[0x10]; 6526 u8 op_mod[0x10]; 6527 6528 struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx; 6529}; 6530 6531struct mlx5_ifc_set_diagnostic_params_out_bits { 6532 u8 status[0x8]; 6533 u8 reserved_0[0x18]; 6534 6535 u8 syndrome[0x20]; 6536 6537 u8 reserved_1[0x40]; 6538}; 6539 6540struct mlx5_ifc_query_diagnostic_counters_in_bits { 6541 u8 opcode[0x10]; 6542 u8 reserved_0[0x10]; 6543 6544 u8 reserved_1[0x10]; 6545 u8 op_mod[0x10]; 6546 6547 u8 num_of_samples[0x10]; 6548 u8 sample_index[0x10]; 6549 6550 u8 reserved_2[0x20]; 6551}; 6552 6553struct mlx5_ifc_diagnostic_counter_bits { 6554 u8 counter_id[0x10]; 6555 u8 sample_id[0x10]; 6556 6557 u8 time_stamp_31_0[0x20]; 6558 6559 u8 counter_value_h[0x20]; 6560 6561 u8 counter_value_l[0x20]; 6562}; 6563 6564struct mlx5_ifc_query_diagnostic_counters_out_bits { 6565 u8 status[0x8]; 6566 u8 reserved_0[0x18]; 6567 6568 u8 syndrome[0x20]; 6569 6570 u8 reserved_1[0x40]; 6571 6572 struct mlx5_ifc_diagnostic_counter_bits diag_counter[0]; 6573}; 6574 6575struct mlx5_ifc_dealloc_q_counter_in_bits { 6576 u8 opcode[0x10]; 6577 u8 reserved_0[0x10]; 6578 6579 u8 reserved_1[0x10]; 6580 u8 op_mod[0x10]; 6581 6582 u8 reserved_2[0x18]; 6583 u8 counter_set_id[0x8]; 6584 6585 u8 reserved_3[0x20]; 6586}; 6587 6588struct mlx5_ifc_dealloc_pd_out_bits { 6589 u8 status[0x8]; 6590 u8 reserved_0[0x18]; 6591 6592 u8 syndrome[0x20]; 6593 6594 u8 reserved_1[0x40]; 6595}; 6596 6597struct mlx5_ifc_dealloc_pd_in_bits { 6598 u8 opcode[0x10]; 6599 u8 reserved_0[0x10]; 6600 6601 u8 reserved_1[0x10]; 6602 u8 op_mod[0x10]; 6603 6604 u8 reserved_2[0x8]; 6605 u8 pd[0x18]; 6606 6607 u8 reserved_3[0x20]; 6608}; 6609 6610struct mlx5_ifc_dealloc_flow_counter_out_bits { 6611 u8 status[0x8]; 6612 u8 reserved_0[0x18]; 6613 6614 u8 syndrome[0x20]; 6615 6616 u8 reserved_1[0x40]; 6617}; 6618 6619struct mlx5_ifc_dealloc_flow_counter_in_bits { 6620 u8 opcode[0x10]; 6621 u8 reserved_0[0x10]; 6622 6623 u8 reserved_1[0x10]; 6624 u8 op_mod[0x10]; 6625 6626 u8 reserved_2[0x10]; 6627 u8 flow_counter_id[0x10]; 6628 6629 u8 reserved_3[0x20]; 6630}; 6631 6632struct mlx5_ifc_deactivate_tracer_out_bits { 6633 u8 status[0x8]; 6634 u8 reserved_0[0x18]; 6635 6636 u8 syndrome[0x20]; 6637 6638 u8 reserved_1[0x40]; 6639}; 6640 6641struct mlx5_ifc_deactivate_tracer_in_bits { 6642 u8 opcode[0x10]; 6643 u8 reserved_0[0x10]; 6644 6645 u8 reserved_1[0x10]; 6646 u8 op_mod[0x10]; 6647 6648 u8 mkey[0x20]; 6649 6650 u8 reserved_2[0x20]; 6651}; 6652 6653struct mlx5_ifc_create_xrc_srq_out_bits { 6654 u8 status[0x8]; 6655 u8 reserved_0[0x18]; 6656 6657 u8 syndrome[0x20]; 6658 6659 u8 reserved_1[0x8]; 6660 u8 xrc_srqn[0x18]; 6661 6662 u8 reserved_2[0x20]; 6663}; 6664 6665struct mlx5_ifc_create_xrc_srq_in_bits { 6666 u8 opcode[0x10]; 6667 u8 reserved_0[0x10]; 6668 6669 u8 reserved_1[0x10]; 6670 u8 op_mod[0x10]; 6671 6672 u8 reserved_2[0x40]; 6673 6674 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6675 6676 u8 reserved_3[0x600]; 6677 6678 u8 pas[0][0x40]; 6679}; 6680 6681struct mlx5_ifc_create_tis_out_bits { 6682 u8 status[0x8]; 6683 u8 reserved_0[0x18]; 6684 6685 u8 syndrome[0x20]; 6686 6687 u8 reserved_1[0x8]; 6688 u8 tisn[0x18]; 6689 6690 u8 reserved_2[0x20]; 6691}; 6692 6693struct mlx5_ifc_create_tis_in_bits { 6694 u8 opcode[0x10]; 6695 u8 reserved_0[0x10]; 6696 6697 u8 reserved_1[0x10]; 6698 u8 op_mod[0x10]; 6699 6700 u8 reserved_2[0xc0]; 6701 6702 struct mlx5_ifc_tisc_bits ctx; 6703}; 6704 6705struct mlx5_ifc_create_tir_out_bits { 6706 u8 status[0x8]; 6707 u8 reserved_0[0x18]; 6708 6709 u8 syndrome[0x20]; 6710 6711 u8 reserved_1[0x8]; 6712 u8 tirn[0x18]; 6713 6714 u8 reserved_2[0x20]; 6715}; 6716 6717struct mlx5_ifc_create_tir_in_bits { 6718 u8 opcode[0x10]; 6719 u8 reserved_0[0x10]; 6720 6721 u8 reserved_1[0x10]; 6722 u8 op_mod[0x10]; 6723 6724 u8 reserved_2[0xc0]; 6725 6726 struct mlx5_ifc_tirc_bits tir_context; 6727}; 6728 6729struct mlx5_ifc_create_srq_out_bits { 6730 u8 status[0x8]; 6731 u8 reserved_0[0x18]; 6732 6733 u8 syndrome[0x20]; 6734 6735 u8 reserved_1[0x8]; 6736 u8 srqn[0x18]; 6737 6738 u8 reserved_2[0x20]; 6739}; 6740 6741struct mlx5_ifc_create_srq_in_bits { 6742 u8 opcode[0x10]; 6743 u8 reserved_0[0x10]; 6744 6745 u8 reserved_1[0x10]; 6746 u8 op_mod[0x10]; 6747 6748 u8 reserved_2[0x40]; 6749 6750 struct mlx5_ifc_srqc_bits srq_context_entry; 6751 6752 u8 reserved_3[0x600]; 6753 6754 u8 pas[0][0x40]; 6755}; 6756 6757struct mlx5_ifc_create_sq_out_bits { 6758 u8 status[0x8]; 6759 u8 reserved_0[0x18]; 6760 6761 u8 syndrome[0x20]; 6762 6763 u8 reserved_1[0x8]; 6764 u8 sqn[0x18]; 6765 6766 u8 reserved_2[0x20]; 6767}; 6768 6769struct mlx5_ifc_create_sq_in_bits { 6770 u8 opcode[0x10]; 6771 u8 reserved_0[0x10]; 6772 6773 u8 reserved_1[0x10]; 6774 u8 op_mod[0x10]; 6775 6776 u8 reserved_2[0xc0]; 6777 6778 struct mlx5_ifc_sqc_bits ctx; 6779}; 6780 6781struct mlx5_ifc_create_scheduling_element_out_bits { 6782 u8 status[0x8]; 6783 u8 reserved_at_8[0x18]; 6784 6785 u8 syndrome[0x20]; 6786 6787 u8 reserved_at_40[0x40]; 6788 6789 u8 scheduling_element_id[0x20]; 6790 6791 u8 reserved_at_a0[0x160]; 6792}; 6793 6794enum { 6795 MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 6796}; 6797 6798struct mlx5_ifc_create_scheduling_element_in_bits { 6799 u8 opcode[0x10]; 6800 u8 reserved_at_10[0x10]; 6801 6802 u8 reserved_at_20[0x10]; 6803 u8 op_mod[0x10]; 6804 6805 u8 scheduling_hierarchy[0x8]; 6806 u8 reserved_at_48[0x18]; 6807 6808 u8 reserved_at_60[0xa0]; 6809 6810 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6811 6812 u8 reserved_at_300[0x100]; 6813}; 6814 6815struct mlx5_ifc_create_rqt_out_bits { 6816 u8 status[0x8]; 6817 u8 reserved_0[0x18]; 6818 6819 u8 syndrome[0x20]; 6820 6821 u8 reserved_1[0x8]; 6822 u8 rqtn[0x18]; 6823 6824 u8 reserved_2[0x20]; 6825}; 6826 6827struct mlx5_ifc_create_rqt_in_bits { 6828 u8 opcode[0x10]; 6829 u8 reserved_0[0x10]; 6830 6831 u8 reserved_1[0x10]; 6832 u8 op_mod[0x10]; 6833 6834 u8 reserved_2[0xc0]; 6835 6836 struct mlx5_ifc_rqtc_bits rqt_context; 6837}; 6838 6839struct mlx5_ifc_create_rq_out_bits { 6840 u8 status[0x8]; 6841 u8 reserved_0[0x18]; 6842 6843 u8 syndrome[0x20]; 6844 6845 u8 reserved_1[0x8]; 6846 u8 rqn[0x18]; 6847 6848 u8 reserved_2[0x20]; 6849}; 6850 6851struct mlx5_ifc_create_rq_in_bits { 6852 u8 opcode[0x10]; 6853 u8 reserved_0[0x10]; 6854 6855 u8 reserved_1[0x10]; 6856 u8 op_mod[0x10]; 6857 6858 u8 reserved_2[0xc0]; 6859 6860 struct mlx5_ifc_rqc_bits ctx; 6861}; 6862 6863struct mlx5_ifc_create_rmp_out_bits { 6864 u8 status[0x8]; 6865 u8 reserved_0[0x18]; 6866 6867 u8 syndrome[0x20]; 6868 6869 u8 reserved_1[0x8]; 6870 u8 rmpn[0x18]; 6871 6872 u8 reserved_2[0x20]; 6873}; 6874 6875struct mlx5_ifc_create_rmp_in_bits { 6876 u8 opcode[0x10]; 6877 u8 reserved_0[0x10]; 6878 6879 u8 reserved_1[0x10]; 6880 u8 op_mod[0x10]; 6881 6882 u8 reserved_2[0xc0]; 6883 6884 struct mlx5_ifc_rmpc_bits ctx; 6885}; 6886 6887struct mlx5_ifc_create_qp_out_bits { 6888 u8 status[0x8]; 6889 u8 reserved_0[0x18]; 6890 6891 u8 syndrome[0x20]; 6892 6893 u8 reserved_1[0x8]; 6894 u8 qpn[0x18]; 6895 6896 u8 reserved_2[0x20]; 6897}; 6898 6899struct mlx5_ifc_create_qp_in_bits { 6900 u8 opcode[0x10]; 6901 u8 reserved_0[0x10]; 6902 6903 u8 reserved_1[0x10]; 6904 u8 op_mod[0x10]; 6905 6906 u8 reserved_2[0x8]; 6907 u8 input_qpn[0x18]; 6908 6909 u8 reserved_3[0x20]; 6910 6911 u8 opt_param_mask[0x20]; 6912 6913 u8 reserved_4[0x20]; 6914 6915 struct mlx5_ifc_qpc_bits qpc; 6916 6917 u8 reserved_5[0x80]; 6918 6919 u8 pas[0][0x40]; 6920}; 6921 6922struct mlx5_ifc_create_qos_para_vport_out_bits { 6923 u8 status[0x8]; 6924 u8 reserved_at_8[0x18]; 6925 6926 u8 syndrome[0x20]; 6927 6928 u8 reserved_at_40[0x20]; 6929 6930 u8 reserved_at_60[0x10]; 6931 u8 qos_para_vport_number[0x10]; 6932 6933 u8 reserved_at_80[0x180]; 6934}; 6935 6936struct mlx5_ifc_create_qos_para_vport_in_bits { 6937 u8 opcode[0x10]; 6938 u8 reserved_at_10[0x10]; 6939 6940 u8 reserved_at_20[0x10]; 6941 u8 op_mod[0x10]; 6942 6943 u8 reserved_at_40[0x1c0]; 6944}; 6945 6946struct mlx5_ifc_create_psv_out_bits { 6947 u8 status[0x8]; 6948 u8 reserved_0[0x18]; 6949 6950 u8 syndrome[0x20]; 6951 6952 u8 reserved_1[0x40]; 6953 6954 u8 reserved_2[0x8]; 6955 u8 psv0_index[0x18]; 6956 6957 u8 reserved_3[0x8]; 6958 u8 psv1_index[0x18]; 6959 6960 u8 reserved_4[0x8]; 6961 u8 psv2_index[0x18]; 6962 6963 u8 reserved_5[0x8]; 6964 u8 psv3_index[0x18]; 6965}; 6966 6967struct mlx5_ifc_create_psv_in_bits { 6968 u8 opcode[0x10]; 6969 u8 reserved_0[0x10]; 6970 6971 u8 reserved_1[0x10]; 6972 u8 op_mod[0x10]; 6973 6974 u8 num_psv[0x4]; 6975 u8 reserved_2[0x4]; 6976 u8 pd[0x18]; 6977 6978 u8 reserved_3[0x20]; 6979}; 6980 6981struct mlx5_ifc_create_mkey_out_bits { 6982 u8 status[0x8]; 6983 u8 reserved_0[0x18]; 6984 6985 u8 syndrome[0x20]; 6986 6987 u8 reserved_1[0x8]; 6988 u8 mkey_index[0x18]; 6989 6990 u8 reserved_2[0x20]; 6991}; 6992 6993struct mlx5_ifc_create_mkey_in_bits { 6994 u8 opcode[0x10]; 6995 u8 reserved_0[0x10]; 6996 6997 u8 reserved_1[0x10]; 6998 u8 op_mod[0x10]; 6999 7000 u8 reserved_2[0x20]; 7001 7002 u8 pg_access[0x1]; 7003 u8 reserved_3[0x1f]; 7004 7005 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7006 7007 u8 reserved_4[0x80]; 7008 7009 u8 translations_octword_actual_size[0x20]; 7010 7011 u8 reserved_5[0x560]; 7012 7013 u8 klm_pas_mtt[0][0x20]; 7014}; 7015 7016struct mlx5_ifc_create_flow_table_out_bits { 7017 u8 status[0x8]; 7018 u8 reserved_0[0x18]; 7019 7020 u8 syndrome[0x20]; 7021 7022 u8 reserved_1[0x8]; 7023 u8 table_id[0x18]; 7024 7025 u8 reserved_2[0x20]; 7026}; 7027 7028struct mlx5_ifc_create_flow_table_in_bits { 7029 u8 opcode[0x10]; 7030 u8 reserved_at_10[0x10]; 7031 7032 u8 reserved_at_20[0x10]; 7033 u8 op_mod[0x10]; 7034 7035 u8 other_vport[0x1]; 7036 u8 reserved_at_41[0xf]; 7037 u8 vport_number[0x10]; 7038 7039 u8 reserved_at_60[0x20]; 7040 7041 u8 table_type[0x8]; 7042 u8 reserved_at_88[0x18]; 7043 7044 u8 reserved_at_a0[0x20]; 7045 7046 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7047}; 7048 7049struct mlx5_ifc_create_flow_group_out_bits { 7050 u8 status[0x8]; 7051 u8 reserved_0[0x18]; 7052 7053 u8 syndrome[0x20]; 7054 7055 u8 reserved_1[0x8]; 7056 u8 group_id[0x18]; 7057 7058 u8 reserved_2[0x20]; 7059}; 7060 7061enum { 7062 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7063 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7064 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7065}; 7066 7067struct mlx5_ifc_create_flow_group_in_bits { 7068 u8 opcode[0x10]; 7069 u8 reserved_0[0x10]; 7070 7071 u8 reserved_1[0x10]; 7072 u8 op_mod[0x10]; 7073 7074 u8 other_vport[0x1]; 7075 u8 reserved_2[0xf]; 7076 u8 vport_number[0x10]; 7077 7078 u8 reserved_3[0x20]; 7079 7080 u8 table_type[0x8]; 7081 u8 reserved_4[0x18]; 7082 7083 u8 reserved_5[0x8]; 7084 u8 table_id[0x18]; 7085 7086 u8 reserved_6[0x20]; 7087 7088 u8 start_flow_index[0x20]; 7089 7090 u8 reserved_7[0x20]; 7091 7092 u8 end_flow_index[0x20]; 7093 7094 u8 reserved_8[0xa0]; 7095 7096 u8 reserved_9[0x18]; 7097 u8 match_criteria_enable[0x8]; 7098 7099 struct mlx5_ifc_fte_match_param_bits match_criteria; 7100 7101 u8 reserved_10[0xe00]; 7102}; 7103 7104struct mlx5_ifc_create_eq_out_bits { 7105 u8 status[0x8]; 7106 u8 reserved_0[0x18]; 7107 7108 u8 syndrome[0x20]; 7109 7110 u8 reserved_1[0x18]; 7111 u8 eq_number[0x8]; 7112 7113 u8 reserved_2[0x20]; 7114}; 7115 7116struct mlx5_ifc_create_eq_in_bits { 7117 u8 opcode[0x10]; 7118 u8 reserved_0[0x10]; 7119 7120 u8 reserved_1[0x10]; 7121 u8 op_mod[0x10]; 7122 7123 u8 reserved_2[0x40]; 7124 7125 struct mlx5_ifc_eqc_bits eq_context_entry; 7126 7127 u8 reserved_3[0x40]; 7128 7129 u8 event_bitmask[0x40]; 7130 7131 u8 reserved_4[0x580]; 7132 7133 u8 pas[0][0x40]; 7134}; 7135 7136struct mlx5_ifc_create_dct_out_bits { 7137 u8 status[0x8]; 7138 u8 reserved_0[0x18]; 7139 7140 u8 syndrome[0x20]; 7141 7142 u8 reserved_1[0x8]; 7143 u8 dctn[0x18]; 7144 7145 u8 reserved_2[0x20]; 7146}; 7147 7148struct mlx5_ifc_create_dct_in_bits { 7149 u8 opcode[0x10]; 7150 u8 reserved_0[0x10]; 7151 7152 u8 reserved_1[0x10]; 7153 u8 op_mod[0x10]; 7154 7155 u8 reserved_2[0x40]; 7156 7157 struct mlx5_ifc_dctc_bits dct_context_entry; 7158 7159 u8 reserved_3[0x180]; 7160}; 7161 7162struct mlx5_ifc_create_cq_out_bits { 7163 u8 status[0x8]; 7164 u8 reserved_0[0x18]; 7165 7166 u8 syndrome[0x20]; 7167 7168 u8 reserved_1[0x8]; 7169 u8 cqn[0x18]; 7170 7171 u8 reserved_2[0x20]; 7172}; 7173 7174struct mlx5_ifc_create_cq_in_bits { 7175 u8 opcode[0x10]; 7176 u8 reserved_0[0x10]; 7177 7178 u8 reserved_1[0x10]; 7179 u8 op_mod[0x10]; 7180 7181 u8 reserved_2[0x40]; 7182 7183 struct mlx5_ifc_cqc_bits cq_context; 7184 7185 u8 reserved_3[0x600]; 7186 7187 u8 pas[0][0x40]; 7188}; 7189 7190struct mlx5_ifc_config_int_moderation_out_bits { 7191 u8 status[0x8]; 7192 u8 reserved_0[0x18]; 7193 7194 u8 syndrome[0x20]; 7195 7196 u8 reserved_1[0x4]; 7197 u8 min_delay[0xc]; 7198 u8 int_vector[0x10]; 7199 7200 u8 reserved_2[0x20]; 7201}; 7202 7203enum { 7204 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7205 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7206}; 7207 7208struct mlx5_ifc_config_int_moderation_in_bits { 7209 u8 opcode[0x10]; 7210 u8 reserved_0[0x10]; 7211 7212 u8 reserved_1[0x10]; 7213 u8 op_mod[0x10]; 7214 7215 u8 reserved_2[0x4]; 7216 u8 min_delay[0xc]; 7217 u8 int_vector[0x10]; 7218 7219 u8 reserved_3[0x20]; 7220}; 7221 7222struct mlx5_ifc_attach_to_mcg_out_bits { 7223 u8 status[0x8]; 7224 u8 reserved_0[0x18]; 7225 7226 u8 syndrome[0x20]; 7227 7228 u8 reserved_1[0x40]; 7229}; 7230 7231struct mlx5_ifc_attach_to_mcg_in_bits { 7232 u8 opcode[0x10]; 7233 u8 reserved_0[0x10]; 7234 7235 u8 reserved_1[0x10]; 7236 u8 op_mod[0x10]; 7237 7238 u8 reserved_2[0x8]; 7239 u8 qpn[0x18]; 7240 7241 u8 reserved_3[0x20]; 7242 7243 u8 multicast_gid[16][0x8]; 7244}; 7245 7246struct mlx5_ifc_arm_xrc_srq_out_bits { 7247 u8 status[0x8]; 7248 u8 reserved_0[0x18]; 7249 7250 u8 syndrome[0x20]; 7251 7252 u8 reserved_1[0x40]; 7253}; 7254 7255enum { 7256 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7257}; 7258 7259struct mlx5_ifc_arm_xrc_srq_in_bits { 7260 u8 opcode[0x10]; 7261 u8 reserved_0[0x10]; 7262 7263 u8 reserved_1[0x10]; 7264 u8 op_mod[0x10]; 7265 7266 u8 reserved_2[0x8]; 7267 u8 xrc_srqn[0x18]; 7268 7269 u8 reserved_3[0x10]; 7270 u8 lwm[0x10]; 7271}; 7272 7273struct mlx5_ifc_arm_rq_out_bits { 7274 u8 status[0x8]; 7275 u8 reserved_0[0x18]; 7276 7277 u8 syndrome[0x20]; 7278 7279 u8 reserved_1[0x40]; 7280}; 7281 7282enum { 7283 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7284}; 7285 7286struct mlx5_ifc_arm_rq_in_bits { 7287 u8 opcode[0x10]; 7288 u8 reserved_0[0x10]; 7289 7290 u8 reserved_1[0x10]; 7291 u8 op_mod[0x10]; 7292 7293 u8 reserved_2[0x8]; 7294 u8 srq_number[0x18]; 7295 7296 u8 reserved_3[0x10]; 7297 u8 lwm[0x10]; 7298}; 7299 7300struct mlx5_ifc_arm_dct_out_bits { 7301 u8 status[0x8]; 7302 u8 reserved_0[0x18]; 7303 7304 u8 syndrome[0x20]; 7305 7306 u8 reserved_1[0x40]; 7307}; 7308 7309struct mlx5_ifc_arm_dct_in_bits { 7310 u8 opcode[0x10]; 7311 u8 reserved_0[0x10]; 7312 7313 u8 reserved_1[0x10]; 7314 u8 op_mod[0x10]; 7315 7316 u8 reserved_2[0x8]; 7317 u8 dctn[0x18]; 7318 7319 u8 reserved_3[0x20]; 7320}; 7321 7322struct mlx5_ifc_alloc_xrcd_out_bits { 7323 u8 status[0x8]; 7324 u8 reserved_0[0x18]; 7325 7326 u8 syndrome[0x20]; 7327 7328 u8 reserved_1[0x8]; 7329 u8 xrcd[0x18]; 7330 7331 u8 reserved_2[0x20]; 7332}; 7333 7334struct mlx5_ifc_alloc_xrcd_in_bits { 7335 u8 opcode[0x10]; 7336 u8 reserved_0[0x10]; 7337 7338 u8 reserved_1[0x10]; 7339 u8 op_mod[0x10]; 7340 7341 u8 reserved_2[0x40]; 7342}; 7343 7344struct mlx5_ifc_alloc_uar_out_bits { 7345 u8 status[0x8]; 7346 u8 reserved_0[0x18]; 7347 7348 u8 syndrome[0x20]; 7349 7350 u8 reserved_1[0x8]; 7351 u8 uar[0x18]; 7352 7353 u8 reserved_2[0x20]; 7354}; 7355 7356struct mlx5_ifc_alloc_uar_in_bits { 7357 u8 opcode[0x10]; 7358 u8 reserved_0[0x10]; 7359 7360 u8 reserved_1[0x10]; 7361 u8 op_mod[0x10]; 7362 7363 u8 reserved_2[0x40]; 7364}; 7365 7366struct mlx5_ifc_alloc_transport_domain_out_bits { 7367 u8 status[0x8]; 7368 u8 reserved_0[0x18]; 7369 7370 u8 syndrome[0x20]; 7371 7372 u8 reserved_1[0x8]; 7373 u8 transport_domain[0x18]; 7374 7375 u8 reserved_2[0x20]; 7376}; 7377 7378struct mlx5_ifc_alloc_transport_domain_in_bits { 7379 u8 opcode[0x10]; 7380 u8 reserved_0[0x10]; 7381 7382 u8 reserved_1[0x10]; 7383 u8 op_mod[0x10]; 7384 7385 u8 reserved_2[0x40]; 7386}; 7387 7388struct mlx5_ifc_alloc_q_counter_out_bits { 7389 u8 status[0x8]; 7390 u8 reserved_0[0x18]; 7391 7392 u8 syndrome[0x20]; 7393 7394 u8 reserved_1[0x18]; 7395 u8 counter_set_id[0x8]; 7396 7397 u8 reserved_2[0x20]; 7398}; 7399 7400struct mlx5_ifc_alloc_q_counter_in_bits { 7401 u8 opcode[0x10]; 7402 u8 reserved_0[0x10]; 7403 7404 u8 reserved_1[0x10]; 7405 u8 op_mod[0x10]; 7406 7407 u8 reserved_2[0x40]; 7408}; 7409 7410struct mlx5_ifc_alloc_pd_out_bits { 7411 u8 status[0x8]; 7412 u8 reserved_0[0x18]; 7413 7414 u8 syndrome[0x20]; 7415 7416 u8 reserved_1[0x8]; 7417 u8 pd[0x18]; 7418 7419 u8 reserved_2[0x20]; 7420}; 7421 7422struct mlx5_ifc_alloc_pd_in_bits { 7423 u8 opcode[0x10]; 7424 u8 reserved_0[0x10]; 7425 7426 u8 reserved_1[0x10]; 7427 u8 op_mod[0x10]; 7428 7429 u8 reserved_2[0x40]; 7430}; 7431 7432struct mlx5_ifc_alloc_flow_counter_out_bits { 7433 u8 status[0x8]; 7434 u8 reserved_0[0x18]; 7435 7436 u8 syndrome[0x20]; 7437 7438 u8 reserved_1[0x10]; 7439 u8 flow_counter_id[0x10]; 7440 7441 u8 reserved_2[0x20]; 7442}; 7443 7444struct mlx5_ifc_alloc_flow_counter_in_bits { 7445 u8 opcode[0x10]; 7446 u8 reserved_0[0x10]; 7447 7448 u8 reserved_1[0x10]; 7449 u8 op_mod[0x10]; 7450 7451 u8 reserved_2[0x40]; 7452}; 7453 7454struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7455 u8 status[0x8]; 7456 u8 reserved_0[0x18]; 7457 7458 u8 syndrome[0x20]; 7459 7460 u8 reserved_1[0x40]; 7461}; 7462 7463struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7464 u8 opcode[0x10]; 7465 u8 reserved_0[0x10]; 7466 7467 u8 reserved_1[0x10]; 7468 u8 op_mod[0x10]; 7469 7470 u8 reserved_2[0x20]; 7471 7472 u8 reserved_3[0x10]; 7473 u8 vxlan_udp_port[0x10]; 7474}; 7475 7476struct mlx5_ifc_activate_tracer_out_bits { 7477 u8 status[0x8]; 7478 u8 reserved_0[0x18]; 7479 7480 u8 syndrome[0x20]; 7481 7482 u8 reserved_1[0x40]; 7483}; 7484 7485struct mlx5_ifc_activate_tracer_in_bits { 7486 u8 opcode[0x10]; 7487 u8 reserved_0[0x10]; 7488 7489 u8 reserved_1[0x10]; 7490 u8 op_mod[0x10]; 7491 7492 u8 mkey[0x20]; 7493 7494 u8 reserved_2[0x20]; 7495}; 7496 7497struct mlx5_ifc_set_rate_limit_out_bits { 7498 u8 status[0x8]; 7499 u8 reserved_at_8[0x18]; 7500 7501 u8 syndrome[0x20]; 7502 7503 u8 reserved_at_40[0x40]; 7504}; 7505 7506struct mlx5_ifc_set_rate_limit_in_bits { 7507 u8 opcode[0x10]; 7508 u8 reserved_at_10[0x10]; 7509 7510 u8 reserved_at_20[0x10]; 7511 u8 op_mod[0x10]; 7512 7513 u8 reserved_at_40[0x10]; 7514 u8 rate_limit_index[0x10]; 7515 7516 u8 reserved_at_60[0x20]; 7517 7518 u8 rate_limit[0x20]; 7519 u8 burst_upper_bound[0x20]; 7520}; 7521 7522struct mlx5_ifc_access_register_out_bits { 7523 u8 status[0x8]; 7524 u8 reserved_0[0x18]; 7525 7526 u8 syndrome[0x20]; 7527 7528 u8 reserved_1[0x40]; 7529 7530 u8 register_data[0][0x20]; 7531}; 7532 7533enum { 7534 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7535 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7536}; 7537 7538struct mlx5_ifc_access_register_in_bits { 7539 u8 opcode[0x10]; 7540 u8 reserved_0[0x10]; 7541 7542 u8 reserved_1[0x10]; 7543 u8 op_mod[0x10]; 7544 7545 u8 reserved_2[0x10]; 7546 u8 register_id[0x10]; 7547 7548 u8 argument[0x20]; 7549 7550 u8 register_data[0][0x20]; 7551}; 7552 7553struct mlx5_ifc_sltp_reg_bits { 7554 u8 status[0x4]; 7555 u8 version[0x4]; 7556 u8 local_port[0x8]; 7557 u8 pnat[0x2]; 7558 u8 reserved_0[0x2]; 7559 u8 lane[0x4]; 7560 u8 reserved_1[0x8]; 7561 7562 u8 reserved_2[0x20]; 7563 7564 u8 reserved_3[0x7]; 7565 u8 polarity[0x1]; 7566 u8 ob_tap0[0x8]; 7567 u8 ob_tap1[0x8]; 7568 u8 ob_tap2[0x8]; 7569 7570 u8 reserved_4[0xc]; 7571 u8 ob_preemp_mode[0x4]; 7572 u8 ob_reg[0x8]; 7573 u8 ob_bias[0x8]; 7574 7575 u8 reserved_5[0x20]; 7576}; 7577 7578struct mlx5_ifc_slrp_reg_bits { 7579 u8 status[0x4]; 7580 u8 version[0x4]; 7581 u8 local_port[0x8]; 7582 u8 pnat[0x2]; 7583 u8 reserved_0[0x2]; 7584 u8 lane[0x4]; 7585 u8 reserved_1[0x8]; 7586 7587 u8 ib_sel[0x2]; 7588 u8 reserved_2[0x11]; 7589 u8 dp_sel[0x1]; 7590 u8 dp90sel[0x4]; 7591 u8 mix90phase[0x8]; 7592 7593 u8 ffe_tap0[0x8]; 7594 u8 ffe_tap1[0x8]; 7595 u8 ffe_tap2[0x8]; 7596 u8 ffe_tap3[0x8]; 7597 7598 u8 ffe_tap4[0x8]; 7599 u8 ffe_tap5[0x8]; 7600 u8 ffe_tap6[0x8]; 7601 u8 ffe_tap7[0x8]; 7602 7603 u8 ffe_tap8[0x8]; 7604 u8 mixerbias_tap_amp[0x8]; 7605 u8 reserved_3[0x7]; 7606 u8 ffe_tap_en[0x9]; 7607 7608 u8 ffe_tap_offset0[0x8]; 7609 u8 ffe_tap_offset1[0x8]; 7610 u8 slicer_offset0[0x10]; 7611 7612 u8 mixer_offset0[0x10]; 7613 u8 mixer_offset1[0x10]; 7614 7615 u8 mixerbgn_inp[0x8]; 7616 u8 mixerbgn_inn[0x8]; 7617 u8 mixerbgn_refp[0x8]; 7618 u8 mixerbgn_refn[0x8]; 7619 7620 u8 sel_slicer_lctrl_h[0x1]; 7621 u8 sel_slicer_lctrl_l[0x1]; 7622 u8 reserved_4[0x1]; 7623 u8 ref_mixer_vreg[0x5]; 7624 u8 slicer_gctrl[0x8]; 7625 u8 lctrl_input[0x8]; 7626 u8 mixer_offset_cm1[0x8]; 7627 7628 u8 common_mode[0x6]; 7629 u8 reserved_5[0x1]; 7630 u8 mixer_offset_cm0[0x9]; 7631 u8 reserved_6[0x7]; 7632 u8 slicer_offset_cm[0x9]; 7633}; 7634 7635struct mlx5_ifc_slrg_reg_bits { 7636 u8 status[0x4]; 7637 u8 version[0x4]; 7638 u8 local_port[0x8]; 7639 u8 pnat[0x2]; 7640 u8 reserved_0[0x2]; 7641 u8 lane[0x4]; 7642 u8 reserved_1[0x8]; 7643 7644 u8 time_to_link_up[0x10]; 7645 u8 reserved_2[0xc]; 7646 u8 grade_lane_speed[0x4]; 7647 7648 u8 grade_version[0x8]; 7649 u8 grade[0x18]; 7650 7651 u8 reserved_3[0x4]; 7652 u8 height_grade_type[0x4]; 7653 u8 height_grade[0x18]; 7654 7655 u8 height_dz[0x10]; 7656 u8 height_dv[0x10]; 7657 7658 u8 reserved_4[0x10]; 7659 u8 height_sigma[0x10]; 7660 7661 u8 reserved_5[0x20]; 7662 7663 u8 reserved_6[0x4]; 7664 u8 phase_grade_type[0x4]; 7665 u8 phase_grade[0x18]; 7666 7667 u8 reserved_7[0x8]; 7668 u8 phase_eo_pos[0x8]; 7669 u8 reserved_8[0x8]; 7670 u8 phase_eo_neg[0x8]; 7671 7672 u8 ffe_set_tested[0x10]; 7673 u8 test_errors_per_lane[0x10]; 7674}; 7675 7676struct mlx5_ifc_pvlc_reg_bits { 7677 u8 reserved_0[0x8]; 7678 u8 local_port[0x8]; 7679 u8 reserved_1[0x10]; 7680 7681 u8 reserved_2[0x1c]; 7682 u8 vl_hw_cap[0x4]; 7683 7684 u8 reserved_3[0x1c]; 7685 u8 vl_admin[0x4]; 7686 7687 u8 reserved_4[0x1c]; 7688 u8 vl_operational[0x4]; 7689}; 7690 7691struct mlx5_ifc_pude_reg_bits { 7692 u8 swid[0x8]; 7693 u8 local_port[0x8]; 7694 u8 reserved_0[0x4]; 7695 u8 admin_status[0x4]; 7696 u8 reserved_1[0x4]; 7697 u8 oper_status[0x4]; 7698 7699 u8 reserved_2[0x60]; 7700}; 7701 7702enum { 7703 MLX5_PTYS_REG_PROTO_MASK_INFINIBAND = 0x1, 7704 MLX5_PTYS_REG_PROTO_MASK_ETHERNET = 0x4, 7705}; 7706 7707struct mlx5_ifc_ptys_reg_bits { 7708 u8 reserved_0[0x1]; 7709 u8 an_disable_admin[0x1]; 7710 u8 an_disable_cap[0x1]; 7711 u8 reserved_1[0x4]; 7712 u8 force_tx_aba_param[0x1]; 7713 u8 local_port[0x8]; 7714 u8 reserved_2[0xd]; 7715 u8 proto_mask[0x3]; 7716 7717 u8 an_status[0x4]; 7718 u8 reserved_3[0xc]; 7719 u8 data_rate_oper[0x10]; 7720 7721 u8 fc_proto_capability[0x20]; 7722 7723 u8 eth_proto_capability[0x20]; 7724 7725 u8 ib_link_width_capability[0x10]; 7726 u8 ib_proto_capability[0x10]; 7727 7728 u8 fc_proto_admin[0x20]; 7729 7730 u8 eth_proto_admin[0x20]; 7731 7732 u8 ib_link_width_admin[0x10]; 7733 u8 ib_proto_admin[0x10]; 7734 7735 u8 fc_proto_oper[0x20]; 7736 7737 u8 eth_proto_oper[0x20]; 7738 7739 u8 ib_link_width_oper[0x10]; 7740 u8 ib_proto_oper[0x10]; 7741 7742 u8 reserved_4[0x20]; 7743 7744 u8 eth_proto_lp_advertise[0x20]; 7745 7746 u8 reserved_5[0x60]; 7747}; 7748 7749struct mlx5_ifc_ptas_reg_bits { 7750 u8 reserved_0[0x20]; 7751 7752 u8 algorithm_options[0x10]; 7753 u8 reserved_1[0x4]; 7754 u8 repetitions_mode[0x4]; 7755 u8 num_of_repetitions[0x8]; 7756 7757 u8 grade_version[0x8]; 7758 u8 height_grade_type[0x4]; 7759 u8 phase_grade_type[0x4]; 7760 u8 height_grade_weight[0x8]; 7761 u8 phase_grade_weight[0x8]; 7762 7763 u8 gisim_measure_bits[0x10]; 7764 u8 adaptive_tap_measure_bits[0x10]; 7765 7766 u8 ber_bath_high_error_threshold[0x10]; 7767 u8 ber_bath_mid_error_threshold[0x10]; 7768 7769 u8 ber_bath_low_error_threshold[0x10]; 7770 u8 one_ratio_high_threshold[0x10]; 7771 7772 u8 one_ratio_high_mid_threshold[0x10]; 7773 u8 one_ratio_low_mid_threshold[0x10]; 7774 7775 u8 one_ratio_low_threshold[0x10]; 7776 u8 ndeo_error_threshold[0x10]; 7777 7778 u8 mixer_offset_step_size[0x10]; 7779 u8 reserved_2[0x8]; 7780 u8 mix90_phase_for_voltage_bath[0x8]; 7781 7782 u8 mixer_offset_start[0x10]; 7783 u8 mixer_offset_end[0x10]; 7784 7785 u8 reserved_3[0x15]; 7786 u8 ber_test_time[0xb]; 7787}; 7788 7789struct mlx5_ifc_pspa_reg_bits { 7790 u8 swid[0x8]; 7791 u8 local_port[0x8]; 7792 u8 sub_port[0x8]; 7793 u8 reserved_0[0x8]; 7794 7795 u8 reserved_1[0x20]; 7796}; 7797 7798struct mlx5_ifc_ppsc_reg_bits { 7799 u8 reserved_0[0x8]; 7800 u8 local_port[0x8]; 7801 u8 reserved_1[0x10]; 7802 7803 u8 reserved_2[0x60]; 7804 7805 u8 reserved_3[0x1c]; 7806 u8 wrps_admin[0x4]; 7807 7808 u8 reserved_4[0x1c]; 7809 u8 wrps_status[0x4]; 7810 7811 u8 up_th_vld[0x1]; 7812 u8 down_th_vld[0x1]; 7813 u8 reserved_5[0x6]; 7814 u8 up_threshold[0x8]; 7815 u8 reserved_6[0x8]; 7816 u8 down_threshold[0x8]; 7817 7818 u8 reserved_7[0x20]; 7819 7820 u8 reserved_8[0x1c]; 7821 u8 srps_admin[0x4]; 7822 7823 u8 reserved_9[0x60]; 7824}; 7825 7826struct mlx5_ifc_pplr_reg_bits { 7827 u8 reserved_0[0x8]; 7828 u8 local_port[0x8]; 7829 u8 reserved_1[0x10]; 7830 7831 u8 reserved_2[0x8]; 7832 u8 lb_cap[0x8]; 7833 u8 reserved_3[0x8]; 7834 u8 lb_en[0x8]; 7835}; 7836 7837struct mlx5_ifc_pplm_reg_bits { 7838 u8 reserved_0[0x8]; 7839 u8 local_port[0x8]; 7840 u8 reserved_1[0x10]; 7841 7842 u8 reserved_2[0x20]; 7843 7844 u8 port_profile_mode[0x8]; 7845 u8 static_port_profile[0x8]; 7846 u8 active_port_profile[0x8]; 7847 u8 reserved_3[0x8]; 7848 7849 u8 retransmission_active[0x8]; 7850 u8 fec_mode_active[0x18]; 7851 7852 u8 reserved_4[0x10]; 7853 u8 v_100g_fec_override_cap[0x4]; 7854 u8 v_50g_fec_override_cap[0x4]; 7855 u8 v_25g_fec_override_cap[0x4]; 7856 u8 v_10g_40g_fec_override_cap[0x4]; 7857 7858 u8 reserved_5[0x10]; 7859 u8 v_100g_fec_override_admin[0x4]; 7860 u8 v_50g_fec_override_admin[0x4]; 7861 u8 v_25g_fec_override_admin[0x4]; 7862 u8 v_10g_40g_fec_override_admin[0x4]; 7863}; 7864 7865struct mlx5_ifc_ppll_reg_bits { 7866 u8 num_pll_groups[0x8]; 7867 u8 pll_group[0x8]; 7868 u8 reserved_0[0x4]; 7869 u8 num_plls[0x4]; 7870 u8 reserved_1[0x8]; 7871 7872 u8 reserved_2[0x1f]; 7873 u8 ae[0x1]; 7874 7875 u8 pll_status[4][0x40]; 7876}; 7877 7878struct mlx5_ifc_ppad_reg_bits { 7879 u8 reserved_0[0x3]; 7880 u8 single_mac[0x1]; 7881 u8 reserved_1[0x4]; 7882 u8 local_port[0x8]; 7883 u8 mac_47_32[0x10]; 7884 7885 u8 mac_31_0[0x20]; 7886 7887 u8 reserved_2[0x40]; 7888}; 7889 7890struct mlx5_ifc_pmtu_reg_bits { 7891 u8 reserved_0[0x8]; 7892 u8 local_port[0x8]; 7893 u8 reserved_1[0x10]; 7894 7895 u8 max_mtu[0x10]; 7896 u8 reserved_2[0x10]; 7897 7898 u8 admin_mtu[0x10]; 7899 u8 reserved_3[0x10]; 7900 7901 u8 oper_mtu[0x10]; 7902 u8 reserved_4[0x10]; 7903}; 7904 7905struct mlx5_ifc_pmpr_reg_bits { 7906 u8 reserved_0[0x8]; 7907 u8 module[0x8]; 7908 u8 reserved_1[0x10]; 7909 7910 u8 reserved_2[0x18]; 7911 u8 attenuation_5g[0x8]; 7912 7913 u8 reserved_3[0x18]; 7914 u8 attenuation_7g[0x8]; 7915 7916 u8 reserved_4[0x18]; 7917 u8 attenuation_12g[0x8]; 7918}; 7919 7920struct mlx5_ifc_pmpe_reg_bits { 7921 u8 reserved_0[0x8]; 7922 u8 module[0x8]; 7923 u8 reserved_1[0xc]; 7924 u8 module_status[0x4]; 7925 7926 u8 reserved_2[0x14]; 7927 u8 error_type[0x4]; 7928 u8 reserved_3[0x8]; 7929 7930 u8 reserved_4[0x40]; 7931}; 7932 7933struct mlx5_ifc_pmpc_reg_bits { 7934 u8 module_state_updated[32][0x8]; 7935}; 7936 7937struct mlx5_ifc_pmlpn_reg_bits { 7938 u8 reserved_0[0x4]; 7939 u8 mlpn_status[0x4]; 7940 u8 local_port[0x8]; 7941 u8 reserved_1[0x10]; 7942 7943 u8 e[0x1]; 7944 u8 reserved_2[0x1f]; 7945}; 7946 7947struct mlx5_ifc_pmlp_reg_bits { 7948 u8 rxtx[0x1]; 7949 u8 reserved_0[0x7]; 7950 u8 local_port[0x8]; 7951 u8 reserved_1[0x8]; 7952 u8 width[0x8]; 7953 7954 u8 lane0_module_mapping[0x20]; 7955 7956 u8 lane1_module_mapping[0x20]; 7957 7958 u8 lane2_module_mapping[0x20]; 7959 7960 u8 lane3_module_mapping[0x20]; 7961 7962 u8 reserved_2[0x160]; 7963}; 7964 7965struct mlx5_ifc_pmaos_reg_bits { 7966 u8 reserved_0[0x8]; 7967 u8 module[0x8]; 7968 u8 reserved_1[0x4]; 7969 u8 admin_status[0x4]; 7970 u8 reserved_2[0x4]; 7971 u8 oper_status[0x4]; 7972 7973 u8 ase[0x1]; 7974 u8 ee[0x1]; 7975 u8 reserved_3[0x12]; 7976 u8 error_type[0x4]; 7977 u8 reserved_4[0x6]; 7978 u8 e[0x2]; 7979 7980 u8 reserved_5[0x40]; 7981}; 7982 7983struct mlx5_ifc_plpc_reg_bits { 7984 u8 reserved_0[0x4]; 7985 u8 profile_id[0xc]; 7986 u8 reserved_1[0x4]; 7987 u8 proto_mask[0x4]; 7988 u8 reserved_2[0x8]; 7989 7990 u8 reserved_3[0x10]; 7991 u8 lane_speed[0x10]; 7992 7993 u8 reserved_4[0x17]; 7994 u8 lpbf[0x1]; 7995 u8 fec_mode_policy[0x8]; 7996 7997 u8 retransmission_capability[0x8]; 7998 u8 fec_mode_capability[0x18]; 7999 8000 u8 retransmission_support_admin[0x8]; 8001 u8 fec_mode_support_admin[0x18]; 8002 8003 u8 retransmission_request_admin[0x8]; 8004 u8 fec_mode_request_admin[0x18]; 8005 8006 u8 reserved_5[0x80]; 8007}; 8008 8009struct mlx5_ifc_pll_status_data_bits { 8010 u8 reserved_0[0x1]; 8011 u8 lock_cal[0x1]; 8012 u8 lock_status[0x2]; 8013 u8 reserved_1[0x2]; 8014 u8 algo_f_ctrl[0xa]; 8015 u8 analog_algo_num_var[0x6]; 8016 u8 f_ctrl_measure[0xa]; 8017 8018 u8 reserved_2[0x2]; 8019 u8 analog_var[0x6]; 8020 u8 reserved_3[0x2]; 8021 u8 high_var[0x6]; 8022 u8 reserved_4[0x2]; 8023 u8 low_var[0x6]; 8024 u8 reserved_5[0x2]; 8025 u8 mid_val[0x6]; 8026}; 8027 8028struct mlx5_ifc_plib_reg_bits { 8029 u8 reserved_0[0x8]; 8030 u8 local_port[0x8]; 8031 u8 reserved_1[0x8]; 8032 u8 ib_port[0x8]; 8033 8034 u8 reserved_2[0x60]; 8035}; 8036 8037struct mlx5_ifc_plbf_reg_bits { 8038 u8 reserved_0[0x8]; 8039 u8 local_port[0x8]; 8040 u8 reserved_1[0xd]; 8041 u8 lbf_mode[0x3]; 8042 8043 u8 reserved_2[0x20]; 8044}; 8045 8046struct mlx5_ifc_pipg_reg_bits { 8047 u8 reserved_0[0x8]; 8048 u8 local_port[0x8]; 8049 u8 reserved_1[0x10]; 8050 8051 u8 dic[0x1]; 8052 u8 reserved_2[0x19]; 8053 u8 ipg[0x4]; 8054 u8 reserved_3[0x2]; 8055}; 8056 8057struct mlx5_ifc_pifr_reg_bits { 8058 u8 reserved_0[0x8]; 8059 u8 local_port[0x8]; 8060 u8 reserved_1[0x10]; 8061 8062 u8 reserved_2[0xe0]; 8063 8064 u8 port_filter[8][0x20]; 8065 8066 u8 port_filter_update_en[8][0x20]; 8067}; 8068 8069struct mlx5_ifc_phys_layer_cntrs_bits { 8070 u8 time_since_last_clear_high[0x20]; 8071 8072 u8 time_since_last_clear_low[0x20]; 8073 8074 u8 symbol_errors_high[0x20]; 8075 8076 u8 symbol_errors_low[0x20]; 8077 8078 u8 sync_headers_errors_high[0x20]; 8079 8080 u8 sync_headers_errors_low[0x20]; 8081 8082 u8 edpl_bip_errors_lane0_high[0x20]; 8083 8084 u8 edpl_bip_errors_lane0_low[0x20]; 8085 8086 u8 edpl_bip_errors_lane1_high[0x20]; 8087 8088 u8 edpl_bip_errors_lane1_low[0x20]; 8089 8090 u8 edpl_bip_errors_lane2_high[0x20]; 8091 8092 u8 edpl_bip_errors_lane2_low[0x20]; 8093 8094 u8 edpl_bip_errors_lane3_high[0x20]; 8095 8096 u8 edpl_bip_errors_lane3_low[0x20]; 8097 8098 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 8099 8100 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 8101 8102 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 8103 8104 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 8105 8106 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 8107 8108 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 8109 8110 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 8111 8112 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 8113 8114 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 8115 8116 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 8117 8118 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 8119 8120 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 8121 8122 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 8123 8124 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 8125 8126 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 8127 8128 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 8129 8130 u8 rs_fec_corrected_blocks_high[0x20]; 8131 8132 u8 rs_fec_corrected_blocks_low[0x20]; 8133 8134 u8 rs_fec_uncorrectable_blocks_high[0x20]; 8135 8136 u8 rs_fec_uncorrectable_blocks_low[0x20]; 8137 8138 u8 rs_fec_no_errors_blocks_high[0x20]; 8139 8140 u8 rs_fec_no_errors_blocks_low[0x20]; 8141 8142 u8 rs_fec_single_error_blocks_high[0x20]; 8143 8144 u8 rs_fec_single_error_blocks_low[0x20]; 8145 8146 u8 rs_fec_corrected_symbols_total_high[0x20]; 8147 8148 u8 rs_fec_corrected_symbols_total_low[0x20]; 8149 8150 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 8151 8152 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 8153 8154 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 8155 8156 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 8157 8158 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 8159 8160 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 8161 8162 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 8163 8164 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 8165 8166 u8 link_down_events[0x20]; 8167 8168 u8 successful_recovery_events[0x20]; 8169 8170 u8 reserved_0[0x180]; 8171}; 8172 8173struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 8174 u8 symbol_error_counter[0x10]; 8175 8176 u8 link_error_recovery_counter[0x8]; 8177 8178 u8 link_downed_counter[0x8]; 8179 8180 u8 port_rcv_errors[0x10]; 8181 8182 u8 port_rcv_remote_physical_errors[0x10]; 8183 8184 u8 port_rcv_switch_relay_errors[0x10]; 8185 8186 u8 port_xmit_discards[0x10]; 8187 8188 u8 port_xmit_constraint_errors[0x8]; 8189 8190 u8 port_rcv_constraint_errors[0x8]; 8191 8192 u8 reserved_at_70[0x8]; 8193 8194 u8 link_overrun_errors[0x8]; 8195 8196 u8 reserved_at_80[0x10]; 8197 8198 u8 vl_15_dropped[0x10]; 8199 8200 u8 reserved_at_a0[0xa0]; 8201}; 8202 8203struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 8204 u8 time_since_last_clear_high[0x20]; 8205 8206 u8 time_since_last_clear_low[0x20]; 8207 8208 u8 phy_received_bits_high[0x20]; 8209 8210 u8 phy_received_bits_low[0x20]; 8211 8212 u8 phy_symbol_errors_high[0x20]; 8213 8214 u8 phy_symbol_errors_low[0x20]; 8215 8216 u8 phy_corrected_bits_high[0x20]; 8217 8218 u8 phy_corrected_bits_low[0x20]; 8219 8220 u8 phy_corrected_bits_lane0_high[0x20]; 8221 8222 u8 phy_corrected_bits_lane0_low[0x20]; 8223 8224 u8 phy_corrected_bits_lane1_high[0x20]; 8225 8226 u8 phy_corrected_bits_lane1_low[0x20]; 8227 8228 u8 phy_corrected_bits_lane2_high[0x20]; 8229 8230 u8 phy_corrected_bits_lane2_low[0x20]; 8231 8232 u8 phy_corrected_bits_lane3_high[0x20]; 8233 8234 u8 phy_corrected_bits_lane3_low[0x20]; 8235 8236 u8 reserved_at_200[0x5c0]; 8237}; 8238 8239struct mlx5_ifc_infiniband_port_cntrs_bits { 8240 u8 symbol_error_counter[0x10]; 8241 u8 link_error_recovery_counter[0x8]; 8242 u8 link_downed_counter[0x8]; 8243 8244 u8 port_rcv_errors[0x10]; 8245 u8 port_rcv_remote_physical_errors[0x10]; 8246 8247 u8 port_rcv_switch_relay_errors[0x10]; 8248 u8 port_xmit_discards[0x10]; 8249 8250 u8 port_xmit_constraint_errors[0x8]; 8251 u8 port_rcv_constraint_errors[0x8]; 8252 u8 reserved_0[0x8]; 8253 u8 local_link_integrity_errors[0x4]; 8254 u8 excessive_buffer_overrun_errors[0x4]; 8255 8256 u8 reserved_1[0x10]; 8257 u8 vl_15_dropped[0x10]; 8258 8259 u8 port_xmit_data[0x20]; 8260 8261 u8 port_rcv_data[0x20]; 8262 8263 u8 port_xmit_pkts[0x20]; 8264 8265 u8 port_rcv_pkts[0x20]; 8266 8267 u8 port_xmit_wait[0x20]; 8268 8269 u8 reserved_2[0x680]; 8270}; 8271 8272struct mlx5_ifc_phrr_reg_bits { 8273 u8 clr[0x1]; 8274 u8 reserved_0[0x7]; 8275 u8 local_port[0x8]; 8276 u8 reserved_1[0x10]; 8277 8278 u8 hist_group[0x8]; 8279 u8 reserved_2[0x10]; 8280 u8 hist_id[0x8]; 8281 8282 u8 reserved_3[0x40]; 8283 8284 u8 time_since_last_clear_high[0x20]; 8285 8286 u8 time_since_last_clear_low[0x20]; 8287 8288 u8 bin[10][0x20]; 8289}; 8290 8291struct mlx5_ifc_phbr_for_prio_reg_bits { 8292 u8 reserved_0[0x18]; 8293 u8 prio[0x8]; 8294}; 8295 8296struct mlx5_ifc_phbr_for_port_tclass_reg_bits { 8297 u8 reserved_0[0x18]; 8298 u8 tclass[0x8]; 8299}; 8300 8301struct mlx5_ifc_phbr_binding_reg_bits { 8302 u8 opcode[0x4]; 8303 u8 reserved_0[0x4]; 8304 u8 local_port[0x8]; 8305 u8 pnat[0x2]; 8306 u8 reserved_1[0xe]; 8307 8308 u8 hist_group[0x8]; 8309 u8 reserved_2[0x10]; 8310 u8 hist_id[0x8]; 8311 8312 u8 reserved_3[0x10]; 8313 u8 hist_type[0x10]; 8314 8315 u8 hist_parameters[0x20]; 8316 8317 u8 hist_min_value[0x20]; 8318 8319 u8 hist_max_value[0x20]; 8320 8321 u8 sample_time[0x20]; 8322}; 8323 8324enum { 8325 MLX5_PFCC_REG_PPAN_DISABLED = 0x0, 8326 MLX5_PFCC_REG_PPAN_ENABLED = 0x1, 8327}; 8328 8329struct mlx5_ifc_pfcc_reg_bits { 8330 u8 dcbx_operation_type[0x2]; 8331 u8 cap_local_admin[0x1]; 8332 u8 cap_remote_admin[0x1]; 8333 u8 reserved_0[0x4]; 8334 u8 local_port[0x8]; 8335 u8 pnat[0x2]; 8336 u8 reserved_1[0xc]; 8337 u8 shl_cap[0x1]; 8338 u8 shl_opr[0x1]; 8339 8340 u8 ppan[0x4]; 8341 u8 reserved_2[0x4]; 8342 u8 prio_mask_tx[0x8]; 8343 u8 reserved_3[0x8]; 8344 u8 prio_mask_rx[0x8]; 8345 8346 u8 pptx[0x1]; 8347 u8 aptx[0x1]; 8348 u8 reserved_4[0x6]; 8349 u8 pfctx[0x8]; 8350 u8 reserved_5[0x8]; 8351 u8 cbftx[0x8]; 8352 8353 u8 pprx[0x1]; 8354 u8 aprx[0x1]; 8355 u8 reserved_6[0x6]; 8356 u8 pfcrx[0x8]; 8357 u8 reserved_7[0x8]; 8358 u8 cbfrx[0x8]; 8359 8360 u8 device_stall_minor_watermark[0x10]; 8361 u8 device_stall_critical_watermark[0x10]; 8362 8363 u8 reserved_8[0x60]; 8364}; 8365 8366struct mlx5_ifc_pelc_reg_bits { 8367 u8 op[0x4]; 8368 u8 reserved_0[0x4]; 8369 u8 local_port[0x8]; 8370 u8 reserved_1[0x10]; 8371 8372 u8 op_admin[0x8]; 8373 u8 op_capability[0x8]; 8374 u8 op_request[0x8]; 8375 u8 op_active[0x8]; 8376 8377 u8 admin[0x40]; 8378 8379 u8 capability[0x40]; 8380 8381 u8 request[0x40]; 8382 8383 u8 active[0x40]; 8384 8385 u8 reserved_2[0x80]; 8386}; 8387 8388struct mlx5_ifc_peir_reg_bits { 8389 u8 reserved_0[0x8]; 8390 u8 local_port[0x8]; 8391 u8 reserved_1[0x10]; 8392 8393 u8 reserved_2[0xc]; 8394 u8 error_count[0x4]; 8395 u8 reserved_3[0x10]; 8396 8397 u8 reserved_4[0xc]; 8398 u8 lane[0x4]; 8399 u8 reserved_5[0x8]; 8400 u8 error_type[0x8]; 8401}; 8402 8403struct mlx5_ifc_qcam_access_reg_cap_mask { 8404 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 8405 u8 qpdpm[0x1]; 8406 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 8407 u8 qdpm[0x1]; 8408 u8 qpts[0x1]; 8409 u8 qcap[0x1]; 8410 u8 qcam_access_reg_cap_mask_0[0x1]; 8411}; 8412 8413struct mlx5_ifc_qcam_qos_feature_cap_mask { 8414 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 8415 u8 qpts_trust_both[0x1]; 8416}; 8417 8418struct mlx5_ifc_qcam_reg_bits { 8419 u8 reserved_at_0[0x8]; 8420 u8 feature_group[0x8]; 8421 u8 reserved_at_10[0x8]; 8422 u8 access_reg_group[0x8]; 8423 u8 reserved_at_20[0x20]; 8424 8425 union { 8426 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 8427 u8 reserved_at_0[0x80]; 8428 } qos_access_reg_cap_mask; 8429 8430 u8 reserved_at_c0[0x80]; 8431 8432 union { 8433 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 8434 u8 reserved_at_0[0x80]; 8435 } qos_feature_cap_mask; 8436 8437 u8 reserved_at_1c0[0x80]; 8438}; 8439 8440struct mlx5_ifc_pcap_reg_bits { 8441 u8 reserved_0[0x8]; 8442 u8 local_port[0x8]; 8443 u8 reserved_1[0x10]; 8444 8445 u8 port_capability_mask[4][0x20]; 8446}; 8447 8448struct mlx5_ifc_pbmc_reg_bits { 8449 u8 reserved_0[0x8]; 8450 u8 local_port[0x8]; 8451 u8 reserved_1[0x10]; 8452 8453 u8 xoff_timer_value[0x10]; 8454 u8 xoff_refresh[0x10]; 8455 8456 u8 reserved_2[0x10]; 8457 u8 port_buffer_size[0x10]; 8458 8459 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 8460 8461 u8 reserved_3[0x40]; 8462 8463 u8 port_shared_buffer[0x40]; 8464}; 8465 8466struct mlx5_ifc_paos_reg_bits { 8467 u8 swid[0x8]; 8468 u8 local_port[0x8]; 8469 u8 reserved_0[0x4]; 8470 u8 admin_status[0x4]; 8471 u8 reserved_1[0x4]; 8472 u8 oper_status[0x4]; 8473 8474 u8 ase[0x1]; 8475 u8 ee[0x1]; 8476 u8 reserved_2[0x1c]; 8477 u8 e[0x2]; 8478 8479 u8 reserved_3[0x40]; 8480}; 8481 8482struct mlx5_ifc_pamp_reg_bits { 8483 u8 reserved_0[0x8]; 8484 u8 opamp_group[0x8]; 8485 u8 reserved_1[0xc]; 8486 u8 opamp_group_type[0x4]; 8487 8488 u8 start_index[0x10]; 8489 u8 reserved_2[0x4]; 8490 u8 num_of_indices[0xc]; 8491 8492 u8 index_data[18][0x10]; 8493}; 8494 8495struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits { 8496 u8 llr_rx_cells_high[0x20]; 8497 8498 u8 llr_rx_cells_low[0x20]; 8499 8500 u8 llr_rx_error_high[0x20]; 8501 8502 u8 llr_rx_error_low[0x20]; 8503 8504 u8 llr_rx_crc_error_high[0x20]; 8505 8506 u8 llr_rx_crc_error_low[0x20]; 8507 8508 u8 llr_tx_cells_high[0x20]; 8509 8510 u8 llr_tx_cells_low[0x20]; 8511 8512 u8 llr_tx_ret_cells_high[0x20]; 8513 8514 u8 llr_tx_ret_cells_low[0x20]; 8515 8516 u8 llr_tx_ret_events_high[0x20]; 8517 8518 u8 llr_tx_ret_events_low[0x20]; 8519 8520 u8 reserved_0[0x640]; 8521}; 8522 8523struct mlx5_ifc_mtmp_reg_bits { 8524 u8 i[0x1]; 8525 u8 reserved_at_1[0x18]; 8526 u8 sensor_index[0x7]; 8527 8528 u8 reserved_at_20[0x10]; 8529 u8 temperature[0x10]; 8530 8531 u8 mte[0x1]; 8532 u8 mtr[0x1]; 8533 u8 reserved_at_42[0x0e]; 8534 u8 max_temperature[0x10]; 8535 8536 u8 tee[0x2]; 8537 u8 reserved_at_62[0x0e]; 8538 u8 temperature_threshold_hi[0x10]; 8539 8540 u8 reserved_at_80[0x10]; 8541 u8 temperature_threshold_lo[0x10]; 8542 8543 u8 reserved_at_100[0x20]; 8544 8545 u8 sensor_name[0x40]; 8546}; 8547 8548struct mlx5_ifc_lane_2_module_mapping_bits { 8549 u8 reserved_0[0x6]; 8550 u8 rx_lane[0x2]; 8551 u8 reserved_1[0x6]; 8552 u8 tx_lane[0x2]; 8553 u8 reserved_2[0x8]; 8554 u8 module[0x8]; 8555}; 8556 8557struct mlx5_ifc_eth_per_traffic_class_layout_bits { 8558 u8 transmit_queue_high[0x20]; 8559 8560 u8 transmit_queue_low[0x20]; 8561 8562 u8 reserved_0[0x780]; 8563}; 8564 8565struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits { 8566 u8 no_buffer_discard_uc_high[0x20]; 8567 8568 u8 no_buffer_discard_uc_low[0x20]; 8569 8570 u8 wred_discard_high[0x20]; 8571 8572 u8 wred_discard_low[0x20]; 8573 8574 u8 reserved_0[0x740]; 8575}; 8576 8577struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 8578 u8 rx_octets_high[0x20]; 8579 8580 u8 rx_octets_low[0x20]; 8581 8582 u8 reserved_0[0xc0]; 8583 8584 u8 rx_frames_high[0x20]; 8585 8586 u8 rx_frames_low[0x20]; 8587 8588 u8 tx_octets_high[0x20]; 8589 8590 u8 tx_octets_low[0x20]; 8591 8592 u8 reserved_1[0xc0]; 8593 8594 u8 tx_frames_high[0x20]; 8595 8596 u8 tx_frames_low[0x20]; 8597 8598 u8 rx_pause_high[0x20]; 8599 8600 u8 rx_pause_low[0x20]; 8601 8602 u8 rx_pause_duration_high[0x20]; 8603 8604 u8 rx_pause_duration_low[0x20]; 8605 8606 u8 tx_pause_high[0x20]; 8607 8608 u8 tx_pause_low[0x20]; 8609 8610 u8 tx_pause_duration_high[0x20]; 8611 8612 u8 tx_pause_duration_low[0x20]; 8613 8614 u8 rx_pause_transition_high[0x20]; 8615 8616 u8 rx_pause_transition_low[0x20]; 8617 8618 u8 rx_discards_high[0x20]; 8619 8620 u8 rx_discards_low[0x20]; 8621 8622 u8 device_stall_minor_watermark_cnt_high[0x20]; 8623 8624 u8 device_stall_minor_watermark_cnt_low[0x20]; 8625 8626 u8 device_stall_critical_watermark_cnt_high[0x20]; 8627 8628 u8 device_stall_critical_watermark_cnt_low[0x20]; 8629 8630 u8 reserved_2[0x340]; 8631}; 8632 8633struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 8634 u8 port_transmit_wait_high[0x20]; 8635 8636 u8 port_transmit_wait_low[0x20]; 8637 8638 u8 ecn_marked_high[0x20]; 8639 8640 u8 ecn_marked_low[0x20]; 8641 8642 u8 no_buffer_discard_mc_high[0x20]; 8643 8644 u8 no_buffer_discard_mc_low[0x20]; 8645 8646 u8 reserved_0[0x700]; 8647}; 8648 8649struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 8650 u8 a_frames_transmitted_ok_high[0x20]; 8651 8652 u8 a_frames_transmitted_ok_low[0x20]; 8653 8654 u8 a_frames_received_ok_high[0x20]; 8655 8656 u8 a_frames_received_ok_low[0x20]; 8657 8658 u8 a_frame_check_sequence_errors_high[0x20]; 8659 8660 u8 a_frame_check_sequence_errors_low[0x20]; 8661 8662 u8 a_alignment_errors_high[0x20]; 8663 8664 u8 a_alignment_errors_low[0x20]; 8665 8666 u8 a_octets_transmitted_ok_high[0x20]; 8667 8668 u8 a_octets_transmitted_ok_low[0x20]; 8669 8670 u8 a_octets_received_ok_high[0x20]; 8671 8672 u8 a_octets_received_ok_low[0x20]; 8673 8674 u8 a_multicast_frames_xmitted_ok_high[0x20]; 8675 8676 u8 a_multicast_frames_xmitted_ok_low[0x20]; 8677 8678 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 8679 8680 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 8681 8682 u8 a_multicast_frames_received_ok_high[0x20]; 8683 8684 u8 a_multicast_frames_received_ok_low[0x20]; 8685 8686 u8 a_broadcast_frames_recieved_ok_high[0x20]; 8687 8688 u8 a_broadcast_frames_recieved_ok_low[0x20]; 8689 8690 u8 a_in_range_length_errors_high[0x20]; 8691 8692 u8 a_in_range_length_errors_low[0x20]; 8693 8694 u8 a_out_of_range_length_field_high[0x20]; 8695 8696 u8 a_out_of_range_length_field_low[0x20]; 8697 8698 u8 a_frame_too_long_errors_high[0x20]; 8699 8700 u8 a_frame_too_long_errors_low[0x20]; 8701 8702 u8 a_symbol_error_during_carrier_high[0x20]; 8703 8704 u8 a_symbol_error_during_carrier_low[0x20]; 8705 8706 u8 a_mac_control_frames_transmitted_high[0x20]; 8707 8708 u8 a_mac_control_frames_transmitted_low[0x20]; 8709 8710 u8 a_mac_control_frames_received_high[0x20]; 8711 8712 u8 a_mac_control_frames_received_low[0x20]; 8713 8714 u8 a_unsupported_opcodes_received_high[0x20]; 8715 8716 u8 a_unsupported_opcodes_received_low[0x20]; 8717 8718 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 8719 8720 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 8721 8722 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 8723 8724 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 8725 8726 u8 reserved_0[0x300]; 8727}; 8728 8729struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 8730 u8 dot3stats_alignment_errors_high[0x20]; 8731 8732 u8 dot3stats_alignment_errors_low[0x20]; 8733 8734 u8 dot3stats_fcs_errors_high[0x20]; 8735 8736 u8 dot3stats_fcs_errors_low[0x20]; 8737 8738 u8 dot3stats_single_collision_frames_high[0x20]; 8739 8740 u8 dot3stats_single_collision_frames_low[0x20]; 8741 8742 u8 dot3stats_multiple_collision_frames_high[0x20]; 8743 8744 u8 dot3stats_multiple_collision_frames_low[0x20]; 8745 8746 u8 dot3stats_sqe_test_errors_high[0x20]; 8747 8748 u8 dot3stats_sqe_test_errors_low[0x20]; 8749 8750 u8 dot3stats_deferred_transmissions_high[0x20]; 8751 8752 u8 dot3stats_deferred_transmissions_low[0x20]; 8753 8754 u8 dot3stats_late_collisions_high[0x20]; 8755 8756 u8 dot3stats_late_collisions_low[0x20]; 8757 8758 u8 dot3stats_excessive_collisions_high[0x20]; 8759 8760 u8 dot3stats_excessive_collisions_low[0x20]; 8761 8762 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 8763 8764 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 8765 8766 u8 dot3stats_carrier_sense_errors_high[0x20]; 8767 8768 u8 dot3stats_carrier_sense_errors_low[0x20]; 8769 8770 u8 dot3stats_frame_too_longs_high[0x20]; 8771 8772 u8 dot3stats_frame_too_longs_low[0x20]; 8773 8774 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 8775 8776 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 8777 8778 u8 dot3stats_symbol_errors_high[0x20]; 8779 8780 u8 dot3stats_symbol_errors_low[0x20]; 8781 8782 u8 dot3control_in_unknown_opcodes_high[0x20]; 8783 8784 u8 dot3control_in_unknown_opcodes_low[0x20]; 8785 8786 u8 dot3in_pause_frames_high[0x20]; 8787 8788 u8 dot3in_pause_frames_low[0x20]; 8789 8790 u8 dot3out_pause_frames_high[0x20]; 8791 8792 u8 dot3out_pause_frames_low[0x20]; 8793 8794 u8 reserved_0[0x3c0]; 8795}; 8796 8797struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 8798 u8 if_in_octets_high[0x20]; 8799 8800 u8 if_in_octets_low[0x20]; 8801 8802 u8 if_in_ucast_pkts_high[0x20]; 8803 8804 u8 if_in_ucast_pkts_low[0x20]; 8805 8806 u8 if_in_discards_high[0x20]; 8807 8808 u8 if_in_discards_low[0x20]; 8809 8810 u8 if_in_errors_high[0x20]; 8811 8812 u8 if_in_errors_low[0x20]; 8813 8814 u8 if_in_unknown_protos_high[0x20]; 8815 8816 u8 if_in_unknown_protos_low[0x20]; 8817 8818 u8 if_out_octets_high[0x20]; 8819 8820 u8 if_out_octets_low[0x20]; 8821 8822 u8 if_out_ucast_pkts_high[0x20]; 8823 8824 u8 if_out_ucast_pkts_low[0x20]; 8825 8826 u8 if_out_discards_high[0x20]; 8827 8828 u8 if_out_discards_low[0x20]; 8829 8830 u8 if_out_errors_high[0x20]; 8831 8832 u8 if_out_errors_low[0x20]; 8833 8834 u8 if_in_multicast_pkts_high[0x20]; 8835 8836 u8 if_in_multicast_pkts_low[0x20]; 8837 8838 u8 if_in_broadcast_pkts_high[0x20]; 8839 8840 u8 if_in_broadcast_pkts_low[0x20]; 8841 8842 u8 if_out_multicast_pkts_high[0x20]; 8843 8844 u8 if_out_multicast_pkts_low[0x20]; 8845 8846 u8 if_out_broadcast_pkts_high[0x20]; 8847 8848 u8 if_out_broadcast_pkts_low[0x20]; 8849 8850 u8 reserved_0[0x480]; 8851}; 8852 8853struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 8854 u8 ether_stats_drop_events_high[0x20]; 8855 8856 u8 ether_stats_drop_events_low[0x20]; 8857 8858 u8 ether_stats_octets_high[0x20]; 8859 8860 u8 ether_stats_octets_low[0x20]; 8861 8862 u8 ether_stats_pkts_high[0x20]; 8863 8864 u8 ether_stats_pkts_low[0x20]; 8865 8866 u8 ether_stats_broadcast_pkts_high[0x20]; 8867 8868 u8 ether_stats_broadcast_pkts_low[0x20]; 8869 8870 u8 ether_stats_multicast_pkts_high[0x20]; 8871 8872 u8 ether_stats_multicast_pkts_low[0x20]; 8873 8874 u8 ether_stats_crc_align_errors_high[0x20]; 8875 8876 u8 ether_stats_crc_align_errors_low[0x20]; 8877 8878 u8 ether_stats_undersize_pkts_high[0x20]; 8879 8880 u8 ether_stats_undersize_pkts_low[0x20]; 8881 8882 u8 ether_stats_oversize_pkts_high[0x20]; 8883 8884 u8 ether_stats_oversize_pkts_low[0x20]; 8885 8886 u8 ether_stats_fragments_high[0x20]; 8887 8888 u8 ether_stats_fragments_low[0x20]; 8889 8890 u8 ether_stats_jabbers_high[0x20]; 8891 8892 u8 ether_stats_jabbers_low[0x20]; 8893 8894 u8 ether_stats_collisions_high[0x20]; 8895 8896 u8 ether_stats_collisions_low[0x20]; 8897 8898 u8 ether_stats_pkts64octets_high[0x20]; 8899 8900 u8 ether_stats_pkts64octets_low[0x20]; 8901 8902 u8 ether_stats_pkts65to127octets_high[0x20]; 8903 8904 u8 ether_stats_pkts65to127octets_low[0x20]; 8905 8906 u8 ether_stats_pkts128to255octets_high[0x20]; 8907 8908 u8 ether_stats_pkts128to255octets_low[0x20]; 8909 8910 u8 ether_stats_pkts256to511octets_high[0x20]; 8911 8912 u8 ether_stats_pkts256to511octets_low[0x20]; 8913 8914 u8 ether_stats_pkts512to1023octets_high[0x20]; 8915 8916 u8 ether_stats_pkts512to1023octets_low[0x20]; 8917 8918 u8 ether_stats_pkts1024to1518octets_high[0x20]; 8919 8920 u8 ether_stats_pkts1024to1518octets_low[0x20]; 8921 8922 u8 ether_stats_pkts1519to2047octets_high[0x20]; 8923 8924 u8 ether_stats_pkts1519to2047octets_low[0x20]; 8925 8926 u8 ether_stats_pkts2048to4095octets_high[0x20]; 8927 8928 u8 ether_stats_pkts2048to4095octets_low[0x20]; 8929 8930 u8 ether_stats_pkts4096to8191octets_high[0x20]; 8931 8932 u8 ether_stats_pkts4096to8191octets_low[0x20]; 8933 8934 u8 ether_stats_pkts8192to10239octets_high[0x20]; 8935 8936 u8 ether_stats_pkts8192to10239octets_low[0x20]; 8937 8938 u8 reserved_0[0x280]; 8939}; 8940 8941struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits { 8942 u8 symbol_error_counter[0x10]; 8943 u8 link_error_recovery_counter[0x8]; 8944 u8 link_downed_counter[0x8]; 8945 8946 u8 port_rcv_errors[0x10]; 8947 u8 port_rcv_remote_physical_errors[0x10]; 8948 8949 u8 port_rcv_switch_relay_errors[0x10]; 8950 u8 port_xmit_discards[0x10]; 8951 8952 u8 port_xmit_constraint_errors[0x8]; 8953 u8 port_rcv_constraint_errors[0x8]; 8954 u8 reserved_0[0x8]; 8955 u8 local_link_integrity_errors[0x4]; 8956 u8 excessive_buffer_overrun_errors[0x4]; 8957 8958 u8 reserved_1[0x10]; 8959 u8 vl_15_dropped[0x10]; 8960 8961 u8 port_xmit_data[0x20]; 8962 8963 u8 port_rcv_data[0x20]; 8964 8965 u8 port_xmit_pkts[0x20]; 8966 8967 u8 port_rcv_pkts[0x20]; 8968 8969 u8 port_xmit_wait[0x20]; 8970 8971 u8 reserved_2[0x680]; 8972}; 8973 8974struct mlx5_ifc_trc_tlb_reg_bits { 8975 u8 reserved_0[0x80]; 8976 8977 u8 tlb_addr[0][0x40]; 8978}; 8979 8980struct mlx5_ifc_trc_read_fifo_reg_bits { 8981 u8 reserved_0[0x10]; 8982 u8 requested_event_num[0x10]; 8983 8984 u8 reserved_1[0x20]; 8985 8986 u8 reserved_2[0x10]; 8987 u8 acual_event_num[0x10]; 8988 8989 u8 reserved_3[0x20]; 8990 8991 u8 event[0][0x40]; 8992}; 8993 8994struct mlx5_ifc_trc_lock_reg_bits { 8995 u8 reserved_0[0x1f]; 8996 u8 lock[0x1]; 8997 8998 u8 reserved_1[0x60]; 8999}; 9000 9001struct mlx5_ifc_trc_filter_reg_bits { 9002 u8 status[0x1]; 9003 u8 reserved_0[0xf]; 9004 u8 filter_index[0x10]; 9005 9006 u8 reserved_1[0x20]; 9007 9008 u8 filter_val[0x20]; 9009 9010 u8 reserved_2[0x1a0]; 9011}; 9012 9013struct mlx5_ifc_trc_event_reg_bits { 9014 u8 status[0x1]; 9015 u8 reserved_0[0xf]; 9016 u8 event_index[0x10]; 9017 9018 u8 reserved_1[0x20]; 9019 9020 u8 event_id[0x20]; 9021 9022 u8 event_selector_val[0x10]; 9023 u8 event_selector_size[0x10]; 9024 9025 u8 reserved_2[0x180]; 9026}; 9027 9028struct mlx5_ifc_trc_conf_reg_bits { 9029 u8 limit_en[0x1]; 9030 u8 reserved_0[0x3]; 9031 u8 dump_mode[0x4]; 9032 u8 reserved_1[0x15]; 9033 u8 state[0x3]; 9034 9035 u8 reserved_2[0x20]; 9036 9037 u8 limit_event_index[0x20]; 9038 9039 u8 mkey[0x20]; 9040 9041 u8 fifo_ready_ev_num[0x20]; 9042 9043 u8 reserved_3[0x160]; 9044}; 9045 9046struct mlx5_ifc_trc_cap_reg_bits { 9047 u8 reserved_0[0x18]; 9048 u8 dump_mode[0x8]; 9049 9050 u8 reserved_1[0x20]; 9051 9052 u8 num_of_events[0x10]; 9053 u8 num_of_filters[0x10]; 9054 9055 u8 fifo_size[0x20]; 9056 9057 u8 tlb_size[0x10]; 9058 u8 event_size[0x10]; 9059 9060 u8 reserved_2[0x160]; 9061}; 9062 9063struct mlx5_ifc_set_node_in_bits { 9064 u8 node_description[64][0x8]; 9065}; 9066 9067struct mlx5_ifc_register_power_settings_bits { 9068 u8 reserved_0[0x18]; 9069 u8 power_settings_level[0x8]; 9070 9071 u8 reserved_1[0x60]; 9072}; 9073 9074struct mlx5_ifc_register_host_endianess_bits { 9075 u8 he[0x1]; 9076 u8 reserved_0[0x1f]; 9077 9078 u8 reserved_1[0x60]; 9079}; 9080 9081struct mlx5_ifc_register_diag_buffer_ctrl_bits { 9082 u8 physical_address[0x40]; 9083}; 9084 9085struct mlx5_ifc_qtct_reg_bits { 9086 u8 operation_type[0x2]; 9087 u8 cap_local_admin[0x1]; 9088 u8 cap_remote_admin[0x1]; 9089 u8 reserved_0[0x4]; 9090 u8 port_number[0x8]; 9091 u8 reserved_1[0xd]; 9092 u8 prio[0x3]; 9093 9094 u8 reserved_2[0x1d]; 9095 u8 tclass[0x3]; 9096}; 9097 9098struct mlx5_ifc_qpdp_reg_bits { 9099 u8 reserved_0[0x8]; 9100 u8 port_number[0x8]; 9101 u8 reserved_1[0x10]; 9102 9103 u8 reserved_2[0x1d]; 9104 u8 pprio[0x3]; 9105}; 9106 9107struct mlx5_ifc_port_info_ro_fields_param_bits { 9108 u8 reserved_0[0x8]; 9109 u8 port[0x8]; 9110 u8 max_gid[0x10]; 9111 9112 u8 reserved_1[0x20]; 9113 9114 u8 port_guid[0x40]; 9115}; 9116 9117struct mlx5_ifc_nvqc_reg_bits { 9118 u8 type[0x20]; 9119 9120 u8 reserved_0[0x18]; 9121 u8 version[0x4]; 9122 u8 reserved_1[0x2]; 9123 u8 support_wr[0x1]; 9124 u8 support_rd[0x1]; 9125}; 9126 9127struct mlx5_ifc_nvia_reg_bits { 9128 u8 reserved_0[0x1d]; 9129 u8 target[0x3]; 9130 9131 u8 reserved_1[0x20]; 9132}; 9133 9134struct mlx5_ifc_nvdi_reg_bits { 9135 struct mlx5_ifc_config_item_bits configuration_item_header; 9136}; 9137 9138struct mlx5_ifc_nvda_reg_bits { 9139 struct mlx5_ifc_config_item_bits configuration_item_header; 9140 9141 u8 configuration_item_data[0x20]; 9142}; 9143 9144struct mlx5_ifc_node_info_ro_fields_param_bits { 9145 u8 system_image_guid[0x40]; 9146 9147 u8 reserved_0[0x40]; 9148 9149 u8 node_guid[0x40]; 9150 9151 u8 reserved_1[0x10]; 9152 u8 max_pkey[0x10]; 9153 9154 u8 reserved_2[0x20]; 9155}; 9156 9157struct mlx5_ifc_ets_tcn_config_reg_bits { 9158 u8 g[0x1]; 9159 u8 b[0x1]; 9160 u8 r[0x1]; 9161 u8 reserved_0[0x9]; 9162 u8 group[0x4]; 9163 u8 reserved_1[0x9]; 9164 u8 bw_allocation[0x7]; 9165 9166 u8 reserved_2[0xc]; 9167 u8 max_bw_units[0x4]; 9168 u8 reserved_3[0x8]; 9169 u8 max_bw_value[0x8]; 9170}; 9171 9172struct mlx5_ifc_ets_global_config_reg_bits { 9173 u8 reserved_0[0x2]; 9174 u8 r[0x1]; 9175 u8 reserved_1[0x1d]; 9176 9177 u8 reserved_2[0xc]; 9178 u8 max_bw_units[0x4]; 9179 u8 reserved_3[0x8]; 9180 u8 max_bw_value[0x8]; 9181}; 9182 9183struct mlx5_ifc_qetc_reg_bits { 9184 u8 reserved_at_0[0x8]; 9185 u8 port_number[0x8]; 9186 u8 reserved_at_10[0x30]; 9187 9188 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 9189 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 9190}; 9191 9192struct mlx5_ifc_nodnic_mac_filters_bits { 9193 struct mlx5_ifc_mac_address_layout_bits mac_filter0; 9194 9195 struct mlx5_ifc_mac_address_layout_bits mac_filter1; 9196 9197 struct mlx5_ifc_mac_address_layout_bits mac_filter2; 9198 9199 struct mlx5_ifc_mac_address_layout_bits mac_filter3; 9200 9201 struct mlx5_ifc_mac_address_layout_bits mac_filter4; 9202 9203 u8 reserved_0[0xc0]; 9204}; 9205 9206struct mlx5_ifc_nodnic_gid_filters_bits { 9207 u8 mgid_filter0[16][0x8]; 9208 9209 u8 mgid_filter1[16][0x8]; 9210 9211 u8 mgid_filter2[16][0x8]; 9212 9213 u8 mgid_filter3[16][0x8]; 9214}; 9215 9216enum { 9217 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT = 0x0, 9218 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT = 0x1, 9219}; 9220 9221enum { 9222 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE = 0x0, 9223 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE = 0x1, 9224}; 9225 9226struct mlx5_ifc_nodnic_config_reg_bits { 9227 u8 no_dram_nic_revision[0x8]; 9228 u8 hardware_format[0x8]; 9229 u8 support_receive_filter[0x1]; 9230 u8 support_promisc_filter[0x1]; 9231 u8 support_promisc_multicast_filter[0x1]; 9232 u8 reserved_0[0x2]; 9233 u8 log_working_buffer_size[0x3]; 9234 u8 log_pkey_table_size[0x4]; 9235 u8 reserved_1[0x3]; 9236 u8 num_ports[0x1]; 9237 9238 u8 reserved_2[0x2]; 9239 u8 log_max_ring_size[0x6]; 9240 u8 reserved_3[0x18]; 9241 9242 u8 lkey[0x20]; 9243 9244 u8 cqe_format[0x4]; 9245 u8 reserved_4[0x1c]; 9246 9247 u8 node_guid[0x40]; 9248 9249 u8 reserved_5[0x740]; 9250 9251 struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings; 9252 9253 struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings; 9254}; 9255 9256struct mlx5_ifc_vlan_layout_bits { 9257 u8 reserved_0[0x14]; 9258 u8 vlan[0xc]; 9259 9260 u8 reserved_1[0x20]; 9261}; 9262 9263struct mlx5_ifc_umr_pointer_desc_argument_bits { 9264 u8 reserved_0[0x20]; 9265 9266 u8 mkey[0x20]; 9267 9268 u8 addressh_63_32[0x20]; 9269 9270 u8 addressl_31_0[0x20]; 9271}; 9272 9273struct mlx5_ifc_ud_adrs_vector_bits { 9274 u8 dc_key[0x40]; 9275 9276 u8 ext[0x1]; 9277 u8 reserved_0[0x7]; 9278 u8 destination_qp_dct[0x18]; 9279 9280 u8 static_rate[0x4]; 9281 u8 sl_eth_prio[0x4]; 9282 u8 fl[0x1]; 9283 u8 mlid[0x7]; 9284 u8 rlid_udp_sport[0x10]; 9285 9286 u8 reserved_1[0x20]; 9287 9288 u8 rmac_47_16[0x20]; 9289 9290 u8 rmac_15_0[0x10]; 9291 u8 tclass[0x8]; 9292 u8 hop_limit[0x8]; 9293 9294 u8 reserved_2[0x1]; 9295 u8 grh[0x1]; 9296 u8 reserved_3[0x2]; 9297 u8 src_addr_index[0x8]; 9298 u8 flow_label[0x14]; 9299 9300 u8 rgid_rip[16][0x8]; 9301}; 9302 9303struct mlx5_ifc_port_module_event_bits { 9304 u8 reserved_0[0x8]; 9305 u8 module[0x8]; 9306 u8 reserved_1[0xc]; 9307 u8 module_status[0x4]; 9308 9309 u8 reserved_2[0x14]; 9310 u8 error_type[0x4]; 9311 u8 reserved_3[0x8]; 9312 9313 u8 reserved_4[0xa0]; 9314}; 9315 9316struct mlx5_ifc_icmd_control_bits { 9317 u8 opcode[0x10]; 9318 u8 status[0x8]; 9319 u8 reserved_0[0x7]; 9320 u8 busy[0x1]; 9321}; 9322 9323struct mlx5_ifc_eqe_bits { 9324 u8 reserved_0[0x8]; 9325 u8 event_type[0x8]; 9326 u8 reserved_1[0x8]; 9327 u8 event_sub_type[0x8]; 9328 9329 u8 reserved_2[0xe0]; 9330 9331 union mlx5_ifc_event_auto_bits event_data; 9332 9333 u8 reserved_3[0x10]; 9334 u8 signature[0x8]; 9335 u8 reserved_4[0x7]; 9336 u8 owner[0x1]; 9337}; 9338 9339enum { 9340 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9341}; 9342 9343struct mlx5_ifc_cmd_queue_entry_bits { 9344 u8 type[0x8]; 9345 u8 reserved_0[0x18]; 9346 9347 u8 input_length[0x20]; 9348 9349 u8 input_mailbox_pointer_63_32[0x20]; 9350 9351 u8 input_mailbox_pointer_31_9[0x17]; 9352 u8 reserved_1[0x9]; 9353 9354 u8 command_input_inline_data[16][0x8]; 9355 9356 u8 command_output_inline_data[16][0x8]; 9357 9358 u8 output_mailbox_pointer_63_32[0x20]; 9359 9360 u8 output_mailbox_pointer_31_9[0x17]; 9361 u8 reserved_2[0x9]; 9362 9363 u8 output_length[0x20]; 9364 9365 u8 token[0x8]; 9366 u8 signature[0x8]; 9367 u8 reserved_3[0x8]; 9368 u8 status[0x7]; 9369 u8 ownership[0x1]; 9370}; 9371 9372struct mlx5_ifc_cmd_out_bits { 9373 u8 status[0x8]; 9374 u8 reserved_0[0x18]; 9375 9376 u8 syndrome[0x20]; 9377 9378 u8 command_output[0x20]; 9379}; 9380 9381struct mlx5_ifc_cmd_in_bits { 9382 u8 opcode[0x10]; 9383 u8 reserved_0[0x10]; 9384 9385 u8 reserved_1[0x10]; 9386 u8 op_mod[0x10]; 9387 9388 u8 command[0][0x20]; 9389}; 9390 9391struct mlx5_ifc_cmd_if_box_bits { 9392 u8 mailbox_data[512][0x8]; 9393 9394 u8 reserved_0[0x180]; 9395 9396 u8 next_pointer_63_32[0x20]; 9397 9398 u8 next_pointer_31_10[0x16]; 9399 u8 reserved_1[0xa]; 9400 9401 u8 block_number[0x20]; 9402 9403 u8 reserved_2[0x8]; 9404 u8 token[0x8]; 9405 u8 ctrl_signature[0x8]; 9406 u8 signature[0x8]; 9407}; 9408 9409struct mlx5_ifc_mtt_bits { 9410 u8 ptag_63_32[0x20]; 9411 9412 u8 ptag_31_8[0x18]; 9413 u8 reserved_0[0x6]; 9414 u8 wr_en[0x1]; 9415 u8 rd_en[0x1]; 9416}; 9417 9418/* Vendor Specific Capabilities, VSC */ 9419enum { 9420 MLX5_VSC_DOMAIN_ICMD = 0x1, 9421 MLX5_VSC_DOMAIN_PROTECTED_CRSPACE = 0x6, 9422 MLX5_VSC_DOMAIN_SEMAPHORES = 0xA, 9423}; 9424 9425struct mlx5_ifc_vendor_specific_cap_bits { 9426 u8 type[0x8]; 9427 u8 length[0x8]; 9428 u8 next_pointer[0x8]; 9429 u8 capability_id[0x8]; 9430 9431 u8 status[0x3]; 9432 u8 reserved_0[0xd]; 9433 u8 space[0x10]; 9434 9435 u8 counter[0x20]; 9436 9437 u8 semaphore[0x20]; 9438 9439 u8 flag[0x1]; 9440 u8 reserved_1[0x1]; 9441 u8 address[0x1e]; 9442 9443 u8 data[0x20]; 9444}; 9445 9446enum { 9447 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9448 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9449 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9450}; 9451 9452enum { 9453 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9454 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9455 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9456}; 9457 9458enum { 9459 MLX5_HEALTH_SYNDR_FW_ERR = 0x1, 9460 MLX5_HEALTH_SYNDR_IRISC_ERR = 0x7, 9461 MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR = 0x8, 9462 MLX5_HEALTH_SYNDR_CRC_ERR = 0x9, 9463 MLX5_HEALTH_SYNDR_FETCH_PCI_ERR = 0xa, 9464 MLX5_HEALTH_SYNDR_HW_FTL_ERR = 0xb, 9465 MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR = 0xc, 9466 MLX5_HEALTH_SYNDR_EQ_ERR = 0xd, 9467 MLX5_HEALTH_SYNDR_EQ_INV = 0xe, 9468 MLX5_HEALTH_SYNDR_FFSER_ERR = 0xf, 9469 MLX5_HEALTH_SYNDR_HIGH_TEMP = 0x10, 9470}; 9471 9472struct mlx5_ifc_initial_seg_bits { 9473 u8 fw_rev_minor[0x10]; 9474 u8 fw_rev_major[0x10]; 9475 9476 u8 cmd_interface_rev[0x10]; 9477 u8 fw_rev_subminor[0x10]; 9478 9479 u8 reserved_0[0x40]; 9480 9481 u8 cmdq_phy_addr_63_32[0x20]; 9482 9483 u8 cmdq_phy_addr_31_12[0x14]; 9484 u8 reserved_1[0x2]; 9485 u8 nic_interface[0x2]; 9486 u8 log_cmdq_size[0x4]; 9487 u8 log_cmdq_stride[0x4]; 9488 9489 u8 command_doorbell_vector[0x20]; 9490 9491 u8 reserved_2[0xf00]; 9492 9493 u8 initializing[0x1]; 9494 u8 reserved_3[0x4]; 9495 u8 nic_interface_supported[0x3]; 9496 u8 reserved_4[0x18]; 9497 9498 struct mlx5_ifc_health_buffer_bits health_buffer; 9499 9500 u8 no_dram_nic_offset[0x20]; 9501 9502 u8 reserved_5[0x6de0]; 9503 9504 u8 internal_timer_h[0x20]; 9505 9506 u8 internal_timer_l[0x20]; 9507 9508 u8 reserved_6[0x20]; 9509 9510 u8 reserved_7[0x1f]; 9511 u8 clear_int[0x1]; 9512 9513 u8 health_syndrome[0x8]; 9514 u8 health_counter[0x18]; 9515 9516 u8 reserved_8[0x17fc0]; 9517}; 9518 9519union mlx5_ifc_icmd_interface_document_bits { 9520 struct mlx5_ifc_fw_version_bits fw_version; 9521 struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in; 9522 struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out; 9523 struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in; 9524 struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in; 9525 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out; 9526 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out; 9527 struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general; 9528 struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in; 9529 struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out; 9530 struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out; 9531 struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in; 9532 struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in; 9533 struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out; 9534 u8 reserved_0[0x42c0]; 9535}; 9536 9537union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 9538 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9539 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9540 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9541 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9542 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9543 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 9544 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9545 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9546 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 9547 struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs; 9548 u8 reserved_0[0x7c0]; 9549}; 9550 9551struct mlx5_ifc_ppcnt_reg_bits { 9552 u8 swid[0x8]; 9553 u8 local_port[0x8]; 9554 u8 pnat[0x2]; 9555 u8 reserved_0[0x8]; 9556 u8 grp[0x6]; 9557 9558 u8 clr[0x1]; 9559 u8 reserved_1[0x1c]; 9560 u8 prio_tc[0x3]; 9561 9562 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9563}; 9564 9565struct mlx5_ifc_pcie_performance_counters_data_layout_bits { 9566 u8 life_time_counter_high[0x20]; 9567 9568 u8 life_time_counter_low[0x20]; 9569 9570 u8 rx_errors[0x20]; 9571 9572 u8 tx_errors[0x20]; 9573 9574 u8 l0_to_recovery_eieos[0x20]; 9575 9576 u8 l0_to_recovery_ts[0x20]; 9577 9578 u8 l0_to_recovery_framing[0x20]; 9579 9580 u8 l0_to_recovery_retrain[0x20]; 9581 9582 u8 crc_error_dllp[0x20]; 9583 9584 u8 crc_error_tlp[0x20]; 9585 9586 u8 reserved_0[0x680]; 9587}; 9588 9589struct mlx5_ifc_pcie_timers_and_states_data_layout_bits { 9590 u8 life_time_counter_high[0x20]; 9591 9592 u8 life_time_counter_low[0x20]; 9593 9594 u8 time_to_boot_image_start[0x20]; 9595 9596 u8 time_to_link_image[0x20]; 9597 9598 u8 calibration_time[0x20]; 9599 9600 u8 time_to_first_perst[0x20]; 9601 9602 u8 time_to_detect_state[0x20]; 9603 9604 u8 time_to_l0[0x20]; 9605 9606 u8 time_to_crs_en[0x20]; 9607 9608 u8 time_to_plastic_image_start[0x20]; 9609 9610 u8 time_to_iron_image_start[0x20]; 9611 9612 u8 perst_handler[0x20]; 9613 9614 u8 times_in_l1[0x20]; 9615 9616 u8 times_in_l23[0x20]; 9617 9618 u8 dl_down[0x20]; 9619 9620 u8 config_cycle1usec[0x20]; 9621 9622 u8 config_cycle2to7usec[0x20]; 9623 9624 u8 config_cycle8to15usec[0x20]; 9625 9626 u8 config_cycle16to63usec[0x20]; 9627 9628 u8 config_cycle64usec[0x20]; 9629 9630 u8 correctable_err_msg_sent[0x20]; 9631 9632 u8 non_fatal_err_msg_sent[0x20]; 9633 9634 u8 fatal_err_msg_sent[0x20]; 9635 9636 u8 reserved_0[0x4e0]; 9637}; 9638 9639struct mlx5_ifc_pcie_lanes_counters_data_layout_bits { 9640 u8 life_time_counter_high[0x20]; 9641 9642 u8 life_time_counter_low[0x20]; 9643 9644 u8 error_counter_lane0[0x20]; 9645 9646 u8 error_counter_lane1[0x20]; 9647 9648 u8 error_counter_lane2[0x20]; 9649 9650 u8 error_counter_lane3[0x20]; 9651 9652 u8 error_counter_lane4[0x20]; 9653 9654 u8 error_counter_lane5[0x20]; 9655 9656 u8 error_counter_lane6[0x20]; 9657 9658 u8 error_counter_lane7[0x20]; 9659 9660 u8 error_counter_lane8[0x20]; 9661 9662 u8 error_counter_lane9[0x20]; 9663 9664 u8 error_counter_lane10[0x20]; 9665 9666 u8 error_counter_lane11[0x20]; 9667 9668 u8 error_counter_lane12[0x20]; 9669 9670 u8 error_counter_lane13[0x20]; 9671 9672 u8 error_counter_lane14[0x20]; 9673 9674 u8 error_counter_lane15[0x20]; 9675 9676 u8 reserved_0[0x580]; 9677}; 9678 9679union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits { 9680 struct mlx5_ifc_pcie_performance_counters_data_layout_bits pcie_performance_counters_data_layout; 9681 struct mlx5_ifc_pcie_timers_and_states_data_layout_bits pcie_timers_and_states_data_layout; 9682 struct mlx5_ifc_pcie_lanes_counters_data_layout_bits pcie_lanes_counters_data_layout; 9683 u8 reserved_0[0xf8]; 9684}; 9685 9686struct mlx5_ifc_mpcnt_reg_bits { 9687 u8 reserved_0[0x8]; 9688 u8 pcie_index[0x8]; 9689 u8 reserved_1[0xa]; 9690 u8 grp[0x6]; 9691 9692 u8 clr[0x1]; 9693 u8 reserved_2[0x1f]; 9694 9695 union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits counter_set; 9696}; 9697 9698union mlx5_ifc_ports_control_registers_document_bits { 9699 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data; 9700 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 9701 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9702 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9703 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9704 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9705 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 9706 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9707 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9708 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout; 9709 struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout; 9710 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 9711 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date; 9712 struct mlx5_ifc_pamp_reg_bits pamp_reg; 9713 struct mlx5_ifc_paos_reg_bits paos_reg; 9714 struct mlx5_ifc_pbmc_reg_bits pbmc_reg; 9715 struct mlx5_ifc_pcap_reg_bits pcap_reg; 9716 struct mlx5_ifc_peir_reg_bits peir_reg; 9717 struct mlx5_ifc_pelc_reg_bits pelc_reg; 9718 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 9719 struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg; 9720 struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg; 9721 struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg; 9722 struct mlx5_ifc_phrr_reg_bits phrr_reg; 9723 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9724 struct mlx5_ifc_pifr_reg_bits pifr_reg; 9725 struct mlx5_ifc_pipg_reg_bits pipg_reg; 9726 struct mlx5_ifc_plbf_reg_bits plbf_reg; 9727 struct mlx5_ifc_plib_reg_bits plib_reg; 9728 struct mlx5_ifc_pll_status_data_bits pll_status_data; 9729 struct mlx5_ifc_plpc_reg_bits plpc_reg; 9730 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 9731 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 9732 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 9733 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 9734 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 9735 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 9736 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 9737 struct mlx5_ifc_ppad_reg_bits ppad_reg; 9738 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 9739 struct mlx5_ifc_ppll_reg_bits ppll_reg; 9740 struct mlx5_ifc_pplm_reg_bits pplm_reg; 9741 struct mlx5_ifc_pplr_reg_bits pplr_reg; 9742 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 9743 struct mlx5_ifc_pspa_reg_bits pspa_reg; 9744 struct mlx5_ifc_ptas_reg_bits ptas_reg; 9745 struct mlx5_ifc_ptys_reg_bits ptys_reg; 9746 struct mlx5_ifc_pude_reg_bits pude_reg; 9747 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 9748 struct mlx5_ifc_slrg_reg_bits slrg_reg; 9749 struct mlx5_ifc_slrp_reg_bits slrp_reg; 9750 struct mlx5_ifc_sltp_reg_bits sltp_reg; 9751 u8 reserved_0[0x7880]; 9752}; 9753 9754union mlx5_ifc_debug_enhancements_document_bits { 9755 struct mlx5_ifc_health_buffer_bits health_buffer; 9756 u8 reserved_0[0x200]; 9757}; 9758 9759union mlx5_ifc_no_dram_nic_document_bits { 9760 struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg; 9761 struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word; 9762 struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word; 9763 struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters; 9764 struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters; 9765 struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg; 9766 struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg; 9767 struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell; 9768 u8 reserved_0[0x3160]; 9769}; 9770 9771union mlx5_ifc_uplink_pci_interface_document_bits { 9772 struct mlx5_ifc_initial_seg_bits initial_seg; 9773 struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap; 9774 u8 reserved_0[0x20120]; 9775}; 9776 9777struct mlx5_ifc_qpdpm_dscp_reg_bits { 9778 u8 e[0x1]; 9779 u8 reserved_at_01[0x0b]; 9780 u8 prio[0x04]; 9781}; 9782 9783struct mlx5_ifc_qpdpm_reg_bits { 9784 u8 reserved_at_0[0x8]; 9785 u8 local_port[0x8]; 9786 u8 reserved_at_10[0x10]; 9787 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 9788}; 9789 9790struct mlx5_ifc_qpts_reg_bits { 9791 u8 reserved_at_0[0x8]; 9792 u8 local_port[0x8]; 9793 u8 reserved_at_10[0x2d]; 9794 u8 trust_state[0x3]; 9795}; 9796 9797#endif /* MLX5_IFC_H */ 9798