mlx5_ifc.h revision 341940
1/*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_ifc.h 341940 2018-12-12 12:26:06Z hselasky $ 26 */ 27 28#ifndef MLX5_IFC_H 29#define MLX5_IFC_H 30 31enum { 32 MLX5_EVENT_TYPE_COMP = 0x0, 33 MLX5_EVENT_TYPE_PATH_MIG = 0x1, 34 MLX5_EVENT_TYPE_COMM_EST = 0x2, 35 MLX5_EVENT_TYPE_SQ_DRAINED = 0x3, 36 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 37 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 38 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c, 39 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d, 40 MLX5_EVENT_TYPE_CQ_ERROR = 0x4, 41 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x5, 42 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x7, 43 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 44 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 45 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 46 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 47 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x8, 48 MLX5_EVENT_TYPE_PORT_CHANGE = 0x9, 49 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 50 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT = 0x16, 51 MLX5_EVENT_TYPE_CODING_TEMP_WARNING_EVENT = 0x17, 52 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 53 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT = 0x1e, 54 MLX5_EVENT_TYPE_CODING_PPS_EVENT = 0x25, 55 MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT = 0x22, 56 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 57 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 58 MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 59 MLX5_EVENT_TYPE_CMD = 0xa, 60 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 61 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd 62}; 63 64enum { 65 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 66 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 67 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 68 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3, 69 MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN = 0x4 70}; 71 72enum { 73 MLX5_MODIFY_RQT_BITMASK_RQN_LIST = 0x1, 74}; 75 76enum { 77 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 78 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 79}; 80 81enum { 82 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 83 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 84 MLX5_CMD_OP_INIT_HCA = 0x102, 85 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 86 MLX5_CMD_OP_ENABLE_HCA = 0x104, 87 MLX5_CMD_OP_DISABLE_HCA = 0x105, 88 MLX5_CMD_OP_QUERY_PAGES = 0x107, 89 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 90 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 91 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 92 MLX5_CMD_OP_SET_ISSI = 0x10b, 93 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 94 MLX5_CMD_OP_QUERY_OTHER_HCA_CAP = 0x10e, 95 MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP = 0x10f, 96 MLX5_CMD_OP_CREATE_MKEY = 0x200, 97 MLX5_CMD_OP_QUERY_MKEY = 0x201, 98 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 99 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 100 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 101 MLX5_CMD_OP_CREATE_EQ = 0x301, 102 MLX5_CMD_OP_DESTROY_EQ = 0x302, 103 MLX5_CMD_OP_QUERY_EQ = 0x303, 104 MLX5_CMD_OP_GEN_EQE = 0x304, 105 MLX5_CMD_OP_CREATE_CQ = 0x400, 106 MLX5_CMD_OP_DESTROY_CQ = 0x401, 107 MLX5_CMD_OP_QUERY_CQ = 0x402, 108 MLX5_CMD_OP_MODIFY_CQ = 0x403, 109 MLX5_CMD_OP_CREATE_QP = 0x500, 110 MLX5_CMD_OP_DESTROY_QP = 0x501, 111 MLX5_CMD_OP_RST2INIT_QP = 0x502, 112 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 113 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 114 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 115 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 116 MLX5_CMD_OP_2ERR_QP = 0x507, 117 MLX5_CMD_OP_2RST_QP = 0x50a, 118 MLX5_CMD_OP_QUERY_QP = 0x50b, 119 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 120 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 121 MLX5_CMD_OP_CREATE_PSV = 0x600, 122 MLX5_CMD_OP_DESTROY_PSV = 0x601, 123 MLX5_CMD_OP_CREATE_SRQ = 0x700, 124 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 125 MLX5_CMD_OP_QUERY_SRQ = 0x702, 126 MLX5_CMD_OP_ARM_RQ = 0x703, 127 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 128 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 129 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 130 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 131 MLX5_CMD_OP_CREATE_DCT = 0x710, 132 MLX5_CMD_OP_DESTROY_DCT = 0x711, 133 MLX5_CMD_OP_DRAIN_DCT = 0x712, 134 MLX5_CMD_OP_QUERY_DCT = 0x713, 135 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 136 MLX5_CMD_OP_SET_DC_CNAK_TRACE = 0x715, 137 MLX5_CMD_OP_QUERY_DC_CNAK_TRACE = 0x716, 138 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 139 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 140 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 141 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 142 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 143 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 144 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 145 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 146 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 147 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 148 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 149 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 150 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 151 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 152 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 153 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 154 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780, 155 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 156 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 157 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 158 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 159 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 160 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 161 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 162 MLX5_CMD_OP_ALLOC_PD = 0x800, 163 MLX5_CMD_OP_DEALLOC_PD = 0x801, 164 MLX5_CMD_OP_ALLOC_UAR = 0x802, 165 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 166 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 167 MLX5_CMD_OP_ACCESS_REG = 0x805, 168 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 169 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 170 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 171 MLX5_CMD_OP_MAD_IFC = 0x50d, 172 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 173 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 174 MLX5_CMD_OP_NOP = 0x80d, 175 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 176 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 177 MLX5_CMD_OP_SET_BURST_SIZE = 0x812, 178 MLX5_CMD_OP_QUERY_BURST_SIZE = 0x813, 179 MLX5_CMD_OP_ACTIVATE_TRACER = 0x814, 180 MLX5_CMD_OP_DEACTIVATE_TRACER = 0x815, 181 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 182 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 183 MLX5_CMD_OP_SET_DIAGNOSTICS = 0x820, 184 MLX5_CMD_OP_QUERY_DIAGNOSTICS = 0x821, 185 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 186 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 187 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 188 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 189 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 190 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 191 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 192 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 193 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 194 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 195 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 196 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 197 MLX5_CMD_OP_CREATE_LAG = 0x840, 198 MLX5_CMD_OP_MODIFY_LAG = 0x841, 199 MLX5_CMD_OP_QUERY_LAG = 0x842, 200 MLX5_CMD_OP_DESTROY_LAG = 0x843, 201 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 202 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 203 MLX5_CMD_OP_CREATE_TIR = 0x900, 204 MLX5_CMD_OP_MODIFY_TIR = 0x901, 205 MLX5_CMD_OP_DESTROY_TIR = 0x902, 206 MLX5_CMD_OP_QUERY_TIR = 0x903, 207 MLX5_CMD_OP_CREATE_SQ = 0x904, 208 MLX5_CMD_OP_MODIFY_SQ = 0x905, 209 MLX5_CMD_OP_DESTROY_SQ = 0x906, 210 MLX5_CMD_OP_QUERY_SQ = 0x907, 211 MLX5_CMD_OP_CREATE_RQ = 0x908, 212 MLX5_CMD_OP_MODIFY_RQ = 0x909, 213 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 214 MLX5_CMD_OP_QUERY_RQ = 0x90b, 215 MLX5_CMD_OP_CREATE_RMP = 0x90c, 216 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 217 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 218 MLX5_CMD_OP_QUERY_RMP = 0x90f, 219 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 220 MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS = 0x911, 221 MLX5_CMD_OP_CREATE_TIS = 0x912, 222 MLX5_CMD_OP_MODIFY_TIS = 0x913, 223 MLX5_CMD_OP_DESTROY_TIS = 0x914, 224 MLX5_CMD_OP_QUERY_TIS = 0x915, 225 MLX5_CMD_OP_CREATE_RQT = 0x916, 226 MLX5_CMD_OP_MODIFY_RQT = 0x917, 227 MLX5_CMD_OP_DESTROY_RQT = 0x918, 228 MLX5_CMD_OP_QUERY_RQT = 0x919, 229 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 230 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 231 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 232 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 233 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 234 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 235 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 236 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 237 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 238 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 239 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 240 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 241 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 242 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 243 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d, 244 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e, 245}; 246 247enum { 248 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO = 0x8007, 249 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY = 0x8400, 250 MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER = 0x9001, 251 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC = 0x9003, 252 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC = 0x9004, 253 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL = 0x9005, 254 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL = 0x9006, 255 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT = 0x9007, 256 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008, 257 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS = 0x9009, 258 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT = 0x900a, 259 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD = 0xf004 260}; 261 262struct mlx5_ifc_flow_table_fields_supported_bits { 263 u8 outer_dmac[0x1]; 264 u8 outer_smac[0x1]; 265 u8 outer_ether_type[0x1]; 266 u8 reserved_0[0x1]; 267 u8 outer_first_prio[0x1]; 268 u8 outer_first_cfi[0x1]; 269 u8 outer_first_vid[0x1]; 270 u8 reserved_1[0x1]; 271 u8 outer_second_prio[0x1]; 272 u8 outer_second_cfi[0x1]; 273 u8 outer_second_vid[0x1]; 274 u8 outer_ipv6_flow_label[0x1]; 275 u8 outer_sip[0x1]; 276 u8 outer_dip[0x1]; 277 u8 outer_frag[0x1]; 278 u8 outer_ip_protocol[0x1]; 279 u8 outer_ip_ecn[0x1]; 280 u8 outer_ip_dscp[0x1]; 281 u8 outer_udp_sport[0x1]; 282 u8 outer_udp_dport[0x1]; 283 u8 outer_tcp_sport[0x1]; 284 u8 outer_tcp_dport[0x1]; 285 u8 outer_tcp_flags[0x1]; 286 u8 outer_gre_protocol[0x1]; 287 u8 outer_gre_key[0x1]; 288 u8 outer_vxlan_vni[0x1]; 289 u8 outer_geneve_vni[0x1]; 290 u8 outer_geneve_oam[0x1]; 291 u8 outer_geneve_protocol_type[0x1]; 292 u8 outer_geneve_opt_len[0x1]; 293 u8 reserved_2[0x1]; 294 u8 source_eswitch_port[0x1]; 295 296 u8 inner_dmac[0x1]; 297 u8 inner_smac[0x1]; 298 u8 inner_ether_type[0x1]; 299 u8 reserved_3[0x1]; 300 u8 inner_first_prio[0x1]; 301 u8 inner_first_cfi[0x1]; 302 u8 inner_first_vid[0x1]; 303 u8 reserved_4[0x1]; 304 u8 inner_second_prio[0x1]; 305 u8 inner_second_cfi[0x1]; 306 u8 inner_second_vid[0x1]; 307 u8 inner_ipv6_flow_label[0x1]; 308 u8 inner_sip[0x1]; 309 u8 inner_dip[0x1]; 310 u8 inner_frag[0x1]; 311 u8 inner_ip_protocol[0x1]; 312 u8 inner_ip_ecn[0x1]; 313 u8 inner_ip_dscp[0x1]; 314 u8 inner_udp_sport[0x1]; 315 u8 inner_udp_dport[0x1]; 316 u8 inner_tcp_sport[0x1]; 317 u8 inner_tcp_dport[0x1]; 318 u8 inner_tcp_flags[0x1]; 319 u8 reserved_5[0x9]; 320 321 u8 reserved_6[0x1a]; 322 u8 bth_dst_qp[0x1]; 323 u8 reserved_7[0x4]; 324 u8 source_sqn[0x1]; 325 326 u8 reserved_8[0x20]; 327}; 328 329struct mlx5_ifc_eth_discard_cntrs_grp_bits { 330 u8 ingress_general_high[0x20]; 331 332 u8 ingress_general_low[0x20]; 333 334 u8 ingress_policy_engine_high[0x20]; 335 336 u8 ingress_policy_engine_low[0x20]; 337 338 u8 ingress_vlan_membership_high[0x20]; 339 340 u8 ingress_vlan_membership_low[0x20]; 341 342 u8 ingress_tag_frame_type_high[0x20]; 343 344 u8 ingress_tag_frame_type_low[0x20]; 345 346 u8 egress_vlan_membership_high[0x20]; 347 348 u8 egress_vlan_membership_low[0x20]; 349 350 u8 loopback_filter_high[0x20]; 351 352 u8 loopback_filter_low[0x20]; 353 354 u8 egress_general_high[0x20]; 355 356 u8 egress_general_low[0x20]; 357 358 u8 reserved_at_1c0[0x40]; 359 360 u8 egress_hoq_high[0x20]; 361 362 u8 egress_hoq_low[0x20]; 363 364 u8 port_isolation_high[0x20]; 365 366 u8 port_isolation_low[0x20]; 367 368 u8 egress_policy_engine_high[0x20]; 369 370 u8 egress_policy_engine_low[0x20]; 371 372 u8 ingress_tx_link_down_high[0x20]; 373 374 u8 ingress_tx_link_down_low[0x20]; 375 376 u8 egress_stp_filter_high[0x20]; 377 378 u8 egress_stp_filter_low[0x20]; 379 380 u8 egress_hoq_stall_high[0x20]; 381 382 u8 egress_hoq_stall_low[0x20]; 383 384 u8 reserved_at_340[0x440]; 385}; 386struct mlx5_ifc_flow_table_prop_layout_bits { 387 u8 ft_support[0x1]; 388 u8 flow_tag[0x1]; 389 u8 flow_counter[0x1]; 390 u8 flow_modify_en[0x1]; 391 u8 modify_root[0x1]; 392 u8 identified_miss_table[0x1]; 393 u8 flow_table_modify[0x1]; 394 u8 encap[0x1]; 395 u8 decap[0x1]; 396 u8 reset_root_to_default[0x1]; 397 u8 reserved_at_a[0x16]; 398 399 u8 reserved_at_20[0x2]; 400 u8 log_max_ft_size[0x6]; 401 u8 reserved_at_28[0x10]; 402 u8 max_ft_level[0x8]; 403 404 u8 reserved_at_40[0x20]; 405 406 u8 reserved_at_60[0x18]; 407 u8 log_max_ft_num[0x8]; 408 409 u8 reserved_at_80[0x10]; 410 u8 log_max_flow_counter[0x8]; 411 u8 log_max_destination[0x8]; 412 413 u8 reserved_at_a0[0x18]; 414 u8 log_max_flow[0x8]; 415 416 u8 reserved_at_c0[0x40]; 417 418 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 419 420 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 421}; 422 423struct mlx5_ifc_odp_per_transport_service_cap_bits { 424 u8 send[0x1]; 425 u8 receive[0x1]; 426 u8 write[0x1]; 427 u8 read[0x1]; 428 u8 atomic[0x1]; 429 u8 srq_receive[0x1]; 430 u8 reserved_0[0x1a]; 431}; 432 433struct mlx5_ifc_flow_counter_list_bits { 434 u8 reserved_0[0x10]; 435 u8 flow_counter_id[0x10]; 436 437 u8 reserved_1[0x20]; 438}; 439 440enum { 441 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0x0, 442 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 0x1, 443 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 0x2, 444 MLX5_FLOW_CONTEXT_DEST_TYPE_QP = 0x3, 445}; 446 447struct mlx5_ifc_dest_format_struct_bits { 448 u8 destination_type[0x8]; 449 u8 destination_id[0x18]; 450 451 u8 reserved_0[0x20]; 452}; 453 454struct mlx5_ifc_ipv4_layout_bits { 455 u8 reserved_at_0[0x60]; 456 457 u8 ipv4[0x20]; 458}; 459 460struct mlx5_ifc_ipv6_layout_bits { 461 u8 ipv6[16][0x8]; 462}; 463 464union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 465 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 466 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 467 u8 reserved_at_0[0x80]; 468}; 469 470struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 471 u8 smac_47_16[0x20]; 472 473 u8 smac_15_0[0x10]; 474 u8 ethertype[0x10]; 475 476 u8 dmac_47_16[0x20]; 477 478 u8 dmac_15_0[0x10]; 479 u8 first_prio[0x3]; 480 u8 first_cfi[0x1]; 481 u8 first_vid[0xc]; 482 483 u8 ip_protocol[0x8]; 484 u8 ip_dscp[0x6]; 485 u8 ip_ecn[0x2]; 486 u8 cvlan_tag[0x1]; 487 u8 svlan_tag[0x1]; 488 u8 frag[0x1]; 489 u8 reserved_1[0x4]; 490 u8 tcp_flags[0x9]; 491 492 u8 tcp_sport[0x10]; 493 u8 tcp_dport[0x10]; 494 495 u8 reserved_2[0x20]; 496 497 u8 udp_sport[0x10]; 498 u8 udp_dport[0x10]; 499 500 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 501 502 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 503}; 504 505struct mlx5_ifc_fte_match_set_misc_bits { 506 u8 reserved_0[0x8]; 507 u8 source_sqn[0x18]; 508 509 u8 reserved_1[0x10]; 510 u8 source_port[0x10]; 511 512 u8 outer_second_prio[0x3]; 513 u8 outer_second_cfi[0x1]; 514 u8 outer_second_vid[0xc]; 515 u8 inner_second_prio[0x3]; 516 u8 inner_second_cfi[0x1]; 517 u8 inner_second_vid[0xc]; 518 519 u8 outer_second_vlan_tag[0x1]; 520 u8 inner_second_vlan_tag[0x1]; 521 u8 reserved_2[0xe]; 522 u8 gre_protocol[0x10]; 523 524 u8 gre_key_h[0x18]; 525 u8 gre_key_l[0x8]; 526 527 u8 vxlan_vni[0x18]; 528 u8 reserved_3[0x8]; 529 530 u8 geneve_vni[0x18]; 531 u8 reserved4[0x7]; 532 u8 geneve_oam[0x1]; 533 534 u8 reserved_5[0xc]; 535 u8 outer_ipv6_flow_label[0x14]; 536 537 u8 reserved_6[0xc]; 538 u8 inner_ipv6_flow_label[0x14]; 539 540 u8 reserved_7[0xa]; 541 u8 geneve_opt_len[0x6]; 542 u8 geneve_protocol_type[0x10]; 543 544 u8 reserved_8[0x8]; 545 u8 bth_dst_qp[0x18]; 546 547 u8 reserved_9[0xa0]; 548}; 549 550struct mlx5_ifc_cmd_pas_bits { 551 u8 pa_h[0x20]; 552 553 u8 pa_l[0x14]; 554 u8 reserved_0[0xc]; 555}; 556 557struct mlx5_ifc_uint64_bits { 558 u8 hi[0x20]; 559 560 u8 lo[0x20]; 561}; 562 563struct mlx5_ifc_application_prio_entry_bits { 564 u8 reserved_0[0x8]; 565 u8 priority[0x3]; 566 u8 reserved_1[0x2]; 567 u8 sel[0x3]; 568 u8 protocol_id[0x10]; 569}; 570 571struct mlx5_ifc_nodnic_ring_doorbell_bits { 572 u8 reserved_0[0x8]; 573 u8 ring_pi[0x10]; 574 u8 reserved_1[0x8]; 575}; 576 577enum { 578 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 579 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 580 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 581 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 582 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 583 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 584 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 585 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 586 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 587 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 588}; 589 590struct mlx5_ifc_ads_bits { 591 u8 fl[0x1]; 592 u8 free_ar[0x1]; 593 u8 reserved_0[0xe]; 594 u8 pkey_index[0x10]; 595 596 u8 reserved_1[0x8]; 597 u8 grh[0x1]; 598 u8 mlid[0x7]; 599 u8 rlid[0x10]; 600 601 u8 ack_timeout[0x5]; 602 u8 reserved_2[0x3]; 603 u8 src_addr_index[0x8]; 604 u8 log_rtm[0x4]; 605 u8 stat_rate[0x4]; 606 u8 hop_limit[0x8]; 607 608 u8 reserved_3[0x4]; 609 u8 tclass[0x8]; 610 u8 flow_label[0x14]; 611 612 u8 rgid_rip[16][0x8]; 613 614 u8 reserved_4[0x4]; 615 u8 f_dscp[0x1]; 616 u8 f_ecn[0x1]; 617 u8 reserved_5[0x1]; 618 u8 f_eth_prio[0x1]; 619 u8 ecn[0x2]; 620 u8 dscp[0x6]; 621 u8 udp_sport[0x10]; 622 623 u8 dei_cfi[0x1]; 624 u8 eth_prio[0x3]; 625 u8 sl[0x4]; 626 u8 port[0x8]; 627 u8 rmac_47_32[0x10]; 628 629 u8 rmac_31_0[0x20]; 630}; 631 632struct mlx5_ifc_diagnostic_counter_cap_bits { 633 u8 sync[0x1]; 634 u8 reserved_0[0xf]; 635 u8 counter_id[0x10]; 636}; 637 638struct mlx5_ifc_debug_cap_bits { 639 u8 reserved_0[0x18]; 640 u8 log_max_samples[0x8]; 641 642 u8 single[0x1]; 643 u8 repetitive[0x1]; 644 u8 health_mon_rx_activity[0x1]; 645 u8 reserved_1[0x15]; 646 u8 log_min_sample_period[0x8]; 647 648 u8 reserved_2[0x1c0]; 649 650 struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0]; 651}; 652 653struct mlx5_ifc_qos_cap_bits { 654 u8 packet_pacing[0x1]; 655 u8 esw_scheduling[0x1]; 656 u8 esw_bw_share[0x1]; 657 u8 esw_rate_limit[0x1]; 658 u8 hll[0x1]; 659 u8 packet_pacing_burst_bound[0x1]; 660 u8 reserved_at_6[0x1a]; 661 662 u8 reserved_at_20[0x20]; 663 664 u8 packet_pacing_max_rate[0x20]; 665 666 u8 packet_pacing_min_rate[0x20]; 667 668 u8 reserved_at_80[0x10]; 669 u8 packet_pacing_rate_table_size[0x10]; 670 671 u8 esw_element_type[0x10]; 672 u8 esw_tsar_type[0x10]; 673 674 u8 reserved_at_c0[0x10]; 675 u8 max_qos_para_vport[0x10]; 676 677 u8 max_tsar_bw_share[0x20]; 678 679 u8 reserved_at_100[0x700]; 680}; 681 682struct mlx5_ifc_snapshot_cap_bits { 683 u8 reserved_0[0x1d]; 684 u8 suspend_qp_uc[0x1]; 685 u8 suspend_qp_ud[0x1]; 686 u8 suspend_qp_rc[0x1]; 687 688 u8 reserved_1[0x1c]; 689 u8 restore_pd[0x1]; 690 u8 restore_uar[0x1]; 691 u8 restore_mkey[0x1]; 692 u8 restore_qp[0x1]; 693 694 u8 reserved_2[0x1e]; 695 u8 named_mkey[0x1]; 696 u8 named_qp[0x1]; 697 698 u8 reserved_3[0x7a0]; 699}; 700 701struct mlx5_ifc_e_switch_cap_bits { 702 u8 vport_svlan_strip[0x1]; 703 u8 vport_cvlan_strip[0x1]; 704 u8 vport_svlan_insert[0x1]; 705 u8 vport_cvlan_insert_if_not_exist[0x1]; 706 u8 vport_cvlan_insert_overwrite[0x1]; 707 708 u8 reserved_0[0x19]; 709 710 u8 nic_vport_node_guid_modify[0x1]; 711 u8 nic_vport_port_guid_modify[0x1]; 712 713 u8 reserved_1[0x7e0]; 714}; 715 716struct mlx5_ifc_flow_table_eswitch_cap_bits { 717 u8 reserved_0[0x200]; 718 719 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 720 721 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 722 723 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 724 725 u8 reserved_1[0x7800]; 726}; 727 728struct mlx5_ifc_flow_table_nic_cap_bits { 729 u8 nic_rx_multi_path_tirs[0x1]; 730 u8 nic_rx_multi_path_tirs_fts[0x1]; 731 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 732 u8 reserved_at_3[0x1fd]; 733 734 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 735 736 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 737 738 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 739 740 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 741 742 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 743 744 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 745 746 u8 reserved_1[0x7200]; 747}; 748 749struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 750 u8 csum_cap[0x1]; 751 u8 vlan_cap[0x1]; 752 u8 lro_cap[0x1]; 753 u8 lro_psh_flag[0x1]; 754 u8 lro_time_stamp[0x1]; 755 u8 lro_max_msg_sz_mode[0x2]; 756 u8 wqe_vlan_insert[0x1]; 757 u8 self_lb_en_modifiable[0x1]; 758 u8 self_lb_mc[0x1]; 759 u8 self_lb_uc[0x1]; 760 u8 max_lso_cap[0x5]; 761 u8 multi_pkt_send_wqe[0x2]; 762 u8 wqe_inline_mode[0x2]; 763 u8 rss_ind_tbl_cap[0x4]; 764 u8 scatter_fcs[0x1]; 765 u8 reserved_1[0x2]; 766 u8 tunnel_lso_const_out_ip_id[0x1]; 767 u8 tunnel_lro_gre[0x1]; 768 u8 tunnel_lro_vxlan[0x1]; 769 u8 tunnel_statless_gre[0x1]; 770 u8 tunnel_stateless_vxlan[0x1]; 771 772 u8 swp[0x1]; 773 u8 swp_csum[0x1]; 774 u8 swp_lso[0x1]; 775 u8 reserved_2[0x1b]; 776 u8 max_geneve_opt_len[0x1]; 777 u8 tunnel_stateless_geneve_rx[0x1]; 778 779 u8 reserved_3[0x10]; 780 u8 lro_min_mss_size[0x10]; 781 782 u8 reserved_4[0x120]; 783 784 u8 lro_timer_supported_periods[4][0x20]; 785 786 u8 reserved_5[0x600]; 787}; 788 789enum { 790 MLX5_ROCE_CAP_L3_TYPE_GRH = 0x1, 791 MLX5_ROCE_CAP_L3_TYPE_IPV4 = 0x2, 792 MLX5_ROCE_CAP_L3_TYPE_IPV6 = 0x4, 793}; 794 795struct mlx5_ifc_roce_cap_bits { 796 u8 roce_apm[0x1]; 797 u8 rts2rts_primary_eth_prio[0x1]; 798 u8 roce_rx_allow_untagged[0x1]; 799 u8 rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1]; 800 801 u8 reserved_0[0x1c]; 802 803 u8 reserved_1[0x60]; 804 805 u8 reserved_2[0xc]; 806 u8 l3_type[0x4]; 807 u8 reserved_3[0x8]; 808 u8 roce_version[0x8]; 809 810 u8 reserved_4[0x10]; 811 u8 r_roce_dest_udp_port[0x10]; 812 813 u8 r_roce_max_src_udp_port[0x10]; 814 u8 r_roce_min_src_udp_port[0x10]; 815 816 u8 reserved_5[0x10]; 817 u8 roce_address_table_size[0x10]; 818 819 u8 reserved_6[0x700]; 820}; 821 822enum { 823 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x1, 824 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 825 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 826 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 827 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 828 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 829 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 830 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 831 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 832}; 833 834enum { 835 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 836 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 837 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 838 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 839 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 840 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 841 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 842 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 843 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 844}; 845 846struct mlx5_ifc_atomic_caps_bits { 847 u8 reserved_0[0x40]; 848 849 u8 atomic_req_8B_endianess_mode[0x2]; 850 u8 reserved_1[0x4]; 851 u8 supported_atomic_req_8B_endianess_mode_1[0x1]; 852 853 u8 reserved_2[0x19]; 854 855 u8 reserved_3[0x20]; 856 857 u8 reserved_4[0x10]; 858 u8 atomic_operations[0x10]; 859 860 u8 reserved_5[0x10]; 861 u8 atomic_size_qp[0x10]; 862 863 u8 reserved_6[0x10]; 864 u8 atomic_size_dc[0x10]; 865 866 u8 reserved_7[0x720]; 867}; 868 869struct mlx5_ifc_odp_cap_bits { 870 u8 reserved_0[0x40]; 871 872 u8 sig[0x1]; 873 u8 reserved_1[0x1f]; 874 875 u8 reserved_2[0x20]; 876 877 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 878 879 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 880 881 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 882 883 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 884 885 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 886 887 u8 reserved_3[0x6e0]; 888}; 889 890enum { 891 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 892 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 893 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 894 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 895 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 896}; 897 898enum { 899 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 900 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 901 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 902 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 903 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 904 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 905}; 906 907enum { 908 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 909 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 910}; 911 912enum { 913 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 914 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 915 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 916}; 917 918struct mlx5_ifc_cmd_hca_cap_bits { 919 u8 reserved_0[0x80]; 920 921 u8 log_max_srq_sz[0x8]; 922 u8 log_max_qp_sz[0x8]; 923 u8 reserved_1[0xb]; 924 u8 log_max_qp[0x5]; 925 926 u8 reserved_2[0xb]; 927 u8 log_max_srq[0x5]; 928 u8 reserved_3[0x10]; 929 930 u8 reserved_4[0x8]; 931 u8 log_max_cq_sz[0x8]; 932 u8 reserved_5[0xb]; 933 u8 log_max_cq[0x5]; 934 935 u8 log_max_eq_sz[0x8]; 936 u8 relaxed_ordering_write[1]; 937 u8 reserved_6[0x1]; 938 u8 log_max_mkey[0x6]; 939 u8 reserved_7[0xc]; 940 u8 log_max_eq[0x4]; 941 942 u8 max_indirection[0x8]; 943 u8 reserved_8[0x1]; 944 u8 log_max_mrw_sz[0x7]; 945 u8 force_teardown[0x1]; 946 u8 reserved_9[0x1]; 947 u8 log_max_bsf_list_size[0x6]; 948 u8 reserved_10[0x2]; 949 u8 log_max_klm_list_size[0x6]; 950 951 u8 reserved_11[0xa]; 952 u8 log_max_ra_req_dc[0x6]; 953 u8 reserved_12[0xa]; 954 u8 log_max_ra_res_dc[0x6]; 955 956 u8 reserved_13[0xa]; 957 u8 log_max_ra_req_qp[0x6]; 958 u8 reserved_14[0xa]; 959 u8 log_max_ra_res_qp[0x6]; 960 961 u8 pad_cap[0x1]; 962 u8 cc_query_allowed[0x1]; 963 u8 cc_modify_allowed[0x1]; 964 u8 start_pad[0x1]; 965 u8 cache_line_128byte[0x1]; 966 u8 reserved_at_165[0xa]; 967 u8 qcam_reg[0x1]; 968 u8 gid_table_size[0x10]; 969 970 u8 out_of_seq_cnt[0x1]; 971 u8 vport_counters[0x1]; 972 u8 retransmission_q_counters[0x1]; 973 u8 debug[0x1]; 974 u8 modify_rq_counters_set_id[0x1]; 975 u8 rq_delay_drop[0x1]; 976 u8 max_qp_cnt[0xa]; 977 u8 pkey_table_size[0x10]; 978 979 u8 vport_group_manager[0x1]; 980 u8 vhca_group_manager[0x1]; 981 u8 ib_virt[0x1]; 982 u8 eth_virt[0x1]; 983 u8 reserved_17[0x1]; 984 u8 ets[0x1]; 985 u8 nic_flow_table[0x1]; 986 u8 eswitch_flow_table[0x1]; 987 u8 reserved_18[0x3]; 988 u8 local_ca_ack_delay[0x5]; 989 u8 port_module_event[0x1]; 990 u8 reserved_19[0x5]; 991 u8 port_type[0x2]; 992 u8 num_ports[0x8]; 993 994 u8 snapshot[0x1]; 995 u8 reserved_20[0x2]; 996 u8 log_max_msg[0x5]; 997 u8 reserved_21[0x4]; 998 u8 max_tc[0x4]; 999 u8 temp_warn_event[0x1]; 1000 u8 dcbx[0x1]; 1001 u8 reserved_22[0x4]; 1002 u8 rol_s[0x1]; 1003 u8 rol_g[0x1]; 1004 u8 reserved_23[0x1]; 1005 u8 wol_s[0x1]; 1006 u8 wol_g[0x1]; 1007 u8 wol_a[0x1]; 1008 u8 wol_b[0x1]; 1009 u8 wol_m[0x1]; 1010 u8 wol_u[0x1]; 1011 u8 wol_p[0x1]; 1012 1013 u8 stat_rate_support[0x10]; 1014 u8 reserved_24[0xc]; 1015 u8 cqe_version[0x4]; 1016 1017 u8 compact_address_vector[0x1]; 1018 u8 striding_rq[0x1]; 1019 u8 reserved_25[0x1]; 1020 u8 ipoib_enhanced_offloads[0x1]; 1021 u8 ipoib_ipoib_offloads[0x1]; 1022 u8 reserved_26[0x8]; 1023 u8 dc_connect_qp[0x1]; 1024 u8 dc_cnak_trace[0x1]; 1025 u8 drain_sigerr[0x1]; 1026 u8 cmdif_checksum[0x2]; 1027 u8 sigerr_cqe[0x1]; 1028 u8 reserved_27[0x1]; 1029 u8 wq_signature[0x1]; 1030 u8 sctr_data_cqe[0x1]; 1031 u8 reserved_28[0x1]; 1032 u8 sho[0x1]; 1033 u8 tph[0x1]; 1034 u8 rf[0x1]; 1035 u8 dct[0x1]; 1036 u8 qos[0x1]; 1037 u8 eth_net_offloads[0x1]; 1038 u8 roce[0x1]; 1039 u8 atomic[0x1]; 1040 u8 reserved_30[0x1]; 1041 1042 u8 cq_oi[0x1]; 1043 u8 cq_resize[0x1]; 1044 u8 cq_moderation[0x1]; 1045 u8 cq_period_mode_modify[0x1]; 1046 u8 cq_invalidate[0x1]; 1047 u8 reserved_at_225[0x1]; 1048 u8 cq_eq_remap[0x1]; 1049 u8 pg[0x1]; 1050 u8 block_lb_mc[0x1]; 1051 u8 exponential_backoff[0x1]; 1052 u8 scqe_break_moderation[0x1]; 1053 u8 cq_period_start_from_cqe[0x1]; 1054 u8 cd[0x1]; 1055 u8 atm[0x1]; 1056 u8 apm[0x1]; 1057 u8 imaicl[0x1]; 1058 u8 reserved_32[0x6]; 1059 u8 qkv[0x1]; 1060 u8 pkv[0x1]; 1061 u8 set_deth_sqpn[0x1]; 1062 u8 reserved_33[0x3]; 1063 u8 xrc[0x1]; 1064 u8 ud[0x1]; 1065 u8 uc[0x1]; 1066 u8 rc[0x1]; 1067 1068 u8 reserved_34[0xa]; 1069 u8 uar_sz[0x6]; 1070 u8 reserved_35[0x8]; 1071 u8 log_pg_sz[0x8]; 1072 1073 u8 bf[0x1]; 1074 u8 driver_version[0x1]; 1075 u8 pad_tx_eth_packet[0x1]; 1076 u8 reserved_36[0x8]; 1077 u8 log_bf_reg_size[0x5]; 1078 u8 reserved_37[0x10]; 1079 1080 u8 num_of_diagnostic_counters[0x10]; 1081 u8 max_wqe_sz_sq[0x10]; 1082 1083 u8 reserved_38[0x10]; 1084 u8 max_wqe_sz_rq[0x10]; 1085 1086 u8 reserved_39[0x10]; 1087 u8 max_wqe_sz_sq_dc[0x10]; 1088 1089 u8 reserved_40[0x7]; 1090 u8 max_qp_mcg[0x19]; 1091 1092 u8 reserved_41[0x18]; 1093 u8 log_max_mcg[0x8]; 1094 1095 u8 reserved_42[0x3]; 1096 u8 log_max_transport_domain[0x5]; 1097 u8 reserved_43[0x3]; 1098 u8 log_max_pd[0x5]; 1099 u8 reserved_44[0xb]; 1100 u8 log_max_xrcd[0x5]; 1101 1102 u8 reserved_45[0x10]; 1103 u8 max_flow_counter[0x10]; 1104 1105 u8 reserved_46[0x3]; 1106 u8 log_max_rq[0x5]; 1107 u8 reserved_47[0x3]; 1108 u8 log_max_sq[0x5]; 1109 u8 reserved_48[0x3]; 1110 u8 log_max_tir[0x5]; 1111 u8 reserved_49[0x3]; 1112 u8 log_max_tis[0x5]; 1113 1114 u8 basic_cyclic_rcv_wqe[0x1]; 1115 u8 reserved_50[0x2]; 1116 u8 log_max_rmp[0x5]; 1117 u8 reserved_51[0x3]; 1118 u8 log_max_rqt[0x5]; 1119 u8 reserved_52[0x3]; 1120 u8 log_max_rqt_size[0x5]; 1121 u8 reserved_53[0x3]; 1122 u8 log_max_tis_per_sq[0x5]; 1123 1124 u8 reserved_54[0x3]; 1125 u8 log_max_stride_sz_rq[0x5]; 1126 u8 reserved_55[0x3]; 1127 u8 log_min_stride_sz_rq[0x5]; 1128 u8 reserved_56[0x3]; 1129 u8 log_max_stride_sz_sq[0x5]; 1130 u8 reserved_57[0x3]; 1131 u8 log_min_stride_sz_sq[0x5]; 1132 1133 u8 reserved_58[0x1b]; 1134 u8 log_max_wq_sz[0x5]; 1135 1136 u8 nic_vport_change_event[0x1]; 1137 u8 disable_local_lb[0x1]; 1138 u8 reserved_59[0x9]; 1139 u8 log_max_vlan_list[0x5]; 1140 u8 reserved_60[0x3]; 1141 u8 log_max_current_mc_list[0x5]; 1142 u8 reserved_61[0x3]; 1143 u8 log_max_current_uc_list[0x5]; 1144 1145 u8 reserved_62[0x80]; 1146 1147 u8 reserved_63[0x3]; 1148 u8 log_max_l2_table[0x5]; 1149 u8 reserved_64[0x8]; 1150 u8 log_uar_page_sz[0x10]; 1151 1152 u8 reserved_65[0x20]; 1153 1154 u8 device_frequency_mhz[0x20]; 1155 1156 u8 device_frequency_khz[0x20]; 1157 1158 u8 reserved_66[0x80]; 1159 1160 u8 log_max_atomic_size_qp[0x8]; 1161 u8 reserved_67[0x10]; 1162 u8 log_max_atomic_size_dc[0x8]; 1163 1164 u8 reserved_68[0x1f]; 1165 u8 cqe_compression[0x1]; 1166 1167 u8 cqe_compression_timeout[0x10]; 1168 u8 cqe_compression_max_num[0x10]; 1169 1170 u8 reserved_69[0x220]; 1171}; 1172 1173enum mlx5_flow_destination_type { 1174 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1175 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1176 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1177}; 1178 1179union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1180 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1181 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1182 u8 reserved_0[0x40]; 1183}; 1184 1185struct mlx5_ifc_fte_match_param_bits { 1186 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1187 1188 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1189 1190 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1191 1192 u8 reserved_0[0xa00]; 1193}; 1194 1195enum { 1196 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1197 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1198 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1199 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1200 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1201}; 1202 1203struct mlx5_ifc_rx_hash_field_select_bits { 1204 u8 l3_prot_type[0x1]; 1205 u8 l4_prot_type[0x1]; 1206 u8 selected_fields[0x1e]; 1207}; 1208 1209enum { 1210 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1211 MLX5_WQ_TYPE_CYCLIC = 0x1, 1212 MLX5_WQ_TYPE_STRQ_LINKED_LIST = 0x2, 1213 MLX5_WQ_TYPE_STRQ_CYCLIC = 0x3, 1214}; 1215 1216enum rq_type { 1217 RQ_TYPE_NONE, 1218 RQ_TYPE_STRIDE, 1219}; 1220 1221enum { 1222 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1223 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1224}; 1225 1226struct mlx5_ifc_wq_bits { 1227 u8 wq_type[0x4]; 1228 u8 wq_signature[0x1]; 1229 u8 end_padding_mode[0x2]; 1230 u8 cd_slave[0x1]; 1231 u8 reserved_0[0x18]; 1232 1233 u8 hds_skip_first_sge[0x1]; 1234 u8 log2_hds_buf_size[0x3]; 1235 u8 reserved_1[0x7]; 1236 u8 page_offset[0x5]; 1237 u8 lwm[0x10]; 1238 1239 u8 reserved_2[0x8]; 1240 u8 pd[0x18]; 1241 1242 u8 reserved_3[0x8]; 1243 u8 uar_page[0x18]; 1244 1245 u8 dbr_addr[0x40]; 1246 1247 u8 hw_counter[0x20]; 1248 1249 u8 sw_counter[0x20]; 1250 1251 u8 reserved_4[0xc]; 1252 u8 log_wq_stride[0x4]; 1253 u8 reserved_5[0x3]; 1254 u8 log_wq_pg_sz[0x5]; 1255 u8 reserved_6[0x3]; 1256 u8 log_wq_sz[0x5]; 1257 1258 u8 reserved_7[0x15]; 1259 u8 single_wqe_log_num_of_strides[0x3]; 1260 u8 two_byte_shift_en[0x1]; 1261 u8 reserved_8[0x4]; 1262 u8 single_stride_log_num_of_bytes[0x3]; 1263 1264 u8 reserved_9[0x4c0]; 1265 1266 struct mlx5_ifc_cmd_pas_bits pas[0]; 1267}; 1268 1269struct mlx5_ifc_rq_num_bits { 1270 u8 reserved_0[0x8]; 1271 u8 rq_num[0x18]; 1272}; 1273 1274struct mlx5_ifc_mac_address_layout_bits { 1275 u8 reserved_0[0x10]; 1276 u8 mac_addr_47_32[0x10]; 1277 1278 u8 mac_addr_31_0[0x20]; 1279}; 1280 1281struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1282 u8 reserved_0[0xa0]; 1283 1284 u8 min_time_between_cnps[0x20]; 1285 1286 u8 reserved_1[0x12]; 1287 u8 cnp_dscp[0x6]; 1288 u8 reserved_2[0x4]; 1289 u8 cnp_prio_mode[0x1]; 1290 u8 cnp_802p_prio[0x3]; 1291 1292 u8 reserved_3[0x720]; 1293}; 1294 1295struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1296 u8 reserved_0[0x60]; 1297 1298 u8 reserved_1[0x4]; 1299 u8 clamp_tgt_rate[0x1]; 1300 u8 reserved_2[0x3]; 1301 u8 clamp_tgt_rate_after_time_inc[0x1]; 1302 u8 reserved_3[0x17]; 1303 1304 u8 reserved_4[0x20]; 1305 1306 u8 rpg_time_reset[0x20]; 1307 1308 u8 rpg_byte_reset[0x20]; 1309 1310 u8 rpg_threshold[0x20]; 1311 1312 u8 rpg_max_rate[0x20]; 1313 1314 u8 rpg_ai_rate[0x20]; 1315 1316 u8 rpg_hai_rate[0x20]; 1317 1318 u8 rpg_gd[0x20]; 1319 1320 u8 rpg_min_dec_fac[0x20]; 1321 1322 u8 rpg_min_rate[0x20]; 1323 1324 u8 reserved_5[0xe0]; 1325 1326 u8 rate_to_set_on_first_cnp[0x20]; 1327 1328 u8 dce_tcp_g[0x20]; 1329 1330 u8 dce_tcp_rtt[0x20]; 1331 1332 u8 rate_reduce_monitor_period[0x20]; 1333 1334 u8 reserved_6[0x20]; 1335 1336 u8 initial_alpha_value[0x20]; 1337 1338 u8 reserved_7[0x4a0]; 1339}; 1340 1341struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1342 u8 reserved_0[0x80]; 1343 1344 u8 rppp_max_rps[0x20]; 1345 1346 u8 rpg_time_reset[0x20]; 1347 1348 u8 rpg_byte_reset[0x20]; 1349 1350 u8 rpg_threshold[0x20]; 1351 1352 u8 rpg_max_rate[0x20]; 1353 1354 u8 rpg_ai_rate[0x20]; 1355 1356 u8 rpg_hai_rate[0x20]; 1357 1358 u8 rpg_gd[0x20]; 1359 1360 u8 rpg_min_dec_fac[0x20]; 1361 1362 u8 rpg_min_rate[0x20]; 1363 1364 u8 reserved_1[0x640]; 1365}; 1366 1367enum { 1368 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1369 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1370 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1371}; 1372 1373struct mlx5_ifc_resize_field_select_bits { 1374 u8 resize_field_select[0x20]; 1375}; 1376 1377enum { 1378 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1379 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1380 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1381 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1382 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE = 0x10, 1383 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS = 0x20, 1384}; 1385 1386struct mlx5_ifc_modify_field_select_bits { 1387 u8 modify_field_select[0x20]; 1388}; 1389 1390struct mlx5_ifc_field_select_r_roce_np_bits { 1391 u8 field_select_r_roce_np[0x20]; 1392}; 1393 1394enum { 1395 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE = 0x2, 1396 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC = 0x4, 1397 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET = 0x8, 1398 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET = 0x10, 1399 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD = 0x20, 1400 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE = 0x40, 1401 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE = 0x80, 1402 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE = 0x100, 1403 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC = 0x200, 1404 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE = 0x400, 1405 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP = 0x800, 1406 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G = 0x1000, 1407 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT = 0x2000, 1408 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD = 0x4000, 1409 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE = 0x8000, 1410}; 1411 1412struct mlx5_ifc_field_select_r_roce_rp_bits { 1413 u8 field_select_r_roce_rp[0x20]; 1414}; 1415 1416enum { 1417 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1418 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1419 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1420 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1421 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1422 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1423 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1424 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1425 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1426 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1427}; 1428 1429struct mlx5_ifc_field_select_802_1qau_rp_bits { 1430 u8 field_select_8021qaurp[0x20]; 1431}; 1432 1433struct mlx5_ifc_pptb_reg_bits { 1434 u8 reserved_0[0x2]; 1435 u8 mm[0x2]; 1436 u8 reserved_1[0x4]; 1437 u8 local_port[0x8]; 1438 u8 reserved_2[0x6]; 1439 u8 cm[0x1]; 1440 u8 um[0x1]; 1441 u8 pm[0x8]; 1442 1443 u8 prio7buff[0x4]; 1444 u8 prio6buff[0x4]; 1445 u8 prio5buff[0x4]; 1446 u8 prio4buff[0x4]; 1447 u8 prio3buff[0x4]; 1448 u8 prio2buff[0x4]; 1449 u8 prio1buff[0x4]; 1450 u8 prio0buff[0x4]; 1451 1452 u8 pm_msb[0x8]; 1453 u8 reserved_3[0x10]; 1454 u8 ctrl_buff[0x4]; 1455 u8 untagged_buff[0x4]; 1456}; 1457 1458struct mlx5_ifc_dcbx_app_reg_bits { 1459 u8 reserved_0[0x8]; 1460 u8 port_number[0x8]; 1461 u8 reserved_1[0x10]; 1462 1463 u8 reserved_2[0x1a]; 1464 u8 num_app_prio[0x6]; 1465 1466 u8 reserved_3[0x40]; 1467 1468 struct mlx5_ifc_application_prio_entry_bits app_prio[0]; 1469}; 1470 1471struct mlx5_ifc_dcbx_param_reg_bits { 1472 u8 dcbx_cee_cap[0x1]; 1473 u8 dcbx_ieee_cap[0x1]; 1474 u8 dcbx_standby_cap[0x1]; 1475 u8 reserved_0[0x5]; 1476 u8 port_number[0x8]; 1477 u8 reserved_1[0xa]; 1478 u8 max_application_table_size[0x6]; 1479 1480 u8 reserved_2[0x15]; 1481 u8 version_oper[0x3]; 1482 u8 reserved_3[0x5]; 1483 u8 version_admin[0x3]; 1484 1485 u8 willing_admin[0x1]; 1486 u8 reserved_4[0x3]; 1487 u8 pfc_cap_oper[0x4]; 1488 u8 reserved_5[0x4]; 1489 u8 pfc_cap_admin[0x4]; 1490 u8 reserved_6[0x4]; 1491 u8 num_of_tc_oper[0x4]; 1492 u8 reserved_7[0x4]; 1493 u8 num_of_tc_admin[0x4]; 1494 1495 u8 remote_willing[0x1]; 1496 u8 reserved_8[0x3]; 1497 u8 remote_pfc_cap[0x4]; 1498 u8 reserved_9[0x14]; 1499 u8 remote_num_of_tc[0x4]; 1500 1501 u8 reserved_10[0x18]; 1502 u8 error[0x8]; 1503 1504 u8 reserved_11[0x160]; 1505}; 1506 1507struct mlx5_ifc_qhll_bits { 1508 u8 reserved_at_0[0x8]; 1509 u8 local_port[0x8]; 1510 u8 reserved_at_10[0x10]; 1511 1512 u8 reserved_at_20[0x1b]; 1513 u8 hll_time[0x5]; 1514 1515 u8 stall_en[0x1]; 1516 u8 reserved_at_41[0x1c]; 1517 u8 stall_cnt[0x3]; 1518}; 1519 1520struct mlx5_ifc_qetcr_reg_bits { 1521 u8 operation_type[0x2]; 1522 u8 cap_local_admin[0x1]; 1523 u8 cap_remote_admin[0x1]; 1524 u8 reserved_0[0x4]; 1525 u8 port_number[0x8]; 1526 u8 reserved_1[0x10]; 1527 1528 u8 reserved_2[0x20]; 1529 1530 u8 tc[8][0x40]; 1531 1532 u8 global_configuration[0x40]; 1533}; 1534 1535struct mlx5_ifc_nodnic_ring_config_reg_bits { 1536 u8 queue_address_63_32[0x20]; 1537 1538 u8 queue_address_31_12[0x14]; 1539 u8 reserved_0[0x6]; 1540 u8 log_size[0x6]; 1541 1542 struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell; 1543 1544 u8 reserved_1[0x8]; 1545 u8 queue_number[0x18]; 1546 1547 u8 q_key[0x20]; 1548 1549 u8 reserved_2[0x10]; 1550 u8 pkey_index[0x10]; 1551 1552 u8 reserved_3[0x40]; 1553}; 1554 1555struct mlx5_ifc_nodnic_cq_arming_word_bits { 1556 u8 reserved_0[0x8]; 1557 u8 cq_ci[0x10]; 1558 u8 reserved_1[0x8]; 1559}; 1560 1561enum { 1562 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND = 0x0, 1563 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET = 0x1, 1564}; 1565 1566enum { 1567 MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN = 0x0, 1568 MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE = 0x1, 1569 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED = 0x2, 1570 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE = 0x3, 1571}; 1572 1573struct mlx5_ifc_nodnic_event_word_bits { 1574 u8 driver_reset_needed[0x1]; 1575 u8 port_management_change_event[0x1]; 1576 u8 reserved_0[0x19]; 1577 u8 link_type[0x1]; 1578 u8 port_state[0x4]; 1579}; 1580 1581struct mlx5_ifc_nic_vport_change_event_bits { 1582 u8 reserved_0[0x10]; 1583 u8 vport_num[0x10]; 1584 1585 u8 reserved_1[0xc0]; 1586}; 1587 1588struct mlx5_ifc_pages_req_event_bits { 1589 u8 reserved_0[0x10]; 1590 u8 function_id[0x10]; 1591 1592 u8 num_pages[0x20]; 1593 1594 u8 reserved_1[0xa0]; 1595}; 1596 1597struct mlx5_ifc_cmd_inter_comp_event_bits { 1598 u8 command_completion_vector[0x20]; 1599 1600 u8 reserved_0[0xc0]; 1601}; 1602 1603struct mlx5_ifc_stall_vl_event_bits { 1604 u8 reserved_0[0x18]; 1605 u8 port_num[0x1]; 1606 u8 reserved_1[0x3]; 1607 u8 vl[0x4]; 1608 1609 u8 reserved_2[0xa0]; 1610}; 1611 1612struct mlx5_ifc_db_bf_congestion_event_bits { 1613 u8 event_subtype[0x8]; 1614 u8 reserved_0[0x8]; 1615 u8 congestion_level[0x8]; 1616 u8 reserved_1[0x8]; 1617 1618 u8 reserved_2[0xa0]; 1619}; 1620 1621struct mlx5_ifc_gpio_event_bits { 1622 u8 reserved_0[0x60]; 1623 1624 u8 gpio_event_hi[0x20]; 1625 1626 u8 gpio_event_lo[0x20]; 1627 1628 u8 reserved_1[0x40]; 1629}; 1630 1631struct mlx5_ifc_port_state_change_event_bits { 1632 u8 reserved_0[0x40]; 1633 1634 u8 port_num[0x4]; 1635 u8 reserved_1[0x1c]; 1636 1637 u8 reserved_2[0x80]; 1638}; 1639 1640struct mlx5_ifc_dropped_packet_logged_bits { 1641 u8 reserved_0[0xe0]; 1642}; 1643 1644enum { 1645 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 1646 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 1647}; 1648 1649struct mlx5_ifc_cq_error_bits { 1650 u8 reserved_0[0x8]; 1651 u8 cqn[0x18]; 1652 1653 u8 reserved_1[0x20]; 1654 1655 u8 reserved_2[0x18]; 1656 u8 syndrome[0x8]; 1657 1658 u8 reserved_3[0x80]; 1659}; 1660 1661struct mlx5_ifc_rdma_page_fault_event_bits { 1662 u8 bytes_commited[0x20]; 1663 1664 u8 r_key[0x20]; 1665 1666 u8 reserved_0[0x10]; 1667 u8 packet_len[0x10]; 1668 1669 u8 rdma_op_len[0x20]; 1670 1671 u8 rdma_va[0x40]; 1672 1673 u8 reserved_1[0x5]; 1674 u8 rdma[0x1]; 1675 u8 write[0x1]; 1676 u8 requestor[0x1]; 1677 u8 qp_number[0x18]; 1678}; 1679 1680struct mlx5_ifc_wqe_associated_page_fault_event_bits { 1681 u8 bytes_committed[0x20]; 1682 1683 u8 reserved_0[0x10]; 1684 u8 wqe_index[0x10]; 1685 1686 u8 reserved_1[0x10]; 1687 u8 len[0x10]; 1688 1689 u8 reserved_2[0x60]; 1690 1691 u8 reserved_3[0x5]; 1692 u8 rdma[0x1]; 1693 u8 write_read[0x1]; 1694 u8 requestor[0x1]; 1695 u8 qpn[0x18]; 1696}; 1697 1698enum { 1699 MLX5_QP_EVENTS_TYPE_QP = 0x0, 1700 MLX5_QP_EVENTS_TYPE_RQ = 0x1, 1701 MLX5_QP_EVENTS_TYPE_SQ = 0x2, 1702}; 1703 1704struct mlx5_ifc_qp_events_bits { 1705 u8 reserved_0[0xa0]; 1706 1707 u8 type[0x8]; 1708 u8 reserved_1[0x18]; 1709 1710 u8 reserved_2[0x8]; 1711 u8 qpn_rqn_sqn[0x18]; 1712}; 1713 1714struct mlx5_ifc_dct_events_bits { 1715 u8 reserved_0[0xc0]; 1716 1717 u8 reserved_1[0x8]; 1718 u8 dct_number[0x18]; 1719}; 1720 1721struct mlx5_ifc_comp_event_bits { 1722 u8 reserved_0[0xc0]; 1723 1724 u8 reserved_1[0x8]; 1725 u8 cq_number[0x18]; 1726}; 1727 1728struct mlx5_ifc_fw_version_bits { 1729 u8 major[0x10]; 1730 u8 reserved_0[0x10]; 1731 1732 u8 minor[0x10]; 1733 u8 subminor[0x10]; 1734 1735 u8 second[0x8]; 1736 u8 minute[0x8]; 1737 u8 hour[0x8]; 1738 u8 reserved_1[0x8]; 1739 1740 u8 year[0x10]; 1741 u8 month[0x8]; 1742 u8 day[0x8]; 1743}; 1744 1745enum { 1746 MLX5_QPC_STATE_RST = 0x0, 1747 MLX5_QPC_STATE_INIT = 0x1, 1748 MLX5_QPC_STATE_RTR = 0x2, 1749 MLX5_QPC_STATE_RTS = 0x3, 1750 MLX5_QPC_STATE_SQER = 0x4, 1751 MLX5_QPC_STATE_SQD = 0x5, 1752 MLX5_QPC_STATE_ERR = 0x6, 1753 MLX5_QPC_STATE_SUSPENDED = 0x9, 1754}; 1755 1756enum { 1757 MLX5_QPC_ST_RC = 0x0, 1758 MLX5_QPC_ST_UC = 0x1, 1759 MLX5_QPC_ST_UD = 0x2, 1760 MLX5_QPC_ST_XRC = 0x3, 1761 MLX5_QPC_ST_DCI = 0x5, 1762 MLX5_QPC_ST_QP0 = 0x7, 1763 MLX5_QPC_ST_QP1 = 0x8, 1764 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 1765 MLX5_QPC_ST_REG_UMR = 0xc, 1766}; 1767 1768enum { 1769 MLX5_QP_PM_ARMED = 0x0, 1770 MLX5_QP_PM_REARM = 0x1, 1771 MLX5_QPC_PM_STATE_RESERVED = 0x2, 1772 MLX5_QP_PM_MIGRATED = 0x3, 1773}; 1774 1775enum { 1776 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 1777 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 1778}; 1779 1780enum { 1781 MLX5_QPC_MTU_256_BYTES = 0x1, 1782 MLX5_QPC_MTU_512_BYTES = 0x2, 1783 MLX5_QPC_MTU_1K_BYTES = 0x3, 1784 MLX5_QPC_MTU_2K_BYTES = 0x4, 1785 MLX5_QPC_MTU_4K_BYTES = 0x5, 1786 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 1787}; 1788 1789enum { 1790 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 1791 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 1792 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 1793 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 1794 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 1795 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 1796 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 1797 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 1798}; 1799 1800enum { 1801 MLX5_QPC_CS_REQ_DISABLE = 0x0, 1802 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 1803 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 1804}; 1805 1806enum { 1807 MLX5_QPC_CS_RES_DISABLE = 0x0, 1808 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 1809 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 1810}; 1811 1812struct mlx5_ifc_qpc_bits { 1813 u8 state[0x4]; 1814 u8 lag_tx_port_affinity[0x4]; 1815 u8 st[0x8]; 1816 u8 reserved_1[0x3]; 1817 u8 pm_state[0x2]; 1818 u8 reserved_2[0x7]; 1819 u8 end_padding_mode[0x2]; 1820 u8 reserved_3[0x2]; 1821 1822 u8 wq_signature[0x1]; 1823 u8 block_lb_mc[0x1]; 1824 u8 atomic_like_write_en[0x1]; 1825 u8 latency_sensitive[0x1]; 1826 u8 reserved_4[0x1]; 1827 u8 drain_sigerr[0x1]; 1828 u8 reserved_5[0x2]; 1829 u8 pd[0x18]; 1830 1831 u8 mtu[0x3]; 1832 u8 log_msg_max[0x5]; 1833 u8 reserved_6[0x1]; 1834 u8 log_rq_size[0x4]; 1835 u8 log_rq_stride[0x3]; 1836 u8 no_sq[0x1]; 1837 u8 log_sq_size[0x4]; 1838 u8 reserved_7[0x6]; 1839 u8 rlky[0x1]; 1840 u8 ulp_stateless_offload_mode[0x4]; 1841 1842 u8 counter_set_id[0x8]; 1843 u8 uar_page[0x18]; 1844 1845 u8 reserved_8[0x8]; 1846 u8 user_index[0x18]; 1847 1848 u8 reserved_9[0x3]; 1849 u8 log_page_size[0x5]; 1850 u8 remote_qpn[0x18]; 1851 1852 struct mlx5_ifc_ads_bits primary_address_path; 1853 1854 struct mlx5_ifc_ads_bits secondary_address_path; 1855 1856 u8 log_ack_req_freq[0x4]; 1857 u8 reserved_10[0x4]; 1858 u8 log_sra_max[0x3]; 1859 u8 reserved_11[0x2]; 1860 u8 retry_count[0x3]; 1861 u8 rnr_retry[0x3]; 1862 u8 reserved_12[0x1]; 1863 u8 fre[0x1]; 1864 u8 cur_rnr_retry[0x3]; 1865 u8 cur_retry_count[0x3]; 1866 u8 reserved_13[0x5]; 1867 1868 u8 reserved_14[0x20]; 1869 1870 u8 reserved_15[0x8]; 1871 u8 next_send_psn[0x18]; 1872 1873 u8 reserved_16[0x8]; 1874 u8 cqn_snd[0x18]; 1875 1876 u8 reserved_at_400[0x8]; 1877 1878 u8 deth_sqpn[0x18]; 1879 u8 reserved_17[0x20]; 1880 1881 u8 reserved_18[0x8]; 1882 u8 last_acked_psn[0x18]; 1883 1884 u8 reserved_19[0x8]; 1885 u8 ssn[0x18]; 1886 1887 u8 reserved_20[0x8]; 1888 u8 log_rra_max[0x3]; 1889 u8 reserved_21[0x1]; 1890 u8 atomic_mode[0x4]; 1891 u8 rre[0x1]; 1892 u8 rwe[0x1]; 1893 u8 rae[0x1]; 1894 u8 reserved_22[0x1]; 1895 u8 page_offset[0x6]; 1896 u8 reserved_23[0x3]; 1897 u8 cd_slave_receive[0x1]; 1898 u8 cd_slave_send[0x1]; 1899 u8 cd_master[0x1]; 1900 1901 u8 reserved_24[0x3]; 1902 u8 min_rnr_nak[0x5]; 1903 u8 next_rcv_psn[0x18]; 1904 1905 u8 reserved_25[0x8]; 1906 u8 xrcd[0x18]; 1907 1908 u8 reserved_26[0x8]; 1909 u8 cqn_rcv[0x18]; 1910 1911 u8 dbr_addr[0x40]; 1912 1913 u8 q_key[0x20]; 1914 1915 u8 reserved_27[0x5]; 1916 u8 rq_type[0x3]; 1917 u8 srqn_rmpn[0x18]; 1918 1919 u8 reserved_28[0x8]; 1920 u8 rmsn[0x18]; 1921 1922 u8 hw_sq_wqebb_counter[0x10]; 1923 u8 sw_sq_wqebb_counter[0x10]; 1924 1925 u8 hw_rq_counter[0x20]; 1926 1927 u8 sw_rq_counter[0x20]; 1928 1929 u8 reserved_29[0x20]; 1930 1931 u8 reserved_30[0xf]; 1932 u8 cgs[0x1]; 1933 u8 cs_req[0x8]; 1934 u8 cs_res[0x8]; 1935 1936 u8 dc_access_key[0x40]; 1937 1938 u8 rdma_active[0x1]; 1939 u8 comm_est[0x1]; 1940 u8 suspended[0x1]; 1941 u8 reserved_31[0x5]; 1942 u8 send_msg_psn[0x18]; 1943 1944 u8 reserved_32[0x8]; 1945 u8 rcv_msg_psn[0x18]; 1946 1947 u8 rdma_va[0x40]; 1948 1949 u8 rdma_key[0x20]; 1950 1951 u8 reserved_33[0x20]; 1952}; 1953 1954struct mlx5_ifc_roce_addr_layout_bits { 1955 u8 source_l3_address[16][0x8]; 1956 1957 u8 reserved_0[0x3]; 1958 u8 vlan_valid[0x1]; 1959 u8 vlan_id[0xc]; 1960 u8 source_mac_47_32[0x10]; 1961 1962 u8 source_mac_31_0[0x20]; 1963 1964 u8 reserved_1[0x14]; 1965 u8 roce_l3_type[0x4]; 1966 u8 roce_version[0x8]; 1967 1968 u8 reserved_2[0x20]; 1969}; 1970 1971struct mlx5_ifc_rdbc_bits { 1972 u8 reserved_0[0x1c]; 1973 u8 type[0x4]; 1974 1975 u8 reserved_1[0x20]; 1976 1977 u8 reserved_2[0x8]; 1978 u8 psn[0x18]; 1979 1980 u8 rkey[0x20]; 1981 1982 u8 address[0x40]; 1983 1984 u8 byte_count[0x20]; 1985 1986 u8 reserved_3[0x20]; 1987 1988 u8 atomic_resp[32][0x8]; 1989}; 1990 1991enum { 1992 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 1993 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 1994 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 1995 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 1996}; 1997 1998struct mlx5_ifc_flow_context_bits { 1999 u8 reserved_0[0x20]; 2000 2001 u8 group_id[0x20]; 2002 2003 u8 reserved_1[0x8]; 2004 u8 flow_tag[0x18]; 2005 2006 u8 reserved_2[0x10]; 2007 u8 action[0x10]; 2008 2009 u8 reserved_3[0x8]; 2010 u8 destination_list_size[0x18]; 2011 2012 u8 reserved_4[0x8]; 2013 u8 flow_counter_list_size[0x18]; 2014 2015 u8 reserved_5[0x140]; 2016 2017 struct mlx5_ifc_fte_match_param_bits match_value; 2018 2019 u8 reserved_6[0x600]; 2020 2021 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2022}; 2023 2024enum { 2025 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2026 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2027}; 2028 2029struct mlx5_ifc_xrc_srqc_bits { 2030 u8 state[0x4]; 2031 u8 log_xrc_srq_size[0x4]; 2032 u8 reserved_0[0x18]; 2033 2034 u8 wq_signature[0x1]; 2035 u8 cont_srq[0x1]; 2036 u8 reserved_1[0x1]; 2037 u8 rlky[0x1]; 2038 u8 basic_cyclic_rcv_wqe[0x1]; 2039 u8 log_rq_stride[0x3]; 2040 u8 xrcd[0x18]; 2041 2042 u8 page_offset[0x6]; 2043 u8 reserved_2[0x2]; 2044 u8 cqn[0x18]; 2045 2046 u8 reserved_3[0x20]; 2047 2048 u8 reserved_4[0x2]; 2049 u8 log_page_size[0x6]; 2050 u8 user_index[0x18]; 2051 2052 u8 reserved_5[0x20]; 2053 2054 u8 reserved_6[0x8]; 2055 u8 pd[0x18]; 2056 2057 u8 lwm[0x10]; 2058 u8 wqe_cnt[0x10]; 2059 2060 u8 reserved_7[0x40]; 2061 2062 u8 db_record_addr_h[0x20]; 2063 2064 u8 db_record_addr_l[0x1e]; 2065 u8 reserved_8[0x2]; 2066 2067 u8 reserved_9[0x80]; 2068}; 2069 2070struct mlx5_ifc_traffic_counter_bits { 2071 u8 packets[0x40]; 2072 2073 u8 octets[0x40]; 2074}; 2075 2076struct mlx5_ifc_tisc_bits { 2077 u8 strict_lag_tx_port_affinity[0x1]; 2078 u8 reserved_at_1[0x3]; 2079 u8 lag_tx_port_affinity[0x04]; 2080 2081 u8 reserved_at_8[0x4]; 2082 u8 prio[0x4]; 2083 u8 reserved_1[0x10]; 2084 2085 u8 reserved_2[0x100]; 2086 2087 u8 reserved_3[0x8]; 2088 u8 transport_domain[0x18]; 2089 2090 u8 reserved_4[0x8]; 2091 u8 underlay_qpn[0x18]; 2092 2093 u8 reserved_5[0x3a0]; 2094}; 2095 2096enum { 2097 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2098 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2099}; 2100 2101enum { 2102 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2103 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2104}; 2105 2106enum { 2107 MLX5_TIRC_RX_HASH_FN_HASH_NONE = 0x0, 2108 MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8 = 0x1, 2109 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ = 0x2, 2110}; 2111 2112enum { 2113 MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST = 0x1, 2114 MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST = 0x2, 2115}; 2116 2117struct mlx5_ifc_tirc_bits { 2118 u8 reserved_0[0x20]; 2119 2120 u8 disp_type[0x4]; 2121 u8 reserved_1[0x1c]; 2122 2123 u8 reserved_2[0x40]; 2124 2125 u8 reserved_3[0x4]; 2126 u8 lro_timeout_period_usecs[0x10]; 2127 u8 lro_enable_mask[0x4]; 2128 u8 lro_max_msg_sz[0x8]; 2129 2130 u8 reserved_4[0x40]; 2131 2132 u8 reserved_5[0x8]; 2133 u8 inline_rqn[0x18]; 2134 2135 u8 rx_hash_symmetric[0x1]; 2136 u8 reserved_6[0x1]; 2137 u8 tunneled_offload_en[0x1]; 2138 u8 reserved_7[0x5]; 2139 u8 indirect_table[0x18]; 2140 2141 u8 rx_hash_fn[0x4]; 2142 u8 reserved_8[0x2]; 2143 u8 self_lb_en[0x2]; 2144 u8 transport_domain[0x18]; 2145 2146 u8 rx_hash_toeplitz_key[10][0x20]; 2147 2148 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2149 2150 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2151 2152 u8 reserved_9[0x4c0]; 2153}; 2154 2155enum { 2156 MLX5_SRQC_STATE_GOOD = 0x0, 2157 MLX5_SRQC_STATE_ERROR = 0x1, 2158}; 2159 2160struct mlx5_ifc_srqc_bits { 2161 u8 state[0x4]; 2162 u8 log_srq_size[0x4]; 2163 u8 reserved_0[0x18]; 2164 2165 u8 wq_signature[0x1]; 2166 u8 cont_srq[0x1]; 2167 u8 reserved_1[0x1]; 2168 u8 rlky[0x1]; 2169 u8 reserved_2[0x1]; 2170 u8 log_rq_stride[0x3]; 2171 u8 xrcd[0x18]; 2172 2173 u8 page_offset[0x6]; 2174 u8 reserved_3[0x2]; 2175 u8 cqn[0x18]; 2176 2177 u8 reserved_4[0x20]; 2178 2179 u8 reserved_5[0x2]; 2180 u8 log_page_size[0x6]; 2181 u8 reserved_6[0x18]; 2182 2183 u8 reserved_7[0x20]; 2184 2185 u8 reserved_8[0x8]; 2186 u8 pd[0x18]; 2187 2188 u8 lwm[0x10]; 2189 u8 wqe_cnt[0x10]; 2190 2191 u8 reserved_9[0x40]; 2192 2193 u8 dbr_addr[0x40]; 2194 2195 u8 reserved_10[0x80]; 2196}; 2197 2198enum { 2199 MLX5_SQC_STATE_RST = 0x0, 2200 MLX5_SQC_STATE_RDY = 0x1, 2201 MLX5_SQC_STATE_ERR = 0x3, 2202}; 2203 2204struct mlx5_ifc_sqc_bits { 2205 u8 rlkey[0x1]; 2206 u8 cd_master[0x1]; 2207 u8 fre[0x1]; 2208 u8 flush_in_error_en[0x1]; 2209 u8 allow_multi_pkt_send_wqe[0x1]; 2210 u8 min_wqe_inline_mode[0x3]; 2211 u8 state[0x4]; 2212 u8 reg_umr[0x1]; 2213 u8 allow_swp[0x1]; 2214 u8 reserved_0[0x12]; 2215 2216 u8 reserved_1[0x8]; 2217 u8 user_index[0x18]; 2218 2219 u8 reserved_2[0x8]; 2220 u8 cqn[0x18]; 2221 2222 u8 reserved_3[0x80]; 2223 2224 u8 qos_para_vport_number[0x10]; 2225 u8 packet_pacing_rate_limit_index[0x10]; 2226 2227 u8 tis_lst_sz[0x10]; 2228 u8 reserved_4[0x10]; 2229 2230 u8 reserved_5[0x40]; 2231 2232 u8 reserved_6[0x8]; 2233 u8 tis_num_0[0x18]; 2234 2235 struct mlx5_ifc_wq_bits wq; 2236}; 2237 2238enum { 2239 MLX5_TSAR_TYPE_DWRR = 0, 2240 MLX5_TSAR_TYPE_ROUND_ROUBIN = 1, 2241 MLX5_TSAR_TYPE_ETS = 2 2242}; 2243 2244struct mlx5_ifc_tsar_element_attributes_bits { 2245 u8 reserved_0[0x8]; 2246 u8 tsar_type[0x8]; 2247 u8 reserved_1[0x10]; 2248}; 2249 2250struct mlx5_ifc_vport_element_attributes_bits { 2251 u8 reserved_0[0x10]; 2252 u8 vport_number[0x10]; 2253}; 2254 2255struct mlx5_ifc_vport_tc_element_attributes_bits { 2256 u8 traffic_class[0x10]; 2257 u8 vport_number[0x10]; 2258}; 2259 2260struct mlx5_ifc_para_vport_tc_element_attributes_bits { 2261 u8 reserved_0[0x0C]; 2262 u8 traffic_class[0x04]; 2263 u8 qos_para_vport_number[0x10]; 2264}; 2265 2266enum { 2267 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2268 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2269 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2270 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2271}; 2272 2273struct mlx5_ifc_scheduling_context_bits { 2274 u8 element_type[0x8]; 2275 u8 reserved_at_8[0x18]; 2276 2277 u8 element_attributes[0x20]; 2278 2279 u8 parent_element_id[0x20]; 2280 2281 u8 reserved_at_60[0x40]; 2282 2283 u8 bw_share[0x20]; 2284 2285 u8 max_average_bw[0x20]; 2286 2287 u8 reserved_at_e0[0x120]; 2288}; 2289 2290struct mlx5_ifc_rqtc_bits { 2291 u8 reserved_0[0xa0]; 2292 2293 u8 reserved_1[0x10]; 2294 u8 rqt_max_size[0x10]; 2295 2296 u8 reserved_2[0x10]; 2297 u8 rqt_actual_size[0x10]; 2298 2299 u8 reserved_3[0x6a0]; 2300 2301 struct mlx5_ifc_rq_num_bits rq_num[0]; 2302}; 2303 2304enum { 2305 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2306 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2307}; 2308 2309enum { 2310 MLX5_RQC_STATE_RST = 0x0, 2311 MLX5_RQC_STATE_RDY = 0x1, 2312 MLX5_RQC_STATE_ERR = 0x3, 2313}; 2314 2315enum { 2316 MLX5_RQC_DROPLESS_MODE_DISABLE = 0x0, 2317 MLX5_RQC_DROPLESS_MODE_ENABLE = 0x1, 2318}; 2319 2320struct mlx5_ifc_rqc_bits { 2321 u8 rlkey[0x1]; 2322 u8 delay_drop_en[0x1]; 2323 u8 scatter_fcs[0x1]; 2324 u8 vlan_strip_disable[0x1]; 2325 u8 mem_rq_type[0x4]; 2326 u8 state[0x4]; 2327 u8 reserved_1[0x1]; 2328 u8 flush_in_error_en[0x1]; 2329 u8 reserved_2[0x12]; 2330 2331 u8 reserved_3[0x8]; 2332 u8 user_index[0x18]; 2333 2334 u8 reserved_4[0x8]; 2335 u8 cqn[0x18]; 2336 2337 u8 counter_set_id[0x8]; 2338 u8 reserved_5[0x18]; 2339 2340 u8 reserved_6[0x8]; 2341 u8 rmpn[0x18]; 2342 2343 u8 reserved_7[0xe0]; 2344 2345 struct mlx5_ifc_wq_bits wq; 2346}; 2347 2348enum { 2349 MLX5_RMPC_STATE_RDY = 0x1, 2350 MLX5_RMPC_STATE_ERR = 0x3, 2351}; 2352 2353struct mlx5_ifc_rmpc_bits { 2354 u8 reserved_0[0x8]; 2355 u8 state[0x4]; 2356 u8 reserved_1[0x14]; 2357 2358 u8 basic_cyclic_rcv_wqe[0x1]; 2359 u8 reserved_2[0x1f]; 2360 2361 u8 reserved_3[0x140]; 2362 2363 struct mlx5_ifc_wq_bits wq; 2364}; 2365 2366enum { 2367 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0, 2368 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS = 0x1, 2369 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST = 0x2, 2370}; 2371 2372struct mlx5_ifc_nic_vport_context_bits { 2373 u8 reserved_0[0x5]; 2374 u8 min_wqe_inline_mode[0x3]; 2375 u8 reserved_1[0x15]; 2376 u8 disable_mc_local_lb[0x1]; 2377 u8 disable_uc_local_lb[0x1]; 2378 u8 roce_en[0x1]; 2379 2380 u8 arm_change_event[0x1]; 2381 u8 reserved_2[0x1a]; 2382 u8 event_on_mtu[0x1]; 2383 u8 event_on_promisc_change[0x1]; 2384 u8 event_on_vlan_change[0x1]; 2385 u8 event_on_mc_address_change[0x1]; 2386 u8 event_on_uc_address_change[0x1]; 2387 2388 u8 reserved_3[0xe0]; 2389 2390 u8 reserved_4[0x10]; 2391 u8 mtu[0x10]; 2392 2393 u8 system_image_guid[0x40]; 2394 2395 u8 port_guid[0x40]; 2396 2397 u8 node_guid[0x40]; 2398 2399 u8 reserved_5[0x140]; 2400 2401 u8 qkey_violation_counter[0x10]; 2402 u8 reserved_6[0x10]; 2403 2404 u8 reserved_7[0x420]; 2405 2406 u8 promisc_uc[0x1]; 2407 u8 promisc_mc[0x1]; 2408 u8 promisc_all[0x1]; 2409 u8 reserved_8[0x2]; 2410 u8 allowed_list_type[0x3]; 2411 u8 reserved_9[0xc]; 2412 u8 allowed_list_size[0xc]; 2413 2414 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2415 2416 u8 reserved_10[0x20]; 2417 2418 u8 current_uc_mac_address[0][0x40]; 2419}; 2420 2421enum { 2422 MLX5_ACCESS_MODE_PA = 0x0, 2423 MLX5_ACCESS_MODE_MTT = 0x1, 2424 MLX5_ACCESS_MODE_KLM = 0x2, 2425}; 2426 2427struct mlx5_ifc_mkc_bits { 2428 u8 reserved_at_0[0x1]; 2429 u8 free[0x1]; 2430 u8 reserved_at_2[0x1]; 2431 u8 access_mode_4_2[0x3]; 2432 u8 reserved_at_6[0x7]; 2433 u8 relaxed_ordering_write[0x1]; 2434 u8 reserved_at_e[0x1]; 2435 u8 small_fence_on_rdma_read_response[0x1]; 2436 u8 umr_en[0x1]; 2437 u8 a[0x1]; 2438 u8 rw[0x1]; 2439 u8 rr[0x1]; 2440 u8 lw[0x1]; 2441 u8 lr[0x1]; 2442 u8 access_mode[0x2]; 2443 u8 reserved_2[0x8]; 2444 2445 u8 qpn[0x18]; 2446 u8 mkey_7_0[0x8]; 2447 2448 u8 reserved_3[0x20]; 2449 2450 u8 length64[0x1]; 2451 u8 bsf_en[0x1]; 2452 u8 sync_umr[0x1]; 2453 u8 reserved_4[0x2]; 2454 u8 expected_sigerr_count[0x1]; 2455 u8 reserved_5[0x1]; 2456 u8 en_rinval[0x1]; 2457 u8 pd[0x18]; 2458 2459 u8 start_addr[0x40]; 2460 2461 u8 len[0x40]; 2462 2463 u8 bsf_octword_size[0x20]; 2464 2465 u8 reserved_6[0x80]; 2466 2467 u8 translations_octword_size[0x20]; 2468 2469 u8 reserved_7[0x1b]; 2470 u8 log_page_size[0x5]; 2471 2472 u8 reserved_8[0x20]; 2473}; 2474 2475struct mlx5_ifc_pkey_bits { 2476 u8 reserved_0[0x10]; 2477 u8 pkey[0x10]; 2478}; 2479 2480struct mlx5_ifc_array128_auto_bits { 2481 u8 array128_auto[16][0x8]; 2482}; 2483 2484enum { 2485 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID = 0x0, 2486 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID = 0x1, 2487 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY = 0x2, 2488}; 2489 2490enum { 2491 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP = 0x1, 2492 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING = 0x2, 2493 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED = 0x3, 2494 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING = 0x4, 2495 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP = 0x5, 2496 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY = 0x6, 2497 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST = 0x7, 2498}; 2499 2500enum { 2501 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN = 0x0, 2502 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP = 0x1, 2503 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW = 0x2, 2504}; 2505 2506enum { 2507 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN = 0x1, 2508 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT = 0x2, 2509 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM = 0x3, 2510 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE = 0x4, 2511}; 2512 2513enum { 2514 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN = 0x1, 2515 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT = 0x2, 2516 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM = 0x3, 2517 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE = 0x4, 2518}; 2519 2520struct mlx5_ifc_hca_vport_context_bits { 2521 u8 field_select[0x20]; 2522 2523 u8 reserved_0[0xe0]; 2524 2525 u8 sm_virt_aware[0x1]; 2526 u8 has_smi[0x1]; 2527 u8 has_raw[0x1]; 2528 u8 grh_required[0x1]; 2529 u8 reserved_1[0x1]; 2530 u8 min_wqe_inline_mode[0x3]; 2531 u8 reserved_2[0x8]; 2532 u8 port_physical_state[0x4]; 2533 u8 vport_state_policy[0x4]; 2534 u8 port_state[0x4]; 2535 u8 vport_state[0x4]; 2536 2537 u8 reserved_3[0x20]; 2538 2539 u8 system_image_guid[0x40]; 2540 2541 u8 port_guid[0x40]; 2542 2543 u8 node_guid[0x40]; 2544 2545 u8 cap_mask1[0x20]; 2546 2547 u8 cap_mask1_field_select[0x20]; 2548 2549 u8 cap_mask2[0x20]; 2550 2551 u8 cap_mask2_field_select[0x20]; 2552 2553 u8 reserved_4[0x80]; 2554 2555 u8 lid[0x10]; 2556 u8 reserved_5[0x4]; 2557 u8 init_type_reply[0x4]; 2558 u8 lmc[0x3]; 2559 u8 subnet_timeout[0x5]; 2560 2561 u8 sm_lid[0x10]; 2562 u8 sm_sl[0x4]; 2563 u8 reserved_6[0xc]; 2564 2565 u8 qkey_violation_counter[0x10]; 2566 u8 pkey_violation_counter[0x10]; 2567 2568 u8 reserved_7[0xca0]; 2569}; 2570 2571union mlx5_ifc_hca_cap_union_bits { 2572 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2573 struct mlx5_ifc_odp_cap_bits odp_cap; 2574 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2575 struct mlx5_ifc_roce_cap_bits roce_cap; 2576 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2577 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2578 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2579 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2580 struct mlx5_ifc_snapshot_cap_bits snapshot_cap; 2581 struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap; 2582 struct mlx5_ifc_qos_cap_bits qos_cap; 2583 u8 reserved_0[0x8000]; 2584}; 2585 2586enum { 2587 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0, 2588 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1, 2589}; 2590 2591struct mlx5_ifc_flow_table_context_bits { 2592 u8 encap_en[0x1]; 2593 u8 decap_en[0x1]; 2594 u8 reserved_at_2[0x2]; 2595 u8 table_miss_action[0x4]; 2596 u8 level[0x8]; 2597 u8 reserved_at_10[0x8]; 2598 u8 log_size[0x8]; 2599 2600 u8 reserved_at_20[0x8]; 2601 u8 table_miss_id[0x18]; 2602 2603 u8 reserved_at_40[0x8]; 2604 u8 lag_master_next_table_id[0x18]; 2605 2606 u8 reserved_at_60[0xe0]; 2607}; 2608 2609struct mlx5_ifc_esw_vport_context_bits { 2610 u8 reserved_0[0x3]; 2611 u8 vport_svlan_strip[0x1]; 2612 u8 vport_cvlan_strip[0x1]; 2613 u8 vport_svlan_insert[0x1]; 2614 u8 vport_cvlan_insert[0x2]; 2615 u8 reserved_1[0x18]; 2616 2617 u8 reserved_2[0x20]; 2618 2619 u8 svlan_cfi[0x1]; 2620 u8 svlan_pcp[0x3]; 2621 u8 svlan_id[0xc]; 2622 u8 cvlan_cfi[0x1]; 2623 u8 cvlan_pcp[0x3]; 2624 u8 cvlan_id[0xc]; 2625 2626 u8 reserved_3[0x7a0]; 2627}; 2628 2629enum { 2630 MLX5_EQC_STATUS_OK = 0x0, 2631 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2632}; 2633 2634enum { 2635 MLX5_EQ_STATE_ARMED = 0x9, 2636 MLX5_EQ_STATE_FIRED = 0xa, 2637}; 2638 2639struct mlx5_ifc_eqc_bits { 2640 u8 status[0x4]; 2641 u8 reserved_0[0x9]; 2642 u8 ec[0x1]; 2643 u8 oi[0x1]; 2644 u8 reserved_1[0x5]; 2645 u8 st[0x4]; 2646 u8 reserved_2[0x8]; 2647 2648 u8 reserved_3[0x20]; 2649 2650 u8 reserved_4[0x14]; 2651 u8 page_offset[0x6]; 2652 u8 reserved_5[0x6]; 2653 2654 u8 reserved_6[0x3]; 2655 u8 log_eq_size[0x5]; 2656 u8 uar_page[0x18]; 2657 2658 u8 reserved_7[0x20]; 2659 2660 u8 reserved_8[0x18]; 2661 u8 intr[0x8]; 2662 2663 u8 reserved_9[0x3]; 2664 u8 log_page_size[0x5]; 2665 u8 reserved_10[0x18]; 2666 2667 u8 reserved_11[0x60]; 2668 2669 u8 reserved_12[0x8]; 2670 u8 consumer_counter[0x18]; 2671 2672 u8 reserved_13[0x8]; 2673 u8 producer_counter[0x18]; 2674 2675 u8 reserved_14[0x80]; 2676}; 2677 2678enum { 2679 MLX5_DCTC_STATE_ACTIVE = 0x0, 2680 MLX5_DCTC_STATE_DRAINING = 0x1, 2681 MLX5_DCTC_STATE_DRAINED = 0x2, 2682}; 2683 2684enum { 2685 MLX5_DCTC_CS_RES_DISABLE = 0x0, 2686 MLX5_DCTC_CS_RES_NA = 0x1, 2687 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 2688}; 2689 2690enum { 2691 MLX5_DCTC_MTU_256_BYTES = 0x1, 2692 MLX5_DCTC_MTU_512_BYTES = 0x2, 2693 MLX5_DCTC_MTU_1K_BYTES = 0x3, 2694 MLX5_DCTC_MTU_2K_BYTES = 0x4, 2695 MLX5_DCTC_MTU_4K_BYTES = 0x5, 2696}; 2697 2698struct mlx5_ifc_dctc_bits { 2699 u8 reserved_0[0x4]; 2700 u8 state[0x4]; 2701 u8 reserved_1[0x18]; 2702 2703 u8 reserved_2[0x8]; 2704 u8 user_index[0x18]; 2705 2706 u8 reserved_3[0x8]; 2707 u8 cqn[0x18]; 2708 2709 u8 counter_set_id[0x8]; 2710 u8 atomic_mode[0x4]; 2711 u8 rre[0x1]; 2712 u8 rwe[0x1]; 2713 u8 rae[0x1]; 2714 u8 atomic_like_write_en[0x1]; 2715 u8 latency_sensitive[0x1]; 2716 u8 rlky[0x1]; 2717 u8 reserved_4[0xe]; 2718 2719 u8 reserved_5[0x8]; 2720 u8 cs_res[0x8]; 2721 u8 reserved_6[0x3]; 2722 u8 min_rnr_nak[0x5]; 2723 u8 reserved_7[0x8]; 2724 2725 u8 reserved_8[0x8]; 2726 u8 srqn[0x18]; 2727 2728 u8 reserved_9[0x8]; 2729 u8 pd[0x18]; 2730 2731 u8 tclass[0x8]; 2732 u8 reserved_10[0x4]; 2733 u8 flow_label[0x14]; 2734 2735 u8 dc_access_key[0x40]; 2736 2737 u8 reserved_11[0x5]; 2738 u8 mtu[0x3]; 2739 u8 port[0x8]; 2740 u8 pkey_index[0x10]; 2741 2742 u8 reserved_12[0x8]; 2743 u8 my_addr_index[0x8]; 2744 u8 reserved_13[0x8]; 2745 u8 hop_limit[0x8]; 2746 2747 u8 dc_access_key_violation_count[0x20]; 2748 2749 u8 reserved_14[0x14]; 2750 u8 dei_cfi[0x1]; 2751 u8 eth_prio[0x3]; 2752 u8 ecn[0x2]; 2753 u8 dscp[0x6]; 2754 2755 u8 reserved_15[0x40]; 2756}; 2757 2758enum { 2759 MLX5_CQC_STATUS_OK = 0x0, 2760 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 2761 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 2762}; 2763 2764enum { 2765 CQE_SIZE_64 = 0x0, 2766 CQE_SIZE_128 = 0x1, 2767}; 2768 2769enum { 2770 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 2771 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 2772}; 2773 2774enum { 2775 MLX5_CQ_STATE_SOLICITED_ARMED = 0x6, 2776 MLX5_CQ_STATE_ARMED = 0x9, 2777 MLX5_CQ_STATE_FIRED = 0xa, 2778}; 2779 2780struct mlx5_ifc_cqc_bits { 2781 u8 status[0x4]; 2782 u8 reserved_0[0x4]; 2783 u8 cqe_sz[0x3]; 2784 u8 cc[0x1]; 2785 u8 reserved_1[0x1]; 2786 u8 scqe_break_moderation_en[0x1]; 2787 u8 oi[0x1]; 2788 u8 cq_period_mode[0x2]; 2789 u8 cqe_compression_en[0x1]; 2790 u8 mini_cqe_res_format[0x2]; 2791 u8 st[0x4]; 2792 u8 reserved_2[0x8]; 2793 2794 u8 reserved_3[0x20]; 2795 2796 u8 reserved_4[0x14]; 2797 u8 page_offset[0x6]; 2798 u8 reserved_5[0x6]; 2799 2800 u8 reserved_6[0x3]; 2801 u8 log_cq_size[0x5]; 2802 u8 uar_page[0x18]; 2803 2804 u8 reserved_7[0x4]; 2805 u8 cq_period[0xc]; 2806 u8 cq_max_count[0x10]; 2807 2808 u8 reserved_8[0x18]; 2809 u8 c_eqn[0x8]; 2810 2811 u8 reserved_9[0x3]; 2812 u8 log_page_size[0x5]; 2813 u8 reserved_10[0x18]; 2814 2815 u8 reserved_11[0x20]; 2816 2817 u8 reserved_12[0x8]; 2818 u8 last_notified_index[0x18]; 2819 2820 u8 reserved_13[0x8]; 2821 u8 last_solicit_index[0x18]; 2822 2823 u8 reserved_14[0x8]; 2824 u8 consumer_counter[0x18]; 2825 2826 u8 reserved_15[0x8]; 2827 u8 producer_counter[0x18]; 2828 2829 u8 reserved_16[0x40]; 2830 2831 u8 dbr_addr[0x40]; 2832}; 2833 2834union mlx5_ifc_cong_control_roce_ecn_auto_bits { 2835 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 2836 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 2837 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 2838 u8 reserved_0[0x800]; 2839}; 2840 2841struct mlx5_ifc_query_adapter_param_block_bits { 2842 u8 reserved_0[0xc0]; 2843 2844 u8 reserved_1[0x8]; 2845 u8 ieee_vendor_id[0x18]; 2846 2847 u8 reserved_2[0x10]; 2848 u8 vsd_vendor_id[0x10]; 2849 2850 u8 vsd[208][0x8]; 2851 2852 u8 vsd_contd_psid[16][0x8]; 2853}; 2854 2855union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 2856 struct mlx5_ifc_modify_field_select_bits modify_field_select; 2857 struct mlx5_ifc_resize_field_select_bits resize_field_select; 2858 u8 reserved_0[0x20]; 2859}; 2860 2861union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 2862 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 2863 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 2864 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 2865 u8 reserved_0[0x20]; 2866}; 2867 2868struct mlx5_ifc_bufferx_reg_bits { 2869 u8 reserved_0[0x6]; 2870 u8 lossy[0x1]; 2871 u8 epsb[0x1]; 2872 u8 reserved_1[0xc]; 2873 u8 size[0xc]; 2874 2875 u8 xoff_threshold[0x10]; 2876 u8 xon_threshold[0x10]; 2877}; 2878 2879struct mlx5_ifc_config_item_bits { 2880 u8 valid[0x2]; 2881 u8 reserved_0[0x2]; 2882 u8 header_type[0x2]; 2883 u8 reserved_1[0x2]; 2884 u8 default_location[0x1]; 2885 u8 reserved_2[0x7]; 2886 u8 version[0x4]; 2887 u8 reserved_3[0x3]; 2888 u8 length[0x9]; 2889 2890 u8 type[0x20]; 2891 2892 u8 reserved_4[0x10]; 2893 u8 crc16[0x10]; 2894}; 2895 2896struct mlx5_ifc_nodnic_port_config_reg_bits { 2897 struct mlx5_ifc_nodnic_event_word_bits event; 2898 2899 u8 network_en[0x1]; 2900 u8 dma_en[0x1]; 2901 u8 promisc_en[0x1]; 2902 u8 promisc_multicast_en[0x1]; 2903 u8 reserved_0[0x17]; 2904 u8 receive_filter_en[0x5]; 2905 2906 u8 reserved_1[0x10]; 2907 u8 mac_47_32[0x10]; 2908 2909 u8 mac_31_0[0x20]; 2910 2911 u8 receive_filters_mgid_mac[64][0x8]; 2912 2913 u8 gid[16][0x8]; 2914 2915 u8 reserved_2[0x10]; 2916 u8 lid[0x10]; 2917 2918 u8 reserved_3[0xc]; 2919 u8 sm_sl[0x4]; 2920 u8 sm_lid[0x10]; 2921 2922 u8 completion_address_63_32[0x20]; 2923 2924 u8 completion_address_31_12[0x14]; 2925 u8 reserved_4[0x6]; 2926 u8 log_cq_size[0x6]; 2927 2928 u8 working_buffer_address_63_32[0x20]; 2929 2930 u8 working_buffer_address_31_12[0x14]; 2931 u8 reserved_5[0xc]; 2932 2933 struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq; 2934 2935 u8 pkey_index[0x10]; 2936 u8 pkey[0x10]; 2937 2938 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0; 2939 2940 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1; 2941 2942 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0; 2943 2944 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1; 2945 2946 u8 reserved_6[0x400]; 2947}; 2948 2949union mlx5_ifc_event_auto_bits { 2950 struct mlx5_ifc_comp_event_bits comp_event; 2951 struct mlx5_ifc_dct_events_bits dct_events; 2952 struct mlx5_ifc_qp_events_bits qp_events; 2953 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 2954 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 2955 struct mlx5_ifc_cq_error_bits cq_error; 2956 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 2957 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 2958 struct mlx5_ifc_gpio_event_bits gpio_event; 2959 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 2960 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 2961 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 2962 struct mlx5_ifc_pages_req_event_bits pages_req_event; 2963 struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event; 2964 u8 reserved_0[0xe0]; 2965}; 2966 2967struct mlx5_ifc_health_buffer_bits { 2968 u8 reserved_0[0x100]; 2969 2970 u8 assert_existptr[0x20]; 2971 2972 u8 assert_callra[0x20]; 2973 2974 u8 reserved_1[0x40]; 2975 2976 u8 fw_version[0x20]; 2977 2978 u8 hw_id[0x20]; 2979 2980 u8 reserved_2[0x20]; 2981 2982 u8 irisc_index[0x8]; 2983 u8 synd[0x8]; 2984 u8 ext_synd[0x10]; 2985}; 2986 2987struct mlx5_ifc_register_loopback_control_bits { 2988 u8 no_lb[0x1]; 2989 u8 reserved_0[0x7]; 2990 u8 port[0x8]; 2991 u8 reserved_1[0x10]; 2992 2993 u8 reserved_2[0x60]; 2994}; 2995 2996struct mlx5_ifc_lrh_bits { 2997 u8 vl[4]; 2998 u8 lver[4]; 2999 u8 sl[4]; 3000 u8 reserved2[2]; 3001 u8 lnh[2]; 3002 u8 dlid[16]; 3003 u8 reserved5[5]; 3004 u8 pkt_len[11]; 3005 u8 slid[16]; 3006}; 3007 3008struct mlx5_ifc_icmd_set_wol_rol_out_bits { 3009 u8 reserved_0[0x40]; 3010 3011 u8 reserved_1[0x10]; 3012 u8 rol_mode[0x8]; 3013 u8 wol_mode[0x8]; 3014}; 3015 3016struct mlx5_ifc_icmd_set_wol_rol_in_bits { 3017 u8 reserved_0[0x40]; 3018 3019 u8 rol_mode_valid[0x1]; 3020 u8 wol_mode_valid[0x1]; 3021 u8 reserved_1[0xe]; 3022 u8 rol_mode[0x8]; 3023 u8 wol_mode[0x8]; 3024 3025 u8 reserved_2[0x7a0]; 3026}; 3027 3028struct mlx5_ifc_icmd_set_virtual_mac_in_bits { 3029 u8 virtual_mac_en[0x1]; 3030 u8 mac_aux_v[0x1]; 3031 u8 reserved_0[0x1e]; 3032 3033 u8 reserved_1[0x40]; 3034 3035 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3036 3037 u8 reserved_2[0x760]; 3038}; 3039 3040struct mlx5_ifc_icmd_query_virtual_mac_out_bits { 3041 u8 virtual_mac_en[0x1]; 3042 u8 mac_aux_v[0x1]; 3043 u8 reserved_0[0x1e]; 3044 3045 struct mlx5_ifc_mac_address_layout_bits permanent_mac; 3046 3047 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3048 3049 u8 reserved_1[0x760]; 3050}; 3051 3052struct mlx5_ifc_icmd_query_fw_info_out_bits { 3053 struct mlx5_ifc_fw_version_bits fw_version; 3054 3055 u8 reserved_0[0x10]; 3056 u8 hash_signature[0x10]; 3057 3058 u8 psid[16][0x8]; 3059 3060 u8 reserved_1[0x6e0]; 3061}; 3062 3063struct mlx5_ifc_icmd_query_cap_in_bits { 3064 u8 reserved_0[0x10]; 3065 u8 capability_group[0x10]; 3066}; 3067 3068struct mlx5_ifc_icmd_query_cap_general_bits { 3069 u8 nv_access[0x1]; 3070 u8 fw_info_psid[0x1]; 3071 u8 reserved_0[0x1e]; 3072 3073 u8 reserved_1[0x16]; 3074 u8 rol_s[0x1]; 3075 u8 rol_g[0x1]; 3076 u8 reserved_2[0x1]; 3077 u8 wol_s[0x1]; 3078 u8 wol_g[0x1]; 3079 u8 wol_a[0x1]; 3080 u8 wol_b[0x1]; 3081 u8 wol_m[0x1]; 3082 u8 wol_u[0x1]; 3083 u8 wol_p[0x1]; 3084}; 3085 3086struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits { 3087 u8 status[0x8]; 3088 u8 reserved_0[0x18]; 3089 3090 u8 reserved_1[0x7e0]; 3091}; 3092 3093struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits { 3094 u8 status[0x8]; 3095 u8 reserved_0[0x18]; 3096 3097 u8 reserved_1[0x7e0]; 3098}; 3099 3100struct mlx5_ifc_icmd_ocbb_init_in_bits { 3101 u8 address_hi[0x20]; 3102 3103 u8 address_lo[0x20]; 3104 3105 u8 reserved_0[0x7c0]; 3106}; 3107 3108struct mlx5_ifc_icmd_init_ocsd_in_bits { 3109 u8 reserved_0[0x20]; 3110 3111 u8 address_hi[0x20]; 3112 3113 u8 address_lo[0x20]; 3114 3115 u8 reserved_1[0x7a0]; 3116}; 3117 3118struct mlx5_ifc_icmd_access_reg_out_bits { 3119 u8 reserved_0[0x11]; 3120 u8 status[0x7]; 3121 u8 reserved_1[0x8]; 3122 3123 u8 register_id[0x10]; 3124 u8 reserved_2[0x10]; 3125 3126 u8 reserved_3[0x40]; 3127 3128 u8 reserved_4[0x5]; 3129 u8 len[0xb]; 3130 u8 reserved_5[0x10]; 3131 3132 u8 register_data[0][0x20]; 3133}; 3134 3135enum { 3136 MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY = 0x1, 3137 MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE = 0x2, 3138}; 3139 3140struct mlx5_ifc_icmd_access_reg_in_bits { 3141 u8 constant_1[0x5]; 3142 u8 constant_2[0xb]; 3143 u8 reserved_0[0x10]; 3144 3145 u8 register_id[0x10]; 3146 u8 reserved_1[0x1]; 3147 u8 method[0x7]; 3148 u8 constant_3[0x8]; 3149 3150 u8 reserved_2[0x40]; 3151 3152 u8 constant_4[0x5]; 3153 u8 len[0xb]; 3154 u8 reserved_3[0x10]; 3155 3156 u8 register_data[0][0x20]; 3157}; 3158 3159enum { 3160 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3161 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3162}; 3163 3164struct mlx5_ifc_teardown_hca_out_bits { 3165 u8 status[0x8]; 3166 u8 reserved_0[0x18]; 3167 3168 u8 syndrome[0x20]; 3169 3170 u8 reserved_1[0x3f]; 3171 3172 u8 force_state[0x1]; 3173}; 3174 3175enum { 3176 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3177 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3178}; 3179 3180struct mlx5_ifc_teardown_hca_in_bits { 3181 u8 opcode[0x10]; 3182 u8 reserved_0[0x10]; 3183 3184 u8 reserved_1[0x10]; 3185 u8 op_mod[0x10]; 3186 3187 u8 reserved_2[0x10]; 3188 u8 profile[0x10]; 3189 3190 u8 reserved_3[0x20]; 3191}; 3192 3193struct mlx5_ifc_set_delay_drop_params_out_bits { 3194 u8 status[0x8]; 3195 u8 reserved_at_8[0x18]; 3196 3197 u8 syndrome[0x20]; 3198 3199 u8 reserved_at_40[0x40]; 3200}; 3201 3202struct mlx5_ifc_set_delay_drop_params_in_bits { 3203 u8 opcode[0x10]; 3204 u8 reserved_at_10[0x10]; 3205 3206 u8 reserved_at_20[0x10]; 3207 u8 op_mod[0x10]; 3208 3209 u8 reserved_at_40[0x20]; 3210 3211 u8 reserved_at_60[0x10]; 3212 u8 delay_drop_timeout[0x10]; 3213}; 3214 3215struct mlx5_ifc_query_delay_drop_params_out_bits { 3216 u8 status[0x8]; 3217 u8 reserved_at_8[0x18]; 3218 3219 u8 syndrome[0x20]; 3220 3221 u8 reserved_at_40[0x20]; 3222 3223 u8 reserved_at_60[0x10]; 3224 u8 delay_drop_timeout[0x10]; 3225}; 3226 3227struct mlx5_ifc_query_delay_drop_params_in_bits { 3228 u8 opcode[0x10]; 3229 u8 reserved_at_10[0x10]; 3230 3231 u8 reserved_at_20[0x10]; 3232 u8 op_mod[0x10]; 3233 3234 u8 reserved_at_40[0x40]; 3235}; 3236 3237struct mlx5_ifc_suspend_qp_out_bits { 3238 u8 status[0x8]; 3239 u8 reserved_0[0x18]; 3240 3241 u8 syndrome[0x20]; 3242 3243 u8 reserved_1[0x40]; 3244}; 3245 3246struct mlx5_ifc_suspend_qp_in_bits { 3247 u8 opcode[0x10]; 3248 u8 reserved_0[0x10]; 3249 3250 u8 reserved_1[0x10]; 3251 u8 op_mod[0x10]; 3252 3253 u8 reserved_2[0x8]; 3254 u8 qpn[0x18]; 3255 3256 u8 reserved_3[0x20]; 3257}; 3258 3259struct mlx5_ifc_sqerr2rts_qp_out_bits { 3260 u8 status[0x8]; 3261 u8 reserved_0[0x18]; 3262 3263 u8 syndrome[0x20]; 3264 3265 u8 reserved_1[0x40]; 3266}; 3267 3268struct mlx5_ifc_sqerr2rts_qp_in_bits { 3269 u8 opcode[0x10]; 3270 u8 reserved_0[0x10]; 3271 3272 u8 reserved_1[0x10]; 3273 u8 op_mod[0x10]; 3274 3275 u8 reserved_2[0x8]; 3276 u8 qpn[0x18]; 3277 3278 u8 reserved_3[0x20]; 3279 3280 u8 opt_param_mask[0x20]; 3281 3282 u8 reserved_4[0x20]; 3283 3284 struct mlx5_ifc_qpc_bits qpc; 3285 3286 u8 reserved_5[0x80]; 3287}; 3288 3289struct mlx5_ifc_sqd2rts_qp_out_bits { 3290 u8 status[0x8]; 3291 u8 reserved_0[0x18]; 3292 3293 u8 syndrome[0x20]; 3294 3295 u8 reserved_1[0x40]; 3296}; 3297 3298struct mlx5_ifc_sqd2rts_qp_in_bits { 3299 u8 opcode[0x10]; 3300 u8 reserved_0[0x10]; 3301 3302 u8 reserved_1[0x10]; 3303 u8 op_mod[0x10]; 3304 3305 u8 reserved_2[0x8]; 3306 u8 qpn[0x18]; 3307 3308 u8 reserved_3[0x20]; 3309 3310 u8 opt_param_mask[0x20]; 3311 3312 u8 reserved_4[0x20]; 3313 3314 struct mlx5_ifc_qpc_bits qpc; 3315 3316 u8 reserved_5[0x80]; 3317}; 3318 3319struct mlx5_ifc_set_wol_rol_out_bits { 3320 u8 status[0x8]; 3321 u8 reserved_0[0x18]; 3322 3323 u8 syndrome[0x20]; 3324 3325 u8 reserved_1[0x40]; 3326}; 3327 3328struct mlx5_ifc_set_wol_rol_in_bits { 3329 u8 opcode[0x10]; 3330 u8 reserved_0[0x10]; 3331 3332 u8 reserved_1[0x10]; 3333 u8 op_mod[0x10]; 3334 3335 u8 rol_mode_valid[0x1]; 3336 u8 wol_mode_valid[0x1]; 3337 u8 reserved_2[0xe]; 3338 u8 rol_mode[0x8]; 3339 u8 wol_mode[0x8]; 3340 3341 u8 reserved_3[0x20]; 3342}; 3343 3344struct mlx5_ifc_set_roce_address_out_bits { 3345 u8 status[0x8]; 3346 u8 reserved_0[0x18]; 3347 3348 u8 syndrome[0x20]; 3349 3350 u8 reserved_1[0x40]; 3351}; 3352 3353struct mlx5_ifc_set_roce_address_in_bits { 3354 u8 opcode[0x10]; 3355 u8 reserved_0[0x10]; 3356 3357 u8 reserved_1[0x10]; 3358 u8 op_mod[0x10]; 3359 3360 u8 roce_address_index[0x10]; 3361 u8 reserved_2[0x10]; 3362 3363 u8 reserved_3[0x20]; 3364 3365 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3366}; 3367 3368struct mlx5_ifc_set_rdb_out_bits { 3369 u8 status[0x8]; 3370 u8 reserved_0[0x18]; 3371 3372 u8 syndrome[0x20]; 3373 3374 u8 reserved_1[0x40]; 3375}; 3376 3377struct mlx5_ifc_set_rdb_in_bits { 3378 u8 opcode[0x10]; 3379 u8 reserved_0[0x10]; 3380 3381 u8 reserved_1[0x10]; 3382 u8 op_mod[0x10]; 3383 3384 u8 reserved_2[0x8]; 3385 u8 qpn[0x18]; 3386 3387 u8 reserved_3[0x18]; 3388 u8 rdb_list_size[0x8]; 3389 3390 struct mlx5_ifc_rdbc_bits rdb_context[0]; 3391}; 3392 3393struct mlx5_ifc_set_mad_demux_out_bits { 3394 u8 status[0x8]; 3395 u8 reserved_0[0x18]; 3396 3397 u8 syndrome[0x20]; 3398 3399 u8 reserved_1[0x40]; 3400}; 3401 3402enum { 3403 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3404 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3405}; 3406 3407struct mlx5_ifc_set_mad_demux_in_bits { 3408 u8 opcode[0x10]; 3409 u8 reserved_0[0x10]; 3410 3411 u8 reserved_1[0x10]; 3412 u8 op_mod[0x10]; 3413 3414 u8 reserved_2[0x20]; 3415 3416 u8 reserved_3[0x6]; 3417 u8 demux_mode[0x2]; 3418 u8 reserved_4[0x18]; 3419}; 3420 3421struct mlx5_ifc_set_l2_table_entry_out_bits { 3422 u8 status[0x8]; 3423 u8 reserved_0[0x18]; 3424 3425 u8 syndrome[0x20]; 3426 3427 u8 reserved_1[0x40]; 3428}; 3429 3430struct mlx5_ifc_set_l2_table_entry_in_bits { 3431 u8 opcode[0x10]; 3432 u8 reserved_0[0x10]; 3433 3434 u8 reserved_1[0x10]; 3435 u8 op_mod[0x10]; 3436 3437 u8 reserved_2[0x60]; 3438 3439 u8 reserved_3[0x8]; 3440 u8 table_index[0x18]; 3441 3442 u8 reserved_4[0x20]; 3443 3444 u8 reserved_5[0x13]; 3445 u8 vlan_valid[0x1]; 3446 u8 vlan[0xc]; 3447 3448 struct mlx5_ifc_mac_address_layout_bits mac_address; 3449 3450 u8 reserved_6[0xc0]; 3451}; 3452 3453struct mlx5_ifc_set_issi_out_bits { 3454 u8 status[0x8]; 3455 u8 reserved_0[0x18]; 3456 3457 u8 syndrome[0x20]; 3458 3459 u8 reserved_1[0x40]; 3460}; 3461 3462struct mlx5_ifc_set_issi_in_bits { 3463 u8 opcode[0x10]; 3464 u8 reserved_0[0x10]; 3465 3466 u8 reserved_1[0x10]; 3467 u8 op_mod[0x10]; 3468 3469 u8 reserved_2[0x10]; 3470 u8 current_issi[0x10]; 3471 3472 u8 reserved_3[0x20]; 3473}; 3474 3475struct mlx5_ifc_set_hca_cap_out_bits { 3476 u8 status[0x8]; 3477 u8 reserved_0[0x18]; 3478 3479 u8 syndrome[0x20]; 3480 3481 u8 reserved_1[0x40]; 3482}; 3483 3484struct mlx5_ifc_set_hca_cap_in_bits { 3485 u8 opcode[0x10]; 3486 u8 reserved_0[0x10]; 3487 3488 u8 reserved_1[0x10]; 3489 u8 op_mod[0x10]; 3490 3491 u8 reserved_2[0x40]; 3492 3493 union mlx5_ifc_hca_cap_union_bits capability; 3494}; 3495 3496enum { 3497 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3498 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3499 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3500 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3501}; 3502 3503struct mlx5_ifc_set_flow_table_root_out_bits { 3504 u8 status[0x8]; 3505 u8 reserved_0[0x18]; 3506 3507 u8 syndrome[0x20]; 3508 3509 u8 reserved_1[0x40]; 3510}; 3511 3512struct mlx5_ifc_set_flow_table_root_in_bits { 3513 u8 opcode[0x10]; 3514 u8 reserved_0[0x10]; 3515 3516 u8 reserved_1[0x10]; 3517 u8 op_mod[0x10]; 3518 3519 u8 other_vport[0x1]; 3520 u8 reserved_2[0xf]; 3521 u8 vport_number[0x10]; 3522 3523 u8 reserved_3[0x20]; 3524 3525 u8 table_type[0x8]; 3526 u8 reserved_4[0x18]; 3527 3528 u8 reserved_5[0x8]; 3529 u8 table_id[0x18]; 3530 3531 u8 reserved_6[0x8]; 3532 u8 underlay_qpn[0x18]; 3533 3534 u8 reserved_7[0x120]; 3535}; 3536 3537struct mlx5_ifc_set_fte_out_bits { 3538 u8 status[0x8]; 3539 u8 reserved_0[0x18]; 3540 3541 u8 syndrome[0x20]; 3542 3543 u8 reserved_1[0x40]; 3544}; 3545 3546struct mlx5_ifc_set_fte_in_bits { 3547 u8 opcode[0x10]; 3548 u8 reserved_0[0x10]; 3549 3550 u8 reserved_1[0x10]; 3551 u8 op_mod[0x10]; 3552 3553 u8 other_vport[0x1]; 3554 u8 reserved_2[0xf]; 3555 u8 vport_number[0x10]; 3556 3557 u8 reserved_3[0x20]; 3558 3559 u8 table_type[0x8]; 3560 u8 reserved_4[0x18]; 3561 3562 u8 reserved_5[0x8]; 3563 u8 table_id[0x18]; 3564 3565 u8 reserved_6[0x18]; 3566 u8 modify_enable_mask[0x8]; 3567 3568 u8 reserved_7[0x20]; 3569 3570 u8 flow_index[0x20]; 3571 3572 u8 reserved_8[0xe0]; 3573 3574 struct mlx5_ifc_flow_context_bits flow_context; 3575}; 3576 3577struct mlx5_ifc_set_driver_version_out_bits { 3578 u8 status[0x8]; 3579 u8 reserved_0[0x18]; 3580 3581 u8 syndrome[0x20]; 3582 3583 u8 reserved_1[0x40]; 3584}; 3585 3586struct mlx5_ifc_set_driver_version_in_bits { 3587 u8 opcode[0x10]; 3588 u8 reserved_0[0x10]; 3589 3590 u8 reserved_1[0x10]; 3591 u8 op_mod[0x10]; 3592 3593 u8 reserved_2[0x40]; 3594 3595 u8 driver_version[64][0x8]; 3596}; 3597 3598struct mlx5_ifc_set_dc_cnak_trace_out_bits { 3599 u8 status[0x8]; 3600 u8 reserved_0[0x18]; 3601 3602 u8 syndrome[0x20]; 3603 3604 u8 reserved_1[0x40]; 3605}; 3606 3607struct mlx5_ifc_set_dc_cnak_trace_in_bits { 3608 u8 opcode[0x10]; 3609 u8 reserved_0[0x10]; 3610 3611 u8 reserved_1[0x10]; 3612 u8 op_mod[0x10]; 3613 3614 u8 enable[0x1]; 3615 u8 reserved_2[0x1f]; 3616 3617 u8 reserved_3[0x160]; 3618 3619 struct mlx5_ifc_cmd_pas_bits pas; 3620}; 3621 3622struct mlx5_ifc_set_burst_size_out_bits { 3623 u8 status[0x8]; 3624 u8 reserved_0[0x18]; 3625 3626 u8 syndrome[0x20]; 3627 3628 u8 reserved_1[0x40]; 3629}; 3630 3631struct mlx5_ifc_set_burst_size_in_bits { 3632 u8 opcode[0x10]; 3633 u8 reserved_0[0x10]; 3634 3635 u8 reserved_1[0x10]; 3636 u8 op_mod[0x10]; 3637 3638 u8 reserved_2[0x20]; 3639 3640 u8 reserved_3[0x9]; 3641 u8 device_burst_size[0x17]; 3642}; 3643 3644struct mlx5_ifc_rts2rts_qp_out_bits { 3645 u8 status[0x8]; 3646 u8 reserved_0[0x18]; 3647 3648 u8 syndrome[0x20]; 3649 3650 u8 reserved_1[0x40]; 3651}; 3652 3653struct mlx5_ifc_rts2rts_qp_in_bits { 3654 u8 opcode[0x10]; 3655 u8 reserved_0[0x10]; 3656 3657 u8 reserved_1[0x10]; 3658 u8 op_mod[0x10]; 3659 3660 u8 reserved_2[0x8]; 3661 u8 qpn[0x18]; 3662 3663 u8 reserved_3[0x20]; 3664 3665 u8 opt_param_mask[0x20]; 3666 3667 u8 reserved_4[0x20]; 3668 3669 struct mlx5_ifc_qpc_bits qpc; 3670 3671 u8 reserved_5[0x80]; 3672}; 3673 3674struct mlx5_ifc_rtr2rts_qp_out_bits { 3675 u8 status[0x8]; 3676 u8 reserved_0[0x18]; 3677 3678 u8 syndrome[0x20]; 3679 3680 u8 reserved_1[0x40]; 3681}; 3682 3683struct mlx5_ifc_rtr2rts_qp_in_bits { 3684 u8 opcode[0x10]; 3685 u8 reserved_0[0x10]; 3686 3687 u8 reserved_1[0x10]; 3688 u8 op_mod[0x10]; 3689 3690 u8 reserved_2[0x8]; 3691 u8 qpn[0x18]; 3692 3693 u8 reserved_3[0x20]; 3694 3695 u8 opt_param_mask[0x20]; 3696 3697 u8 reserved_4[0x20]; 3698 3699 struct mlx5_ifc_qpc_bits qpc; 3700 3701 u8 reserved_5[0x80]; 3702}; 3703 3704struct mlx5_ifc_rst2init_qp_out_bits { 3705 u8 status[0x8]; 3706 u8 reserved_0[0x18]; 3707 3708 u8 syndrome[0x20]; 3709 3710 u8 reserved_1[0x40]; 3711}; 3712 3713struct mlx5_ifc_rst2init_qp_in_bits { 3714 u8 opcode[0x10]; 3715 u8 reserved_0[0x10]; 3716 3717 u8 reserved_1[0x10]; 3718 u8 op_mod[0x10]; 3719 3720 u8 reserved_2[0x8]; 3721 u8 qpn[0x18]; 3722 3723 u8 reserved_3[0x20]; 3724 3725 u8 opt_param_mask[0x20]; 3726 3727 u8 reserved_4[0x20]; 3728 3729 struct mlx5_ifc_qpc_bits qpc; 3730 3731 u8 reserved_5[0x80]; 3732}; 3733 3734struct mlx5_ifc_resume_qp_out_bits { 3735 u8 status[0x8]; 3736 u8 reserved_0[0x18]; 3737 3738 u8 syndrome[0x20]; 3739 3740 u8 reserved_1[0x40]; 3741}; 3742 3743struct mlx5_ifc_resume_qp_in_bits { 3744 u8 opcode[0x10]; 3745 u8 reserved_0[0x10]; 3746 3747 u8 reserved_1[0x10]; 3748 u8 op_mod[0x10]; 3749 3750 u8 reserved_2[0x8]; 3751 u8 qpn[0x18]; 3752 3753 u8 reserved_3[0x20]; 3754}; 3755 3756struct mlx5_ifc_query_xrc_srq_out_bits { 3757 u8 status[0x8]; 3758 u8 reserved_0[0x18]; 3759 3760 u8 syndrome[0x20]; 3761 3762 u8 reserved_1[0x40]; 3763 3764 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3765 3766 u8 reserved_2[0x600]; 3767 3768 u8 pas[0][0x40]; 3769}; 3770 3771struct mlx5_ifc_query_xrc_srq_in_bits { 3772 u8 opcode[0x10]; 3773 u8 reserved_0[0x10]; 3774 3775 u8 reserved_1[0x10]; 3776 u8 op_mod[0x10]; 3777 3778 u8 reserved_2[0x8]; 3779 u8 xrc_srqn[0x18]; 3780 3781 u8 reserved_3[0x20]; 3782}; 3783 3784struct mlx5_ifc_query_wol_rol_out_bits { 3785 u8 status[0x8]; 3786 u8 reserved_0[0x18]; 3787 3788 u8 syndrome[0x20]; 3789 3790 u8 reserved_1[0x10]; 3791 u8 rol_mode[0x8]; 3792 u8 wol_mode[0x8]; 3793 3794 u8 reserved_2[0x20]; 3795}; 3796 3797struct mlx5_ifc_query_wol_rol_in_bits { 3798 u8 opcode[0x10]; 3799 u8 reserved_0[0x10]; 3800 3801 u8 reserved_1[0x10]; 3802 u8 op_mod[0x10]; 3803 3804 u8 reserved_2[0x40]; 3805}; 3806 3807enum { 3808 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3809 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3810}; 3811 3812struct mlx5_ifc_query_vport_state_out_bits { 3813 u8 status[0x8]; 3814 u8 reserved_0[0x18]; 3815 3816 u8 syndrome[0x20]; 3817 3818 u8 reserved_1[0x20]; 3819 3820 u8 reserved_2[0x18]; 3821 u8 admin_state[0x4]; 3822 u8 state[0x4]; 3823}; 3824 3825enum { 3826 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 3827 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 3828 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 3829}; 3830 3831struct mlx5_ifc_query_vport_state_in_bits { 3832 u8 opcode[0x10]; 3833 u8 reserved_0[0x10]; 3834 3835 u8 reserved_1[0x10]; 3836 u8 op_mod[0x10]; 3837 3838 u8 other_vport[0x1]; 3839 u8 reserved_2[0xf]; 3840 u8 vport_number[0x10]; 3841 3842 u8 reserved_3[0x20]; 3843}; 3844 3845struct mlx5_ifc_query_vport_counter_out_bits { 3846 u8 status[0x8]; 3847 u8 reserved_0[0x18]; 3848 3849 u8 syndrome[0x20]; 3850 3851 u8 reserved_1[0x40]; 3852 3853 struct mlx5_ifc_traffic_counter_bits received_errors; 3854 3855 struct mlx5_ifc_traffic_counter_bits transmit_errors; 3856 3857 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 3858 3859 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 3860 3861 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 3862 3863 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 3864 3865 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 3866 3867 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 3868 3869 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 3870 3871 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 3872 3873 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 3874 3875 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 3876 3877 u8 reserved_2[0xa00]; 3878}; 3879 3880enum { 3881 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 3882}; 3883 3884struct mlx5_ifc_query_vport_counter_in_bits { 3885 u8 opcode[0x10]; 3886 u8 reserved_0[0x10]; 3887 3888 u8 reserved_1[0x10]; 3889 u8 op_mod[0x10]; 3890 3891 u8 other_vport[0x1]; 3892 u8 reserved_2[0xb]; 3893 u8 port_num[0x4]; 3894 u8 vport_number[0x10]; 3895 3896 u8 reserved_3[0x60]; 3897 3898 u8 clear[0x1]; 3899 u8 reserved_4[0x1f]; 3900 3901 u8 reserved_5[0x20]; 3902}; 3903 3904struct mlx5_ifc_query_tis_out_bits { 3905 u8 status[0x8]; 3906 u8 reserved_0[0x18]; 3907 3908 u8 syndrome[0x20]; 3909 3910 u8 reserved_1[0x40]; 3911 3912 struct mlx5_ifc_tisc_bits tis_context; 3913}; 3914 3915struct mlx5_ifc_query_tis_in_bits { 3916 u8 opcode[0x10]; 3917 u8 reserved_0[0x10]; 3918 3919 u8 reserved_1[0x10]; 3920 u8 op_mod[0x10]; 3921 3922 u8 reserved_2[0x8]; 3923 u8 tisn[0x18]; 3924 3925 u8 reserved_3[0x20]; 3926}; 3927 3928struct mlx5_ifc_query_tir_out_bits { 3929 u8 status[0x8]; 3930 u8 reserved_0[0x18]; 3931 3932 u8 syndrome[0x20]; 3933 3934 u8 reserved_1[0xc0]; 3935 3936 struct mlx5_ifc_tirc_bits tir_context; 3937}; 3938 3939struct mlx5_ifc_query_tir_in_bits { 3940 u8 opcode[0x10]; 3941 u8 reserved_0[0x10]; 3942 3943 u8 reserved_1[0x10]; 3944 u8 op_mod[0x10]; 3945 3946 u8 reserved_2[0x8]; 3947 u8 tirn[0x18]; 3948 3949 u8 reserved_3[0x20]; 3950}; 3951 3952struct mlx5_ifc_query_srq_out_bits { 3953 u8 status[0x8]; 3954 u8 reserved_0[0x18]; 3955 3956 u8 syndrome[0x20]; 3957 3958 u8 reserved_1[0x40]; 3959 3960 struct mlx5_ifc_srqc_bits srq_context_entry; 3961 3962 u8 reserved_2[0x600]; 3963 3964 u8 pas[0][0x40]; 3965}; 3966 3967struct mlx5_ifc_query_srq_in_bits { 3968 u8 opcode[0x10]; 3969 u8 reserved_0[0x10]; 3970 3971 u8 reserved_1[0x10]; 3972 u8 op_mod[0x10]; 3973 3974 u8 reserved_2[0x8]; 3975 u8 srqn[0x18]; 3976 3977 u8 reserved_3[0x20]; 3978}; 3979 3980struct mlx5_ifc_query_sq_out_bits { 3981 u8 status[0x8]; 3982 u8 reserved_0[0x18]; 3983 3984 u8 syndrome[0x20]; 3985 3986 u8 reserved_1[0xc0]; 3987 3988 struct mlx5_ifc_sqc_bits sq_context; 3989}; 3990 3991struct mlx5_ifc_query_sq_in_bits { 3992 u8 opcode[0x10]; 3993 u8 reserved_0[0x10]; 3994 3995 u8 reserved_1[0x10]; 3996 u8 op_mod[0x10]; 3997 3998 u8 reserved_2[0x8]; 3999 u8 sqn[0x18]; 4000 4001 u8 reserved_3[0x20]; 4002}; 4003 4004struct mlx5_ifc_query_special_contexts_out_bits { 4005 u8 status[0x8]; 4006 u8 reserved_0[0x18]; 4007 4008 u8 syndrome[0x20]; 4009 4010 u8 dump_fill_mkey[0x20]; 4011 4012 u8 resd_lkey[0x20]; 4013}; 4014 4015struct mlx5_ifc_query_special_contexts_in_bits { 4016 u8 opcode[0x10]; 4017 u8 reserved_0[0x10]; 4018 4019 u8 reserved_1[0x10]; 4020 u8 op_mod[0x10]; 4021 4022 u8 reserved_2[0x40]; 4023}; 4024 4025struct mlx5_ifc_query_scheduling_element_out_bits { 4026 u8 status[0x8]; 4027 u8 reserved_at_8[0x18]; 4028 4029 u8 syndrome[0x20]; 4030 4031 u8 reserved_at_40[0xc0]; 4032 4033 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4034 4035 u8 reserved_at_300[0x100]; 4036}; 4037 4038enum { 4039 MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2, 4040}; 4041 4042struct mlx5_ifc_query_scheduling_element_in_bits { 4043 u8 opcode[0x10]; 4044 u8 reserved_at_10[0x10]; 4045 4046 u8 reserved_at_20[0x10]; 4047 u8 op_mod[0x10]; 4048 4049 u8 scheduling_hierarchy[0x8]; 4050 u8 reserved_at_48[0x18]; 4051 4052 u8 scheduling_element_id[0x20]; 4053 4054 u8 reserved_at_80[0x180]; 4055}; 4056 4057struct mlx5_ifc_query_rqt_out_bits { 4058 u8 status[0x8]; 4059 u8 reserved_0[0x18]; 4060 4061 u8 syndrome[0x20]; 4062 4063 u8 reserved_1[0xc0]; 4064 4065 struct mlx5_ifc_rqtc_bits rqt_context; 4066}; 4067 4068struct mlx5_ifc_query_rqt_in_bits { 4069 u8 opcode[0x10]; 4070 u8 reserved_0[0x10]; 4071 4072 u8 reserved_1[0x10]; 4073 u8 op_mod[0x10]; 4074 4075 u8 reserved_2[0x8]; 4076 u8 rqtn[0x18]; 4077 4078 u8 reserved_3[0x20]; 4079}; 4080 4081struct mlx5_ifc_query_rq_out_bits { 4082 u8 status[0x8]; 4083 u8 reserved_0[0x18]; 4084 4085 u8 syndrome[0x20]; 4086 4087 u8 reserved_1[0xc0]; 4088 4089 struct mlx5_ifc_rqc_bits rq_context; 4090}; 4091 4092struct mlx5_ifc_query_rq_in_bits { 4093 u8 opcode[0x10]; 4094 u8 reserved_0[0x10]; 4095 4096 u8 reserved_1[0x10]; 4097 u8 op_mod[0x10]; 4098 4099 u8 reserved_2[0x8]; 4100 u8 rqn[0x18]; 4101 4102 u8 reserved_3[0x20]; 4103}; 4104 4105struct mlx5_ifc_query_roce_address_out_bits { 4106 u8 status[0x8]; 4107 u8 reserved_0[0x18]; 4108 4109 u8 syndrome[0x20]; 4110 4111 u8 reserved_1[0x40]; 4112 4113 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4114}; 4115 4116struct mlx5_ifc_query_roce_address_in_bits { 4117 u8 opcode[0x10]; 4118 u8 reserved_0[0x10]; 4119 4120 u8 reserved_1[0x10]; 4121 u8 op_mod[0x10]; 4122 4123 u8 roce_address_index[0x10]; 4124 u8 reserved_2[0x10]; 4125 4126 u8 reserved_3[0x20]; 4127}; 4128 4129struct mlx5_ifc_query_rmp_out_bits { 4130 u8 status[0x8]; 4131 u8 reserved_0[0x18]; 4132 4133 u8 syndrome[0x20]; 4134 4135 u8 reserved_1[0xc0]; 4136 4137 struct mlx5_ifc_rmpc_bits rmp_context; 4138}; 4139 4140struct mlx5_ifc_query_rmp_in_bits { 4141 u8 opcode[0x10]; 4142 u8 reserved_0[0x10]; 4143 4144 u8 reserved_1[0x10]; 4145 u8 op_mod[0x10]; 4146 4147 u8 reserved_2[0x8]; 4148 u8 rmpn[0x18]; 4149 4150 u8 reserved_3[0x20]; 4151}; 4152 4153struct mlx5_ifc_query_rdb_out_bits { 4154 u8 status[0x8]; 4155 u8 reserved_0[0x18]; 4156 4157 u8 syndrome[0x20]; 4158 4159 u8 reserved_1[0x20]; 4160 4161 u8 reserved_2[0x18]; 4162 u8 rdb_list_size[0x8]; 4163 4164 struct mlx5_ifc_rdbc_bits rdb_context[0]; 4165}; 4166 4167struct mlx5_ifc_query_rdb_in_bits { 4168 u8 opcode[0x10]; 4169 u8 reserved_0[0x10]; 4170 4171 u8 reserved_1[0x10]; 4172 u8 op_mod[0x10]; 4173 4174 u8 reserved_2[0x8]; 4175 u8 qpn[0x18]; 4176 4177 u8 reserved_3[0x20]; 4178}; 4179 4180struct mlx5_ifc_query_qp_out_bits { 4181 u8 status[0x8]; 4182 u8 reserved_0[0x18]; 4183 4184 u8 syndrome[0x20]; 4185 4186 u8 reserved_1[0x40]; 4187 4188 u8 opt_param_mask[0x20]; 4189 4190 u8 reserved_2[0x20]; 4191 4192 struct mlx5_ifc_qpc_bits qpc; 4193 4194 u8 reserved_3[0x80]; 4195 4196 u8 pas[0][0x40]; 4197}; 4198 4199struct mlx5_ifc_query_qp_in_bits { 4200 u8 opcode[0x10]; 4201 u8 reserved_0[0x10]; 4202 4203 u8 reserved_1[0x10]; 4204 u8 op_mod[0x10]; 4205 4206 u8 reserved_2[0x8]; 4207 u8 qpn[0x18]; 4208 4209 u8 reserved_3[0x20]; 4210}; 4211 4212struct mlx5_ifc_query_q_counter_out_bits { 4213 u8 status[0x8]; 4214 u8 reserved_0[0x18]; 4215 4216 u8 syndrome[0x20]; 4217 4218 u8 reserved_1[0x40]; 4219 4220 u8 rx_write_requests[0x20]; 4221 4222 u8 reserved_2[0x20]; 4223 4224 u8 rx_read_requests[0x20]; 4225 4226 u8 reserved_3[0x20]; 4227 4228 u8 rx_atomic_requests[0x20]; 4229 4230 u8 reserved_4[0x20]; 4231 4232 u8 rx_dct_connect[0x20]; 4233 4234 u8 reserved_5[0x20]; 4235 4236 u8 out_of_buffer[0x20]; 4237 4238 u8 reserved_7[0x20]; 4239 4240 u8 out_of_sequence[0x20]; 4241 4242 u8 reserved_8[0x20]; 4243 4244 u8 duplicate_request[0x20]; 4245 4246 u8 reserved_9[0x20]; 4247 4248 u8 rnr_nak_retry_err[0x20]; 4249 4250 u8 reserved_10[0x20]; 4251 4252 u8 packet_seq_err[0x20]; 4253 4254 u8 reserved_11[0x20]; 4255 4256 u8 implied_nak_seq_err[0x20]; 4257 4258 u8 reserved_12[0x20]; 4259 4260 u8 local_ack_timeout_err[0x20]; 4261 4262 u8 reserved_13[0x20]; 4263 4264 u8 resp_rnr_nak[0x20]; 4265 4266 u8 reserved_14[0x20]; 4267 4268 u8 req_rnr_retries_exceeded[0x20]; 4269 4270 u8 reserved_15[0x460]; 4271}; 4272 4273struct mlx5_ifc_query_q_counter_in_bits { 4274 u8 opcode[0x10]; 4275 u8 reserved_0[0x10]; 4276 4277 u8 reserved_1[0x10]; 4278 u8 op_mod[0x10]; 4279 4280 u8 reserved_2[0x80]; 4281 4282 u8 clear[0x1]; 4283 u8 reserved_3[0x1f]; 4284 4285 u8 reserved_4[0x18]; 4286 u8 counter_set_id[0x8]; 4287}; 4288 4289struct mlx5_ifc_query_pages_out_bits { 4290 u8 status[0x8]; 4291 u8 reserved_0[0x18]; 4292 4293 u8 syndrome[0x20]; 4294 4295 u8 reserved_1[0x10]; 4296 u8 function_id[0x10]; 4297 4298 u8 num_pages[0x20]; 4299}; 4300 4301enum { 4302 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4303 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4304 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4305}; 4306 4307struct mlx5_ifc_query_pages_in_bits { 4308 u8 opcode[0x10]; 4309 u8 reserved_0[0x10]; 4310 4311 u8 reserved_1[0x10]; 4312 u8 op_mod[0x10]; 4313 4314 u8 reserved_2[0x10]; 4315 u8 function_id[0x10]; 4316 4317 u8 reserved_3[0x20]; 4318}; 4319 4320struct mlx5_ifc_query_nic_vport_context_out_bits { 4321 u8 status[0x8]; 4322 u8 reserved_0[0x18]; 4323 4324 u8 syndrome[0x20]; 4325 4326 u8 reserved_1[0x40]; 4327 4328 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4329}; 4330 4331struct mlx5_ifc_query_nic_vport_context_in_bits { 4332 u8 opcode[0x10]; 4333 u8 reserved_0[0x10]; 4334 4335 u8 reserved_1[0x10]; 4336 u8 op_mod[0x10]; 4337 4338 u8 other_vport[0x1]; 4339 u8 reserved_2[0xf]; 4340 u8 vport_number[0x10]; 4341 4342 u8 reserved_3[0x5]; 4343 u8 allowed_list_type[0x3]; 4344 u8 reserved_4[0x18]; 4345}; 4346 4347struct mlx5_ifc_query_mkey_out_bits { 4348 u8 status[0x8]; 4349 u8 reserved_0[0x18]; 4350 4351 u8 syndrome[0x20]; 4352 4353 u8 reserved_1[0x40]; 4354 4355 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4356 4357 u8 reserved_2[0x600]; 4358 4359 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4360 4361 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4362}; 4363 4364struct mlx5_ifc_query_mkey_in_bits { 4365 u8 opcode[0x10]; 4366 u8 reserved_0[0x10]; 4367 4368 u8 reserved_1[0x10]; 4369 u8 op_mod[0x10]; 4370 4371 u8 reserved_2[0x8]; 4372 u8 mkey_index[0x18]; 4373 4374 u8 pg_access[0x1]; 4375 u8 reserved_3[0x1f]; 4376}; 4377 4378struct mlx5_ifc_query_mad_demux_out_bits { 4379 u8 status[0x8]; 4380 u8 reserved_0[0x18]; 4381 4382 u8 syndrome[0x20]; 4383 4384 u8 reserved_1[0x40]; 4385 4386 u8 mad_dumux_parameters_block[0x20]; 4387}; 4388 4389struct mlx5_ifc_query_mad_demux_in_bits { 4390 u8 opcode[0x10]; 4391 u8 reserved_0[0x10]; 4392 4393 u8 reserved_1[0x10]; 4394 u8 op_mod[0x10]; 4395 4396 u8 reserved_2[0x40]; 4397}; 4398 4399struct mlx5_ifc_query_l2_table_entry_out_bits { 4400 u8 status[0x8]; 4401 u8 reserved_0[0x18]; 4402 4403 u8 syndrome[0x20]; 4404 4405 u8 reserved_1[0xa0]; 4406 4407 u8 reserved_2[0x13]; 4408 u8 vlan_valid[0x1]; 4409 u8 vlan[0xc]; 4410 4411 struct mlx5_ifc_mac_address_layout_bits mac_address; 4412 4413 u8 reserved_3[0xc0]; 4414}; 4415 4416struct mlx5_ifc_query_l2_table_entry_in_bits { 4417 u8 opcode[0x10]; 4418 u8 reserved_0[0x10]; 4419 4420 u8 reserved_1[0x10]; 4421 u8 op_mod[0x10]; 4422 4423 u8 reserved_2[0x60]; 4424 4425 u8 reserved_3[0x8]; 4426 u8 table_index[0x18]; 4427 4428 u8 reserved_4[0x140]; 4429}; 4430 4431struct mlx5_ifc_query_issi_out_bits { 4432 u8 status[0x8]; 4433 u8 reserved_0[0x18]; 4434 4435 u8 syndrome[0x20]; 4436 4437 u8 reserved_1[0x10]; 4438 u8 current_issi[0x10]; 4439 4440 u8 reserved_2[0xa0]; 4441 4442 u8 supported_issi_reserved[76][0x8]; 4443 u8 supported_issi_dw0[0x20]; 4444}; 4445 4446struct mlx5_ifc_query_issi_in_bits { 4447 u8 opcode[0x10]; 4448 u8 reserved_0[0x10]; 4449 4450 u8 reserved_1[0x10]; 4451 u8 op_mod[0x10]; 4452 4453 u8 reserved_2[0x40]; 4454}; 4455 4456struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4457 u8 status[0x8]; 4458 u8 reserved_0[0x18]; 4459 4460 u8 syndrome[0x20]; 4461 4462 u8 reserved_1[0x40]; 4463 4464 struct mlx5_ifc_pkey_bits pkey[0]; 4465}; 4466 4467struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4468 u8 opcode[0x10]; 4469 u8 reserved_0[0x10]; 4470 4471 u8 reserved_1[0x10]; 4472 u8 op_mod[0x10]; 4473 4474 u8 other_vport[0x1]; 4475 u8 reserved_2[0xb]; 4476 u8 port_num[0x4]; 4477 u8 vport_number[0x10]; 4478 4479 u8 reserved_3[0x10]; 4480 u8 pkey_index[0x10]; 4481}; 4482 4483struct mlx5_ifc_query_hca_vport_gid_out_bits { 4484 u8 status[0x8]; 4485 u8 reserved_0[0x18]; 4486 4487 u8 syndrome[0x20]; 4488 4489 u8 reserved_1[0x20]; 4490 4491 u8 gids_num[0x10]; 4492 u8 reserved_2[0x10]; 4493 4494 struct mlx5_ifc_array128_auto_bits gid[0]; 4495}; 4496 4497struct mlx5_ifc_query_hca_vport_gid_in_bits { 4498 u8 opcode[0x10]; 4499 u8 reserved_0[0x10]; 4500 4501 u8 reserved_1[0x10]; 4502 u8 op_mod[0x10]; 4503 4504 u8 other_vport[0x1]; 4505 u8 reserved_2[0xb]; 4506 u8 port_num[0x4]; 4507 u8 vport_number[0x10]; 4508 4509 u8 reserved_3[0x10]; 4510 u8 gid_index[0x10]; 4511}; 4512 4513struct mlx5_ifc_query_hca_vport_context_out_bits { 4514 u8 status[0x8]; 4515 u8 reserved_0[0x18]; 4516 4517 u8 syndrome[0x20]; 4518 4519 u8 reserved_1[0x40]; 4520 4521 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4522}; 4523 4524struct mlx5_ifc_query_hca_vport_context_in_bits { 4525 u8 opcode[0x10]; 4526 u8 reserved_0[0x10]; 4527 4528 u8 reserved_1[0x10]; 4529 u8 op_mod[0x10]; 4530 4531 u8 other_vport[0x1]; 4532 u8 reserved_2[0xb]; 4533 u8 port_num[0x4]; 4534 u8 vport_number[0x10]; 4535 4536 u8 reserved_3[0x20]; 4537}; 4538 4539struct mlx5_ifc_query_hca_cap_out_bits { 4540 u8 status[0x8]; 4541 u8 reserved_0[0x18]; 4542 4543 u8 syndrome[0x20]; 4544 4545 u8 reserved_1[0x40]; 4546 4547 union mlx5_ifc_hca_cap_union_bits capability; 4548}; 4549 4550struct mlx5_ifc_query_hca_cap_in_bits { 4551 u8 opcode[0x10]; 4552 u8 reserved_0[0x10]; 4553 4554 u8 reserved_1[0x10]; 4555 u8 op_mod[0x10]; 4556 4557 u8 reserved_2[0x40]; 4558}; 4559 4560struct mlx5_ifc_query_flow_table_out_bits { 4561 u8 status[0x8]; 4562 u8 reserved_at_8[0x18]; 4563 4564 u8 syndrome[0x20]; 4565 4566 u8 reserved_at_40[0x80]; 4567 4568 struct mlx5_ifc_flow_table_context_bits flow_table_context; 4569}; 4570 4571struct mlx5_ifc_query_flow_table_in_bits { 4572 u8 opcode[0x10]; 4573 u8 reserved_0[0x10]; 4574 4575 u8 reserved_1[0x10]; 4576 u8 op_mod[0x10]; 4577 4578 u8 other_vport[0x1]; 4579 u8 reserved_2[0xf]; 4580 u8 vport_number[0x10]; 4581 4582 u8 reserved_3[0x20]; 4583 4584 u8 table_type[0x8]; 4585 u8 reserved_4[0x18]; 4586 4587 u8 reserved_5[0x8]; 4588 u8 table_id[0x18]; 4589 4590 u8 reserved_6[0x140]; 4591}; 4592 4593struct mlx5_ifc_query_fte_out_bits { 4594 u8 status[0x8]; 4595 u8 reserved_0[0x18]; 4596 4597 u8 syndrome[0x20]; 4598 4599 u8 reserved_1[0x1c0]; 4600 4601 struct mlx5_ifc_flow_context_bits flow_context; 4602}; 4603 4604struct mlx5_ifc_query_fte_in_bits { 4605 u8 opcode[0x10]; 4606 u8 reserved_0[0x10]; 4607 4608 u8 reserved_1[0x10]; 4609 u8 op_mod[0x10]; 4610 4611 u8 other_vport[0x1]; 4612 u8 reserved_2[0xf]; 4613 u8 vport_number[0x10]; 4614 4615 u8 reserved_3[0x20]; 4616 4617 u8 table_type[0x8]; 4618 u8 reserved_4[0x18]; 4619 4620 u8 reserved_5[0x8]; 4621 u8 table_id[0x18]; 4622 4623 u8 reserved_6[0x40]; 4624 4625 u8 flow_index[0x20]; 4626 4627 u8 reserved_7[0xe0]; 4628}; 4629 4630enum { 4631 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4632 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4633 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4634}; 4635 4636struct mlx5_ifc_query_flow_group_out_bits { 4637 u8 status[0x8]; 4638 u8 reserved_0[0x18]; 4639 4640 u8 syndrome[0x20]; 4641 4642 u8 reserved_1[0xa0]; 4643 4644 u8 start_flow_index[0x20]; 4645 4646 u8 reserved_2[0x20]; 4647 4648 u8 end_flow_index[0x20]; 4649 4650 u8 reserved_3[0xa0]; 4651 4652 u8 reserved_4[0x18]; 4653 u8 match_criteria_enable[0x8]; 4654 4655 struct mlx5_ifc_fte_match_param_bits match_criteria; 4656 4657 u8 reserved_5[0xe00]; 4658}; 4659 4660struct mlx5_ifc_query_flow_group_in_bits { 4661 u8 opcode[0x10]; 4662 u8 reserved_0[0x10]; 4663 4664 u8 reserved_1[0x10]; 4665 u8 op_mod[0x10]; 4666 4667 u8 other_vport[0x1]; 4668 u8 reserved_2[0xf]; 4669 u8 vport_number[0x10]; 4670 4671 u8 reserved_3[0x20]; 4672 4673 u8 table_type[0x8]; 4674 u8 reserved_4[0x18]; 4675 4676 u8 reserved_5[0x8]; 4677 u8 table_id[0x18]; 4678 4679 u8 group_id[0x20]; 4680 4681 u8 reserved_6[0x120]; 4682}; 4683 4684struct mlx5_ifc_query_flow_counter_out_bits { 4685 u8 status[0x8]; 4686 u8 reserved_at_8[0x18]; 4687 4688 u8 syndrome[0x20]; 4689 4690 u8 reserved_at_40[0x40]; 4691 4692 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4693}; 4694 4695struct mlx5_ifc_query_flow_counter_in_bits { 4696 u8 opcode[0x10]; 4697 u8 reserved_at_10[0x10]; 4698 4699 u8 reserved_at_20[0x10]; 4700 u8 op_mod[0x10]; 4701 4702 u8 reserved_at_40[0x80]; 4703 4704 u8 clear[0x1]; 4705 u8 reserved_at_c1[0xf]; 4706 u8 num_of_counters[0x10]; 4707 4708 u8 reserved_at_e0[0x10]; 4709 u8 flow_counter_id[0x10]; 4710}; 4711 4712struct mlx5_ifc_query_esw_vport_context_out_bits { 4713 u8 status[0x8]; 4714 u8 reserved_0[0x18]; 4715 4716 u8 syndrome[0x20]; 4717 4718 u8 reserved_1[0x40]; 4719 4720 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4721}; 4722 4723struct mlx5_ifc_query_esw_vport_context_in_bits { 4724 u8 opcode[0x10]; 4725 u8 reserved_0[0x10]; 4726 4727 u8 reserved_1[0x10]; 4728 u8 op_mod[0x10]; 4729 4730 u8 other_vport[0x1]; 4731 u8 reserved_2[0xf]; 4732 u8 vport_number[0x10]; 4733 4734 u8 reserved_3[0x20]; 4735}; 4736 4737struct mlx5_ifc_query_eq_out_bits { 4738 u8 status[0x8]; 4739 u8 reserved_0[0x18]; 4740 4741 u8 syndrome[0x20]; 4742 4743 u8 reserved_1[0x40]; 4744 4745 struct mlx5_ifc_eqc_bits eq_context_entry; 4746 4747 u8 reserved_2[0x40]; 4748 4749 u8 event_bitmask[0x40]; 4750 4751 u8 reserved_3[0x580]; 4752 4753 u8 pas[0][0x40]; 4754}; 4755 4756struct mlx5_ifc_query_eq_in_bits { 4757 u8 opcode[0x10]; 4758 u8 reserved_0[0x10]; 4759 4760 u8 reserved_1[0x10]; 4761 u8 op_mod[0x10]; 4762 4763 u8 reserved_2[0x18]; 4764 u8 eq_number[0x8]; 4765 4766 u8 reserved_3[0x20]; 4767}; 4768 4769struct mlx5_ifc_query_dct_out_bits { 4770 u8 status[0x8]; 4771 u8 reserved_0[0x18]; 4772 4773 u8 syndrome[0x20]; 4774 4775 u8 reserved_1[0x40]; 4776 4777 struct mlx5_ifc_dctc_bits dct_context_entry; 4778 4779 u8 reserved_2[0x180]; 4780}; 4781 4782struct mlx5_ifc_query_dct_in_bits { 4783 u8 opcode[0x10]; 4784 u8 reserved_0[0x10]; 4785 4786 u8 reserved_1[0x10]; 4787 u8 op_mod[0x10]; 4788 4789 u8 reserved_2[0x8]; 4790 u8 dctn[0x18]; 4791 4792 u8 reserved_3[0x20]; 4793}; 4794 4795struct mlx5_ifc_query_dc_cnak_trace_out_bits { 4796 u8 status[0x8]; 4797 u8 reserved_0[0x18]; 4798 4799 u8 syndrome[0x20]; 4800 4801 u8 enable[0x1]; 4802 u8 reserved_1[0x1f]; 4803 4804 u8 reserved_2[0x160]; 4805 4806 struct mlx5_ifc_cmd_pas_bits pas; 4807}; 4808 4809struct mlx5_ifc_query_dc_cnak_trace_in_bits { 4810 u8 opcode[0x10]; 4811 u8 reserved_0[0x10]; 4812 4813 u8 reserved_1[0x10]; 4814 u8 op_mod[0x10]; 4815 4816 u8 reserved_2[0x40]; 4817}; 4818 4819struct mlx5_ifc_query_cq_out_bits { 4820 u8 status[0x8]; 4821 u8 reserved_0[0x18]; 4822 4823 u8 syndrome[0x20]; 4824 4825 u8 reserved_1[0x40]; 4826 4827 struct mlx5_ifc_cqc_bits cq_context; 4828 4829 u8 reserved_2[0x600]; 4830 4831 u8 pas[0][0x40]; 4832}; 4833 4834struct mlx5_ifc_query_cq_in_bits { 4835 u8 opcode[0x10]; 4836 u8 reserved_0[0x10]; 4837 4838 u8 reserved_1[0x10]; 4839 u8 op_mod[0x10]; 4840 4841 u8 reserved_2[0x8]; 4842 u8 cqn[0x18]; 4843 4844 u8 reserved_3[0x20]; 4845}; 4846 4847struct mlx5_ifc_query_cong_status_out_bits { 4848 u8 status[0x8]; 4849 u8 reserved_0[0x18]; 4850 4851 u8 syndrome[0x20]; 4852 4853 u8 reserved_1[0x20]; 4854 4855 u8 enable[0x1]; 4856 u8 tag_enable[0x1]; 4857 u8 reserved_2[0x1e]; 4858}; 4859 4860struct mlx5_ifc_query_cong_status_in_bits { 4861 u8 opcode[0x10]; 4862 u8 reserved_0[0x10]; 4863 4864 u8 reserved_1[0x10]; 4865 u8 op_mod[0x10]; 4866 4867 u8 reserved_2[0x18]; 4868 u8 priority[0x4]; 4869 u8 cong_protocol[0x4]; 4870 4871 u8 reserved_3[0x20]; 4872}; 4873 4874struct mlx5_ifc_query_cong_statistics_out_bits { 4875 u8 status[0x8]; 4876 u8 reserved_0[0x18]; 4877 4878 u8 syndrome[0x20]; 4879 4880 u8 reserved_1[0x40]; 4881 4882 u8 rp_cur_flows[0x20]; 4883 4884 u8 sum_flows[0x20]; 4885 4886 u8 rp_cnp_ignored_high[0x20]; 4887 4888 u8 rp_cnp_ignored_low[0x20]; 4889 4890 u8 rp_cnp_handled_high[0x20]; 4891 4892 u8 rp_cnp_handled_low[0x20]; 4893 4894 u8 reserved_2[0x100]; 4895 4896 u8 time_stamp_high[0x20]; 4897 4898 u8 time_stamp_low[0x20]; 4899 4900 u8 accumulators_period[0x20]; 4901 4902 u8 np_ecn_marked_roce_packets_high[0x20]; 4903 4904 u8 np_ecn_marked_roce_packets_low[0x20]; 4905 4906 u8 np_cnp_sent_high[0x20]; 4907 4908 u8 np_cnp_sent_low[0x20]; 4909 4910 u8 reserved_3[0x560]; 4911}; 4912 4913struct mlx5_ifc_query_cong_statistics_in_bits { 4914 u8 opcode[0x10]; 4915 u8 reserved_0[0x10]; 4916 4917 u8 reserved_1[0x10]; 4918 u8 op_mod[0x10]; 4919 4920 u8 clear[0x1]; 4921 u8 reserved_2[0x1f]; 4922 4923 u8 reserved_3[0x20]; 4924}; 4925 4926struct mlx5_ifc_query_cong_params_out_bits { 4927 u8 status[0x8]; 4928 u8 reserved_0[0x18]; 4929 4930 u8 syndrome[0x20]; 4931 4932 u8 reserved_1[0x40]; 4933 4934 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 4935}; 4936 4937struct mlx5_ifc_query_cong_params_in_bits { 4938 u8 opcode[0x10]; 4939 u8 reserved_0[0x10]; 4940 4941 u8 reserved_1[0x10]; 4942 u8 op_mod[0x10]; 4943 4944 u8 reserved_2[0x1c]; 4945 u8 cong_protocol[0x4]; 4946 4947 u8 reserved_3[0x20]; 4948}; 4949 4950struct mlx5_ifc_query_burst_size_out_bits { 4951 u8 status[0x8]; 4952 u8 reserved_0[0x18]; 4953 4954 u8 syndrome[0x20]; 4955 4956 u8 reserved_1[0x20]; 4957 4958 u8 reserved_2[0x9]; 4959 u8 device_burst_size[0x17]; 4960}; 4961 4962struct mlx5_ifc_query_burst_size_in_bits { 4963 u8 opcode[0x10]; 4964 u8 reserved_0[0x10]; 4965 4966 u8 reserved_1[0x10]; 4967 u8 op_mod[0x10]; 4968 4969 u8 reserved_2[0x40]; 4970}; 4971 4972struct mlx5_ifc_query_adapter_out_bits { 4973 u8 status[0x8]; 4974 u8 reserved_0[0x18]; 4975 4976 u8 syndrome[0x20]; 4977 4978 u8 reserved_1[0x40]; 4979 4980 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 4981}; 4982 4983struct mlx5_ifc_query_adapter_in_bits { 4984 u8 opcode[0x10]; 4985 u8 reserved_0[0x10]; 4986 4987 u8 reserved_1[0x10]; 4988 u8 op_mod[0x10]; 4989 4990 u8 reserved_2[0x40]; 4991}; 4992 4993struct mlx5_ifc_qp_2rst_out_bits { 4994 u8 status[0x8]; 4995 u8 reserved_0[0x18]; 4996 4997 u8 syndrome[0x20]; 4998 4999 u8 reserved_1[0x40]; 5000}; 5001 5002struct mlx5_ifc_qp_2rst_in_bits { 5003 u8 opcode[0x10]; 5004 u8 reserved_0[0x10]; 5005 5006 u8 reserved_1[0x10]; 5007 u8 op_mod[0x10]; 5008 5009 u8 reserved_2[0x8]; 5010 u8 qpn[0x18]; 5011 5012 u8 reserved_3[0x20]; 5013}; 5014 5015struct mlx5_ifc_qp_2err_out_bits { 5016 u8 status[0x8]; 5017 u8 reserved_0[0x18]; 5018 5019 u8 syndrome[0x20]; 5020 5021 u8 reserved_1[0x40]; 5022}; 5023 5024struct mlx5_ifc_qp_2err_in_bits { 5025 u8 opcode[0x10]; 5026 u8 reserved_0[0x10]; 5027 5028 u8 reserved_1[0x10]; 5029 u8 op_mod[0x10]; 5030 5031 u8 reserved_2[0x8]; 5032 u8 qpn[0x18]; 5033 5034 u8 reserved_3[0x20]; 5035}; 5036 5037struct mlx5_ifc_para_vport_element_bits { 5038 u8 reserved_at_0[0xc]; 5039 u8 traffic_class[0x4]; 5040 u8 qos_para_vport_number[0x10]; 5041}; 5042 5043struct mlx5_ifc_page_fault_resume_out_bits { 5044 u8 status[0x8]; 5045 u8 reserved_0[0x18]; 5046 5047 u8 syndrome[0x20]; 5048 5049 u8 reserved_1[0x40]; 5050}; 5051 5052struct mlx5_ifc_page_fault_resume_in_bits { 5053 u8 opcode[0x10]; 5054 u8 reserved_0[0x10]; 5055 5056 u8 reserved_1[0x10]; 5057 u8 op_mod[0x10]; 5058 5059 u8 error[0x1]; 5060 u8 reserved_2[0x4]; 5061 u8 rdma[0x1]; 5062 u8 read_write[0x1]; 5063 u8 req_res[0x1]; 5064 u8 qpn[0x18]; 5065 5066 u8 reserved_3[0x20]; 5067}; 5068 5069struct mlx5_ifc_nop_out_bits { 5070 u8 status[0x8]; 5071 u8 reserved_0[0x18]; 5072 5073 u8 syndrome[0x20]; 5074 5075 u8 reserved_1[0x40]; 5076}; 5077 5078struct mlx5_ifc_nop_in_bits { 5079 u8 opcode[0x10]; 5080 u8 reserved_0[0x10]; 5081 5082 u8 reserved_1[0x10]; 5083 u8 op_mod[0x10]; 5084 5085 u8 reserved_2[0x40]; 5086}; 5087 5088struct mlx5_ifc_modify_vport_state_out_bits { 5089 u8 status[0x8]; 5090 u8 reserved_0[0x18]; 5091 5092 u8 syndrome[0x20]; 5093 5094 u8 reserved_1[0x40]; 5095}; 5096 5097enum { 5098 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT = 0x0, 5099 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 5100 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 5101}; 5102 5103enum { 5104 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN = 0x0, 5105 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP = 0x1, 5106 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW = 0x2, 5107}; 5108 5109struct mlx5_ifc_modify_vport_state_in_bits { 5110 u8 opcode[0x10]; 5111 u8 reserved_0[0x10]; 5112 5113 u8 reserved_1[0x10]; 5114 u8 op_mod[0x10]; 5115 5116 u8 other_vport[0x1]; 5117 u8 reserved_2[0xf]; 5118 u8 vport_number[0x10]; 5119 5120 u8 reserved_3[0x18]; 5121 u8 admin_state[0x4]; 5122 u8 reserved_4[0x4]; 5123}; 5124 5125struct mlx5_ifc_modify_tis_out_bits { 5126 u8 status[0x8]; 5127 u8 reserved_0[0x18]; 5128 5129 u8 syndrome[0x20]; 5130 5131 u8 reserved_1[0x40]; 5132}; 5133 5134struct mlx5_ifc_modify_tis_bitmask_bits { 5135 u8 reserved_at_0[0x20]; 5136 5137 u8 reserved_at_20[0x1d]; 5138 u8 lag_tx_port_affinity[0x1]; 5139 u8 strict_lag_tx_port_affinity[0x1]; 5140 u8 prio[0x1]; 5141}; 5142 5143struct mlx5_ifc_modify_tis_in_bits { 5144 u8 opcode[0x10]; 5145 u8 reserved_0[0x10]; 5146 5147 u8 reserved_1[0x10]; 5148 u8 op_mod[0x10]; 5149 5150 u8 reserved_2[0x8]; 5151 u8 tisn[0x18]; 5152 5153 u8 reserved_3[0x20]; 5154 5155 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5156 5157 u8 reserved_4[0x40]; 5158 5159 struct mlx5_ifc_tisc_bits ctx; 5160}; 5161 5162struct mlx5_ifc_modify_tir_out_bits { 5163 u8 status[0x8]; 5164 u8 reserved_0[0x18]; 5165 5166 u8 syndrome[0x20]; 5167 5168 u8 reserved_1[0x40]; 5169}; 5170 5171enum 5172{ 5173 MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0, 5174 MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER = 0x1 << 1 5175}; 5176 5177struct mlx5_ifc_modify_tir_in_bits { 5178 u8 opcode[0x10]; 5179 u8 reserved_0[0x10]; 5180 5181 u8 reserved_1[0x10]; 5182 u8 op_mod[0x10]; 5183 5184 u8 reserved_2[0x8]; 5185 u8 tirn[0x18]; 5186 5187 u8 reserved_3[0x20]; 5188 5189 u8 modify_bitmask[0x40]; 5190 5191 u8 reserved_4[0x40]; 5192 5193 struct mlx5_ifc_tirc_bits tir_context; 5194}; 5195 5196struct mlx5_ifc_modify_sq_out_bits { 5197 u8 status[0x8]; 5198 u8 reserved_0[0x18]; 5199 5200 u8 syndrome[0x20]; 5201 5202 u8 reserved_1[0x40]; 5203}; 5204 5205struct mlx5_ifc_modify_sq_in_bits { 5206 u8 opcode[0x10]; 5207 u8 reserved_0[0x10]; 5208 5209 u8 reserved_1[0x10]; 5210 u8 op_mod[0x10]; 5211 5212 u8 sq_state[0x4]; 5213 u8 reserved_2[0x4]; 5214 u8 sqn[0x18]; 5215 5216 u8 reserved_3[0x20]; 5217 5218 u8 modify_bitmask[0x40]; 5219 5220 u8 reserved_4[0x40]; 5221 5222 struct mlx5_ifc_sqc_bits ctx; 5223}; 5224 5225struct mlx5_ifc_modify_scheduling_element_out_bits { 5226 u8 status[0x8]; 5227 u8 reserved_at_8[0x18]; 5228 5229 u8 syndrome[0x20]; 5230 5231 u8 reserved_at_40[0x1c0]; 5232}; 5233 5234enum { 5235 MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5236}; 5237 5238enum { 5239 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE = 0x1, 5240 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW = 0x2, 5241}; 5242 5243struct mlx5_ifc_modify_scheduling_element_in_bits { 5244 u8 opcode[0x10]; 5245 u8 reserved_at_10[0x10]; 5246 5247 u8 reserved_at_20[0x10]; 5248 u8 op_mod[0x10]; 5249 5250 u8 scheduling_hierarchy[0x8]; 5251 u8 reserved_at_48[0x18]; 5252 5253 u8 scheduling_element_id[0x20]; 5254 5255 u8 reserved_at_80[0x20]; 5256 5257 u8 modify_bitmask[0x20]; 5258 5259 u8 reserved_at_c0[0x40]; 5260 5261 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5262 5263 u8 reserved_at_300[0x100]; 5264}; 5265 5266struct mlx5_ifc_modify_rqt_out_bits { 5267 u8 status[0x8]; 5268 u8 reserved_0[0x18]; 5269 5270 u8 syndrome[0x20]; 5271 5272 u8 reserved_1[0x40]; 5273}; 5274 5275struct mlx5_ifc_modify_rqt_in_bits { 5276 u8 opcode[0x10]; 5277 u8 reserved_0[0x10]; 5278 5279 u8 reserved_1[0x10]; 5280 u8 op_mod[0x10]; 5281 5282 u8 reserved_2[0x8]; 5283 u8 rqtn[0x18]; 5284 5285 u8 reserved_3[0x20]; 5286 5287 u8 modify_bitmask[0x40]; 5288 5289 u8 reserved_4[0x40]; 5290 5291 struct mlx5_ifc_rqtc_bits ctx; 5292}; 5293 5294struct mlx5_ifc_modify_rq_out_bits { 5295 u8 status[0x8]; 5296 u8 reserved_0[0x18]; 5297 5298 u8 syndrome[0x20]; 5299 5300 u8 reserved_1[0x40]; 5301}; 5302 5303enum { 5304 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5305 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3, 5306}; 5307 5308struct mlx5_ifc_modify_rq_in_bits { 5309 u8 opcode[0x10]; 5310 u8 reserved_0[0x10]; 5311 5312 u8 reserved_1[0x10]; 5313 u8 op_mod[0x10]; 5314 5315 u8 rq_state[0x4]; 5316 u8 reserved_2[0x4]; 5317 u8 rqn[0x18]; 5318 5319 u8 reserved_3[0x20]; 5320 5321 u8 modify_bitmask[0x40]; 5322 5323 u8 reserved_4[0x40]; 5324 5325 struct mlx5_ifc_rqc_bits ctx; 5326}; 5327 5328struct mlx5_ifc_modify_rmp_out_bits { 5329 u8 status[0x8]; 5330 u8 reserved_0[0x18]; 5331 5332 u8 syndrome[0x20]; 5333 5334 u8 reserved_1[0x40]; 5335}; 5336 5337struct mlx5_ifc_rmp_bitmask_bits { 5338 u8 reserved[0x20]; 5339 5340 u8 reserved1[0x1f]; 5341 u8 lwm[0x1]; 5342}; 5343 5344struct mlx5_ifc_modify_rmp_in_bits { 5345 u8 opcode[0x10]; 5346 u8 reserved_0[0x10]; 5347 5348 u8 reserved_1[0x10]; 5349 u8 op_mod[0x10]; 5350 5351 u8 rmp_state[0x4]; 5352 u8 reserved_2[0x4]; 5353 u8 rmpn[0x18]; 5354 5355 u8 reserved_3[0x20]; 5356 5357 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5358 5359 u8 reserved_4[0x40]; 5360 5361 struct mlx5_ifc_rmpc_bits ctx; 5362}; 5363 5364struct mlx5_ifc_modify_nic_vport_context_out_bits { 5365 u8 status[0x8]; 5366 u8 reserved_0[0x18]; 5367 5368 u8 syndrome[0x20]; 5369 5370 u8 reserved_1[0x40]; 5371}; 5372 5373struct mlx5_ifc_modify_nic_vport_field_select_bits { 5374 u8 reserved_0[0x14]; 5375 u8 disable_uc_local_lb[0x1]; 5376 u8 disable_mc_local_lb[0x1]; 5377 u8 node_guid[0x1]; 5378 u8 port_guid[0x1]; 5379 u8 min_wqe_inline_mode[0x1]; 5380 u8 mtu[0x1]; 5381 u8 change_event[0x1]; 5382 u8 promisc[0x1]; 5383 u8 permanent_address[0x1]; 5384 u8 addresses_list[0x1]; 5385 u8 roce_en[0x1]; 5386 u8 reserved_1[0x1]; 5387}; 5388 5389struct mlx5_ifc_modify_nic_vport_context_in_bits { 5390 u8 opcode[0x10]; 5391 u8 reserved_0[0x10]; 5392 5393 u8 reserved_1[0x10]; 5394 u8 op_mod[0x10]; 5395 5396 u8 other_vport[0x1]; 5397 u8 reserved_2[0xf]; 5398 u8 vport_number[0x10]; 5399 5400 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5401 5402 u8 reserved_3[0x780]; 5403 5404 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5405}; 5406 5407struct mlx5_ifc_modify_hca_vport_context_out_bits { 5408 u8 status[0x8]; 5409 u8 reserved_0[0x18]; 5410 5411 u8 syndrome[0x20]; 5412 5413 u8 reserved_1[0x40]; 5414}; 5415 5416struct mlx5_ifc_grh_bits { 5417 u8 ip_version[4]; 5418 u8 traffic_class[8]; 5419 u8 flow_label[20]; 5420 u8 payload_length[16]; 5421 u8 next_header[8]; 5422 u8 hop_limit[8]; 5423 u8 sgid[128]; 5424 u8 dgid[128]; 5425}; 5426 5427struct mlx5_ifc_bth_bits { 5428 u8 opcode[8]; 5429 u8 se[1]; 5430 u8 migreq[1]; 5431 u8 pad_count[2]; 5432 u8 tver[4]; 5433 u8 p_key[16]; 5434 u8 reserved8[8]; 5435 u8 dest_qp[24]; 5436 u8 ack_req[1]; 5437 u8 reserved7[7]; 5438 u8 psn[24]; 5439}; 5440 5441struct mlx5_ifc_aeth_bits { 5442 u8 syndrome[8]; 5443 u8 msn[24]; 5444}; 5445 5446struct mlx5_ifc_dceth_bits { 5447 u8 reserved0[8]; 5448 u8 session_id[24]; 5449 u8 reserved1[8]; 5450 u8 dci_dct[24]; 5451}; 5452 5453struct mlx5_ifc_modify_hca_vport_context_in_bits { 5454 u8 opcode[0x10]; 5455 u8 reserved_0[0x10]; 5456 5457 u8 reserved_1[0x10]; 5458 u8 op_mod[0x10]; 5459 5460 u8 other_vport[0x1]; 5461 u8 reserved_2[0xb]; 5462 u8 port_num[0x4]; 5463 u8 vport_number[0x10]; 5464 5465 u8 reserved_3[0x20]; 5466 5467 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5468}; 5469 5470struct mlx5_ifc_modify_flow_table_out_bits { 5471 u8 status[0x8]; 5472 u8 reserved_at_8[0x18]; 5473 5474 u8 syndrome[0x20]; 5475 5476 u8 reserved_at_40[0x40]; 5477}; 5478 5479enum { 5480 MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1, 5481 MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000, 5482}; 5483 5484struct mlx5_ifc_modify_flow_table_in_bits { 5485 u8 opcode[0x10]; 5486 u8 reserved_at_10[0x10]; 5487 5488 u8 reserved_at_20[0x10]; 5489 u8 op_mod[0x10]; 5490 5491 u8 other_vport[0x1]; 5492 u8 reserved_at_41[0xf]; 5493 u8 vport_number[0x10]; 5494 5495 u8 reserved_at_60[0x10]; 5496 u8 modify_field_select[0x10]; 5497 5498 u8 table_type[0x8]; 5499 u8 reserved_at_88[0x18]; 5500 5501 u8 reserved_at_a0[0x8]; 5502 u8 table_id[0x18]; 5503 5504 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5505}; 5506 5507struct mlx5_ifc_modify_esw_vport_context_out_bits { 5508 u8 status[0x8]; 5509 u8 reserved_0[0x18]; 5510 5511 u8 syndrome[0x20]; 5512 5513 u8 reserved_1[0x40]; 5514}; 5515 5516struct mlx5_ifc_esw_vport_context_fields_select_bits { 5517 u8 reserved[0x1c]; 5518 u8 vport_cvlan_insert[0x1]; 5519 u8 vport_svlan_insert[0x1]; 5520 u8 vport_cvlan_strip[0x1]; 5521 u8 vport_svlan_strip[0x1]; 5522}; 5523 5524struct mlx5_ifc_modify_esw_vport_context_in_bits { 5525 u8 opcode[0x10]; 5526 u8 reserved_0[0x10]; 5527 5528 u8 reserved_1[0x10]; 5529 u8 op_mod[0x10]; 5530 5531 u8 other_vport[0x1]; 5532 u8 reserved_2[0xf]; 5533 u8 vport_number[0x10]; 5534 5535 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5536 5537 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5538}; 5539 5540struct mlx5_ifc_modify_cq_out_bits { 5541 u8 status[0x8]; 5542 u8 reserved_0[0x18]; 5543 5544 u8 syndrome[0x20]; 5545 5546 u8 reserved_1[0x40]; 5547}; 5548 5549enum { 5550 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5551 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5552}; 5553 5554struct mlx5_ifc_modify_cq_in_bits { 5555 u8 opcode[0x10]; 5556 u8 reserved_0[0x10]; 5557 5558 u8 reserved_1[0x10]; 5559 u8 op_mod[0x10]; 5560 5561 u8 reserved_2[0x8]; 5562 u8 cqn[0x18]; 5563 5564 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5565 5566 struct mlx5_ifc_cqc_bits cq_context; 5567 5568 u8 reserved_3[0x600]; 5569 5570 u8 pas[0][0x40]; 5571}; 5572 5573struct mlx5_ifc_modify_cong_status_out_bits { 5574 u8 status[0x8]; 5575 u8 reserved_0[0x18]; 5576 5577 u8 syndrome[0x20]; 5578 5579 u8 reserved_1[0x40]; 5580}; 5581 5582struct mlx5_ifc_modify_cong_status_in_bits { 5583 u8 opcode[0x10]; 5584 u8 reserved_0[0x10]; 5585 5586 u8 reserved_1[0x10]; 5587 u8 op_mod[0x10]; 5588 5589 u8 reserved_2[0x18]; 5590 u8 priority[0x4]; 5591 u8 cong_protocol[0x4]; 5592 5593 u8 enable[0x1]; 5594 u8 tag_enable[0x1]; 5595 u8 reserved_3[0x1e]; 5596}; 5597 5598struct mlx5_ifc_modify_cong_params_out_bits { 5599 u8 status[0x8]; 5600 u8 reserved_0[0x18]; 5601 5602 u8 syndrome[0x20]; 5603 5604 u8 reserved_1[0x40]; 5605}; 5606 5607struct mlx5_ifc_modify_cong_params_in_bits { 5608 u8 opcode[0x10]; 5609 u8 reserved_0[0x10]; 5610 5611 u8 reserved_1[0x10]; 5612 u8 op_mod[0x10]; 5613 5614 u8 reserved_2[0x1c]; 5615 u8 cong_protocol[0x4]; 5616 5617 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5618 5619 u8 reserved_3[0x80]; 5620 5621 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5622}; 5623 5624struct mlx5_ifc_manage_pages_out_bits { 5625 u8 status[0x8]; 5626 u8 reserved_0[0x18]; 5627 5628 u8 syndrome[0x20]; 5629 5630 u8 output_num_entries[0x20]; 5631 5632 u8 reserved_1[0x20]; 5633 5634 u8 pas[0][0x40]; 5635}; 5636 5637enum { 5638 MLX5_PAGES_CANT_GIVE = 0x0, 5639 MLX5_PAGES_GIVE = 0x1, 5640 MLX5_PAGES_TAKE = 0x2, 5641}; 5642 5643struct mlx5_ifc_manage_pages_in_bits { 5644 u8 opcode[0x10]; 5645 u8 reserved_0[0x10]; 5646 5647 u8 reserved_1[0x10]; 5648 u8 op_mod[0x10]; 5649 5650 u8 reserved_2[0x10]; 5651 u8 function_id[0x10]; 5652 5653 u8 input_num_entries[0x20]; 5654 5655 u8 pas[0][0x40]; 5656}; 5657 5658struct mlx5_ifc_mad_ifc_out_bits { 5659 u8 status[0x8]; 5660 u8 reserved_0[0x18]; 5661 5662 u8 syndrome[0x20]; 5663 5664 u8 reserved_1[0x40]; 5665 5666 u8 response_mad_packet[256][0x8]; 5667}; 5668 5669struct mlx5_ifc_mad_ifc_in_bits { 5670 u8 opcode[0x10]; 5671 u8 reserved_0[0x10]; 5672 5673 u8 reserved_1[0x10]; 5674 u8 op_mod[0x10]; 5675 5676 u8 remote_lid[0x10]; 5677 u8 reserved_2[0x8]; 5678 u8 port[0x8]; 5679 5680 u8 reserved_3[0x20]; 5681 5682 u8 mad[256][0x8]; 5683}; 5684 5685struct mlx5_ifc_init_hca_out_bits { 5686 u8 status[0x8]; 5687 u8 reserved_0[0x18]; 5688 5689 u8 syndrome[0x20]; 5690 5691 u8 reserved_1[0x40]; 5692}; 5693 5694enum { 5695 MLX5_INIT_HCA_IN_OP_MOD_INIT = 0x0, 5696 MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT = 0x1, 5697}; 5698 5699struct mlx5_ifc_init_hca_in_bits { 5700 u8 opcode[0x10]; 5701 u8 reserved_0[0x10]; 5702 5703 u8 reserved_1[0x10]; 5704 u8 op_mod[0x10]; 5705 5706 u8 reserved_2[0x40]; 5707}; 5708 5709struct mlx5_ifc_init2rtr_qp_out_bits { 5710 u8 status[0x8]; 5711 u8 reserved_0[0x18]; 5712 5713 u8 syndrome[0x20]; 5714 5715 u8 reserved_1[0x40]; 5716}; 5717 5718struct mlx5_ifc_init2rtr_qp_in_bits { 5719 u8 opcode[0x10]; 5720 u8 reserved_0[0x10]; 5721 5722 u8 reserved_1[0x10]; 5723 u8 op_mod[0x10]; 5724 5725 u8 reserved_2[0x8]; 5726 u8 qpn[0x18]; 5727 5728 u8 reserved_3[0x20]; 5729 5730 u8 opt_param_mask[0x20]; 5731 5732 u8 reserved_4[0x20]; 5733 5734 struct mlx5_ifc_qpc_bits qpc; 5735 5736 u8 reserved_5[0x80]; 5737}; 5738 5739struct mlx5_ifc_init2init_qp_out_bits { 5740 u8 status[0x8]; 5741 u8 reserved_0[0x18]; 5742 5743 u8 syndrome[0x20]; 5744 5745 u8 reserved_1[0x40]; 5746}; 5747 5748struct mlx5_ifc_init2init_qp_in_bits { 5749 u8 opcode[0x10]; 5750 u8 reserved_0[0x10]; 5751 5752 u8 reserved_1[0x10]; 5753 u8 op_mod[0x10]; 5754 5755 u8 reserved_2[0x8]; 5756 u8 qpn[0x18]; 5757 5758 u8 reserved_3[0x20]; 5759 5760 u8 opt_param_mask[0x20]; 5761 5762 u8 reserved_4[0x20]; 5763 5764 struct mlx5_ifc_qpc_bits qpc; 5765 5766 u8 reserved_5[0x80]; 5767}; 5768 5769struct mlx5_ifc_get_dropped_packet_log_out_bits { 5770 u8 status[0x8]; 5771 u8 reserved_0[0x18]; 5772 5773 u8 syndrome[0x20]; 5774 5775 u8 reserved_1[0x40]; 5776 5777 u8 packet_headers_log[128][0x8]; 5778 5779 u8 packet_syndrome[64][0x8]; 5780}; 5781 5782struct mlx5_ifc_get_dropped_packet_log_in_bits { 5783 u8 opcode[0x10]; 5784 u8 reserved_0[0x10]; 5785 5786 u8 reserved_1[0x10]; 5787 u8 op_mod[0x10]; 5788 5789 u8 reserved_2[0x40]; 5790}; 5791 5792struct mlx5_ifc_gen_eqe_in_bits { 5793 u8 opcode[0x10]; 5794 u8 reserved_0[0x10]; 5795 5796 u8 reserved_1[0x10]; 5797 u8 op_mod[0x10]; 5798 5799 u8 reserved_2[0x18]; 5800 u8 eq_number[0x8]; 5801 5802 u8 reserved_3[0x20]; 5803 5804 u8 eqe[64][0x8]; 5805}; 5806 5807struct mlx5_ifc_gen_eq_out_bits { 5808 u8 status[0x8]; 5809 u8 reserved_0[0x18]; 5810 5811 u8 syndrome[0x20]; 5812 5813 u8 reserved_1[0x40]; 5814}; 5815 5816struct mlx5_ifc_enable_hca_out_bits { 5817 u8 status[0x8]; 5818 u8 reserved_0[0x18]; 5819 5820 u8 syndrome[0x20]; 5821 5822 u8 reserved_1[0x20]; 5823}; 5824 5825struct mlx5_ifc_enable_hca_in_bits { 5826 u8 opcode[0x10]; 5827 u8 reserved_0[0x10]; 5828 5829 u8 reserved_1[0x10]; 5830 u8 op_mod[0x10]; 5831 5832 u8 reserved_2[0x10]; 5833 u8 function_id[0x10]; 5834 5835 u8 reserved_3[0x20]; 5836}; 5837 5838struct mlx5_ifc_drain_dct_out_bits { 5839 u8 status[0x8]; 5840 u8 reserved_0[0x18]; 5841 5842 u8 syndrome[0x20]; 5843 5844 u8 reserved_1[0x40]; 5845}; 5846 5847struct mlx5_ifc_drain_dct_in_bits { 5848 u8 opcode[0x10]; 5849 u8 reserved_0[0x10]; 5850 5851 u8 reserved_1[0x10]; 5852 u8 op_mod[0x10]; 5853 5854 u8 reserved_2[0x8]; 5855 u8 dctn[0x18]; 5856 5857 u8 reserved_3[0x20]; 5858}; 5859 5860struct mlx5_ifc_disable_hca_out_bits { 5861 u8 status[0x8]; 5862 u8 reserved_0[0x18]; 5863 5864 u8 syndrome[0x20]; 5865 5866 u8 reserved_1[0x20]; 5867}; 5868 5869struct mlx5_ifc_disable_hca_in_bits { 5870 u8 opcode[0x10]; 5871 u8 reserved_0[0x10]; 5872 5873 u8 reserved_1[0x10]; 5874 u8 op_mod[0x10]; 5875 5876 u8 reserved_2[0x10]; 5877 u8 function_id[0x10]; 5878 5879 u8 reserved_3[0x20]; 5880}; 5881 5882struct mlx5_ifc_detach_from_mcg_out_bits { 5883 u8 status[0x8]; 5884 u8 reserved_0[0x18]; 5885 5886 u8 syndrome[0x20]; 5887 5888 u8 reserved_1[0x40]; 5889}; 5890 5891struct mlx5_ifc_detach_from_mcg_in_bits { 5892 u8 opcode[0x10]; 5893 u8 reserved_0[0x10]; 5894 5895 u8 reserved_1[0x10]; 5896 u8 op_mod[0x10]; 5897 5898 u8 reserved_2[0x8]; 5899 u8 qpn[0x18]; 5900 5901 u8 reserved_3[0x20]; 5902 5903 u8 multicast_gid[16][0x8]; 5904}; 5905 5906struct mlx5_ifc_destroy_xrc_srq_out_bits { 5907 u8 status[0x8]; 5908 u8 reserved_0[0x18]; 5909 5910 u8 syndrome[0x20]; 5911 5912 u8 reserved_1[0x40]; 5913}; 5914 5915struct mlx5_ifc_destroy_xrc_srq_in_bits { 5916 u8 opcode[0x10]; 5917 u8 reserved_0[0x10]; 5918 5919 u8 reserved_1[0x10]; 5920 u8 op_mod[0x10]; 5921 5922 u8 reserved_2[0x8]; 5923 u8 xrc_srqn[0x18]; 5924 5925 u8 reserved_3[0x20]; 5926}; 5927 5928struct mlx5_ifc_destroy_tis_out_bits { 5929 u8 status[0x8]; 5930 u8 reserved_0[0x18]; 5931 5932 u8 syndrome[0x20]; 5933 5934 u8 reserved_1[0x40]; 5935}; 5936 5937struct mlx5_ifc_destroy_tis_in_bits { 5938 u8 opcode[0x10]; 5939 u8 reserved_0[0x10]; 5940 5941 u8 reserved_1[0x10]; 5942 u8 op_mod[0x10]; 5943 5944 u8 reserved_2[0x8]; 5945 u8 tisn[0x18]; 5946 5947 u8 reserved_3[0x20]; 5948}; 5949 5950struct mlx5_ifc_destroy_tir_out_bits { 5951 u8 status[0x8]; 5952 u8 reserved_0[0x18]; 5953 5954 u8 syndrome[0x20]; 5955 5956 u8 reserved_1[0x40]; 5957}; 5958 5959struct mlx5_ifc_destroy_tir_in_bits { 5960 u8 opcode[0x10]; 5961 u8 reserved_0[0x10]; 5962 5963 u8 reserved_1[0x10]; 5964 u8 op_mod[0x10]; 5965 5966 u8 reserved_2[0x8]; 5967 u8 tirn[0x18]; 5968 5969 u8 reserved_3[0x20]; 5970}; 5971 5972struct mlx5_ifc_destroy_srq_out_bits { 5973 u8 status[0x8]; 5974 u8 reserved_0[0x18]; 5975 5976 u8 syndrome[0x20]; 5977 5978 u8 reserved_1[0x40]; 5979}; 5980 5981struct mlx5_ifc_destroy_srq_in_bits { 5982 u8 opcode[0x10]; 5983 u8 reserved_0[0x10]; 5984 5985 u8 reserved_1[0x10]; 5986 u8 op_mod[0x10]; 5987 5988 u8 reserved_2[0x8]; 5989 u8 srqn[0x18]; 5990 5991 u8 reserved_3[0x20]; 5992}; 5993 5994struct mlx5_ifc_destroy_sq_out_bits { 5995 u8 status[0x8]; 5996 u8 reserved_0[0x18]; 5997 5998 u8 syndrome[0x20]; 5999 6000 u8 reserved_1[0x40]; 6001}; 6002 6003struct mlx5_ifc_destroy_sq_in_bits { 6004 u8 opcode[0x10]; 6005 u8 reserved_0[0x10]; 6006 6007 u8 reserved_1[0x10]; 6008 u8 op_mod[0x10]; 6009 6010 u8 reserved_2[0x8]; 6011 u8 sqn[0x18]; 6012 6013 u8 reserved_3[0x20]; 6014}; 6015 6016struct mlx5_ifc_destroy_scheduling_element_out_bits { 6017 u8 status[0x8]; 6018 u8 reserved_at_8[0x18]; 6019 6020 u8 syndrome[0x20]; 6021 6022 u8 reserved_at_40[0x1c0]; 6023}; 6024 6025enum { 6026 MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 6027}; 6028 6029struct mlx5_ifc_destroy_scheduling_element_in_bits { 6030 u8 opcode[0x10]; 6031 u8 reserved_at_10[0x10]; 6032 6033 u8 reserved_at_20[0x10]; 6034 u8 op_mod[0x10]; 6035 6036 u8 scheduling_hierarchy[0x8]; 6037 u8 reserved_at_48[0x18]; 6038 6039 u8 scheduling_element_id[0x20]; 6040 6041 u8 reserved_at_80[0x180]; 6042}; 6043 6044struct mlx5_ifc_destroy_rqt_out_bits { 6045 u8 status[0x8]; 6046 u8 reserved_0[0x18]; 6047 6048 u8 syndrome[0x20]; 6049 6050 u8 reserved_1[0x40]; 6051}; 6052 6053struct mlx5_ifc_destroy_rqt_in_bits { 6054 u8 opcode[0x10]; 6055 u8 reserved_0[0x10]; 6056 6057 u8 reserved_1[0x10]; 6058 u8 op_mod[0x10]; 6059 6060 u8 reserved_2[0x8]; 6061 u8 rqtn[0x18]; 6062 6063 u8 reserved_3[0x20]; 6064}; 6065 6066struct mlx5_ifc_destroy_rq_out_bits { 6067 u8 status[0x8]; 6068 u8 reserved_0[0x18]; 6069 6070 u8 syndrome[0x20]; 6071 6072 u8 reserved_1[0x40]; 6073}; 6074 6075struct mlx5_ifc_destroy_rq_in_bits { 6076 u8 opcode[0x10]; 6077 u8 reserved_0[0x10]; 6078 6079 u8 reserved_1[0x10]; 6080 u8 op_mod[0x10]; 6081 6082 u8 reserved_2[0x8]; 6083 u8 rqn[0x18]; 6084 6085 u8 reserved_3[0x20]; 6086}; 6087 6088struct mlx5_ifc_destroy_rmp_out_bits { 6089 u8 status[0x8]; 6090 u8 reserved_0[0x18]; 6091 6092 u8 syndrome[0x20]; 6093 6094 u8 reserved_1[0x40]; 6095}; 6096 6097struct mlx5_ifc_destroy_rmp_in_bits { 6098 u8 opcode[0x10]; 6099 u8 reserved_0[0x10]; 6100 6101 u8 reserved_1[0x10]; 6102 u8 op_mod[0x10]; 6103 6104 u8 reserved_2[0x8]; 6105 u8 rmpn[0x18]; 6106 6107 u8 reserved_3[0x20]; 6108}; 6109 6110struct mlx5_ifc_destroy_qp_out_bits { 6111 u8 status[0x8]; 6112 u8 reserved_0[0x18]; 6113 6114 u8 syndrome[0x20]; 6115 6116 u8 reserved_1[0x40]; 6117}; 6118 6119struct mlx5_ifc_destroy_qp_in_bits { 6120 u8 opcode[0x10]; 6121 u8 reserved_0[0x10]; 6122 6123 u8 reserved_1[0x10]; 6124 u8 op_mod[0x10]; 6125 6126 u8 reserved_2[0x8]; 6127 u8 qpn[0x18]; 6128 6129 u8 reserved_3[0x20]; 6130}; 6131 6132struct mlx5_ifc_destroy_qos_para_vport_out_bits { 6133 u8 status[0x8]; 6134 u8 reserved_at_8[0x18]; 6135 6136 u8 syndrome[0x20]; 6137 6138 u8 reserved_at_40[0x1c0]; 6139}; 6140 6141struct mlx5_ifc_destroy_qos_para_vport_in_bits { 6142 u8 opcode[0x10]; 6143 u8 reserved_at_10[0x10]; 6144 6145 u8 reserved_at_20[0x10]; 6146 u8 op_mod[0x10]; 6147 6148 u8 reserved_at_40[0x20]; 6149 6150 u8 reserved_at_60[0x10]; 6151 u8 qos_para_vport_number[0x10]; 6152 6153 u8 reserved_at_80[0x180]; 6154}; 6155 6156struct mlx5_ifc_destroy_psv_out_bits { 6157 u8 status[0x8]; 6158 u8 reserved_0[0x18]; 6159 6160 u8 syndrome[0x20]; 6161 6162 u8 reserved_1[0x40]; 6163}; 6164 6165struct mlx5_ifc_destroy_psv_in_bits { 6166 u8 opcode[0x10]; 6167 u8 reserved_0[0x10]; 6168 6169 u8 reserved_1[0x10]; 6170 u8 op_mod[0x10]; 6171 6172 u8 reserved_2[0x8]; 6173 u8 psvn[0x18]; 6174 6175 u8 reserved_3[0x20]; 6176}; 6177 6178struct mlx5_ifc_destroy_mkey_out_bits { 6179 u8 status[0x8]; 6180 u8 reserved_0[0x18]; 6181 6182 u8 syndrome[0x20]; 6183 6184 u8 reserved_1[0x40]; 6185}; 6186 6187struct mlx5_ifc_destroy_mkey_in_bits { 6188 u8 opcode[0x10]; 6189 u8 reserved_0[0x10]; 6190 6191 u8 reserved_1[0x10]; 6192 u8 op_mod[0x10]; 6193 6194 u8 reserved_2[0x8]; 6195 u8 mkey_index[0x18]; 6196 6197 u8 reserved_3[0x20]; 6198}; 6199 6200struct mlx5_ifc_destroy_flow_table_out_bits { 6201 u8 status[0x8]; 6202 u8 reserved_0[0x18]; 6203 6204 u8 syndrome[0x20]; 6205 6206 u8 reserved_1[0x40]; 6207}; 6208 6209struct mlx5_ifc_destroy_flow_table_in_bits { 6210 u8 opcode[0x10]; 6211 u8 reserved_0[0x10]; 6212 6213 u8 reserved_1[0x10]; 6214 u8 op_mod[0x10]; 6215 6216 u8 other_vport[0x1]; 6217 u8 reserved_2[0xf]; 6218 u8 vport_number[0x10]; 6219 6220 u8 reserved_3[0x20]; 6221 6222 u8 table_type[0x8]; 6223 u8 reserved_4[0x18]; 6224 6225 u8 reserved_5[0x8]; 6226 u8 table_id[0x18]; 6227 6228 u8 reserved_6[0x140]; 6229}; 6230 6231struct mlx5_ifc_destroy_flow_group_out_bits { 6232 u8 status[0x8]; 6233 u8 reserved_0[0x18]; 6234 6235 u8 syndrome[0x20]; 6236 6237 u8 reserved_1[0x40]; 6238}; 6239 6240struct mlx5_ifc_destroy_flow_group_in_bits { 6241 u8 opcode[0x10]; 6242 u8 reserved_0[0x10]; 6243 6244 u8 reserved_1[0x10]; 6245 u8 op_mod[0x10]; 6246 6247 u8 other_vport[0x1]; 6248 u8 reserved_2[0xf]; 6249 u8 vport_number[0x10]; 6250 6251 u8 reserved_3[0x20]; 6252 6253 u8 table_type[0x8]; 6254 u8 reserved_4[0x18]; 6255 6256 u8 reserved_5[0x8]; 6257 u8 table_id[0x18]; 6258 6259 u8 group_id[0x20]; 6260 6261 u8 reserved_6[0x120]; 6262}; 6263 6264struct mlx5_ifc_destroy_eq_out_bits { 6265 u8 status[0x8]; 6266 u8 reserved_0[0x18]; 6267 6268 u8 syndrome[0x20]; 6269 6270 u8 reserved_1[0x40]; 6271}; 6272 6273struct mlx5_ifc_destroy_eq_in_bits { 6274 u8 opcode[0x10]; 6275 u8 reserved_0[0x10]; 6276 6277 u8 reserved_1[0x10]; 6278 u8 op_mod[0x10]; 6279 6280 u8 reserved_2[0x18]; 6281 u8 eq_number[0x8]; 6282 6283 u8 reserved_3[0x20]; 6284}; 6285 6286struct mlx5_ifc_destroy_dct_out_bits { 6287 u8 status[0x8]; 6288 u8 reserved_0[0x18]; 6289 6290 u8 syndrome[0x20]; 6291 6292 u8 reserved_1[0x40]; 6293}; 6294 6295struct mlx5_ifc_destroy_dct_in_bits { 6296 u8 opcode[0x10]; 6297 u8 reserved_0[0x10]; 6298 6299 u8 reserved_1[0x10]; 6300 u8 op_mod[0x10]; 6301 6302 u8 reserved_2[0x8]; 6303 u8 dctn[0x18]; 6304 6305 u8 reserved_3[0x20]; 6306}; 6307 6308struct mlx5_ifc_destroy_cq_out_bits { 6309 u8 status[0x8]; 6310 u8 reserved_0[0x18]; 6311 6312 u8 syndrome[0x20]; 6313 6314 u8 reserved_1[0x40]; 6315}; 6316 6317struct mlx5_ifc_destroy_cq_in_bits { 6318 u8 opcode[0x10]; 6319 u8 reserved_0[0x10]; 6320 6321 u8 reserved_1[0x10]; 6322 u8 op_mod[0x10]; 6323 6324 u8 reserved_2[0x8]; 6325 u8 cqn[0x18]; 6326 6327 u8 reserved_3[0x20]; 6328}; 6329 6330struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6331 u8 status[0x8]; 6332 u8 reserved_0[0x18]; 6333 6334 u8 syndrome[0x20]; 6335 6336 u8 reserved_1[0x40]; 6337}; 6338 6339struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6340 u8 opcode[0x10]; 6341 u8 reserved_0[0x10]; 6342 6343 u8 reserved_1[0x10]; 6344 u8 op_mod[0x10]; 6345 6346 u8 reserved_2[0x20]; 6347 6348 u8 reserved_3[0x10]; 6349 u8 vxlan_udp_port[0x10]; 6350}; 6351 6352struct mlx5_ifc_delete_l2_table_entry_out_bits { 6353 u8 status[0x8]; 6354 u8 reserved_0[0x18]; 6355 6356 u8 syndrome[0x20]; 6357 6358 u8 reserved_1[0x40]; 6359}; 6360 6361struct mlx5_ifc_delete_l2_table_entry_in_bits { 6362 u8 opcode[0x10]; 6363 u8 reserved_0[0x10]; 6364 6365 u8 reserved_1[0x10]; 6366 u8 op_mod[0x10]; 6367 6368 u8 reserved_2[0x60]; 6369 6370 u8 reserved_3[0x8]; 6371 u8 table_index[0x18]; 6372 6373 u8 reserved_4[0x140]; 6374}; 6375 6376struct mlx5_ifc_delete_fte_out_bits { 6377 u8 status[0x8]; 6378 u8 reserved_0[0x18]; 6379 6380 u8 syndrome[0x20]; 6381 6382 u8 reserved_1[0x40]; 6383}; 6384 6385struct mlx5_ifc_delete_fte_in_bits { 6386 u8 opcode[0x10]; 6387 u8 reserved_0[0x10]; 6388 6389 u8 reserved_1[0x10]; 6390 u8 op_mod[0x10]; 6391 6392 u8 other_vport[0x1]; 6393 u8 reserved_2[0xf]; 6394 u8 vport_number[0x10]; 6395 6396 u8 reserved_3[0x20]; 6397 6398 u8 table_type[0x8]; 6399 u8 reserved_4[0x18]; 6400 6401 u8 reserved_5[0x8]; 6402 u8 table_id[0x18]; 6403 6404 u8 reserved_6[0x40]; 6405 6406 u8 flow_index[0x20]; 6407 6408 u8 reserved_7[0xe0]; 6409}; 6410 6411struct mlx5_ifc_dealloc_xrcd_out_bits { 6412 u8 status[0x8]; 6413 u8 reserved_0[0x18]; 6414 6415 u8 syndrome[0x20]; 6416 6417 u8 reserved_1[0x40]; 6418}; 6419 6420struct mlx5_ifc_dealloc_xrcd_in_bits { 6421 u8 opcode[0x10]; 6422 u8 reserved_0[0x10]; 6423 6424 u8 reserved_1[0x10]; 6425 u8 op_mod[0x10]; 6426 6427 u8 reserved_2[0x8]; 6428 u8 xrcd[0x18]; 6429 6430 u8 reserved_3[0x20]; 6431}; 6432 6433struct mlx5_ifc_dealloc_uar_out_bits { 6434 u8 status[0x8]; 6435 u8 reserved_0[0x18]; 6436 6437 u8 syndrome[0x20]; 6438 6439 u8 reserved_1[0x40]; 6440}; 6441 6442struct mlx5_ifc_dealloc_uar_in_bits { 6443 u8 opcode[0x10]; 6444 u8 reserved_0[0x10]; 6445 6446 u8 reserved_1[0x10]; 6447 u8 op_mod[0x10]; 6448 6449 u8 reserved_2[0x8]; 6450 u8 uar[0x18]; 6451 6452 u8 reserved_3[0x20]; 6453}; 6454 6455struct mlx5_ifc_dealloc_transport_domain_out_bits { 6456 u8 status[0x8]; 6457 u8 reserved_0[0x18]; 6458 6459 u8 syndrome[0x20]; 6460 6461 u8 reserved_1[0x40]; 6462}; 6463 6464struct mlx5_ifc_dealloc_transport_domain_in_bits { 6465 u8 opcode[0x10]; 6466 u8 reserved_0[0x10]; 6467 6468 u8 reserved_1[0x10]; 6469 u8 op_mod[0x10]; 6470 6471 u8 reserved_2[0x8]; 6472 u8 transport_domain[0x18]; 6473 6474 u8 reserved_3[0x20]; 6475}; 6476 6477struct mlx5_ifc_dealloc_q_counter_out_bits { 6478 u8 status[0x8]; 6479 u8 reserved_0[0x18]; 6480 6481 u8 syndrome[0x20]; 6482 6483 u8 reserved_1[0x40]; 6484}; 6485 6486struct mlx5_ifc_counter_id_bits { 6487 u8 reserved[0x10]; 6488 u8 counter_id[0x10]; 6489}; 6490 6491struct mlx5_ifc_diagnostic_params_context_bits { 6492 u8 num_of_counters[0x10]; 6493 u8 reserved_2[0x8]; 6494 u8 log_num_of_samples[0x8]; 6495 6496 u8 single[0x1]; 6497 u8 repetitive[0x1]; 6498 u8 sync[0x1]; 6499 u8 clear[0x1]; 6500 u8 on_demand[0x1]; 6501 u8 enable[0x1]; 6502 u8 reserved_3[0x12]; 6503 u8 log_sample_period[0x8]; 6504 6505 u8 reserved_4[0x80]; 6506 6507 struct mlx5_ifc_counter_id_bits counter_id[0]; 6508}; 6509 6510struct mlx5_ifc_set_diagnostic_params_in_bits { 6511 u8 opcode[0x10]; 6512 u8 reserved_0[0x10]; 6513 6514 u8 reserved_1[0x10]; 6515 u8 op_mod[0x10]; 6516 6517 struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx; 6518}; 6519 6520struct mlx5_ifc_set_diagnostic_params_out_bits { 6521 u8 status[0x8]; 6522 u8 reserved_0[0x18]; 6523 6524 u8 syndrome[0x20]; 6525 6526 u8 reserved_1[0x40]; 6527}; 6528 6529struct mlx5_ifc_query_diagnostic_counters_in_bits { 6530 u8 opcode[0x10]; 6531 u8 reserved_0[0x10]; 6532 6533 u8 reserved_1[0x10]; 6534 u8 op_mod[0x10]; 6535 6536 u8 num_of_samples[0x10]; 6537 u8 sample_index[0x10]; 6538 6539 u8 reserved_2[0x20]; 6540}; 6541 6542struct mlx5_ifc_diagnostic_counter_bits { 6543 u8 counter_id[0x10]; 6544 u8 sample_id[0x10]; 6545 6546 u8 time_stamp_31_0[0x20]; 6547 6548 u8 counter_value_h[0x20]; 6549 6550 u8 counter_value_l[0x20]; 6551}; 6552 6553struct mlx5_ifc_query_diagnostic_counters_out_bits { 6554 u8 status[0x8]; 6555 u8 reserved_0[0x18]; 6556 6557 u8 syndrome[0x20]; 6558 6559 u8 reserved_1[0x40]; 6560 6561 struct mlx5_ifc_diagnostic_counter_bits diag_counter[0]; 6562}; 6563 6564struct mlx5_ifc_dealloc_q_counter_in_bits { 6565 u8 opcode[0x10]; 6566 u8 reserved_0[0x10]; 6567 6568 u8 reserved_1[0x10]; 6569 u8 op_mod[0x10]; 6570 6571 u8 reserved_2[0x18]; 6572 u8 counter_set_id[0x8]; 6573 6574 u8 reserved_3[0x20]; 6575}; 6576 6577struct mlx5_ifc_dealloc_pd_out_bits { 6578 u8 status[0x8]; 6579 u8 reserved_0[0x18]; 6580 6581 u8 syndrome[0x20]; 6582 6583 u8 reserved_1[0x40]; 6584}; 6585 6586struct mlx5_ifc_dealloc_pd_in_bits { 6587 u8 opcode[0x10]; 6588 u8 reserved_0[0x10]; 6589 6590 u8 reserved_1[0x10]; 6591 u8 op_mod[0x10]; 6592 6593 u8 reserved_2[0x8]; 6594 u8 pd[0x18]; 6595 6596 u8 reserved_3[0x20]; 6597}; 6598 6599struct mlx5_ifc_dealloc_flow_counter_out_bits { 6600 u8 status[0x8]; 6601 u8 reserved_0[0x18]; 6602 6603 u8 syndrome[0x20]; 6604 6605 u8 reserved_1[0x40]; 6606}; 6607 6608struct mlx5_ifc_dealloc_flow_counter_in_bits { 6609 u8 opcode[0x10]; 6610 u8 reserved_0[0x10]; 6611 6612 u8 reserved_1[0x10]; 6613 u8 op_mod[0x10]; 6614 6615 u8 reserved_2[0x10]; 6616 u8 flow_counter_id[0x10]; 6617 6618 u8 reserved_3[0x20]; 6619}; 6620 6621struct mlx5_ifc_deactivate_tracer_out_bits { 6622 u8 status[0x8]; 6623 u8 reserved_0[0x18]; 6624 6625 u8 syndrome[0x20]; 6626 6627 u8 reserved_1[0x40]; 6628}; 6629 6630struct mlx5_ifc_deactivate_tracer_in_bits { 6631 u8 opcode[0x10]; 6632 u8 reserved_0[0x10]; 6633 6634 u8 reserved_1[0x10]; 6635 u8 op_mod[0x10]; 6636 6637 u8 mkey[0x20]; 6638 6639 u8 reserved_2[0x20]; 6640}; 6641 6642struct mlx5_ifc_create_xrc_srq_out_bits { 6643 u8 status[0x8]; 6644 u8 reserved_0[0x18]; 6645 6646 u8 syndrome[0x20]; 6647 6648 u8 reserved_1[0x8]; 6649 u8 xrc_srqn[0x18]; 6650 6651 u8 reserved_2[0x20]; 6652}; 6653 6654struct mlx5_ifc_create_xrc_srq_in_bits { 6655 u8 opcode[0x10]; 6656 u8 reserved_0[0x10]; 6657 6658 u8 reserved_1[0x10]; 6659 u8 op_mod[0x10]; 6660 6661 u8 reserved_2[0x40]; 6662 6663 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6664 6665 u8 reserved_3[0x600]; 6666 6667 u8 pas[0][0x40]; 6668}; 6669 6670struct mlx5_ifc_create_tis_out_bits { 6671 u8 status[0x8]; 6672 u8 reserved_0[0x18]; 6673 6674 u8 syndrome[0x20]; 6675 6676 u8 reserved_1[0x8]; 6677 u8 tisn[0x18]; 6678 6679 u8 reserved_2[0x20]; 6680}; 6681 6682struct mlx5_ifc_create_tis_in_bits { 6683 u8 opcode[0x10]; 6684 u8 reserved_0[0x10]; 6685 6686 u8 reserved_1[0x10]; 6687 u8 op_mod[0x10]; 6688 6689 u8 reserved_2[0xc0]; 6690 6691 struct mlx5_ifc_tisc_bits ctx; 6692}; 6693 6694struct mlx5_ifc_create_tir_out_bits { 6695 u8 status[0x8]; 6696 u8 reserved_0[0x18]; 6697 6698 u8 syndrome[0x20]; 6699 6700 u8 reserved_1[0x8]; 6701 u8 tirn[0x18]; 6702 6703 u8 reserved_2[0x20]; 6704}; 6705 6706struct mlx5_ifc_create_tir_in_bits { 6707 u8 opcode[0x10]; 6708 u8 reserved_0[0x10]; 6709 6710 u8 reserved_1[0x10]; 6711 u8 op_mod[0x10]; 6712 6713 u8 reserved_2[0xc0]; 6714 6715 struct mlx5_ifc_tirc_bits tir_context; 6716}; 6717 6718struct mlx5_ifc_create_srq_out_bits { 6719 u8 status[0x8]; 6720 u8 reserved_0[0x18]; 6721 6722 u8 syndrome[0x20]; 6723 6724 u8 reserved_1[0x8]; 6725 u8 srqn[0x18]; 6726 6727 u8 reserved_2[0x20]; 6728}; 6729 6730struct mlx5_ifc_create_srq_in_bits { 6731 u8 opcode[0x10]; 6732 u8 reserved_0[0x10]; 6733 6734 u8 reserved_1[0x10]; 6735 u8 op_mod[0x10]; 6736 6737 u8 reserved_2[0x40]; 6738 6739 struct mlx5_ifc_srqc_bits srq_context_entry; 6740 6741 u8 reserved_3[0x600]; 6742 6743 u8 pas[0][0x40]; 6744}; 6745 6746struct mlx5_ifc_create_sq_out_bits { 6747 u8 status[0x8]; 6748 u8 reserved_0[0x18]; 6749 6750 u8 syndrome[0x20]; 6751 6752 u8 reserved_1[0x8]; 6753 u8 sqn[0x18]; 6754 6755 u8 reserved_2[0x20]; 6756}; 6757 6758struct mlx5_ifc_create_sq_in_bits { 6759 u8 opcode[0x10]; 6760 u8 reserved_0[0x10]; 6761 6762 u8 reserved_1[0x10]; 6763 u8 op_mod[0x10]; 6764 6765 u8 reserved_2[0xc0]; 6766 6767 struct mlx5_ifc_sqc_bits ctx; 6768}; 6769 6770struct mlx5_ifc_create_scheduling_element_out_bits { 6771 u8 status[0x8]; 6772 u8 reserved_at_8[0x18]; 6773 6774 u8 syndrome[0x20]; 6775 6776 u8 reserved_at_40[0x40]; 6777 6778 u8 scheduling_element_id[0x20]; 6779 6780 u8 reserved_at_a0[0x160]; 6781}; 6782 6783enum { 6784 MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 6785}; 6786 6787struct mlx5_ifc_create_scheduling_element_in_bits { 6788 u8 opcode[0x10]; 6789 u8 reserved_at_10[0x10]; 6790 6791 u8 reserved_at_20[0x10]; 6792 u8 op_mod[0x10]; 6793 6794 u8 scheduling_hierarchy[0x8]; 6795 u8 reserved_at_48[0x18]; 6796 6797 u8 reserved_at_60[0xa0]; 6798 6799 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6800 6801 u8 reserved_at_300[0x100]; 6802}; 6803 6804struct mlx5_ifc_create_rqt_out_bits { 6805 u8 status[0x8]; 6806 u8 reserved_0[0x18]; 6807 6808 u8 syndrome[0x20]; 6809 6810 u8 reserved_1[0x8]; 6811 u8 rqtn[0x18]; 6812 6813 u8 reserved_2[0x20]; 6814}; 6815 6816struct mlx5_ifc_create_rqt_in_bits { 6817 u8 opcode[0x10]; 6818 u8 reserved_0[0x10]; 6819 6820 u8 reserved_1[0x10]; 6821 u8 op_mod[0x10]; 6822 6823 u8 reserved_2[0xc0]; 6824 6825 struct mlx5_ifc_rqtc_bits rqt_context; 6826}; 6827 6828struct mlx5_ifc_create_rq_out_bits { 6829 u8 status[0x8]; 6830 u8 reserved_0[0x18]; 6831 6832 u8 syndrome[0x20]; 6833 6834 u8 reserved_1[0x8]; 6835 u8 rqn[0x18]; 6836 6837 u8 reserved_2[0x20]; 6838}; 6839 6840struct mlx5_ifc_create_rq_in_bits { 6841 u8 opcode[0x10]; 6842 u8 reserved_0[0x10]; 6843 6844 u8 reserved_1[0x10]; 6845 u8 op_mod[0x10]; 6846 6847 u8 reserved_2[0xc0]; 6848 6849 struct mlx5_ifc_rqc_bits ctx; 6850}; 6851 6852struct mlx5_ifc_create_rmp_out_bits { 6853 u8 status[0x8]; 6854 u8 reserved_0[0x18]; 6855 6856 u8 syndrome[0x20]; 6857 6858 u8 reserved_1[0x8]; 6859 u8 rmpn[0x18]; 6860 6861 u8 reserved_2[0x20]; 6862}; 6863 6864struct mlx5_ifc_create_rmp_in_bits { 6865 u8 opcode[0x10]; 6866 u8 reserved_0[0x10]; 6867 6868 u8 reserved_1[0x10]; 6869 u8 op_mod[0x10]; 6870 6871 u8 reserved_2[0xc0]; 6872 6873 struct mlx5_ifc_rmpc_bits ctx; 6874}; 6875 6876struct mlx5_ifc_create_qp_out_bits { 6877 u8 status[0x8]; 6878 u8 reserved_0[0x18]; 6879 6880 u8 syndrome[0x20]; 6881 6882 u8 reserved_1[0x8]; 6883 u8 qpn[0x18]; 6884 6885 u8 reserved_2[0x20]; 6886}; 6887 6888struct mlx5_ifc_create_qp_in_bits { 6889 u8 opcode[0x10]; 6890 u8 reserved_0[0x10]; 6891 6892 u8 reserved_1[0x10]; 6893 u8 op_mod[0x10]; 6894 6895 u8 reserved_2[0x8]; 6896 u8 input_qpn[0x18]; 6897 6898 u8 reserved_3[0x20]; 6899 6900 u8 opt_param_mask[0x20]; 6901 6902 u8 reserved_4[0x20]; 6903 6904 struct mlx5_ifc_qpc_bits qpc; 6905 6906 u8 reserved_5[0x80]; 6907 6908 u8 pas[0][0x40]; 6909}; 6910 6911struct mlx5_ifc_create_qos_para_vport_out_bits { 6912 u8 status[0x8]; 6913 u8 reserved_at_8[0x18]; 6914 6915 u8 syndrome[0x20]; 6916 6917 u8 reserved_at_40[0x20]; 6918 6919 u8 reserved_at_60[0x10]; 6920 u8 qos_para_vport_number[0x10]; 6921 6922 u8 reserved_at_80[0x180]; 6923}; 6924 6925struct mlx5_ifc_create_qos_para_vport_in_bits { 6926 u8 opcode[0x10]; 6927 u8 reserved_at_10[0x10]; 6928 6929 u8 reserved_at_20[0x10]; 6930 u8 op_mod[0x10]; 6931 6932 u8 reserved_at_40[0x1c0]; 6933}; 6934 6935struct mlx5_ifc_create_psv_out_bits { 6936 u8 status[0x8]; 6937 u8 reserved_0[0x18]; 6938 6939 u8 syndrome[0x20]; 6940 6941 u8 reserved_1[0x40]; 6942 6943 u8 reserved_2[0x8]; 6944 u8 psv0_index[0x18]; 6945 6946 u8 reserved_3[0x8]; 6947 u8 psv1_index[0x18]; 6948 6949 u8 reserved_4[0x8]; 6950 u8 psv2_index[0x18]; 6951 6952 u8 reserved_5[0x8]; 6953 u8 psv3_index[0x18]; 6954}; 6955 6956struct mlx5_ifc_create_psv_in_bits { 6957 u8 opcode[0x10]; 6958 u8 reserved_0[0x10]; 6959 6960 u8 reserved_1[0x10]; 6961 u8 op_mod[0x10]; 6962 6963 u8 num_psv[0x4]; 6964 u8 reserved_2[0x4]; 6965 u8 pd[0x18]; 6966 6967 u8 reserved_3[0x20]; 6968}; 6969 6970struct mlx5_ifc_create_mkey_out_bits { 6971 u8 status[0x8]; 6972 u8 reserved_0[0x18]; 6973 6974 u8 syndrome[0x20]; 6975 6976 u8 reserved_1[0x8]; 6977 u8 mkey_index[0x18]; 6978 6979 u8 reserved_2[0x20]; 6980}; 6981 6982struct mlx5_ifc_create_mkey_in_bits { 6983 u8 opcode[0x10]; 6984 u8 reserved_0[0x10]; 6985 6986 u8 reserved_1[0x10]; 6987 u8 op_mod[0x10]; 6988 6989 u8 reserved_2[0x20]; 6990 6991 u8 pg_access[0x1]; 6992 u8 reserved_3[0x1f]; 6993 6994 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6995 6996 u8 reserved_4[0x80]; 6997 6998 u8 translations_octword_actual_size[0x20]; 6999 7000 u8 reserved_5[0x560]; 7001 7002 u8 klm_pas_mtt[0][0x20]; 7003}; 7004 7005struct mlx5_ifc_create_flow_table_out_bits { 7006 u8 status[0x8]; 7007 u8 reserved_0[0x18]; 7008 7009 u8 syndrome[0x20]; 7010 7011 u8 reserved_1[0x8]; 7012 u8 table_id[0x18]; 7013 7014 u8 reserved_2[0x20]; 7015}; 7016 7017struct mlx5_ifc_create_flow_table_in_bits { 7018 u8 opcode[0x10]; 7019 u8 reserved_at_10[0x10]; 7020 7021 u8 reserved_at_20[0x10]; 7022 u8 op_mod[0x10]; 7023 7024 u8 other_vport[0x1]; 7025 u8 reserved_at_41[0xf]; 7026 u8 vport_number[0x10]; 7027 7028 u8 reserved_at_60[0x20]; 7029 7030 u8 table_type[0x8]; 7031 u8 reserved_at_88[0x18]; 7032 7033 u8 reserved_at_a0[0x20]; 7034 7035 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7036}; 7037 7038struct mlx5_ifc_create_flow_group_out_bits { 7039 u8 status[0x8]; 7040 u8 reserved_0[0x18]; 7041 7042 u8 syndrome[0x20]; 7043 7044 u8 reserved_1[0x8]; 7045 u8 group_id[0x18]; 7046 7047 u8 reserved_2[0x20]; 7048}; 7049 7050enum { 7051 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7052 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7053 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7054}; 7055 7056struct mlx5_ifc_create_flow_group_in_bits { 7057 u8 opcode[0x10]; 7058 u8 reserved_0[0x10]; 7059 7060 u8 reserved_1[0x10]; 7061 u8 op_mod[0x10]; 7062 7063 u8 other_vport[0x1]; 7064 u8 reserved_2[0xf]; 7065 u8 vport_number[0x10]; 7066 7067 u8 reserved_3[0x20]; 7068 7069 u8 table_type[0x8]; 7070 u8 reserved_4[0x18]; 7071 7072 u8 reserved_5[0x8]; 7073 u8 table_id[0x18]; 7074 7075 u8 reserved_6[0x20]; 7076 7077 u8 start_flow_index[0x20]; 7078 7079 u8 reserved_7[0x20]; 7080 7081 u8 end_flow_index[0x20]; 7082 7083 u8 reserved_8[0xa0]; 7084 7085 u8 reserved_9[0x18]; 7086 u8 match_criteria_enable[0x8]; 7087 7088 struct mlx5_ifc_fte_match_param_bits match_criteria; 7089 7090 u8 reserved_10[0xe00]; 7091}; 7092 7093struct mlx5_ifc_create_eq_out_bits { 7094 u8 status[0x8]; 7095 u8 reserved_0[0x18]; 7096 7097 u8 syndrome[0x20]; 7098 7099 u8 reserved_1[0x18]; 7100 u8 eq_number[0x8]; 7101 7102 u8 reserved_2[0x20]; 7103}; 7104 7105struct mlx5_ifc_create_eq_in_bits { 7106 u8 opcode[0x10]; 7107 u8 reserved_0[0x10]; 7108 7109 u8 reserved_1[0x10]; 7110 u8 op_mod[0x10]; 7111 7112 u8 reserved_2[0x40]; 7113 7114 struct mlx5_ifc_eqc_bits eq_context_entry; 7115 7116 u8 reserved_3[0x40]; 7117 7118 u8 event_bitmask[0x40]; 7119 7120 u8 reserved_4[0x580]; 7121 7122 u8 pas[0][0x40]; 7123}; 7124 7125struct mlx5_ifc_create_dct_out_bits { 7126 u8 status[0x8]; 7127 u8 reserved_0[0x18]; 7128 7129 u8 syndrome[0x20]; 7130 7131 u8 reserved_1[0x8]; 7132 u8 dctn[0x18]; 7133 7134 u8 reserved_2[0x20]; 7135}; 7136 7137struct mlx5_ifc_create_dct_in_bits { 7138 u8 opcode[0x10]; 7139 u8 reserved_0[0x10]; 7140 7141 u8 reserved_1[0x10]; 7142 u8 op_mod[0x10]; 7143 7144 u8 reserved_2[0x40]; 7145 7146 struct mlx5_ifc_dctc_bits dct_context_entry; 7147 7148 u8 reserved_3[0x180]; 7149}; 7150 7151struct mlx5_ifc_create_cq_out_bits { 7152 u8 status[0x8]; 7153 u8 reserved_0[0x18]; 7154 7155 u8 syndrome[0x20]; 7156 7157 u8 reserved_1[0x8]; 7158 u8 cqn[0x18]; 7159 7160 u8 reserved_2[0x20]; 7161}; 7162 7163struct mlx5_ifc_create_cq_in_bits { 7164 u8 opcode[0x10]; 7165 u8 reserved_0[0x10]; 7166 7167 u8 reserved_1[0x10]; 7168 u8 op_mod[0x10]; 7169 7170 u8 reserved_2[0x40]; 7171 7172 struct mlx5_ifc_cqc_bits cq_context; 7173 7174 u8 reserved_3[0x600]; 7175 7176 u8 pas[0][0x40]; 7177}; 7178 7179struct mlx5_ifc_config_int_moderation_out_bits { 7180 u8 status[0x8]; 7181 u8 reserved_0[0x18]; 7182 7183 u8 syndrome[0x20]; 7184 7185 u8 reserved_1[0x4]; 7186 u8 min_delay[0xc]; 7187 u8 int_vector[0x10]; 7188 7189 u8 reserved_2[0x20]; 7190}; 7191 7192enum { 7193 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7194 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7195}; 7196 7197struct mlx5_ifc_config_int_moderation_in_bits { 7198 u8 opcode[0x10]; 7199 u8 reserved_0[0x10]; 7200 7201 u8 reserved_1[0x10]; 7202 u8 op_mod[0x10]; 7203 7204 u8 reserved_2[0x4]; 7205 u8 min_delay[0xc]; 7206 u8 int_vector[0x10]; 7207 7208 u8 reserved_3[0x20]; 7209}; 7210 7211struct mlx5_ifc_attach_to_mcg_out_bits { 7212 u8 status[0x8]; 7213 u8 reserved_0[0x18]; 7214 7215 u8 syndrome[0x20]; 7216 7217 u8 reserved_1[0x40]; 7218}; 7219 7220struct mlx5_ifc_attach_to_mcg_in_bits { 7221 u8 opcode[0x10]; 7222 u8 reserved_0[0x10]; 7223 7224 u8 reserved_1[0x10]; 7225 u8 op_mod[0x10]; 7226 7227 u8 reserved_2[0x8]; 7228 u8 qpn[0x18]; 7229 7230 u8 reserved_3[0x20]; 7231 7232 u8 multicast_gid[16][0x8]; 7233}; 7234 7235struct mlx5_ifc_arm_xrc_srq_out_bits { 7236 u8 status[0x8]; 7237 u8 reserved_0[0x18]; 7238 7239 u8 syndrome[0x20]; 7240 7241 u8 reserved_1[0x40]; 7242}; 7243 7244enum { 7245 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7246}; 7247 7248struct mlx5_ifc_arm_xrc_srq_in_bits { 7249 u8 opcode[0x10]; 7250 u8 reserved_0[0x10]; 7251 7252 u8 reserved_1[0x10]; 7253 u8 op_mod[0x10]; 7254 7255 u8 reserved_2[0x8]; 7256 u8 xrc_srqn[0x18]; 7257 7258 u8 reserved_3[0x10]; 7259 u8 lwm[0x10]; 7260}; 7261 7262struct mlx5_ifc_arm_rq_out_bits { 7263 u8 status[0x8]; 7264 u8 reserved_0[0x18]; 7265 7266 u8 syndrome[0x20]; 7267 7268 u8 reserved_1[0x40]; 7269}; 7270 7271enum { 7272 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7273}; 7274 7275struct mlx5_ifc_arm_rq_in_bits { 7276 u8 opcode[0x10]; 7277 u8 reserved_0[0x10]; 7278 7279 u8 reserved_1[0x10]; 7280 u8 op_mod[0x10]; 7281 7282 u8 reserved_2[0x8]; 7283 u8 srq_number[0x18]; 7284 7285 u8 reserved_3[0x10]; 7286 u8 lwm[0x10]; 7287}; 7288 7289struct mlx5_ifc_arm_dct_out_bits { 7290 u8 status[0x8]; 7291 u8 reserved_0[0x18]; 7292 7293 u8 syndrome[0x20]; 7294 7295 u8 reserved_1[0x40]; 7296}; 7297 7298struct mlx5_ifc_arm_dct_in_bits { 7299 u8 opcode[0x10]; 7300 u8 reserved_0[0x10]; 7301 7302 u8 reserved_1[0x10]; 7303 u8 op_mod[0x10]; 7304 7305 u8 reserved_2[0x8]; 7306 u8 dctn[0x18]; 7307 7308 u8 reserved_3[0x20]; 7309}; 7310 7311struct mlx5_ifc_alloc_xrcd_out_bits { 7312 u8 status[0x8]; 7313 u8 reserved_0[0x18]; 7314 7315 u8 syndrome[0x20]; 7316 7317 u8 reserved_1[0x8]; 7318 u8 xrcd[0x18]; 7319 7320 u8 reserved_2[0x20]; 7321}; 7322 7323struct mlx5_ifc_alloc_xrcd_in_bits { 7324 u8 opcode[0x10]; 7325 u8 reserved_0[0x10]; 7326 7327 u8 reserved_1[0x10]; 7328 u8 op_mod[0x10]; 7329 7330 u8 reserved_2[0x40]; 7331}; 7332 7333struct mlx5_ifc_alloc_uar_out_bits { 7334 u8 status[0x8]; 7335 u8 reserved_0[0x18]; 7336 7337 u8 syndrome[0x20]; 7338 7339 u8 reserved_1[0x8]; 7340 u8 uar[0x18]; 7341 7342 u8 reserved_2[0x20]; 7343}; 7344 7345struct mlx5_ifc_alloc_uar_in_bits { 7346 u8 opcode[0x10]; 7347 u8 reserved_0[0x10]; 7348 7349 u8 reserved_1[0x10]; 7350 u8 op_mod[0x10]; 7351 7352 u8 reserved_2[0x40]; 7353}; 7354 7355struct mlx5_ifc_alloc_transport_domain_out_bits { 7356 u8 status[0x8]; 7357 u8 reserved_0[0x18]; 7358 7359 u8 syndrome[0x20]; 7360 7361 u8 reserved_1[0x8]; 7362 u8 transport_domain[0x18]; 7363 7364 u8 reserved_2[0x20]; 7365}; 7366 7367struct mlx5_ifc_alloc_transport_domain_in_bits { 7368 u8 opcode[0x10]; 7369 u8 reserved_0[0x10]; 7370 7371 u8 reserved_1[0x10]; 7372 u8 op_mod[0x10]; 7373 7374 u8 reserved_2[0x40]; 7375}; 7376 7377struct mlx5_ifc_alloc_q_counter_out_bits { 7378 u8 status[0x8]; 7379 u8 reserved_0[0x18]; 7380 7381 u8 syndrome[0x20]; 7382 7383 u8 reserved_1[0x18]; 7384 u8 counter_set_id[0x8]; 7385 7386 u8 reserved_2[0x20]; 7387}; 7388 7389struct mlx5_ifc_alloc_q_counter_in_bits { 7390 u8 opcode[0x10]; 7391 u8 reserved_0[0x10]; 7392 7393 u8 reserved_1[0x10]; 7394 u8 op_mod[0x10]; 7395 7396 u8 reserved_2[0x40]; 7397}; 7398 7399struct mlx5_ifc_alloc_pd_out_bits { 7400 u8 status[0x8]; 7401 u8 reserved_0[0x18]; 7402 7403 u8 syndrome[0x20]; 7404 7405 u8 reserved_1[0x8]; 7406 u8 pd[0x18]; 7407 7408 u8 reserved_2[0x20]; 7409}; 7410 7411struct mlx5_ifc_alloc_pd_in_bits { 7412 u8 opcode[0x10]; 7413 u8 reserved_0[0x10]; 7414 7415 u8 reserved_1[0x10]; 7416 u8 op_mod[0x10]; 7417 7418 u8 reserved_2[0x40]; 7419}; 7420 7421struct mlx5_ifc_alloc_flow_counter_out_bits { 7422 u8 status[0x8]; 7423 u8 reserved_0[0x18]; 7424 7425 u8 syndrome[0x20]; 7426 7427 u8 reserved_1[0x10]; 7428 u8 flow_counter_id[0x10]; 7429 7430 u8 reserved_2[0x20]; 7431}; 7432 7433struct mlx5_ifc_alloc_flow_counter_in_bits { 7434 u8 opcode[0x10]; 7435 u8 reserved_0[0x10]; 7436 7437 u8 reserved_1[0x10]; 7438 u8 op_mod[0x10]; 7439 7440 u8 reserved_2[0x40]; 7441}; 7442 7443struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7444 u8 status[0x8]; 7445 u8 reserved_0[0x18]; 7446 7447 u8 syndrome[0x20]; 7448 7449 u8 reserved_1[0x40]; 7450}; 7451 7452struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7453 u8 opcode[0x10]; 7454 u8 reserved_0[0x10]; 7455 7456 u8 reserved_1[0x10]; 7457 u8 op_mod[0x10]; 7458 7459 u8 reserved_2[0x20]; 7460 7461 u8 reserved_3[0x10]; 7462 u8 vxlan_udp_port[0x10]; 7463}; 7464 7465struct mlx5_ifc_activate_tracer_out_bits { 7466 u8 status[0x8]; 7467 u8 reserved_0[0x18]; 7468 7469 u8 syndrome[0x20]; 7470 7471 u8 reserved_1[0x40]; 7472}; 7473 7474struct mlx5_ifc_activate_tracer_in_bits { 7475 u8 opcode[0x10]; 7476 u8 reserved_0[0x10]; 7477 7478 u8 reserved_1[0x10]; 7479 u8 op_mod[0x10]; 7480 7481 u8 mkey[0x20]; 7482 7483 u8 reserved_2[0x20]; 7484}; 7485 7486struct mlx5_ifc_set_rate_limit_out_bits { 7487 u8 status[0x8]; 7488 u8 reserved_at_8[0x18]; 7489 7490 u8 syndrome[0x20]; 7491 7492 u8 reserved_at_40[0x40]; 7493}; 7494 7495struct mlx5_ifc_set_rate_limit_in_bits { 7496 u8 opcode[0x10]; 7497 u8 reserved_at_10[0x10]; 7498 7499 u8 reserved_at_20[0x10]; 7500 u8 op_mod[0x10]; 7501 7502 u8 reserved_at_40[0x10]; 7503 u8 rate_limit_index[0x10]; 7504 7505 u8 reserved_at_60[0x20]; 7506 7507 u8 rate_limit[0x20]; 7508 u8 burst_upper_bound[0x20]; 7509}; 7510 7511struct mlx5_ifc_access_register_out_bits { 7512 u8 status[0x8]; 7513 u8 reserved_0[0x18]; 7514 7515 u8 syndrome[0x20]; 7516 7517 u8 reserved_1[0x40]; 7518 7519 u8 register_data[0][0x20]; 7520}; 7521 7522enum { 7523 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7524 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7525}; 7526 7527struct mlx5_ifc_access_register_in_bits { 7528 u8 opcode[0x10]; 7529 u8 reserved_0[0x10]; 7530 7531 u8 reserved_1[0x10]; 7532 u8 op_mod[0x10]; 7533 7534 u8 reserved_2[0x10]; 7535 u8 register_id[0x10]; 7536 7537 u8 argument[0x20]; 7538 7539 u8 register_data[0][0x20]; 7540}; 7541 7542struct mlx5_ifc_sltp_reg_bits { 7543 u8 status[0x4]; 7544 u8 version[0x4]; 7545 u8 local_port[0x8]; 7546 u8 pnat[0x2]; 7547 u8 reserved_0[0x2]; 7548 u8 lane[0x4]; 7549 u8 reserved_1[0x8]; 7550 7551 u8 reserved_2[0x20]; 7552 7553 u8 reserved_3[0x7]; 7554 u8 polarity[0x1]; 7555 u8 ob_tap0[0x8]; 7556 u8 ob_tap1[0x8]; 7557 u8 ob_tap2[0x8]; 7558 7559 u8 reserved_4[0xc]; 7560 u8 ob_preemp_mode[0x4]; 7561 u8 ob_reg[0x8]; 7562 u8 ob_bias[0x8]; 7563 7564 u8 reserved_5[0x20]; 7565}; 7566 7567struct mlx5_ifc_slrp_reg_bits { 7568 u8 status[0x4]; 7569 u8 version[0x4]; 7570 u8 local_port[0x8]; 7571 u8 pnat[0x2]; 7572 u8 reserved_0[0x2]; 7573 u8 lane[0x4]; 7574 u8 reserved_1[0x8]; 7575 7576 u8 ib_sel[0x2]; 7577 u8 reserved_2[0x11]; 7578 u8 dp_sel[0x1]; 7579 u8 dp90sel[0x4]; 7580 u8 mix90phase[0x8]; 7581 7582 u8 ffe_tap0[0x8]; 7583 u8 ffe_tap1[0x8]; 7584 u8 ffe_tap2[0x8]; 7585 u8 ffe_tap3[0x8]; 7586 7587 u8 ffe_tap4[0x8]; 7588 u8 ffe_tap5[0x8]; 7589 u8 ffe_tap6[0x8]; 7590 u8 ffe_tap7[0x8]; 7591 7592 u8 ffe_tap8[0x8]; 7593 u8 mixerbias_tap_amp[0x8]; 7594 u8 reserved_3[0x7]; 7595 u8 ffe_tap_en[0x9]; 7596 7597 u8 ffe_tap_offset0[0x8]; 7598 u8 ffe_tap_offset1[0x8]; 7599 u8 slicer_offset0[0x10]; 7600 7601 u8 mixer_offset0[0x10]; 7602 u8 mixer_offset1[0x10]; 7603 7604 u8 mixerbgn_inp[0x8]; 7605 u8 mixerbgn_inn[0x8]; 7606 u8 mixerbgn_refp[0x8]; 7607 u8 mixerbgn_refn[0x8]; 7608 7609 u8 sel_slicer_lctrl_h[0x1]; 7610 u8 sel_slicer_lctrl_l[0x1]; 7611 u8 reserved_4[0x1]; 7612 u8 ref_mixer_vreg[0x5]; 7613 u8 slicer_gctrl[0x8]; 7614 u8 lctrl_input[0x8]; 7615 u8 mixer_offset_cm1[0x8]; 7616 7617 u8 common_mode[0x6]; 7618 u8 reserved_5[0x1]; 7619 u8 mixer_offset_cm0[0x9]; 7620 u8 reserved_6[0x7]; 7621 u8 slicer_offset_cm[0x9]; 7622}; 7623 7624struct mlx5_ifc_slrg_reg_bits { 7625 u8 status[0x4]; 7626 u8 version[0x4]; 7627 u8 local_port[0x8]; 7628 u8 pnat[0x2]; 7629 u8 reserved_0[0x2]; 7630 u8 lane[0x4]; 7631 u8 reserved_1[0x8]; 7632 7633 u8 time_to_link_up[0x10]; 7634 u8 reserved_2[0xc]; 7635 u8 grade_lane_speed[0x4]; 7636 7637 u8 grade_version[0x8]; 7638 u8 grade[0x18]; 7639 7640 u8 reserved_3[0x4]; 7641 u8 height_grade_type[0x4]; 7642 u8 height_grade[0x18]; 7643 7644 u8 height_dz[0x10]; 7645 u8 height_dv[0x10]; 7646 7647 u8 reserved_4[0x10]; 7648 u8 height_sigma[0x10]; 7649 7650 u8 reserved_5[0x20]; 7651 7652 u8 reserved_6[0x4]; 7653 u8 phase_grade_type[0x4]; 7654 u8 phase_grade[0x18]; 7655 7656 u8 reserved_7[0x8]; 7657 u8 phase_eo_pos[0x8]; 7658 u8 reserved_8[0x8]; 7659 u8 phase_eo_neg[0x8]; 7660 7661 u8 ffe_set_tested[0x10]; 7662 u8 test_errors_per_lane[0x10]; 7663}; 7664 7665struct mlx5_ifc_pvlc_reg_bits { 7666 u8 reserved_0[0x8]; 7667 u8 local_port[0x8]; 7668 u8 reserved_1[0x10]; 7669 7670 u8 reserved_2[0x1c]; 7671 u8 vl_hw_cap[0x4]; 7672 7673 u8 reserved_3[0x1c]; 7674 u8 vl_admin[0x4]; 7675 7676 u8 reserved_4[0x1c]; 7677 u8 vl_operational[0x4]; 7678}; 7679 7680struct mlx5_ifc_pude_reg_bits { 7681 u8 swid[0x8]; 7682 u8 local_port[0x8]; 7683 u8 reserved_0[0x4]; 7684 u8 admin_status[0x4]; 7685 u8 reserved_1[0x4]; 7686 u8 oper_status[0x4]; 7687 7688 u8 reserved_2[0x60]; 7689}; 7690 7691enum { 7692 MLX5_PTYS_REG_PROTO_MASK_INFINIBAND = 0x1, 7693 MLX5_PTYS_REG_PROTO_MASK_ETHERNET = 0x4, 7694}; 7695 7696struct mlx5_ifc_ptys_reg_bits { 7697 u8 reserved_0[0x1]; 7698 u8 an_disable_admin[0x1]; 7699 u8 an_disable_cap[0x1]; 7700 u8 reserved_1[0x4]; 7701 u8 force_tx_aba_param[0x1]; 7702 u8 local_port[0x8]; 7703 u8 reserved_2[0xd]; 7704 u8 proto_mask[0x3]; 7705 7706 u8 an_status[0x4]; 7707 u8 reserved_3[0xc]; 7708 u8 data_rate_oper[0x10]; 7709 7710 u8 fc_proto_capability[0x20]; 7711 7712 u8 eth_proto_capability[0x20]; 7713 7714 u8 ib_link_width_capability[0x10]; 7715 u8 ib_proto_capability[0x10]; 7716 7717 u8 fc_proto_admin[0x20]; 7718 7719 u8 eth_proto_admin[0x20]; 7720 7721 u8 ib_link_width_admin[0x10]; 7722 u8 ib_proto_admin[0x10]; 7723 7724 u8 fc_proto_oper[0x20]; 7725 7726 u8 eth_proto_oper[0x20]; 7727 7728 u8 ib_link_width_oper[0x10]; 7729 u8 ib_proto_oper[0x10]; 7730 7731 u8 reserved_4[0x20]; 7732 7733 u8 eth_proto_lp_advertise[0x20]; 7734 7735 u8 reserved_5[0x60]; 7736}; 7737 7738struct mlx5_ifc_ptas_reg_bits { 7739 u8 reserved_0[0x20]; 7740 7741 u8 algorithm_options[0x10]; 7742 u8 reserved_1[0x4]; 7743 u8 repetitions_mode[0x4]; 7744 u8 num_of_repetitions[0x8]; 7745 7746 u8 grade_version[0x8]; 7747 u8 height_grade_type[0x4]; 7748 u8 phase_grade_type[0x4]; 7749 u8 height_grade_weight[0x8]; 7750 u8 phase_grade_weight[0x8]; 7751 7752 u8 gisim_measure_bits[0x10]; 7753 u8 adaptive_tap_measure_bits[0x10]; 7754 7755 u8 ber_bath_high_error_threshold[0x10]; 7756 u8 ber_bath_mid_error_threshold[0x10]; 7757 7758 u8 ber_bath_low_error_threshold[0x10]; 7759 u8 one_ratio_high_threshold[0x10]; 7760 7761 u8 one_ratio_high_mid_threshold[0x10]; 7762 u8 one_ratio_low_mid_threshold[0x10]; 7763 7764 u8 one_ratio_low_threshold[0x10]; 7765 u8 ndeo_error_threshold[0x10]; 7766 7767 u8 mixer_offset_step_size[0x10]; 7768 u8 reserved_2[0x8]; 7769 u8 mix90_phase_for_voltage_bath[0x8]; 7770 7771 u8 mixer_offset_start[0x10]; 7772 u8 mixer_offset_end[0x10]; 7773 7774 u8 reserved_3[0x15]; 7775 u8 ber_test_time[0xb]; 7776}; 7777 7778struct mlx5_ifc_pspa_reg_bits { 7779 u8 swid[0x8]; 7780 u8 local_port[0x8]; 7781 u8 sub_port[0x8]; 7782 u8 reserved_0[0x8]; 7783 7784 u8 reserved_1[0x20]; 7785}; 7786 7787struct mlx5_ifc_ppsc_reg_bits { 7788 u8 reserved_0[0x8]; 7789 u8 local_port[0x8]; 7790 u8 reserved_1[0x10]; 7791 7792 u8 reserved_2[0x60]; 7793 7794 u8 reserved_3[0x1c]; 7795 u8 wrps_admin[0x4]; 7796 7797 u8 reserved_4[0x1c]; 7798 u8 wrps_status[0x4]; 7799 7800 u8 up_th_vld[0x1]; 7801 u8 down_th_vld[0x1]; 7802 u8 reserved_5[0x6]; 7803 u8 up_threshold[0x8]; 7804 u8 reserved_6[0x8]; 7805 u8 down_threshold[0x8]; 7806 7807 u8 reserved_7[0x20]; 7808 7809 u8 reserved_8[0x1c]; 7810 u8 srps_admin[0x4]; 7811 7812 u8 reserved_9[0x60]; 7813}; 7814 7815struct mlx5_ifc_pplr_reg_bits { 7816 u8 reserved_0[0x8]; 7817 u8 local_port[0x8]; 7818 u8 reserved_1[0x10]; 7819 7820 u8 reserved_2[0x8]; 7821 u8 lb_cap[0x8]; 7822 u8 reserved_3[0x8]; 7823 u8 lb_en[0x8]; 7824}; 7825 7826struct mlx5_ifc_pplm_reg_bits { 7827 u8 reserved_0[0x8]; 7828 u8 local_port[0x8]; 7829 u8 reserved_1[0x10]; 7830 7831 u8 reserved_2[0x20]; 7832 7833 u8 port_profile_mode[0x8]; 7834 u8 static_port_profile[0x8]; 7835 u8 active_port_profile[0x8]; 7836 u8 reserved_3[0x8]; 7837 7838 u8 retransmission_active[0x8]; 7839 u8 fec_mode_active[0x18]; 7840 7841 u8 reserved_4[0x10]; 7842 u8 v_100g_fec_override_cap[0x4]; 7843 u8 v_50g_fec_override_cap[0x4]; 7844 u8 v_25g_fec_override_cap[0x4]; 7845 u8 v_10g_40g_fec_override_cap[0x4]; 7846 7847 u8 reserved_5[0x10]; 7848 u8 v_100g_fec_override_admin[0x4]; 7849 u8 v_50g_fec_override_admin[0x4]; 7850 u8 v_25g_fec_override_admin[0x4]; 7851 u8 v_10g_40g_fec_override_admin[0x4]; 7852}; 7853 7854struct mlx5_ifc_ppll_reg_bits { 7855 u8 num_pll_groups[0x8]; 7856 u8 pll_group[0x8]; 7857 u8 reserved_0[0x4]; 7858 u8 num_plls[0x4]; 7859 u8 reserved_1[0x8]; 7860 7861 u8 reserved_2[0x1f]; 7862 u8 ae[0x1]; 7863 7864 u8 pll_status[4][0x40]; 7865}; 7866 7867struct mlx5_ifc_ppad_reg_bits { 7868 u8 reserved_0[0x3]; 7869 u8 single_mac[0x1]; 7870 u8 reserved_1[0x4]; 7871 u8 local_port[0x8]; 7872 u8 mac_47_32[0x10]; 7873 7874 u8 mac_31_0[0x20]; 7875 7876 u8 reserved_2[0x40]; 7877}; 7878 7879struct mlx5_ifc_pmtu_reg_bits { 7880 u8 reserved_0[0x8]; 7881 u8 local_port[0x8]; 7882 u8 reserved_1[0x10]; 7883 7884 u8 max_mtu[0x10]; 7885 u8 reserved_2[0x10]; 7886 7887 u8 admin_mtu[0x10]; 7888 u8 reserved_3[0x10]; 7889 7890 u8 oper_mtu[0x10]; 7891 u8 reserved_4[0x10]; 7892}; 7893 7894struct mlx5_ifc_pmpr_reg_bits { 7895 u8 reserved_0[0x8]; 7896 u8 module[0x8]; 7897 u8 reserved_1[0x10]; 7898 7899 u8 reserved_2[0x18]; 7900 u8 attenuation_5g[0x8]; 7901 7902 u8 reserved_3[0x18]; 7903 u8 attenuation_7g[0x8]; 7904 7905 u8 reserved_4[0x18]; 7906 u8 attenuation_12g[0x8]; 7907}; 7908 7909struct mlx5_ifc_pmpe_reg_bits { 7910 u8 reserved_0[0x8]; 7911 u8 module[0x8]; 7912 u8 reserved_1[0xc]; 7913 u8 module_status[0x4]; 7914 7915 u8 reserved_2[0x14]; 7916 u8 error_type[0x4]; 7917 u8 reserved_3[0x8]; 7918 7919 u8 reserved_4[0x40]; 7920}; 7921 7922struct mlx5_ifc_pmpc_reg_bits { 7923 u8 module_state_updated[32][0x8]; 7924}; 7925 7926struct mlx5_ifc_pmlpn_reg_bits { 7927 u8 reserved_0[0x4]; 7928 u8 mlpn_status[0x4]; 7929 u8 local_port[0x8]; 7930 u8 reserved_1[0x10]; 7931 7932 u8 e[0x1]; 7933 u8 reserved_2[0x1f]; 7934}; 7935 7936struct mlx5_ifc_pmlp_reg_bits { 7937 u8 rxtx[0x1]; 7938 u8 reserved_0[0x7]; 7939 u8 local_port[0x8]; 7940 u8 reserved_1[0x8]; 7941 u8 width[0x8]; 7942 7943 u8 lane0_module_mapping[0x20]; 7944 7945 u8 lane1_module_mapping[0x20]; 7946 7947 u8 lane2_module_mapping[0x20]; 7948 7949 u8 lane3_module_mapping[0x20]; 7950 7951 u8 reserved_2[0x160]; 7952}; 7953 7954struct mlx5_ifc_pmaos_reg_bits { 7955 u8 reserved_0[0x8]; 7956 u8 module[0x8]; 7957 u8 reserved_1[0x4]; 7958 u8 admin_status[0x4]; 7959 u8 reserved_2[0x4]; 7960 u8 oper_status[0x4]; 7961 7962 u8 ase[0x1]; 7963 u8 ee[0x1]; 7964 u8 reserved_3[0x12]; 7965 u8 error_type[0x4]; 7966 u8 reserved_4[0x6]; 7967 u8 e[0x2]; 7968 7969 u8 reserved_5[0x40]; 7970}; 7971 7972struct mlx5_ifc_plpc_reg_bits { 7973 u8 reserved_0[0x4]; 7974 u8 profile_id[0xc]; 7975 u8 reserved_1[0x4]; 7976 u8 proto_mask[0x4]; 7977 u8 reserved_2[0x8]; 7978 7979 u8 reserved_3[0x10]; 7980 u8 lane_speed[0x10]; 7981 7982 u8 reserved_4[0x17]; 7983 u8 lpbf[0x1]; 7984 u8 fec_mode_policy[0x8]; 7985 7986 u8 retransmission_capability[0x8]; 7987 u8 fec_mode_capability[0x18]; 7988 7989 u8 retransmission_support_admin[0x8]; 7990 u8 fec_mode_support_admin[0x18]; 7991 7992 u8 retransmission_request_admin[0x8]; 7993 u8 fec_mode_request_admin[0x18]; 7994 7995 u8 reserved_5[0x80]; 7996}; 7997 7998struct mlx5_ifc_pll_status_data_bits { 7999 u8 reserved_0[0x1]; 8000 u8 lock_cal[0x1]; 8001 u8 lock_status[0x2]; 8002 u8 reserved_1[0x2]; 8003 u8 algo_f_ctrl[0xa]; 8004 u8 analog_algo_num_var[0x6]; 8005 u8 f_ctrl_measure[0xa]; 8006 8007 u8 reserved_2[0x2]; 8008 u8 analog_var[0x6]; 8009 u8 reserved_3[0x2]; 8010 u8 high_var[0x6]; 8011 u8 reserved_4[0x2]; 8012 u8 low_var[0x6]; 8013 u8 reserved_5[0x2]; 8014 u8 mid_val[0x6]; 8015}; 8016 8017struct mlx5_ifc_plib_reg_bits { 8018 u8 reserved_0[0x8]; 8019 u8 local_port[0x8]; 8020 u8 reserved_1[0x8]; 8021 u8 ib_port[0x8]; 8022 8023 u8 reserved_2[0x60]; 8024}; 8025 8026struct mlx5_ifc_plbf_reg_bits { 8027 u8 reserved_0[0x8]; 8028 u8 local_port[0x8]; 8029 u8 reserved_1[0xd]; 8030 u8 lbf_mode[0x3]; 8031 8032 u8 reserved_2[0x20]; 8033}; 8034 8035struct mlx5_ifc_pipg_reg_bits { 8036 u8 reserved_0[0x8]; 8037 u8 local_port[0x8]; 8038 u8 reserved_1[0x10]; 8039 8040 u8 dic[0x1]; 8041 u8 reserved_2[0x19]; 8042 u8 ipg[0x4]; 8043 u8 reserved_3[0x2]; 8044}; 8045 8046struct mlx5_ifc_pifr_reg_bits { 8047 u8 reserved_0[0x8]; 8048 u8 local_port[0x8]; 8049 u8 reserved_1[0x10]; 8050 8051 u8 reserved_2[0xe0]; 8052 8053 u8 port_filter[8][0x20]; 8054 8055 u8 port_filter_update_en[8][0x20]; 8056}; 8057 8058struct mlx5_ifc_phys_layer_cntrs_bits { 8059 u8 time_since_last_clear_high[0x20]; 8060 8061 u8 time_since_last_clear_low[0x20]; 8062 8063 u8 symbol_errors_high[0x20]; 8064 8065 u8 symbol_errors_low[0x20]; 8066 8067 u8 sync_headers_errors_high[0x20]; 8068 8069 u8 sync_headers_errors_low[0x20]; 8070 8071 u8 edpl_bip_errors_lane0_high[0x20]; 8072 8073 u8 edpl_bip_errors_lane0_low[0x20]; 8074 8075 u8 edpl_bip_errors_lane1_high[0x20]; 8076 8077 u8 edpl_bip_errors_lane1_low[0x20]; 8078 8079 u8 edpl_bip_errors_lane2_high[0x20]; 8080 8081 u8 edpl_bip_errors_lane2_low[0x20]; 8082 8083 u8 edpl_bip_errors_lane3_high[0x20]; 8084 8085 u8 edpl_bip_errors_lane3_low[0x20]; 8086 8087 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 8088 8089 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 8090 8091 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 8092 8093 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 8094 8095 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 8096 8097 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 8098 8099 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 8100 8101 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 8102 8103 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 8104 8105 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 8106 8107 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 8108 8109 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 8110 8111 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 8112 8113 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 8114 8115 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 8116 8117 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 8118 8119 u8 rs_fec_corrected_blocks_high[0x20]; 8120 8121 u8 rs_fec_corrected_blocks_low[0x20]; 8122 8123 u8 rs_fec_uncorrectable_blocks_high[0x20]; 8124 8125 u8 rs_fec_uncorrectable_blocks_low[0x20]; 8126 8127 u8 rs_fec_no_errors_blocks_high[0x20]; 8128 8129 u8 rs_fec_no_errors_blocks_low[0x20]; 8130 8131 u8 rs_fec_single_error_blocks_high[0x20]; 8132 8133 u8 rs_fec_single_error_blocks_low[0x20]; 8134 8135 u8 rs_fec_corrected_symbols_total_high[0x20]; 8136 8137 u8 rs_fec_corrected_symbols_total_low[0x20]; 8138 8139 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 8140 8141 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 8142 8143 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 8144 8145 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 8146 8147 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 8148 8149 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 8150 8151 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 8152 8153 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 8154 8155 u8 link_down_events[0x20]; 8156 8157 u8 successful_recovery_events[0x20]; 8158 8159 u8 reserved_0[0x180]; 8160}; 8161 8162struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 8163 u8 symbol_error_counter[0x10]; 8164 8165 u8 link_error_recovery_counter[0x8]; 8166 8167 u8 link_downed_counter[0x8]; 8168 8169 u8 port_rcv_errors[0x10]; 8170 8171 u8 port_rcv_remote_physical_errors[0x10]; 8172 8173 u8 port_rcv_switch_relay_errors[0x10]; 8174 8175 u8 port_xmit_discards[0x10]; 8176 8177 u8 port_xmit_constraint_errors[0x8]; 8178 8179 u8 port_rcv_constraint_errors[0x8]; 8180 8181 u8 reserved_at_70[0x8]; 8182 8183 u8 link_overrun_errors[0x8]; 8184 8185 u8 reserved_at_80[0x10]; 8186 8187 u8 vl_15_dropped[0x10]; 8188 8189 u8 reserved_at_a0[0xa0]; 8190}; 8191 8192struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 8193 u8 time_since_last_clear_high[0x20]; 8194 8195 u8 time_since_last_clear_low[0x20]; 8196 8197 u8 phy_received_bits_high[0x20]; 8198 8199 u8 phy_received_bits_low[0x20]; 8200 8201 u8 phy_symbol_errors_high[0x20]; 8202 8203 u8 phy_symbol_errors_low[0x20]; 8204 8205 u8 phy_corrected_bits_high[0x20]; 8206 8207 u8 phy_corrected_bits_low[0x20]; 8208 8209 u8 phy_corrected_bits_lane0_high[0x20]; 8210 8211 u8 phy_corrected_bits_lane0_low[0x20]; 8212 8213 u8 phy_corrected_bits_lane1_high[0x20]; 8214 8215 u8 phy_corrected_bits_lane1_low[0x20]; 8216 8217 u8 phy_corrected_bits_lane2_high[0x20]; 8218 8219 u8 phy_corrected_bits_lane2_low[0x20]; 8220 8221 u8 phy_corrected_bits_lane3_high[0x20]; 8222 8223 u8 phy_corrected_bits_lane3_low[0x20]; 8224 8225 u8 reserved_at_200[0x5c0]; 8226}; 8227 8228struct mlx5_ifc_infiniband_port_cntrs_bits { 8229 u8 symbol_error_counter[0x10]; 8230 u8 link_error_recovery_counter[0x8]; 8231 u8 link_downed_counter[0x8]; 8232 8233 u8 port_rcv_errors[0x10]; 8234 u8 port_rcv_remote_physical_errors[0x10]; 8235 8236 u8 port_rcv_switch_relay_errors[0x10]; 8237 u8 port_xmit_discards[0x10]; 8238 8239 u8 port_xmit_constraint_errors[0x8]; 8240 u8 port_rcv_constraint_errors[0x8]; 8241 u8 reserved_0[0x8]; 8242 u8 local_link_integrity_errors[0x4]; 8243 u8 excessive_buffer_overrun_errors[0x4]; 8244 8245 u8 reserved_1[0x10]; 8246 u8 vl_15_dropped[0x10]; 8247 8248 u8 port_xmit_data[0x20]; 8249 8250 u8 port_rcv_data[0x20]; 8251 8252 u8 port_xmit_pkts[0x20]; 8253 8254 u8 port_rcv_pkts[0x20]; 8255 8256 u8 port_xmit_wait[0x20]; 8257 8258 u8 reserved_2[0x680]; 8259}; 8260 8261struct mlx5_ifc_phrr_reg_bits { 8262 u8 clr[0x1]; 8263 u8 reserved_0[0x7]; 8264 u8 local_port[0x8]; 8265 u8 reserved_1[0x10]; 8266 8267 u8 hist_group[0x8]; 8268 u8 reserved_2[0x10]; 8269 u8 hist_id[0x8]; 8270 8271 u8 reserved_3[0x40]; 8272 8273 u8 time_since_last_clear_high[0x20]; 8274 8275 u8 time_since_last_clear_low[0x20]; 8276 8277 u8 bin[10][0x20]; 8278}; 8279 8280struct mlx5_ifc_phbr_for_prio_reg_bits { 8281 u8 reserved_0[0x18]; 8282 u8 prio[0x8]; 8283}; 8284 8285struct mlx5_ifc_phbr_for_port_tclass_reg_bits { 8286 u8 reserved_0[0x18]; 8287 u8 tclass[0x8]; 8288}; 8289 8290struct mlx5_ifc_phbr_binding_reg_bits { 8291 u8 opcode[0x4]; 8292 u8 reserved_0[0x4]; 8293 u8 local_port[0x8]; 8294 u8 pnat[0x2]; 8295 u8 reserved_1[0xe]; 8296 8297 u8 hist_group[0x8]; 8298 u8 reserved_2[0x10]; 8299 u8 hist_id[0x8]; 8300 8301 u8 reserved_3[0x10]; 8302 u8 hist_type[0x10]; 8303 8304 u8 hist_parameters[0x20]; 8305 8306 u8 hist_min_value[0x20]; 8307 8308 u8 hist_max_value[0x20]; 8309 8310 u8 sample_time[0x20]; 8311}; 8312 8313enum { 8314 MLX5_PFCC_REG_PPAN_DISABLED = 0x0, 8315 MLX5_PFCC_REG_PPAN_ENABLED = 0x1, 8316}; 8317 8318struct mlx5_ifc_pfcc_reg_bits { 8319 u8 dcbx_operation_type[0x2]; 8320 u8 cap_local_admin[0x1]; 8321 u8 cap_remote_admin[0x1]; 8322 u8 reserved_0[0x4]; 8323 u8 local_port[0x8]; 8324 u8 pnat[0x2]; 8325 u8 reserved_1[0xc]; 8326 u8 shl_cap[0x1]; 8327 u8 shl_opr[0x1]; 8328 8329 u8 ppan[0x4]; 8330 u8 reserved_2[0x4]; 8331 u8 prio_mask_tx[0x8]; 8332 u8 reserved_3[0x8]; 8333 u8 prio_mask_rx[0x8]; 8334 8335 u8 pptx[0x1]; 8336 u8 aptx[0x1]; 8337 u8 reserved_4[0x6]; 8338 u8 pfctx[0x8]; 8339 u8 reserved_5[0x8]; 8340 u8 cbftx[0x8]; 8341 8342 u8 pprx[0x1]; 8343 u8 aprx[0x1]; 8344 u8 reserved_6[0x6]; 8345 u8 pfcrx[0x8]; 8346 u8 reserved_7[0x8]; 8347 u8 cbfrx[0x8]; 8348 8349 u8 device_stall_minor_watermark[0x10]; 8350 u8 device_stall_critical_watermark[0x10]; 8351 8352 u8 reserved_8[0x60]; 8353}; 8354 8355struct mlx5_ifc_pelc_reg_bits { 8356 u8 op[0x4]; 8357 u8 reserved_0[0x4]; 8358 u8 local_port[0x8]; 8359 u8 reserved_1[0x10]; 8360 8361 u8 op_admin[0x8]; 8362 u8 op_capability[0x8]; 8363 u8 op_request[0x8]; 8364 u8 op_active[0x8]; 8365 8366 u8 admin[0x40]; 8367 8368 u8 capability[0x40]; 8369 8370 u8 request[0x40]; 8371 8372 u8 active[0x40]; 8373 8374 u8 reserved_2[0x80]; 8375}; 8376 8377struct mlx5_ifc_peir_reg_bits { 8378 u8 reserved_0[0x8]; 8379 u8 local_port[0x8]; 8380 u8 reserved_1[0x10]; 8381 8382 u8 reserved_2[0xc]; 8383 u8 error_count[0x4]; 8384 u8 reserved_3[0x10]; 8385 8386 u8 reserved_4[0xc]; 8387 u8 lane[0x4]; 8388 u8 reserved_5[0x8]; 8389 u8 error_type[0x8]; 8390}; 8391 8392struct mlx5_ifc_qcam_access_reg_cap_mask { 8393 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 8394 u8 qpdpm[0x1]; 8395 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 8396 u8 qdpm[0x1]; 8397 u8 qpts[0x1]; 8398 u8 qcap[0x1]; 8399 u8 qcam_access_reg_cap_mask_0[0x1]; 8400}; 8401 8402struct mlx5_ifc_qcam_qos_feature_cap_mask { 8403 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 8404 u8 qpts_trust_both[0x1]; 8405}; 8406 8407struct mlx5_ifc_qcam_reg_bits { 8408 u8 reserved_at_0[0x8]; 8409 u8 feature_group[0x8]; 8410 u8 reserved_at_10[0x8]; 8411 u8 access_reg_group[0x8]; 8412 u8 reserved_at_20[0x20]; 8413 8414 union { 8415 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 8416 u8 reserved_at_0[0x80]; 8417 } qos_access_reg_cap_mask; 8418 8419 u8 reserved_at_c0[0x80]; 8420 8421 union { 8422 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 8423 u8 reserved_at_0[0x80]; 8424 } qos_feature_cap_mask; 8425 8426 u8 reserved_at_1c0[0x80]; 8427}; 8428 8429struct mlx5_ifc_pcap_reg_bits { 8430 u8 reserved_0[0x8]; 8431 u8 local_port[0x8]; 8432 u8 reserved_1[0x10]; 8433 8434 u8 port_capability_mask[4][0x20]; 8435}; 8436 8437struct mlx5_ifc_pbmc_reg_bits { 8438 u8 reserved_0[0x8]; 8439 u8 local_port[0x8]; 8440 u8 reserved_1[0x10]; 8441 8442 u8 xoff_timer_value[0x10]; 8443 u8 xoff_refresh[0x10]; 8444 8445 u8 reserved_2[0x10]; 8446 u8 port_buffer_size[0x10]; 8447 8448 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 8449 8450 u8 reserved_3[0x40]; 8451 8452 u8 port_shared_buffer[0x40]; 8453}; 8454 8455struct mlx5_ifc_paos_reg_bits { 8456 u8 swid[0x8]; 8457 u8 local_port[0x8]; 8458 u8 reserved_0[0x4]; 8459 u8 admin_status[0x4]; 8460 u8 reserved_1[0x4]; 8461 u8 oper_status[0x4]; 8462 8463 u8 ase[0x1]; 8464 u8 ee[0x1]; 8465 u8 reserved_2[0x1c]; 8466 u8 e[0x2]; 8467 8468 u8 reserved_3[0x40]; 8469}; 8470 8471struct mlx5_ifc_pamp_reg_bits { 8472 u8 reserved_0[0x8]; 8473 u8 opamp_group[0x8]; 8474 u8 reserved_1[0xc]; 8475 u8 opamp_group_type[0x4]; 8476 8477 u8 start_index[0x10]; 8478 u8 reserved_2[0x4]; 8479 u8 num_of_indices[0xc]; 8480 8481 u8 index_data[18][0x10]; 8482}; 8483 8484struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits { 8485 u8 llr_rx_cells_high[0x20]; 8486 8487 u8 llr_rx_cells_low[0x20]; 8488 8489 u8 llr_rx_error_high[0x20]; 8490 8491 u8 llr_rx_error_low[0x20]; 8492 8493 u8 llr_rx_crc_error_high[0x20]; 8494 8495 u8 llr_rx_crc_error_low[0x20]; 8496 8497 u8 llr_tx_cells_high[0x20]; 8498 8499 u8 llr_tx_cells_low[0x20]; 8500 8501 u8 llr_tx_ret_cells_high[0x20]; 8502 8503 u8 llr_tx_ret_cells_low[0x20]; 8504 8505 u8 llr_tx_ret_events_high[0x20]; 8506 8507 u8 llr_tx_ret_events_low[0x20]; 8508 8509 u8 reserved_0[0x640]; 8510}; 8511 8512struct mlx5_ifc_lane_2_module_mapping_bits { 8513 u8 reserved_0[0x6]; 8514 u8 rx_lane[0x2]; 8515 u8 reserved_1[0x6]; 8516 u8 tx_lane[0x2]; 8517 u8 reserved_2[0x8]; 8518 u8 module[0x8]; 8519}; 8520 8521struct mlx5_ifc_eth_per_traffic_class_layout_bits { 8522 u8 transmit_queue_high[0x20]; 8523 8524 u8 transmit_queue_low[0x20]; 8525 8526 u8 reserved_0[0x780]; 8527}; 8528 8529struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits { 8530 u8 no_buffer_discard_uc_high[0x20]; 8531 8532 u8 no_buffer_discard_uc_low[0x20]; 8533 8534 u8 wred_discard_high[0x20]; 8535 8536 u8 wred_discard_low[0x20]; 8537 8538 u8 reserved_0[0x740]; 8539}; 8540 8541struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 8542 u8 rx_octets_high[0x20]; 8543 8544 u8 rx_octets_low[0x20]; 8545 8546 u8 reserved_0[0xc0]; 8547 8548 u8 rx_frames_high[0x20]; 8549 8550 u8 rx_frames_low[0x20]; 8551 8552 u8 tx_octets_high[0x20]; 8553 8554 u8 tx_octets_low[0x20]; 8555 8556 u8 reserved_1[0xc0]; 8557 8558 u8 tx_frames_high[0x20]; 8559 8560 u8 tx_frames_low[0x20]; 8561 8562 u8 rx_pause_high[0x20]; 8563 8564 u8 rx_pause_low[0x20]; 8565 8566 u8 rx_pause_duration_high[0x20]; 8567 8568 u8 rx_pause_duration_low[0x20]; 8569 8570 u8 tx_pause_high[0x20]; 8571 8572 u8 tx_pause_low[0x20]; 8573 8574 u8 tx_pause_duration_high[0x20]; 8575 8576 u8 tx_pause_duration_low[0x20]; 8577 8578 u8 rx_pause_transition_high[0x20]; 8579 8580 u8 rx_pause_transition_low[0x20]; 8581 8582 u8 rx_discards_high[0x20]; 8583 8584 u8 rx_discards_low[0x20]; 8585 8586 u8 device_stall_minor_watermark_cnt_high[0x20]; 8587 8588 u8 device_stall_minor_watermark_cnt_low[0x20]; 8589 8590 u8 device_stall_critical_watermark_cnt_high[0x20]; 8591 8592 u8 device_stall_critical_watermark_cnt_low[0x20]; 8593 8594 u8 reserved_2[0x340]; 8595}; 8596 8597struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 8598 u8 port_transmit_wait_high[0x20]; 8599 8600 u8 port_transmit_wait_low[0x20]; 8601 8602 u8 ecn_marked_high[0x20]; 8603 8604 u8 ecn_marked_low[0x20]; 8605 8606 u8 no_buffer_discard_mc_high[0x20]; 8607 8608 u8 no_buffer_discard_mc_low[0x20]; 8609 8610 u8 reserved_0[0x700]; 8611}; 8612 8613struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 8614 u8 a_frames_transmitted_ok_high[0x20]; 8615 8616 u8 a_frames_transmitted_ok_low[0x20]; 8617 8618 u8 a_frames_received_ok_high[0x20]; 8619 8620 u8 a_frames_received_ok_low[0x20]; 8621 8622 u8 a_frame_check_sequence_errors_high[0x20]; 8623 8624 u8 a_frame_check_sequence_errors_low[0x20]; 8625 8626 u8 a_alignment_errors_high[0x20]; 8627 8628 u8 a_alignment_errors_low[0x20]; 8629 8630 u8 a_octets_transmitted_ok_high[0x20]; 8631 8632 u8 a_octets_transmitted_ok_low[0x20]; 8633 8634 u8 a_octets_received_ok_high[0x20]; 8635 8636 u8 a_octets_received_ok_low[0x20]; 8637 8638 u8 a_multicast_frames_xmitted_ok_high[0x20]; 8639 8640 u8 a_multicast_frames_xmitted_ok_low[0x20]; 8641 8642 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 8643 8644 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 8645 8646 u8 a_multicast_frames_received_ok_high[0x20]; 8647 8648 u8 a_multicast_frames_received_ok_low[0x20]; 8649 8650 u8 a_broadcast_frames_recieved_ok_high[0x20]; 8651 8652 u8 a_broadcast_frames_recieved_ok_low[0x20]; 8653 8654 u8 a_in_range_length_errors_high[0x20]; 8655 8656 u8 a_in_range_length_errors_low[0x20]; 8657 8658 u8 a_out_of_range_length_field_high[0x20]; 8659 8660 u8 a_out_of_range_length_field_low[0x20]; 8661 8662 u8 a_frame_too_long_errors_high[0x20]; 8663 8664 u8 a_frame_too_long_errors_low[0x20]; 8665 8666 u8 a_symbol_error_during_carrier_high[0x20]; 8667 8668 u8 a_symbol_error_during_carrier_low[0x20]; 8669 8670 u8 a_mac_control_frames_transmitted_high[0x20]; 8671 8672 u8 a_mac_control_frames_transmitted_low[0x20]; 8673 8674 u8 a_mac_control_frames_received_high[0x20]; 8675 8676 u8 a_mac_control_frames_received_low[0x20]; 8677 8678 u8 a_unsupported_opcodes_received_high[0x20]; 8679 8680 u8 a_unsupported_opcodes_received_low[0x20]; 8681 8682 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 8683 8684 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 8685 8686 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 8687 8688 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 8689 8690 u8 reserved_0[0x300]; 8691}; 8692 8693struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 8694 u8 dot3stats_alignment_errors_high[0x20]; 8695 8696 u8 dot3stats_alignment_errors_low[0x20]; 8697 8698 u8 dot3stats_fcs_errors_high[0x20]; 8699 8700 u8 dot3stats_fcs_errors_low[0x20]; 8701 8702 u8 dot3stats_single_collision_frames_high[0x20]; 8703 8704 u8 dot3stats_single_collision_frames_low[0x20]; 8705 8706 u8 dot3stats_multiple_collision_frames_high[0x20]; 8707 8708 u8 dot3stats_multiple_collision_frames_low[0x20]; 8709 8710 u8 dot3stats_sqe_test_errors_high[0x20]; 8711 8712 u8 dot3stats_sqe_test_errors_low[0x20]; 8713 8714 u8 dot3stats_deferred_transmissions_high[0x20]; 8715 8716 u8 dot3stats_deferred_transmissions_low[0x20]; 8717 8718 u8 dot3stats_late_collisions_high[0x20]; 8719 8720 u8 dot3stats_late_collisions_low[0x20]; 8721 8722 u8 dot3stats_excessive_collisions_high[0x20]; 8723 8724 u8 dot3stats_excessive_collisions_low[0x20]; 8725 8726 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 8727 8728 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 8729 8730 u8 dot3stats_carrier_sense_errors_high[0x20]; 8731 8732 u8 dot3stats_carrier_sense_errors_low[0x20]; 8733 8734 u8 dot3stats_frame_too_longs_high[0x20]; 8735 8736 u8 dot3stats_frame_too_longs_low[0x20]; 8737 8738 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 8739 8740 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 8741 8742 u8 dot3stats_symbol_errors_high[0x20]; 8743 8744 u8 dot3stats_symbol_errors_low[0x20]; 8745 8746 u8 dot3control_in_unknown_opcodes_high[0x20]; 8747 8748 u8 dot3control_in_unknown_opcodes_low[0x20]; 8749 8750 u8 dot3in_pause_frames_high[0x20]; 8751 8752 u8 dot3in_pause_frames_low[0x20]; 8753 8754 u8 dot3out_pause_frames_high[0x20]; 8755 8756 u8 dot3out_pause_frames_low[0x20]; 8757 8758 u8 reserved_0[0x3c0]; 8759}; 8760 8761struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 8762 u8 if_in_octets_high[0x20]; 8763 8764 u8 if_in_octets_low[0x20]; 8765 8766 u8 if_in_ucast_pkts_high[0x20]; 8767 8768 u8 if_in_ucast_pkts_low[0x20]; 8769 8770 u8 if_in_discards_high[0x20]; 8771 8772 u8 if_in_discards_low[0x20]; 8773 8774 u8 if_in_errors_high[0x20]; 8775 8776 u8 if_in_errors_low[0x20]; 8777 8778 u8 if_in_unknown_protos_high[0x20]; 8779 8780 u8 if_in_unknown_protos_low[0x20]; 8781 8782 u8 if_out_octets_high[0x20]; 8783 8784 u8 if_out_octets_low[0x20]; 8785 8786 u8 if_out_ucast_pkts_high[0x20]; 8787 8788 u8 if_out_ucast_pkts_low[0x20]; 8789 8790 u8 if_out_discards_high[0x20]; 8791 8792 u8 if_out_discards_low[0x20]; 8793 8794 u8 if_out_errors_high[0x20]; 8795 8796 u8 if_out_errors_low[0x20]; 8797 8798 u8 if_in_multicast_pkts_high[0x20]; 8799 8800 u8 if_in_multicast_pkts_low[0x20]; 8801 8802 u8 if_in_broadcast_pkts_high[0x20]; 8803 8804 u8 if_in_broadcast_pkts_low[0x20]; 8805 8806 u8 if_out_multicast_pkts_high[0x20]; 8807 8808 u8 if_out_multicast_pkts_low[0x20]; 8809 8810 u8 if_out_broadcast_pkts_high[0x20]; 8811 8812 u8 if_out_broadcast_pkts_low[0x20]; 8813 8814 u8 reserved_0[0x480]; 8815}; 8816 8817struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 8818 u8 ether_stats_drop_events_high[0x20]; 8819 8820 u8 ether_stats_drop_events_low[0x20]; 8821 8822 u8 ether_stats_octets_high[0x20]; 8823 8824 u8 ether_stats_octets_low[0x20]; 8825 8826 u8 ether_stats_pkts_high[0x20]; 8827 8828 u8 ether_stats_pkts_low[0x20]; 8829 8830 u8 ether_stats_broadcast_pkts_high[0x20]; 8831 8832 u8 ether_stats_broadcast_pkts_low[0x20]; 8833 8834 u8 ether_stats_multicast_pkts_high[0x20]; 8835 8836 u8 ether_stats_multicast_pkts_low[0x20]; 8837 8838 u8 ether_stats_crc_align_errors_high[0x20]; 8839 8840 u8 ether_stats_crc_align_errors_low[0x20]; 8841 8842 u8 ether_stats_undersize_pkts_high[0x20]; 8843 8844 u8 ether_stats_undersize_pkts_low[0x20]; 8845 8846 u8 ether_stats_oversize_pkts_high[0x20]; 8847 8848 u8 ether_stats_oversize_pkts_low[0x20]; 8849 8850 u8 ether_stats_fragments_high[0x20]; 8851 8852 u8 ether_stats_fragments_low[0x20]; 8853 8854 u8 ether_stats_jabbers_high[0x20]; 8855 8856 u8 ether_stats_jabbers_low[0x20]; 8857 8858 u8 ether_stats_collisions_high[0x20]; 8859 8860 u8 ether_stats_collisions_low[0x20]; 8861 8862 u8 ether_stats_pkts64octets_high[0x20]; 8863 8864 u8 ether_stats_pkts64octets_low[0x20]; 8865 8866 u8 ether_stats_pkts65to127octets_high[0x20]; 8867 8868 u8 ether_stats_pkts65to127octets_low[0x20]; 8869 8870 u8 ether_stats_pkts128to255octets_high[0x20]; 8871 8872 u8 ether_stats_pkts128to255octets_low[0x20]; 8873 8874 u8 ether_stats_pkts256to511octets_high[0x20]; 8875 8876 u8 ether_stats_pkts256to511octets_low[0x20]; 8877 8878 u8 ether_stats_pkts512to1023octets_high[0x20]; 8879 8880 u8 ether_stats_pkts512to1023octets_low[0x20]; 8881 8882 u8 ether_stats_pkts1024to1518octets_high[0x20]; 8883 8884 u8 ether_stats_pkts1024to1518octets_low[0x20]; 8885 8886 u8 ether_stats_pkts1519to2047octets_high[0x20]; 8887 8888 u8 ether_stats_pkts1519to2047octets_low[0x20]; 8889 8890 u8 ether_stats_pkts2048to4095octets_high[0x20]; 8891 8892 u8 ether_stats_pkts2048to4095octets_low[0x20]; 8893 8894 u8 ether_stats_pkts4096to8191octets_high[0x20]; 8895 8896 u8 ether_stats_pkts4096to8191octets_low[0x20]; 8897 8898 u8 ether_stats_pkts8192to10239octets_high[0x20]; 8899 8900 u8 ether_stats_pkts8192to10239octets_low[0x20]; 8901 8902 u8 reserved_0[0x280]; 8903}; 8904 8905struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits { 8906 u8 symbol_error_counter[0x10]; 8907 u8 link_error_recovery_counter[0x8]; 8908 u8 link_downed_counter[0x8]; 8909 8910 u8 port_rcv_errors[0x10]; 8911 u8 port_rcv_remote_physical_errors[0x10]; 8912 8913 u8 port_rcv_switch_relay_errors[0x10]; 8914 u8 port_xmit_discards[0x10]; 8915 8916 u8 port_xmit_constraint_errors[0x8]; 8917 u8 port_rcv_constraint_errors[0x8]; 8918 u8 reserved_0[0x8]; 8919 u8 local_link_integrity_errors[0x4]; 8920 u8 excessive_buffer_overrun_errors[0x4]; 8921 8922 u8 reserved_1[0x10]; 8923 u8 vl_15_dropped[0x10]; 8924 8925 u8 port_xmit_data[0x20]; 8926 8927 u8 port_rcv_data[0x20]; 8928 8929 u8 port_xmit_pkts[0x20]; 8930 8931 u8 port_rcv_pkts[0x20]; 8932 8933 u8 port_xmit_wait[0x20]; 8934 8935 u8 reserved_2[0x680]; 8936}; 8937 8938struct mlx5_ifc_trc_tlb_reg_bits { 8939 u8 reserved_0[0x80]; 8940 8941 u8 tlb_addr[0][0x40]; 8942}; 8943 8944struct mlx5_ifc_trc_read_fifo_reg_bits { 8945 u8 reserved_0[0x10]; 8946 u8 requested_event_num[0x10]; 8947 8948 u8 reserved_1[0x20]; 8949 8950 u8 reserved_2[0x10]; 8951 u8 acual_event_num[0x10]; 8952 8953 u8 reserved_3[0x20]; 8954 8955 u8 event[0][0x40]; 8956}; 8957 8958struct mlx5_ifc_trc_lock_reg_bits { 8959 u8 reserved_0[0x1f]; 8960 u8 lock[0x1]; 8961 8962 u8 reserved_1[0x60]; 8963}; 8964 8965struct mlx5_ifc_trc_filter_reg_bits { 8966 u8 status[0x1]; 8967 u8 reserved_0[0xf]; 8968 u8 filter_index[0x10]; 8969 8970 u8 reserved_1[0x20]; 8971 8972 u8 filter_val[0x20]; 8973 8974 u8 reserved_2[0x1a0]; 8975}; 8976 8977struct mlx5_ifc_trc_event_reg_bits { 8978 u8 status[0x1]; 8979 u8 reserved_0[0xf]; 8980 u8 event_index[0x10]; 8981 8982 u8 reserved_1[0x20]; 8983 8984 u8 event_id[0x20]; 8985 8986 u8 event_selector_val[0x10]; 8987 u8 event_selector_size[0x10]; 8988 8989 u8 reserved_2[0x180]; 8990}; 8991 8992struct mlx5_ifc_trc_conf_reg_bits { 8993 u8 limit_en[0x1]; 8994 u8 reserved_0[0x3]; 8995 u8 dump_mode[0x4]; 8996 u8 reserved_1[0x15]; 8997 u8 state[0x3]; 8998 8999 u8 reserved_2[0x20]; 9000 9001 u8 limit_event_index[0x20]; 9002 9003 u8 mkey[0x20]; 9004 9005 u8 fifo_ready_ev_num[0x20]; 9006 9007 u8 reserved_3[0x160]; 9008}; 9009 9010struct mlx5_ifc_trc_cap_reg_bits { 9011 u8 reserved_0[0x18]; 9012 u8 dump_mode[0x8]; 9013 9014 u8 reserved_1[0x20]; 9015 9016 u8 num_of_events[0x10]; 9017 u8 num_of_filters[0x10]; 9018 9019 u8 fifo_size[0x20]; 9020 9021 u8 tlb_size[0x10]; 9022 u8 event_size[0x10]; 9023 9024 u8 reserved_2[0x160]; 9025}; 9026 9027struct mlx5_ifc_set_node_in_bits { 9028 u8 node_description[64][0x8]; 9029}; 9030 9031struct mlx5_ifc_register_power_settings_bits { 9032 u8 reserved_0[0x18]; 9033 u8 power_settings_level[0x8]; 9034 9035 u8 reserved_1[0x60]; 9036}; 9037 9038struct mlx5_ifc_register_host_endianess_bits { 9039 u8 he[0x1]; 9040 u8 reserved_0[0x1f]; 9041 9042 u8 reserved_1[0x60]; 9043}; 9044 9045struct mlx5_ifc_register_diag_buffer_ctrl_bits { 9046 u8 physical_address[0x40]; 9047}; 9048 9049struct mlx5_ifc_qtct_reg_bits { 9050 u8 operation_type[0x2]; 9051 u8 cap_local_admin[0x1]; 9052 u8 cap_remote_admin[0x1]; 9053 u8 reserved_0[0x4]; 9054 u8 port_number[0x8]; 9055 u8 reserved_1[0xd]; 9056 u8 prio[0x3]; 9057 9058 u8 reserved_2[0x1d]; 9059 u8 tclass[0x3]; 9060}; 9061 9062struct mlx5_ifc_qpdp_reg_bits { 9063 u8 reserved_0[0x8]; 9064 u8 port_number[0x8]; 9065 u8 reserved_1[0x10]; 9066 9067 u8 reserved_2[0x1d]; 9068 u8 pprio[0x3]; 9069}; 9070 9071struct mlx5_ifc_port_info_ro_fields_param_bits { 9072 u8 reserved_0[0x8]; 9073 u8 port[0x8]; 9074 u8 max_gid[0x10]; 9075 9076 u8 reserved_1[0x20]; 9077 9078 u8 port_guid[0x40]; 9079}; 9080 9081struct mlx5_ifc_nvqc_reg_bits { 9082 u8 type[0x20]; 9083 9084 u8 reserved_0[0x18]; 9085 u8 version[0x4]; 9086 u8 reserved_1[0x2]; 9087 u8 support_wr[0x1]; 9088 u8 support_rd[0x1]; 9089}; 9090 9091struct mlx5_ifc_nvia_reg_bits { 9092 u8 reserved_0[0x1d]; 9093 u8 target[0x3]; 9094 9095 u8 reserved_1[0x20]; 9096}; 9097 9098struct mlx5_ifc_nvdi_reg_bits { 9099 struct mlx5_ifc_config_item_bits configuration_item_header; 9100}; 9101 9102struct mlx5_ifc_nvda_reg_bits { 9103 struct mlx5_ifc_config_item_bits configuration_item_header; 9104 9105 u8 configuration_item_data[0x20]; 9106}; 9107 9108struct mlx5_ifc_node_info_ro_fields_param_bits { 9109 u8 system_image_guid[0x40]; 9110 9111 u8 reserved_0[0x40]; 9112 9113 u8 node_guid[0x40]; 9114 9115 u8 reserved_1[0x10]; 9116 u8 max_pkey[0x10]; 9117 9118 u8 reserved_2[0x20]; 9119}; 9120 9121struct mlx5_ifc_ets_tcn_config_reg_bits { 9122 u8 g[0x1]; 9123 u8 b[0x1]; 9124 u8 r[0x1]; 9125 u8 reserved_0[0x9]; 9126 u8 group[0x4]; 9127 u8 reserved_1[0x9]; 9128 u8 bw_allocation[0x7]; 9129 9130 u8 reserved_2[0xc]; 9131 u8 max_bw_units[0x4]; 9132 u8 reserved_3[0x8]; 9133 u8 max_bw_value[0x8]; 9134}; 9135 9136struct mlx5_ifc_ets_global_config_reg_bits { 9137 u8 reserved_0[0x2]; 9138 u8 r[0x1]; 9139 u8 reserved_1[0x1d]; 9140 9141 u8 reserved_2[0xc]; 9142 u8 max_bw_units[0x4]; 9143 u8 reserved_3[0x8]; 9144 u8 max_bw_value[0x8]; 9145}; 9146 9147struct mlx5_ifc_qetc_reg_bits { 9148 u8 reserved_at_0[0x8]; 9149 u8 port_number[0x8]; 9150 u8 reserved_at_10[0x30]; 9151 9152 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 9153 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 9154}; 9155 9156struct mlx5_ifc_nodnic_mac_filters_bits { 9157 struct mlx5_ifc_mac_address_layout_bits mac_filter0; 9158 9159 struct mlx5_ifc_mac_address_layout_bits mac_filter1; 9160 9161 struct mlx5_ifc_mac_address_layout_bits mac_filter2; 9162 9163 struct mlx5_ifc_mac_address_layout_bits mac_filter3; 9164 9165 struct mlx5_ifc_mac_address_layout_bits mac_filter4; 9166 9167 u8 reserved_0[0xc0]; 9168}; 9169 9170struct mlx5_ifc_nodnic_gid_filters_bits { 9171 u8 mgid_filter0[16][0x8]; 9172 9173 u8 mgid_filter1[16][0x8]; 9174 9175 u8 mgid_filter2[16][0x8]; 9176 9177 u8 mgid_filter3[16][0x8]; 9178}; 9179 9180enum { 9181 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT = 0x0, 9182 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT = 0x1, 9183}; 9184 9185enum { 9186 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE = 0x0, 9187 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE = 0x1, 9188}; 9189 9190struct mlx5_ifc_nodnic_config_reg_bits { 9191 u8 no_dram_nic_revision[0x8]; 9192 u8 hardware_format[0x8]; 9193 u8 support_receive_filter[0x1]; 9194 u8 support_promisc_filter[0x1]; 9195 u8 support_promisc_multicast_filter[0x1]; 9196 u8 reserved_0[0x2]; 9197 u8 log_working_buffer_size[0x3]; 9198 u8 log_pkey_table_size[0x4]; 9199 u8 reserved_1[0x3]; 9200 u8 num_ports[0x1]; 9201 9202 u8 reserved_2[0x2]; 9203 u8 log_max_ring_size[0x6]; 9204 u8 reserved_3[0x18]; 9205 9206 u8 lkey[0x20]; 9207 9208 u8 cqe_format[0x4]; 9209 u8 reserved_4[0x1c]; 9210 9211 u8 node_guid[0x40]; 9212 9213 u8 reserved_5[0x740]; 9214 9215 struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings; 9216 9217 struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings; 9218}; 9219 9220struct mlx5_ifc_vlan_layout_bits { 9221 u8 reserved_0[0x14]; 9222 u8 vlan[0xc]; 9223 9224 u8 reserved_1[0x20]; 9225}; 9226 9227struct mlx5_ifc_umr_pointer_desc_argument_bits { 9228 u8 reserved_0[0x20]; 9229 9230 u8 mkey[0x20]; 9231 9232 u8 addressh_63_32[0x20]; 9233 9234 u8 addressl_31_0[0x20]; 9235}; 9236 9237struct mlx5_ifc_ud_adrs_vector_bits { 9238 u8 dc_key[0x40]; 9239 9240 u8 ext[0x1]; 9241 u8 reserved_0[0x7]; 9242 u8 destination_qp_dct[0x18]; 9243 9244 u8 static_rate[0x4]; 9245 u8 sl_eth_prio[0x4]; 9246 u8 fl[0x1]; 9247 u8 mlid[0x7]; 9248 u8 rlid_udp_sport[0x10]; 9249 9250 u8 reserved_1[0x20]; 9251 9252 u8 rmac_47_16[0x20]; 9253 9254 u8 rmac_15_0[0x10]; 9255 u8 tclass[0x8]; 9256 u8 hop_limit[0x8]; 9257 9258 u8 reserved_2[0x1]; 9259 u8 grh[0x1]; 9260 u8 reserved_3[0x2]; 9261 u8 src_addr_index[0x8]; 9262 u8 flow_label[0x14]; 9263 9264 u8 rgid_rip[16][0x8]; 9265}; 9266 9267struct mlx5_ifc_port_module_event_bits { 9268 u8 reserved_0[0x8]; 9269 u8 module[0x8]; 9270 u8 reserved_1[0xc]; 9271 u8 module_status[0x4]; 9272 9273 u8 reserved_2[0x14]; 9274 u8 error_type[0x4]; 9275 u8 reserved_3[0x8]; 9276 9277 u8 reserved_4[0xa0]; 9278}; 9279 9280struct mlx5_ifc_icmd_control_bits { 9281 u8 opcode[0x10]; 9282 u8 status[0x8]; 9283 u8 reserved_0[0x7]; 9284 u8 busy[0x1]; 9285}; 9286 9287struct mlx5_ifc_eqe_bits { 9288 u8 reserved_0[0x8]; 9289 u8 event_type[0x8]; 9290 u8 reserved_1[0x8]; 9291 u8 event_sub_type[0x8]; 9292 9293 u8 reserved_2[0xe0]; 9294 9295 union mlx5_ifc_event_auto_bits event_data; 9296 9297 u8 reserved_3[0x10]; 9298 u8 signature[0x8]; 9299 u8 reserved_4[0x7]; 9300 u8 owner[0x1]; 9301}; 9302 9303enum { 9304 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9305}; 9306 9307struct mlx5_ifc_cmd_queue_entry_bits { 9308 u8 type[0x8]; 9309 u8 reserved_0[0x18]; 9310 9311 u8 input_length[0x20]; 9312 9313 u8 input_mailbox_pointer_63_32[0x20]; 9314 9315 u8 input_mailbox_pointer_31_9[0x17]; 9316 u8 reserved_1[0x9]; 9317 9318 u8 command_input_inline_data[16][0x8]; 9319 9320 u8 command_output_inline_data[16][0x8]; 9321 9322 u8 output_mailbox_pointer_63_32[0x20]; 9323 9324 u8 output_mailbox_pointer_31_9[0x17]; 9325 u8 reserved_2[0x9]; 9326 9327 u8 output_length[0x20]; 9328 9329 u8 token[0x8]; 9330 u8 signature[0x8]; 9331 u8 reserved_3[0x8]; 9332 u8 status[0x7]; 9333 u8 ownership[0x1]; 9334}; 9335 9336struct mlx5_ifc_cmd_out_bits { 9337 u8 status[0x8]; 9338 u8 reserved_0[0x18]; 9339 9340 u8 syndrome[0x20]; 9341 9342 u8 command_output[0x20]; 9343}; 9344 9345struct mlx5_ifc_cmd_in_bits { 9346 u8 opcode[0x10]; 9347 u8 reserved_0[0x10]; 9348 9349 u8 reserved_1[0x10]; 9350 u8 op_mod[0x10]; 9351 9352 u8 command[0][0x20]; 9353}; 9354 9355struct mlx5_ifc_cmd_if_box_bits { 9356 u8 mailbox_data[512][0x8]; 9357 9358 u8 reserved_0[0x180]; 9359 9360 u8 next_pointer_63_32[0x20]; 9361 9362 u8 next_pointer_31_10[0x16]; 9363 u8 reserved_1[0xa]; 9364 9365 u8 block_number[0x20]; 9366 9367 u8 reserved_2[0x8]; 9368 u8 token[0x8]; 9369 u8 ctrl_signature[0x8]; 9370 u8 signature[0x8]; 9371}; 9372 9373struct mlx5_ifc_mtt_bits { 9374 u8 ptag_63_32[0x20]; 9375 9376 u8 ptag_31_8[0x18]; 9377 u8 reserved_0[0x6]; 9378 u8 wr_en[0x1]; 9379 u8 rd_en[0x1]; 9380}; 9381 9382/* Vendor Specific Capabilities, VSC */ 9383enum { 9384 MLX5_VSC_DOMAIN_ICMD = 0x1, 9385 MLX5_VSC_DOMAIN_PROTECTED_CRSPACE = 0x6, 9386 MLX5_VSC_DOMAIN_SEMAPHORES = 0xA, 9387}; 9388 9389struct mlx5_ifc_vendor_specific_cap_bits { 9390 u8 type[0x8]; 9391 u8 length[0x8]; 9392 u8 next_pointer[0x8]; 9393 u8 capability_id[0x8]; 9394 9395 u8 status[0x3]; 9396 u8 reserved_0[0xd]; 9397 u8 space[0x10]; 9398 9399 u8 counter[0x20]; 9400 9401 u8 semaphore[0x20]; 9402 9403 u8 flag[0x1]; 9404 u8 reserved_1[0x1]; 9405 u8 address[0x1e]; 9406 9407 u8 data[0x20]; 9408}; 9409 9410enum { 9411 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9412 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9413 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9414}; 9415 9416enum { 9417 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9418 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9419 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9420}; 9421 9422enum { 9423 MLX5_HEALTH_SYNDR_FW_ERR = 0x1, 9424 MLX5_HEALTH_SYNDR_IRISC_ERR = 0x7, 9425 MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR = 0x8, 9426 MLX5_HEALTH_SYNDR_CRC_ERR = 0x9, 9427 MLX5_HEALTH_SYNDR_FETCH_PCI_ERR = 0xa, 9428 MLX5_HEALTH_SYNDR_HW_FTL_ERR = 0xb, 9429 MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR = 0xc, 9430 MLX5_HEALTH_SYNDR_EQ_ERR = 0xd, 9431 MLX5_HEALTH_SYNDR_EQ_INV = 0xe, 9432 MLX5_HEALTH_SYNDR_FFSER_ERR = 0xf, 9433 MLX5_HEALTH_SYNDR_HIGH_TEMP = 0x10, 9434}; 9435 9436struct mlx5_ifc_initial_seg_bits { 9437 u8 fw_rev_minor[0x10]; 9438 u8 fw_rev_major[0x10]; 9439 9440 u8 cmd_interface_rev[0x10]; 9441 u8 fw_rev_subminor[0x10]; 9442 9443 u8 reserved_0[0x40]; 9444 9445 u8 cmdq_phy_addr_63_32[0x20]; 9446 9447 u8 cmdq_phy_addr_31_12[0x14]; 9448 u8 reserved_1[0x2]; 9449 u8 nic_interface[0x2]; 9450 u8 log_cmdq_size[0x4]; 9451 u8 log_cmdq_stride[0x4]; 9452 9453 u8 command_doorbell_vector[0x20]; 9454 9455 u8 reserved_2[0xf00]; 9456 9457 u8 initializing[0x1]; 9458 u8 reserved_3[0x4]; 9459 u8 nic_interface_supported[0x3]; 9460 u8 reserved_4[0x18]; 9461 9462 struct mlx5_ifc_health_buffer_bits health_buffer; 9463 9464 u8 no_dram_nic_offset[0x20]; 9465 9466 u8 reserved_5[0x6de0]; 9467 9468 u8 internal_timer_h[0x20]; 9469 9470 u8 internal_timer_l[0x20]; 9471 9472 u8 reserved_6[0x20]; 9473 9474 u8 reserved_7[0x1f]; 9475 u8 clear_int[0x1]; 9476 9477 u8 health_syndrome[0x8]; 9478 u8 health_counter[0x18]; 9479 9480 u8 reserved_8[0x17fc0]; 9481}; 9482 9483union mlx5_ifc_icmd_interface_document_bits { 9484 struct mlx5_ifc_fw_version_bits fw_version; 9485 struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in; 9486 struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out; 9487 struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in; 9488 struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in; 9489 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out; 9490 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out; 9491 struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general; 9492 struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in; 9493 struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out; 9494 struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out; 9495 struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in; 9496 struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in; 9497 struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out; 9498 u8 reserved_0[0x42c0]; 9499}; 9500 9501union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 9502 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9503 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9504 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9505 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9506 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9507 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 9508 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9509 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9510 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 9511 struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs; 9512 u8 reserved_0[0x7c0]; 9513}; 9514 9515struct mlx5_ifc_ppcnt_reg_bits { 9516 u8 swid[0x8]; 9517 u8 local_port[0x8]; 9518 u8 pnat[0x2]; 9519 u8 reserved_0[0x8]; 9520 u8 grp[0x6]; 9521 9522 u8 clr[0x1]; 9523 u8 reserved_1[0x1c]; 9524 u8 prio_tc[0x3]; 9525 9526 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9527}; 9528 9529struct mlx5_ifc_pcie_performance_counters_data_layout_bits { 9530 u8 life_time_counter_high[0x20]; 9531 9532 u8 life_time_counter_low[0x20]; 9533 9534 u8 rx_errors[0x20]; 9535 9536 u8 tx_errors[0x20]; 9537 9538 u8 l0_to_recovery_eieos[0x20]; 9539 9540 u8 l0_to_recovery_ts[0x20]; 9541 9542 u8 l0_to_recovery_framing[0x20]; 9543 9544 u8 l0_to_recovery_retrain[0x20]; 9545 9546 u8 crc_error_dllp[0x20]; 9547 9548 u8 crc_error_tlp[0x20]; 9549 9550 u8 reserved_0[0x680]; 9551}; 9552 9553struct mlx5_ifc_pcie_timers_and_states_data_layout_bits { 9554 u8 life_time_counter_high[0x20]; 9555 9556 u8 life_time_counter_low[0x20]; 9557 9558 u8 time_to_boot_image_start[0x20]; 9559 9560 u8 time_to_link_image[0x20]; 9561 9562 u8 calibration_time[0x20]; 9563 9564 u8 time_to_first_perst[0x20]; 9565 9566 u8 time_to_detect_state[0x20]; 9567 9568 u8 time_to_l0[0x20]; 9569 9570 u8 time_to_crs_en[0x20]; 9571 9572 u8 time_to_plastic_image_start[0x20]; 9573 9574 u8 time_to_iron_image_start[0x20]; 9575 9576 u8 perst_handler[0x20]; 9577 9578 u8 times_in_l1[0x20]; 9579 9580 u8 times_in_l23[0x20]; 9581 9582 u8 dl_down[0x20]; 9583 9584 u8 config_cycle1usec[0x20]; 9585 9586 u8 config_cycle2to7usec[0x20]; 9587 9588 u8 config_cycle8to15usec[0x20]; 9589 9590 u8 config_cycle16to63usec[0x20]; 9591 9592 u8 config_cycle64usec[0x20]; 9593 9594 u8 correctable_err_msg_sent[0x20]; 9595 9596 u8 non_fatal_err_msg_sent[0x20]; 9597 9598 u8 fatal_err_msg_sent[0x20]; 9599 9600 u8 reserved_0[0x4e0]; 9601}; 9602 9603struct mlx5_ifc_pcie_lanes_counters_data_layout_bits { 9604 u8 life_time_counter_high[0x20]; 9605 9606 u8 life_time_counter_low[0x20]; 9607 9608 u8 error_counter_lane0[0x20]; 9609 9610 u8 error_counter_lane1[0x20]; 9611 9612 u8 error_counter_lane2[0x20]; 9613 9614 u8 error_counter_lane3[0x20]; 9615 9616 u8 error_counter_lane4[0x20]; 9617 9618 u8 error_counter_lane5[0x20]; 9619 9620 u8 error_counter_lane6[0x20]; 9621 9622 u8 error_counter_lane7[0x20]; 9623 9624 u8 error_counter_lane8[0x20]; 9625 9626 u8 error_counter_lane9[0x20]; 9627 9628 u8 error_counter_lane10[0x20]; 9629 9630 u8 error_counter_lane11[0x20]; 9631 9632 u8 error_counter_lane12[0x20]; 9633 9634 u8 error_counter_lane13[0x20]; 9635 9636 u8 error_counter_lane14[0x20]; 9637 9638 u8 error_counter_lane15[0x20]; 9639 9640 u8 reserved_0[0x580]; 9641}; 9642 9643union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits { 9644 struct mlx5_ifc_pcie_performance_counters_data_layout_bits pcie_performance_counters_data_layout; 9645 struct mlx5_ifc_pcie_timers_and_states_data_layout_bits pcie_timers_and_states_data_layout; 9646 struct mlx5_ifc_pcie_lanes_counters_data_layout_bits pcie_lanes_counters_data_layout; 9647 u8 reserved_0[0xf8]; 9648}; 9649 9650struct mlx5_ifc_mpcnt_reg_bits { 9651 u8 reserved_0[0x8]; 9652 u8 pcie_index[0x8]; 9653 u8 reserved_1[0xa]; 9654 u8 grp[0x6]; 9655 9656 u8 clr[0x1]; 9657 u8 reserved_2[0x1f]; 9658 9659 union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits counter_set; 9660}; 9661 9662union mlx5_ifc_ports_control_registers_document_bits { 9663 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data; 9664 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 9665 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9666 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9667 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9668 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9669 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 9670 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9671 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9672 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout; 9673 struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout; 9674 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 9675 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date; 9676 struct mlx5_ifc_pamp_reg_bits pamp_reg; 9677 struct mlx5_ifc_paos_reg_bits paos_reg; 9678 struct mlx5_ifc_pbmc_reg_bits pbmc_reg; 9679 struct mlx5_ifc_pcap_reg_bits pcap_reg; 9680 struct mlx5_ifc_peir_reg_bits peir_reg; 9681 struct mlx5_ifc_pelc_reg_bits pelc_reg; 9682 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 9683 struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg; 9684 struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg; 9685 struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg; 9686 struct mlx5_ifc_phrr_reg_bits phrr_reg; 9687 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9688 struct mlx5_ifc_pifr_reg_bits pifr_reg; 9689 struct mlx5_ifc_pipg_reg_bits pipg_reg; 9690 struct mlx5_ifc_plbf_reg_bits plbf_reg; 9691 struct mlx5_ifc_plib_reg_bits plib_reg; 9692 struct mlx5_ifc_pll_status_data_bits pll_status_data; 9693 struct mlx5_ifc_plpc_reg_bits plpc_reg; 9694 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 9695 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 9696 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 9697 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 9698 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 9699 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 9700 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 9701 struct mlx5_ifc_ppad_reg_bits ppad_reg; 9702 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 9703 struct mlx5_ifc_ppll_reg_bits ppll_reg; 9704 struct mlx5_ifc_pplm_reg_bits pplm_reg; 9705 struct mlx5_ifc_pplr_reg_bits pplr_reg; 9706 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 9707 struct mlx5_ifc_pspa_reg_bits pspa_reg; 9708 struct mlx5_ifc_ptas_reg_bits ptas_reg; 9709 struct mlx5_ifc_ptys_reg_bits ptys_reg; 9710 struct mlx5_ifc_pude_reg_bits pude_reg; 9711 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 9712 struct mlx5_ifc_slrg_reg_bits slrg_reg; 9713 struct mlx5_ifc_slrp_reg_bits slrp_reg; 9714 struct mlx5_ifc_sltp_reg_bits sltp_reg; 9715 u8 reserved_0[0x7880]; 9716}; 9717 9718union mlx5_ifc_debug_enhancements_document_bits { 9719 struct mlx5_ifc_health_buffer_bits health_buffer; 9720 u8 reserved_0[0x200]; 9721}; 9722 9723union mlx5_ifc_no_dram_nic_document_bits { 9724 struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg; 9725 struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word; 9726 struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word; 9727 struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters; 9728 struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters; 9729 struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg; 9730 struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg; 9731 struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell; 9732 u8 reserved_0[0x3160]; 9733}; 9734 9735union mlx5_ifc_uplink_pci_interface_document_bits { 9736 struct mlx5_ifc_initial_seg_bits initial_seg; 9737 struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap; 9738 u8 reserved_0[0x20120]; 9739}; 9740 9741struct mlx5_ifc_qpdpm_dscp_reg_bits { 9742 u8 e[0x1]; 9743 u8 reserved_at_01[0x0b]; 9744 u8 prio[0x04]; 9745}; 9746 9747struct mlx5_ifc_qpdpm_reg_bits { 9748 u8 reserved_at_0[0x8]; 9749 u8 local_port[0x8]; 9750 u8 reserved_at_10[0x10]; 9751 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 9752}; 9753 9754struct mlx5_ifc_qpts_reg_bits { 9755 u8 reserved_at_0[0x8]; 9756 u8 local_port[0x8]; 9757 u8 reserved_at_10[0x2d]; 9758 u8 trust_state[0x3]; 9759}; 9760 9761#endif /* MLX5_IFC_H */ 9762