mlx5_ifc.h revision 331810
1/*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_ifc.h 331810 2018-03-30 19:18:33Z hselasky $ 26 */ 27 28#ifndef MLX5_IFC_H 29#define MLX5_IFC_H 30 31enum { 32 MLX5_EVENT_TYPE_COMP = 0x0, 33 MLX5_EVENT_TYPE_PATH_MIG = 0x1, 34 MLX5_EVENT_TYPE_COMM_EST = 0x2, 35 MLX5_EVENT_TYPE_SQ_DRAINED = 0x3, 36 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 37 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 38 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c, 39 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d, 40 MLX5_EVENT_TYPE_CQ_ERROR = 0x4, 41 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x5, 42 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x7, 43 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 44 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 45 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 46 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 47 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x8, 48 MLX5_EVENT_TYPE_PORT_CHANGE = 0x9, 49 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 50 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT = 0x16, 51 MLX5_EVENT_TYPE_CODING_TEMP_WARNING_EVENT = 0x17, 52 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 53 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT = 0x1e, 54 MLX5_EVENT_TYPE_CODING_PPS_EVENT = 0x25, 55 MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT = 0x22, 56 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 57 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 58 MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 59 MLX5_EVENT_TYPE_CMD = 0xa, 60 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 61 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd 62}; 63 64enum { 65 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 66 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 67 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 68 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3, 69 MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN = 0x4 70}; 71 72enum { 73 MLX5_MODIFY_RQT_BITMASK_RQN_LIST = 0x1, 74}; 75 76enum { 77 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 78 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 79}; 80 81enum { 82 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 83 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 84 MLX5_CMD_OP_INIT_HCA = 0x102, 85 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 86 MLX5_CMD_OP_ENABLE_HCA = 0x104, 87 MLX5_CMD_OP_DISABLE_HCA = 0x105, 88 MLX5_CMD_OP_QUERY_PAGES = 0x107, 89 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 90 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 91 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 92 MLX5_CMD_OP_SET_ISSI = 0x10b, 93 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 94 MLX5_CMD_OP_QUERY_OTHER_HCA_CAP = 0x10e, 95 MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP = 0x10f, 96 MLX5_CMD_OP_CREATE_MKEY = 0x200, 97 MLX5_CMD_OP_QUERY_MKEY = 0x201, 98 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 99 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 100 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 101 MLX5_CMD_OP_CREATE_EQ = 0x301, 102 MLX5_CMD_OP_DESTROY_EQ = 0x302, 103 MLX5_CMD_OP_QUERY_EQ = 0x303, 104 MLX5_CMD_OP_GEN_EQE = 0x304, 105 MLX5_CMD_OP_CREATE_CQ = 0x400, 106 MLX5_CMD_OP_DESTROY_CQ = 0x401, 107 MLX5_CMD_OP_QUERY_CQ = 0x402, 108 MLX5_CMD_OP_MODIFY_CQ = 0x403, 109 MLX5_CMD_OP_CREATE_QP = 0x500, 110 MLX5_CMD_OP_DESTROY_QP = 0x501, 111 MLX5_CMD_OP_RST2INIT_QP = 0x502, 112 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 113 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 114 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 115 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 116 MLX5_CMD_OP_2ERR_QP = 0x507, 117 MLX5_CMD_OP_2RST_QP = 0x50a, 118 MLX5_CMD_OP_QUERY_QP = 0x50b, 119 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 120 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 121 MLX5_CMD_OP_CREATE_PSV = 0x600, 122 MLX5_CMD_OP_DESTROY_PSV = 0x601, 123 MLX5_CMD_OP_CREATE_SRQ = 0x700, 124 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 125 MLX5_CMD_OP_QUERY_SRQ = 0x702, 126 MLX5_CMD_OP_ARM_RQ = 0x703, 127 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 128 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 129 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 130 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 131 MLX5_CMD_OP_CREATE_DCT = 0x710, 132 MLX5_CMD_OP_DESTROY_DCT = 0x711, 133 MLX5_CMD_OP_DRAIN_DCT = 0x712, 134 MLX5_CMD_OP_QUERY_DCT = 0x713, 135 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 136 MLX5_CMD_OP_SET_DC_CNAK_TRACE = 0x715, 137 MLX5_CMD_OP_QUERY_DC_CNAK_TRACE = 0x716, 138 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 139 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 140 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 141 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 142 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 143 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 144 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 145 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 146 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 147 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 148 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 149 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 150 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 151 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 152 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 153 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 154 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780, 155 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 156 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 157 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 158 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 159 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 160 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 161 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 162 MLX5_CMD_OP_ALLOC_PD = 0x800, 163 MLX5_CMD_OP_DEALLOC_PD = 0x801, 164 MLX5_CMD_OP_ALLOC_UAR = 0x802, 165 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 166 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 167 MLX5_CMD_OP_ACCESS_REG = 0x805, 168 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 169 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 170 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 171 MLX5_CMD_OP_MAD_IFC = 0x50d, 172 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 173 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 174 MLX5_CMD_OP_NOP = 0x80d, 175 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 176 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 177 MLX5_CMD_OP_SET_BURST_SIZE = 0x812, 178 MLX5_CMD_OP_QUERY_BURST_SIZE = 0x813, 179 MLX5_CMD_OP_ACTIVATE_TRACER = 0x814, 180 MLX5_CMD_OP_DEACTIVATE_TRACER = 0x815, 181 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 182 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 183 MLX5_CMD_OP_SET_DIAGNOSTICS = 0x820, 184 MLX5_CMD_OP_QUERY_DIAGNOSTICS = 0x821, 185 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 186 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 187 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 188 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 189 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 190 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 191 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 192 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 193 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 194 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 195 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 196 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 197 MLX5_CMD_OP_CREATE_LAG = 0x840, 198 MLX5_CMD_OP_MODIFY_LAG = 0x841, 199 MLX5_CMD_OP_QUERY_LAG = 0x842, 200 MLX5_CMD_OP_DESTROY_LAG = 0x843, 201 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 202 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 203 MLX5_CMD_OP_CREATE_TIR = 0x900, 204 MLX5_CMD_OP_MODIFY_TIR = 0x901, 205 MLX5_CMD_OP_DESTROY_TIR = 0x902, 206 MLX5_CMD_OP_QUERY_TIR = 0x903, 207 MLX5_CMD_OP_CREATE_SQ = 0x904, 208 MLX5_CMD_OP_MODIFY_SQ = 0x905, 209 MLX5_CMD_OP_DESTROY_SQ = 0x906, 210 MLX5_CMD_OP_QUERY_SQ = 0x907, 211 MLX5_CMD_OP_CREATE_RQ = 0x908, 212 MLX5_CMD_OP_MODIFY_RQ = 0x909, 213 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 214 MLX5_CMD_OP_QUERY_RQ = 0x90b, 215 MLX5_CMD_OP_CREATE_RMP = 0x90c, 216 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 217 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 218 MLX5_CMD_OP_QUERY_RMP = 0x90f, 219 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 220 MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS = 0x911, 221 MLX5_CMD_OP_CREATE_TIS = 0x912, 222 MLX5_CMD_OP_MODIFY_TIS = 0x913, 223 MLX5_CMD_OP_DESTROY_TIS = 0x914, 224 MLX5_CMD_OP_QUERY_TIS = 0x915, 225 MLX5_CMD_OP_CREATE_RQT = 0x916, 226 MLX5_CMD_OP_MODIFY_RQT = 0x917, 227 MLX5_CMD_OP_DESTROY_RQT = 0x918, 228 MLX5_CMD_OP_QUERY_RQT = 0x919, 229 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 230 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 231 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 232 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 233 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 234 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 235 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 236 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 237 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 238 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 239 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 240 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 241 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 242 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 243 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d, 244 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e, 245}; 246 247enum { 248 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO = 0x8007, 249 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY = 0x8400, 250 MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER = 0x9001, 251 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC = 0x9003, 252 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC = 0x9004, 253 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL = 0x9005, 254 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL = 0x9006, 255 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT = 0x9007, 256 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008, 257 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS = 0x9009, 258 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT = 0x900a, 259 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD = 0xf004 260}; 261 262struct mlx5_ifc_flow_table_fields_supported_bits { 263 u8 outer_dmac[0x1]; 264 u8 outer_smac[0x1]; 265 u8 outer_ether_type[0x1]; 266 u8 reserved_0[0x1]; 267 u8 outer_first_prio[0x1]; 268 u8 outer_first_cfi[0x1]; 269 u8 outer_first_vid[0x1]; 270 u8 reserved_1[0x1]; 271 u8 outer_second_prio[0x1]; 272 u8 outer_second_cfi[0x1]; 273 u8 outer_second_vid[0x1]; 274 u8 outer_ipv6_flow_label[0x1]; 275 u8 outer_sip[0x1]; 276 u8 outer_dip[0x1]; 277 u8 outer_frag[0x1]; 278 u8 outer_ip_protocol[0x1]; 279 u8 outer_ip_ecn[0x1]; 280 u8 outer_ip_dscp[0x1]; 281 u8 outer_udp_sport[0x1]; 282 u8 outer_udp_dport[0x1]; 283 u8 outer_tcp_sport[0x1]; 284 u8 outer_tcp_dport[0x1]; 285 u8 outer_tcp_flags[0x1]; 286 u8 outer_gre_protocol[0x1]; 287 u8 outer_gre_key[0x1]; 288 u8 outer_vxlan_vni[0x1]; 289 u8 outer_geneve_vni[0x1]; 290 u8 outer_geneve_oam[0x1]; 291 u8 outer_geneve_protocol_type[0x1]; 292 u8 outer_geneve_opt_len[0x1]; 293 u8 reserved_2[0x1]; 294 u8 source_eswitch_port[0x1]; 295 296 u8 inner_dmac[0x1]; 297 u8 inner_smac[0x1]; 298 u8 inner_ether_type[0x1]; 299 u8 reserved_3[0x1]; 300 u8 inner_first_prio[0x1]; 301 u8 inner_first_cfi[0x1]; 302 u8 inner_first_vid[0x1]; 303 u8 reserved_4[0x1]; 304 u8 inner_second_prio[0x1]; 305 u8 inner_second_cfi[0x1]; 306 u8 inner_second_vid[0x1]; 307 u8 inner_ipv6_flow_label[0x1]; 308 u8 inner_sip[0x1]; 309 u8 inner_dip[0x1]; 310 u8 inner_frag[0x1]; 311 u8 inner_ip_protocol[0x1]; 312 u8 inner_ip_ecn[0x1]; 313 u8 inner_ip_dscp[0x1]; 314 u8 inner_udp_sport[0x1]; 315 u8 inner_udp_dport[0x1]; 316 u8 inner_tcp_sport[0x1]; 317 u8 inner_tcp_dport[0x1]; 318 u8 inner_tcp_flags[0x1]; 319 u8 reserved_5[0x9]; 320 321 u8 reserved_6[0x1a]; 322 u8 bth_dst_qp[0x1]; 323 u8 reserved_7[0x4]; 324 u8 source_sqn[0x1]; 325 326 u8 reserved_8[0x20]; 327}; 328 329struct mlx5_ifc_eth_discard_cntrs_grp_bits { 330 u8 ingress_general_high[0x20]; 331 332 u8 ingress_general_low[0x20]; 333 334 u8 ingress_policy_engine_high[0x20]; 335 336 u8 ingress_policy_engine_low[0x20]; 337 338 u8 ingress_vlan_membership_high[0x20]; 339 340 u8 ingress_vlan_membership_low[0x20]; 341 342 u8 ingress_tag_frame_type_high[0x20]; 343 344 u8 ingress_tag_frame_type_low[0x20]; 345 346 u8 egress_vlan_membership_high[0x20]; 347 348 u8 egress_vlan_membership_low[0x20]; 349 350 u8 loopback_filter_high[0x20]; 351 352 u8 loopback_filter_low[0x20]; 353 354 u8 egress_general_high[0x20]; 355 356 u8 egress_general_low[0x20]; 357 358 u8 reserved_at_1c0[0x40]; 359 360 u8 egress_hoq_high[0x20]; 361 362 u8 egress_hoq_low[0x20]; 363 364 u8 port_isolation_high[0x20]; 365 366 u8 port_isolation_low[0x20]; 367 368 u8 egress_policy_engine_high[0x20]; 369 370 u8 egress_policy_engine_low[0x20]; 371 372 u8 ingress_tx_link_down_high[0x20]; 373 374 u8 ingress_tx_link_down_low[0x20]; 375 376 u8 egress_stp_filter_high[0x20]; 377 378 u8 egress_stp_filter_low[0x20]; 379 380 u8 egress_hoq_stall_high[0x20]; 381 382 u8 egress_hoq_stall_low[0x20]; 383 384 u8 reserved_at_340[0x440]; 385}; 386struct mlx5_ifc_flow_table_prop_layout_bits { 387 u8 ft_support[0x1]; 388 u8 flow_tag[0x1]; 389 u8 flow_counter[0x1]; 390 u8 flow_modify_en[0x1]; 391 u8 modify_root[0x1]; 392 u8 identified_miss_table[0x1]; 393 u8 flow_table_modify[0x1]; 394 u8 encap[0x1]; 395 u8 decap[0x1]; 396 u8 reset_root_to_default[0x1]; 397 u8 reserved_at_a[0x16]; 398 399 u8 reserved_at_20[0x2]; 400 u8 log_max_ft_size[0x6]; 401 u8 reserved_at_28[0x10]; 402 u8 max_ft_level[0x8]; 403 404 u8 reserved_at_40[0x20]; 405 406 u8 reserved_at_60[0x18]; 407 u8 log_max_ft_num[0x8]; 408 409 u8 reserved_at_80[0x10]; 410 u8 log_max_flow_counter[0x8]; 411 u8 log_max_destination[0x8]; 412 413 u8 reserved_at_a0[0x18]; 414 u8 log_max_flow[0x8]; 415 416 u8 reserved_at_c0[0x40]; 417 418 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 419 420 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 421}; 422 423struct mlx5_ifc_odp_per_transport_service_cap_bits { 424 u8 send[0x1]; 425 u8 receive[0x1]; 426 u8 write[0x1]; 427 u8 read[0x1]; 428 u8 atomic[0x1]; 429 u8 srq_receive[0x1]; 430 u8 reserved_0[0x1a]; 431}; 432 433struct mlx5_ifc_flow_counter_list_bits { 434 u8 reserved_0[0x10]; 435 u8 flow_counter_id[0x10]; 436 437 u8 reserved_1[0x20]; 438}; 439 440enum { 441 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0x0, 442 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 0x1, 443 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 0x2, 444 MLX5_FLOW_CONTEXT_DEST_TYPE_QP = 0x3, 445}; 446 447struct mlx5_ifc_dest_format_struct_bits { 448 u8 destination_type[0x8]; 449 u8 destination_id[0x18]; 450 451 u8 reserved_0[0x20]; 452}; 453 454struct mlx5_ifc_ipv4_layout_bits { 455 u8 reserved_at_0[0x60]; 456 457 u8 ipv4[0x20]; 458}; 459 460struct mlx5_ifc_ipv6_layout_bits { 461 u8 ipv6[16][0x8]; 462}; 463 464union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 465 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 466 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 467 u8 reserved_at_0[0x80]; 468}; 469 470struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 471 u8 smac_47_16[0x20]; 472 473 u8 smac_15_0[0x10]; 474 u8 ethertype[0x10]; 475 476 u8 dmac_47_16[0x20]; 477 478 u8 dmac_15_0[0x10]; 479 u8 first_prio[0x3]; 480 u8 first_cfi[0x1]; 481 u8 first_vid[0xc]; 482 483 u8 ip_protocol[0x8]; 484 u8 ip_dscp[0x6]; 485 u8 ip_ecn[0x2]; 486 u8 cvlan_tag[0x1]; 487 u8 svlan_tag[0x1]; 488 u8 frag[0x1]; 489 u8 reserved_1[0x4]; 490 u8 tcp_flags[0x9]; 491 492 u8 tcp_sport[0x10]; 493 u8 tcp_dport[0x10]; 494 495 u8 reserved_2[0x20]; 496 497 u8 udp_sport[0x10]; 498 u8 udp_dport[0x10]; 499 500 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 501 502 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 503}; 504 505struct mlx5_ifc_fte_match_set_misc_bits { 506 u8 reserved_0[0x8]; 507 u8 source_sqn[0x18]; 508 509 u8 reserved_1[0x10]; 510 u8 source_port[0x10]; 511 512 u8 outer_second_prio[0x3]; 513 u8 outer_second_cfi[0x1]; 514 u8 outer_second_vid[0xc]; 515 u8 inner_second_prio[0x3]; 516 u8 inner_second_cfi[0x1]; 517 u8 inner_second_vid[0xc]; 518 519 u8 outer_second_vlan_tag[0x1]; 520 u8 inner_second_vlan_tag[0x1]; 521 u8 reserved_2[0xe]; 522 u8 gre_protocol[0x10]; 523 524 u8 gre_key_h[0x18]; 525 u8 gre_key_l[0x8]; 526 527 u8 vxlan_vni[0x18]; 528 u8 reserved_3[0x8]; 529 530 u8 geneve_vni[0x18]; 531 u8 reserved4[0x7]; 532 u8 geneve_oam[0x1]; 533 534 u8 reserved_5[0xc]; 535 u8 outer_ipv6_flow_label[0x14]; 536 537 u8 reserved_6[0xc]; 538 u8 inner_ipv6_flow_label[0x14]; 539 540 u8 reserved_7[0xa]; 541 u8 geneve_opt_len[0x6]; 542 u8 geneve_protocol_type[0x10]; 543 544 u8 reserved_8[0x8]; 545 u8 bth_dst_qp[0x18]; 546 547 u8 reserved_9[0xa0]; 548}; 549 550struct mlx5_ifc_cmd_pas_bits { 551 u8 pa_h[0x20]; 552 553 u8 pa_l[0x14]; 554 u8 reserved_0[0xc]; 555}; 556 557struct mlx5_ifc_uint64_bits { 558 u8 hi[0x20]; 559 560 u8 lo[0x20]; 561}; 562 563struct mlx5_ifc_application_prio_entry_bits { 564 u8 reserved_0[0x8]; 565 u8 priority[0x3]; 566 u8 reserved_1[0x2]; 567 u8 sel[0x3]; 568 u8 protocol_id[0x10]; 569}; 570 571struct mlx5_ifc_nodnic_ring_doorbell_bits { 572 u8 reserved_0[0x8]; 573 u8 ring_pi[0x10]; 574 u8 reserved_1[0x8]; 575}; 576 577enum { 578 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 579 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 580 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 581 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 582 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 583 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 584 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 585 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 586 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 587 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 588}; 589 590struct mlx5_ifc_ads_bits { 591 u8 fl[0x1]; 592 u8 free_ar[0x1]; 593 u8 reserved_0[0xe]; 594 u8 pkey_index[0x10]; 595 596 u8 reserved_1[0x8]; 597 u8 grh[0x1]; 598 u8 mlid[0x7]; 599 u8 rlid[0x10]; 600 601 u8 ack_timeout[0x5]; 602 u8 reserved_2[0x3]; 603 u8 src_addr_index[0x8]; 604 u8 log_rtm[0x4]; 605 u8 stat_rate[0x4]; 606 u8 hop_limit[0x8]; 607 608 u8 reserved_3[0x4]; 609 u8 tclass[0x8]; 610 u8 flow_label[0x14]; 611 612 u8 rgid_rip[16][0x8]; 613 614 u8 reserved_4[0x4]; 615 u8 f_dscp[0x1]; 616 u8 f_ecn[0x1]; 617 u8 reserved_5[0x1]; 618 u8 f_eth_prio[0x1]; 619 u8 ecn[0x2]; 620 u8 dscp[0x6]; 621 u8 udp_sport[0x10]; 622 623 u8 dei_cfi[0x1]; 624 u8 eth_prio[0x3]; 625 u8 sl[0x4]; 626 u8 port[0x8]; 627 u8 rmac_47_32[0x10]; 628 629 u8 rmac_31_0[0x20]; 630}; 631 632struct mlx5_ifc_diagnostic_counter_cap_bits { 633 u8 sync[0x1]; 634 u8 reserved_0[0xf]; 635 u8 counter_id[0x10]; 636}; 637 638struct mlx5_ifc_debug_cap_bits { 639 u8 reserved_0[0x18]; 640 u8 log_max_samples[0x8]; 641 642 u8 single[0x1]; 643 u8 repetitive[0x1]; 644 u8 health_mon_rx_activity[0x1]; 645 u8 reserved_1[0x15]; 646 u8 log_min_sample_period[0x8]; 647 648 u8 reserved_2[0x1c0]; 649 650 struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0]; 651}; 652 653struct mlx5_ifc_qos_cap_bits { 654 u8 packet_pacing[0x1]; 655 u8 esw_scheduling[0x1]; 656 u8 esw_bw_share[0x1]; 657 u8 esw_rate_limit[0x1]; 658 u8 hll[0x1]; 659 u8 packet_pacing_burst_bound[0x1]; 660 u8 reserved_at_6[0x1a]; 661 662 u8 reserved_at_20[0x20]; 663 664 u8 packet_pacing_max_rate[0x20]; 665 666 u8 packet_pacing_min_rate[0x20]; 667 668 u8 reserved_at_80[0x10]; 669 u8 packet_pacing_rate_table_size[0x10]; 670 671 u8 esw_element_type[0x10]; 672 u8 esw_tsar_type[0x10]; 673 674 u8 reserved_at_c0[0x10]; 675 u8 max_qos_para_vport[0x10]; 676 677 u8 max_tsar_bw_share[0x20]; 678 679 u8 reserved_at_100[0x700]; 680}; 681 682struct mlx5_ifc_snapshot_cap_bits { 683 u8 reserved_0[0x1d]; 684 u8 suspend_qp_uc[0x1]; 685 u8 suspend_qp_ud[0x1]; 686 u8 suspend_qp_rc[0x1]; 687 688 u8 reserved_1[0x1c]; 689 u8 restore_pd[0x1]; 690 u8 restore_uar[0x1]; 691 u8 restore_mkey[0x1]; 692 u8 restore_qp[0x1]; 693 694 u8 reserved_2[0x1e]; 695 u8 named_mkey[0x1]; 696 u8 named_qp[0x1]; 697 698 u8 reserved_3[0x7a0]; 699}; 700 701struct mlx5_ifc_e_switch_cap_bits { 702 u8 vport_svlan_strip[0x1]; 703 u8 vport_cvlan_strip[0x1]; 704 u8 vport_svlan_insert[0x1]; 705 u8 vport_cvlan_insert_if_not_exist[0x1]; 706 u8 vport_cvlan_insert_overwrite[0x1]; 707 708 u8 reserved_0[0x19]; 709 710 u8 nic_vport_node_guid_modify[0x1]; 711 u8 nic_vport_port_guid_modify[0x1]; 712 713 u8 reserved_1[0x7e0]; 714}; 715 716struct mlx5_ifc_flow_table_eswitch_cap_bits { 717 u8 reserved_0[0x200]; 718 719 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 720 721 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 722 723 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 724 725 u8 reserved_1[0x7800]; 726}; 727 728struct mlx5_ifc_flow_table_nic_cap_bits { 729 u8 nic_rx_multi_path_tirs[0x1]; 730 u8 nic_rx_multi_path_tirs_fts[0x1]; 731 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 732 u8 reserved_at_3[0x1fd]; 733 734 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 735 736 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 737 738 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 739 740 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 741 742 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 743 744 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 745 746 u8 reserved_1[0x7200]; 747}; 748 749struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 750 u8 csum_cap[0x1]; 751 u8 vlan_cap[0x1]; 752 u8 lro_cap[0x1]; 753 u8 lro_psh_flag[0x1]; 754 u8 lro_time_stamp[0x1]; 755 u8 lro_max_msg_sz_mode[0x2]; 756 u8 wqe_vlan_insert[0x1]; 757 u8 self_lb_en_modifiable[0x1]; 758 u8 self_lb_mc[0x1]; 759 u8 self_lb_uc[0x1]; 760 u8 max_lso_cap[0x5]; 761 u8 multi_pkt_send_wqe[0x2]; 762 u8 wqe_inline_mode[0x2]; 763 u8 rss_ind_tbl_cap[0x4]; 764 u8 scatter_fcs[0x1]; 765 u8 reserved_1[0x2]; 766 u8 tunnel_lso_const_out_ip_id[0x1]; 767 u8 tunnel_lro_gre[0x1]; 768 u8 tunnel_lro_vxlan[0x1]; 769 u8 tunnel_statless_gre[0x1]; 770 u8 tunnel_stateless_vxlan[0x1]; 771 772 u8 swp[0x1]; 773 u8 swp_csum[0x1]; 774 u8 swp_lso[0x1]; 775 u8 reserved_2[0x1b]; 776 u8 max_geneve_opt_len[0x1]; 777 u8 tunnel_stateless_geneve_rx[0x1]; 778 779 u8 reserved_3[0x10]; 780 u8 lro_min_mss_size[0x10]; 781 782 u8 reserved_4[0x120]; 783 784 u8 lro_timer_supported_periods[4][0x20]; 785 786 u8 reserved_5[0x600]; 787}; 788 789enum { 790 MLX5_ROCE_CAP_L3_TYPE_GRH = 0x1, 791 MLX5_ROCE_CAP_L3_TYPE_IPV4 = 0x2, 792 MLX5_ROCE_CAP_L3_TYPE_IPV6 = 0x4, 793}; 794 795struct mlx5_ifc_roce_cap_bits { 796 u8 roce_apm[0x1]; 797 u8 rts2rts_primary_eth_prio[0x1]; 798 u8 roce_rx_allow_untagged[0x1]; 799 u8 rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1]; 800 801 u8 reserved_0[0x1c]; 802 803 u8 reserved_1[0x60]; 804 805 u8 reserved_2[0xc]; 806 u8 l3_type[0x4]; 807 u8 reserved_3[0x8]; 808 u8 roce_version[0x8]; 809 810 u8 reserved_4[0x10]; 811 u8 r_roce_dest_udp_port[0x10]; 812 813 u8 r_roce_max_src_udp_port[0x10]; 814 u8 r_roce_min_src_udp_port[0x10]; 815 816 u8 reserved_5[0x10]; 817 u8 roce_address_table_size[0x10]; 818 819 u8 reserved_6[0x700]; 820}; 821 822enum { 823 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x1, 824 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 825 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 826 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 827 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 828 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 829 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 830 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 831 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 832}; 833 834enum { 835 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 836 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 837 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 838 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 839 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 840 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 841 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 842 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 843 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 844}; 845 846struct mlx5_ifc_atomic_caps_bits { 847 u8 reserved_0[0x40]; 848 849 u8 atomic_req_8B_endianess_mode[0x2]; 850 u8 reserved_1[0x4]; 851 u8 supported_atomic_req_8B_endianess_mode_1[0x1]; 852 853 u8 reserved_2[0x19]; 854 855 u8 reserved_3[0x20]; 856 857 u8 reserved_4[0x10]; 858 u8 atomic_operations[0x10]; 859 860 u8 reserved_5[0x10]; 861 u8 atomic_size_qp[0x10]; 862 863 u8 reserved_6[0x10]; 864 u8 atomic_size_dc[0x10]; 865 866 u8 reserved_7[0x720]; 867}; 868 869struct mlx5_ifc_odp_cap_bits { 870 u8 reserved_0[0x40]; 871 872 u8 sig[0x1]; 873 u8 reserved_1[0x1f]; 874 875 u8 reserved_2[0x20]; 876 877 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 878 879 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 880 881 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 882 883 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 884 885 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 886 887 u8 reserved_3[0x6e0]; 888}; 889 890enum { 891 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 892 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 893 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 894 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 895 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 896}; 897 898enum { 899 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 900 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 901 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 902 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 903 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 904 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 905}; 906 907enum { 908 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 909 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 910}; 911 912enum { 913 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 914 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 915 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 916}; 917 918struct mlx5_ifc_cmd_hca_cap_bits { 919 u8 reserved_0[0x80]; 920 921 u8 log_max_srq_sz[0x8]; 922 u8 log_max_qp_sz[0x8]; 923 u8 reserved_1[0xb]; 924 u8 log_max_qp[0x5]; 925 926 u8 reserved_2[0xb]; 927 u8 log_max_srq[0x5]; 928 u8 reserved_3[0x10]; 929 930 u8 reserved_4[0x8]; 931 u8 log_max_cq_sz[0x8]; 932 u8 reserved_5[0xb]; 933 u8 log_max_cq[0x5]; 934 935 u8 log_max_eq_sz[0x8]; 936 u8 reserved_6[0x2]; 937 u8 log_max_mkey[0x6]; 938 u8 reserved_7[0xc]; 939 u8 log_max_eq[0x4]; 940 941 u8 max_indirection[0x8]; 942 u8 reserved_8[0x1]; 943 u8 log_max_mrw_sz[0x7]; 944 u8 force_teardown[0x1]; 945 u8 reserved_9[0x1]; 946 u8 log_max_bsf_list_size[0x6]; 947 u8 reserved_10[0x2]; 948 u8 log_max_klm_list_size[0x6]; 949 950 u8 reserved_11[0xa]; 951 u8 log_max_ra_req_dc[0x6]; 952 u8 reserved_12[0xa]; 953 u8 log_max_ra_res_dc[0x6]; 954 955 u8 reserved_13[0xa]; 956 u8 log_max_ra_req_qp[0x6]; 957 u8 reserved_14[0xa]; 958 u8 log_max_ra_res_qp[0x6]; 959 960 u8 pad_cap[0x1]; 961 u8 cc_query_allowed[0x1]; 962 u8 cc_modify_allowed[0x1]; 963 u8 start_pad[0x1]; 964 u8 cache_line_128byte[0x1]; 965 u8 reserved_15[0xb]; 966 u8 gid_table_size[0x10]; 967 968 u8 out_of_seq_cnt[0x1]; 969 u8 vport_counters[0x1]; 970 u8 retransmission_q_counters[0x1]; 971 u8 debug[0x1]; 972 u8 modify_rq_counters_set_id[0x1]; 973 u8 rq_delay_drop[0x1]; 974 u8 max_qp_cnt[0xa]; 975 u8 pkey_table_size[0x10]; 976 977 u8 vport_group_manager[0x1]; 978 u8 vhca_group_manager[0x1]; 979 u8 ib_virt[0x1]; 980 u8 eth_virt[0x1]; 981 u8 reserved_17[0x1]; 982 u8 ets[0x1]; 983 u8 nic_flow_table[0x1]; 984 u8 eswitch_flow_table[0x1]; 985 u8 reserved_18[0x3]; 986 u8 local_ca_ack_delay[0x5]; 987 u8 port_module_event[0x1]; 988 u8 reserved_19[0x5]; 989 u8 port_type[0x2]; 990 u8 num_ports[0x8]; 991 992 u8 snapshot[0x1]; 993 u8 reserved_20[0x2]; 994 u8 log_max_msg[0x5]; 995 u8 reserved_21[0x4]; 996 u8 max_tc[0x4]; 997 u8 temp_warn_event[0x1]; 998 u8 dcbx[0x1]; 999 u8 reserved_22[0x4]; 1000 u8 rol_s[0x1]; 1001 u8 rol_g[0x1]; 1002 u8 reserved_23[0x1]; 1003 u8 wol_s[0x1]; 1004 u8 wol_g[0x1]; 1005 u8 wol_a[0x1]; 1006 u8 wol_b[0x1]; 1007 u8 wol_m[0x1]; 1008 u8 wol_u[0x1]; 1009 u8 wol_p[0x1]; 1010 1011 u8 stat_rate_support[0x10]; 1012 u8 reserved_24[0xc]; 1013 u8 cqe_version[0x4]; 1014 1015 u8 compact_address_vector[0x1]; 1016 u8 striding_rq[0x1]; 1017 u8 reserved_25[0x1]; 1018 u8 ipoib_enhanced_offloads[0x1]; 1019 u8 ipoib_ipoib_offloads[0x1]; 1020 u8 reserved_26[0x8]; 1021 u8 dc_connect_qp[0x1]; 1022 u8 dc_cnak_trace[0x1]; 1023 u8 drain_sigerr[0x1]; 1024 u8 cmdif_checksum[0x2]; 1025 u8 sigerr_cqe[0x1]; 1026 u8 reserved_27[0x1]; 1027 u8 wq_signature[0x1]; 1028 u8 sctr_data_cqe[0x1]; 1029 u8 reserved_28[0x1]; 1030 u8 sho[0x1]; 1031 u8 tph[0x1]; 1032 u8 rf[0x1]; 1033 u8 dct[0x1]; 1034 u8 qos[0x1]; 1035 u8 eth_net_offloads[0x1]; 1036 u8 roce[0x1]; 1037 u8 atomic[0x1]; 1038 u8 reserved_30[0x1]; 1039 1040 u8 cq_oi[0x1]; 1041 u8 cq_resize[0x1]; 1042 u8 cq_moderation[0x1]; 1043 u8 cq_period_mode_modify[0x1]; 1044 u8 cq_invalidate[0x1]; 1045 u8 reserved_at_225[0x1]; 1046 u8 cq_eq_remap[0x1]; 1047 u8 pg[0x1]; 1048 u8 block_lb_mc[0x1]; 1049 u8 exponential_backoff[0x1]; 1050 u8 scqe_break_moderation[0x1]; 1051 u8 cq_period_start_from_cqe[0x1]; 1052 u8 cd[0x1]; 1053 u8 atm[0x1]; 1054 u8 apm[0x1]; 1055 u8 imaicl[0x1]; 1056 u8 reserved_32[0x6]; 1057 u8 qkv[0x1]; 1058 u8 pkv[0x1]; 1059 u8 set_deth_sqpn[0x1]; 1060 u8 reserved_33[0x3]; 1061 u8 xrc[0x1]; 1062 u8 ud[0x1]; 1063 u8 uc[0x1]; 1064 u8 rc[0x1]; 1065 1066 u8 reserved_34[0xa]; 1067 u8 uar_sz[0x6]; 1068 u8 reserved_35[0x8]; 1069 u8 log_pg_sz[0x8]; 1070 1071 u8 bf[0x1]; 1072 u8 driver_version[0x1]; 1073 u8 pad_tx_eth_packet[0x1]; 1074 u8 reserved_36[0x8]; 1075 u8 log_bf_reg_size[0x5]; 1076 u8 reserved_37[0x10]; 1077 1078 u8 num_of_diagnostic_counters[0x10]; 1079 u8 max_wqe_sz_sq[0x10]; 1080 1081 u8 reserved_38[0x10]; 1082 u8 max_wqe_sz_rq[0x10]; 1083 1084 u8 reserved_39[0x10]; 1085 u8 max_wqe_sz_sq_dc[0x10]; 1086 1087 u8 reserved_40[0x7]; 1088 u8 max_qp_mcg[0x19]; 1089 1090 u8 reserved_41[0x18]; 1091 u8 log_max_mcg[0x8]; 1092 1093 u8 reserved_42[0x3]; 1094 u8 log_max_transport_domain[0x5]; 1095 u8 reserved_43[0x3]; 1096 u8 log_max_pd[0x5]; 1097 u8 reserved_44[0xb]; 1098 u8 log_max_xrcd[0x5]; 1099 1100 u8 reserved_45[0x10]; 1101 u8 max_flow_counter[0x10]; 1102 1103 u8 reserved_46[0x3]; 1104 u8 log_max_rq[0x5]; 1105 u8 reserved_47[0x3]; 1106 u8 log_max_sq[0x5]; 1107 u8 reserved_48[0x3]; 1108 u8 log_max_tir[0x5]; 1109 u8 reserved_49[0x3]; 1110 u8 log_max_tis[0x5]; 1111 1112 u8 basic_cyclic_rcv_wqe[0x1]; 1113 u8 reserved_50[0x2]; 1114 u8 log_max_rmp[0x5]; 1115 u8 reserved_51[0x3]; 1116 u8 log_max_rqt[0x5]; 1117 u8 reserved_52[0x3]; 1118 u8 log_max_rqt_size[0x5]; 1119 u8 reserved_53[0x3]; 1120 u8 log_max_tis_per_sq[0x5]; 1121 1122 u8 reserved_54[0x3]; 1123 u8 log_max_stride_sz_rq[0x5]; 1124 u8 reserved_55[0x3]; 1125 u8 log_min_stride_sz_rq[0x5]; 1126 u8 reserved_56[0x3]; 1127 u8 log_max_stride_sz_sq[0x5]; 1128 u8 reserved_57[0x3]; 1129 u8 log_min_stride_sz_sq[0x5]; 1130 1131 u8 reserved_58[0x1b]; 1132 u8 log_max_wq_sz[0x5]; 1133 1134 u8 nic_vport_change_event[0x1]; 1135 u8 disable_local_lb[0x1]; 1136 u8 reserved_59[0x9]; 1137 u8 log_max_vlan_list[0x5]; 1138 u8 reserved_60[0x3]; 1139 u8 log_max_current_mc_list[0x5]; 1140 u8 reserved_61[0x3]; 1141 u8 log_max_current_uc_list[0x5]; 1142 1143 u8 reserved_62[0x80]; 1144 1145 u8 reserved_63[0x3]; 1146 u8 log_max_l2_table[0x5]; 1147 u8 reserved_64[0x8]; 1148 u8 log_uar_page_sz[0x10]; 1149 1150 u8 reserved_65[0x20]; 1151 1152 u8 device_frequency_mhz[0x20]; 1153 1154 u8 device_frequency_khz[0x20]; 1155 1156 u8 reserved_66[0x80]; 1157 1158 u8 log_max_atomic_size_qp[0x8]; 1159 u8 reserved_67[0x10]; 1160 u8 log_max_atomic_size_dc[0x8]; 1161 1162 u8 reserved_68[0x1f]; 1163 u8 cqe_compression[0x1]; 1164 1165 u8 cqe_compression_timeout[0x10]; 1166 u8 cqe_compression_max_num[0x10]; 1167 1168 u8 reserved_69[0x220]; 1169}; 1170 1171enum mlx5_flow_destination_type { 1172 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1173 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1174 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1175}; 1176 1177union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1178 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1179 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1180 u8 reserved_0[0x40]; 1181}; 1182 1183struct mlx5_ifc_fte_match_param_bits { 1184 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1185 1186 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1187 1188 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1189 1190 u8 reserved_0[0xa00]; 1191}; 1192 1193enum { 1194 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1195 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1196 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1197 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1198 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1199}; 1200 1201struct mlx5_ifc_rx_hash_field_select_bits { 1202 u8 l3_prot_type[0x1]; 1203 u8 l4_prot_type[0x1]; 1204 u8 selected_fields[0x1e]; 1205}; 1206 1207enum { 1208 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1209 MLX5_WQ_TYPE_CYCLIC = 0x1, 1210 MLX5_WQ_TYPE_STRQ_LINKED_LIST = 0x2, 1211 MLX5_WQ_TYPE_STRQ_CYCLIC = 0x3, 1212}; 1213 1214enum rq_type { 1215 RQ_TYPE_NONE, 1216 RQ_TYPE_STRIDE, 1217}; 1218 1219enum { 1220 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1221 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1222}; 1223 1224struct mlx5_ifc_wq_bits { 1225 u8 wq_type[0x4]; 1226 u8 wq_signature[0x1]; 1227 u8 end_padding_mode[0x2]; 1228 u8 cd_slave[0x1]; 1229 u8 reserved_0[0x18]; 1230 1231 u8 hds_skip_first_sge[0x1]; 1232 u8 log2_hds_buf_size[0x3]; 1233 u8 reserved_1[0x7]; 1234 u8 page_offset[0x5]; 1235 u8 lwm[0x10]; 1236 1237 u8 reserved_2[0x8]; 1238 u8 pd[0x18]; 1239 1240 u8 reserved_3[0x8]; 1241 u8 uar_page[0x18]; 1242 1243 u8 dbr_addr[0x40]; 1244 1245 u8 hw_counter[0x20]; 1246 1247 u8 sw_counter[0x20]; 1248 1249 u8 reserved_4[0xc]; 1250 u8 log_wq_stride[0x4]; 1251 u8 reserved_5[0x3]; 1252 u8 log_wq_pg_sz[0x5]; 1253 u8 reserved_6[0x3]; 1254 u8 log_wq_sz[0x5]; 1255 1256 u8 reserved_7[0x15]; 1257 u8 single_wqe_log_num_of_strides[0x3]; 1258 u8 two_byte_shift_en[0x1]; 1259 u8 reserved_8[0x4]; 1260 u8 single_stride_log_num_of_bytes[0x3]; 1261 1262 u8 reserved_9[0x4c0]; 1263 1264 struct mlx5_ifc_cmd_pas_bits pas[0]; 1265}; 1266 1267struct mlx5_ifc_rq_num_bits { 1268 u8 reserved_0[0x8]; 1269 u8 rq_num[0x18]; 1270}; 1271 1272struct mlx5_ifc_mac_address_layout_bits { 1273 u8 reserved_0[0x10]; 1274 u8 mac_addr_47_32[0x10]; 1275 1276 u8 mac_addr_31_0[0x20]; 1277}; 1278 1279struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1280 u8 reserved_0[0xa0]; 1281 1282 u8 min_time_between_cnps[0x20]; 1283 1284 u8 reserved_1[0x12]; 1285 u8 cnp_dscp[0x6]; 1286 u8 reserved_2[0x4]; 1287 u8 cnp_prio_mode[0x1]; 1288 u8 cnp_802p_prio[0x3]; 1289 1290 u8 reserved_3[0x720]; 1291}; 1292 1293struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1294 u8 reserved_0[0x60]; 1295 1296 u8 reserved_1[0x4]; 1297 u8 clamp_tgt_rate[0x1]; 1298 u8 reserved_2[0x3]; 1299 u8 clamp_tgt_rate_after_time_inc[0x1]; 1300 u8 reserved_3[0x17]; 1301 1302 u8 reserved_4[0x20]; 1303 1304 u8 rpg_time_reset[0x20]; 1305 1306 u8 rpg_byte_reset[0x20]; 1307 1308 u8 rpg_threshold[0x20]; 1309 1310 u8 rpg_max_rate[0x20]; 1311 1312 u8 rpg_ai_rate[0x20]; 1313 1314 u8 rpg_hai_rate[0x20]; 1315 1316 u8 rpg_gd[0x20]; 1317 1318 u8 rpg_min_dec_fac[0x20]; 1319 1320 u8 rpg_min_rate[0x20]; 1321 1322 u8 reserved_5[0xe0]; 1323 1324 u8 rate_to_set_on_first_cnp[0x20]; 1325 1326 u8 dce_tcp_g[0x20]; 1327 1328 u8 dce_tcp_rtt[0x20]; 1329 1330 u8 rate_reduce_monitor_period[0x20]; 1331 1332 u8 reserved_6[0x20]; 1333 1334 u8 initial_alpha_value[0x20]; 1335 1336 u8 reserved_7[0x4a0]; 1337}; 1338 1339struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1340 u8 reserved_0[0x80]; 1341 1342 u8 rppp_max_rps[0x20]; 1343 1344 u8 rpg_time_reset[0x20]; 1345 1346 u8 rpg_byte_reset[0x20]; 1347 1348 u8 rpg_threshold[0x20]; 1349 1350 u8 rpg_max_rate[0x20]; 1351 1352 u8 rpg_ai_rate[0x20]; 1353 1354 u8 rpg_hai_rate[0x20]; 1355 1356 u8 rpg_gd[0x20]; 1357 1358 u8 rpg_min_dec_fac[0x20]; 1359 1360 u8 rpg_min_rate[0x20]; 1361 1362 u8 reserved_1[0x640]; 1363}; 1364 1365enum { 1366 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1367 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1368 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1369}; 1370 1371struct mlx5_ifc_resize_field_select_bits { 1372 u8 resize_field_select[0x20]; 1373}; 1374 1375enum { 1376 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1377 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1378 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1379 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1380 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE = 0x10, 1381 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS = 0x20, 1382}; 1383 1384struct mlx5_ifc_modify_field_select_bits { 1385 u8 modify_field_select[0x20]; 1386}; 1387 1388struct mlx5_ifc_field_select_r_roce_np_bits { 1389 u8 field_select_r_roce_np[0x20]; 1390}; 1391 1392enum { 1393 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE = 0x2, 1394 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC = 0x4, 1395 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET = 0x8, 1396 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET = 0x10, 1397 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD = 0x20, 1398 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE = 0x40, 1399 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE = 0x80, 1400 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE = 0x100, 1401 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC = 0x200, 1402 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE = 0x400, 1403 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP = 0x800, 1404 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G = 0x1000, 1405 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT = 0x2000, 1406 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD = 0x4000, 1407 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE = 0x8000, 1408}; 1409 1410struct mlx5_ifc_field_select_r_roce_rp_bits { 1411 u8 field_select_r_roce_rp[0x20]; 1412}; 1413 1414enum { 1415 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1416 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1417 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1418 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1419 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1420 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1421 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1422 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1423 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1424 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1425}; 1426 1427struct mlx5_ifc_field_select_802_1qau_rp_bits { 1428 u8 field_select_8021qaurp[0x20]; 1429}; 1430 1431struct mlx5_ifc_pptb_reg_bits { 1432 u8 reserved_0[0x2]; 1433 u8 mm[0x2]; 1434 u8 reserved_1[0x4]; 1435 u8 local_port[0x8]; 1436 u8 reserved_2[0x6]; 1437 u8 cm[0x1]; 1438 u8 um[0x1]; 1439 u8 pm[0x8]; 1440 1441 u8 prio7buff[0x4]; 1442 u8 prio6buff[0x4]; 1443 u8 prio5buff[0x4]; 1444 u8 prio4buff[0x4]; 1445 u8 prio3buff[0x4]; 1446 u8 prio2buff[0x4]; 1447 u8 prio1buff[0x4]; 1448 u8 prio0buff[0x4]; 1449 1450 u8 pm_msb[0x8]; 1451 u8 reserved_3[0x10]; 1452 u8 ctrl_buff[0x4]; 1453 u8 untagged_buff[0x4]; 1454}; 1455 1456struct mlx5_ifc_dcbx_app_reg_bits { 1457 u8 reserved_0[0x8]; 1458 u8 port_number[0x8]; 1459 u8 reserved_1[0x10]; 1460 1461 u8 reserved_2[0x1a]; 1462 u8 num_app_prio[0x6]; 1463 1464 u8 reserved_3[0x40]; 1465 1466 struct mlx5_ifc_application_prio_entry_bits app_prio[0]; 1467}; 1468 1469struct mlx5_ifc_dcbx_param_reg_bits { 1470 u8 dcbx_cee_cap[0x1]; 1471 u8 dcbx_ieee_cap[0x1]; 1472 u8 dcbx_standby_cap[0x1]; 1473 u8 reserved_0[0x5]; 1474 u8 port_number[0x8]; 1475 u8 reserved_1[0xa]; 1476 u8 max_application_table_size[0x6]; 1477 1478 u8 reserved_2[0x15]; 1479 u8 version_oper[0x3]; 1480 u8 reserved_3[0x5]; 1481 u8 version_admin[0x3]; 1482 1483 u8 willing_admin[0x1]; 1484 u8 reserved_4[0x3]; 1485 u8 pfc_cap_oper[0x4]; 1486 u8 reserved_5[0x4]; 1487 u8 pfc_cap_admin[0x4]; 1488 u8 reserved_6[0x4]; 1489 u8 num_of_tc_oper[0x4]; 1490 u8 reserved_7[0x4]; 1491 u8 num_of_tc_admin[0x4]; 1492 1493 u8 remote_willing[0x1]; 1494 u8 reserved_8[0x3]; 1495 u8 remote_pfc_cap[0x4]; 1496 u8 reserved_9[0x14]; 1497 u8 remote_num_of_tc[0x4]; 1498 1499 u8 reserved_10[0x18]; 1500 u8 error[0x8]; 1501 1502 u8 reserved_11[0x160]; 1503}; 1504 1505struct mlx5_ifc_qhll_bits { 1506 u8 reserved_at_0[0x8]; 1507 u8 local_port[0x8]; 1508 u8 reserved_at_10[0x10]; 1509 1510 u8 reserved_at_20[0x1b]; 1511 u8 hll_time[0x5]; 1512 1513 u8 stall_en[0x1]; 1514 u8 reserved_at_41[0x1c]; 1515 u8 stall_cnt[0x3]; 1516}; 1517 1518struct mlx5_ifc_qetcr_reg_bits { 1519 u8 operation_type[0x2]; 1520 u8 cap_local_admin[0x1]; 1521 u8 cap_remote_admin[0x1]; 1522 u8 reserved_0[0x4]; 1523 u8 port_number[0x8]; 1524 u8 reserved_1[0x10]; 1525 1526 u8 reserved_2[0x20]; 1527 1528 u8 tc[8][0x40]; 1529 1530 u8 global_configuration[0x40]; 1531}; 1532 1533struct mlx5_ifc_nodnic_ring_config_reg_bits { 1534 u8 queue_address_63_32[0x20]; 1535 1536 u8 queue_address_31_12[0x14]; 1537 u8 reserved_0[0x6]; 1538 u8 log_size[0x6]; 1539 1540 struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell; 1541 1542 u8 reserved_1[0x8]; 1543 u8 queue_number[0x18]; 1544 1545 u8 q_key[0x20]; 1546 1547 u8 reserved_2[0x10]; 1548 u8 pkey_index[0x10]; 1549 1550 u8 reserved_3[0x40]; 1551}; 1552 1553struct mlx5_ifc_nodnic_cq_arming_word_bits { 1554 u8 reserved_0[0x8]; 1555 u8 cq_ci[0x10]; 1556 u8 reserved_1[0x8]; 1557}; 1558 1559enum { 1560 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND = 0x0, 1561 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET = 0x1, 1562}; 1563 1564enum { 1565 MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN = 0x0, 1566 MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE = 0x1, 1567 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED = 0x2, 1568 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE = 0x3, 1569}; 1570 1571struct mlx5_ifc_nodnic_event_word_bits { 1572 u8 driver_reset_needed[0x1]; 1573 u8 port_management_change_event[0x1]; 1574 u8 reserved_0[0x19]; 1575 u8 link_type[0x1]; 1576 u8 port_state[0x4]; 1577}; 1578 1579struct mlx5_ifc_nic_vport_change_event_bits { 1580 u8 reserved_0[0x10]; 1581 u8 vport_num[0x10]; 1582 1583 u8 reserved_1[0xc0]; 1584}; 1585 1586struct mlx5_ifc_pages_req_event_bits { 1587 u8 reserved_0[0x10]; 1588 u8 function_id[0x10]; 1589 1590 u8 num_pages[0x20]; 1591 1592 u8 reserved_1[0xa0]; 1593}; 1594 1595struct mlx5_ifc_cmd_inter_comp_event_bits { 1596 u8 command_completion_vector[0x20]; 1597 1598 u8 reserved_0[0xc0]; 1599}; 1600 1601struct mlx5_ifc_stall_vl_event_bits { 1602 u8 reserved_0[0x18]; 1603 u8 port_num[0x1]; 1604 u8 reserved_1[0x3]; 1605 u8 vl[0x4]; 1606 1607 u8 reserved_2[0xa0]; 1608}; 1609 1610struct mlx5_ifc_db_bf_congestion_event_bits { 1611 u8 event_subtype[0x8]; 1612 u8 reserved_0[0x8]; 1613 u8 congestion_level[0x8]; 1614 u8 reserved_1[0x8]; 1615 1616 u8 reserved_2[0xa0]; 1617}; 1618 1619struct mlx5_ifc_gpio_event_bits { 1620 u8 reserved_0[0x60]; 1621 1622 u8 gpio_event_hi[0x20]; 1623 1624 u8 gpio_event_lo[0x20]; 1625 1626 u8 reserved_1[0x40]; 1627}; 1628 1629struct mlx5_ifc_port_state_change_event_bits { 1630 u8 reserved_0[0x40]; 1631 1632 u8 port_num[0x4]; 1633 u8 reserved_1[0x1c]; 1634 1635 u8 reserved_2[0x80]; 1636}; 1637 1638struct mlx5_ifc_dropped_packet_logged_bits { 1639 u8 reserved_0[0xe0]; 1640}; 1641 1642enum { 1643 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 1644 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 1645}; 1646 1647struct mlx5_ifc_cq_error_bits { 1648 u8 reserved_0[0x8]; 1649 u8 cqn[0x18]; 1650 1651 u8 reserved_1[0x20]; 1652 1653 u8 reserved_2[0x18]; 1654 u8 syndrome[0x8]; 1655 1656 u8 reserved_3[0x80]; 1657}; 1658 1659struct mlx5_ifc_rdma_page_fault_event_bits { 1660 u8 bytes_commited[0x20]; 1661 1662 u8 r_key[0x20]; 1663 1664 u8 reserved_0[0x10]; 1665 u8 packet_len[0x10]; 1666 1667 u8 rdma_op_len[0x20]; 1668 1669 u8 rdma_va[0x40]; 1670 1671 u8 reserved_1[0x5]; 1672 u8 rdma[0x1]; 1673 u8 write[0x1]; 1674 u8 requestor[0x1]; 1675 u8 qp_number[0x18]; 1676}; 1677 1678struct mlx5_ifc_wqe_associated_page_fault_event_bits { 1679 u8 bytes_committed[0x20]; 1680 1681 u8 reserved_0[0x10]; 1682 u8 wqe_index[0x10]; 1683 1684 u8 reserved_1[0x10]; 1685 u8 len[0x10]; 1686 1687 u8 reserved_2[0x60]; 1688 1689 u8 reserved_3[0x5]; 1690 u8 rdma[0x1]; 1691 u8 write_read[0x1]; 1692 u8 requestor[0x1]; 1693 u8 qpn[0x18]; 1694}; 1695 1696enum { 1697 MLX5_QP_EVENTS_TYPE_QP = 0x0, 1698 MLX5_QP_EVENTS_TYPE_RQ = 0x1, 1699 MLX5_QP_EVENTS_TYPE_SQ = 0x2, 1700}; 1701 1702struct mlx5_ifc_qp_events_bits { 1703 u8 reserved_0[0xa0]; 1704 1705 u8 type[0x8]; 1706 u8 reserved_1[0x18]; 1707 1708 u8 reserved_2[0x8]; 1709 u8 qpn_rqn_sqn[0x18]; 1710}; 1711 1712struct mlx5_ifc_dct_events_bits { 1713 u8 reserved_0[0xc0]; 1714 1715 u8 reserved_1[0x8]; 1716 u8 dct_number[0x18]; 1717}; 1718 1719struct mlx5_ifc_comp_event_bits { 1720 u8 reserved_0[0xc0]; 1721 1722 u8 reserved_1[0x8]; 1723 u8 cq_number[0x18]; 1724}; 1725 1726struct mlx5_ifc_fw_version_bits { 1727 u8 major[0x10]; 1728 u8 reserved_0[0x10]; 1729 1730 u8 minor[0x10]; 1731 u8 subminor[0x10]; 1732 1733 u8 second[0x8]; 1734 u8 minute[0x8]; 1735 u8 hour[0x8]; 1736 u8 reserved_1[0x8]; 1737 1738 u8 year[0x10]; 1739 u8 month[0x8]; 1740 u8 day[0x8]; 1741}; 1742 1743enum { 1744 MLX5_QPC_STATE_RST = 0x0, 1745 MLX5_QPC_STATE_INIT = 0x1, 1746 MLX5_QPC_STATE_RTR = 0x2, 1747 MLX5_QPC_STATE_RTS = 0x3, 1748 MLX5_QPC_STATE_SQER = 0x4, 1749 MLX5_QPC_STATE_SQD = 0x5, 1750 MLX5_QPC_STATE_ERR = 0x6, 1751 MLX5_QPC_STATE_SUSPENDED = 0x9, 1752}; 1753 1754enum { 1755 MLX5_QPC_ST_RC = 0x0, 1756 MLX5_QPC_ST_UC = 0x1, 1757 MLX5_QPC_ST_UD = 0x2, 1758 MLX5_QPC_ST_XRC = 0x3, 1759 MLX5_QPC_ST_DCI = 0x5, 1760 MLX5_QPC_ST_QP0 = 0x7, 1761 MLX5_QPC_ST_QP1 = 0x8, 1762 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 1763 MLX5_QPC_ST_REG_UMR = 0xc, 1764}; 1765 1766enum { 1767 MLX5_QP_PM_ARMED = 0x0, 1768 MLX5_QP_PM_REARM = 0x1, 1769 MLX5_QPC_PM_STATE_RESERVED = 0x2, 1770 MLX5_QP_PM_MIGRATED = 0x3, 1771}; 1772 1773enum { 1774 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 1775 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 1776}; 1777 1778enum { 1779 MLX5_QPC_MTU_256_BYTES = 0x1, 1780 MLX5_QPC_MTU_512_BYTES = 0x2, 1781 MLX5_QPC_MTU_1K_BYTES = 0x3, 1782 MLX5_QPC_MTU_2K_BYTES = 0x4, 1783 MLX5_QPC_MTU_4K_BYTES = 0x5, 1784 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 1785}; 1786 1787enum { 1788 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 1789 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 1790 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 1791 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 1792 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 1793 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 1794 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 1795 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 1796}; 1797 1798enum { 1799 MLX5_QPC_CS_REQ_DISABLE = 0x0, 1800 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 1801 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 1802}; 1803 1804enum { 1805 MLX5_QPC_CS_RES_DISABLE = 0x0, 1806 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 1807 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 1808}; 1809 1810struct mlx5_ifc_qpc_bits { 1811 u8 state[0x4]; 1812 u8 lag_tx_port_affinity[0x4]; 1813 u8 st[0x8]; 1814 u8 reserved_1[0x3]; 1815 u8 pm_state[0x2]; 1816 u8 reserved_2[0x7]; 1817 u8 end_padding_mode[0x2]; 1818 u8 reserved_3[0x2]; 1819 1820 u8 wq_signature[0x1]; 1821 u8 block_lb_mc[0x1]; 1822 u8 atomic_like_write_en[0x1]; 1823 u8 latency_sensitive[0x1]; 1824 u8 reserved_4[0x1]; 1825 u8 drain_sigerr[0x1]; 1826 u8 reserved_5[0x2]; 1827 u8 pd[0x18]; 1828 1829 u8 mtu[0x3]; 1830 u8 log_msg_max[0x5]; 1831 u8 reserved_6[0x1]; 1832 u8 log_rq_size[0x4]; 1833 u8 log_rq_stride[0x3]; 1834 u8 no_sq[0x1]; 1835 u8 log_sq_size[0x4]; 1836 u8 reserved_7[0x6]; 1837 u8 rlky[0x1]; 1838 u8 ulp_stateless_offload_mode[0x4]; 1839 1840 u8 counter_set_id[0x8]; 1841 u8 uar_page[0x18]; 1842 1843 u8 reserved_8[0x8]; 1844 u8 user_index[0x18]; 1845 1846 u8 reserved_9[0x3]; 1847 u8 log_page_size[0x5]; 1848 u8 remote_qpn[0x18]; 1849 1850 struct mlx5_ifc_ads_bits primary_address_path; 1851 1852 struct mlx5_ifc_ads_bits secondary_address_path; 1853 1854 u8 log_ack_req_freq[0x4]; 1855 u8 reserved_10[0x4]; 1856 u8 log_sra_max[0x3]; 1857 u8 reserved_11[0x2]; 1858 u8 retry_count[0x3]; 1859 u8 rnr_retry[0x3]; 1860 u8 reserved_12[0x1]; 1861 u8 fre[0x1]; 1862 u8 cur_rnr_retry[0x3]; 1863 u8 cur_retry_count[0x3]; 1864 u8 reserved_13[0x5]; 1865 1866 u8 reserved_14[0x20]; 1867 1868 u8 reserved_15[0x8]; 1869 u8 next_send_psn[0x18]; 1870 1871 u8 reserved_16[0x8]; 1872 u8 cqn_snd[0x18]; 1873 1874 u8 reserved_at_400[0x8]; 1875 1876 u8 deth_sqpn[0x18]; 1877 u8 reserved_17[0x20]; 1878 1879 u8 reserved_18[0x8]; 1880 u8 last_acked_psn[0x18]; 1881 1882 u8 reserved_19[0x8]; 1883 u8 ssn[0x18]; 1884 1885 u8 reserved_20[0x8]; 1886 u8 log_rra_max[0x3]; 1887 u8 reserved_21[0x1]; 1888 u8 atomic_mode[0x4]; 1889 u8 rre[0x1]; 1890 u8 rwe[0x1]; 1891 u8 rae[0x1]; 1892 u8 reserved_22[0x1]; 1893 u8 page_offset[0x6]; 1894 u8 reserved_23[0x3]; 1895 u8 cd_slave_receive[0x1]; 1896 u8 cd_slave_send[0x1]; 1897 u8 cd_master[0x1]; 1898 1899 u8 reserved_24[0x3]; 1900 u8 min_rnr_nak[0x5]; 1901 u8 next_rcv_psn[0x18]; 1902 1903 u8 reserved_25[0x8]; 1904 u8 xrcd[0x18]; 1905 1906 u8 reserved_26[0x8]; 1907 u8 cqn_rcv[0x18]; 1908 1909 u8 dbr_addr[0x40]; 1910 1911 u8 q_key[0x20]; 1912 1913 u8 reserved_27[0x5]; 1914 u8 rq_type[0x3]; 1915 u8 srqn_rmpn[0x18]; 1916 1917 u8 reserved_28[0x8]; 1918 u8 rmsn[0x18]; 1919 1920 u8 hw_sq_wqebb_counter[0x10]; 1921 u8 sw_sq_wqebb_counter[0x10]; 1922 1923 u8 hw_rq_counter[0x20]; 1924 1925 u8 sw_rq_counter[0x20]; 1926 1927 u8 reserved_29[0x20]; 1928 1929 u8 reserved_30[0xf]; 1930 u8 cgs[0x1]; 1931 u8 cs_req[0x8]; 1932 u8 cs_res[0x8]; 1933 1934 u8 dc_access_key[0x40]; 1935 1936 u8 rdma_active[0x1]; 1937 u8 comm_est[0x1]; 1938 u8 suspended[0x1]; 1939 u8 reserved_31[0x5]; 1940 u8 send_msg_psn[0x18]; 1941 1942 u8 reserved_32[0x8]; 1943 u8 rcv_msg_psn[0x18]; 1944 1945 u8 rdma_va[0x40]; 1946 1947 u8 rdma_key[0x20]; 1948 1949 u8 reserved_33[0x20]; 1950}; 1951 1952struct mlx5_ifc_roce_addr_layout_bits { 1953 u8 source_l3_address[16][0x8]; 1954 1955 u8 reserved_0[0x3]; 1956 u8 vlan_valid[0x1]; 1957 u8 vlan_id[0xc]; 1958 u8 source_mac_47_32[0x10]; 1959 1960 u8 source_mac_31_0[0x20]; 1961 1962 u8 reserved_1[0x14]; 1963 u8 roce_l3_type[0x4]; 1964 u8 roce_version[0x8]; 1965 1966 u8 reserved_2[0x20]; 1967}; 1968 1969struct mlx5_ifc_rdbc_bits { 1970 u8 reserved_0[0x1c]; 1971 u8 type[0x4]; 1972 1973 u8 reserved_1[0x20]; 1974 1975 u8 reserved_2[0x8]; 1976 u8 psn[0x18]; 1977 1978 u8 rkey[0x20]; 1979 1980 u8 address[0x40]; 1981 1982 u8 byte_count[0x20]; 1983 1984 u8 reserved_3[0x20]; 1985 1986 u8 atomic_resp[32][0x8]; 1987}; 1988 1989enum { 1990 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 1991 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 1992 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 1993 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 1994}; 1995 1996struct mlx5_ifc_flow_context_bits { 1997 u8 reserved_0[0x20]; 1998 1999 u8 group_id[0x20]; 2000 2001 u8 reserved_1[0x8]; 2002 u8 flow_tag[0x18]; 2003 2004 u8 reserved_2[0x10]; 2005 u8 action[0x10]; 2006 2007 u8 reserved_3[0x8]; 2008 u8 destination_list_size[0x18]; 2009 2010 u8 reserved_4[0x8]; 2011 u8 flow_counter_list_size[0x18]; 2012 2013 u8 reserved_5[0x140]; 2014 2015 struct mlx5_ifc_fte_match_param_bits match_value; 2016 2017 u8 reserved_6[0x600]; 2018 2019 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2020}; 2021 2022enum { 2023 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2024 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2025}; 2026 2027struct mlx5_ifc_xrc_srqc_bits { 2028 u8 state[0x4]; 2029 u8 log_xrc_srq_size[0x4]; 2030 u8 reserved_0[0x18]; 2031 2032 u8 wq_signature[0x1]; 2033 u8 cont_srq[0x1]; 2034 u8 reserved_1[0x1]; 2035 u8 rlky[0x1]; 2036 u8 basic_cyclic_rcv_wqe[0x1]; 2037 u8 log_rq_stride[0x3]; 2038 u8 xrcd[0x18]; 2039 2040 u8 page_offset[0x6]; 2041 u8 reserved_2[0x2]; 2042 u8 cqn[0x18]; 2043 2044 u8 reserved_3[0x20]; 2045 2046 u8 reserved_4[0x2]; 2047 u8 log_page_size[0x6]; 2048 u8 user_index[0x18]; 2049 2050 u8 reserved_5[0x20]; 2051 2052 u8 reserved_6[0x8]; 2053 u8 pd[0x18]; 2054 2055 u8 lwm[0x10]; 2056 u8 wqe_cnt[0x10]; 2057 2058 u8 reserved_7[0x40]; 2059 2060 u8 db_record_addr_h[0x20]; 2061 2062 u8 db_record_addr_l[0x1e]; 2063 u8 reserved_8[0x2]; 2064 2065 u8 reserved_9[0x80]; 2066}; 2067 2068struct mlx5_ifc_traffic_counter_bits { 2069 u8 packets[0x40]; 2070 2071 u8 octets[0x40]; 2072}; 2073 2074struct mlx5_ifc_tisc_bits { 2075 u8 strict_lag_tx_port_affinity[0x1]; 2076 u8 reserved_at_1[0x3]; 2077 u8 lag_tx_port_affinity[0x04]; 2078 2079 u8 reserved_at_8[0x4]; 2080 u8 prio[0x4]; 2081 u8 reserved_1[0x10]; 2082 2083 u8 reserved_2[0x100]; 2084 2085 u8 reserved_3[0x8]; 2086 u8 transport_domain[0x18]; 2087 2088 u8 reserved_4[0x8]; 2089 u8 underlay_qpn[0x18]; 2090 2091 u8 reserved_5[0x3a0]; 2092}; 2093 2094enum { 2095 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2096 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2097}; 2098 2099enum { 2100 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2101 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2102}; 2103 2104enum { 2105 MLX5_TIRC_RX_HASH_FN_HASH_NONE = 0x0, 2106 MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8 = 0x1, 2107 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ = 0x2, 2108}; 2109 2110enum { 2111 MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST = 0x1, 2112 MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST = 0x2, 2113}; 2114 2115struct mlx5_ifc_tirc_bits { 2116 u8 reserved_0[0x20]; 2117 2118 u8 disp_type[0x4]; 2119 u8 reserved_1[0x1c]; 2120 2121 u8 reserved_2[0x40]; 2122 2123 u8 reserved_3[0x4]; 2124 u8 lro_timeout_period_usecs[0x10]; 2125 u8 lro_enable_mask[0x4]; 2126 u8 lro_max_msg_sz[0x8]; 2127 2128 u8 reserved_4[0x40]; 2129 2130 u8 reserved_5[0x8]; 2131 u8 inline_rqn[0x18]; 2132 2133 u8 rx_hash_symmetric[0x1]; 2134 u8 reserved_6[0x1]; 2135 u8 tunneled_offload_en[0x1]; 2136 u8 reserved_7[0x5]; 2137 u8 indirect_table[0x18]; 2138 2139 u8 rx_hash_fn[0x4]; 2140 u8 reserved_8[0x2]; 2141 u8 self_lb_en[0x2]; 2142 u8 transport_domain[0x18]; 2143 2144 u8 rx_hash_toeplitz_key[10][0x20]; 2145 2146 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2147 2148 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2149 2150 u8 reserved_9[0x4c0]; 2151}; 2152 2153enum { 2154 MLX5_SRQC_STATE_GOOD = 0x0, 2155 MLX5_SRQC_STATE_ERROR = 0x1, 2156}; 2157 2158struct mlx5_ifc_srqc_bits { 2159 u8 state[0x4]; 2160 u8 log_srq_size[0x4]; 2161 u8 reserved_0[0x18]; 2162 2163 u8 wq_signature[0x1]; 2164 u8 cont_srq[0x1]; 2165 u8 reserved_1[0x1]; 2166 u8 rlky[0x1]; 2167 u8 reserved_2[0x1]; 2168 u8 log_rq_stride[0x3]; 2169 u8 xrcd[0x18]; 2170 2171 u8 page_offset[0x6]; 2172 u8 reserved_3[0x2]; 2173 u8 cqn[0x18]; 2174 2175 u8 reserved_4[0x20]; 2176 2177 u8 reserved_5[0x2]; 2178 u8 log_page_size[0x6]; 2179 u8 reserved_6[0x18]; 2180 2181 u8 reserved_7[0x20]; 2182 2183 u8 reserved_8[0x8]; 2184 u8 pd[0x18]; 2185 2186 u8 lwm[0x10]; 2187 u8 wqe_cnt[0x10]; 2188 2189 u8 reserved_9[0x40]; 2190 2191 u8 dbr_addr[0x40]; 2192 2193 u8 reserved_10[0x80]; 2194}; 2195 2196enum { 2197 MLX5_SQC_STATE_RST = 0x0, 2198 MLX5_SQC_STATE_RDY = 0x1, 2199 MLX5_SQC_STATE_ERR = 0x3, 2200}; 2201 2202struct mlx5_ifc_sqc_bits { 2203 u8 rlkey[0x1]; 2204 u8 cd_master[0x1]; 2205 u8 fre[0x1]; 2206 u8 flush_in_error_en[0x1]; 2207 u8 allow_multi_pkt_send_wqe[0x1]; 2208 u8 min_wqe_inline_mode[0x3]; 2209 u8 state[0x4]; 2210 u8 reg_umr[0x1]; 2211 u8 allow_swp[0x1]; 2212 u8 reserved_0[0x12]; 2213 2214 u8 reserved_1[0x8]; 2215 u8 user_index[0x18]; 2216 2217 u8 reserved_2[0x8]; 2218 u8 cqn[0x18]; 2219 2220 u8 reserved_3[0x80]; 2221 2222 u8 qos_para_vport_number[0x10]; 2223 u8 packet_pacing_rate_limit_index[0x10]; 2224 2225 u8 tis_lst_sz[0x10]; 2226 u8 reserved_4[0x10]; 2227 2228 u8 reserved_5[0x40]; 2229 2230 u8 reserved_6[0x8]; 2231 u8 tis_num_0[0x18]; 2232 2233 struct mlx5_ifc_wq_bits wq; 2234}; 2235 2236enum { 2237 MLX5_TSAR_TYPE_DWRR = 0, 2238 MLX5_TSAR_TYPE_ROUND_ROUBIN = 1, 2239 MLX5_TSAR_TYPE_ETS = 2 2240}; 2241 2242struct mlx5_ifc_tsar_element_attributes_bits { 2243 u8 reserved_0[0x8]; 2244 u8 tsar_type[0x8]; 2245 u8 reserved_1[0x10]; 2246}; 2247 2248struct mlx5_ifc_vport_element_attributes_bits { 2249 u8 reserved_0[0x10]; 2250 u8 vport_number[0x10]; 2251}; 2252 2253struct mlx5_ifc_vport_tc_element_attributes_bits { 2254 u8 traffic_class[0x10]; 2255 u8 vport_number[0x10]; 2256}; 2257 2258struct mlx5_ifc_para_vport_tc_element_attributes_bits { 2259 u8 reserved_0[0x0C]; 2260 u8 traffic_class[0x04]; 2261 u8 qos_para_vport_number[0x10]; 2262}; 2263 2264enum { 2265 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2266 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2267 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2268 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2269}; 2270 2271struct mlx5_ifc_scheduling_context_bits { 2272 u8 element_type[0x8]; 2273 u8 reserved_at_8[0x18]; 2274 2275 u8 element_attributes[0x20]; 2276 2277 u8 parent_element_id[0x20]; 2278 2279 u8 reserved_at_60[0x40]; 2280 2281 u8 bw_share[0x20]; 2282 2283 u8 max_average_bw[0x20]; 2284 2285 u8 reserved_at_e0[0x120]; 2286}; 2287 2288struct mlx5_ifc_rqtc_bits { 2289 u8 reserved_0[0xa0]; 2290 2291 u8 reserved_1[0x10]; 2292 u8 rqt_max_size[0x10]; 2293 2294 u8 reserved_2[0x10]; 2295 u8 rqt_actual_size[0x10]; 2296 2297 u8 reserved_3[0x6a0]; 2298 2299 struct mlx5_ifc_rq_num_bits rq_num[0]; 2300}; 2301 2302enum { 2303 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2304 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2305}; 2306 2307enum { 2308 MLX5_RQC_STATE_RST = 0x0, 2309 MLX5_RQC_STATE_RDY = 0x1, 2310 MLX5_RQC_STATE_ERR = 0x3, 2311}; 2312 2313enum { 2314 MLX5_RQC_DROPLESS_MODE_DISABLE = 0x0, 2315 MLX5_RQC_DROPLESS_MODE_ENABLE = 0x1, 2316}; 2317 2318struct mlx5_ifc_rqc_bits { 2319 u8 rlkey[0x1]; 2320 u8 delay_drop_en[0x1]; 2321 u8 scatter_fcs[0x1]; 2322 u8 vlan_strip_disable[0x1]; 2323 u8 mem_rq_type[0x4]; 2324 u8 state[0x4]; 2325 u8 reserved_1[0x1]; 2326 u8 flush_in_error_en[0x1]; 2327 u8 reserved_2[0x12]; 2328 2329 u8 reserved_3[0x8]; 2330 u8 user_index[0x18]; 2331 2332 u8 reserved_4[0x8]; 2333 u8 cqn[0x18]; 2334 2335 u8 counter_set_id[0x8]; 2336 u8 reserved_5[0x18]; 2337 2338 u8 reserved_6[0x8]; 2339 u8 rmpn[0x18]; 2340 2341 u8 reserved_7[0xe0]; 2342 2343 struct mlx5_ifc_wq_bits wq; 2344}; 2345 2346enum { 2347 MLX5_RMPC_STATE_RDY = 0x1, 2348 MLX5_RMPC_STATE_ERR = 0x3, 2349}; 2350 2351struct mlx5_ifc_rmpc_bits { 2352 u8 reserved_0[0x8]; 2353 u8 state[0x4]; 2354 u8 reserved_1[0x14]; 2355 2356 u8 basic_cyclic_rcv_wqe[0x1]; 2357 u8 reserved_2[0x1f]; 2358 2359 u8 reserved_3[0x140]; 2360 2361 struct mlx5_ifc_wq_bits wq; 2362}; 2363 2364enum { 2365 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0, 2366 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS = 0x1, 2367 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST = 0x2, 2368}; 2369 2370struct mlx5_ifc_nic_vport_context_bits { 2371 u8 reserved_0[0x5]; 2372 u8 min_wqe_inline_mode[0x3]; 2373 u8 reserved_1[0x15]; 2374 u8 disable_mc_local_lb[0x1]; 2375 u8 disable_uc_local_lb[0x1]; 2376 u8 roce_en[0x1]; 2377 2378 u8 arm_change_event[0x1]; 2379 u8 reserved_2[0x1a]; 2380 u8 event_on_mtu[0x1]; 2381 u8 event_on_promisc_change[0x1]; 2382 u8 event_on_vlan_change[0x1]; 2383 u8 event_on_mc_address_change[0x1]; 2384 u8 event_on_uc_address_change[0x1]; 2385 2386 u8 reserved_3[0xe0]; 2387 2388 u8 reserved_4[0x10]; 2389 u8 mtu[0x10]; 2390 2391 u8 system_image_guid[0x40]; 2392 2393 u8 port_guid[0x40]; 2394 2395 u8 node_guid[0x40]; 2396 2397 u8 reserved_5[0x140]; 2398 2399 u8 qkey_violation_counter[0x10]; 2400 u8 reserved_6[0x10]; 2401 2402 u8 reserved_7[0x420]; 2403 2404 u8 promisc_uc[0x1]; 2405 u8 promisc_mc[0x1]; 2406 u8 promisc_all[0x1]; 2407 u8 reserved_8[0x2]; 2408 u8 allowed_list_type[0x3]; 2409 u8 reserved_9[0xc]; 2410 u8 allowed_list_size[0xc]; 2411 2412 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2413 2414 u8 reserved_10[0x20]; 2415 2416 u8 current_uc_mac_address[0][0x40]; 2417}; 2418 2419enum { 2420 MLX5_ACCESS_MODE_PA = 0x0, 2421 MLX5_ACCESS_MODE_MTT = 0x1, 2422 MLX5_ACCESS_MODE_KLM = 0x2, 2423}; 2424 2425struct mlx5_ifc_mkc_bits { 2426 u8 reserved_0[0x1]; 2427 u8 free[0x1]; 2428 u8 reserved_1[0xd]; 2429 u8 small_fence_on_rdma_read_response[0x1]; 2430 u8 umr_en[0x1]; 2431 u8 a[0x1]; 2432 u8 rw[0x1]; 2433 u8 rr[0x1]; 2434 u8 lw[0x1]; 2435 u8 lr[0x1]; 2436 u8 access_mode[0x2]; 2437 u8 reserved_2[0x8]; 2438 2439 u8 qpn[0x18]; 2440 u8 mkey_7_0[0x8]; 2441 2442 u8 reserved_3[0x20]; 2443 2444 u8 length64[0x1]; 2445 u8 bsf_en[0x1]; 2446 u8 sync_umr[0x1]; 2447 u8 reserved_4[0x2]; 2448 u8 expected_sigerr_count[0x1]; 2449 u8 reserved_5[0x1]; 2450 u8 en_rinval[0x1]; 2451 u8 pd[0x18]; 2452 2453 u8 start_addr[0x40]; 2454 2455 u8 len[0x40]; 2456 2457 u8 bsf_octword_size[0x20]; 2458 2459 u8 reserved_6[0x80]; 2460 2461 u8 translations_octword_size[0x20]; 2462 2463 u8 reserved_7[0x1b]; 2464 u8 log_page_size[0x5]; 2465 2466 u8 reserved_8[0x20]; 2467}; 2468 2469struct mlx5_ifc_pkey_bits { 2470 u8 reserved_0[0x10]; 2471 u8 pkey[0x10]; 2472}; 2473 2474struct mlx5_ifc_array128_auto_bits { 2475 u8 array128_auto[16][0x8]; 2476}; 2477 2478enum { 2479 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID = 0x0, 2480 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID = 0x1, 2481 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY = 0x2, 2482}; 2483 2484enum { 2485 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP = 0x1, 2486 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING = 0x2, 2487 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED = 0x3, 2488 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING = 0x4, 2489 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP = 0x5, 2490 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY = 0x6, 2491 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST = 0x7, 2492}; 2493 2494enum { 2495 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN = 0x0, 2496 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP = 0x1, 2497 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW = 0x2, 2498}; 2499 2500enum { 2501 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN = 0x1, 2502 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT = 0x2, 2503 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM = 0x3, 2504 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE = 0x4, 2505}; 2506 2507enum { 2508 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN = 0x1, 2509 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT = 0x2, 2510 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM = 0x3, 2511 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE = 0x4, 2512}; 2513 2514struct mlx5_ifc_hca_vport_context_bits { 2515 u8 field_select[0x20]; 2516 2517 u8 reserved_0[0xe0]; 2518 2519 u8 sm_virt_aware[0x1]; 2520 u8 has_smi[0x1]; 2521 u8 has_raw[0x1]; 2522 u8 grh_required[0x1]; 2523 u8 reserved_1[0x1]; 2524 u8 min_wqe_inline_mode[0x3]; 2525 u8 reserved_2[0x8]; 2526 u8 port_physical_state[0x4]; 2527 u8 vport_state_policy[0x4]; 2528 u8 port_state[0x4]; 2529 u8 vport_state[0x4]; 2530 2531 u8 reserved_3[0x20]; 2532 2533 u8 system_image_guid[0x40]; 2534 2535 u8 port_guid[0x40]; 2536 2537 u8 node_guid[0x40]; 2538 2539 u8 cap_mask1[0x20]; 2540 2541 u8 cap_mask1_field_select[0x20]; 2542 2543 u8 cap_mask2[0x20]; 2544 2545 u8 cap_mask2_field_select[0x20]; 2546 2547 u8 reserved_4[0x80]; 2548 2549 u8 lid[0x10]; 2550 u8 reserved_5[0x4]; 2551 u8 init_type_reply[0x4]; 2552 u8 lmc[0x3]; 2553 u8 subnet_timeout[0x5]; 2554 2555 u8 sm_lid[0x10]; 2556 u8 sm_sl[0x4]; 2557 u8 reserved_6[0xc]; 2558 2559 u8 qkey_violation_counter[0x10]; 2560 u8 pkey_violation_counter[0x10]; 2561 2562 u8 reserved_7[0xca0]; 2563}; 2564 2565union mlx5_ifc_hca_cap_union_bits { 2566 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2567 struct mlx5_ifc_odp_cap_bits odp_cap; 2568 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2569 struct mlx5_ifc_roce_cap_bits roce_cap; 2570 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2571 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2572 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2573 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2574 struct mlx5_ifc_snapshot_cap_bits snapshot_cap; 2575 struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap; 2576 struct mlx5_ifc_qos_cap_bits qos_cap; 2577 u8 reserved_0[0x8000]; 2578}; 2579 2580enum { 2581 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0, 2582 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1, 2583}; 2584 2585struct mlx5_ifc_flow_table_context_bits { 2586 u8 encap_en[0x1]; 2587 u8 decap_en[0x1]; 2588 u8 reserved_at_2[0x2]; 2589 u8 table_miss_action[0x4]; 2590 u8 level[0x8]; 2591 u8 reserved_at_10[0x8]; 2592 u8 log_size[0x8]; 2593 2594 u8 reserved_at_20[0x8]; 2595 u8 table_miss_id[0x18]; 2596 2597 u8 reserved_at_40[0x8]; 2598 u8 lag_master_next_table_id[0x18]; 2599 2600 u8 reserved_at_60[0xe0]; 2601}; 2602 2603struct mlx5_ifc_esw_vport_context_bits { 2604 u8 reserved_0[0x3]; 2605 u8 vport_svlan_strip[0x1]; 2606 u8 vport_cvlan_strip[0x1]; 2607 u8 vport_svlan_insert[0x1]; 2608 u8 vport_cvlan_insert[0x2]; 2609 u8 reserved_1[0x18]; 2610 2611 u8 reserved_2[0x20]; 2612 2613 u8 svlan_cfi[0x1]; 2614 u8 svlan_pcp[0x3]; 2615 u8 svlan_id[0xc]; 2616 u8 cvlan_cfi[0x1]; 2617 u8 cvlan_pcp[0x3]; 2618 u8 cvlan_id[0xc]; 2619 2620 u8 reserved_3[0x7a0]; 2621}; 2622 2623enum { 2624 MLX5_EQC_STATUS_OK = 0x0, 2625 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2626}; 2627 2628enum { 2629 MLX5_EQ_STATE_ARMED = 0x9, 2630 MLX5_EQ_STATE_FIRED = 0xa, 2631}; 2632 2633struct mlx5_ifc_eqc_bits { 2634 u8 status[0x4]; 2635 u8 reserved_0[0x9]; 2636 u8 ec[0x1]; 2637 u8 oi[0x1]; 2638 u8 reserved_1[0x5]; 2639 u8 st[0x4]; 2640 u8 reserved_2[0x8]; 2641 2642 u8 reserved_3[0x20]; 2643 2644 u8 reserved_4[0x14]; 2645 u8 page_offset[0x6]; 2646 u8 reserved_5[0x6]; 2647 2648 u8 reserved_6[0x3]; 2649 u8 log_eq_size[0x5]; 2650 u8 uar_page[0x18]; 2651 2652 u8 reserved_7[0x20]; 2653 2654 u8 reserved_8[0x18]; 2655 u8 intr[0x8]; 2656 2657 u8 reserved_9[0x3]; 2658 u8 log_page_size[0x5]; 2659 u8 reserved_10[0x18]; 2660 2661 u8 reserved_11[0x60]; 2662 2663 u8 reserved_12[0x8]; 2664 u8 consumer_counter[0x18]; 2665 2666 u8 reserved_13[0x8]; 2667 u8 producer_counter[0x18]; 2668 2669 u8 reserved_14[0x80]; 2670}; 2671 2672enum { 2673 MLX5_DCTC_STATE_ACTIVE = 0x0, 2674 MLX5_DCTC_STATE_DRAINING = 0x1, 2675 MLX5_DCTC_STATE_DRAINED = 0x2, 2676}; 2677 2678enum { 2679 MLX5_DCTC_CS_RES_DISABLE = 0x0, 2680 MLX5_DCTC_CS_RES_NA = 0x1, 2681 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 2682}; 2683 2684enum { 2685 MLX5_DCTC_MTU_256_BYTES = 0x1, 2686 MLX5_DCTC_MTU_512_BYTES = 0x2, 2687 MLX5_DCTC_MTU_1K_BYTES = 0x3, 2688 MLX5_DCTC_MTU_2K_BYTES = 0x4, 2689 MLX5_DCTC_MTU_4K_BYTES = 0x5, 2690}; 2691 2692struct mlx5_ifc_dctc_bits { 2693 u8 reserved_0[0x4]; 2694 u8 state[0x4]; 2695 u8 reserved_1[0x18]; 2696 2697 u8 reserved_2[0x8]; 2698 u8 user_index[0x18]; 2699 2700 u8 reserved_3[0x8]; 2701 u8 cqn[0x18]; 2702 2703 u8 counter_set_id[0x8]; 2704 u8 atomic_mode[0x4]; 2705 u8 rre[0x1]; 2706 u8 rwe[0x1]; 2707 u8 rae[0x1]; 2708 u8 atomic_like_write_en[0x1]; 2709 u8 latency_sensitive[0x1]; 2710 u8 rlky[0x1]; 2711 u8 reserved_4[0xe]; 2712 2713 u8 reserved_5[0x8]; 2714 u8 cs_res[0x8]; 2715 u8 reserved_6[0x3]; 2716 u8 min_rnr_nak[0x5]; 2717 u8 reserved_7[0x8]; 2718 2719 u8 reserved_8[0x8]; 2720 u8 srqn[0x18]; 2721 2722 u8 reserved_9[0x8]; 2723 u8 pd[0x18]; 2724 2725 u8 tclass[0x8]; 2726 u8 reserved_10[0x4]; 2727 u8 flow_label[0x14]; 2728 2729 u8 dc_access_key[0x40]; 2730 2731 u8 reserved_11[0x5]; 2732 u8 mtu[0x3]; 2733 u8 port[0x8]; 2734 u8 pkey_index[0x10]; 2735 2736 u8 reserved_12[0x8]; 2737 u8 my_addr_index[0x8]; 2738 u8 reserved_13[0x8]; 2739 u8 hop_limit[0x8]; 2740 2741 u8 dc_access_key_violation_count[0x20]; 2742 2743 u8 reserved_14[0x14]; 2744 u8 dei_cfi[0x1]; 2745 u8 eth_prio[0x3]; 2746 u8 ecn[0x2]; 2747 u8 dscp[0x6]; 2748 2749 u8 reserved_15[0x40]; 2750}; 2751 2752enum { 2753 MLX5_CQC_STATUS_OK = 0x0, 2754 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 2755 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 2756}; 2757 2758enum { 2759 CQE_SIZE_64 = 0x0, 2760 CQE_SIZE_128 = 0x1, 2761}; 2762 2763enum { 2764 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 2765 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 2766}; 2767 2768enum { 2769 MLX5_CQ_STATE_SOLICITED_ARMED = 0x6, 2770 MLX5_CQ_STATE_ARMED = 0x9, 2771 MLX5_CQ_STATE_FIRED = 0xa, 2772}; 2773 2774struct mlx5_ifc_cqc_bits { 2775 u8 status[0x4]; 2776 u8 reserved_0[0x4]; 2777 u8 cqe_sz[0x3]; 2778 u8 cc[0x1]; 2779 u8 reserved_1[0x1]; 2780 u8 scqe_break_moderation_en[0x1]; 2781 u8 oi[0x1]; 2782 u8 cq_period_mode[0x2]; 2783 u8 cqe_compression_en[0x1]; 2784 u8 mini_cqe_res_format[0x2]; 2785 u8 st[0x4]; 2786 u8 reserved_2[0x8]; 2787 2788 u8 reserved_3[0x20]; 2789 2790 u8 reserved_4[0x14]; 2791 u8 page_offset[0x6]; 2792 u8 reserved_5[0x6]; 2793 2794 u8 reserved_6[0x3]; 2795 u8 log_cq_size[0x5]; 2796 u8 uar_page[0x18]; 2797 2798 u8 reserved_7[0x4]; 2799 u8 cq_period[0xc]; 2800 u8 cq_max_count[0x10]; 2801 2802 u8 reserved_8[0x18]; 2803 u8 c_eqn[0x8]; 2804 2805 u8 reserved_9[0x3]; 2806 u8 log_page_size[0x5]; 2807 u8 reserved_10[0x18]; 2808 2809 u8 reserved_11[0x20]; 2810 2811 u8 reserved_12[0x8]; 2812 u8 last_notified_index[0x18]; 2813 2814 u8 reserved_13[0x8]; 2815 u8 last_solicit_index[0x18]; 2816 2817 u8 reserved_14[0x8]; 2818 u8 consumer_counter[0x18]; 2819 2820 u8 reserved_15[0x8]; 2821 u8 producer_counter[0x18]; 2822 2823 u8 reserved_16[0x40]; 2824 2825 u8 dbr_addr[0x40]; 2826}; 2827 2828union mlx5_ifc_cong_control_roce_ecn_auto_bits { 2829 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 2830 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 2831 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 2832 u8 reserved_0[0x800]; 2833}; 2834 2835struct mlx5_ifc_query_adapter_param_block_bits { 2836 u8 reserved_0[0xc0]; 2837 2838 u8 reserved_1[0x8]; 2839 u8 ieee_vendor_id[0x18]; 2840 2841 u8 reserved_2[0x10]; 2842 u8 vsd_vendor_id[0x10]; 2843 2844 u8 vsd[208][0x8]; 2845 2846 u8 vsd_contd_psid[16][0x8]; 2847}; 2848 2849union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 2850 struct mlx5_ifc_modify_field_select_bits modify_field_select; 2851 struct mlx5_ifc_resize_field_select_bits resize_field_select; 2852 u8 reserved_0[0x20]; 2853}; 2854 2855union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 2856 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 2857 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 2858 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 2859 u8 reserved_0[0x20]; 2860}; 2861 2862struct mlx5_ifc_bufferx_reg_bits { 2863 u8 reserved_0[0x6]; 2864 u8 lossy[0x1]; 2865 u8 epsb[0x1]; 2866 u8 reserved_1[0xc]; 2867 u8 size[0xc]; 2868 2869 u8 xoff_threshold[0x10]; 2870 u8 xon_threshold[0x10]; 2871}; 2872 2873struct mlx5_ifc_config_item_bits { 2874 u8 valid[0x2]; 2875 u8 reserved_0[0x2]; 2876 u8 header_type[0x2]; 2877 u8 reserved_1[0x2]; 2878 u8 default_location[0x1]; 2879 u8 reserved_2[0x7]; 2880 u8 version[0x4]; 2881 u8 reserved_3[0x3]; 2882 u8 length[0x9]; 2883 2884 u8 type[0x20]; 2885 2886 u8 reserved_4[0x10]; 2887 u8 crc16[0x10]; 2888}; 2889 2890struct mlx5_ifc_nodnic_port_config_reg_bits { 2891 struct mlx5_ifc_nodnic_event_word_bits event; 2892 2893 u8 network_en[0x1]; 2894 u8 dma_en[0x1]; 2895 u8 promisc_en[0x1]; 2896 u8 promisc_multicast_en[0x1]; 2897 u8 reserved_0[0x17]; 2898 u8 receive_filter_en[0x5]; 2899 2900 u8 reserved_1[0x10]; 2901 u8 mac_47_32[0x10]; 2902 2903 u8 mac_31_0[0x20]; 2904 2905 u8 receive_filters_mgid_mac[64][0x8]; 2906 2907 u8 gid[16][0x8]; 2908 2909 u8 reserved_2[0x10]; 2910 u8 lid[0x10]; 2911 2912 u8 reserved_3[0xc]; 2913 u8 sm_sl[0x4]; 2914 u8 sm_lid[0x10]; 2915 2916 u8 completion_address_63_32[0x20]; 2917 2918 u8 completion_address_31_12[0x14]; 2919 u8 reserved_4[0x6]; 2920 u8 log_cq_size[0x6]; 2921 2922 u8 working_buffer_address_63_32[0x20]; 2923 2924 u8 working_buffer_address_31_12[0x14]; 2925 u8 reserved_5[0xc]; 2926 2927 struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq; 2928 2929 u8 pkey_index[0x10]; 2930 u8 pkey[0x10]; 2931 2932 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0; 2933 2934 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1; 2935 2936 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0; 2937 2938 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1; 2939 2940 u8 reserved_6[0x400]; 2941}; 2942 2943union mlx5_ifc_event_auto_bits { 2944 struct mlx5_ifc_comp_event_bits comp_event; 2945 struct mlx5_ifc_dct_events_bits dct_events; 2946 struct mlx5_ifc_qp_events_bits qp_events; 2947 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 2948 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 2949 struct mlx5_ifc_cq_error_bits cq_error; 2950 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 2951 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 2952 struct mlx5_ifc_gpio_event_bits gpio_event; 2953 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 2954 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 2955 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 2956 struct mlx5_ifc_pages_req_event_bits pages_req_event; 2957 struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event; 2958 u8 reserved_0[0xe0]; 2959}; 2960 2961struct mlx5_ifc_health_buffer_bits { 2962 u8 reserved_0[0x100]; 2963 2964 u8 assert_existptr[0x20]; 2965 2966 u8 assert_callra[0x20]; 2967 2968 u8 reserved_1[0x40]; 2969 2970 u8 fw_version[0x20]; 2971 2972 u8 hw_id[0x20]; 2973 2974 u8 reserved_2[0x20]; 2975 2976 u8 irisc_index[0x8]; 2977 u8 synd[0x8]; 2978 u8 ext_synd[0x10]; 2979}; 2980 2981struct mlx5_ifc_register_loopback_control_bits { 2982 u8 no_lb[0x1]; 2983 u8 reserved_0[0x7]; 2984 u8 port[0x8]; 2985 u8 reserved_1[0x10]; 2986 2987 u8 reserved_2[0x60]; 2988}; 2989 2990struct mlx5_ifc_lrh_bits { 2991 u8 vl[4]; 2992 u8 lver[4]; 2993 u8 sl[4]; 2994 u8 reserved2[2]; 2995 u8 lnh[2]; 2996 u8 dlid[16]; 2997 u8 reserved5[5]; 2998 u8 pkt_len[11]; 2999 u8 slid[16]; 3000}; 3001 3002struct mlx5_ifc_icmd_set_wol_rol_out_bits { 3003 u8 reserved_0[0x40]; 3004 3005 u8 reserved_1[0x10]; 3006 u8 rol_mode[0x8]; 3007 u8 wol_mode[0x8]; 3008}; 3009 3010struct mlx5_ifc_icmd_set_wol_rol_in_bits { 3011 u8 reserved_0[0x40]; 3012 3013 u8 rol_mode_valid[0x1]; 3014 u8 wol_mode_valid[0x1]; 3015 u8 reserved_1[0xe]; 3016 u8 rol_mode[0x8]; 3017 u8 wol_mode[0x8]; 3018 3019 u8 reserved_2[0x7a0]; 3020}; 3021 3022struct mlx5_ifc_icmd_set_virtual_mac_in_bits { 3023 u8 virtual_mac_en[0x1]; 3024 u8 mac_aux_v[0x1]; 3025 u8 reserved_0[0x1e]; 3026 3027 u8 reserved_1[0x40]; 3028 3029 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3030 3031 u8 reserved_2[0x760]; 3032}; 3033 3034struct mlx5_ifc_icmd_query_virtual_mac_out_bits { 3035 u8 virtual_mac_en[0x1]; 3036 u8 mac_aux_v[0x1]; 3037 u8 reserved_0[0x1e]; 3038 3039 struct mlx5_ifc_mac_address_layout_bits permanent_mac; 3040 3041 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3042 3043 u8 reserved_1[0x760]; 3044}; 3045 3046struct mlx5_ifc_icmd_query_fw_info_out_bits { 3047 struct mlx5_ifc_fw_version_bits fw_version; 3048 3049 u8 reserved_0[0x10]; 3050 u8 hash_signature[0x10]; 3051 3052 u8 psid[16][0x8]; 3053 3054 u8 reserved_1[0x6e0]; 3055}; 3056 3057struct mlx5_ifc_icmd_query_cap_in_bits { 3058 u8 reserved_0[0x10]; 3059 u8 capability_group[0x10]; 3060}; 3061 3062struct mlx5_ifc_icmd_query_cap_general_bits { 3063 u8 nv_access[0x1]; 3064 u8 fw_info_psid[0x1]; 3065 u8 reserved_0[0x1e]; 3066 3067 u8 reserved_1[0x16]; 3068 u8 rol_s[0x1]; 3069 u8 rol_g[0x1]; 3070 u8 reserved_2[0x1]; 3071 u8 wol_s[0x1]; 3072 u8 wol_g[0x1]; 3073 u8 wol_a[0x1]; 3074 u8 wol_b[0x1]; 3075 u8 wol_m[0x1]; 3076 u8 wol_u[0x1]; 3077 u8 wol_p[0x1]; 3078}; 3079 3080struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits { 3081 u8 status[0x8]; 3082 u8 reserved_0[0x18]; 3083 3084 u8 reserved_1[0x7e0]; 3085}; 3086 3087struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits { 3088 u8 status[0x8]; 3089 u8 reserved_0[0x18]; 3090 3091 u8 reserved_1[0x7e0]; 3092}; 3093 3094struct mlx5_ifc_icmd_ocbb_init_in_bits { 3095 u8 address_hi[0x20]; 3096 3097 u8 address_lo[0x20]; 3098 3099 u8 reserved_0[0x7c0]; 3100}; 3101 3102struct mlx5_ifc_icmd_init_ocsd_in_bits { 3103 u8 reserved_0[0x20]; 3104 3105 u8 address_hi[0x20]; 3106 3107 u8 address_lo[0x20]; 3108 3109 u8 reserved_1[0x7a0]; 3110}; 3111 3112struct mlx5_ifc_icmd_access_reg_out_bits { 3113 u8 reserved_0[0x11]; 3114 u8 status[0x7]; 3115 u8 reserved_1[0x8]; 3116 3117 u8 register_id[0x10]; 3118 u8 reserved_2[0x10]; 3119 3120 u8 reserved_3[0x40]; 3121 3122 u8 reserved_4[0x5]; 3123 u8 len[0xb]; 3124 u8 reserved_5[0x10]; 3125 3126 u8 register_data[0][0x20]; 3127}; 3128 3129enum { 3130 MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY = 0x1, 3131 MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE = 0x2, 3132}; 3133 3134struct mlx5_ifc_icmd_access_reg_in_bits { 3135 u8 constant_1[0x5]; 3136 u8 constant_2[0xb]; 3137 u8 reserved_0[0x10]; 3138 3139 u8 register_id[0x10]; 3140 u8 reserved_1[0x1]; 3141 u8 method[0x7]; 3142 u8 constant_3[0x8]; 3143 3144 u8 reserved_2[0x40]; 3145 3146 u8 constant_4[0x5]; 3147 u8 len[0xb]; 3148 u8 reserved_3[0x10]; 3149 3150 u8 register_data[0][0x20]; 3151}; 3152 3153enum { 3154 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3155 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3156}; 3157 3158struct mlx5_ifc_teardown_hca_out_bits { 3159 u8 status[0x8]; 3160 u8 reserved_0[0x18]; 3161 3162 u8 syndrome[0x20]; 3163 3164 u8 reserved_1[0x3f]; 3165 3166 u8 force_state[0x1]; 3167}; 3168 3169enum { 3170 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3171 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3172}; 3173 3174struct mlx5_ifc_teardown_hca_in_bits { 3175 u8 opcode[0x10]; 3176 u8 reserved_0[0x10]; 3177 3178 u8 reserved_1[0x10]; 3179 u8 op_mod[0x10]; 3180 3181 u8 reserved_2[0x10]; 3182 u8 profile[0x10]; 3183 3184 u8 reserved_3[0x20]; 3185}; 3186 3187struct mlx5_ifc_set_delay_drop_params_out_bits { 3188 u8 status[0x8]; 3189 u8 reserved_at_8[0x18]; 3190 3191 u8 syndrome[0x20]; 3192 3193 u8 reserved_at_40[0x40]; 3194}; 3195 3196struct mlx5_ifc_set_delay_drop_params_in_bits { 3197 u8 opcode[0x10]; 3198 u8 reserved_at_10[0x10]; 3199 3200 u8 reserved_at_20[0x10]; 3201 u8 op_mod[0x10]; 3202 3203 u8 reserved_at_40[0x20]; 3204 3205 u8 reserved_at_60[0x10]; 3206 u8 delay_drop_timeout[0x10]; 3207}; 3208 3209struct mlx5_ifc_query_delay_drop_params_out_bits { 3210 u8 status[0x8]; 3211 u8 reserved_at_8[0x18]; 3212 3213 u8 syndrome[0x20]; 3214 3215 u8 reserved_at_40[0x20]; 3216 3217 u8 reserved_at_60[0x10]; 3218 u8 delay_drop_timeout[0x10]; 3219}; 3220 3221struct mlx5_ifc_query_delay_drop_params_in_bits { 3222 u8 opcode[0x10]; 3223 u8 reserved_at_10[0x10]; 3224 3225 u8 reserved_at_20[0x10]; 3226 u8 op_mod[0x10]; 3227 3228 u8 reserved_at_40[0x40]; 3229}; 3230 3231struct mlx5_ifc_suspend_qp_out_bits { 3232 u8 status[0x8]; 3233 u8 reserved_0[0x18]; 3234 3235 u8 syndrome[0x20]; 3236 3237 u8 reserved_1[0x40]; 3238}; 3239 3240struct mlx5_ifc_suspend_qp_in_bits { 3241 u8 opcode[0x10]; 3242 u8 reserved_0[0x10]; 3243 3244 u8 reserved_1[0x10]; 3245 u8 op_mod[0x10]; 3246 3247 u8 reserved_2[0x8]; 3248 u8 qpn[0x18]; 3249 3250 u8 reserved_3[0x20]; 3251}; 3252 3253struct mlx5_ifc_sqerr2rts_qp_out_bits { 3254 u8 status[0x8]; 3255 u8 reserved_0[0x18]; 3256 3257 u8 syndrome[0x20]; 3258 3259 u8 reserved_1[0x40]; 3260}; 3261 3262struct mlx5_ifc_sqerr2rts_qp_in_bits { 3263 u8 opcode[0x10]; 3264 u8 reserved_0[0x10]; 3265 3266 u8 reserved_1[0x10]; 3267 u8 op_mod[0x10]; 3268 3269 u8 reserved_2[0x8]; 3270 u8 qpn[0x18]; 3271 3272 u8 reserved_3[0x20]; 3273 3274 u8 opt_param_mask[0x20]; 3275 3276 u8 reserved_4[0x20]; 3277 3278 struct mlx5_ifc_qpc_bits qpc; 3279 3280 u8 reserved_5[0x80]; 3281}; 3282 3283struct mlx5_ifc_sqd2rts_qp_out_bits { 3284 u8 status[0x8]; 3285 u8 reserved_0[0x18]; 3286 3287 u8 syndrome[0x20]; 3288 3289 u8 reserved_1[0x40]; 3290}; 3291 3292struct mlx5_ifc_sqd2rts_qp_in_bits { 3293 u8 opcode[0x10]; 3294 u8 reserved_0[0x10]; 3295 3296 u8 reserved_1[0x10]; 3297 u8 op_mod[0x10]; 3298 3299 u8 reserved_2[0x8]; 3300 u8 qpn[0x18]; 3301 3302 u8 reserved_3[0x20]; 3303 3304 u8 opt_param_mask[0x20]; 3305 3306 u8 reserved_4[0x20]; 3307 3308 struct mlx5_ifc_qpc_bits qpc; 3309 3310 u8 reserved_5[0x80]; 3311}; 3312 3313struct mlx5_ifc_set_wol_rol_out_bits { 3314 u8 status[0x8]; 3315 u8 reserved_0[0x18]; 3316 3317 u8 syndrome[0x20]; 3318 3319 u8 reserved_1[0x40]; 3320}; 3321 3322struct mlx5_ifc_set_wol_rol_in_bits { 3323 u8 opcode[0x10]; 3324 u8 reserved_0[0x10]; 3325 3326 u8 reserved_1[0x10]; 3327 u8 op_mod[0x10]; 3328 3329 u8 rol_mode_valid[0x1]; 3330 u8 wol_mode_valid[0x1]; 3331 u8 reserved_2[0xe]; 3332 u8 rol_mode[0x8]; 3333 u8 wol_mode[0x8]; 3334 3335 u8 reserved_3[0x20]; 3336}; 3337 3338struct mlx5_ifc_set_roce_address_out_bits { 3339 u8 status[0x8]; 3340 u8 reserved_0[0x18]; 3341 3342 u8 syndrome[0x20]; 3343 3344 u8 reserved_1[0x40]; 3345}; 3346 3347struct mlx5_ifc_set_roce_address_in_bits { 3348 u8 opcode[0x10]; 3349 u8 reserved_0[0x10]; 3350 3351 u8 reserved_1[0x10]; 3352 u8 op_mod[0x10]; 3353 3354 u8 roce_address_index[0x10]; 3355 u8 reserved_2[0x10]; 3356 3357 u8 reserved_3[0x20]; 3358 3359 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3360}; 3361 3362struct mlx5_ifc_set_rdb_out_bits { 3363 u8 status[0x8]; 3364 u8 reserved_0[0x18]; 3365 3366 u8 syndrome[0x20]; 3367 3368 u8 reserved_1[0x40]; 3369}; 3370 3371struct mlx5_ifc_set_rdb_in_bits { 3372 u8 opcode[0x10]; 3373 u8 reserved_0[0x10]; 3374 3375 u8 reserved_1[0x10]; 3376 u8 op_mod[0x10]; 3377 3378 u8 reserved_2[0x8]; 3379 u8 qpn[0x18]; 3380 3381 u8 reserved_3[0x18]; 3382 u8 rdb_list_size[0x8]; 3383 3384 struct mlx5_ifc_rdbc_bits rdb_context[0]; 3385}; 3386 3387struct mlx5_ifc_set_mad_demux_out_bits { 3388 u8 status[0x8]; 3389 u8 reserved_0[0x18]; 3390 3391 u8 syndrome[0x20]; 3392 3393 u8 reserved_1[0x40]; 3394}; 3395 3396enum { 3397 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3398 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3399}; 3400 3401struct mlx5_ifc_set_mad_demux_in_bits { 3402 u8 opcode[0x10]; 3403 u8 reserved_0[0x10]; 3404 3405 u8 reserved_1[0x10]; 3406 u8 op_mod[0x10]; 3407 3408 u8 reserved_2[0x20]; 3409 3410 u8 reserved_3[0x6]; 3411 u8 demux_mode[0x2]; 3412 u8 reserved_4[0x18]; 3413}; 3414 3415struct mlx5_ifc_set_l2_table_entry_out_bits { 3416 u8 status[0x8]; 3417 u8 reserved_0[0x18]; 3418 3419 u8 syndrome[0x20]; 3420 3421 u8 reserved_1[0x40]; 3422}; 3423 3424struct mlx5_ifc_set_l2_table_entry_in_bits { 3425 u8 opcode[0x10]; 3426 u8 reserved_0[0x10]; 3427 3428 u8 reserved_1[0x10]; 3429 u8 op_mod[0x10]; 3430 3431 u8 reserved_2[0x60]; 3432 3433 u8 reserved_3[0x8]; 3434 u8 table_index[0x18]; 3435 3436 u8 reserved_4[0x20]; 3437 3438 u8 reserved_5[0x13]; 3439 u8 vlan_valid[0x1]; 3440 u8 vlan[0xc]; 3441 3442 struct mlx5_ifc_mac_address_layout_bits mac_address; 3443 3444 u8 reserved_6[0xc0]; 3445}; 3446 3447struct mlx5_ifc_set_issi_out_bits { 3448 u8 status[0x8]; 3449 u8 reserved_0[0x18]; 3450 3451 u8 syndrome[0x20]; 3452 3453 u8 reserved_1[0x40]; 3454}; 3455 3456struct mlx5_ifc_set_issi_in_bits { 3457 u8 opcode[0x10]; 3458 u8 reserved_0[0x10]; 3459 3460 u8 reserved_1[0x10]; 3461 u8 op_mod[0x10]; 3462 3463 u8 reserved_2[0x10]; 3464 u8 current_issi[0x10]; 3465 3466 u8 reserved_3[0x20]; 3467}; 3468 3469struct mlx5_ifc_set_hca_cap_out_bits { 3470 u8 status[0x8]; 3471 u8 reserved_0[0x18]; 3472 3473 u8 syndrome[0x20]; 3474 3475 u8 reserved_1[0x40]; 3476}; 3477 3478struct mlx5_ifc_set_hca_cap_in_bits { 3479 u8 opcode[0x10]; 3480 u8 reserved_0[0x10]; 3481 3482 u8 reserved_1[0x10]; 3483 u8 op_mod[0x10]; 3484 3485 u8 reserved_2[0x40]; 3486 3487 union mlx5_ifc_hca_cap_union_bits capability; 3488}; 3489 3490enum { 3491 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3492 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3493 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3494 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3495}; 3496 3497struct mlx5_ifc_set_flow_table_root_out_bits { 3498 u8 status[0x8]; 3499 u8 reserved_0[0x18]; 3500 3501 u8 syndrome[0x20]; 3502 3503 u8 reserved_1[0x40]; 3504}; 3505 3506struct mlx5_ifc_set_flow_table_root_in_bits { 3507 u8 opcode[0x10]; 3508 u8 reserved_0[0x10]; 3509 3510 u8 reserved_1[0x10]; 3511 u8 op_mod[0x10]; 3512 3513 u8 other_vport[0x1]; 3514 u8 reserved_2[0xf]; 3515 u8 vport_number[0x10]; 3516 3517 u8 reserved_3[0x20]; 3518 3519 u8 table_type[0x8]; 3520 u8 reserved_4[0x18]; 3521 3522 u8 reserved_5[0x8]; 3523 u8 table_id[0x18]; 3524 3525 u8 reserved_6[0x8]; 3526 u8 underlay_qpn[0x18]; 3527 3528 u8 reserved_7[0x120]; 3529}; 3530 3531struct mlx5_ifc_set_fte_out_bits { 3532 u8 status[0x8]; 3533 u8 reserved_0[0x18]; 3534 3535 u8 syndrome[0x20]; 3536 3537 u8 reserved_1[0x40]; 3538}; 3539 3540struct mlx5_ifc_set_fte_in_bits { 3541 u8 opcode[0x10]; 3542 u8 reserved_0[0x10]; 3543 3544 u8 reserved_1[0x10]; 3545 u8 op_mod[0x10]; 3546 3547 u8 other_vport[0x1]; 3548 u8 reserved_2[0xf]; 3549 u8 vport_number[0x10]; 3550 3551 u8 reserved_3[0x20]; 3552 3553 u8 table_type[0x8]; 3554 u8 reserved_4[0x18]; 3555 3556 u8 reserved_5[0x8]; 3557 u8 table_id[0x18]; 3558 3559 u8 reserved_6[0x18]; 3560 u8 modify_enable_mask[0x8]; 3561 3562 u8 reserved_7[0x20]; 3563 3564 u8 flow_index[0x20]; 3565 3566 u8 reserved_8[0xe0]; 3567 3568 struct mlx5_ifc_flow_context_bits flow_context; 3569}; 3570 3571struct mlx5_ifc_set_driver_version_out_bits { 3572 u8 status[0x8]; 3573 u8 reserved_0[0x18]; 3574 3575 u8 syndrome[0x20]; 3576 3577 u8 reserved_1[0x40]; 3578}; 3579 3580struct mlx5_ifc_set_driver_version_in_bits { 3581 u8 opcode[0x10]; 3582 u8 reserved_0[0x10]; 3583 3584 u8 reserved_1[0x10]; 3585 u8 op_mod[0x10]; 3586 3587 u8 reserved_2[0x40]; 3588 3589 u8 driver_version[64][0x8]; 3590}; 3591 3592struct mlx5_ifc_set_dc_cnak_trace_out_bits { 3593 u8 status[0x8]; 3594 u8 reserved_0[0x18]; 3595 3596 u8 syndrome[0x20]; 3597 3598 u8 reserved_1[0x40]; 3599}; 3600 3601struct mlx5_ifc_set_dc_cnak_trace_in_bits { 3602 u8 opcode[0x10]; 3603 u8 reserved_0[0x10]; 3604 3605 u8 reserved_1[0x10]; 3606 u8 op_mod[0x10]; 3607 3608 u8 enable[0x1]; 3609 u8 reserved_2[0x1f]; 3610 3611 u8 reserved_3[0x160]; 3612 3613 struct mlx5_ifc_cmd_pas_bits pas; 3614}; 3615 3616struct mlx5_ifc_set_burst_size_out_bits { 3617 u8 status[0x8]; 3618 u8 reserved_0[0x18]; 3619 3620 u8 syndrome[0x20]; 3621 3622 u8 reserved_1[0x40]; 3623}; 3624 3625struct mlx5_ifc_set_burst_size_in_bits { 3626 u8 opcode[0x10]; 3627 u8 reserved_0[0x10]; 3628 3629 u8 reserved_1[0x10]; 3630 u8 op_mod[0x10]; 3631 3632 u8 reserved_2[0x20]; 3633 3634 u8 reserved_3[0x9]; 3635 u8 device_burst_size[0x17]; 3636}; 3637 3638struct mlx5_ifc_rts2rts_qp_out_bits { 3639 u8 status[0x8]; 3640 u8 reserved_0[0x18]; 3641 3642 u8 syndrome[0x20]; 3643 3644 u8 reserved_1[0x40]; 3645}; 3646 3647struct mlx5_ifc_rts2rts_qp_in_bits { 3648 u8 opcode[0x10]; 3649 u8 reserved_0[0x10]; 3650 3651 u8 reserved_1[0x10]; 3652 u8 op_mod[0x10]; 3653 3654 u8 reserved_2[0x8]; 3655 u8 qpn[0x18]; 3656 3657 u8 reserved_3[0x20]; 3658 3659 u8 opt_param_mask[0x20]; 3660 3661 u8 reserved_4[0x20]; 3662 3663 struct mlx5_ifc_qpc_bits qpc; 3664 3665 u8 reserved_5[0x80]; 3666}; 3667 3668struct mlx5_ifc_rtr2rts_qp_out_bits { 3669 u8 status[0x8]; 3670 u8 reserved_0[0x18]; 3671 3672 u8 syndrome[0x20]; 3673 3674 u8 reserved_1[0x40]; 3675}; 3676 3677struct mlx5_ifc_rtr2rts_qp_in_bits { 3678 u8 opcode[0x10]; 3679 u8 reserved_0[0x10]; 3680 3681 u8 reserved_1[0x10]; 3682 u8 op_mod[0x10]; 3683 3684 u8 reserved_2[0x8]; 3685 u8 qpn[0x18]; 3686 3687 u8 reserved_3[0x20]; 3688 3689 u8 opt_param_mask[0x20]; 3690 3691 u8 reserved_4[0x20]; 3692 3693 struct mlx5_ifc_qpc_bits qpc; 3694 3695 u8 reserved_5[0x80]; 3696}; 3697 3698struct mlx5_ifc_rst2init_qp_out_bits { 3699 u8 status[0x8]; 3700 u8 reserved_0[0x18]; 3701 3702 u8 syndrome[0x20]; 3703 3704 u8 reserved_1[0x40]; 3705}; 3706 3707struct mlx5_ifc_rst2init_qp_in_bits { 3708 u8 opcode[0x10]; 3709 u8 reserved_0[0x10]; 3710 3711 u8 reserved_1[0x10]; 3712 u8 op_mod[0x10]; 3713 3714 u8 reserved_2[0x8]; 3715 u8 qpn[0x18]; 3716 3717 u8 reserved_3[0x20]; 3718 3719 u8 opt_param_mask[0x20]; 3720 3721 u8 reserved_4[0x20]; 3722 3723 struct mlx5_ifc_qpc_bits qpc; 3724 3725 u8 reserved_5[0x80]; 3726}; 3727 3728struct mlx5_ifc_resume_qp_out_bits { 3729 u8 status[0x8]; 3730 u8 reserved_0[0x18]; 3731 3732 u8 syndrome[0x20]; 3733 3734 u8 reserved_1[0x40]; 3735}; 3736 3737struct mlx5_ifc_resume_qp_in_bits { 3738 u8 opcode[0x10]; 3739 u8 reserved_0[0x10]; 3740 3741 u8 reserved_1[0x10]; 3742 u8 op_mod[0x10]; 3743 3744 u8 reserved_2[0x8]; 3745 u8 qpn[0x18]; 3746 3747 u8 reserved_3[0x20]; 3748}; 3749 3750struct mlx5_ifc_query_xrc_srq_out_bits { 3751 u8 status[0x8]; 3752 u8 reserved_0[0x18]; 3753 3754 u8 syndrome[0x20]; 3755 3756 u8 reserved_1[0x40]; 3757 3758 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3759 3760 u8 reserved_2[0x600]; 3761 3762 u8 pas[0][0x40]; 3763}; 3764 3765struct mlx5_ifc_query_xrc_srq_in_bits { 3766 u8 opcode[0x10]; 3767 u8 reserved_0[0x10]; 3768 3769 u8 reserved_1[0x10]; 3770 u8 op_mod[0x10]; 3771 3772 u8 reserved_2[0x8]; 3773 u8 xrc_srqn[0x18]; 3774 3775 u8 reserved_3[0x20]; 3776}; 3777 3778struct mlx5_ifc_query_wol_rol_out_bits { 3779 u8 status[0x8]; 3780 u8 reserved_0[0x18]; 3781 3782 u8 syndrome[0x20]; 3783 3784 u8 reserved_1[0x10]; 3785 u8 rol_mode[0x8]; 3786 u8 wol_mode[0x8]; 3787 3788 u8 reserved_2[0x20]; 3789}; 3790 3791struct mlx5_ifc_query_wol_rol_in_bits { 3792 u8 opcode[0x10]; 3793 u8 reserved_0[0x10]; 3794 3795 u8 reserved_1[0x10]; 3796 u8 op_mod[0x10]; 3797 3798 u8 reserved_2[0x40]; 3799}; 3800 3801enum { 3802 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3803 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3804}; 3805 3806struct mlx5_ifc_query_vport_state_out_bits { 3807 u8 status[0x8]; 3808 u8 reserved_0[0x18]; 3809 3810 u8 syndrome[0x20]; 3811 3812 u8 reserved_1[0x20]; 3813 3814 u8 reserved_2[0x18]; 3815 u8 admin_state[0x4]; 3816 u8 state[0x4]; 3817}; 3818 3819enum { 3820 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 3821 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 3822 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 3823}; 3824 3825struct mlx5_ifc_query_vport_state_in_bits { 3826 u8 opcode[0x10]; 3827 u8 reserved_0[0x10]; 3828 3829 u8 reserved_1[0x10]; 3830 u8 op_mod[0x10]; 3831 3832 u8 other_vport[0x1]; 3833 u8 reserved_2[0xf]; 3834 u8 vport_number[0x10]; 3835 3836 u8 reserved_3[0x20]; 3837}; 3838 3839struct mlx5_ifc_query_vport_counter_out_bits { 3840 u8 status[0x8]; 3841 u8 reserved_0[0x18]; 3842 3843 u8 syndrome[0x20]; 3844 3845 u8 reserved_1[0x40]; 3846 3847 struct mlx5_ifc_traffic_counter_bits received_errors; 3848 3849 struct mlx5_ifc_traffic_counter_bits transmit_errors; 3850 3851 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 3852 3853 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 3854 3855 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 3856 3857 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 3858 3859 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 3860 3861 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 3862 3863 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 3864 3865 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 3866 3867 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 3868 3869 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 3870 3871 u8 reserved_2[0xa00]; 3872}; 3873 3874enum { 3875 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 3876}; 3877 3878struct mlx5_ifc_query_vport_counter_in_bits { 3879 u8 opcode[0x10]; 3880 u8 reserved_0[0x10]; 3881 3882 u8 reserved_1[0x10]; 3883 u8 op_mod[0x10]; 3884 3885 u8 other_vport[0x1]; 3886 u8 reserved_2[0xb]; 3887 u8 port_num[0x4]; 3888 u8 vport_number[0x10]; 3889 3890 u8 reserved_3[0x60]; 3891 3892 u8 clear[0x1]; 3893 u8 reserved_4[0x1f]; 3894 3895 u8 reserved_5[0x20]; 3896}; 3897 3898struct mlx5_ifc_query_tis_out_bits { 3899 u8 status[0x8]; 3900 u8 reserved_0[0x18]; 3901 3902 u8 syndrome[0x20]; 3903 3904 u8 reserved_1[0x40]; 3905 3906 struct mlx5_ifc_tisc_bits tis_context; 3907}; 3908 3909struct mlx5_ifc_query_tis_in_bits { 3910 u8 opcode[0x10]; 3911 u8 reserved_0[0x10]; 3912 3913 u8 reserved_1[0x10]; 3914 u8 op_mod[0x10]; 3915 3916 u8 reserved_2[0x8]; 3917 u8 tisn[0x18]; 3918 3919 u8 reserved_3[0x20]; 3920}; 3921 3922struct mlx5_ifc_query_tir_out_bits { 3923 u8 status[0x8]; 3924 u8 reserved_0[0x18]; 3925 3926 u8 syndrome[0x20]; 3927 3928 u8 reserved_1[0xc0]; 3929 3930 struct mlx5_ifc_tirc_bits tir_context; 3931}; 3932 3933struct mlx5_ifc_query_tir_in_bits { 3934 u8 opcode[0x10]; 3935 u8 reserved_0[0x10]; 3936 3937 u8 reserved_1[0x10]; 3938 u8 op_mod[0x10]; 3939 3940 u8 reserved_2[0x8]; 3941 u8 tirn[0x18]; 3942 3943 u8 reserved_3[0x20]; 3944}; 3945 3946struct mlx5_ifc_query_srq_out_bits { 3947 u8 status[0x8]; 3948 u8 reserved_0[0x18]; 3949 3950 u8 syndrome[0x20]; 3951 3952 u8 reserved_1[0x40]; 3953 3954 struct mlx5_ifc_srqc_bits srq_context_entry; 3955 3956 u8 reserved_2[0x600]; 3957 3958 u8 pas[0][0x40]; 3959}; 3960 3961struct mlx5_ifc_query_srq_in_bits { 3962 u8 opcode[0x10]; 3963 u8 reserved_0[0x10]; 3964 3965 u8 reserved_1[0x10]; 3966 u8 op_mod[0x10]; 3967 3968 u8 reserved_2[0x8]; 3969 u8 srqn[0x18]; 3970 3971 u8 reserved_3[0x20]; 3972}; 3973 3974struct mlx5_ifc_query_sq_out_bits { 3975 u8 status[0x8]; 3976 u8 reserved_0[0x18]; 3977 3978 u8 syndrome[0x20]; 3979 3980 u8 reserved_1[0xc0]; 3981 3982 struct mlx5_ifc_sqc_bits sq_context; 3983}; 3984 3985struct mlx5_ifc_query_sq_in_bits { 3986 u8 opcode[0x10]; 3987 u8 reserved_0[0x10]; 3988 3989 u8 reserved_1[0x10]; 3990 u8 op_mod[0x10]; 3991 3992 u8 reserved_2[0x8]; 3993 u8 sqn[0x18]; 3994 3995 u8 reserved_3[0x20]; 3996}; 3997 3998struct mlx5_ifc_query_special_contexts_out_bits { 3999 u8 status[0x8]; 4000 u8 reserved_0[0x18]; 4001 4002 u8 syndrome[0x20]; 4003 4004 u8 dump_fill_mkey[0x20]; 4005 4006 u8 resd_lkey[0x20]; 4007}; 4008 4009struct mlx5_ifc_query_special_contexts_in_bits { 4010 u8 opcode[0x10]; 4011 u8 reserved_0[0x10]; 4012 4013 u8 reserved_1[0x10]; 4014 u8 op_mod[0x10]; 4015 4016 u8 reserved_2[0x40]; 4017}; 4018 4019struct mlx5_ifc_query_scheduling_element_out_bits { 4020 u8 status[0x8]; 4021 u8 reserved_at_8[0x18]; 4022 4023 u8 syndrome[0x20]; 4024 4025 u8 reserved_at_40[0xc0]; 4026 4027 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4028 4029 u8 reserved_at_300[0x100]; 4030}; 4031 4032enum { 4033 MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2, 4034}; 4035 4036struct mlx5_ifc_query_scheduling_element_in_bits { 4037 u8 opcode[0x10]; 4038 u8 reserved_at_10[0x10]; 4039 4040 u8 reserved_at_20[0x10]; 4041 u8 op_mod[0x10]; 4042 4043 u8 scheduling_hierarchy[0x8]; 4044 u8 reserved_at_48[0x18]; 4045 4046 u8 scheduling_element_id[0x20]; 4047 4048 u8 reserved_at_80[0x180]; 4049}; 4050 4051struct mlx5_ifc_query_rqt_out_bits { 4052 u8 status[0x8]; 4053 u8 reserved_0[0x18]; 4054 4055 u8 syndrome[0x20]; 4056 4057 u8 reserved_1[0xc0]; 4058 4059 struct mlx5_ifc_rqtc_bits rqt_context; 4060}; 4061 4062struct mlx5_ifc_query_rqt_in_bits { 4063 u8 opcode[0x10]; 4064 u8 reserved_0[0x10]; 4065 4066 u8 reserved_1[0x10]; 4067 u8 op_mod[0x10]; 4068 4069 u8 reserved_2[0x8]; 4070 u8 rqtn[0x18]; 4071 4072 u8 reserved_3[0x20]; 4073}; 4074 4075struct mlx5_ifc_query_rq_out_bits { 4076 u8 status[0x8]; 4077 u8 reserved_0[0x18]; 4078 4079 u8 syndrome[0x20]; 4080 4081 u8 reserved_1[0xc0]; 4082 4083 struct mlx5_ifc_rqc_bits rq_context; 4084}; 4085 4086struct mlx5_ifc_query_rq_in_bits { 4087 u8 opcode[0x10]; 4088 u8 reserved_0[0x10]; 4089 4090 u8 reserved_1[0x10]; 4091 u8 op_mod[0x10]; 4092 4093 u8 reserved_2[0x8]; 4094 u8 rqn[0x18]; 4095 4096 u8 reserved_3[0x20]; 4097}; 4098 4099struct mlx5_ifc_query_roce_address_out_bits { 4100 u8 status[0x8]; 4101 u8 reserved_0[0x18]; 4102 4103 u8 syndrome[0x20]; 4104 4105 u8 reserved_1[0x40]; 4106 4107 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4108}; 4109 4110struct mlx5_ifc_query_roce_address_in_bits { 4111 u8 opcode[0x10]; 4112 u8 reserved_0[0x10]; 4113 4114 u8 reserved_1[0x10]; 4115 u8 op_mod[0x10]; 4116 4117 u8 roce_address_index[0x10]; 4118 u8 reserved_2[0x10]; 4119 4120 u8 reserved_3[0x20]; 4121}; 4122 4123struct mlx5_ifc_query_rmp_out_bits { 4124 u8 status[0x8]; 4125 u8 reserved_0[0x18]; 4126 4127 u8 syndrome[0x20]; 4128 4129 u8 reserved_1[0xc0]; 4130 4131 struct mlx5_ifc_rmpc_bits rmp_context; 4132}; 4133 4134struct mlx5_ifc_query_rmp_in_bits { 4135 u8 opcode[0x10]; 4136 u8 reserved_0[0x10]; 4137 4138 u8 reserved_1[0x10]; 4139 u8 op_mod[0x10]; 4140 4141 u8 reserved_2[0x8]; 4142 u8 rmpn[0x18]; 4143 4144 u8 reserved_3[0x20]; 4145}; 4146 4147struct mlx5_ifc_query_rdb_out_bits { 4148 u8 status[0x8]; 4149 u8 reserved_0[0x18]; 4150 4151 u8 syndrome[0x20]; 4152 4153 u8 reserved_1[0x20]; 4154 4155 u8 reserved_2[0x18]; 4156 u8 rdb_list_size[0x8]; 4157 4158 struct mlx5_ifc_rdbc_bits rdb_context[0]; 4159}; 4160 4161struct mlx5_ifc_query_rdb_in_bits { 4162 u8 opcode[0x10]; 4163 u8 reserved_0[0x10]; 4164 4165 u8 reserved_1[0x10]; 4166 u8 op_mod[0x10]; 4167 4168 u8 reserved_2[0x8]; 4169 u8 qpn[0x18]; 4170 4171 u8 reserved_3[0x20]; 4172}; 4173 4174struct mlx5_ifc_query_qp_out_bits { 4175 u8 status[0x8]; 4176 u8 reserved_0[0x18]; 4177 4178 u8 syndrome[0x20]; 4179 4180 u8 reserved_1[0x40]; 4181 4182 u8 opt_param_mask[0x20]; 4183 4184 u8 reserved_2[0x20]; 4185 4186 struct mlx5_ifc_qpc_bits qpc; 4187 4188 u8 reserved_3[0x80]; 4189 4190 u8 pas[0][0x40]; 4191}; 4192 4193struct mlx5_ifc_query_qp_in_bits { 4194 u8 opcode[0x10]; 4195 u8 reserved_0[0x10]; 4196 4197 u8 reserved_1[0x10]; 4198 u8 op_mod[0x10]; 4199 4200 u8 reserved_2[0x8]; 4201 u8 qpn[0x18]; 4202 4203 u8 reserved_3[0x20]; 4204}; 4205 4206struct mlx5_ifc_query_q_counter_out_bits { 4207 u8 status[0x8]; 4208 u8 reserved_0[0x18]; 4209 4210 u8 syndrome[0x20]; 4211 4212 u8 reserved_1[0x40]; 4213 4214 u8 rx_write_requests[0x20]; 4215 4216 u8 reserved_2[0x20]; 4217 4218 u8 rx_read_requests[0x20]; 4219 4220 u8 reserved_3[0x20]; 4221 4222 u8 rx_atomic_requests[0x20]; 4223 4224 u8 reserved_4[0x20]; 4225 4226 u8 rx_dct_connect[0x20]; 4227 4228 u8 reserved_5[0x20]; 4229 4230 u8 out_of_buffer[0x20]; 4231 4232 u8 reserved_7[0x20]; 4233 4234 u8 out_of_sequence[0x20]; 4235 4236 u8 reserved_8[0x20]; 4237 4238 u8 duplicate_request[0x20]; 4239 4240 u8 reserved_9[0x20]; 4241 4242 u8 rnr_nak_retry_err[0x20]; 4243 4244 u8 reserved_10[0x20]; 4245 4246 u8 packet_seq_err[0x20]; 4247 4248 u8 reserved_11[0x20]; 4249 4250 u8 implied_nak_seq_err[0x20]; 4251 4252 u8 reserved_12[0x20]; 4253 4254 u8 local_ack_timeout_err[0x20]; 4255 4256 u8 reserved_13[0x20]; 4257 4258 u8 resp_rnr_nak[0x20]; 4259 4260 u8 reserved_14[0x20]; 4261 4262 u8 req_rnr_retries_exceeded[0x20]; 4263 4264 u8 reserved_15[0x460]; 4265}; 4266 4267struct mlx5_ifc_query_q_counter_in_bits { 4268 u8 opcode[0x10]; 4269 u8 reserved_0[0x10]; 4270 4271 u8 reserved_1[0x10]; 4272 u8 op_mod[0x10]; 4273 4274 u8 reserved_2[0x80]; 4275 4276 u8 clear[0x1]; 4277 u8 reserved_3[0x1f]; 4278 4279 u8 reserved_4[0x18]; 4280 u8 counter_set_id[0x8]; 4281}; 4282 4283struct mlx5_ifc_query_pages_out_bits { 4284 u8 status[0x8]; 4285 u8 reserved_0[0x18]; 4286 4287 u8 syndrome[0x20]; 4288 4289 u8 reserved_1[0x10]; 4290 u8 function_id[0x10]; 4291 4292 u8 num_pages[0x20]; 4293}; 4294 4295enum { 4296 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4297 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4298 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4299}; 4300 4301struct mlx5_ifc_query_pages_in_bits { 4302 u8 opcode[0x10]; 4303 u8 reserved_0[0x10]; 4304 4305 u8 reserved_1[0x10]; 4306 u8 op_mod[0x10]; 4307 4308 u8 reserved_2[0x10]; 4309 u8 function_id[0x10]; 4310 4311 u8 reserved_3[0x20]; 4312}; 4313 4314struct mlx5_ifc_query_nic_vport_context_out_bits { 4315 u8 status[0x8]; 4316 u8 reserved_0[0x18]; 4317 4318 u8 syndrome[0x20]; 4319 4320 u8 reserved_1[0x40]; 4321 4322 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4323}; 4324 4325struct mlx5_ifc_query_nic_vport_context_in_bits { 4326 u8 opcode[0x10]; 4327 u8 reserved_0[0x10]; 4328 4329 u8 reserved_1[0x10]; 4330 u8 op_mod[0x10]; 4331 4332 u8 other_vport[0x1]; 4333 u8 reserved_2[0xf]; 4334 u8 vport_number[0x10]; 4335 4336 u8 reserved_3[0x5]; 4337 u8 allowed_list_type[0x3]; 4338 u8 reserved_4[0x18]; 4339}; 4340 4341struct mlx5_ifc_query_mkey_out_bits { 4342 u8 status[0x8]; 4343 u8 reserved_0[0x18]; 4344 4345 u8 syndrome[0x20]; 4346 4347 u8 reserved_1[0x40]; 4348 4349 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4350 4351 u8 reserved_2[0x600]; 4352 4353 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4354 4355 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4356}; 4357 4358struct mlx5_ifc_query_mkey_in_bits { 4359 u8 opcode[0x10]; 4360 u8 reserved_0[0x10]; 4361 4362 u8 reserved_1[0x10]; 4363 u8 op_mod[0x10]; 4364 4365 u8 reserved_2[0x8]; 4366 u8 mkey_index[0x18]; 4367 4368 u8 pg_access[0x1]; 4369 u8 reserved_3[0x1f]; 4370}; 4371 4372struct mlx5_ifc_query_mad_demux_out_bits { 4373 u8 status[0x8]; 4374 u8 reserved_0[0x18]; 4375 4376 u8 syndrome[0x20]; 4377 4378 u8 reserved_1[0x40]; 4379 4380 u8 mad_dumux_parameters_block[0x20]; 4381}; 4382 4383struct mlx5_ifc_query_mad_demux_in_bits { 4384 u8 opcode[0x10]; 4385 u8 reserved_0[0x10]; 4386 4387 u8 reserved_1[0x10]; 4388 u8 op_mod[0x10]; 4389 4390 u8 reserved_2[0x40]; 4391}; 4392 4393struct mlx5_ifc_query_l2_table_entry_out_bits { 4394 u8 status[0x8]; 4395 u8 reserved_0[0x18]; 4396 4397 u8 syndrome[0x20]; 4398 4399 u8 reserved_1[0xa0]; 4400 4401 u8 reserved_2[0x13]; 4402 u8 vlan_valid[0x1]; 4403 u8 vlan[0xc]; 4404 4405 struct mlx5_ifc_mac_address_layout_bits mac_address; 4406 4407 u8 reserved_3[0xc0]; 4408}; 4409 4410struct mlx5_ifc_query_l2_table_entry_in_bits { 4411 u8 opcode[0x10]; 4412 u8 reserved_0[0x10]; 4413 4414 u8 reserved_1[0x10]; 4415 u8 op_mod[0x10]; 4416 4417 u8 reserved_2[0x60]; 4418 4419 u8 reserved_3[0x8]; 4420 u8 table_index[0x18]; 4421 4422 u8 reserved_4[0x140]; 4423}; 4424 4425struct mlx5_ifc_query_issi_out_bits { 4426 u8 status[0x8]; 4427 u8 reserved_0[0x18]; 4428 4429 u8 syndrome[0x20]; 4430 4431 u8 reserved_1[0x10]; 4432 u8 current_issi[0x10]; 4433 4434 u8 reserved_2[0xa0]; 4435 4436 u8 supported_issi_reserved[76][0x8]; 4437 u8 supported_issi_dw0[0x20]; 4438}; 4439 4440struct mlx5_ifc_query_issi_in_bits { 4441 u8 opcode[0x10]; 4442 u8 reserved_0[0x10]; 4443 4444 u8 reserved_1[0x10]; 4445 u8 op_mod[0x10]; 4446 4447 u8 reserved_2[0x40]; 4448}; 4449 4450struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4451 u8 status[0x8]; 4452 u8 reserved_0[0x18]; 4453 4454 u8 syndrome[0x20]; 4455 4456 u8 reserved_1[0x40]; 4457 4458 struct mlx5_ifc_pkey_bits pkey[0]; 4459}; 4460 4461struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4462 u8 opcode[0x10]; 4463 u8 reserved_0[0x10]; 4464 4465 u8 reserved_1[0x10]; 4466 u8 op_mod[0x10]; 4467 4468 u8 other_vport[0x1]; 4469 u8 reserved_2[0xb]; 4470 u8 port_num[0x4]; 4471 u8 vport_number[0x10]; 4472 4473 u8 reserved_3[0x10]; 4474 u8 pkey_index[0x10]; 4475}; 4476 4477struct mlx5_ifc_query_hca_vport_gid_out_bits { 4478 u8 status[0x8]; 4479 u8 reserved_0[0x18]; 4480 4481 u8 syndrome[0x20]; 4482 4483 u8 reserved_1[0x20]; 4484 4485 u8 gids_num[0x10]; 4486 u8 reserved_2[0x10]; 4487 4488 struct mlx5_ifc_array128_auto_bits gid[0]; 4489}; 4490 4491struct mlx5_ifc_query_hca_vport_gid_in_bits { 4492 u8 opcode[0x10]; 4493 u8 reserved_0[0x10]; 4494 4495 u8 reserved_1[0x10]; 4496 u8 op_mod[0x10]; 4497 4498 u8 other_vport[0x1]; 4499 u8 reserved_2[0xb]; 4500 u8 port_num[0x4]; 4501 u8 vport_number[0x10]; 4502 4503 u8 reserved_3[0x10]; 4504 u8 gid_index[0x10]; 4505}; 4506 4507struct mlx5_ifc_query_hca_vport_context_out_bits { 4508 u8 status[0x8]; 4509 u8 reserved_0[0x18]; 4510 4511 u8 syndrome[0x20]; 4512 4513 u8 reserved_1[0x40]; 4514 4515 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4516}; 4517 4518struct mlx5_ifc_query_hca_vport_context_in_bits { 4519 u8 opcode[0x10]; 4520 u8 reserved_0[0x10]; 4521 4522 u8 reserved_1[0x10]; 4523 u8 op_mod[0x10]; 4524 4525 u8 other_vport[0x1]; 4526 u8 reserved_2[0xb]; 4527 u8 port_num[0x4]; 4528 u8 vport_number[0x10]; 4529 4530 u8 reserved_3[0x20]; 4531}; 4532 4533struct mlx5_ifc_query_hca_cap_out_bits { 4534 u8 status[0x8]; 4535 u8 reserved_0[0x18]; 4536 4537 u8 syndrome[0x20]; 4538 4539 u8 reserved_1[0x40]; 4540 4541 union mlx5_ifc_hca_cap_union_bits capability; 4542}; 4543 4544struct mlx5_ifc_query_hca_cap_in_bits { 4545 u8 opcode[0x10]; 4546 u8 reserved_0[0x10]; 4547 4548 u8 reserved_1[0x10]; 4549 u8 op_mod[0x10]; 4550 4551 u8 reserved_2[0x40]; 4552}; 4553 4554struct mlx5_ifc_query_flow_table_out_bits { 4555 u8 status[0x8]; 4556 u8 reserved_at_8[0x18]; 4557 4558 u8 syndrome[0x20]; 4559 4560 u8 reserved_at_40[0x80]; 4561 4562 struct mlx5_ifc_flow_table_context_bits flow_table_context; 4563}; 4564 4565struct mlx5_ifc_query_flow_table_in_bits { 4566 u8 opcode[0x10]; 4567 u8 reserved_0[0x10]; 4568 4569 u8 reserved_1[0x10]; 4570 u8 op_mod[0x10]; 4571 4572 u8 other_vport[0x1]; 4573 u8 reserved_2[0xf]; 4574 u8 vport_number[0x10]; 4575 4576 u8 reserved_3[0x20]; 4577 4578 u8 table_type[0x8]; 4579 u8 reserved_4[0x18]; 4580 4581 u8 reserved_5[0x8]; 4582 u8 table_id[0x18]; 4583 4584 u8 reserved_6[0x140]; 4585}; 4586 4587struct mlx5_ifc_query_fte_out_bits { 4588 u8 status[0x8]; 4589 u8 reserved_0[0x18]; 4590 4591 u8 syndrome[0x20]; 4592 4593 u8 reserved_1[0x1c0]; 4594 4595 struct mlx5_ifc_flow_context_bits flow_context; 4596}; 4597 4598struct mlx5_ifc_query_fte_in_bits { 4599 u8 opcode[0x10]; 4600 u8 reserved_0[0x10]; 4601 4602 u8 reserved_1[0x10]; 4603 u8 op_mod[0x10]; 4604 4605 u8 other_vport[0x1]; 4606 u8 reserved_2[0xf]; 4607 u8 vport_number[0x10]; 4608 4609 u8 reserved_3[0x20]; 4610 4611 u8 table_type[0x8]; 4612 u8 reserved_4[0x18]; 4613 4614 u8 reserved_5[0x8]; 4615 u8 table_id[0x18]; 4616 4617 u8 reserved_6[0x40]; 4618 4619 u8 flow_index[0x20]; 4620 4621 u8 reserved_7[0xe0]; 4622}; 4623 4624enum { 4625 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4626 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4627 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4628}; 4629 4630struct mlx5_ifc_query_flow_group_out_bits { 4631 u8 status[0x8]; 4632 u8 reserved_0[0x18]; 4633 4634 u8 syndrome[0x20]; 4635 4636 u8 reserved_1[0xa0]; 4637 4638 u8 start_flow_index[0x20]; 4639 4640 u8 reserved_2[0x20]; 4641 4642 u8 end_flow_index[0x20]; 4643 4644 u8 reserved_3[0xa0]; 4645 4646 u8 reserved_4[0x18]; 4647 u8 match_criteria_enable[0x8]; 4648 4649 struct mlx5_ifc_fte_match_param_bits match_criteria; 4650 4651 u8 reserved_5[0xe00]; 4652}; 4653 4654struct mlx5_ifc_query_flow_group_in_bits { 4655 u8 opcode[0x10]; 4656 u8 reserved_0[0x10]; 4657 4658 u8 reserved_1[0x10]; 4659 u8 op_mod[0x10]; 4660 4661 u8 other_vport[0x1]; 4662 u8 reserved_2[0xf]; 4663 u8 vport_number[0x10]; 4664 4665 u8 reserved_3[0x20]; 4666 4667 u8 table_type[0x8]; 4668 u8 reserved_4[0x18]; 4669 4670 u8 reserved_5[0x8]; 4671 u8 table_id[0x18]; 4672 4673 u8 group_id[0x20]; 4674 4675 u8 reserved_6[0x120]; 4676}; 4677 4678struct mlx5_ifc_query_flow_counter_out_bits { 4679 u8 status[0x8]; 4680 u8 reserved_at_8[0x18]; 4681 4682 u8 syndrome[0x20]; 4683 4684 u8 reserved_at_40[0x40]; 4685 4686 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4687}; 4688 4689struct mlx5_ifc_query_flow_counter_in_bits { 4690 u8 opcode[0x10]; 4691 u8 reserved_at_10[0x10]; 4692 4693 u8 reserved_at_20[0x10]; 4694 u8 op_mod[0x10]; 4695 4696 u8 reserved_at_40[0x80]; 4697 4698 u8 clear[0x1]; 4699 u8 reserved_at_c1[0xf]; 4700 u8 num_of_counters[0x10]; 4701 4702 u8 reserved_at_e0[0x10]; 4703 u8 flow_counter_id[0x10]; 4704}; 4705 4706struct mlx5_ifc_query_esw_vport_context_out_bits { 4707 u8 status[0x8]; 4708 u8 reserved_0[0x18]; 4709 4710 u8 syndrome[0x20]; 4711 4712 u8 reserved_1[0x40]; 4713 4714 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4715}; 4716 4717struct mlx5_ifc_query_esw_vport_context_in_bits { 4718 u8 opcode[0x10]; 4719 u8 reserved_0[0x10]; 4720 4721 u8 reserved_1[0x10]; 4722 u8 op_mod[0x10]; 4723 4724 u8 other_vport[0x1]; 4725 u8 reserved_2[0xf]; 4726 u8 vport_number[0x10]; 4727 4728 u8 reserved_3[0x20]; 4729}; 4730 4731struct mlx5_ifc_query_eq_out_bits { 4732 u8 status[0x8]; 4733 u8 reserved_0[0x18]; 4734 4735 u8 syndrome[0x20]; 4736 4737 u8 reserved_1[0x40]; 4738 4739 struct mlx5_ifc_eqc_bits eq_context_entry; 4740 4741 u8 reserved_2[0x40]; 4742 4743 u8 event_bitmask[0x40]; 4744 4745 u8 reserved_3[0x580]; 4746 4747 u8 pas[0][0x40]; 4748}; 4749 4750struct mlx5_ifc_query_eq_in_bits { 4751 u8 opcode[0x10]; 4752 u8 reserved_0[0x10]; 4753 4754 u8 reserved_1[0x10]; 4755 u8 op_mod[0x10]; 4756 4757 u8 reserved_2[0x18]; 4758 u8 eq_number[0x8]; 4759 4760 u8 reserved_3[0x20]; 4761}; 4762 4763struct mlx5_ifc_query_dct_out_bits { 4764 u8 status[0x8]; 4765 u8 reserved_0[0x18]; 4766 4767 u8 syndrome[0x20]; 4768 4769 u8 reserved_1[0x40]; 4770 4771 struct mlx5_ifc_dctc_bits dct_context_entry; 4772 4773 u8 reserved_2[0x180]; 4774}; 4775 4776struct mlx5_ifc_query_dct_in_bits { 4777 u8 opcode[0x10]; 4778 u8 reserved_0[0x10]; 4779 4780 u8 reserved_1[0x10]; 4781 u8 op_mod[0x10]; 4782 4783 u8 reserved_2[0x8]; 4784 u8 dctn[0x18]; 4785 4786 u8 reserved_3[0x20]; 4787}; 4788 4789struct mlx5_ifc_query_dc_cnak_trace_out_bits { 4790 u8 status[0x8]; 4791 u8 reserved_0[0x18]; 4792 4793 u8 syndrome[0x20]; 4794 4795 u8 enable[0x1]; 4796 u8 reserved_1[0x1f]; 4797 4798 u8 reserved_2[0x160]; 4799 4800 struct mlx5_ifc_cmd_pas_bits pas; 4801}; 4802 4803struct mlx5_ifc_query_dc_cnak_trace_in_bits { 4804 u8 opcode[0x10]; 4805 u8 reserved_0[0x10]; 4806 4807 u8 reserved_1[0x10]; 4808 u8 op_mod[0x10]; 4809 4810 u8 reserved_2[0x40]; 4811}; 4812 4813struct mlx5_ifc_query_cq_out_bits { 4814 u8 status[0x8]; 4815 u8 reserved_0[0x18]; 4816 4817 u8 syndrome[0x20]; 4818 4819 u8 reserved_1[0x40]; 4820 4821 struct mlx5_ifc_cqc_bits cq_context; 4822 4823 u8 reserved_2[0x600]; 4824 4825 u8 pas[0][0x40]; 4826}; 4827 4828struct mlx5_ifc_query_cq_in_bits { 4829 u8 opcode[0x10]; 4830 u8 reserved_0[0x10]; 4831 4832 u8 reserved_1[0x10]; 4833 u8 op_mod[0x10]; 4834 4835 u8 reserved_2[0x8]; 4836 u8 cqn[0x18]; 4837 4838 u8 reserved_3[0x20]; 4839}; 4840 4841struct mlx5_ifc_query_cong_status_out_bits { 4842 u8 status[0x8]; 4843 u8 reserved_0[0x18]; 4844 4845 u8 syndrome[0x20]; 4846 4847 u8 reserved_1[0x20]; 4848 4849 u8 enable[0x1]; 4850 u8 tag_enable[0x1]; 4851 u8 reserved_2[0x1e]; 4852}; 4853 4854struct mlx5_ifc_query_cong_status_in_bits { 4855 u8 opcode[0x10]; 4856 u8 reserved_0[0x10]; 4857 4858 u8 reserved_1[0x10]; 4859 u8 op_mod[0x10]; 4860 4861 u8 reserved_2[0x18]; 4862 u8 priority[0x4]; 4863 u8 cong_protocol[0x4]; 4864 4865 u8 reserved_3[0x20]; 4866}; 4867 4868struct mlx5_ifc_query_cong_statistics_out_bits { 4869 u8 status[0x8]; 4870 u8 reserved_0[0x18]; 4871 4872 u8 syndrome[0x20]; 4873 4874 u8 reserved_1[0x40]; 4875 4876 u8 rp_cur_flows[0x20]; 4877 4878 u8 sum_flows[0x20]; 4879 4880 u8 rp_cnp_ignored_high[0x20]; 4881 4882 u8 rp_cnp_ignored_low[0x20]; 4883 4884 u8 rp_cnp_handled_high[0x20]; 4885 4886 u8 rp_cnp_handled_low[0x20]; 4887 4888 u8 reserved_2[0x100]; 4889 4890 u8 time_stamp_high[0x20]; 4891 4892 u8 time_stamp_low[0x20]; 4893 4894 u8 accumulators_period[0x20]; 4895 4896 u8 np_ecn_marked_roce_packets_high[0x20]; 4897 4898 u8 np_ecn_marked_roce_packets_low[0x20]; 4899 4900 u8 np_cnp_sent_high[0x20]; 4901 4902 u8 np_cnp_sent_low[0x20]; 4903 4904 u8 reserved_3[0x560]; 4905}; 4906 4907struct mlx5_ifc_query_cong_statistics_in_bits { 4908 u8 opcode[0x10]; 4909 u8 reserved_0[0x10]; 4910 4911 u8 reserved_1[0x10]; 4912 u8 op_mod[0x10]; 4913 4914 u8 clear[0x1]; 4915 u8 reserved_2[0x1f]; 4916 4917 u8 reserved_3[0x20]; 4918}; 4919 4920struct mlx5_ifc_query_cong_params_out_bits { 4921 u8 status[0x8]; 4922 u8 reserved_0[0x18]; 4923 4924 u8 syndrome[0x20]; 4925 4926 u8 reserved_1[0x40]; 4927 4928 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 4929}; 4930 4931struct mlx5_ifc_query_cong_params_in_bits { 4932 u8 opcode[0x10]; 4933 u8 reserved_0[0x10]; 4934 4935 u8 reserved_1[0x10]; 4936 u8 op_mod[0x10]; 4937 4938 u8 reserved_2[0x1c]; 4939 u8 cong_protocol[0x4]; 4940 4941 u8 reserved_3[0x20]; 4942}; 4943 4944struct mlx5_ifc_query_burst_size_out_bits { 4945 u8 status[0x8]; 4946 u8 reserved_0[0x18]; 4947 4948 u8 syndrome[0x20]; 4949 4950 u8 reserved_1[0x20]; 4951 4952 u8 reserved_2[0x9]; 4953 u8 device_burst_size[0x17]; 4954}; 4955 4956struct mlx5_ifc_query_burst_size_in_bits { 4957 u8 opcode[0x10]; 4958 u8 reserved_0[0x10]; 4959 4960 u8 reserved_1[0x10]; 4961 u8 op_mod[0x10]; 4962 4963 u8 reserved_2[0x40]; 4964}; 4965 4966struct mlx5_ifc_query_adapter_out_bits { 4967 u8 status[0x8]; 4968 u8 reserved_0[0x18]; 4969 4970 u8 syndrome[0x20]; 4971 4972 u8 reserved_1[0x40]; 4973 4974 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 4975}; 4976 4977struct mlx5_ifc_query_adapter_in_bits { 4978 u8 opcode[0x10]; 4979 u8 reserved_0[0x10]; 4980 4981 u8 reserved_1[0x10]; 4982 u8 op_mod[0x10]; 4983 4984 u8 reserved_2[0x40]; 4985}; 4986 4987struct mlx5_ifc_qp_2rst_out_bits { 4988 u8 status[0x8]; 4989 u8 reserved_0[0x18]; 4990 4991 u8 syndrome[0x20]; 4992 4993 u8 reserved_1[0x40]; 4994}; 4995 4996struct mlx5_ifc_qp_2rst_in_bits { 4997 u8 opcode[0x10]; 4998 u8 reserved_0[0x10]; 4999 5000 u8 reserved_1[0x10]; 5001 u8 op_mod[0x10]; 5002 5003 u8 reserved_2[0x8]; 5004 u8 qpn[0x18]; 5005 5006 u8 reserved_3[0x20]; 5007}; 5008 5009struct mlx5_ifc_qp_2err_out_bits { 5010 u8 status[0x8]; 5011 u8 reserved_0[0x18]; 5012 5013 u8 syndrome[0x20]; 5014 5015 u8 reserved_1[0x40]; 5016}; 5017 5018struct mlx5_ifc_qp_2err_in_bits { 5019 u8 opcode[0x10]; 5020 u8 reserved_0[0x10]; 5021 5022 u8 reserved_1[0x10]; 5023 u8 op_mod[0x10]; 5024 5025 u8 reserved_2[0x8]; 5026 u8 qpn[0x18]; 5027 5028 u8 reserved_3[0x20]; 5029}; 5030 5031struct mlx5_ifc_para_vport_element_bits { 5032 u8 reserved_at_0[0xc]; 5033 u8 traffic_class[0x4]; 5034 u8 qos_para_vport_number[0x10]; 5035}; 5036 5037struct mlx5_ifc_page_fault_resume_out_bits { 5038 u8 status[0x8]; 5039 u8 reserved_0[0x18]; 5040 5041 u8 syndrome[0x20]; 5042 5043 u8 reserved_1[0x40]; 5044}; 5045 5046struct mlx5_ifc_page_fault_resume_in_bits { 5047 u8 opcode[0x10]; 5048 u8 reserved_0[0x10]; 5049 5050 u8 reserved_1[0x10]; 5051 u8 op_mod[0x10]; 5052 5053 u8 error[0x1]; 5054 u8 reserved_2[0x4]; 5055 u8 rdma[0x1]; 5056 u8 read_write[0x1]; 5057 u8 req_res[0x1]; 5058 u8 qpn[0x18]; 5059 5060 u8 reserved_3[0x20]; 5061}; 5062 5063struct mlx5_ifc_nop_out_bits { 5064 u8 status[0x8]; 5065 u8 reserved_0[0x18]; 5066 5067 u8 syndrome[0x20]; 5068 5069 u8 reserved_1[0x40]; 5070}; 5071 5072struct mlx5_ifc_nop_in_bits { 5073 u8 opcode[0x10]; 5074 u8 reserved_0[0x10]; 5075 5076 u8 reserved_1[0x10]; 5077 u8 op_mod[0x10]; 5078 5079 u8 reserved_2[0x40]; 5080}; 5081 5082struct mlx5_ifc_modify_vport_state_out_bits { 5083 u8 status[0x8]; 5084 u8 reserved_0[0x18]; 5085 5086 u8 syndrome[0x20]; 5087 5088 u8 reserved_1[0x40]; 5089}; 5090 5091enum { 5092 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT = 0x0, 5093 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 5094 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 5095}; 5096 5097enum { 5098 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN = 0x0, 5099 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP = 0x1, 5100 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW = 0x2, 5101}; 5102 5103struct mlx5_ifc_modify_vport_state_in_bits { 5104 u8 opcode[0x10]; 5105 u8 reserved_0[0x10]; 5106 5107 u8 reserved_1[0x10]; 5108 u8 op_mod[0x10]; 5109 5110 u8 other_vport[0x1]; 5111 u8 reserved_2[0xf]; 5112 u8 vport_number[0x10]; 5113 5114 u8 reserved_3[0x18]; 5115 u8 admin_state[0x4]; 5116 u8 reserved_4[0x4]; 5117}; 5118 5119struct mlx5_ifc_modify_tis_out_bits { 5120 u8 status[0x8]; 5121 u8 reserved_0[0x18]; 5122 5123 u8 syndrome[0x20]; 5124 5125 u8 reserved_1[0x40]; 5126}; 5127 5128struct mlx5_ifc_modify_tis_bitmask_bits { 5129 u8 reserved_at_0[0x20]; 5130 5131 u8 reserved_at_20[0x1d]; 5132 u8 lag_tx_port_affinity[0x1]; 5133 u8 strict_lag_tx_port_affinity[0x1]; 5134 u8 prio[0x1]; 5135}; 5136 5137struct mlx5_ifc_modify_tis_in_bits { 5138 u8 opcode[0x10]; 5139 u8 reserved_0[0x10]; 5140 5141 u8 reserved_1[0x10]; 5142 u8 op_mod[0x10]; 5143 5144 u8 reserved_2[0x8]; 5145 u8 tisn[0x18]; 5146 5147 u8 reserved_3[0x20]; 5148 5149 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5150 5151 u8 reserved_4[0x40]; 5152 5153 struct mlx5_ifc_tisc_bits ctx; 5154}; 5155 5156struct mlx5_ifc_modify_tir_out_bits { 5157 u8 status[0x8]; 5158 u8 reserved_0[0x18]; 5159 5160 u8 syndrome[0x20]; 5161 5162 u8 reserved_1[0x40]; 5163}; 5164 5165enum 5166{ 5167 MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0, 5168 MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER = 0x1 << 1 5169}; 5170 5171struct mlx5_ifc_modify_tir_in_bits { 5172 u8 opcode[0x10]; 5173 u8 reserved_0[0x10]; 5174 5175 u8 reserved_1[0x10]; 5176 u8 op_mod[0x10]; 5177 5178 u8 reserved_2[0x8]; 5179 u8 tirn[0x18]; 5180 5181 u8 reserved_3[0x20]; 5182 5183 u8 modify_bitmask[0x40]; 5184 5185 u8 reserved_4[0x40]; 5186 5187 struct mlx5_ifc_tirc_bits tir_context; 5188}; 5189 5190struct mlx5_ifc_modify_sq_out_bits { 5191 u8 status[0x8]; 5192 u8 reserved_0[0x18]; 5193 5194 u8 syndrome[0x20]; 5195 5196 u8 reserved_1[0x40]; 5197}; 5198 5199struct mlx5_ifc_modify_sq_in_bits { 5200 u8 opcode[0x10]; 5201 u8 reserved_0[0x10]; 5202 5203 u8 reserved_1[0x10]; 5204 u8 op_mod[0x10]; 5205 5206 u8 sq_state[0x4]; 5207 u8 reserved_2[0x4]; 5208 u8 sqn[0x18]; 5209 5210 u8 reserved_3[0x20]; 5211 5212 u8 modify_bitmask[0x40]; 5213 5214 u8 reserved_4[0x40]; 5215 5216 struct mlx5_ifc_sqc_bits ctx; 5217}; 5218 5219struct mlx5_ifc_modify_scheduling_element_out_bits { 5220 u8 status[0x8]; 5221 u8 reserved_at_8[0x18]; 5222 5223 u8 syndrome[0x20]; 5224 5225 u8 reserved_at_40[0x1c0]; 5226}; 5227 5228enum { 5229 MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5230}; 5231 5232enum { 5233 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE = 0x1, 5234 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW = 0x2, 5235}; 5236 5237struct mlx5_ifc_modify_scheduling_element_in_bits { 5238 u8 opcode[0x10]; 5239 u8 reserved_at_10[0x10]; 5240 5241 u8 reserved_at_20[0x10]; 5242 u8 op_mod[0x10]; 5243 5244 u8 scheduling_hierarchy[0x8]; 5245 u8 reserved_at_48[0x18]; 5246 5247 u8 scheduling_element_id[0x20]; 5248 5249 u8 reserved_at_80[0x20]; 5250 5251 u8 modify_bitmask[0x20]; 5252 5253 u8 reserved_at_c0[0x40]; 5254 5255 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5256 5257 u8 reserved_at_300[0x100]; 5258}; 5259 5260struct mlx5_ifc_modify_rqt_out_bits { 5261 u8 status[0x8]; 5262 u8 reserved_0[0x18]; 5263 5264 u8 syndrome[0x20]; 5265 5266 u8 reserved_1[0x40]; 5267}; 5268 5269struct mlx5_ifc_modify_rqt_in_bits { 5270 u8 opcode[0x10]; 5271 u8 reserved_0[0x10]; 5272 5273 u8 reserved_1[0x10]; 5274 u8 op_mod[0x10]; 5275 5276 u8 reserved_2[0x8]; 5277 u8 rqtn[0x18]; 5278 5279 u8 reserved_3[0x20]; 5280 5281 u8 modify_bitmask[0x40]; 5282 5283 u8 reserved_4[0x40]; 5284 5285 struct mlx5_ifc_rqtc_bits ctx; 5286}; 5287 5288struct mlx5_ifc_modify_rq_out_bits { 5289 u8 status[0x8]; 5290 u8 reserved_0[0x18]; 5291 5292 u8 syndrome[0x20]; 5293 5294 u8 reserved_1[0x40]; 5295}; 5296 5297enum { 5298 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5299 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3, 5300}; 5301 5302struct mlx5_ifc_modify_rq_in_bits { 5303 u8 opcode[0x10]; 5304 u8 reserved_0[0x10]; 5305 5306 u8 reserved_1[0x10]; 5307 u8 op_mod[0x10]; 5308 5309 u8 rq_state[0x4]; 5310 u8 reserved_2[0x4]; 5311 u8 rqn[0x18]; 5312 5313 u8 reserved_3[0x20]; 5314 5315 u8 modify_bitmask[0x40]; 5316 5317 u8 reserved_4[0x40]; 5318 5319 struct mlx5_ifc_rqc_bits ctx; 5320}; 5321 5322struct mlx5_ifc_modify_rmp_out_bits { 5323 u8 status[0x8]; 5324 u8 reserved_0[0x18]; 5325 5326 u8 syndrome[0x20]; 5327 5328 u8 reserved_1[0x40]; 5329}; 5330 5331struct mlx5_ifc_rmp_bitmask_bits { 5332 u8 reserved[0x20]; 5333 5334 u8 reserved1[0x1f]; 5335 u8 lwm[0x1]; 5336}; 5337 5338struct mlx5_ifc_modify_rmp_in_bits { 5339 u8 opcode[0x10]; 5340 u8 reserved_0[0x10]; 5341 5342 u8 reserved_1[0x10]; 5343 u8 op_mod[0x10]; 5344 5345 u8 rmp_state[0x4]; 5346 u8 reserved_2[0x4]; 5347 u8 rmpn[0x18]; 5348 5349 u8 reserved_3[0x20]; 5350 5351 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5352 5353 u8 reserved_4[0x40]; 5354 5355 struct mlx5_ifc_rmpc_bits ctx; 5356}; 5357 5358struct mlx5_ifc_modify_nic_vport_context_out_bits { 5359 u8 status[0x8]; 5360 u8 reserved_0[0x18]; 5361 5362 u8 syndrome[0x20]; 5363 5364 u8 reserved_1[0x40]; 5365}; 5366 5367struct mlx5_ifc_modify_nic_vport_field_select_bits { 5368 u8 reserved_0[0x14]; 5369 u8 disable_uc_local_lb[0x1]; 5370 u8 disable_mc_local_lb[0x1]; 5371 u8 node_guid[0x1]; 5372 u8 port_guid[0x1]; 5373 u8 min_wqe_inline_mode[0x1]; 5374 u8 mtu[0x1]; 5375 u8 change_event[0x1]; 5376 u8 promisc[0x1]; 5377 u8 permanent_address[0x1]; 5378 u8 addresses_list[0x1]; 5379 u8 roce_en[0x1]; 5380 u8 reserved_1[0x1]; 5381}; 5382 5383struct mlx5_ifc_modify_nic_vport_context_in_bits { 5384 u8 opcode[0x10]; 5385 u8 reserved_0[0x10]; 5386 5387 u8 reserved_1[0x10]; 5388 u8 op_mod[0x10]; 5389 5390 u8 other_vport[0x1]; 5391 u8 reserved_2[0xf]; 5392 u8 vport_number[0x10]; 5393 5394 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5395 5396 u8 reserved_3[0x780]; 5397 5398 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5399}; 5400 5401struct mlx5_ifc_modify_hca_vport_context_out_bits { 5402 u8 status[0x8]; 5403 u8 reserved_0[0x18]; 5404 5405 u8 syndrome[0x20]; 5406 5407 u8 reserved_1[0x40]; 5408}; 5409 5410struct mlx5_ifc_grh_bits { 5411 u8 ip_version[4]; 5412 u8 traffic_class[8]; 5413 u8 flow_label[20]; 5414 u8 payload_length[16]; 5415 u8 next_header[8]; 5416 u8 hop_limit[8]; 5417 u8 sgid[128]; 5418 u8 dgid[128]; 5419}; 5420 5421struct mlx5_ifc_bth_bits { 5422 u8 opcode[8]; 5423 u8 se[1]; 5424 u8 migreq[1]; 5425 u8 pad_count[2]; 5426 u8 tver[4]; 5427 u8 p_key[16]; 5428 u8 reserved8[8]; 5429 u8 dest_qp[24]; 5430 u8 ack_req[1]; 5431 u8 reserved7[7]; 5432 u8 psn[24]; 5433}; 5434 5435struct mlx5_ifc_aeth_bits { 5436 u8 syndrome[8]; 5437 u8 msn[24]; 5438}; 5439 5440struct mlx5_ifc_dceth_bits { 5441 u8 reserved0[8]; 5442 u8 session_id[24]; 5443 u8 reserved1[8]; 5444 u8 dci_dct[24]; 5445}; 5446 5447struct mlx5_ifc_modify_hca_vport_context_in_bits { 5448 u8 opcode[0x10]; 5449 u8 reserved_0[0x10]; 5450 5451 u8 reserved_1[0x10]; 5452 u8 op_mod[0x10]; 5453 5454 u8 other_vport[0x1]; 5455 u8 reserved_2[0xb]; 5456 u8 port_num[0x4]; 5457 u8 vport_number[0x10]; 5458 5459 u8 reserved_3[0x20]; 5460 5461 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5462}; 5463 5464struct mlx5_ifc_modify_flow_table_out_bits { 5465 u8 status[0x8]; 5466 u8 reserved_at_8[0x18]; 5467 5468 u8 syndrome[0x20]; 5469 5470 u8 reserved_at_40[0x40]; 5471}; 5472 5473enum { 5474 MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1, 5475 MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000, 5476}; 5477 5478struct mlx5_ifc_modify_flow_table_in_bits { 5479 u8 opcode[0x10]; 5480 u8 reserved_at_10[0x10]; 5481 5482 u8 reserved_at_20[0x10]; 5483 u8 op_mod[0x10]; 5484 5485 u8 other_vport[0x1]; 5486 u8 reserved_at_41[0xf]; 5487 u8 vport_number[0x10]; 5488 5489 u8 reserved_at_60[0x10]; 5490 u8 modify_field_select[0x10]; 5491 5492 u8 table_type[0x8]; 5493 u8 reserved_at_88[0x18]; 5494 5495 u8 reserved_at_a0[0x8]; 5496 u8 table_id[0x18]; 5497 5498 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5499}; 5500 5501struct mlx5_ifc_modify_esw_vport_context_out_bits { 5502 u8 status[0x8]; 5503 u8 reserved_0[0x18]; 5504 5505 u8 syndrome[0x20]; 5506 5507 u8 reserved_1[0x40]; 5508}; 5509 5510struct mlx5_ifc_esw_vport_context_fields_select_bits { 5511 u8 reserved[0x1c]; 5512 u8 vport_cvlan_insert[0x1]; 5513 u8 vport_svlan_insert[0x1]; 5514 u8 vport_cvlan_strip[0x1]; 5515 u8 vport_svlan_strip[0x1]; 5516}; 5517 5518struct mlx5_ifc_modify_esw_vport_context_in_bits { 5519 u8 opcode[0x10]; 5520 u8 reserved_0[0x10]; 5521 5522 u8 reserved_1[0x10]; 5523 u8 op_mod[0x10]; 5524 5525 u8 other_vport[0x1]; 5526 u8 reserved_2[0xf]; 5527 u8 vport_number[0x10]; 5528 5529 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5530 5531 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5532}; 5533 5534struct mlx5_ifc_modify_cq_out_bits { 5535 u8 status[0x8]; 5536 u8 reserved_0[0x18]; 5537 5538 u8 syndrome[0x20]; 5539 5540 u8 reserved_1[0x40]; 5541}; 5542 5543enum { 5544 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5545 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5546}; 5547 5548struct mlx5_ifc_modify_cq_in_bits { 5549 u8 opcode[0x10]; 5550 u8 reserved_0[0x10]; 5551 5552 u8 reserved_1[0x10]; 5553 u8 op_mod[0x10]; 5554 5555 u8 reserved_2[0x8]; 5556 u8 cqn[0x18]; 5557 5558 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5559 5560 struct mlx5_ifc_cqc_bits cq_context; 5561 5562 u8 reserved_3[0x600]; 5563 5564 u8 pas[0][0x40]; 5565}; 5566 5567struct mlx5_ifc_modify_cong_status_out_bits { 5568 u8 status[0x8]; 5569 u8 reserved_0[0x18]; 5570 5571 u8 syndrome[0x20]; 5572 5573 u8 reserved_1[0x40]; 5574}; 5575 5576struct mlx5_ifc_modify_cong_status_in_bits { 5577 u8 opcode[0x10]; 5578 u8 reserved_0[0x10]; 5579 5580 u8 reserved_1[0x10]; 5581 u8 op_mod[0x10]; 5582 5583 u8 reserved_2[0x18]; 5584 u8 priority[0x4]; 5585 u8 cong_protocol[0x4]; 5586 5587 u8 enable[0x1]; 5588 u8 tag_enable[0x1]; 5589 u8 reserved_3[0x1e]; 5590}; 5591 5592struct mlx5_ifc_modify_cong_params_out_bits { 5593 u8 status[0x8]; 5594 u8 reserved_0[0x18]; 5595 5596 u8 syndrome[0x20]; 5597 5598 u8 reserved_1[0x40]; 5599}; 5600 5601struct mlx5_ifc_modify_cong_params_in_bits { 5602 u8 opcode[0x10]; 5603 u8 reserved_0[0x10]; 5604 5605 u8 reserved_1[0x10]; 5606 u8 op_mod[0x10]; 5607 5608 u8 reserved_2[0x1c]; 5609 u8 cong_protocol[0x4]; 5610 5611 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5612 5613 u8 reserved_3[0x80]; 5614 5615 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5616}; 5617 5618struct mlx5_ifc_manage_pages_out_bits { 5619 u8 status[0x8]; 5620 u8 reserved_0[0x18]; 5621 5622 u8 syndrome[0x20]; 5623 5624 u8 output_num_entries[0x20]; 5625 5626 u8 reserved_1[0x20]; 5627 5628 u8 pas[0][0x40]; 5629}; 5630 5631enum { 5632 MLX5_PAGES_CANT_GIVE = 0x0, 5633 MLX5_PAGES_GIVE = 0x1, 5634 MLX5_PAGES_TAKE = 0x2, 5635}; 5636 5637struct mlx5_ifc_manage_pages_in_bits { 5638 u8 opcode[0x10]; 5639 u8 reserved_0[0x10]; 5640 5641 u8 reserved_1[0x10]; 5642 u8 op_mod[0x10]; 5643 5644 u8 reserved_2[0x10]; 5645 u8 function_id[0x10]; 5646 5647 u8 input_num_entries[0x20]; 5648 5649 u8 pas[0][0x40]; 5650}; 5651 5652struct mlx5_ifc_mad_ifc_out_bits { 5653 u8 status[0x8]; 5654 u8 reserved_0[0x18]; 5655 5656 u8 syndrome[0x20]; 5657 5658 u8 reserved_1[0x40]; 5659 5660 u8 response_mad_packet[256][0x8]; 5661}; 5662 5663struct mlx5_ifc_mad_ifc_in_bits { 5664 u8 opcode[0x10]; 5665 u8 reserved_0[0x10]; 5666 5667 u8 reserved_1[0x10]; 5668 u8 op_mod[0x10]; 5669 5670 u8 remote_lid[0x10]; 5671 u8 reserved_2[0x8]; 5672 u8 port[0x8]; 5673 5674 u8 reserved_3[0x20]; 5675 5676 u8 mad[256][0x8]; 5677}; 5678 5679struct mlx5_ifc_init_hca_out_bits { 5680 u8 status[0x8]; 5681 u8 reserved_0[0x18]; 5682 5683 u8 syndrome[0x20]; 5684 5685 u8 reserved_1[0x40]; 5686}; 5687 5688enum { 5689 MLX5_INIT_HCA_IN_OP_MOD_INIT = 0x0, 5690 MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT = 0x1, 5691}; 5692 5693struct mlx5_ifc_init_hca_in_bits { 5694 u8 opcode[0x10]; 5695 u8 reserved_0[0x10]; 5696 5697 u8 reserved_1[0x10]; 5698 u8 op_mod[0x10]; 5699 5700 u8 reserved_2[0x40]; 5701}; 5702 5703struct mlx5_ifc_init2rtr_qp_out_bits { 5704 u8 status[0x8]; 5705 u8 reserved_0[0x18]; 5706 5707 u8 syndrome[0x20]; 5708 5709 u8 reserved_1[0x40]; 5710}; 5711 5712struct mlx5_ifc_init2rtr_qp_in_bits { 5713 u8 opcode[0x10]; 5714 u8 reserved_0[0x10]; 5715 5716 u8 reserved_1[0x10]; 5717 u8 op_mod[0x10]; 5718 5719 u8 reserved_2[0x8]; 5720 u8 qpn[0x18]; 5721 5722 u8 reserved_3[0x20]; 5723 5724 u8 opt_param_mask[0x20]; 5725 5726 u8 reserved_4[0x20]; 5727 5728 struct mlx5_ifc_qpc_bits qpc; 5729 5730 u8 reserved_5[0x80]; 5731}; 5732 5733struct mlx5_ifc_init2init_qp_out_bits { 5734 u8 status[0x8]; 5735 u8 reserved_0[0x18]; 5736 5737 u8 syndrome[0x20]; 5738 5739 u8 reserved_1[0x40]; 5740}; 5741 5742struct mlx5_ifc_init2init_qp_in_bits { 5743 u8 opcode[0x10]; 5744 u8 reserved_0[0x10]; 5745 5746 u8 reserved_1[0x10]; 5747 u8 op_mod[0x10]; 5748 5749 u8 reserved_2[0x8]; 5750 u8 qpn[0x18]; 5751 5752 u8 reserved_3[0x20]; 5753 5754 u8 opt_param_mask[0x20]; 5755 5756 u8 reserved_4[0x20]; 5757 5758 struct mlx5_ifc_qpc_bits qpc; 5759 5760 u8 reserved_5[0x80]; 5761}; 5762 5763struct mlx5_ifc_get_dropped_packet_log_out_bits { 5764 u8 status[0x8]; 5765 u8 reserved_0[0x18]; 5766 5767 u8 syndrome[0x20]; 5768 5769 u8 reserved_1[0x40]; 5770 5771 u8 packet_headers_log[128][0x8]; 5772 5773 u8 packet_syndrome[64][0x8]; 5774}; 5775 5776struct mlx5_ifc_get_dropped_packet_log_in_bits { 5777 u8 opcode[0x10]; 5778 u8 reserved_0[0x10]; 5779 5780 u8 reserved_1[0x10]; 5781 u8 op_mod[0x10]; 5782 5783 u8 reserved_2[0x40]; 5784}; 5785 5786struct mlx5_ifc_gen_eqe_in_bits { 5787 u8 opcode[0x10]; 5788 u8 reserved_0[0x10]; 5789 5790 u8 reserved_1[0x10]; 5791 u8 op_mod[0x10]; 5792 5793 u8 reserved_2[0x18]; 5794 u8 eq_number[0x8]; 5795 5796 u8 reserved_3[0x20]; 5797 5798 u8 eqe[64][0x8]; 5799}; 5800 5801struct mlx5_ifc_gen_eq_out_bits { 5802 u8 status[0x8]; 5803 u8 reserved_0[0x18]; 5804 5805 u8 syndrome[0x20]; 5806 5807 u8 reserved_1[0x40]; 5808}; 5809 5810struct mlx5_ifc_enable_hca_out_bits { 5811 u8 status[0x8]; 5812 u8 reserved_0[0x18]; 5813 5814 u8 syndrome[0x20]; 5815 5816 u8 reserved_1[0x20]; 5817}; 5818 5819struct mlx5_ifc_enable_hca_in_bits { 5820 u8 opcode[0x10]; 5821 u8 reserved_0[0x10]; 5822 5823 u8 reserved_1[0x10]; 5824 u8 op_mod[0x10]; 5825 5826 u8 reserved_2[0x10]; 5827 u8 function_id[0x10]; 5828 5829 u8 reserved_3[0x20]; 5830}; 5831 5832struct mlx5_ifc_drain_dct_out_bits { 5833 u8 status[0x8]; 5834 u8 reserved_0[0x18]; 5835 5836 u8 syndrome[0x20]; 5837 5838 u8 reserved_1[0x40]; 5839}; 5840 5841struct mlx5_ifc_drain_dct_in_bits { 5842 u8 opcode[0x10]; 5843 u8 reserved_0[0x10]; 5844 5845 u8 reserved_1[0x10]; 5846 u8 op_mod[0x10]; 5847 5848 u8 reserved_2[0x8]; 5849 u8 dctn[0x18]; 5850 5851 u8 reserved_3[0x20]; 5852}; 5853 5854struct mlx5_ifc_disable_hca_out_bits { 5855 u8 status[0x8]; 5856 u8 reserved_0[0x18]; 5857 5858 u8 syndrome[0x20]; 5859 5860 u8 reserved_1[0x20]; 5861}; 5862 5863struct mlx5_ifc_disable_hca_in_bits { 5864 u8 opcode[0x10]; 5865 u8 reserved_0[0x10]; 5866 5867 u8 reserved_1[0x10]; 5868 u8 op_mod[0x10]; 5869 5870 u8 reserved_2[0x10]; 5871 u8 function_id[0x10]; 5872 5873 u8 reserved_3[0x20]; 5874}; 5875 5876struct mlx5_ifc_detach_from_mcg_out_bits { 5877 u8 status[0x8]; 5878 u8 reserved_0[0x18]; 5879 5880 u8 syndrome[0x20]; 5881 5882 u8 reserved_1[0x40]; 5883}; 5884 5885struct mlx5_ifc_detach_from_mcg_in_bits { 5886 u8 opcode[0x10]; 5887 u8 reserved_0[0x10]; 5888 5889 u8 reserved_1[0x10]; 5890 u8 op_mod[0x10]; 5891 5892 u8 reserved_2[0x8]; 5893 u8 qpn[0x18]; 5894 5895 u8 reserved_3[0x20]; 5896 5897 u8 multicast_gid[16][0x8]; 5898}; 5899 5900struct mlx5_ifc_destroy_xrc_srq_out_bits { 5901 u8 status[0x8]; 5902 u8 reserved_0[0x18]; 5903 5904 u8 syndrome[0x20]; 5905 5906 u8 reserved_1[0x40]; 5907}; 5908 5909struct mlx5_ifc_destroy_xrc_srq_in_bits { 5910 u8 opcode[0x10]; 5911 u8 reserved_0[0x10]; 5912 5913 u8 reserved_1[0x10]; 5914 u8 op_mod[0x10]; 5915 5916 u8 reserved_2[0x8]; 5917 u8 xrc_srqn[0x18]; 5918 5919 u8 reserved_3[0x20]; 5920}; 5921 5922struct mlx5_ifc_destroy_tis_out_bits { 5923 u8 status[0x8]; 5924 u8 reserved_0[0x18]; 5925 5926 u8 syndrome[0x20]; 5927 5928 u8 reserved_1[0x40]; 5929}; 5930 5931struct mlx5_ifc_destroy_tis_in_bits { 5932 u8 opcode[0x10]; 5933 u8 reserved_0[0x10]; 5934 5935 u8 reserved_1[0x10]; 5936 u8 op_mod[0x10]; 5937 5938 u8 reserved_2[0x8]; 5939 u8 tisn[0x18]; 5940 5941 u8 reserved_3[0x20]; 5942}; 5943 5944struct mlx5_ifc_destroy_tir_out_bits { 5945 u8 status[0x8]; 5946 u8 reserved_0[0x18]; 5947 5948 u8 syndrome[0x20]; 5949 5950 u8 reserved_1[0x40]; 5951}; 5952 5953struct mlx5_ifc_destroy_tir_in_bits { 5954 u8 opcode[0x10]; 5955 u8 reserved_0[0x10]; 5956 5957 u8 reserved_1[0x10]; 5958 u8 op_mod[0x10]; 5959 5960 u8 reserved_2[0x8]; 5961 u8 tirn[0x18]; 5962 5963 u8 reserved_3[0x20]; 5964}; 5965 5966struct mlx5_ifc_destroy_srq_out_bits { 5967 u8 status[0x8]; 5968 u8 reserved_0[0x18]; 5969 5970 u8 syndrome[0x20]; 5971 5972 u8 reserved_1[0x40]; 5973}; 5974 5975struct mlx5_ifc_destroy_srq_in_bits { 5976 u8 opcode[0x10]; 5977 u8 reserved_0[0x10]; 5978 5979 u8 reserved_1[0x10]; 5980 u8 op_mod[0x10]; 5981 5982 u8 reserved_2[0x8]; 5983 u8 srqn[0x18]; 5984 5985 u8 reserved_3[0x20]; 5986}; 5987 5988struct mlx5_ifc_destroy_sq_out_bits { 5989 u8 status[0x8]; 5990 u8 reserved_0[0x18]; 5991 5992 u8 syndrome[0x20]; 5993 5994 u8 reserved_1[0x40]; 5995}; 5996 5997struct mlx5_ifc_destroy_sq_in_bits { 5998 u8 opcode[0x10]; 5999 u8 reserved_0[0x10]; 6000 6001 u8 reserved_1[0x10]; 6002 u8 op_mod[0x10]; 6003 6004 u8 reserved_2[0x8]; 6005 u8 sqn[0x18]; 6006 6007 u8 reserved_3[0x20]; 6008}; 6009 6010struct mlx5_ifc_destroy_scheduling_element_out_bits { 6011 u8 status[0x8]; 6012 u8 reserved_at_8[0x18]; 6013 6014 u8 syndrome[0x20]; 6015 6016 u8 reserved_at_40[0x1c0]; 6017}; 6018 6019enum { 6020 MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 6021}; 6022 6023struct mlx5_ifc_destroy_scheduling_element_in_bits { 6024 u8 opcode[0x10]; 6025 u8 reserved_at_10[0x10]; 6026 6027 u8 reserved_at_20[0x10]; 6028 u8 op_mod[0x10]; 6029 6030 u8 scheduling_hierarchy[0x8]; 6031 u8 reserved_at_48[0x18]; 6032 6033 u8 scheduling_element_id[0x20]; 6034 6035 u8 reserved_at_80[0x180]; 6036}; 6037 6038struct mlx5_ifc_destroy_rqt_out_bits { 6039 u8 status[0x8]; 6040 u8 reserved_0[0x18]; 6041 6042 u8 syndrome[0x20]; 6043 6044 u8 reserved_1[0x40]; 6045}; 6046 6047struct mlx5_ifc_destroy_rqt_in_bits { 6048 u8 opcode[0x10]; 6049 u8 reserved_0[0x10]; 6050 6051 u8 reserved_1[0x10]; 6052 u8 op_mod[0x10]; 6053 6054 u8 reserved_2[0x8]; 6055 u8 rqtn[0x18]; 6056 6057 u8 reserved_3[0x20]; 6058}; 6059 6060struct mlx5_ifc_destroy_rq_out_bits { 6061 u8 status[0x8]; 6062 u8 reserved_0[0x18]; 6063 6064 u8 syndrome[0x20]; 6065 6066 u8 reserved_1[0x40]; 6067}; 6068 6069struct mlx5_ifc_destroy_rq_in_bits { 6070 u8 opcode[0x10]; 6071 u8 reserved_0[0x10]; 6072 6073 u8 reserved_1[0x10]; 6074 u8 op_mod[0x10]; 6075 6076 u8 reserved_2[0x8]; 6077 u8 rqn[0x18]; 6078 6079 u8 reserved_3[0x20]; 6080}; 6081 6082struct mlx5_ifc_destroy_rmp_out_bits { 6083 u8 status[0x8]; 6084 u8 reserved_0[0x18]; 6085 6086 u8 syndrome[0x20]; 6087 6088 u8 reserved_1[0x40]; 6089}; 6090 6091struct mlx5_ifc_destroy_rmp_in_bits { 6092 u8 opcode[0x10]; 6093 u8 reserved_0[0x10]; 6094 6095 u8 reserved_1[0x10]; 6096 u8 op_mod[0x10]; 6097 6098 u8 reserved_2[0x8]; 6099 u8 rmpn[0x18]; 6100 6101 u8 reserved_3[0x20]; 6102}; 6103 6104struct mlx5_ifc_destroy_qp_out_bits { 6105 u8 status[0x8]; 6106 u8 reserved_0[0x18]; 6107 6108 u8 syndrome[0x20]; 6109 6110 u8 reserved_1[0x40]; 6111}; 6112 6113struct mlx5_ifc_destroy_qp_in_bits { 6114 u8 opcode[0x10]; 6115 u8 reserved_0[0x10]; 6116 6117 u8 reserved_1[0x10]; 6118 u8 op_mod[0x10]; 6119 6120 u8 reserved_2[0x8]; 6121 u8 qpn[0x18]; 6122 6123 u8 reserved_3[0x20]; 6124}; 6125 6126struct mlx5_ifc_destroy_qos_para_vport_out_bits { 6127 u8 status[0x8]; 6128 u8 reserved_at_8[0x18]; 6129 6130 u8 syndrome[0x20]; 6131 6132 u8 reserved_at_40[0x1c0]; 6133}; 6134 6135struct mlx5_ifc_destroy_qos_para_vport_in_bits { 6136 u8 opcode[0x10]; 6137 u8 reserved_at_10[0x10]; 6138 6139 u8 reserved_at_20[0x10]; 6140 u8 op_mod[0x10]; 6141 6142 u8 reserved_at_40[0x20]; 6143 6144 u8 reserved_at_60[0x10]; 6145 u8 qos_para_vport_number[0x10]; 6146 6147 u8 reserved_at_80[0x180]; 6148}; 6149 6150struct mlx5_ifc_destroy_psv_out_bits { 6151 u8 status[0x8]; 6152 u8 reserved_0[0x18]; 6153 6154 u8 syndrome[0x20]; 6155 6156 u8 reserved_1[0x40]; 6157}; 6158 6159struct mlx5_ifc_destroy_psv_in_bits { 6160 u8 opcode[0x10]; 6161 u8 reserved_0[0x10]; 6162 6163 u8 reserved_1[0x10]; 6164 u8 op_mod[0x10]; 6165 6166 u8 reserved_2[0x8]; 6167 u8 psvn[0x18]; 6168 6169 u8 reserved_3[0x20]; 6170}; 6171 6172struct mlx5_ifc_destroy_mkey_out_bits { 6173 u8 status[0x8]; 6174 u8 reserved_0[0x18]; 6175 6176 u8 syndrome[0x20]; 6177 6178 u8 reserved_1[0x40]; 6179}; 6180 6181struct mlx5_ifc_destroy_mkey_in_bits { 6182 u8 opcode[0x10]; 6183 u8 reserved_0[0x10]; 6184 6185 u8 reserved_1[0x10]; 6186 u8 op_mod[0x10]; 6187 6188 u8 reserved_2[0x8]; 6189 u8 mkey_index[0x18]; 6190 6191 u8 reserved_3[0x20]; 6192}; 6193 6194struct mlx5_ifc_destroy_flow_table_out_bits { 6195 u8 status[0x8]; 6196 u8 reserved_0[0x18]; 6197 6198 u8 syndrome[0x20]; 6199 6200 u8 reserved_1[0x40]; 6201}; 6202 6203struct mlx5_ifc_destroy_flow_table_in_bits { 6204 u8 opcode[0x10]; 6205 u8 reserved_0[0x10]; 6206 6207 u8 reserved_1[0x10]; 6208 u8 op_mod[0x10]; 6209 6210 u8 other_vport[0x1]; 6211 u8 reserved_2[0xf]; 6212 u8 vport_number[0x10]; 6213 6214 u8 reserved_3[0x20]; 6215 6216 u8 table_type[0x8]; 6217 u8 reserved_4[0x18]; 6218 6219 u8 reserved_5[0x8]; 6220 u8 table_id[0x18]; 6221 6222 u8 reserved_6[0x140]; 6223}; 6224 6225struct mlx5_ifc_destroy_flow_group_out_bits { 6226 u8 status[0x8]; 6227 u8 reserved_0[0x18]; 6228 6229 u8 syndrome[0x20]; 6230 6231 u8 reserved_1[0x40]; 6232}; 6233 6234struct mlx5_ifc_destroy_flow_group_in_bits { 6235 u8 opcode[0x10]; 6236 u8 reserved_0[0x10]; 6237 6238 u8 reserved_1[0x10]; 6239 u8 op_mod[0x10]; 6240 6241 u8 other_vport[0x1]; 6242 u8 reserved_2[0xf]; 6243 u8 vport_number[0x10]; 6244 6245 u8 reserved_3[0x20]; 6246 6247 u8 table_type[0x8]; 6248 u8 reserved_4[0x18]; 6249 6250 u8 reserved_5[0x8]; 6251 u8 table_id[0x18]; 6252 6253 u8 group_id[0x20]; 6254 6255 u8 reserved_6[0x120]; 6256}; 6257 6258struct mlx5_ifc_destroy_eq_out_bits { 6259 u8 status[0x8]; 6260 u8 reserved_0[0x18]; 6261 6262 u8 syndrome[0x20]; 6263 6264 u8 reserved_1[0x40]; 6265}; 6266 6267struct mlx5_ifc_destroy_eq_in_bits { 6268 u8 opcode[0x10]; 6269 u8 reserved_0[0x10]; 6270 6271 u8 reserved_1[0x10]; 6272 u8 op_mod[0x10]; 6273 6274 u8 reserved_2[0x18]; 6275 u8 eq_number[0x8]; 6276 6277 u8 reserved_3[0x20]; 6278}; 6279 6280struct mlx5_ifc_destroy_dct_out_bits { 6281 u8 status[0x8]; 6282 u8 reserved_0[0x18]; 6283 6284 u8 syndrome[0x20]; 6285 6286 u8 reserved_1[0x40]; 6287}; 6288 6289struct mlx5_ifc_destroy_dct_in_bits { 6290 u8 opcode[0x10]; 6291 u8 reserved_0[0x10]; 6292 6293 u8 reserved_1[0x10]; 6294 u8 op_mod[0x10]; 6295 6296 u8 reserved_2[0x8]; 6297 u8 dctn[0x18]; 6298 6299 u8 reserved_3[0x20]; 6300}; 6301 6302struct mlx5_ifc_destroy_cq_out_bits { 6303 u8 status[0x8]; 6304 u8 reserved_0[0x18]; 6305 6306 u8 syndrome[0x20]; 6307 6308 u8 reserved_1[0x40]; 6309}; 6310 6311struct mlx5_ifc_destroy_cq_in_bits { 6312 u8 opcode[0x10]; 6313 u8 reserved_0[0x10]; 6314 6315 u8 reserved_1[0x10]; 6316 u8 op_mod[0x10]; 6317 6318 u8 reserved_2[0x8]; 6319 u8 cqn[0x18]; 6320 6321 u8 reserved_3[0x20]; 6322}; 6323 6324struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6325 u8 status[0x8]; 6326 u8 reserved_0[0x18]; 6327 6328 u8 syndrome[0x20]; 6329 6330 u8 reserved_1[0x40]; 6331}; 6332 6333struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6334 u8 opcode[0x10]; 6335 u8 reserved_0[0x10]; 6336 6337 u8 reserved_1[0x10]; 6338 u8 op_mod[0x10]; 6339 6340 u8 reserved_2[0x20]; 6341 6342 u8 reserved_3[0x10]; 6343 u8 vxlan_udp_port[0x10]; 6344}; 6345 6346struct mlx5_ifc_delete_l2_table_entry_out_bits { 6347 u8 status[0x8]; 6348 u8 reserved_0[0x18]; 6349 6350 u8 syndrome[0x20]; 6351 6352 u8 reserved_1[0x40]; 6353}; 6354 6355struct mlx5_ifc_delete_l2_table_entry_in_bits { 6356 u8 opcode[0x10]; 6357 u8 reserved_0[0x10]; 6358 6359 u8 reserved_1[0x10]; 6360 u8 op_mod[0x10]; 6361 6362 u8 reserved_2[0x60]; 6363 6364 u8 reserved_3[0x8]; 6365 u8 table_index[0x18]; 6366 6367 u8 reserved_4[0x140]; 6368}; 6369 6370struct mlx5_ifc_delete_fte_out_bits { 6371 u8 status[0x8]; 6372 u8 reserved_0[0x18]; 6373 6374 u8 syndrome[0x20]; 6375 6376 u8 reserved_1[0x40]; 6377}; 6378 6379struct mlx5_ifc_delete_fte_in_bits { 6380 u8 opcode[0x10]; 6381 u8 reserved_0[0x10]; 6382 6383 u8 reserved_1[0x10]; 6384 u8 op_mod[0x10]; 6385 6386 u8 other_vport[0x1]; 6387 u8 reserved_2[0xf]; 6388 u8 vport_number[0x10]; 6389 6390 u8 reserved_3[0x20]; 6391 6392 u8 table_type[0x8]; 6393 u8 reserved_4[0x18]; 6394 6395 u8 reserved_5[0x8]; 6396 u8 table_id[0x18]; 6397 6398 u8 reserved_6[0x40]; 6399 6400 u8 flow_index[0x20]; 6401 6402 u8 reserved_7[0xe0]; 6403}; 6404 6405struct mlx5_ifc_dealloc_xrcd_out_bits { 6406 u8 status[0x8]; 6407 u8 reserved_0[0x18]; 6408 6409 u8 syndrome[0x20]; 6410 6411 u8 reserved_1[0x40]; 6412}; 6413 6414struct mlx5_ifc_dealloc_xrcd_in_bits { 6415 u8 opcode[0x10]; 6416 u8 reserved_0[0x10]; 6417 6418 u8 reserved_1[0x10]; 6419 u8 op_mod[0x10]; 6420 6421 u8 reserved_2[0x8]; 6422 u8 xrcd[0x18]; 6423 6424 u8 reserved_3[0x20]; 6425}; 6426 6427struct mlx5_ifc_dealloc_uar_out_bits { 6428 u8 status[0x8]; 6429 u8 reserved_0[0x18]; 6430 6431 u8 syndrome[0x20]; 6432 6433 u8 reserved_1[0x40]; 6434}; 6435 6436struct mlx5_ifc_dealloc_uar_in_bits { 6437 u8 opcode[0x10]; 6438 u8 reserved_0[0x10]; 6439 6440 u8 reserved_1[0x10]; 6441 u8 op_mod[0x10]; 6442 6443 u8 reserved_2[0x8]; 6444 u8 uar[0x18]; 6445 6446 u8 reserved_3[0x20]; 6447}; 6448 6449struct mlx5_ifc_dealloc_transport_domain_out_bits { 6450 u8 status[0x8]; 6451 u8 reserved_0[0x18]; 6452 6453 u8 syndrome[0x20]; 6454 6455 u8 reserved_1[0x40]; 6456}; 6457 6458struct mlx5_ifc_dealloc_transport_domain_in_bits { 6459 u8 opcode[0x10]; 6460 u8 reserved_0[0x10]; 6461 6462 u8 reserved_1[0x10]; 6463 u8 op_mod[0x10]; 6464 6465 u8 reserved_2[0x8]; 6466 u8 transport_domain[0x18]; 6467 6468 u8 reserved_3[0x20]; 6469}; 6470 6471struct mlx5_ifc_dealloc_q_counter_out_bits { 6472 u8 status[0x8]; 6473 u8 reserved_0[0x18]; 6474 6475 u8 syndrome[0x20]; 6476 6477 u8 reserved_1[0x40]; 6478}; 6479 6480struct mlx5_ifc_counter_id_bits { 6481 u8 reserved[0x10]; 6482 u8 counter_id[0x10]; 6483}; 6484 6485struct mlx5_ifc_diagnostic_params_context_bits { 6486 u8 num_of_counters[0x10]; 6487 u8 reserved_2[0x8]; 6488 u8 log_num_of_samples[0x8]; 6489 6490 u8 single[0x1]; 6491 u8 repetitive[0x1]; 6492 u8 sync[0x1]; 6493 u8 clear[0x1]; 6494 u8 on_demand[0x1]; 6495 u8 enable[0x1]; 6496 u8 reserved_3[0x12]; 6497 u8 log_sample_period[0x8]; 6498 6499 u8 reserved_4[0x80]; 6500 6501 struct mlx5_ifc_counter_id_bits counter_id[0]; 6502}; 6503 6504struct mlx5_ifc_set_diagnostic_params_in_bits { 6505 u8 opcode[0x10]; 6506 u8 reserved_0[0x10]; 6507 6508 u8 reserved_1[0x10]; 6509 u8 op_mod[0x10]; 6510 6511 struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx; 6512}; 6513 6514struct mlx5_ifc_set_diagnostic_params_out_bits { 6515 u8 status[0x8]; 6516 u8 reserved_0[0x18]; 6517 6518 u8 syndrome[0x20]; 6519 6520 u8 reserved_1[0x40]; 6521}; 6522 6523struct mlx5_ifc_query_diagnostic_counters_in_bits { 6524 u8 opcode[0x10]; 6525 u8 reserved_0[0x10]; 6526 6527 u8 reserved_1[0x10]; 6528 u8 op_mod[0x10]; 6529 6530 u8 num_of_samples[0x10]; 6531 u8 sample_index[0x10]; 6532 6533 u8 reserved_2[0x20]; 6534}; 6535 6536struct mlx5_ifc_diagnostic_counter_bits { 6537 u8 counter_id[0x10]; 6538 u8 sample_id[0x10]; 6539 6540 u8 time_stamp_31_0[0x20]; 6541 6542 u8 counter_value_h[0x20]; 6543 6544 u8 counter_value_l[0x20]; 6545}; 6546 6547struct mlx5_ifc_query_diagnostic_counters_out_bits { 6548 u8 status[0x8]; 6549 u8 reserved_0[0x18]; 6550 6551 u8 syndrome[0x20]; 6552 6553 u8 reserved_1[0x40]; 6554 6555 struct mlx5_ifc_diagnostic_counter_bits diag_counter[0]; 6556}; 6557 6558struct mlx5_ifc_dealloc_q_counter_in_bits { 6559 u8 opcode[0x10]; 6560 u8 reserved_0[0x10]; 6561 6562 u8 reserved_1[0x10]; 6563 u8 op_mod[0x10]; 6564 6565 u8 reserved_2[0x18]; 6566 u8 counter_set_id[0x8]; 6567 6568 u8 reserved_3[0x20]; 6569}; 6570 6571struct mlx5_ifc_dealloc_pd_out_bits { 6572 u8 status[0x8]; 6573 u8 reserved_0[0x18]; 6574 6575 u8 syndrome[0x20]; 6576 6577 u8 reserved_1[0x40]; 6578}; 6579 6580struct mlx5_ifc_dealloc_pd_in_bits { 6581 u8 opcode[0x10]; 6582 u8 reserved_0[0x10]; 6583 6584 u8 reserved_1[0x10]; 6585 u8 op_mod[0x10]; 6586 6587 u8 reserved_2[0x8]; 6588 u8 pd[0x18]; 6589 6590 u8 reserved_3[0x20]; 6591}; 6592 6593struct mlx5_ifc_dealloc_flow_counter_out_bits { 6594 u8 status[0x8]; 6595 u8 reserved_0[0x18]; 6596 6597 u8 syndrome[0x20]; 6598 6599 u8 reserved_1[0x40]; 6600}; 6601 6602struct mlx5_ifc_dealloc_flow_counter_in_bits { 6603 u8 opcode[0x10]; 6604 u8 reserved_0[0x10]; 6605 6606 u8 reserved_1[0x10]; 6607 u8 op_mod[0x10]; 6608 6609 u8 reserved_2[0x10]; 6610 u8 flow_counter_id[0x10]; 6611 6612 u8 reserved_3[0x20]; 6613}; 6614 6615struct mlx5_ifc_deactivate_tracer_out_bits { 6616 u8 status[0x8]; 6617 u8 reserved_0[0x18]; 6618 6619 u8 syndrome[0x20]; 6620 6621 u8 reserved_1[0x40]; 6622}; 6623 6624struct mlx5_ifc_deactivate_tracer_in_bits { 6625 u8 opcode[0x10]; 6626 u8 reserved_0[0x10]; 6627 6628 u8 reserved_1[0x10]; 6629 u8 op_mod[0x10]; 6630 6631 u8 mkey[0x20]; 6632 6633 u8 reserved_2[0x20]; 6634}; 6635 6636struct mlx5_ifc_create_xrc_srq_out_bits { 6637 u8 status[0x8]; 6638 u8 reserved_0[0x18]; 6639 6640 u8 syndrome[0x20]; 6641 6642 u8 reserved_1[0x8]; 6643 u8 xrc_srqn[0x18]; 6644 6645 u8 reserved_2[0x20]; 6646}; 6647 6648struct mlx5_ifc_create_xrc_srq_in_bits { 6649 u8 opcode[0x10]; 6650 u8 reserved_0[0x10]; 6651 6652 u8 reserved_1[0x10]; 6653 u8 op_mod[0x10]; 6654 6655 u8 reserved_2[0x40]; 6656 6657 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6658 6659 u8 reserved_3[0x600]; 6660 6661 u8 pas[0][0x40]; 6662}; 6663 6664struct mlx5_ifc_create_tis_out_bits { 6665 u8 status[0x8]; 6666 u8 reserved_0[0x18]; 6667 6668 u8 syndrome[0x20]; 6669 6670 u8 reserved_1[0x8]; 6671 u8 tisn[0x18]; 6672 6673 u8 reserved_2[0x20]; 6674}; 6675 6676struct mlx5_ifc_create_tis_in_bits { 6677 u8 opcode[0x10]; 6678 u8 reserved_0[0x10]; 6679 6680 u8 reserved_1[0x10]; 6681 u8 op_mod[0x10]; 6682 6683 u8 reserved_2[0xc0]; 6684 6685 struct mlx5_ifc_tisc_bits ctx; 6686}; 6687 6688struct mlx5_ifc_create_tir_out_bits { 6689 u8 status[0x8]; 6690 u8 reserved_0[0x18]; 6691 6692 u8 syndrome[0x20]; 6693 6694 u8 reserved_1[0x8]; 6695 u8 tirn[0x18]; 6696 6697 u8 reserved_2[0x20]; 6698}; 6699 6700struct mlx5_ifc_create_tir_in_bits { 6701 u8 opcode[0x10]; 6702 u8 reserved_0[0x10]; 6703 6704 u8 reserved_1[0x10]; 6705 u8 op_mod[0x10]; 6706 6707 u8 reserved_2[0xc0]; 6708 6709 struct mlx5_ifc_tirc_bits tir_context; 6710}; 6711 6712struct mlx5_ifc_create_srq_out_bits { 6713 u8 status[0x8]; 6714 u8 reserved_0[0x18]; 6715 6716 u8 syndrome[0x20]; 6717 6718 u8 reserved_1[0x8]; 6719 u8 srqn[0x18]; 6720 6721 u8 reserved_2[0x20]; 6722}; 6723 6724struct mlx5_ifc_create_srq_in_bits { 6725 u8 opcode[0x10]; 6726 u8 reserved_0[0x10]; 6727 6728 u8 reserved_1[0x10]; 6729 u8 op_mod[0x10]; 6730 6731 u8 reserved_2[0x40]; 6732 6733 struct mlx5_ifc_srqc_bits srq_context_entry; 6734 6735 u8 reserved_3[0x600]; 6736 6737 u8 pas[0][0x40]; 6738}; 6739 6740struct mlx5_ifc_create_sq_out_bits { 6741 u8 status[0x8]; 6742 u8 reserved_0[0x18]; 6743 6744 u8 syndrome[0x20]; 6745 6746 u8 reserved_1[0x8]; 6747 u8 sqn[0x18]; 6748 6749 u8 reserved_2[0x20]; 6750}; 6751 6752struct mlx5_ifc_create_sq_in_bits { 6753 u8 opcode[0x10]; 6754 u8 reserved_0[0x10]; 6755 6756 u8 reserved_1[0x10]; 6757 u8 op_mod[0x10]; 6758 6759 u8 reserved_2[0xc0]; 6760 6761 struct mlx5_ifc_sqc_bits ctx; 6762}; 6763 6764struct mlx5_ifc_create_scheduling_element_out_bits { 6765 u8 status[0x8]; 6766 u8 reserved_at_8[0x18]; 6767 6768 u8 syndrome[0x20]; 6769 6770 u8 reserved_at_40[0x40]; 6771 6772 u8 scheduling_element_id[0x20]; 6773 6774 u8 reserved_at_a0[0x160]; 6775}; 6776 6777enum { 6778 MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 6779}; 6780 6781struct mlx5_ifc_create_scheduling_element_in_bits { 6782 u8 opcode[0x10]; 6783 u8 reserved_at_10[0x10]; 6784 6785 u8 reserved_at_20[0x10]; 6786 u8 op_mod[0x10]; 6787 6788 u8 scheduling_hierarchy[0x8]; 6789 u8 reserved_at_48[0x18]; 6790 6791 u8 reserved_at_60[0xa0]; 6792 6793 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6794 6795 u8 reserved_at_300[0x100]; 6796}; 6797 6798struct mlx5_ifc_create_rqt_out_bits { 6799 u8 status[0x8]; 6800 u8 reserved_0[0x18]; 6801 6802 u8 syndrome[0x20]; 6803 6804 u8 reserved_1[0x8]; 6805 u8 rqtn[0x18]; 6806 6807 u8 reserved_2[0x20]; 6808}; 6809 6810struct mlx5_ifc_create_rqt_in_bits { 6811 u8 opcode[0x10]; 6812 u8 reserved_0[0x10]; 6813 6814 u8 reserved_1[0x10]; 6815 u8 op_mod[0x10]; 6816 6817 u8 reserved_2[0xc0]; 6818 6819 struct mlx5_ifc_rqtc_bits rqt_context; 6820}; 6821 6822struct mlx5_ifc_create_rq_out_bits { 6823 u8 status[0x8]; 6824 u8 reserved_0[0x18]; 6825 6826 u8 syndrome[0x20]; 6827 6828 u8 reserved_1[0x8]; 6829 u8 rqn[0x18]; 6830 6831 u8 reserved_2[0x20]; 6832}; 6833 6834struct mlx5_ifc_create_rq_in_bits { 6835 u8 opcode[0x10]; 6836 u8 reserved_0[0x10]; 6837 6838 u8 reserved_1[0x10]; 6839 u8 op_mod[0x10]; 6840 6841 u8 reserved_2[0xc0]; 6842 6843 struct mlx5_ifc_rqc_bits ctx; 6844}; 6845 6846struct mlx5_ifc_create_rmp_out_bits { 6847 u8 status[0x8]; 6848 u8 reserved_0[0x18]; 6849 6850 u8 syndrome[0x20]; 6851 6852 u8 reserved_1[0x8]; 6853 u8 rmpn[0x18]; 6854 6855 u8 reserved_2[0x20]; 6856}; 6857 6858struct mlx5_ifc_create_rmp_in_bits { 6859 u8 opcode[0x10]; 6860 u8 reserved_0[0x10]; 6861 6862 u8 reserved_1[0x10]; 6863 u8 op_mod[0x10]; 6864 6865 u8 reserved_2[0xc0]; 6866 6867 struct mlx5_ifc_rmpc_bits ctx; 6868}; 6869 6870struct mlx5_ifc_create_qp_out_bits { 6871 u8 status[0x8]; 6872 u8 reserved_0[0x18]; 6873 6874 u8 syndrome[0x20]; 6875 6876 u8 reserved_1[0x8]; 6877 u8 qpn[0x18]; 6878 6879 u8 reserved_2[0x20]; 6880}; 6881 6882struct mlx5_ifc_create_qp_in_bits { 6883 u8 opcode[0x10]; 6884 u8 reserved_0[0x10]; 6885 6886 u8 reserved_1[0x10]; 6887 u8 op_mod[0x10]; 6888 6889 u8 reserved_2[0x8]; 6890 u8 input_qpn[0x18]; 6891 6892 u8 reserved_3[0x20]; 6893 6894 u8 opt_param_mask[0x20]; 6895 6896 u8 reserved_4[0x20]; 6897 6898 struct mlx5_ifc_qpc_bits qpc; 6899 6900 u8 reserved_5[0x80]; 6901 6902 u8 pas[0][0x40]; 6903}; 6904 6905struct mlx5_ifc_create_qos_para_vport_out_bits { 6906 u8 status[0x8]; 6907 u8 reserved_at_8[0x18]; 6908 6909 u8 syndrome[0x20]; 6910 6911 u8 reserved_at_40[0x20]; 6912 6913 u8 reserved_at_60[0x10]; 6914 u8 qos_para_vport_number[0x10]; 6915 6916 u8 reserved_at_80[0x180]; 6917}; 6918 6919struct mlx5_ifc_create_qos_para_vport_in_bits { 6920 u8 opcode[0x10]; 6921 u8 reserved_at_10[0x10]; 6922 6923 u8 reserved_at_20[0x10]; 6924 u8 op_mod[0x10]; 6925 6926 u8 reserved_at_40[0x1c0]; 6927}; 6928 6929struct mlx5_ifc_create_psv_out_bits { 6930 u8 status[0x8]; 6931 u8 reserved_0[0x18]; 6932 6933 u8 syndrome[0x20]; 6934 6935 u8 reserved_1[0x40]; 6936 6937 u8 reserved_2[0x8]; 6938 u8 psv0_index[0x18]; 6939 6940 u8 reserved_3[0x8]; 6941 u8 psv1_index[0x18]; 6942 6943 u8 reserved_4[0x8]; 6944 u8 psv2_index[0x18]; 6945 6946 u8 reserved_5[0x8]; 6947 u8 psv3_index[0x18]; 6948}; 6949 6950struct mlx5_ifc_create_psv_in_bits { 6951 u8 opcode[0x10]; 6952 u8 reserved_0[0x10]; 6953 6954 u8 reserved_1[0x10]; 6955 u8 op_mod[0x10]; 6956 6957 u8 num_psv[0x4]; 6958 u8 reserved_2[0x4]; 6959 u8 pd[0x18]; 6960 6961 u8 reserved_3[0x20]; 6962}; 6963 6964struct mlx5_ifc_create_mkey_out_bits { 6965 u8 status[0x8]; 6966 u8 reserved_0[0x18]; 6967 6968 u8 syndrome[0x20]; 6969 6970 u8 reserved_1[0x8]; 6971 u8 mkey_index[0x18]; 6972 6973 u8 reserved_2[0x20]; 6974}; 6975 6976struct mlx5_ifc_create_mkey_in_bits { 6977 u8 opcode[0x10]; 6978 u8 reserved_0[0x10]; 6979 6980 u8 reserved_1[0x10]; 6981 u8 op_mod[0x10]; 6982 6983 u8 reserved_2[0x20]; 6984 6985 u8 pg_access[0x1]; 6986 u8 reserved_3[0x1f]; 6987 6988 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6989 6990 u8 reserved_4[0x80]; 6991 6992 u8 translations_octword_actual_size[0x20]; 6993 6994 u8 reserved_5[0x560]; 6995 6996 u8 klm_pas_mtt[0][0x20]; 6997}; 6998 6999struct mlx5_ifc_create_flow_table_out_bits { 7000 u8 status[0x8]; 7001 u8 reserved_0[0x18]; 7002 7003 u8 syndrome[0x20]; 7004 7005 u8 reserved_1[0x8]; 7006 u8 table_id[0x18]; 7007 7008 u8 reserved_2[0x20]; 7009}; 7010 7011struct mlx5_ifc_create_flow_table_in_bits { 7012 u8 opcode[0x10]; 7013 u8 reserved_at_10[0x10]; 7014 7015 u8 reserved_at_20[0x10]; 7016 u8 op_mod[0x10]; 7017 7018 u8 other_vport[0x1]; 7019 u8 reserved_at_41[0xf]; 7020 u8 vport_number[0x10]; 7021 7022 u8 reserved_at_60[0x20]; 7023 7024 u8 table_type[0x8]; 7025 u8 reserved_at_88[0x18]; 7026 7027 u8 reserved_at_a0[0x20]; 7028 7029 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7030}; 7031 7032struct mlx5_ifc_create_flow_group_out_bits { 7033 u8 status[0x8]; 7034 u8 reserved_0[0x18]; 7035 7036 u8 syndrome[0x20]; 7037 7038 u8 reserved_1[0x8]; 7039 u8 group_id[0x18]; 7040 7041 u8 reserved_2[0x20]; 7042}; 7043 7044enum { 7045 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7046 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7047 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7048}; 7049 7050struct mlx5_ifc_create_flow_group_in_bits { 7051 u8 opcode[0x10]; 7052 u8 reserved_0[0x10]; 7053 7054 u8 reserved_1[0x10]; 7055 u8 op_mod[0x10]; 7056 7057 u8 other_vport[0x1]; 7058 u8 reserved_2[0xf]; 7059 u8 vport_number[0x10]; 7060 7061 u8 reserved_3[0x20]; 7062 7063 u8 table_type[0x8]; 7064 u8 reserved_4[0x18]; 7065 7066 u8 reserved_5[0x8]; 7067 u8 table_id[0x18]; 7068 7069 u8 reserved_6[0x20]; 7070 7071 u8 start_flow_index[0x20]; 7072 7073 u8 reserved_7[0x20]; 7074 7075 u8 end_flow_index[0x20]; 7076 7077 u8 reserved_8[0xa0]; 7078 7079 u8 reserved_9[0x18]; 7080 u8 match_criteria_enable[0x8]; 7081 7082 struct mlx5_ifc_fte_match_param_bits match_criteria; 7083 7084 u8 reserved_10[0xe00]; 7085}; 7086 7087struct mlx5_ifc_create_eq_out_bits { 7088 u8 status[0x8]; 7089 u8 reserved_0[0x18]; 7090 7091 u8 syndrome[0x20]; 7092 7093 u8 reserved_1[0x18]; 7094 u8 eq_number[0x8]; 7095 7096 u8 reserved_2[0x20]; 7097}; 7098 7099struct mlx5_ifc_create_eq_in_bits { 7100 u8 opcode[0x10]; 7101 u8 reserved_0[0x10]; 7102 7103 u8 reserved_1[0x10]; 7104 u8 op_mod[0x10]; 7105 7106 u8 reserved_2[0x40]; 7107 7108 struct mlx5_ifc_eqc_bits eq_context_entry; 7109 7110 u8 reserved_3[0x40]; 7111 7112 u8 event_bitmask[0x40]; 7113 7114 u8 reserved_4[0x580]; 7115 7116 u8 pas[0][0x40]; 7117}; 7118 7119struct mlx5_ifc_create_dct_out_bits { 7120 u8 status[0x8]; 7121 u8 reserved_0[0x18]; 7122 7123 u8 syndrome[0x20]; 7124 7125 u8 reserved_1[0x8]; 7126 u8 dctn[0x18]; 7127 7128 u8 reserved_2[0x20]; 7129}; 7130 7131struct mlx5_ifc_create_dct_in_bits { 7132 u8 opcode[0x10]; 7133 u8 reserved_0[0x10]; 7134 7135 u8 reserved_1[0x10]; 7136 u8 op_mod[0x10]; 7137 7138 u8 reserved_2[0x40]; 7139 7140 struct mlx5_ifc_dctc_bits dct_context_entry; 7141 7142 u8 reserved_3[0x180]; 7143}; 7144 7145struct mlx5_ifc_create_cq_out_bits { 7146 u8 status[0x8]; 7147 u8 reserved_0[0x18]; 7148 7149 u8 syndrome[0x20]; 7150 7151 u8 reserved_1[0x8]; 7152 u8 cqn[0x18]; 7153 7154 u8 reserved_2[0x20]; 7155}; 7156 7157struct mlx5_ifc_create_cq_in_bits { 7158 u8 opcode[0x10]; 7159 u8 reserved_0[0x10]; 7160 7161 u8 reserved_1[0x10]; 7162 u8 op_mod[0x10]; 7163 7164 u8 reserved_2[0x40]; 7165 7166 struct mlx5_ifc_cqc_bits cq_context; 7167 7168 u8 reserved_3[0x600]; 7169 7170 u8 pas[0][0x40]; 7171}; 7172 7173struct mlx5_ifc_config_int_moderation_out_bits { 7174 u8 status[0x8]; 7175 u8 reserved_0[0x18]; 7176 7177 u8 syndrome[0x20]; 7178 7179 u8 reserved_1[0x4]; 7180 u8 min_delay[0xc]; 7181 u8 int_vector[0x10]; 7182 7183 u8 reserved_2[0x20]; 7184}; 7185 7186enum { 7187 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7188 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7189}; 7190 7191struct mlx5_ifc_config_int_moderation_in_bits { 7192 u8 opcode[0x10]; 7193 u8 reserved_0[0x10]; 7194 7195 u8 reserved_1[0x10]; 7196 u8 op_mod[0x10]; 7197 7198 u8 reserved_2[0x4]; 7199 u8 min_delay[0xc]; 7200 u8 int_vector[0x10]; 7201 7202 u8 reserved_3[0x20]; 7203}; 7204 7205struct mlx5_ifc_attach_to_mcg_out_bits { 7206 u8 status[0x8]; 7207 u8 reserved_0[0x18]; 7208 7209 u8 syndrome[0x20]; 7210 7211 u8 reserved_1[0x40]; 7212}; 7213 7214struct mlx5_ifc_attach_to_mcg_in_bits { 7215 u8 opcode[0x10]; 7216 u8 reserved_0[0x10]; 7217 7218 u8 reserved_1[0x10]; 7219 u8 op_mod[0x10]; 7220 7221 u8 reserved_2[0x8]; 7222 u8 qpn[0x18]; 7223 7224 u8 reserved_3[0x20]; 7225 7226 u8 multicast_gid[16][0x8]; 7227}; 7228 7229struct mlx5_ifc_arm_xrc_srq_out_bits { 7230 u8 status[0x8]; 7231 u8 reserved_0[0x18]; 7232 7233 u8 syndrome[0x20]; 7234 7235 u8 reserved_1[0x40]; 7236}; 7237 7238enum { 7239 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7240}; 7241 7242struct mlx5_ifc_arm_xrc_srq_in_bits { 7243 u8 opcode[0x10]; 7244 u8 reserved_0[0x10]; 7245 7246 u8 reserved_1[0x10]; 7247 u8 op_mod[0x10]; 7248 7249 u8 reserved_2[0x8]; 7250 u8 xrc_srqn[0x18]; 7251 7252 u8 reserved_3[0x10]; 7253 u8 lwm[0x10]; 7254}; 7255 7256struct mlx5_ifc_arm_rq_out_bits { 7257 u8 status[0x8]; 7258 u8 reserved_0[0x18]; 7259 7260 u8 syndrome[0x20]; 7261 7262 u8 reserved_1[0x40]; 7263}; 7264 7265enum { 7266 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7267}; 7268 7269struct mlx5_ifc_arm_rq_in_bits { 7270 u8 opcode[0x10]; 7271 u8 reserved_0[0x10]; 7272 7273 u8 reserved_1[0x10]; 7274 u8 op_mod[0x10]; 7275 7276 u8 reserved_2[0x8]; 7277 u8 srq_number[0x18]; 7278 7279 u8 reserved_3[0x10]; 7280 u8 lwm[0x10]; 7281}; 7282 7283struct mlx5_ifc_arm_dct_out_bits { 7284 u8 status[0x8]; 7285 u8 reserved_0[0x18]; 7286 7287 u8 syndrome[0x20]; 7288 7289 u8 reserved_1[0x40]; 7290}; 7291 7292struct mlx5_ifc_arm_dct_in_bits { 7293 u8 opcode[0x10]; 7294 u8 reserved_0[0x10]; 7295 7296 u8 reserved_1[0x10]; 7297 u8 op_mod[0x10]; 7298 7299 u8 reserved_2[0x8]; 7300 u8 dctn[0x18]; 7301 7302 u8 reserved_3[0x20]; 7303}; 7304 7305struct mlx5_ifc_alloc_xrcd_out_bits { 7306 u8 status[0x8]; 7307 u8 reserved_0[0x18]; 7308 7309 u8 syndrome[0x20]; 7310 7311 u8 reserved_1[0x8]; 7312 u8 xrcd[0x18]; 7313 7314 u8 reserved_2[0x20]; 7315}; 7316 7317struct mlx5_ifc_alloc_xrcd_in_bits { 7318 u8 opcode[0x10]; 7319 u8 reserved_0[0x10]; 7320 7321 u8 reserved_1[0x10]; 7322 u8 op_mod[0x10]; 7323 7324 u8 reserved_2[0x40]; 7325}; 7326 7327struct mlx5_ifc_alloc_uar_out_bits { 7328 u8 status[0x8]; 7329 u8 reserved_0[0x18]; 7330 7331 u8 syndrome[0x20]; 7332 7333 u8 reserved_1[0x8]; 7334 u8 uar[0x18]; 7335 7336 u8 reserved_2[0x20]; 7337}; 7338 7339struct mlx5_ifc_alloc_uar_in_bits { 7340 u8 opcode[0x10]; 7341 u8 reserved_0[0x10]; 7342 7343 u8 reserved_1[0x10]; 7344 u8 op_mod[0x10]; 7345 7346 u8 reserved_2[0x40]; 7347}; 7348 7349struct mlx5_ifc_alloc_transport_domain_out_bits { 7350 u8 status[0x8]; 7351 u8 reserved_0[0x18]; 7352 7353 u8 syndrome[0x20]; 7354 7355 u8 reserved_1[0x8]; 7356 u8 transport_domain[0x18]; 7357 7358 u8 reserved_2[0x20]; 7359}; 7360 7361struct mlx5_ifc_alloc_transport_domain_in_bits { 7362 u8 opcode[0x10]; 7363 u8 reserved_0[0x10]; 7364 7365 u8 reserved_1[0x10]; 7366 u8 op_mod[0x10]; 7367 7368 u8 reserved_2[0x40]; 7369}; 7370 7371struct mlx5_ifc_alloc_q_counter_out_bits { 7372 u8 status[0x8]; 7373 u8 reserved_0[0x18]; 7374 7375 u8 syndrome[0x20]; 7376 7377 u8 reserved_1[0x18]; 7378 u8 counter_set_id[0x8]; 7379 7380 u8 reserved_2[0x20]; 7381}; 7382 7383struct mlx5_ifc_alloc_q_counter_in_bits { 7384 u8 opcode[0x10]; 7385 u8 reserved_0[0x10]; 7386 7387 u8 reserved_1[0x10]; 7388 u8 op_mod[0x10]; 7389 7390 u8 reserved_2[0x40]; 7391}; 7392 7393struct mlx5_ifc_alloc_pd_out_bits { 7394 u8 status[0x8]; 7395 u8 reserved_0[0x18]; 7396 7397 u8 syndrome[0x20]; 7398 7399 u8 reserved_1[0x8]; 7400 u8 pd[0x18]; 7401 7402 u8 reserved_2[0x20]; 7403}; 7404 7405struct mlx5_ifc_alloc_pd_in_bits { 7406 u8 opcode[0x10]; 7407 u8 reserved_0[0x10]; 7408 7409 u8 reserved_1[0x10]; 7410 u8 op_mod[0x10]; 7411 7412 u8 reserved_2[0x40]; 7413}; 7414 7415struct mlx5_ifc_alloc_flow_counter_out_bits { 7416 u8 status[0x8]; 7417 u8 reserved_0[0x18]; 7418 7419 u8 syndrome[0x20]; 7420 7421 u8 reserved_1[0x10]; 7422 u8 flow_counter_id[0x10]; 7423 7424 u8 reserved_2[0x20]; 7425}; 7426 7427struct mlx5_ifc_alloc_flow_counter_in_bits { 7428 u8 opcode[0x10]; 7429 u8 reserved_0[0x10]; 7430 7431 u8 reserved_1[0x10]; 7432 u8 op_mod[0x10]; 7433 7434 u8 reserved_2[0x40]; 7435}; 7436 7437struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7438 u8 status[0x8]; 7439 u8 reserved_0[0x18]; 7440 7441 u8 syndrome[0x20]; 7442 7443 u8 reserved_1[0x40]; 7444}; 7445 7446struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7447 u8 opcode[0x10]; 7448 u8 reserved_0[0x10]; 7449 7450 u8 reserved_1[0x10]; 7451 u8 op_mod[0x10]; 7452 7453 u8 reserved_2[0x20]; 7454 7455 u8 reserved_3[0x10]; 7456 u8 vxlan_udp_port[0x10]; 7457}; 7458 7459struct mlx5_ifc_activate_tracer_out_bits { 7460 u8 status[0x8]; 7461 u8 reserved_0[0x18]; 7462 7463 u8 syndrome[0x20]; 7464 7465 u8 reserved_1[0x40]; 7466}; 7467 7468struct mlx5_ifc_activate_tracer_in_bits { 7469 u8 opcode[0x10]; 7470 u8 reserved_0[0x10]; 7471 7472 u8 reserved_1[0x10]; 7473 u8 op_mod[0x10]; 7474 7475 u8 mkey[0x20]; 7476 7477 u8 reserved_2[0x20]; 7478}; 7479 7480struct mlx5_ifc_set_rate_limit_out_bits { 7481 u8 status[0x8]; 7482 u8 reserved_at_8[0x18]; 7483 7484 u8 syndrome[0x20]; 7485 7486 u8 reserved_at_40[0x40]; 7487}; 7488 7489struct mlx5_ifc_set_rate_limit_in_bits { 7490 u8 opcode[0x10]; 7491 u8 reserved_at_10[0x10]; 7492 7493 u8 reserved_at_20[0x10]; 7494 u8 op_mod[0x10]; 7495 7496 u8 reserved_at_40[0x10]; 7497 u8 rate_limit_index[0x10]; 7498 7499 u8 reserved_at_60[0x20]; 7500 7501 u8 rate_limit[0x20]; 7502 u8 burst_upper_bound[0x20]; 7503}; 7504 7505struct mlx5_ifc_access_register_out_bits { 7506 u8 status[0x8]; 7507 u8 reserved_0[0x18]; 7508 7509 u8 syndrome[0x20]; 7510 7511 u8 reserved_1[0x40]; 7512 7513 u8 register_data[0][0x20]; 7514}; 7515 7516enum { 7517 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7518 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7519}; 7520 7521struct mlx5_ifc_access_register_in_bits { 7522 u8 opcode[0x10]; 7523 u8 reserved_0[0x10]; 7524 7525 u8 reserved_1[0x10]; 7526 u8 op_mod[0x10]; 7527 7528 u8 reserved_2[0x10]; 7529 u8 register_id[0x10]; 7530 7531 u8 argument[0x20]; 7532 7533 u8 register_data[0][0x20]; 7534}; 7535 7536struct mlx5_ifc_sltp_reg_bits { 7537 u8 status[0x4]; 7538 u8 version[0x4]; 7539 u8 local_port[0x8]; 7540 u8 pnat[0x2]; 7541 u8 reserved_0[0x2]; 7542 u8 lane[0x4]; 7543 u8 reserved_1[0x8]; 7544 7545 u8 reserved_2[0x20]; 7546 7547 u8 reserved_3[0x7]; 7548 u8 polarity[0x1]; 7549 u8 ob_tap0[0x8]; 7550 u8 ob_tap1[0x8]; 7551 u8 ob_tap2[0x8]; 7552 7553 u8 reserved_4[0xc]; 7554 u8 ob_preemp_mode[0x4]; 7555 u8 ob_reg[0x8]; 7556 u8 ob_bias[0x8]; 7557 7558 u8 reserved_5[0x20]; 7559}; 7560 7561struct mlx5_ifc_slrp_reg_bits { 7562 u8 status[0x4]; 7563 u8 version[0x4]; 7564 u8 local_port[0x8]; 7565 u8 pnat[0x2]; 7566 u8 reserved_0[0x2]; 7567 u8 lane[0x4]; 7568 u8 reserved_1[0x8]; 7569 7570 u8 ib_sel[0x2]; 7571 u8 reserved_2[0x11]; 7572 u8 dp_sel[0x1]; 7573 u8 dp90sel[0x4]; 7574 u8 mix90phase[0x8]; 7575 7576 u8 ffe_tap0[0x8]; 7577 u8 ffe_tap1[0x8]; 7578 u8 ffe_tap2[0x8]; 7579 u8 ffe_tap3[0x8]; 7580 7581 u8 ffe_tap4[0x8]; 7582 u8 ffe_tap5[0x8]; 7583 u8 ffe_tap6[0x8]; 7584 u8 ffe_tap7[0x8]; 7585 7586 u8 ffe_tap8[0x8]; 7587 u8 mixerbias_tap_amp[0x8]; 7588 u8 reserved_3[0x7]; 7589 u8 ffe_tap_en[0x9]; 7590 7591 u8 ffe_tap_offset0[0x8]; 7592 u8 ffe_tap_offset1[0x8]; 7593 u8 slicer_offset0[0x10]; 7594 7595 u8 mixer_offset0[0x10]; 7596 u8 mixer_offset1[0x10]; 7597 7598 u8 mixerbgn_inp[0x8]; 7599 u8 mixerbgn_inn[0x8]; 7600 u8 mixerbgn_refp[0x8]; 7601 u8 mixerbgn_refn[0x8]; 7602 7603 u8 sel_slicer_lctrl_h[0x1]; 7604 u8 sel_slicer_lctrl_l[0x1]; 7605 u8 reserved_4[0x1]; 7606 u8 ref_mixer_vreg[0x5]; 7607 u8 slicer_gctrl[0x8]; 7608 u8 lctrl_input[0x8]; 7609 u8 mixer_offset_cm1[0x8]; 7610 7611 u8 common_mode[0x6]; 7612 u8 reserved_5[0x1]; 7613 u8 mixer_offset_cm0[0x9]; 7614 u8 reserved_6[0x7]; 7615 u8 slicer_offset_cm[0x9]; 7616}; 7617 7618struct mlx5_ifc_slrg_reg_bits { 7619 u8 status[0x4]; 7620 u8 version[0x4]; 7621 u8 local_port[0x8]; 7622 u8 pnat[0x2]; 7623 u8 reserved_0[0x2]; 7624 u8 lane[0x4]; 7625 u8 reserved_1[0x8]; 7626 7627 u8 time_to_link_up[0x10]; 7628 u8 reserved_2[0xc]; 7629 u8 grade_lane_speed[0x4]; 7630 7631 u8 grade_version[0x8]; 7632 u8 grade[0x18]; 7633 7634 u8 reserved_3[0x4]; 7635 u8 height_grade_type[0x4]; 7636 u8 height_grade[0x18]; 7637 7638 u8 height_dz[0x10]; 7639 u8 height_dv[0x10]; 7640 7641 u8 reserved_4[0x10]; 7642 u8 height_sigma[0x10]; 7643 7644 u8 reserved_5[0x20]; 7645 7646 u8 reserved_6[0x4]; 7647 u8 phase_grade_type[0x4]; 7648 u8 phase_grade[0x18]; 7649 7650 u8 reserved_7[0x8]; 7651 u8 phase_eo_pos[0x8]; 7652 u8 reserved_8[0x8]; 7653 u8 phase_eo_neg[0x8]; 7654 7655 u8 ffe_set_tested[0x10]; 7656 u8 test_errors_per_lane[0x10]; 7657}; 7658 7659struct mlx5_ifc_pvlc_reg_bits { 7660 u8 reserved_0[0x8]; 7661 u8 local_port[0x8]; 7662 u8 reserved_1[0x10]; 7663 7664 u8 reserved_2[0x1c]; 7665 u8 vl_hw_cap[0x4]; 7666 7667 u8 reserved_3[0x1c]; 7668 u8 vl_admin[0x4]; 7669 7670 u8 reserved_4[0x1c]; 7671 u8 vl_operational[0x4]; 7672}; 7673 7674struct mlx5_ifc_pude_reg_bits { 7675 u8 swid[0x8]; 7676 u8 local_port[0x8]; 7677 u8 reserved_0[0x4]; 7678 u8 admin_status[0x4]; 7679 u8 reserved_1[0x4]; 7680 u8 oper_status[0x4]; 7681 7682 u8 reserved_2[0x60]; 7683}; 7684 7685enum { 7686 MLX5_PTYS_REG_PROTO_MASK_INFINIBAND = 0x1, 7687 MLX5_PTYS_REG_PROTO_MASK_ETHERNET = 0x4, 7688}; 7689 7690struct mlx5_ifc_ptys_reg_bits { 7691 u8 reserved_0[0x1]; 7692 u8 an_disable_admin[0x1]; 7693 u8 an_disable_cap[0x1]; 7694 u8 reserved_1[0x4]; 7695 u8 force_tx_aba_param[0x1]; 7696 u8 local_port[0x8]; 7697 u8 reserved_2[0xd]; 7698 u8 proto_mask[0x3]; 7699 7700 u8 an_status[0x4]; 7701 u8 reserved_3[0xc]; 7702 u8 data_rate_oper[0x10]; 7703 7704 u8 fc_proto_capability[0x20]; 7705 7706 u8 eth_proto_capability[0x20]; 7707 7708 u8 ib_link_width_capability[0x10]; 7709 u8 ib_proto_capability[0x10]; 7710 7711 u8 fc_proto_admin[0x20]; 7712 7713 u8 eth_proto_admin[0x20]; 7714 7715 u8 ib_link_width_admin[0x10]; 7716 u8 ib_proto_admin[0x10]; 7717 7718 u8 fc_proto_oper[0x20]; 7719 7720 u8 eth_proto_oper[0x20]; 7721 7722 u8 ib_link_width_oper[0x10]; 7723 u8 ib_proto_oper[0x10]; 7724 7725 u8 reserved_4[0x20]; 7726 7727 u8 eth_proto_lp_advertise[0x20]; 7728 7729 u8 reserved_5[0x60]; 7730}; 7731 7732struct mlx5_ifc_ptas_reg_bits { 7733 u8 reserved_0[0x20]; 7734 7735 u8 algorithm_options[0x10]; 7736 u8 reserved_1[0x4]; 7737 u8 repetitions_mode[0x4]; 7738 u8 num_of_repetitions[0x8]; 7739 7740 u8 grade_version[0x8]; 7741 u8 height_grade_type[0x4]; 7742 u8 phase_grade_type[0x4]; 7743 u8 height_grade_weight[0x8]; 7744 u8 phase_grade_weight[0x8]; 7745 7746 u8 gisim_measure_bits[0x10]; 7747 u8 adaptive_tap_measure_bits[0x10]; 7748 7749 u8 ber_bath_high_error_threshold[0x10]; 7750 u8 ber_bath_mid_error_threshold[0x10]; 7751 7752 u8 ber_bath_low_error_threshold[0x10]; 7753 u8 one_ratio_high_threshold[0x10]; 7754 7755 u8 one_ratio_high_mid_threshold[0x10]; 7756 u8 one_ratio_low_mid_threshold[0x10]; 7757 7758 u8 one_ratio_low_threshold[0x10]; 7759 u8 ndeo_error_threshold[0x10]; 7760 7761 u8 mixer_offset_step_size[0x10]; 7762 u8 reserved_2[0x8]; 7763 u8 mix90_phase_for_voltage_bath[0x8]; 7764 7765 u8 mixer_offset_start[0x10]; 7766 u8 mixer_offset_end[0x10]; 7767 7768 u8 reserved_3[0x15]; 7769 u8 ber_test_time[0xb]; 7770}; 7771 7772struct mlx5_ifc_pspa_reg_bits { 7773 u8 swid[0x8]; 7774 u8 local_port[0x8]; 7775 u8 sub_port[0x8]; 7776 u8 reserved_0[0x8]; 7777 7778 u8 reserved_1[0x20]; 7779}; 7780 7781struct mlx5_ifc_ppsc_reg_bits { 7782 u8 reserved_0[0x8]; 7783 u8 local_port[0x8]; 7784 u8 reserved_1[0x10]; 7785 7786 u8 reserved_2[0x60]; 7787 7788 u8 reserved_3[0x1c]; 7789 u8 wrps_admin[0x4]; 7790 7791 u8 reserved_4[0x1c]; 7792 u8 wrps_status[0x4]; 7793 7794 u8 up_th_vld[0x1]; 7795 u8 down_th_vld[0x1]; 7796 u8 reserved_5[0x6]; 7797 u8 up_threshold[0x8]; 7798 u8 reserved_6[0x8]; 7799 u8 down_threshold[0x8]; 7800 7801 u8 reserved_7[0x20]; 7802 7803 u8 reserved_8[0x1c]; 7804 u8 srps_admin[0x4]; 7805 7806 u8 reserved_9[0x60]; 7807}; 7808 7809struct mlx5_ifc_pplr_reg_bits { 7810 u8 reserved_0[0x8]; 7811 u8 local_port[0x8]; 7812 u8 reserved_1[0x10]; 7813 7814 u8 reserved_2[0x8]; 7815 u8 lb_cap[0x8]; 7816 u8 reserved_3[0x8]; 7817 u8 lb_en[0x8]; 7818}; 7819 7820struct mlx5_ifc_pplm_reg_bits { 7821 u8 reserved_0[0x8]; 7822 u8 local_port[0x8]; 7823 u8 reserved_1[0x10]; 7824 7825 u8 reserved_2[0x20]; 7826 7827 u8 port_profile_mode[0x8]; 7828 u8 static_port_profile[0x8]; 7829 u8 active_port_profile[0x8]; 7830 u8 reserved_3[0x8]; 7831 7832 u8 retransmission_active[0x8]; 7833 u8 fec_mode_active[0x18]; 7834 7835 u8 reserved_4[0x10]; 7836 u8 v_100g_fec_override_cap[0x4]; 7837 u8 v_50g_fec_override_cap[0x4]; 7838 u8 v_25g_fec_override_cap[0x4]; 7839 u8 v_10g_40g_fec_override_cap[0x4]; 7840 7841 u8 reserved_5[0x10]; 7842 u8 v_100g_fec_override_admin[0x4]; 7843 u8 v_50g_fec_override_admin[0x4]; 7844 u8 v_25g_fec_override_admin[0x4]; 7845 u8 v_10g_40g_fec_override_admin[0x4]; 7846}; 7847 7848struct mlx5_ifc_ppll_reg_bits { 7849 u8 num_pll_groups[0x8]; 7850 u8 pll_group[0x8]; 7851 u8 reserved_0[0x4]; 7852 u8 num_plls[0x4]; 7853 u8 reserved_1[0x8]; 7854 7855 u8 reserved_2[0x1f]; 7856 u8 ae[0x1]; 7857 7858 u8 pll_status[4][0x40]; 7859}; 7860 7861struct mlx5_ifc_ppad_reg_bits { 7862 u8 reserved_0[0x3]; 7863 u8 single_mac[0x1]; 7864 u8 reserved_1[0x4]; 7865 u8 local_port[0x8]; 7866 u8 mac_47_32[0x10]; 7867 7868 u8 mac_31_0[0x20]; 7869 7870 u8 reserved_2[0x40]; 7871}; 7872 7873struct mlx5_ifc_pmtu_reg_bits { 7874 u8 reserved_0[0x8]; 7875 u8 local_port[0x8]; 7876 u8 reserved_1[0x10]; 7877 7878 u8 max_mtu[0x10]; 7879 u8 reserved_2[0x10]; 7880 7881 u8 admin_mtu[0x10]; 7882 u8 reserved_3[0x10]; 7883 7884 u8 oper_mtu[0x10]; 7885 u8 reserved_4[0x10]; 7886}; 7887 7888struct mlx5_ifc_pmpr_reg_bits { 7889 u8 reserved_0[0x8]; 7890 u8 module[0x8]; 7891 u8 reserved_1[0x10]; 7892 7893 u8 reserved_2[0x18]; 7894 u8 attenuation_5g[0x8]; 7895 7896 u8 reserved_3[0x18]; 7897 u8 attenuation_7g[0x8]; 7898 7899 u8 reserved_4[0x18]; 7900 u8 attenuation_12g[0x8]; 7901}; 7902 7903struct mlx5_ifc_pmpe_reg_bits { 7904 u8 reserved_0[0x8]; 7905 u8 module[0x8]; 7906 u8 reserved_1[0xc]; 7907 u8 module_status[0x4]; 7908 7909 u8 reserved_2[0x14]; 7910 u8 error_type[0x4]; 7911 u8 reserved_3[0x8]; 7912 7913 u8 reserved_4[0x40]; 7914}; 7915 7916struct mlx5_ifc_pmpc_reg_bits { 7917 u8 module_state_updated[32][0x8]; 7918}; 7919 7920struct mlx5_ifc_pmlpn_reg_bits { 7921 u8 reserved_0[0x4]; 7922 u8 mlpn_status[0x4]; 7923 u8 local_port[0x8]; 7924 u8 reserved_1[0x10]; 7925 7926 u8 e[0x1]; 7927 u8 reserved_2[0x1f]; 7928}; 7929 7930struct mlx5_ifc_pmlp_reg_bits { 7931 u8 rxtx[0x1]; 7932 u8 reserved_0[0x7]; 7933 u8 local_port[0x8]; 7934 u8 reserved_1[0x8]; 7935 u8 width[0x8]; 7936 7937 u8 lane0_module_mapping[0x20]; 7938 7939 u8 lane1_module_mapping[0x20]; 7940 7941 u8 lane2_module_mapping[0x20]; 7942 7943 u8 lane3_module_mapping[0x20]; 7944 7945 u8 reserved_2[0x160]; 7946}; 7947 7948struct mlx5_ifc_pmaos_reg_bits { 7949 u8 reserved_0[0x8]; 7950 u8 module[0x8]; 7951 u8 reserved_1[0x4]; 7952 u8 admin_status[0x4]; 7953 u8 reserved_2[0x4]; 7954 u8 oper_status[0x4]; 7955 7956 u8 ase[0x1]; 7957 u8 ee[0x1]; 7958 u8 reserved_3[0x12]; 7959 u8 error_type[0x4]; 7960 u8 reserved_4[0x6]; 7961 u8 e[0x2]; 7962 7963 u8 reserved_5[0x40]; 7964}; 7965 7966struct mlx5_ifc_plpc_reg_bits { 7967 u8 reserved_0[0x4]; 7968 u8 profile_id[0xc]; 7969 u8 reserved_1[0x4]; 7970 u8 proto_mask[0x4]; 7971 u8 reserved_2[0x8]; 7972 7973 u8 reserved_3[0x10]; 7974 u8 lane_speed[0x10]; 7975 7976 u8 reserved_4[0x17]; 7977 u8 lpbf[0x1]; 7978 u8 fec_mode_policy[0x8]; 7979 7980 u8 retransmission_capability[0x8]; 7981 u8 fec_mode_capability[0x18]; 7982 7983 u8 retransmission_support_admin[0x8]; 7984 u8 fec_mode_support_admin[0x18]; 7985 7986 u8 retransmission_request_admin[0x8]; 7987 u8 fec_mode_request_admin[0x18]; 7988 7989 u8 reserved_5[0x80]; 7990}; 7991 7992struct mlx5_ifc_pll_status_data_bits { 7993 u8 reserved_0[0x1]; 7994 u8 lock_cal[0x1]; 7995 u8 lock_status[0x2]; 7996 u8 reserved_1[0x2]; 7997 u8 algo_f_ctrl[0xa]; 7998 u8 analog_algo_num_var[0x6]; 7999 u8 f_ctrl_measure[0xa]; 8000 8001 u8 reserved_2[0x2]; 8002 u8 analog_var[0x6]; 8003 u8 reserved_3[0x2]; 8004 u8 high_var[0x6]; 8005 u8 reserved_4[0x2]; 8006 u8 low_var[0x6]; 8007 u8 reserved_5[0x2]; 8008 u8 mid_val[0x6]; 8009}; 8010 8011struct mlx5_ifc_plib_reg_bits { 8012 u8 reserved_0[0x8]; 8013 u8 local_port[0x8]; 8014 u8 reserved_1[0x8]; 8015 u8 ib_port[0x8]; 8016 8017 u8 reserved_2[0x60]; 8018}; 8019 8020struct mlx5_ifc_plbf_reg_bits { 8021 u8 reserved_0[0x8]; 8022 u8 local_port[0x8]; 8023 u8 reserved_1[0xd]; 8024 u8 lbf_mode[0x3]; 8025 8026 u8 reserved_2[0x20]; 8027}; 8028 8029struct mlx5_ifc_pipg_reg_bits { 8030 u8 reserved_0[0x8]; 8031 u8 local_port[0x8]; 8032 u8 reserved_1[0x10]; 8033 8034 u8 dic[0x1]; 8035 u8 reserved_2[0x19]; 8036 u8 ipg[0x4]; 8037 u8 reserved_3[0x2]; 8038}; 8039 8040struct mlx5_ifc_pifr_reg_bits { 8041 u8 reserved_0[0x8]; 8042 u8 local_port[0x8]; 8043 u8 reserved_1[0x10]; 8044 8045 u8 reserved_2[0xe0]; 8046 8047 u8 port_filter[8][0x20]; 8048 8049 u8 port_filter_update_en[8][0x20]; 8050}; 8051 8052struct mlx5_ifc_phys_layer_cntrs_bits { 8053 u8 time_since_last_clear_high[0x20]; 8054 8055 u8 time_since_last_clear_low[0x20]; 8056 8057 u8 symbol_errors_high[0x20]; 8058 8059 u8 symbol_errors_low[0x20]; 8060 8061 u8 sync_headers_errors_high[0x20]; 8062 8063 u8 sync_headers_errors_low[0x20]; 8064 8065 u8 edpl_bip_errors_lane0_high[0x20]; 8066 8067 u8 edpl_bip_errors_lane0_low[0x20]; 8068 8069 u8 edpl_bip_errors_lane1_high[0x20]; 8070 8071 u8 edpl_bip_errors_lane1_low[0x20]; 8072 8073 u8 edpl_bip_errors_lane2_high[0x20]; 8074 8075 u8 edpl_bip_errors_lane2_low[0x20]; 8076 8077 u8 edpl_bip_errors_lane3_high[0x20]; 8078 8079 u8 edpl_bip_errors_lane3_low[0x20]; 8080 8081 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 8082 8083 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 8084 8085 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 8086 8087 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 8088 8089 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 8090 8091 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 8092 8093 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 8094 8095 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 8096 8097 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 8098 8099 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 8100 8101 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 8102 8103 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 8104 8105 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 8106 8107 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 8108 8109 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 8110 8111 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 8112 8113 u8 rs_fec_corrected_blocks_high[0x20]; 8114 8115 u8 rs_fec_corrected_blocks_low[0x20]; 8116 8117 u8 rs_fec_uncorrectable_blocks_high[0x20]; 8118 8119 u8 rs_fec_uncorrectable_blocks_low[0x20]; 8120 8121 u8 rs_fec_no_errors_blocks_high[0x20]; 8122 8123 u8 rs_fec_no_errors_blocks_low[0x20]; 8124 8125 u8 rs_fec_single_error_blocks_high[0x20]; 8126 8127 u8 rs_fec_single_error_blocks_low[0x20]; 8128 8129 u8 rs_fec_corrected_symbols_total_high[0x20]; 8130 8131 u8 rs_fec_corrected_symbols_total_low[0x20]; 8132 8133 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 8134 8135 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 8136 8137 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 8138 8139 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 8140 8141 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 8142 8143 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 8144 8145 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 8146 8147 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 8148 8149 u8 link_down_events[0x20]; 8150 8151 u8 successful_recovery_events[0x20]; 8152 8153 u8 reserved_0[0x180]; 8154}; 8155 8156struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 8157 u8 symbol_error_counter[0x10]; 8158 8159 u8 link_error_recovery_counter[0x8]; 8160 8161 u8 link_downed_counter[0x8]; 8162 8163 u8 port_rcv_errors[0x10]; 8164 8165 u8 port_rcv_remote_physical_errors[0x10]; 8166 8167 u8 port_rcv_switch_relay_errors[0x10]; 8168 8169 u8 port_xmit_discards[0x10]; 8170 8171 u8 port_xmit_constraint_errors[0x8]; 8172 8173 u8 port_rcv_constraint_errors[0x8]; 8174 8175 u8 reserved_at_70[0x8]; 8176 8177 u8 link_overrun_errors[0x8]; 8178 8179 u8 reserved_at_80[0x10]; 8180 8181 u8 vl_15_dropped[0x10]; 8182 8183 u8 reserved_at_a0[0xa0]; 8184}; 8185 8186struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 8187 u8 time_since_last_clear_high[0x20]; 8188 8189 u8 time_since_last_clear_low[0x20]; 8190 8191 u8 phy_received_bits_high[0x20]; 8192 8193 u8 phy_received_bits_low[0x20]; 8194 8195 u8 phy_symbol_errors_high[0x20]; 8196 8197 u8 phy_symbol_errors_low[0x20]; 8198 8199 u8 phy_corrected_bits_high[0x20]; 8200 8201 u8 phy_corrected_bits_low[0x20]; 8202 8203 u8 phy_corrected_bits_lane0_high[0x20]; 8204 8205 u8 phy_corrected_bits_lane0_low[0x20]; 8206 8207 u8 phy_corrected_bits_lane1_high[0x20]; 8208 8209 u8 phy_corrected_bits_lane1_low[0x20]; 8210 8211 u8 phy_corrected_bits_lane2_high[0x20]; 8212 8213 u8 phy_corrected_bits_lane2_low[0x20]; 8214 8215 u8 phy_corrected_bits_lane3_high[0x20]; 8216 8217 u8 phy_corrected_bits_lane3_low[0x20]; 8218 8219 u8 reserved_at_200[0x5c0]; 8220}; 8221 8222struct mlx5_ifc_infiniband_port_cntrs_bits { 8223 u8 symbol_error_counter[0x10]; 8224 u8 link_error_recovery_counter[0x8]; 8225 u8 link_downed_counter[0x8]; 8226 8227 u8 port_rcv_errors[0x10]; 8228 u8 port_rcv_remote_physical_errors[0x10]; 8229 8230 u8 port_rcv_switch_relay_errors[0x10]; 8231 u8 port_xmit_discards[0x10]; 8232 8233 u8 port_xmit_constraint_errors[0x8]; 8234 u8 port_rcv_constraint_errors[0x8]; 8235 u8 reserved_0[0x8]; 8236 u8 local_link_integrity_errors[0x4]; 8237 u8 excessive_buffer_overrun_errors[0x4]; 8238 8239 u8 reserved_1[0x10]; 8240 u8 vl_15_dropped[0x10]; 8241 8242 u8 port_xmit_data[0x20]; 8243 8244 u8 port_rcv_data[0x20]; 8245 8246 u8 port_xmit_pkts[0x20]; 8247 8248 u8 port_rcv_pkts[0x20]; 8249 8250 u8 port_xmit_wait[0x20]; 8251 8252 u8 reserved_2[0x680]; 8253}; 8254 8255struct mlx5_ifc_phrr_reg_bits { 8256 u8 clr[0x1]; 8257 u8 reserved_0[0x7]; 8258 u8 local_port[0x8]; 8259 u8 reserved_1[0x10]; 8260 8261 u8 hist_group[0x8]; 8262 u8 reserved_2[0x10]; 8263 u8 hist_id[0x8]; 8264 8265 u8 reserved_3[0x40]; 8266 8267 u8 time_since_last_clear_high[0x20]; 8268 8269 u8 time_since_last_clear_low[0x20]; 8270 8271 u8 bin[10][0x20]; 8272}; 8273 8274struct mlx5_ifc_phbr_for_prio_reg_bits { 8275 u8 reserved_0[0x18]; 8276 u8 prio[0x8]; 8277}; 8278 8279struct mlx5_ifc_phbr_for_port_tclass_reg_bits { 8280 u8 reserved_0[0x18]; 8281 u8 tclass[0x8]; 8282}; 8283 8284struct mlx5_ifc_phbr_binding_reg_bits { 8285 u8 opcode[0x4]; 8286 u8 reserved_0[0x4]; 8287 u8 local_port[0x8]; 8288 u8 pnat[0x2]; 8289 u8 reserved_1[0xe]; 8290 8291 u8 hist_group[0x8]; 8292 u8 reserved_2[0x10]; 8293 u8 hist_id[0x8]; 8294 8295 u8 reserved_3[0x10]; 8296 u8 hist_type[0x10]; 8297 8298 u8 hist_parameters[0x20]; 8299 8300 u8 hist_min_value[0x20]; 8301 8302 u8 hist_max_value[0x20]; 8303 8304 u8 sample_time[0x20]; 8305}; 8306 8307enum { 8308 MLX5_PFCC_REG_PPAN_DISABLED = 0x0, 8309 MLX5_PFCC_REG_PPAN_ENABLED = 0x1, 8310}; 8311 8312struct mlx5_ifc_pfcc_reg_bits { 8313 u8 dcbx_operation_type[0x2]; 8314 u8 cap_local_admin[0x1]; 8315 u8 cap_remote_admin[0x1]; 8316 u8 reserved_0[0x4]; 8317 u8 local_port[0x8]; 8318 u8 pnat[0x2]; 8319 u8 reserved_1[0xc]; 8320 u8 shl_cap[0x1]; 8321 u8 shl_opr[0x1]; 8322 8323 u8 ppan[0x4]; 8324 u8 reserved_2[0x4]; 8325 u8 prio_mask_tx[0x8]; 8326 u8 reserved_3[0x8]; 8327 u8 prio_mask_rx[0x8]; 8328 8329 u8 pptx[0x1]; 8330 u8 aptx[0x1]; 8331 u8 reserved_4[0x6]; 8332 u8 pfctx[0x8]; 8333 u8 reserved_5[0x8]; 8334 u8 cbftx[0x8]; 8335 8336 u8 pprx[0x1]; 8337 u8 aprx[0x1]; 8338 u8 reserved_6[0x6]; 8339 u8 pfcrx[0x8]; 8340 u8 reserved_7[0x8]; 8341 u8 cbfrx[0x8]; 8342 8343 u8 device_stall_minor_watermark[0x10]; 8344 u8 device_stall_critical_watermark[0x10]; 8345 8346 u8 reserved_8[0x60]; 8347}; 8348 8349struct mlx5_ifc_pelc_reg_bits { 8350 u8 op[0x4]; 8351 u8 reserved_0[0x4]; 8352 u8 local_port[0x8]; 8353 u8 reserved_1[0x10]; 8354 8355 u8 op_admin[0x8]; 8356 u8 op_capability[0x8]; 8357 u8 op_request[0x8]; 8358 u8 op_active[0x8]; 8359 8360 u8 admin[0x40]; 8361 8362 u8 capability[0x40]; 8363 8364 u8 request[0x40]; 8365 8366 u8 active[0x40]; 8367 8368 u8 reserved_2[0x80]; 8369}; 8370 8371struct mlx5_ifc_peir_reg_bits { 8372 u8 reserved_0[0x8]; 8373 u8 local_port[0x8]; 8374 u8 reserved_1[0x10]; 8375 8376 u8 reserved_2[0xc]; 8377 u8 error_count[0x4]; 8378 u8 reserved_3[0x10]; 8379 8380 u8 reserved_4[0xc]; 8381 u8 lane[0x4]; 8382 u8 reserved_5[0x8]; 8383 u8 error_type[0x8]; 8384}; 8385 8386struct mlx5_ifc_pcap_reg_bits { 8387 u8 reserved_0[0x8]; 8388 u8 local_port[0x8]; 8389 u8 reserved_1[0x10]; 8390 8391 u8 port_capability_mask[4][0x20]; 8392}; 8393 8394struct mlx5_ifc_pbmc_reg_bits { 8395 u8 reserved_0[0x8]; 8396 u8 local_port[0x8]; 8397 u8 reserved_1[0x10]; 8398 8399 u8 xoff_timer_value[0x10]; 8400 u8 xoff_refresh[0x10]; 8401 8402 u8 reserved_2[0x10]; 8403 u8 port_buffer_size[0x10]; 8404 8405 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 8406 8407 u8 reserved_3[0x40]; 8408 8409 u8 port_shared_buffer[0x40]; 8410}; 8411 8412struct mlx5_ifc_paos_reg_bits { 8413 u8 swid[0x8]; 8414 u8 local_port[0x8]; 8415 u8 reserved_0[0x4]; 8416 u8 admin_status[0x4]; 8417 u8 reserved_1[0x4]; 8418 u8 oper_status[0x4]; 8419 8420 u8 ase[0x1]; 8421 u8 ee[0x1]; 8422 u8 reserved_2[0x1c]; 8423 u8 e[0x2]; 8424 8425 u8 reserved_3[0x40]; 8426}; 8427 8428struct mlx5_ifc_pamp_reg_bits { 8429 u8 reserved_0[0x8]; 8430 u8 opamp_group[0x8]; 8431 u8 reserved_1[0xc]; 8432 u8 opamp_group_type[0x4]; 8433 8434 u8 start_index[0x10]; 8435 u8 reserved_2[0x4]; 8436 u8 num_of_indices[0xc]; 8437 8438 u8 index_data[18][0x10]; 8439}; 8440 8441struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits { 8442 u8 llr_rx_cells_high[0x20]; 8443 8444 u8 llr_rx_cells_low[0x20]; 8445 8446 u8 llr_rx_error_high[0x20]; 8447 8448 u8 llr_rx_error_low[0x20]; 8449 8450 u8 llr_rx_crc_error_high[0x20]; 8451 8452 u8 llr_rx_crc_error_low[0x20]; 8453 8454 u8 llr_tx_cells_high[0x20]; 8455 8456 u8 llr_tx_cells_low[0x20]; 8457 8458 u8 llr_tx_ret_cells_high[0x20]; 8459 8460 u8 llr_tx_ret_cells_low[0x20]; 8461 8462 u8 llr_tx_ret_events_high[0x20]; 8463 8464 u8 llr_tx_ret_events_low[0x20]; 8465 8466 u8 reserved_0[0x640]; 8467}; 8468 8469struct mlx5_ifc_lane_2_module_mapping_bits { 8470 u8 reserved_0[0x6]; 8471 u8 rx_lane[0x2]; 8472 u8 reserved_1[0x6]; 8473 u8 tx_lane[0x2]; 8474 u8 reserved_2[0x8]; 8475 u8 module[0x8]; 8476}; 8477 8478struct mlx5_ifc_eth_per_traffic_class_layout_bits { 8479 u8 transmit_queue_high[0x20]; 8480 8481 u8 transmit_queue_low[0x20]; 8482 8483 u8 reserved_0[0x780]; 8484}; 8485 8486struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits { 8487 u8 no_buffer_discard_uc_high[0x20]; 8488 8489 u8 no_buffer_discard_uc_low[0x20]; 8490 8491 u8 wred_discard_high[0x20]; 8492 8493 u8 wred_discard_low[0x20]; 8494 8495 u8 reserved_0[0x740]; 8496}; 8497 8498struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 8499 u8 rx_octets_high[0x20]; 8500 8501 u8 rx_octets_low[0x20]; 8502 8503 u8 reserved_0[0xc0]; 8504 8505 u8 rx_frames_high[0x20]; 8506 8507 u8 rx_frames_low[0x20]; 8508 8509 u8 tx_octets_high[0x20]; 8510 8511 u8 tx_octets_low[0x20]; 8512 8513 u8 reserved_1[0xc0]; 8514 8515 u8 tx_frames_high[0x20]; 8516 8517 u8 tx_frames_low[0x20]; 8518 8519 u8 rx_pause_high[0x20]; 8520 8521 u8 rx_pause_low[0x20]; 8522 8523 u8 rx_pause_duration_high[0x20]; 8524 8525 u8 rx_pause_duration_low[0x20]; 8526 8527 u8 tx_pause_high[0x20]; 8528 8529 u8 tx_pause_low[0x20]; 8530 8531 u8 tx_pause_duration_high[0x20]; 8532 8533 u8 tx_pause_duration_low[0x20]; 8534 8535 u8 rx_pause_transition_high[0x20]; 8536 8537 u8 rx_pause_transition_low[0x20]; 8538 8539 u8 rx_discards_high[0x20]; 8540 8541 u8 rx_discards_low[0x20]; 8542 8543 u8 device_stall_minor_watermark_cnt_high[0x20]; 8544 8545 u8 device_stall_minor_watermark_cnt_low[0x20]; 8546 8547 u8 device_stall_critical_watermark_cnt_high[0x20]; 8548 8549 u8 device_stall_critical_watermark_cnt_low[0x20]; 8550 8551 u8 reserved_2[0x340]; 8552}; 8553 8554struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 8555 u8 port_transmit_wait_high[0x20]; 8556 8557 u8 port_transmit_wait_low[0x20]; 8558 8559 u8 ecn_marked_high[0x20]; 8560 8561 u8 ecn_marked_low[0x20]; 8562 8563 u8 no_buffer_discard_mc_high[0x20]; 8564 8565 u8 no_buffer_discard_mc_low[0x20]; 8566 8567 u8 reserved_0[0x700]; 8568}; 8569 8570struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 8571 u8 a_frames_transmitted_ok_high[0x20]; 8572 8573 u8 a_frames_transmitted_ok_low[0x20]; 8574 8575 u8 a_frames_received_ok_high[0x20]; 8576 8577 u8 a_frames_received_ok_low[0x20]; 8578 8579 u8 a_frame_check_sequence_errors_high[0x20]; 8580 8581 u8 a_frame_check_sequence_errors_low[0x20]; 8582 8583 u8 a_alignment_errors_high[0x20]; 8584 8585 u8 a_alignment_errors_low[0x20]; 8586 8587 u8 a_octets_transmitted_ok_high[0x20]; 8588 8589 u8 a_octets_transmitted_ok_low[0x20]; 8590 8591 u8 a_octets_received_ok_high[0x20]; 8592 8593 u8 a_octets_received_ok_low[0x20]; 8594 8595 u8 a_multicast_frames_xmitted_ok_high[0x20]; 8596 8597 u8 a_multicast_frames_xmitted_ok_low[0x20]; 8598 8599 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 8600 8601 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 8602 8603 u8 a_multicast_frames_received_ok_high[0x20]; 8604 8605 u8 a_multicast_frames_received_ok_low[0x20]; 8606 8607 u8 a_broadcast_frames_recieved_ok_high[0x20]; 8608 8609 u8 a_broadcast_frames_recieved_ok_low[0x20]; 8610 8611 u8 a_in_range_length_errors_high[0x20]; 8612 8613 u8 a_in_range_length_errors_low[0x20]; 8614 8615 u8 a_out_of_range_length_field_high[0x20]; 8616 8617 u8 a_out_of_range_length_field_low[0x20]; 8618 8619 u8 a_frame_too_long_errors_high[0x20]; 8620 8621 u8 a_frame_too_long_errors_low[0x20]; 8622 8623 u8 a_symbol_error_during_carrier_high[0x20]; 8624 8625 u8 a_symbol_error_during_carrier_low[0x20]; 8626 8627 u8 a_mac_control_frames_transmitted_high[0x20]; 8628 8629 u8 a_mac_control_frames_transmitted_low[0x20]; 8630 8631 u8 a_mac_control_frames_received_high[0x20]; 8632 8633 u8 a_mac_control_frames_received_low[0x20]; 8634 8635 u8 a_unsupported_opcodes_received_high[0x20]; 8636 8637 u8 a_unsupported_opcodes_received_low[0x20]; 8638 8639 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 8640 8641 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 8642 8643 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 8644 8645 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 8646 8647 u8 reserved_0[0x300]; 8648}; 8649 8650struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 8651 u8 dot3stats_alignment_errors_high[0x20]; 8652 8653 u8 dot3stats_alignment_errors_low[0x20]; 8654 8655 u8 dot3stats_fcs_errors_high[0x20]; 8656 8657 u8 dot3stats_fcs_errors_low[0x20]; 8658 8659 u8 dot3stats_single_collision_frames_high[0x20]; 8660 8661 u8 dot3stats_single_collision_frames_low[0x20]; 8662 8663 u8 dot3stats_multiple_collision_frames_high[0x20]; 8664 8665 u8 dot3stats_multiple_collision_frames_low[0x20]; 8666 8667 u8 dot3stats_sqe_test_errors_high[0x20]; 8668 8669 u8 dot3stats_sqe_test_errors_low[0x20]; 8670 8671 u8 dot3stats_deferred_transmissions_high[0x20]; 8672 8673 u8 dot3stats_deferred_transmissions_low[0x20]; 8674 8675 u8 dot3stats_late_collisions_high[0x20]; 8676 8677 u8 dot3stats_late_collisions_low[0x20]; 8678 8679 u8 dot3stats_excessive_collisions_high[0x20]; 8680 8681 u8 dot3stats_excessive_collisions_low[0x20]; 8682 8683 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 8684 8685 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 8686 8687 u8 dot3stats_carrier_sense_errors_high[0x20]; 8688 8689 u8 dot3stats_carrier_sense_errors_low[0x20]; 8690 8691 u8 dot3stats_frame_too_longs_high[0x20]; 8692 8693 u8 dot3stats_frame_too_longs_low[0x20]; 8694 8695 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 8696 8697 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 8698 8699 u8 dot3stats_symbol_errors_high[0x20]; 8700 8701 u8 dot3stats_symbol_errors_low[0x20]; 8702 8703 u8 dot3control_in_unknown_opcodes_high[0x20]; 8704 8705 u8 dot3control_in_unknown_opcodes_low[0x20]; 8706 8707 u8 dot3in_pause_frames_high[0x20]; 8708 8709 u8 dot3in_pause_frames_low[0x20]; 8710 8711 u8 dot3out_pause_frames_high[0x20]; 8712 8713 u8 dot3out_pause_frames_low[0x20]; 8714 8715 u8 reserved_0[0x3c0]; 8716}; 8717 8718struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 8719 u8 if_in_octets_high[0x20]; 8720 8721 u8 if_in_octets_low[0x20]; 8722 8723 u8 if_in_ucast_pkts_high[0x20]; 8724 8725 u8 if_in_ucast_pkts_low[0x20]; 8726 8727 u8 if_in_discards_high[0x20]; 8728 8729 u8 if_in_discards_low[0x20]; 8730 8731 u8 if_in_errors_high[0x20]; 8732 8733 u8 if_in_errors_low[0x20]; 8734 8735 u8 if_in_unknown_protos_high[0x20]; 8736 8737 u8 if_in_unknown_protos_low[0x20]; 8738 8739 u8 if_out_octets_high[0x20]; 8740 8741 u8 if_out_octets_low[0x20]; 8742 8743 u8 if_out_ucast_pkts_high[0x20]; 8744 8745 u8 if_out_ucast_pkts_low[0x20]; 8746 8747 u8 if_out_discards_high[0x20]; 8748 8749 u8 if_out_discards_low[0x20]; 8750 8751 u8 if_out_errors_high[0x20]; 8752 8753 u8 if_out_errors_low[0x20]; 8754 8755 u8 if_in_multicast_pkts_high[0x20]; 8756 8757 u8 if_in_multicast_pkts_low[0x20]; 8758 8759 u8 if_in_broadcast_pkts_high[0x20]; 8760 8761 u8 if_in_broadcast_pkts_low[0x20]; 8762 8763 u8 if_out_multicast_pkts_high[0x20]; 8764 8765 u8 if_out_multicast_pkts_low[0x20]; 8766 8767 u8 if_out_broadcast_pkts_high[0x20]; 8768 8769 u8 if_out_broadcast_pkts_low[0x20]; 8770 8771 u8 reserved_0[0x480]; 8772}; 8773 8774struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 8775 u8 ether_stats_drop_events_high[0x20]; 8776 8777 u8 ether_stats_drop_events_low[0x20]; 8778 8779 u8 ether_stats_octets_high[0x20]; 8780 8781 u8 ether_stats_octets_low[0x20]; 8782 8783 u8 ether_stats_pkts_high[0x20]; 8784 8785 u8 ether_stats_pkts_low[0x20]; 8786 8787 u8 ether_stats_broadcast_pkts_high[0x20]; 8788 8789 u8 ether_stats_broadcast_pkts_low[0x20]; 8790 8791 u8 ether_stats_multicast_pkts_high[0x20]; 8792 8793 u8 ether_stats_multicast_pkts_low[0x20]; 8794 8795 u8 ether_stats_crc_align_errors_high[0x20]; 8796 8797 u8 ether_stats_crc_align_errors_low[0x20]; 8798 8799 u8 ether_stats_undersize_pkts_high[0x20]; 8800 8801 u8 ether_stats_undersize_pkts_low[0x20]; 8802 8803 u8 ether_stats_oversize_pkts_high[0x20]; 8804 8805 u8 ether_stats_oversize_pkts_low[0x20]; 8806 8807 u8 ether_stats_fragments_high[0x20]; 8808 8809 u8 ether_stats_fragments_low[0x20]; 8810 8811 u8 ether_stats_jabbers_high[0x20]; 8812 8813 u8 ether_stats_jabbers_low[0x20]; 8814 8815 u8 ether_stats_collisions_high[0x20]; 8816 8817 u8 ether_stats_collisions_low[0x20]; 8818 8819 u8 ether_stats_pkts64octets_high[0x20]; 8820 8821 u8 ether_stats_pkts64octets_low[0x20]; 8822 8823 u8 ether_stats_pkts65to127octets_high[0x20]; 8824 8825 u8 ether_stats_pkts65to127octets_low[0x20]; 8826 8827 u8 ether_stats_pkts128to255octets_high[0x20]; 8828 8829 u8 ether_stats_pkts128to255octets_low[0x20]; 8830 8831 u8 ether_stats_pkts256to511octets_high[0x20]; 8832 8833 u8 ether_stats_pkts256to511octets_low[0x20]; 8834 8835 u8 ether_stats_pkts512to1023octets_high[0x20]; 8836 8837 u8 ether_stats_pkts512to1023octets_low[0x20]; 8838 8839 u8 ether_stats_pkts1024to1518octets_high[0x20]; 8840 8841 u8 ether_stats_pkts1024to1518octets_low[0x20]; 8842 8843 u8 ether_stats_pkts1519to2047octets_high[0x20]; 8844 8845 u8 ether_stats_pkts1519to2047octets_low[0x20]; 8846 8847 u8 ether_stats_pkts2048to4095octets_high[0x20]; 8848 8849 u8 ether_stats_pkts2048to4095octets_low[0x20]; 8850 8851 u8 ether_stats_pkts4096to8191octets_high[0x20]; 8852 8853 u8 ether_stats_pkts4096to8191octets_low[0x20]; 8854 8855 u8 ether_stats_pkts8192to10239octets_high[0x20]; 8856 8857 u8 ether_stats_pkts8192to10239octets_low[0x20]; 8858 8859 u8 reserved_0[0x280]; 8860}; 8861 8862struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits { 8863 u8 symbol_error_counter[0x10]; 8864 u8 link_error_recovery_counter[0x8]; 8865 u8 link_downed_counter[0x8]; 8866 8867 u8 port_rcv_errors[0x10]; 8868 u8 port_rcv_remote_physical_errors[0x10]; 8869 8870 u8 port_rcv_switch_relay_errors[0x10]; 8871 u8 port_xmit_discards[0x10]; 8872 8873 u8 port_xmit_constraint_errors[0x8]; 8874 u8 port_rcv_constraint_errors[0x8]; 8875 u8 reserved_0[0x8]; 8876 u8 local_link_integrity_errors[0x4]; 8877 u8 excessive_buffer_overrun_errors[0x4]; 8878 8879 u8 reserved_1[0x10]; 8880 u8 vl_15_dropped[0x10]; 8881 8882 u8 port_xmit_data[0x20]; 8883 8884 u8 port_rcv_data[0x20]; 8885 8886 u8 port_xmit_pkts[0x20]; 8887 8888 u8 port_rcv_pkts[0x20]; 8889 8890 u8 port_xmit_wait[0x20]; 8891 8892 u8 reserved_2[0x680]; 8893}; 8894 8895struct mlx5_ifc_trc_tlb_reg_bits { 8896 u8 reserved_0[0x80]; 8897 8898 u8 tlb_addr[0][0x40]; 8899}; 8900 8901struct mlx5_ifc_trc_read_fifo_reg_bits { 8902 u8 reserved_0[0x10]; 8903 u8 requested_event_num[0x10]; 8904 8905 u8 reserved_1[0x20]; 8906 8907 u8 reserved_2[0x10]; 8908 u8 acual_event_num[0x10]; 8909 8910 u8 reserved_3[0x20]; 8911 8912 u8 event[0][0x40]; 8913}; 8914 8915struct mlx5_ifc_trc_lock_reg_bits { 8916 u8 reserved_0[0x1f]; 8917 u8 lock[0x1]; 8918 8919 u8 reserved_1[0x60]; 8920}; 8921 8922struct mlx5_ifc_trc_filter_reg_bits { 8923 u8 status[0x1]; 8924 u8 reserved_0[0xf]; 8925 u8 filter_index[0x10]; 8926 8927 u8 reserved_1[0x20]; 8928 8929 u8 filter_val[0x20]; 8930 8931 u8 reserved_2[0x1a0]; 8932}; 8933 8934struct mlx5_ifc_trc_event_reg_bits { 8935 u8 status[0x1]; 8936 u8 reserved_0[0xf]; 8937 u8 event_index[0x10]; 8938 8939 u8 reserved_1[0x20]; 8940 8941 u8 event_id[0x20]; 8942 8943 u8 event_selector_val[0x10]; 8944 u8 event_selector_size[0x10]; 8945 8946 u8 reserved_2[0x180]; 8947}; 8948 8949struct mlx5_ifc_trc_conf_reg_bits { 8950 u8 limit_en[0x1]; 8951 u8 reserved_0[0x3]; 8952 u8 dump_mode[0x4]; 8953 u8 reserved_1[0x15]; 8954 u8 state[0x3]; 8955 8956 u8 reserved_2[0x20]; 8957 8958 u8 limit_event_index[0x20]; 8959 8960 u8 mkey[0x20]; 8961 8962 u8 fifo_ready_ev_num[0x20]; 8963 8964 u8 reserved_3[0x160]; 8965}; 8966 8967struct mlx5_ifc_trc_cap_reg_bits { 8968 u8 reserved_0[0x18]; 8969 u8 dump_mode[0x8]; 8970 8971 u8 reserved_1[0x20]; 8972 8973 u8 num_of_events[0x10]; 8974 u8 num_of_filters[0x10]; 8975 8976 u8 fifo_size[0x20]; 8977 8978 u8 tlb_size[0x10]; 8979 u8 event_size[0x10]; 8980 8981 u8 reserved_2[0x160]; 8982}; 8983 8984struct mlx5_ifc_set_node_in_bits { 8985 u8 node_description[64][0x8]; 8986}; 8987 8988struct mlx5_ifc_register_power_settings_bits { 8989 u8 reserved_0[0x18]; 8990 u8 power_settings_level[0x8]; 8991 8992 u8 reserved_1[0x60]; 8993}; 8994 8995struct mlx5_ifc_register_host_endianess_bits { 8996 u8 he[0x1]; 8997 u8 reserved_0[0x1f]; 8998 8999 u8 reserved_1[0x60]; 9000}; 9001 9002struct mlx5_ifc_register_diag_buffer_ctrl_bits { 9003 u8 physical_address[0x40]; 9004}; 9005 9006struct mlx5_ifc_qtct_reg_bits { 9007 u8 operation_type[0x2]; 9008 u8 cap_local_admin[0x1]; 9009 u8 cap_remote_admin[0x1]; 9010 u8 reserved_0[0x4]; 9011 u8 port_number[0x8]; 9012 u8 reserved_1[0xd]; 9013 u8 prio[0x3]; 9014 9015 u8 reserved_2[0x1d]; 9016 u8 tclass[0x3]; 9017}; 9018 9019struct mlx5_ifc_qpdp_reg_bits { 9020 u8 reserved_0[0x8]; 9021 u8 port_number[0x8]; 9022 u8 reserved_1[0x10]; 9023 9024 u8 reserved_2[0x1d]; 9025 u8 pprio[0x3]; 9026}; 9027 9028struct mlx5_ifc_port_info_ro_fields_param_bits { 9029 u8 reserved_0[0x8]; 9030 u8 port[0x8]; 9031 u8 max_gid[0x10]; 9032 9033 u8 reserved_1[0x20]; 9034 9035 u8 port_guid[0x40]; 9036}; 9037 9038struct mlx5_ifc_nvqc_reg_bits { 9039 u8 type[0x20]; 9040 9041 u8 reserved_0[0x18]; 9042 u8 version[0x4]; 9043 u8 reserved_1[0x2]; 9044 u8 support_wr[0x1]; 9045 u8 support_rd[0x1]; 9046}; 9047 9048struct mlx5_ifc_nvia_reg_bits { 9049 u8 reserved_0[0x1d]; 9050 u8 target[0x3]; 9051 9052 u8 reserved_1[0x20]; 9053}; 9054 9055struct mlx5_ifc_nvdi_reg_bits { 9056 struct mlx5_ifc_config_item_bits configuration_item_header; 9057}; 9058 9059struct mlx5_ifc_nvda_reg_bits { 9060 struct mlx5_ifc_config_item_bits configuration_item_header; 9061 9062 u8 configuration_item_data[0x20]; 9063}; 9064 9065struct mlx5_ifc_node_info_ro_fields_param_bits { 9066 u8 system_image_guid[0x40]; 9067 9068 u8 reserved_0[0x40]; 9069 9070 u8 node_guid[0x40]; 9071 9072 u8 reserved_1[0x10]; 9073 u8 max_pkey[0x10]; 9074 9075 u8 reserved_2[0x20]; 9076}; 9077 9078struct mlx5_ifc_ets_tcn_config_reg_bits { 9079 u8 g[0x1]; 9080 u8 b[0x1]; 9081 u8 r[0x1]; 9082 u8 reserved_0[0x9]; 9083 u8 group[0x4]; 9084 u8 reserved_1[0x9]; 9085 u8 bw_allocation[0x7]; 9086 9087 u8 reserved_2[0xc]; 9088 u8 max_bw_units[0x4]; 9089 u8 reserved_3[0x8]; 9090 u8 max_bw_value[0x8]; 9091}; 9092 9093struct mlx5_ifc_ets_global_config_reg_bits { 9094 u8 reserved_0[0x2]; 9095 u8 r[0x1]; 9096 u8 reserved_1[0x1d]; 9097 9098 u8 reserved_2[0xc]; 9099 u8 max_bw_units[0x4]; 9100 u8 reserved_3[0x8]; 9101 u8 max_bw_value[0x8]; 9102}; 9103 9104struct mlx5_ifc_qetc_reg_bits { 9105 u8 reserved_at_0[0x8]; 9106 u8 port_number[0x8]; 9107 u8 reserved_at_10[0x30]; 9108 9109 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 9110 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 9111}; 9112 9113struct mlx5_ifc_nodnic_mac_filters_bits { 9114 struct mlx5_ifc_mac_address_layout_bits mac_filter0; 9115 9116 struct mlx5_ifc_mac_address_layout_bits mac_filter1; 9117 9118 struct mlx5_ifc_mac_address_layout_bits mac_filter2; 9119 9120 struct mlx5_ifc_mac_address_layout_bits mac_filter3; 9121 9122 struct mlx5_ifc_mac_address_layout_bits mac_filter4; 9123 9124 u8 reserved_0[0xc0]; 9125}; 9126 9127struct mlx5_ifc_nodnic_gid_filters_bits { 9128 u8 mgid_filter0[16][0x8]; 9129 9130 u8 mgid_filter1[16][0x8]; 9131 9132 u8 mgid_filter2[16][0x8]; 9133 9134 u8 mgid_filter3[16][0x8]; 9135}; 9136 9137enum { 9138 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT = 0x0, 9139 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT = 0x1, 9140}; 9141 9142enum { 9143 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE = 0x0, 9144 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE = 0x1, 9145}; 9146 9147struct mlx5_ifc_nodnic_config_reg_bits { 9148 u8 no_dram_nic_revision[0x8]; 9149 u8 hardware_format[0x8]; 9150 u8 support_receive_filter[0x1]; 9151 u8 support_promisc_filter[0x1]; 9152 u8 support_promisc_multicast_filter[0x1]; 9153 u8 reserved_0[0x2]; 9154 u8 log_working_buffer_size[0x3]; 9155 u8 log_pkey_table_size[0x4]; 9156 u8 reserved_1[0x3]; 9157 u8 num_ports[0x1]; 9158 9159 u8 reserved_2[0x2]; 9160 u8 log_max_ring_size[0x6]; 9161 u8 reserved_3[0x18]; 9162 9163 u8 lkey[0x20]; 9164 9165 u8 cqe_format[0x4]; 9166 u8 reserved_4[0x1c]; 9167 9168 u8 node_guid[0x40]; 9169 9170 u8 reserved_5[0x740]; 9171 9172 struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings; 9173 9174 struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings; 9175}; 9176 9177struct mlx5_ifc_vlan_layout_bits { 9178 u8 reserved_0[0x14]; 9179 u8 vlan[0xc]; 9180 9181 u8 reserved_1[0x20]; 9182}; 9183 9184struct mlx5_ifc_umr_pointer_desc_argument_bits { 9185 u8 reserved_0[0x20]; 9186 9187 u8 mkey[0x20]; 9188 9189 u8 addressh_63_32[0x20]; 9190 9191 u8 addressl_31_0[0x20]; 9192}; 9193 9194struct mlx5_ifc_ud_adrs_vector_bits { 9195 u8 dc_key[0x40]; 9196 9197 u8 ext[0x1]; 9198 u8 reserved_0[0x7]; 9199 u8 destination_qp_dct[0x18]; 9200 9201 u8 static_rate[0x4]; 9202 u8 sl_eth_prio[0x4]; 9203 u8 fl[0x1]; 9204 u8 mlid[0x7]; 9205 u8 rlid_udp_sport[0x10]; 9206 9207 u8 reserved_1[0x20]; 9208 9209 u8 rmac_47_16[0x20]; 9210 9211 u8 rmac_15_0[0x10]; 9212 u8 tclass[0x8]; 9213 u8 hop_limit[0x8]; 9214 9215 u8 reserved_2[0x1]; 9216 u8 grh[0x1]; 9217 u8 reserved_3[0x2]; 9218 u8 src_addr_index[0x8]; 9219 u8 flow_label[0x14]; 9220 9221 u8 rgid_rip[16][0x8]; 9222}; 9223 9224struct mlx5_ifc_port_module_event_bits { 9225 u8 reserved_0[0x8]; 9226 u8 module[0x8]; 9227 u8 reserved_1[0xc]; 9228 u8 module_status[0x4]; 9229 9230 u8 reserved_2[0x14]; 9231 u8 error_type[0x4]; 9232 u8 reserved_3[0x8]; 9233 9234 u8 reserved_4[0xa0]; 9235}; 9236 9237struct mlx5_ifc_icmd_control_bits { 9238 u8 opcode[0x10]; 9239 u8 status[0x8]; 9240 u8 reserved_0[0x7]; 9241 u8 busy[0x1]; 9242}; 9243 9244struct mlx5_ifc_eqe_bits { 9245 u8 reserved_0[0x8]; 9246 u8 event_type[0x8]; 9247 u8 reserved_1[0x8]; 9248 u8 event_sub_type[0x8]; 9249 9250 u8 reserved_2[0xe0]; 9251 9252 union mlx5_ifc_event_auto_bits event_data; 9253 9254 u8 reserved_3[0x10]; 9255 u8 signature[0x8]; 9256 u8 reserved_4[0x7]; 9257 u8 owner[0x1]; 9258}; 9259 9260enum { 9261 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9262}; 9263 9264struct mlx5_ifc_cmd_queue_entry_bits { 9265 u8 type[0x8]; 9266 u8 reserved_0[0x18]; 9267 9268 u8 input_length[0x20]; 9269 9270 u8 input_mailbox_pointer_63_32[0x20]; 9271 9272 u8 input_mailbox_pointer_31_9[0x17]; 9273 u8 reserved_1[0x9]; 9274 9275 u8 command_input_inline_data[16][0x8]; 9276 9277 u8 command_output_inline_data[16][0x8]; 9278 9279 u8 output_mailbox_pointer_63_32[0x20]; 9280 9281 u8 output_mailbox_pointer_31_9[0x17]; 9282 u8 reserved_2[0x9]; 9283 9284 u8 output_length[0x20]; 9285 9286 u8 token[0x8]; 9287 u8 signature[0x8]; 9288 u8 reserved_3[0x8]; 9289 u8 status[0x7]; 9290 u8 ownership[0x1]; 9291}; 9292 9293struct mlx5_ifc_cmd_out_bits { 9294 u8 status[0x8]; 9295 u8 reserved_0[0x18]; 9296 9297 u8 syndrome[0x20]; 9298 9299 u8 command_output[0x20]; 9300}; 9301 9302struct mlx5_ifc_cmd_in_bits { 9303 u8 opcode[0x10]; 9304 u8 reserved_0[0x10]; 9305 9306 u8 reserved_1[0x10]; 9307 u8 op_mod[0x10]; 9308 9309 u8 command[0][0x20]; 9310}; 9311 9312struct mlx5_ifc_cmd_if_box_bits { 9313 u8 mailbox_data[512][0x8]; 9314 9315 u8 reserved_0[0x180]; 9316 9317 u8 next_pointer_63_32[0x20]; 9318 9319 u8 next_pointer_31_10[0x16]; 9320 u8 reserved_1[0xa]; 9321 9322 u8 block_number[0x20]; 9323 9324 u8 reserved_2[0x8]; 9325 u8 token[0x8]; 9326 u8 ctrl_signature[0x8]; 9327 u8 signature[0x8]; 9328}; 9329 9330struct mlx5_ifc_mtt_bits { 9331 u8 ptag_63_32[0x20]; 9332 9333 u8 ptag_31_8[0x18]; 9334 u8 reserved_0[0x6]; 9335 u8 wr_en[0x1]; 9336 u8 rd_en[0x1]; 9337}; 9338 9339/* Vendor Specific Capabilities, VSC */ 9340enum { 9341 MLX5_VSC_DOMAIN_ICMD = 0x1, 9342 MLX5_VSC_DOMAIN_PROTECTED_CRSPACE = 0x6, 9343 MLX5_VSC_DOMAIN_SEMAPHORES = 0xA, 9344}; 9345 9346struct mlx5_ifc_vendor_specific_cap_bits { 9347 u8 type[0x8]; 9348 u8 length[0x8]; 9349 u8 next_pointer[0x8]; 9350 u8 capability_id[0x8]; 9351 9352 u8 status[0x3]; 9353 u8 reserved_0[0xd]; 9354 u8 space[0x10]; 9355 9356 u8 counter[0x20]; 9357 9358 u8 semaphore[0x20]; 9359 9360 u8 flag[0x1]; 9361 u8 reserved_1[0x1]; 9362 u8 address[0x1e]; 9363 9364 u8 data[0x20]; 9365}; 9366 9367enum { 9368 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9369 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9370 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9371}; 9372 9373enum { 9374 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9375 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9376 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9377}; 9378 9379enum { 9380 MLX5_HEALTH_SYNDR_FW_ERR = 0x1, 9381 MLX5_HEALTH_SYNDR_IRISC_ERR = 0x7, 9382 MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR = 0x8, 9383 MLX5_HEALTH_SYNDR_CRC_ERR = 0x9, 9384 MLX5_HEALTH_SYNDR_FETCH_PCI_ERR = 0xa, 9385 MLX5_HEALTH_SYNDR_HW_FTL_ERR = 0xb, 9386 MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR = 0xc, 9387 MLX5_HEALTH_SYNDR_EQ_ERR = 0xd, 9388 MLX5_HEALTH_SYNDR_EQ_INV = 0xe, 9389 MLX5_HEALTH_SYNDR_FFSER_ERR = 0xf, 9390 MLX5_HEALTH_SYNDR_HIGH_TEMP = 0x10, 9391}; 9392 9393struct mlx5_ifc_initial_seg_bits { 9394 u8 fw_rev_minor[0x10]; 9395 u8 fw_rev_major[0x10]; 9396 9397 u8 cmd_interface_rev[0x10]; 9398 u8 fw_rev_subminor[0x10]; 9399 9400 u8 reserved_0[0x40]; 9401 9402 u8 cmdq_phy_addr_63_32[0x20]; 9403 9404 u8 cmdq_phy_addr_31_12[0x14]; 9405 u8 reserved_1[0x2]; 9406 u8 nic_interface[0x2]; 9407 u8 log_cmdq_size[0x4]; 9408 u8 log_cmdq_stride[0x4]; 9409 9410 u8 command_doorbell_vector[0x20]; 9411 9412 u8 reserved_2[0xf00]; 9413 9414 u8 initializing[0x1]; 9415 u8 reserved_3[0x4]; 9416 u8 nic_interface_supported[0x3]; 9417 u8 reserved_4[0x18]; 9418 9419 struct mlx5_ifc_health_buffer_bits health_buffer; 9420 9421 u8 no_dram_nic_offset[0x20]; 9422 9423 u8 reserved_5[0x6de0]; 9424 9425 u8 internal_timer_h[0x20]; 9426 9427 u8 internal_timer_l[0x20]; 9428 9429 u8 reserved_6[0x20]; 9430 9431 u8 reserved_7[0x1f]; 9432 u8 clear_int[0x1]; 9433 9434 u8 health_syndrome[0x8]; 9435 u8 health_counter[0x18]; 9436 9437 u8 reserved_8[0x17fc0]; 9438}; 9439 9440union mlx5_ifc_icmd_interface_document_bits { 9441 struct mlx5_ifc_fw_version_bits fw_version; 9442 struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in; 9443 struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out; 9444 struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in; 9445 struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in; 9446 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out; 9447 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out; 9448 struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general; 9449 struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in; 9450 struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out; 9451 struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out; 9452 struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in; 9453 struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in; 9454 struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out; 9455 u8 reserved_0[0x42c0]; 9456}; 9457 9458union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 9459 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9460 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9461 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9462 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9463 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9464 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 9465 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9466 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9467 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 9468 struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs; 9469 u8 reserved_0[0x7c0]; 9470}; 9471 9472struct mlx5_ifc_ppcnt_reg_bits { 9473 u8 swid[0x8]; 9474 u8 local_port[0x8]; 9475 u8 pnat[0x2]; 9476 u8 reserved_0[0x8]; 9477 u8 grp[0x6]; 9478 9479 u8 clr[0x1]; 9480 u8 reserved_1[0x1c]; 9481 u8 prio_tc[0x3]; 9482 9483 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9484}; 9485 9486struct mlx5_ifc_pcie_performance_counters_data_layout_bits { 9487 u8 life_time_counter_high[0x20]; 9488 9489 u8 life_time_counter_low[0x20]; 9490 9491 u8 rx_errors[0x20]; 9492 9493 u8 tx_errors[0x20]; 9494 9495 u8 l0_to_recovery_eieos[0x20]; 9496 9497 u8 l0_to_recovery_ts[0x20]; 9498 9499 u8 l0_to_recovery_framing[0x20]; 9500 9501 u8 l0_to_recovery_retrain[0x20]; 9502 9503 u8 crc_error_dllp[0x20]; 9504 9505 u8 crc_error_tlp[0x20]; 9506 9507 u8 reserved_0[0x680]; 9508}; 9509 9510struct mlx5_ifc_pcie_timers_and_states_data_layout_bits { 9511 u8 life_time_counter_high[0x20]; 9512 9513 u8 life_time_counter_low[0x20]; 9514 9515 u8 time_to_boot_image_start[0x20]; 9516 9517 u8 time_to_link_image[0x20]; 9518 9519 u8 calibration_time[0x20]; 9520 9521 u8 time_to_first_perst[0x20]; 9522 9523 u8 time_to_detect_state[0x20]; 9524 9525 u8 time_to_l0[0x20]; 9526 9527 u8 time_to_crs_en[0x20]; 9528 9529 u8 time_to_plastic_image_start[0x20]; 9530 9531 u8 time_to_iron_image_start[0x20]; 9532 9533 u8 perst_handler[0x20]; 9534 9535 u8 times_in_l1[0x20]; 9536 9537 u8 times_in_l23[0x20]; 9538 9539 u8 dl_down[0x20]; 9540 9541 u8 config_cycle1usec[0x20]; 9542 9543 u8 config_cycle2to7usec[0x20]; 9544 9545 u8 config_cycle8to15usec[0x20]; 9546 9547 u8 config_cycle16to63usec[0x20]; 9548 9549 u8 config_cycle64usec[0x20]; 9550 9551 u8 correctable_err_msg_sent[0x20]; 9552 9553 u8 non_fatal_err_msg_sent[0x20]; 9554 9555 u8 fatal_err_msg_sent[0x20]; 9556 9557 u8 reserved_0[0x4e0]; 9558}; 9559 9560struct mlx5_ifc_pcie_lanes_counters_data_layout_bits { 9561 u8 life_time_counter_high[0x20]; 9562 9563 u8 life_time_counter_low[0x20]; 9564 9565 u8 error_counter_lane0[0x20]; 9566 9567 u8 error_counter_lane1[0x20]; 9568 9569 u8 error_counter_lane2[0x20]; 9570 9571 u8 error_counter_lane3[0x20]; 9572 9573 u8 error_counter_lane4[0x20]; 9574 9575 u8 error_counter_lane5[0x20]; 9576 9577 u8 error_counter_lane6[0x20]; 9578 9579 u8 error_counter_lane7[0x20]; 9580 9581 u8 error_counter_lane8[0x20]; 9582 9583 u8 error_counter_lane9[0x20]; 9584 9585 u8 error_counter_lane10[0x20]; 9586 9587 u8 error_counter_lane11[0x20]; 9588 9589 u8 error_counter_lane12[0x20]; 9590 9591 u8 error_counter_lane13[0x20]; 9592 9593 u8 error_counter_lane14[0x20]; 9594 9595 u8 error_counter_lane15[0x20]; 9596 9597 u8 reserved_0[0x580]; 9598}; 9599 9600union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits { 9601 struct mlx5_ifc_pcie_performance_counters_data_layout_bits pcie_performance_counters_data_layout; 9602 struct mlx5_ifc_pcie_timers_and_states_data_layout_bits pcie_timers_and_states_data_layout; 9603 struct mlx5_ifc_pcie_lanes_counters_data_layout_bits pcie_lanes_counters_data_layout; 9604 u8 reserved_0[0xf8]; 9605}; 9606 9607struct mlx5_ifc_mpcnt_reg_bits { 9608 u8 reserved_0[0x8]; 9609 u8 pcie_index[0x8]; 9610 u8 reserved_1[0xa]; 9611 u8 grp[0x6]; 9612 9613 u8 clr[0x1]; 9614 u8 reserved_2[0x1f]; 9615 9616 union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits counter_set; 9617}; 9618 9619union mlx5_ifc_ports_control_registers_document_bits { 9620 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data; 9621 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 9622 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9623 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9624 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9625 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9626 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 9627 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9628 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9629 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout; 9630 struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout; 9631 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 9632 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date; 9633 struct mlx5_ifc_pamp_reg_bits pamp_reg; 9634 struct mlx5_ifc_paos_reg_bits paos_reg; 9635 struct mlx5_ifc_pbmc_reg_bits pbmc_reg; 9636 struct mlx5_ifc_pcap_reg_bits pcap_reg; 9637 struct mlx5_ifc_peir_reg_bits peir_reg; 9638 struct mlx5_ifc_pelc_reg_bits pelc_reg; 9639 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 9640 struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg; 9641 struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg; 9642 struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg; 9643 struct mlx5_ifc_phrr_reg_bits phrr_reg; 9644 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9645 struct mlx5_ifc_pifr_reg_bits pifr_reg; 9646 struct mlx5_ifc_pipg_reg_bits pipg_reg; 9647 struct mlx5_ifc_plbf_reg_bits plbf_reg; 9648 struct mlx5_ifc_plib_reg_bits plib_reg; 9649 struct mlx5_ifc_pll_status_data_bits pll_status_data; 9650 struct mlx5_ifc_plpc_reg_bits plpc_reg; 9651 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 9652 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 9653 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 9654 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 9655 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 9656 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 9657 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 9658 struct mlx5_ifc_ppad_reg_bits ppad_reg; 9659 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 9660 struct mlx5_ifc_ppll_reg_bits ppll_reg; 9661 struct mlx5_ifc_pplm_reg_bits pplm_reg; 9662 struct mlx5_ifc_pplr_reg_bits pplr_reg; 9663 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 9664 struct mlx5_ifc_pspa_reg_bits pspa_reg; 9665 struct mlx5_ifc_ptas_reg_bits ptas_reg; 9666 struct mlx5_ifc_ptys_reg_bits ptys_reg; 9667 struct mlx5_ifc_pude_reg_bits pude_reg; 9668 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 9669 struct mlx5_ifc_slrg_reg_bits slrg_reg; 9670 struct mlx5_ifc_slrp_reg_bits slrp_reg; 9671 struct mlx5_ifc_sltp_reg_bits sltp_reg; 9672 u8 reserved_0[0x7880]; 9673}; 9674 9675union mlx5_ifc_debug_enhancements_document_bits { 9676 struct mlx5_ifc_health_buffer_bits health_buffer; 9677 u8 reserved_0[0x200]; 9678}; 9679 9680union mlx5_ifc_no_dram_nic_document_bits { 9681 struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg; 9682 struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word; 9683 struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word; 9684 struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters; 9685 struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters; 9686 struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg; 9687 struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg; 9688 struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell; 9689 u8 reserved_0[0x3160]; 9690}; 9691 9692union mlx5_ifc_uplink_pci_interface_document_bits { 9693 struct mlx5_ifc_initial_seg_bits initial_seg; 9694 struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap; 9695 u8 reserved_0[0x20120]; 9696}; 9697 9698 9699#endif /* MLX5_IFC_H */ 9700