mlx5_ifc.h revision 331807 
1/*-
2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd.  All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_ifc.h 331807 2018-03-30 19:13:17Z hselasky $
26 */
27
28#ifndef MLX5_IFC_H
29#define MLX5_IFC_H
30
31enum {
32	MLX5_EVENT_TYPE_COMP                                       = 0x0,
33	MLX5_EVENT_TYPE_PATH_MIG                                   = 0x1,
34	MLX5_EVENT_TYPE_COMM_EST                                   = 0x2,
35	MLX5_EVENT_TYPE_SQ_DRAINED                                 = 0x3,
36	MLX5_EVENT_TYPE_SRQ_LAST_WQE                               = 0x13,
37	MLX5_EVENT_TYPE_SRQ_RQ_LIMIT                               = 0x14,
38	MLX5_EVENT_TYPE_DCT_DRAINED                                = 0x1c,
39	MLX5_EVENT_TYPE_DCT_KEY_VIOLATION                          = 0x1d,
40	MLX5_EVENT_TYPE_CQ_ERROR                                   = 0x4,
41	MLX5_EVENT_TYPE_WQ_CATAS_ERROR                             = 0x5,
42	MLX5_EVENT_TYPE_PATH_MIG_FAILED                            = 0x7,
43	MLX5_EVENT_TYPE_PAGE_FAULT                                 = 0xc,
44	MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR                         = 0x10,
45	MLX5_EVENT_TYPE_WQ_ACCESS_ERROR                            = 0x11,
46	MLX5_EVENT_TYPE_SRQ_CATAS_ERROR                            = 0x12,
47	MLX5_EVENT_TYPE_INTERNAL_ERROR                             = 0x8,
48	MLX5_EVENT_TYPE_PORT_CHANGE                                = 0x9,
49	MLX5_EVENT_TYPE_GPIO_EVENT                                 = 0x15,
50	MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT                   = 0x16,
51	MLX5_EVENT_TYPE_CODING_TEMP_WARNING_EVENT                  = 0x17,
52	MLX5_EVENT_TYPE_REMOTE_CONFIG                              = 0x19,
53	MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT                   = 0x1e,
54	MLX5_EVENT_TYPE_CODING_PPS_EVENT                           = 0x25,
55	MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT          = 0x22,
56	MLX5_EVENT_TYPE_DB_BF_CONGESTION                           = 0x1a,
57	MLX5_EVENT_TYPE_STALL_EVENT                                = 0x1b,
58	MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT                = 0x1f,
59	MLX5_EVENT_TYPE_CMD                                        = 0xa,
60	MLX5_EVENT_TYPE_PAGE_REQUEST                               = 0xb,
61	MLX5_EVENT_TYPE_NIC_VPORT_CHANGE                           = 0xd
62};
63
64enum {
65	MLX5_MODIFY_TIR_BITMASK_LRO                                = 0x0,
66	MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE                     = 0x1,
67	MLX5_MODIFY_TIR_BITMASK_HASH                               = 0x2,
68	MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN                = 0x3,
69	MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN                         = 0x4
70};
71
72enum {
73	MLX5_MODIFY_RQT_BITMASK_RQN_LIST          = 0x1,
74};
75
76enum {
77	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
78	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
79};
80
81enum {
82	MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
83	MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
84	MLX5_CMD_OP_INIT_HCA                      = 0x102,
85	MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
86	MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
87	MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
88	MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
89	MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
90	MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
91	MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
92	MLX5_CMD_OP_SET_ISSI                      = 0x10b,
93	MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
94	MLX5_CMD_OP_QUERY_OTHER_HCA_CAP           = 0x10e,
95	MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP          = 0x10f,
96	MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
97	MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
98	MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
99	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
100	MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
101	MLX5_CMD_OP_CREATE_EQ                     = 0x301,
102	MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
103	MLX5_CMD_OP_QUERY_EQ                      = 0x303,
104	MLX5_CMD_OP_GEN_EQE                       = 0x304,
105	MLX5_CMD_OP_CREATE_CQ                     = 0x400,
106	MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
107	MLX5_CMD_OP_QUERY_CQ                      = 0x402,
108	MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
109	MLX5_CMD_OP_CREATE_QP                     = 0x500,
110	MLX5_CMD_OP_DESTROY_QP                    = 0x501,
111	MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
112	MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
113	MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
114	MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
115	MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
116	MLX5_CMD_OP_2ERR_QP                       = 0x507,
117	MLX5_CMD_OP_2RST_QP                       = 0x50a,
118	MLX5_CMD_OP_QUERY_QP                      = 0x50b,
119	MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
120	MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
121	MLX5_CMD_OP_CREATE_PSV                    = 0x600,
122	MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
123	MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
124	MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
125	MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
126	MLX5_CMD_OP_ARM_RQ                        = 0x703,
127	MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
128	MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
129	MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
130	MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
131	MLX5_CMD_OP_CREATE_DCT                    = 0x710,
132	MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
133	MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
134	MLX5_CMD_OP_QUERY_DCT                     = 0x713,
135	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
136	MLX5_CMD_OP_SET_DC_CNAK_TRACE             = 0x715,
137	MLX5_CMD_OP_QUERY_DC_CNAK_TRACE           = 0x716,
138	MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
139	MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
140	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
141	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
142	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
143	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
144	MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
145	MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
146	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
147	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
148	MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
149	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
150	MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
151	MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
152	MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
153	MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
154	MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
155	MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
156	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT     = 0x782,
157	MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT    = 0x783,
158	MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT      = 0x784,
159	MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT     = 0x785,
160	MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
161	MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
162	MLX5_CMD_OP_ALLOC_PD                      = 0x800,
163	MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
164	MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
165	MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
166	MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
167	MLX5_CMD_OP_ACCESS_REG                    = 0x805,
168	MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
169	MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
170	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
171	MLX5_CMD_OP_MAD_IFC                       = 0x50d,
172	MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
173	MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
174	MLX5_CMD_OP_NOP                           = 0x80d,
175	MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
176	MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
177	MLX5_CMD_OP_SET_BURST_SIZE                = 0x812,
178	MLX5_CMD_OP_QUERY_BURST_SIZE              = 0x813,
179	MLX5_CMD_OP_ACTIVATE_TRACER               = 0x814,
180	MLX5_CMD_OP_DEACTIVATE_TRACER             = 0x815,
181	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
182	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
183	MLX5_CMD_OP_SET_DIAGNOSTICS               = 0x820,
184	MLX5_CMD_OP_QUERY_DIAGNOSTICS             = 0x821,
185	MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
186	MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
187	MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
188	MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
189	MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
190	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
191	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
192	MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
193	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
194	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
195	MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
196	MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
197	MLX5_CMD_OP_CREATE_LAG                    = 0x840,
198	MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
199	MLX5_CMD_OP_QUERY_LAG                     = 0x842,
200	MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
201	MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
202	MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
203	MLX5_CMD_OP_CREATE_TIR                    = 0x900,
204	MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
205	MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
206	MLX5_CMD_OP_QUERY_TIR                     = 0x903,
207	MLX5_CMD_OP_CREATE_SQ                     = 0x904,
208	MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
209	MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
210	MLX5_CMD_OP_QUERY_SQ                      = 0x907,
211	MLX5_CMD_OP_CREATE_RQ                     = 0x908,
212	MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
213	MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
214	MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
215	MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
216	MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
217	MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
218	MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
219	MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
220	MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS       = 0x911,
221	MLX5_CMD_OP_CREATE_TIS                    = 0x912,
222	MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
223	MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
224	MLX5_CMD_OP_QUERY_TIS                     = 0x915,
225	MLX5_CMD_OP_CREATE_RQT                    = 0x916,
226	MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
227	MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
228	MLX5_CMD_OP_QUERY_RQT                     = 0x919,
229	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
230	MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
231	MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
232	MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
233	MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
234	MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
235	MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
236	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
237	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
238	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
239	MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
240	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
241	MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
242	MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
243	MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
244	MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
245};
246
247enum {
248	MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO     = 0x8007,
249	MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY         = 0x8400,
250	MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER          = 0x9001,
251	MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC        = 0x9003,
252	MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC          = 0x9004,
253	MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL            = 0x9005,
254	MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL              = 0x9006,
255	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT                = 0x9007,
256	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008,
257	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS   = 0x9009,
258	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT           = 0x900a,
259	MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD         = 0xf004
260};
261
262struct mlx5_ifc_flow_table_fields_supported_bits {
263	u8         outer_dmac[0x1];
264	u8         outer_smac[0x1];
265	u8         outer_ether_type[0x1];
266	u8         reserved_0[0x1];
267	u8         outer_first_prio[0x1];
268	u8         outer_first_cfi[0x1];
269	u8         outer_first_vid[0x1];
270	u8         reserved_1[0x1];
271	u8         outer_second_prio[0x1];
272	u8         outer_second_cfi[0x1];
273	u8         outer_second_vid[0x1];
274	u8         outer_ipv6_flow_label[0x1];
275	u8         outer_sip[0x1];
276	u8         outer_dip[0x1];
277	u8         outer_frag[0x1];
278	u8         outer_ip_protocol[0x1];
279	u8         outer_ip_ecn[0x1];
280	u8         outer_ip_dscp[0x1];
281	u8         outer_udp_sport[0x1];
282	u8         outer_udp_dport[0x1];
283	u8         outer_tcp_sport[0x1];
284	u8         outer_tcp_dport[0x1];
285	u8         outer_tcp_flags[0x1];
286	u8         outer_gre_protocol[0x1];
287	u8         outer_gre_key[0x1];
288	u8         outer_vxlan_vni[0x1];
289	u8         outer_geneve_vni[0x1];
290	u8         outer_geneve_oam[0x1];
291	u8         outer_geneve_protocol_type[0x1];
292	u8         outer_geneve_opt_len[0x1];
293	u8         reserved_2[0x1];
294	u8         source_eswitch_port[0x1];
295
296	u8         inner_dmac[0x1];
297	u8         inner_smac[0x1];
298	u8         inner_ether_type[0x1];
299	u8         reserved_3[0x1];
300	u8         inner_first_prio[0x1];
301	u8         inner_first_cfi[0x1];
302	u8         inner_first_vid[0x1];
303	u8         reserved_4[0x1];
304	u8         inner_second_prio[0x1];
305	u8         inner_second_cfi[0x1];
306	u8         inner_second_vid[0x1];
307	u8         inner_ipv6_flow_label[0x1];
308	u8         inner_sip[0x1];
309	u8         inner_dip[0x1];
310	u8         inner_frag[0x1];
311	u8         inner_ip_protocol[0x1];
312	u8         inner_ip_ecn[0x1];
313	u8         inner_ip_dscp[0x1];
314	u8         inner_udp_sport[0x1];
315	u8         inner_udp_dport[0x1];
316	u8         inner_tcp_sport[0x1];
317	u8         inner_tcp_dport[0x1];
318	u8         inner_tcp_flags[0x1];
319	u8         reserved_5[0x9];
320
321	u8         reserved_6[0x1a];
322	u8         bth_dst_qp[0x1];
323	u8         reserved_7[0x4];
324	u8         source_sqn[0x1];
325
326	u8         reserved_8[0x20];
327};
328
329struct mlx5_ifc_eth_discard_cntrs_grp_bits {
330	u8         ingress_general_high[0x20];
331
332	u8         ingress_general_low[0x20];
333
334	u8         ingress_policy_engine_high[0x20];
335
336	u8         ingress_policy_engine_low[0x20];
337
338	u8         ingress_vlan_membership_high[0x20];
339
340	u8         ingress_vlan_membership_low[0x20];
341
342	u8         ingress_tag_frame_type_high[0x20];
343
344	u8         ingress_tag_frame_type_low[0x20];
345
346	u8         egress_vlan_membership_high[0x20];
347
348	u8         egress_vlan_membership_low[0x20];
349
350	u8         loopback_filter_high[0x20];
351
352	u8         loopback_filter_low[0x20];
353
354	u8         egress_general_high[0x20];
355
356	u8         egress_general_low[0x20];
357
358	u8         reserved_at_1c0[0x40];
359
360	u8         egress_hoq_high[0x20];
361
362	u8         egress_hoq_low[0x20];
363
364	u8         port_isolation_high[0x20];
365
366	u8         port_isolation_low[0x20];
367
368	u8         egress_policy_engine_high[0x20];
369
370	u8         egress_policy_engine_low[0x20];
371
372	u8         ingress_tx_link_down_high[0x20];
373
374	u8         ingress_tx_link_down_low[0x20];
375
376	u8         egress_stp_filter_high[0x20];
377
378	u8         egress_stp_filter_low[0x20];
379
380	u8         egress_hoq_stall_high[0x20];
381
382	u8         egress_hoq_stall_low[0x20];
383
384	u8         reserved_at_340[0x440];
385};
386struct mlx5_ifc_flow_table_prop_layout_bits {
387	u8         ft_support[0x1];
388	u8         flow_tag[0x1];
389	u8         flow_counter[0x1];
390	u8         flow_modify_en[0x1];
391	u8         modify_root[0x1];
392	u8         identified_miss_table[0x1];
393	u8         flow_table_modify[0x1];
394	u8         encap[0x1];
395	u8         decap[0x1];
396	u8         reset_root_to_default[0x1];
397	u8         reserved_at_a[0x16];
398
399	u8         reserved_at_20[0x2];
400	u8         log_max_ft_size[0x6];
401	u8         reserved_at_28[0x10];
402	u8         max_ft_level[0x8];
403
404	u8         reserved_at_40[0x20];
405
406	u8         reserved_at_60[0x18];
407	u8         log_max_ft_num[0x8];
408
409	u8         reserved_at_80[0x10];
410	u8         log_max_flow_counter[0x8];
411	u8         log_max_destination[0x8];
412
413	u8         reserved_at_a0[0x18];
414	u8         log_max_flow[0x8];
415
416	u8         reserved_at_c0[0x40];
417
418	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
419
420	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
421};
422
423struct mlx5_ifc_odp_per_transport_service_cap_bits {
424	u8         send[0x1];
425	u8         receive[0x1];
426	u8         write[0x1];
427	u8         read[0x1];
428	u8         atomic[0x1];
429	u8         srq_receive[0x1];
430	u8         reserved_0[0x1a];
431};
432
433struct mlx5_ifc_flow_counter_list_bits {
434	u8         reserved_0[0x10];
435	u8         flow_counter_id[0x10];
436
437	u8         reserved_1[0x20];
438};
439
440enum {
441	MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT                    = 0x0,
442	MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE               = 0x1,
443	MLX5_FLOW_CONTEXT_DEST_TYPE_TIR                      = 0x2,
444	MLX5_FLOW_CONTEXT_DEST_TYPE_QP                       = 0x3,
445};
446
447struct mlx5_ifc_dest_format_struct_bits {
448	u8         destination_type[0x8];
449	u8         destination_id[0x18];
450
451	u8         reserved_0[0x20];
452};
453
454struct mlx5_ifc_ipv4_layout_bits {
455	u8         reserved_at_0[0x60];
456
457	u8         ipv4[0x20];
458};
459
460struct mlx5_ifc_ipv6_layout_bits {
461	u8         ipv6[16][0x8];
462};
463
464union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
465	struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
466	struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
467	u8         reserved_at_0[0x80];
468};
469
470struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
471	u8         smac_47_16[0x20];
472
473	u8         smac_15_0[0x10];
474	u8         ethertype[0x10];
475
476	u8         dmac_47_16[0x20];
477
478	u8         dmac_15_0[0x10];
479	u8         first_prio[0x3];
480	u8         first_cfi[0x1];
481	u8         first_vid[0xc];
482
483	u8         ip_protocol[0x8];
484	u8         ip_dscp[0x6];
485	u8         ip_ecn[0x2];
486	u8         cvlan_tag[0x1];
487	u8         svlan_tag[0x1];
488	u8         frag[0x1];
489	u8         reserved_1[0x4];
490	u8         tcp_flags[0x9];
491
492	u8         tcp_sport[0x10];
493	u8         tcp_dport[0x10];
494
495	u8         reserved_2[0x20];
496
497	u8         udp_sport[0x10];
498	u8         udp_dport[0x10];
499
500	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
501
502	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
503};
504
505struct mlx5_ifc_fte_match_set_misc_bits {
506	u8         reserved_0[0x8];
507	u8         source_sqn[0x18];
508
509	u8         reserved_1[0x10];
510	u8         source_port[0x10];
511
512	u8         outer_second_prio[0x3];
513	u8         outer_second_cfi[0x1];
514	u8         outer_second_vid[0xc];
515	u8         inner_second_prio[0x3];
516	u8         inner_second_cfi[0x1];
517	u8         inner_second_vid[0xc];
518
519	u8         outer_second_vlan_tag[0x1];
520	u8         inner_second_vlan_tag[0x1];
521	u8         reserved_2[0xe];
522	u8         gre_protocol[0x10];
523
524	u8         gre_key_h[0x18];
525	u8         gre_key_l[0x8];
526
527	u8         vxlan_vni[0x18];
528	u8         reserved_3[0x8];
529
530	u8         geneve_vni[0x18];
531	u8         reserved4[0x7];
532	u8         geneve_oam[0x1];
533
534	u8         reserved_5[0xc];
535	u8         outer_ipv6_flow_label[0x14];
536
537	u8         reserved_6[0xc];
538	u8         inner_ipv6_flow_label[0x14];
539
540	u8         reserved_7[0xa];
541	u8         geneve_opt_len[0x6];
542	u8         geneve_protocol_type[0x10];
543
544	u8         reserved_8[0x8];
545	u8         bth_dst_qp[0x18];
546
547	u8         reserved_9[0xa0];
548};
549
550struct mlx5_ifc_cmd_pas_bits {
551	u8         pa_h[0x20];
552
553	u8         pa_l[0x14];
554	u8         reserved_0[0xc];
555};
556
557struct mlx5_ifc_uint64_bits {
558	u8         hi[0x20];
559
560	u8         lo[0x20];
561};
562
563struct mlx5_ifc_application_prio_entry_bits {
564	u8         reserved_0[0x8];
565	u8         priority[0x3];
566	u8         reserved_1[0x2];
567	u8         sel[0x3];
568	u8         protocol_id[0x10];
569};
570
571struct mlx5_ifc_nodnic_ring_doorbell_bits {
572	u8         reserved_0[0x8];
573	u8         ring_pi[0x10];
574	u8         reserved_1[0x8];
575};
576
577enum {
578	MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
579	MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
580	MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
581	MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
582	MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
583	MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
584	MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
585	MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
586	MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
587	MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
588};
589
590struct mlx5_ifc_ads_bits {
591	u8         fl[0x1];
592	u8         free_ar[0x1];
593	u8         reserved_0[0xe];
594	u8         pkey_index[0x10];
595
596	u8         reserved_1[0x8];
597	u8         grh[0x1];
598	u8         mlid[0x7];
599	u8         rlid[0x10];
600
601	u8         ack_timeout[0x5];
602	u8         reserved_2[0x3];
603	u8         src_addr_index[0x8];
604	u8         log_rtm[0x4];
605	u8         stat_rate[0x4];
606	u8         hop_limit[0x8];
607
608	u8         reserved_3[0x4];
609	u8         tclass[0x8];
610	u8         flow_label[0x14];
611
612	u8         rgid_rip[16][0x8];
613
614	u8         reserved_4[0x4];
615	u8         f_dscp[0x1];
616	u8         f_ecn[0x1];
617	u8         reserved_5[0x1];
618	u8         f_eth_prio[0x1];
619	u8         ecn[0x2];
620	u8         dscp[0x6];
621	u8         udp_sport[0x10];
622
623	u8         dei_cfi[0x1];
624	u8         eth_prio[0x3];
625	u8         sl[0x4];
626	u8         port[0x8];
627	u8         rmac_47_32[0x10];
628
629	u8         rmac_31_0[0x20];
630};
631
632struct mlx5_ifc_diagnostic_counter_cap_bits {
633	u8         sync[0x1];
634	u8         reserved_0[0xf];
635	u8         counter_id[0x10];
636};
637
638struct mlx5_ifc_debug_cap_bits {
639	u8         reserved_0[0x18];
640	u8         log_max_samples[0x8];
641
642	u8         single[0x1];
643	u8         repetitive[0x1];
644	u8         health_mon_rx_activity[0x1];
645	u8         reserved_1[0x15];
646	u8         log_min_sample_period[0x8];
647
648	u8         reserved_2[0x1c0];
649
650	struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0];
651};
652
653struct mlx5_ifc_qos_cap_bits {
654	u8         packet_pacing[0x1];
655	u8         esw_scheduling[0x1];
656	u8         esw_bw_share[0x1];
657	u8         esw_rate_limit[0x1];
658	u8         hll[0x1];
659	u8         packet_pacing_burst_bound[0x1];
660	u8         reserved_at_6[0x1a];
661
662	u8         reserved_at_20[0x20];
663
664	u8         packet_pacing_max_rate[0x20];
665
666	u8         packet_pacing_min_rate[0x20];
667
668	u8         reserved_at_80[0x10];
669	u8         packet_pacing_rate_table_size[0x10];
670
671	u8         esw_element_type[0x10];
672	u8         esw_tsar_type[0x10];
673
674	u8         reserved_at_c0[0x10];
675	u8         max_qos_para_vport[0x10];
676
677	u8         max_tsar_bw_share[0x20];
678
679	u8         reserved_at_100[0x700];
680};
681
682struct mlx5_ifc_snapshot_cap_bits {
683	u8         reserved_0[0x1d];
684	u8         suspend_qp_uc[0x1];
685	u8         suspend_qp_ud[0x1];
686	u8         suspend_qp_rc[0x1];
687
688	u8         reserved_1[0x1c];
689	u8         restore_pd[0x1];
690	u8         restore_uar[0x1];
691	u8         restore_mkey[0x1];
692	u8         restore_qp[0x1];
693
694	u8         reserved_2[0x1e];
695	u8         named_mkey[0x1];
696	u8         named_qp[0x1];
697
698	u8         reserved_3[0x7a0];
699};
700
701struct mlx5_ifc_e_switch_cap_bits {
702	u8         vport_svlan_strip[0x1];
703	u8         vport_cvlan_strip[0x1];
704	u8         vport_svlan_insert[0x1];
705	u8         vport_cvlan_insert_if_not_exist[0x1];
706	u8         vport_cvlan_insert_overwrite[0x1];
707
708	u8         reserved_0[0x19];
709
710	u8         nic_vport_node_guid_modify[0x1];
711	u8         nic_vport_port_guid_modify[0x1];
712
713	u8         reserved_1[0x7e0];
714};
715
716struct mlx5_ifc_flow_table_eswitch_cap_bits {
717	u8         reserved_0[0x200];
718
719	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
720
721	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
722
723	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
724
725	u8         reserved_1[0x7800];
726};
727
728struct mlx5_ifc_flow_table_nic_cap_bits {
729	u8         nic_rx_multi_path_tirs[0x1];
730	u8         nic_rx_multi_path_tirs_fts[0x1];
731	u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
732	u8         reserved_at_3[0x1fd];
733
734	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
735
736	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
737
738	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
739
740	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
741
742	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
743
744	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
745
746	u8         reserved_1[0x7200];
747};
748
749struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
750	u8         csum_cap[0x1];
751	u8         vlan_cap[0x1];
752	u8         lro_cap[0x1];
753	u8         lro_psh_flag[0x1];
754	u8         lro_time_stamp[0x1];
755	u8         lro_max_msg_sz_mode[0x2];
756	u8         wqe_vlan_insert[0x1];
757	u8         self_lb_en_modifiable[0x1];
758	u8         self_lb_mc[0x1];
759	u8         self_lb_uc[0x1];
760	u8         max_lso_cap[0x5];
761	u8         multi_pkt_send_wqe[0x2];
762	u8         wqe_inline_mode[0x2];
763	u8         rss_ind_tbl_cap[0x4];
764	u8         scatter_fcs[0x1];
765	u8         reserved_1[0x2];
766	u8         tunnel_lso_const_out_ip_id[0x1];
767	u8         tunnel_lro_gre[0x1];
768	u8         tunnel_lro_vxlan[0x1];
769	u8         tunnel_statless_gre[0x1];
770	u8         tunnel_stateless_vxlan[0x1];
771
772	u8         swp[0x1];
773	u8         swp_csum[0x1];
774	u8         swp_lso[0x1];
775	u8         reserved_2[0x1b];
776	u8         max_geneve_opt_len[0x1];
777	u8         tunnel_stateless_geneve_rx[0x1];
778
779	u8         reserved_3[0x10];
780	u8         lro_min_mss_size[0x10];
781
782	u8         reserved_4[0x120];
783
784	u8         lro_timer_supported_periods[4][0x20];
785
786	u8         reserved_5[0x600];
787};
788
789enum {
790	MLX5_ROCE_CAP_L3_TYPE_GRH   = 0x1,
791	MLX5_ROCE_CAP_L3_TYPE_IPV4  = 0x2,
792	MLX5_ROCE_CAP_L3_TYPE_IPV6  = 0x4,
793};
794
795struct mlx5_ifc_roce_cap_bits {
796	u8         roce_apm[0x1];
797	u8         rts2rts_primary_eth_prio[0x1];
798	u8         roce_rx_allow_untagged[0x1];
799	u8         rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1];
800
801	u8         reserved_0[0x1c];
802
803	u8         reserved_1[0x60];
804
805	u8         reserved_2[0xc];
806	u8         l3_type[0x4];
807	u8         reserved_3[0x8];
808	u8         roce_version[0x8];
809
810	u8         reserved_4[0x10];
811	u8         r_roce_dest_udp_port[0x10];
812
813	u8         r_roce_max_src_udp_port[0x10];
814	u8         r_roce_min_src_udp_port[0x10];
815
816	u8         reserved_5[0x10];
817	u8         roce_address_table_size[0x10];
818
819	u8         reserved_6[0x700];
820};
821
822enum {
823	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x1,
824	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
825	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
826	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
827	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
828	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
829	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
830	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
831	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
832};
833
834enum {
835	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
836	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
837	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
838	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
839	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
840	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
841	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
842	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
843	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
844};
845
846struct mlx5_ifc_atomic_caps_bits {
847	u8         reserved_0[0x40];
848
849	u8         atomic_req_8B_endianess_mode[0x2];
850	u8         reserved_1[0x4];
851	u8         supported_atomic_req_8B_endianess_mode_1[0x1];
852
853	u8         reserved_2[0x19];
854
855	u8         reserved_3[0x20];
856
857	u8         reserved_4[0x10];
858	u8         atomic_operations[0x10];
859
860	u8         reserved_5[0x10];
861	u8         atomic_size_qp[0x10];
862
863	u8         reserved_6[0x10];
864	u8         atomic_size_dc[0x10];
865
866	u8         reserved_7[0x720];
867};
868
869struct mlx5_ifc_odp_cap_bits {
870	u8         reserved_0[0x40];
871
872	u8         sig[0x1];
873	u8         reserved_1[0x1f];
874
875	u8         reserved_2[0x20];
876
877	struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
878
879	struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
880
881	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
882
883	struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
884
885	struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
886
887	u8         reserved_3[0x6e0];
888};
889
890enum {
891	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
892	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
893	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
894	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
895	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
896};
897
898enum {
899	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
900	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
901	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
902	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
903	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
904	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
905};
906
907enum {
908	MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
909	MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
910};
911
912enum {
913	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
914	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
915	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
916};
917
918struct mlx5_ifc_cmd_hca_cap_bits {
919	u8         reserved_0[0x80];
920
921	u8         log_max_srq_sz[0x8];
922	u8         log_max_qp_sz[0x8];
923	u8         reserved_1[0xb];
924	u8         log_max_qp[0x5];
925
926	u8         reserved_2[0xb];
927	u8         log_max_srq[0x5];
928	u8         reserved_3[0x10];
929
930	u8         reserved_4[0x8];
931	u8         log_max_cq_sz[0x8];
932	u8         reserved_5[0xb];
933	u8         log_max_cq[0x5];
934
935	u8         log_max_eq_sz[0x8];
936	u8         reserved_6[0x2];
937	u8         log_max_mkey[0x6];
938	u8         reserved_7[0xc];
939	u8         log_max_eq[0x4];
940
941	u8         max_indirection[0x8];
942	u8         reserved_8[0x1];
943	u8         log_max_mrw_sz[0x7];
944	u8         reserved_9[0x2];
945	u8         log_max_bsf_list_size[0x6];
946	u8         reserved_10[0x2];
947	u8         log_max_klm_list_size[0x6];
948
949	u8         reserved_11[0xa];
950	u8         log_max_ra_req_dc[0x6];
951	u8         reserved_12[0xa];
952	u8         log_max_ra_res_dc[0x6];
953
954	u8         reserved_13[0xa];
955	u8         log_max_ra_req_qp[0x6];
956	u8         reserved_14[0xa];
957	u8         log_max_ra_res_qp[0x6];
958
959	u8         pad_cap[0x1];
960	u8         cc_query_allowed[0x1];
961	u8         cc_modify_allowed[0x1];
962	u8         start_pad[0x1];
963	u8         cache_line_128byte[0x1];
964	u8         reserved_15[0xb];
965	u8         gid_table_size[0x10];
966
967	u8         out_of_seq_cnt[0x1];
968	u8         vport_counters[0x1];
969	u8         retransmission_q_counters[0x1];
970	u8         debug[0x1];
971	u8         modify_rq_counters_set_id[0x1];
972	u8         rq_delay_drop[0x1];
973	u8         max_qp_cnt[0xa];
974	u8         pkey_table_size[0x10];
975
976	u8         vport_group_manager[0x1];
977	u8         vhca_group_manager[0x1];
978	u8         ib_virt[0x1];
979	u8         eth_virt[0x1];
980	u8         reserved_17[0x1];
981	u8         ets[0x1];
982	u8         nic_flow_table[0x1];
983	u8         eswitch_flow_table[0x1];
984	u8         reserved_18[0x3];
985	u8         local_ca_ack_delay[0x5];
986	u8         port_module_event[0x1];
987	u8         reserved_19[0x5];
988	u8         port_type[0x2];
989	u8         num_ports[0x8];
990
991	u8         snapshot[0x1];
992	u8         reserved_20[0x2];
993	u8         log_max_msg[0x5];
994	u8         reserved_21[0x4];
995	u8         max_tc[0x4];
996	u8         temp_warn_event[0x1];
997	u8         dcbx[0x1];
998	u8         reserved_22[0x4];
999	u8         rol_s[0x1];
1000	u8         rol_g[0x1];
1001	u8         reserved_23[0x1];
1002	u8         wol_s[0x1];
1003	u8         wol_g[0x1];
1004	u8         wol_a[0x1];
1005	u8         wol_b[0x1];
1006	u8         wol_m[0x1];
1007	u8         wol_u[0x1];
1008	u8         wol_p[0x1];
1009
1010	u8         stat_rate_support[0x10];
1011	u8         reserved_24[0xc];
1012	u8         cqe_version[0x4];
1013
1014	u8         compact_address_vector[0x1];
1015	u8         striding_rq[0x1];
1016	u8         reserved_25[0x1];
1017	u8         ipoib_enhanced_offloads[0x1];
1018	u8         ipoib_ipoib_offloads[0x1];
1019	u8         reserved_26[0x8];
1020	u8         dc_connect_qp[0x1];
1021	u8         dc_cnak_trace[0x1];
1022	u8         drain_sigerr[0x1];
1023	u8         cmdif_checksum[0x2];
1024	u8         sigerr_cqe[0x1];
1025	u8         reserved_27[0x1];
1026	u8         wq_signature[0x1];
1027	u8         sctr_data_cqe[0x1];
1028	u8         reserved_28[0x1];
1029	u8         sho[0x1];
1030	u8         tph[0x1];
1031	u8         rf[0x1];
1032	u8         dct[0x1];
1033	u8         qos[0x1];
1034	u8         eth_net_offloads[0x1];
1035	u8         roce[0x1];
1036	u8         atomic[0x1];
1037	u8         reserved_30[0x1];
1038
1039	u8         cq_oi[0x1];
1040	u8         cq_resize[0x1];
1041	u8         cq_moderation[0x1];
1042	u8         cq_period_mode_modify[0x1];
1043	u8         cq_invalidate[0x1];
1044	u8         reserved_at_225[0x1];
1045	u8         cq_eq_remap[0x1];
1046	u8         pg[0x1];
1047	u8         block_lb_mc[0x1];
1048	u8         exponential_backoff[0x1];
1049	u8         scqe_break_moderation[0x1];
1050	u8         cq_period_start_from_cqe[0x1];
1051	u8         cd[0x1];
1052	u8         atm[0x1];
1053	u8         apm[0x1];
1054	u8	   imaicl[0x1];
1055	u8         reserved_32[0x6];
1056	u8         qkv[0x1];
1057	u8         pkv[0x1];
1058	u8	   set_deth_sqpn[0x1];
1059	u8         reserved_33[0x3];
1060	u8         xrc[0x1];
1061	u8         ud[0x1];
1062	u8         uc[0x1];
1063	u8         rc[0x1];
1064
1065	u8         reserved_34[0xa];
1066	u8         uar_sz[0x6];
1067	u8         reserved_35[0x8];
1068	u8         log_pg_sz[0x8];
1069
1070	u8         bf[0x1];
1071	u8         driver_version[0x1];
1072	u8         pad_tx_eth_packet[0x1];
1073	u8         reserved_36[0x8];
1074	u8         log_bf_reg_size[0x5];
1075	u8         reserved_37[0x10];
1076
1077	u8         num_of_diagnostic_counters[0x10];
1078	u8         max_wqe_sz_sq[0x10];
1079
1080	u8         reserved_38[0x10];
1081	u8         max_wqe_sz_rq[0x10];
1082
1083	u8         reserved_39[0x10];
1084	u8         max_wqe_sz_sq_dc[0x10];
1085
1086	u8         reserved_40[0x7];
1087	u8         max_qp_mcg[0x19];
1088
1089	u8         reserved_41[0x18];
1090	u8         log_max_mcg[0x8];
1091
1092	u8         reserved_42[0x3];
1093	u8         log_max_transport_domain[0x5];
1094	u8         reserved_43[0x3];
1095	u8         log_max_pd[0x5];
1096	u8         reserved_44[0xb];
1097	u8         log_max_xrcd[0x5];
1098
1099	u8         reserved_45[0x10];
1100	u8         max_flow_counter[0x10];
1101
1102	u8         reserved_46[0x3];
1103	u8         log_max_rq[0x5];
1104	u8         reserved_47[0x3];
1105	u8         log_max_sq[0x5];
1106	u8         reserved_48[0x3];
1107	u8         log_max_tir[0x5];
1108	u8         reserved_49[0x3];
1109	u8         log_max_tis[0x5];
1110
1111	u8         basic_cyclic_rcv_wqe[0x1];
1112	u8         reserved_50[0x2];
1113	u8         log_max_rmp[0x5];
1114	u8         reserved_51[0x3];
1115	u8         log_max_rqt[0x5];
1116	u8         reserved_52[0x3];
1117	u8         log_max_rqt_size[0x5];
1118	u8         reserved_53[0x3];
1119	u8         log_max_tis_per_sq[0x5];
1120
1121	u8         reserved_54[0x3];
1122	u8         log_max_stride_sz_rq[0x5];
1123	u8         reserved_55[0x3];
1124	u8         log_min_stride_sz_rq[0x5];
1125	u8         reserved_56[0x3];
1126	u8         log_max_stride_sz_sq[0x5];
1127	u8         reserved_57[0x3];
1128	u8         log_min_stride_sz_sq[0x5];
1129
1130	u8         reserved_58[0x1b];
1131	u8         log_max_wq_sz[0x5];
1132
1133	u8         nic_vport_change_event[0x1];
1134	u8         disable_local_lb[0x1];
1135	u8         reserved_59[0x9];
1136	u8         log_max_vlan_list[0x5];
1137	u8         reserved_60[0x3];
1138	u8         log_max_current_mc_list[0x5];
1139	u8         reserved_61[0x3];
1140	u8         log_max_current_uc_list[0x5];
1141
1142	u8         reserved_62[0x80];
1143
1144	u8         reserved_63[0x3];
1145	u8         log_max_l2_table[0x5];
1146	u8         reserved_64[0x8];
1147	u8         log_uar_page_sz[0x10];
1148
1149	u8         reserved_65[0x20];
1150
1151	u8         device_frequency_mhz[0x20];
1152
1153	u8         device_frequency_khz[0x20];
1154
1155	u8         reserved_66[0x80];
1156
1157	u8         log_max_atomic_size_qp[0x8];
1158	u8         reserved_67[0x10];
1159	u8         log_max_atomic_size_dc[0x8];
1160
1161	u8         reserved_68[0x1f];
1162	u8         cqe_compression[0x1];
1163
1164	u8         cqe_compression_timeout[0x10];
1165	u8         cqe_compression_max_num[0x10];
1166
1167	u8         reserved_69[0x220];
1168};
1169
1170enum mlx5_flow_destination_type {
1171	MLX5_FLOW_DESTINATION_TYPE_VPORT	= 0x0,
1172	MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE	= 0x1,
1173	MLX5_FLOW_DESTINATION_TYPE_TIR		= 0x2,
1174};
1175
1176union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1177	struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1178	struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1179	u8         reserved_0[0x40];
1180};
1181
1182struct mlx5_ifc_fte_match_param_bits {
1183	struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1184
1185	struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1186
1187	struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1188
1189	u8         reserved_0[0xa00];
1190};
1191
1192enum {
1193	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1194	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1195	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1196	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1197	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1198};
1199
1200struct mlx5_ifc_rx_hash_field_select_bits {
1201	u8         l3_prot_type[0x1];
1202	u8         l4_prot_type[0x1];
1203	u8         selected_fields[0x1e];
1204};
1205
1206enum {
1207	MLX5_WQ_TYPE_LINKED_LIST                 = 0x0,
1208	MLX5_WQ_TYPE_CYCLIC                      = 0x1,
1209	MLX5_WQ_TYPE_STRQ_LINKED_LIST            = 0x2,
1210	MLX5_WQ_TYPE_STRQ_CYCLIC                 = 0x3,
1211};
1212
1213enum rq_type {
1214	RQ_TYPE_NONE,
1215	RQ_TYPE_STRIDE,
1216};
1217
1218enum {
1219	MLX5_WQ_END_PAD_MODE_NONE               = 0x0,
1220	MLX5_WQ_END_PAD_MODE_ALIGN              = 0x1,
1221};
1222
1223struct mlx5_ifc_wq_bits {
1224	u8         wq_type[0x4];
1225	u8         wq_signature[0x1];
1226	u8         end_padding_mode[0x2];
1227	u8         cd_slave[0x1];
1228	u8         reserved_0[0x18];
1229
1230	u8         hds_skip_first_sge[0x1];
1231	u8         log2_hds_buf_size[0x3];
1232	u8         reserved_1[0x7];
1233	u8         page_offset[0x5];
1234	u8         lwm[0x10];
1235
1236	u8         reserved_2[0x8];
1237	u8         pd[0x18];
1238
1239	u8         reserved_3[0x8];
1240	u8         uar_page[0x18];
1241
1242	u8         dbr_addr[0x40];
1243
1244	u8         hw_counter[0x20];
1245
1246	u8         sw_counter[0x20];
1247
1248	u8         reserved_4[0xc];
1249	u8         log_wq_stride[0x4];
1250	u8         reserved_5[0x3];
1251	u8         log_wq_pg_sz[0x5];
1252	u8         reserved_6[0x3];
1253	u8         log_wq_sz[0x5];
1254
1255	u8         reserved_7[0x15];
1256	u8         single_wqe_log_num_of_strides[0x3];
1257	u8         two_byte_shift_en[0x1];
1258	u8         reserved_8[0x4];
1259	u8         single_stride_log_num_of_bytes[0x3];
1260
1261	u8         reserved_9[0x4c0];
1262
1263	struct mlx5_ifc_cmd_pas_bits pas[0];
1264};
1265
1266struct mlx5_ifc_rq_num_bits {
1267	u8         reserved_0[0x8];
1268	u8         rq_num[0x18];
1269};
1270
1271struct mlx5_ifc_mac_address_layout_bits {
1272	u8         reserved_0[0x10];
1273	u8         mac_addr_47_32[0x10];
1274
1275	u8         mac_addr_31_0[0x20];
1276};
1277
1278struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1279	u8         reserved_0[0xa0];
1280
1281	u8         min_time_between_cnps[0x20];
1282
1283	u8         reserved_1[0x12];
1284	u8         cnp_dscp[0x6];
1285	u8         reserved_2[0x4];
1286	u8         cnp_prio_mode[0x1];
1287	u8         cnp_802p_prio[0x3];
1288
1289	u8         reserved_3[0x720];
1290};
1291
1292struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1293	u8         reserved_0[0x60];
1294
1295	u8         reserved_1[0x4];
1296	u8         clamp_tgt_rate[0x1];
1297	u8         reserved_2[0x3];
1298	u8         clamp_tgt_rate_after_time_inc[0x1];
1299	u8         reserved_3[0x17];
1300
1301	u8         reserved_4[0x20];
1302
1303	u8         rpg_time_reset[0x20];
1304
1305	u8         rpg_byte_reset[0x20];
1306
1307	u8         rpg_threshold[0x20];
1308
1309	u8         rpg_max_rate[0x20];
1310
1311	u8         rpg_ai_rate[0x20];
1312
1313	u8         rpg_hai_rate[0x20];
1314
1315	u8         rpg_gd[0x20];
1316
1317	u8         rpg_min_dec_fac[0x20];
1318
1319	u8         rpg_min_rate[0x20];
1320
1321	u8         reserved_5[0xe0];
1322
1323	u8         rate_to_set_on_first_cnp[0x20];
1324
1325	u8         dce_tcp_g[0x20];
1326
1327	u8         dce_tcp_rtt[0x20];
1328
1329	u8         rate_reduce_monitor_period[0x20];
1330
1331	u8         reserved_6[0x20];
1332
1333	u8         initial_alpha_value[0x20];
1334
1335	u8         reserved_7[0x4a0];
1336};
1337
1338struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1339	u8         reserved_0[0x80];
1340
1341	u8         rppp_max_rps[0x20];
1342
1343	u8         rpg_time_reset[0x20];
1344
1345	u8         rpg_byte_reset[0x20];
1346
1347	u8         rpg_threshold[0x20];
1348
1349	u8         rpg_max_rate[0x20];
1350
1351	u8         rpg_ai_rate[0x20];
1352
1353	u8         rpg_hai_rate[0x20];
1354
1355	u8         rpg_gd[0x20];
1356
1357	u8         rpg_min_dec_fac[0x20];
1358
1359	u8         rpg_min_rate[0x20];
1360
1361	u8         reserved_1[0x640];
1362};
1363
1364enum {
1365	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1366	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1367	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1368};
1369
1370struct mlx5_ifc_resize_field_select_bits {
1371	u8         resize_field_select[0x20];
1372};
1373
1374enum {
1375	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1376	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1377	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1378	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1379	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE  = 0x10,
1380	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS          = 0x20,
1381};
1382
1383struct mlx5_ifc_modify_field_select_bits {
1384	u8         modify_field_select[0x20];
1385};
1386
1387struct mlx5_ifc_field_select_r_roce_np_bits {
1388	u8         field_select_r_roce_np[0x20];
1389};
1390
1391enum {
1392	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE                 = 0x2,
1393	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC  = 0x4,
1394	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET                 = 0x8,
1395	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET                 = 0x10,
1396	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD                  = 0x20,
1397	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE                   = 0x40,
1398	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE                    = 0x80,
1399	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE                   = 0x100,
1400	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC                = 0x200,
1401	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE                   = 0x400,
1402	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP       = 0x800,
1403	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G                      = 0x1000,
1404	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT                    = 0x2000,
1405	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD     = 0x4000,
1406	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE            = 0x8000,
1407};
1408
1409struct mlx5_ifc_field_select_r_roce_rp_bits {
1410	u8         field_select_r_roce_rp[0x20];
1411};
1412
1413enum {
1414	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1415	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1416	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1417	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1418	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1419	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1420	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1421	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1422	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1423	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1424};
1425
1426struct mlx5_ifc_field_select_802_1qau_rp_bits {
1427	u8         field_select_8021qaurp[0x20];
1428};
1429
1430struct mlx5_ifc_pptb_reg_bits {
1431	u8         reserved_0[0x2];
1432	u8         mm[0x2];
1433	u8         reserved_1[0x4];
1434	u8         local_port[0x8];
1435	u8         reserved_2[0x6];
1436	u8         cm[0x1];
1437	u8         um[0x1];
1438	u8         pm[0x8];
1439
1440	u8         prio7buff[0x4];
1441	u8         prio6buff[0x4];
1442	u8         prio5buff[0x4];
1443	u8         prio4buff[0x4];
1444	u8         prio3buff[0x4];
1445	u8         prio2buff[0x4];
1446	u8         prio1buff[0x4];
1447	u8         prio0buff[0x4];
1448
1449	u8         pm_msb[0x8];
1450	u8         reserved_3[0x10];
1451	u8         ctrl_buff[0x4];
1452	u8         untagged_buff[0x4];
1453};
1454
1455struct mlx5_ifc_dcbx_app_reg_bits {
1456	u8         reserved_0[0x8];
1457	u8         port_number[0x8];
1458	u8         reserved_1[0x10];
1459
1460	u8         reserved_2[0x1a];
1461	u8         num_app_prio[0x6];
1462
1463	u8         reserved_3[0x40];
1464
1465	struct mlx5_ifc_application_prio_entry_bits app_prio[0];
1466};
1467
1468struct mlx5_ifc_dcbx_param_reg_bits {
1469	u8         dcbx_cee_cap[0x1];
1470	u8         dcbx_ieee_cap[0x1];
1471	u8         dcbx_standby_cap[0x1];
1472	u8         reserved_0[0x5];
1473	u8         port_number[0x8];
1474	u8         reserved_1[0xa];
1475	u8         max_application_table_size[0x6];
1476
1477	u8         reserved_2[0x15];
1478	u8         version_oper[0x3];
1479	u8         reserved_3[0x5];
1480	u8         version_admin[0x3];
1481
1482	u8         willing_admin[0x1];
1483	u8         reserved_4[0x3];
1484	u8         pfc_cap_oper[0x4];
1485	u8         reserved_5[0x4];
1486	u8         pfc_cap_admin[0x4];
1487	u8         reserved_6[0x4];
1488	u8         num_of_tc_oper[0x4];
1489	u8         reserved_7[0x4];
1490	u8         num_of_tc_admin[0x4];
1491
1492	u8         remote_willing[0x1];
1493	u8         reserved_8[0x3];
1494	u8         remote_pfc_cap[0x4];
1495	u8         reserved_9[0x14];
1496	u8         remote_num_of_tc[0x4];
1497
1498	u8         reserved_10[0x18];
1499	u8         error[0x8];
1500
1501	u8         reserved_11[0x160];
1502};
1503
1504struct mlx5_ifc_qhll_bits {
1505	u8         reserved_at_0[0x8];
1506	u8         local_port[0x8];
1507	u8         reserved_at_10[0x10];
1508
1509	u8         reserved_at_20[0x1b];
1510	u8         hll_time[0x5];
1511
1512	u8         stall_en[0x1];
1513	u8         reserved_at_41[0x1c];
1514	u8         stall_cnt[0x3];
1515};
1516
1517struct mlx5_ifc_qetcr_reg_bits {
1518	u8         operation_type[0x2];
1519	u8         cap_local_admin[0x1];
1520	u8         cap_remote_admin[0x1];
1521	u8         reserved_0[0x4];
1522	u8         port_number[0x8];
1523	u8         reserved_1[0x10];
1524
1525	u8         reserved_2[0x20];
1526
1527	u8         tc[8][0x40];
1528
1529	u8         global_configuration[0x40];
1530};
1531
1532struct mlx5_ifc_nodnic_ring_config_reg_bits {
1533	u8         queue_address_63_32[0x20];
1534
1535	u8         queue_address_31_12[0x14];
1536	u8         reserved_0[0x6];
1537	u8         log_size[0x6];
1538
1539	struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell;
1540
1541	u8         reserved_1[0x8];
1542	u8         queue_number[0x18];
1543
1544	u8         q_key[0x20];
1545
1546	u8         reserved_2[0x10];
1547	u8         pkey_index[0x10];
1548
1549	u8         reserved_3[0x40];
1550};
1551
1552struct mlx5_ifc_nodnic_cq_arming_word_bits {
1553	u8         reserved_0[0x8];
1554	u8         cq_ci[0x10];
1555	u8         reserved_1[0x8];
1556};
1557
1558enum {
1559	MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND  = 0x0,
1560	MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET    = 0x1,
1561};
1562
1563enum {
1564	MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN        = 0x0,
1565	MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE  = 0x1,
1566	MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED       = 0x2,
1567	MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE      = 0x3,
1568};
1569
1570struct mlx5_ifc_nodnic_event_word_bits {
1571	u8         driver_reset_needed[0x1];
1572	u8         port_management_change_event[0x1];
1573	u8         reserved_0[0x19];
1574	u8         link_type[0x1];
1575	u8         port_state[0x4];
1576};
1577
1578struct mlx5_ifc_nic_vport_change_event_bits {
1579	u8         reserved_0[0x10];
1580	u8         vport_num[0x10];
1581
1582	u8         reserved_1[0xc0];
1583};
1584
1585struct mlx5_ifc_pages_req_event_bits {
1586	u8         reserved_0[0x10];
1587	u8         function_id[0x10];
1588
1589	u8         num_pages[0x20];
1590
1591	u8         reserved_1[0xa0];
1592};
1593
1594struct mlx5_ifc_cmd_inter_comp_event_bits {
1595	u8         command_completion_vector[0x20];
1596
1597	u8         reserved_0[0xc0];
1598};
1599
1600struct mlx5_ifc_stall_vl_event_bits {
1601	u8         reserved_0[0x18];
1602	u8         port_num[0x1];
1603	u8         reserved_1[0x3];
1604	u8         vl[0x4];
1605
1606	u8         reserved_2[0xa0];
1607};
1608
1609struct mlx5_ifc_db_bf_congestion_event_bits {
1610	u8         event_subtype[0x8];
1611	u8         reserved_0[0x8];
1612	u8         congestion_level[0x8];
1613	u8         reserved_1[0x8];
1614
1615	u8         reserved_2[0xa0];
1616};
1617
1618struct mlx5_ifc_gpio_event_bits {
1619	u8         reserved_0[0x60];
1620
1621	u8         gpio_event_hi[0x20];
1622
1623	u8         gpio_event_lo[0x20];
1624
1625	u8         reserved_1[0x40];
1626};
1627
1628struct mlx5_ifc_port_state_change_event_bits {
1629	u8         reserved_0[0x40];
1630
1631	u8         port_num[0x4];
1632	u8         reserved_1[0x1c];
1633
1634	u8         reserved_2[0x80];
1635};
1636
1637struct mlx5_ifc_dropped_packet_logged_bits {
1638	u8         reserved_0[0xe0];
1639};
1640
1641enum {
1642	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1643	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1644};
1645
1646struct mlx5_ifc_cq_error_bits {
1647	u8         reserved_0[0x8];
1648	u8         cqn[0x18];
1649
1650	u8         reserved_1[0x20];
1651
1652	u8         reserved_2[0x18];
1653	u8         syndrome[0x8];
1654
1655	u8         reserved_3[0x80];
1656};
1657
1658struct mlx5_ifc_rdma_page_fault_event_bits {
1659	u8         bytes_commited[0x20];
1660
1661	u8         r_key[0x20];
1662
1663	u8         reserved_0[0x10];
1664	u8         packet_len[0x10];
1665
1666	u8         rdma_op_len[0x20];
1667
1668	u8         rdma_va[0x40];
1669
1670	u8         reserved_1[0x5];
1671	u8         rdma[0x1];
1672	u8         write[0x1];
1673	u8         requestor[0x1];
1674	u8         qp_number[0x18];
1675};
1676
1677struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1678	u8         bytes_committed[0x20];
1679
1680	u8         reserved_0[0x10];
1681	u8         wqe_index[0x10];
1682
1683	u8         reserved_1[0x10];
1684	u8         len[0x10];
1685
1686	u8         reserved_2[0x60];
1687
1688	u8         reserved_3[0x5];
1689	u8         rdma[0x1];
1690	u8         write_read[0x1];
1691	u8         requestor[0x1];
1692	u8         qpn[0x18];
1693};
1694
1695enum {
1696	MLX5_QP_EVENTS_TYPE_QP  = 0x0,
1697	MLX5_QP_EVENTS_TYPE_RQ  = 0x1,
1698	MLX5_QP_EVENTS_TYPE_SQ  = 0x2,
1699};
1700
1701struct mlx5_ifc_qp_events_bits {
1702	u8         reserved_0[0xa0];
1703
1704	u8         type[0x8];
1705	u8         reserved_1[0x18];
1706
1707	u8         reserved_2[0x8];
1708	u8         qpn_rqn_sqn[0x18];
1709};
1710
1711struct mlx5_ifc_dct_events_bits {
1712	u8         reserved_0[0xc0];
1713
1714	u8         reserved_1[0x8];
1715	u8         dct_number[0x18];
1716};
1717
1718struct mlx5_ifc_comp_event_bits {
1719	u8         reserved_0[0xc0];
1720
1721	u8         reserved_1[0x8];
1722	u8         cq_number[0x18];
1723};
1724
1725struct mlx5_ifc_fw_version_bits {
1726	u8         major[0x10];
1727	u8         reserved_0[0x10];
1728
1729	u8         minor[0x10];
1730	u8         subminor[0x10];
1731
1732	u8         second[0x8];
1733	u8         minute[0x8];
1734	u8         hour[0x8];
1735	u8         reserved_1[0x8];
1736
1737	u8         year[0x10];
1738	u8         month[0x8];
1739	u8         day[0x8];
1740};
1741
1742enum {
1743	MLX5_QPC_STATE_RST        = 0x0,
1744	MLX5_QPC_STATE_INIT       = 0x1,
1745	MLX5_QPC_STATE_RTR        = 0x2,
1746	MLX5_QPC_STATE_RTS        = 0x3,
1747	MLX5_QPC_STATE_SQER       = 0x4,
1748	MLX5_QPC_STATE_SQD        = 0x5,
1749	MLX5_QPC_STATE_ERR        = 0x6,
1750	MLX5_QPC_STATE_SUSPENDED  = 0x9,
1751};
1752
1753enum {
1754	MLX5_QPC_ST_RC            = 0x0,
1755	MLX5_QPC_ST_UC            = 0x1,
1756	MLX5_QPC_ST_UD            = 0x2,
1757	MLX5_QPC_ST_XRC           = 0x3,
1758	MLX5_QPC_ST_DCI           = 0x5,
1759	MLX5_QPC_ST_QP0           = 0x7,
1760	MLX5_QPC_ST_QP1           = 0x8,
1761	MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1762	MLX5_QPC_ST_REG_UMR       = 0xc,
1763};
1764
1765enum {
1766	MLX5_QP_PM_ARMED            = 0x0,
1767	MLX5_QP_PM_REARM            = 0x1,
1768	MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1769	MLX5_QP_PM_MIGRATED         = 0x3,
1770};
1771
1772enum {
1773	MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1774	MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1775};
1776
1777enum {
1778	MLX5_QPC_MTU_256_BYTES        = 0x1,
1779	MLX5_QPC_MTU_512_BYTES        = 0x2,
1780	MLX5_QPC_MTU_1K_BYTES         = 0x3,
1781	MLX5_QPC_MTU_2K_BYTES         = 0x4,
1782	MLX5_QPC_MTU_4K_BYTES         = 0x5,
1783	MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1784};
1785
1786enum {
1787	MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1788	MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1789	MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1790	MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1791	MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1792	MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1793	MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1794	MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1795};
1796
1797enum {
1798	MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1799	MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1800	MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1801};
1802
1803enum {
1804	MLX5_QPC_CS_RES_DISABLE    = 0x0,
1805	MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1806	MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1807};
1808
1809struct mlx5_ifc_qpc_bits {
1810	u8         state[0x4];
1811	u8         lag_tx_port_affinity[0x4];
1812	u8         st[0x8];
1813	u8         reserved_1[0x3];
1814	u8         pm_state[0x2];
1815	u8         reserved_2[0x7];
1816	u8         end_padding_mode[0x2];
1817	u8         reserved_3[0x2];
1818
1819	u8         wq_signature[0x1];
1820	u8         block_lb_mc[0x1];
1821	u8         atomic_like_write_en[0x1];
1822	u8         latency_sensitive[0x1];
1823	u8         reserved_4[0x1];
1824	u8         drain_sigerr[0x1];
1825	u8         reserved_5[0x2];
1826	u8         pd[0x18];
1827
1828	u8         mtu[0x3];
1829	u8         log_msg_max[0x5];
1830	u8         reserved_6[0x1];
1831	u8         log_rq_size[0x4];
1832	u8         log_rq_stride[0x3];
1833	u8         no_sq[0x1];
1834	u8         log_sq_size[0x4];
1835	u8         reserved_7[0x6];
1836	u8         rlky[0x1];
1837	u8         ulp_stateless_offload_mode[0x4];
1838
1839	u8         counter_set_id[0x8];
1840	u8         uar_page[0x18];
1841
1842	u8         reserved_8[0x8];
1843	u8         user_index[0x18];
1844
1845	u8         reserved_9[0x3];
1846	u8         log_page_size[0x5];
1847	u8         remote_qpn[0x18];
1848
1849	struct mlx5_ifc_ads_bits primary_address_path;
1850
1851	struct mlx5_ifc_ads_bits secondary_address_path;
1852
1853	u8         log_ack_req_freq[0x4];
1854	u8         reserved_10[0x4];
1855	u8         log_sra_max[0x3];
1856	u8         reserved_11[0x2];
1857	u8         retry_count[0x3];
1858	u8         rnr_retry[0x3];
1859	u8         reserved_12[0x1];
1860	u8         fre[0x1];
1861	u8         cur_rnr_retry[0x3];
1862	u8         cur_retry_count[0x3];
1863	u8         reserved_13[0x5];
1864
1865	u8         reserved_14[0x20];
1866
1867	u8         reserved_15[0x8];
1868	u8         next_send_psn[0x18];
1869
1870	u8         reserved_16[0x8];
1871	u8         cqn_snd[0x18];
1872
1873	u8         reserved_at_400[0x8];
1874
1875	u8         deth_sqpn[0x18];
1876	u8         reserved_17[0x20];
1877
1878	u8         reserved_18[0x8];
1879	u8         last_acked_psn[0x18];
1880
1881	u8         reserved_19[0x8];
1882	u8         ssn[0x18];
1883
1884	u8         reserved_20[0x8];
1885	u8         log_rra_max[0x3];
1886	u8         reserved_21[0x1];
1887	u8         atomic_mode[0x4];
1888	u8         rre[0x1];
1889	u8         rwe[0x1];
1890	u8         rae[0x1];
1891	u8         reserved_22[0x1];
1892	u8         page_offset[0x6];
1893	u8         reserved_23[0x3];
1894	u8         cd_slave_receive[0x1];
1895	u8         cd_slave_send[0x1];
1896	u8         cd_master[0x1];
1897
1898	u8         reserved_24[0x3];
1899	u8         min_rnr_nak[0x5];
1900	u8         next_rcv_psn[0x18];
1901
1902	u8         reserved_25[0x8];
1903	u8         xrcd[0x18];
1904
1905	u8         reserved_26[0x8];
1906	u8         cqn_rcv[0x18];
1907
1908	u8         dbr_addr[0x40];
1909
1910	u8         q_key[0x20];
1911
1912	u8         reserved_27[0x5];
1913	u8         rq_type[0x3];
1914	u8         srqn_rmpn[0x18];
1915
1916	u8         reserved_28[0x8];
1917	u8         rmsn[0x18];
1918
1919	u8         hw_sq_wqebb_counter[0x10];
1920	u8         sw_sq_wqebb_counter[0x10];
1921
1922	u8         hw_rq_counter[0x20];
1923
1924	u8         sw_rq_counter[0x20];
1925
1926	u8         reserved_29[0x20];
1927
1928	u8         reserved_30[0xf];
1929	u8         cgs[0x1];
1930	u8         cs_req[0x8];
1931	u8         cs_res[0x8];
1932
1933	u8         dc_access_key[0x40];
1934
1935	u8         rdma_active[0x1];
1936	u8         comm_est[0x1];
1937	u8         suspended[0x1];
1938	u8         reserved_31[0x5];
1939	u8         send_msg_psn[0x18];
1940
1941	u8         reserved_32[0x8];
1942	u8         rcv_msg_psn[0x18];
1943
1944	u8         rdma_va[0x40];
1945
1946	u8         rdma_key[0x20];
1947
1948	u8         reserved_33[0x20];
1949};
1950
1951struct mlx5_ifc_roce_addr_layout_bits {
1952	u8         source_l3_address[16][0x8];
1953
1954	u8         reserved_0[0x3];
1955	u8         vlan_valid[0x1];
1956	u8         vlan_id[0xc];
1957	u8         source_mac_47_32[0x10];
1958
1959	u8         source_mac_31_0[0x20];
1960
1961	u8         reserved_1[0x14];
1962	u8         roce_l3_type[0x4];
1963	u8         roce_version[0x8];
1964
1965	u8         reserved_2[0x20];
1966};
1967
1968struct mlx5_ifc_rdbc_bits {
1969	u8         reserved_0[0x1c];
1970	u8         type[0x4];
1971
1972	u8         reserved_1[0x20];
1973
1974	u8         reserved_2[0x8];
1975	u8         psn[0x18];
1976
1977	u8         rkey[0x20];
1978
1979	u8         address[0x40];
1980
1981	u8         byte_count[0x20];
1982
1983	u8         reserved_3[0x20];
1984
1985	u8         atomic_resp[32][0x8];
1986};
1987
1988enum {
1989	MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
1990	MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
1991	MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
1992	MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
1993};
1994
1995struct mlx5_ifc_flow_context_bits {
1996	u8         reserved_0[0x20];
1997
1998	u8         group_id[0x20];
1999
2000	u8         reserved_1[0x8];
2001	u8         flow_tag[0x18];
2002
2003	u8         reserved_2[0x10];
2004	u8         action[0x10];
2005
2006	u8         reserved_3[0x8];
2007	u8         destination_list_size[0x18];
2008
2009	u8         reserved_4[0x8];
2010	u8         flow_counter_list_size[0x18];
2011
2012	u8         reserved_5[0x140];
2013
2014	struct mlx5_ifc_fte_match_param_bits match_value;
2015
2016	u8         reserved_6[0x600];
2017
2018	union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2019};
2020
2021enum {
2022	MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2023	MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2024};
2025
2026struct mlx5_ifc_xrc_srqc_bits {
2027	u8         state[0x4];
2028	u8         log_xrc_srq_size[0x4];
2029	u8         reserved_0[0x18];
2030
2031	u8         wq_signature[0x1];
2032	u8         cont_srq[0x1];
2033	u8         reserved_1[0x1];
2034	u8         rlky[0x1];
2035	u8         basic_cyclic_rcv_wqe[0x1];
2036	u8         log_rq_stride[0x3];
2037	u8         xrcd[0x18];
2038
2039	u8         page_offset[0x6];
2040	u8         reserved_2[0x2];
2041	u8         cqn[0x18];
2042
2043	u8         reserved_3[0x20];
2044
2045	u8         reserved_4[0x2];
2046	u8         log_page_size[0x6];
2047	u8         user_index[0x18];
2048
2049	u8         reserved_5[0x20];
2050
2051	u8         reserved_6[0x8];
2052	u8         pd[0x18];
2053
2054	u8         lwm[0x10];
2055	u8         wqe_cnt[0x10];
2056
2057	u8         reserved_7[0x40];
2058
2059	u8         db_record_addr_h[0x20];
2060
2061	u8         db_record_addr_l[0x1e];
2062	u8         reserved_8[0x2];
2063
2064	u8         reserved_9[0x80];
2065};
2066
2067struct mlx5_ifc_traffic_counter_bits {
2068	u8         packets[0x40];
2069
2070	u8         octets[0x40];
2071};
2072
2073struct mlx5_ifc_tisc_bits {
2074	u8         strict_lag_tx_port_affinity[0x1];
2075	u8         reserved_at_1[0x3];
2076	u8         lag_tx_port_affinity[0x04];
2077
2078	u8         reserved_at_8[0x4];
2079	u8         prio[0x4];
2080	u8         reserved_1[0x10];
2081
2082	u8         reserved_2[0x100];
2083
2084	u8         reserved_3[0x8];
2085	u8         transport_domain[0x18];
2086
2087	u8         reserved_4[0x8];
2088	u8         underlay_qpn[0x18];
2089
2090	u8         reserved_5[0x3a0];
2091};
2092
2093enum {
2094	MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2095	MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2096};
2097
2098enum {
2099	MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2100	MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2101};
2102
2103enum {
2104	MLX5_TIRC_RX_HASH_FN_HASH_NONE           = 0x0,
2105	MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8  = 0x1,
2106	MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ       = 0x2,
2107};
2108
2109enum {
2110	MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST    = 0x1,
2111	MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST  = 0x2,
2112};
2113
2114struct mlx5_ifc_tirc_bits {
2115	u8         reserved_0[0x20];
2116
2117	u8         disp_type[0x4];
2118	u8         reserved_1[0x1c];
2119
2120	u8         reserved_2[0x40];
2121
2122	u8         reserved_3[0x4];
2123	u8         lro_timeout_period_usecs[0x10];
2124	u8         lro_enable_mask[0x4];
2125	u8         lro_max_msg_sz[0x8];
2126
2127	u8         reserved_4[0x40];
2128
2129	u8         reserved_5[0x8];
2130	u8         inline_rqn[0x18];
2131
2132	u8         rx_hash_symmetric[0x1];
2133	u8         reserved_6[0x1];
2134	u8         tunneled_offload_en[0x1];
2135	u8         reserved_7[0x5];
2136	u8         indirect_table[0x18];
2137
2138	u8         rx_hash_fn[0x4];
2139	u8         reserved_8[0x2];
2140	u8         self_lb_en[0x2];
2141	u8         transport_domain[0x18];
2142
2143	u8         rx_hash_toeplitz_key[10][0x20];
2144
2145	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2146
2147	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2148
2149	u8         reserved_9[0x4c0];
2150};
2151
2152enum {
2153	MLX5_SRQC_STATE_GOOD   = 0x0,
2154	MLX5_SRQC_STATE_ERROR  = 0x1,
2155};
2156
2157struct mlx5_ifc_srqc_bits {
2158	u8         state[0x4];
2159	u8         log_srq_size[0x4];
2160	u8         reserved_0[0x18];
2161
2162	u8         wq_signature[0x1];
2163	u8         cont_srq[0x1];
2164	u8         reserved_1[0x1];
2165	u8         rlky[0x1];
2166	u8         reserved_2[0x1];
2167	u8         log_rq_stride[0x3];
2168	u8         xrcd[0x18];
2169
2170	u8         page_offset[0x6];
2171	u8         reserved_3[0x2];
2172	u8         cqn[0x18];
2173
2174	u8         reserved_4[0x20];
2175
2176	u8         reserved_5[0x2];
2177	u8         log_page_size[0x6];
2178	u8         reserved_6[0x18];
2179
2180	u8         reserved_7[0x20];
2181
2182	u8         reserved_8[0x8];
2183	u8         pd[0x18];
2184
2185	u8         lwm[0x10];
2186	u8         wqe_cnt[0x10];
2187
2188	u8         reserved_9[0x40];
2189
2190	u8	   dbr_addr[0x40];
2191
2192	u8	   reserved_10[0x80];
2193};
2194
2195enum {
2196	MLX5_SQC_STATE_RST  = 0x0,
2197	MLX5_SQC_STATE_RDY  = 0x1,
2198	MLX5_SQC_STATE_ERR  = 0x3,
2199};
2200
2201struct mlx5_ifc_sqc_bits {
2202	u8         rlkey[0x1];
2203	u8         cd_master[0x1];
2204	u8         fre[0x1];
2205	u8         flush_in_error_en[0x1];
2206	u8         allow_multi_pkt_send_wqe[0x1];
2207	u8         min_wqe_inline_mode[0x3];
2208	u8         state[0x4];
2209	u8         reg_umr[0x1];
2210	u8         allow_swp[0x1];
2211	u8         reserved_0[0x12];
2212
2213	u8         reserved_1[0x8];
2214	u8         user_index[0x18];
2215
2216	u8         reserved_2[0x8];
2217	u8         cqn[0x18];
2218
2219	u8         reserved_3[0x80];
2220
2221	u8         qos_para_vport_number[0x10];
2222	u8         packet_pacing_rate_limit_index[0x10];
2223
2224	u8         tis_lst_sz[0x10];
2225	u8         reserved_4[0x10];
2226
2227	u8         reserved_5[0x40];
2228
2229	u8         reserved_6[0x8];
2230	u8         tis_num_0[0x18];
2231
2232	struct mlx5_ifc_wq_bits wq;
2233};
2234
2235enum {
2236	MLX5_TSAR_TYPE_DWRR = 0,
2237	MLX5_TSAR_TYPE_ROUND_ROUBIN = 1,
2238	MLX5_TSAR_TYPE_ETS = 2
2239};
2240
2241struct mlx5_ifc_tsar_element_attributes_bits {
2242	u8         reserved_0[0x8];
2243	u8         tsar_type[0x8];
2244	u8	   reserved_1[0x10];
2245};
2246
2247struct mlx5_ifc_vport_element_attributes_bits {
2248	u8         reserved_0[0x10];
2249	u8         vport_number[0x10];
2250};
2251
2252struct mlx5_ifc_vport_tc_element_attributes_bits {
2253	u8         traffic_class[0x10];
2254	u8         vport_number[0x10];
2255};
2256
2257struct mlx5_ifc_para_vport_tc_element_attributes_bits {
2258	u8         reserved_0[0x0C];
2259	u8         traffic_class[0x04];
2260	u8         qos_para_vport_number[0x10];
2261};
2262
2263enum {
2264	MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR           = 0x0,
2265	MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT          = 0x1,
2266	MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC       = 0x2,
2267	MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC  = 0x3,
2268};
2269
2270struct mlx5_ifc_scheduling_context_bits {
2271	u8         element_type[0x8];
2272	u8         reserved_at_8[0x18];
2273
2274	u8         element_attributes[0x20];
2275
2276	u8         parent_element_id[0x20];
2277
2278	u8         reserved_at_60[0x40];
2279
2280	u8         bw_share[0x20];
2281
2282	u8         max_average_bw[0x20];
2283
2284	u8         reserved_at_e0[0x120];
2285};
2286
2287struct mlx5_ifc_rqtc_bits {
2288	u8         reserved_0[0xa0];
2289
2290	u8         reserved_1[0x10];
2291	u8         rqt_max_size[0x10];
2292
2293	u8         reserved_2[0x10];
2294	u8         rqt_actual_size[0x10];
2295
2296	u8         reserved_3[0x6a0];
2297
2298	struct mlx5_ifc_rq_num_bits rq_num[0];
2299};
2300
2301enum {
2302	MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE      = 0x0,
2303	MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP         = 0x1,
2304};
2305
2306enum {
2307	MLX5_RQC_STATE_RST  = 0x0,
2308	MLX5_RQC_STATE_RDY  = 0x1,
2309	MLX5_RQC_STATE_ERR  = 0x3,
2310};
2311
2312enum {
2313	MLX5_RQC_DROPLESS_MODE_DISABLE        = 0x0,
2314	MLX5_RQC_DROPLESS_MODE_ENABLE         = 0x1,
2315};
2316
2317struct mlx5_ifc_rqc_bits {
2318	u8         rlkey[0x1];
2319	u8         delay_drop_en[0x1];
2320	u8         scatter_fcs[0x1];
2321	u8         vlan_strip_disable[0x1];
2322	u8         mem_rq_type[0x4];
2323	u8         state[0x4];
2324	u8         reserved_1[0x1];
2325	u8         flush_in_error_en[0x1];
2326	u8         reserved_2[0x12];
2327
2328	u8         reserved_3[0x8];
2329	u8         user_index[0x18];
2330
2331	u8         reserved_4[0x8];
2332	u8         cqn[0x18];
2333
2334	u8         counter_set_id[0x8];
2335	u8         reserved_5[0x18];
2336
2337	u8         reserved_6[0x8];
2338	u8         rmpn[0x18];
2339
2340	u8         reserved_7[0xe0];
2341
2342	struct mlx5_ifc_wq_bits wq;
2343};
2344
2345enum {
2346	MLX5_RMPC_STATE_RDY  = 0x1,
2347	MLX5_RMPC_STATE_ERR  = 0x3,
2348};
2349
2350struct mlx5_ifc_rmpc_bits {
2351	u8         reserved_0[0x8];
2352	u8         state[0x4];
2353	u8         reserved_1[0x14];
2354
2355	u8         basic_cyclic_rcv_wqe[0x1];
2356	u8         reserved_2[0x1f];
2357
2358	u8         reserved_3[0x140];
2359
2360	struct mlx5_ifc_wq_bits wq;
2361};
2362
2363enum {
2364	MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS  = 0x0,
2365	MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS  = 0x1,
2366	MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST               = 0x2,
2367};
2368
2369struct mlx5_ifc_nic_vport_context_bits {
2370	u8         reserved_0[0x5];
2371	u8         min_wqe_inline_mode[0x3];
2372	u8         reserved_1[0x15];
2373	u8         disable_mc_local_lb[0x1];
2374	u8         disable_uc_local_lb[0x1];
2375	u8         roce_en[0x1];
2376
2377	u8         arm_change_event[0x1];
2378	u8         reserved_2[0x1a];
2379	u8         event_on_mtu[0x1];
2380	u8         event_on_promisc_change[0x1];
2381	u8         event_on_vlan_change[0x1];
2382	u8         event_on_mc_address_change[0x1];
2383	u8         event_on_uc_address_change[0x1];
2384
2385	u8         reserved_3[0xe0];
2386
2387	u8         reserved_4[0x10];
2388	u8         mtu[0x10];
2389
2390	u8         system_image_guid[0x40];
2391
2392	u8         port_guid[0x40];
2393
2394	u8         node_guid[0x40];
2395
2396	u8         reserved_5[0x140];
2397
2398	u8         qkey_violation_counter[0x10];
2399	u8         reserved_6[0x10];
2400
2401	u8         reserved_7[0x420];
2402
2403	u8         promisc_uc[0x1];
2404	u8         promisc_mc[0x1];
2405	u8         promisc_all[0x1];
2406	u8         reserved_8[0x2];
2407	u8         allowed_list_type[0x3];
2408	u8         reserved_9[0xc];
2409	u8         allowed_list_size[0xc];
2410
2411	struct mlx5_ifc_mac_address_layout_bits permanent_address;
2412
2413	u8         reserved_10[0x20];
2414
2415	u8         current_uc_mac_address[0][0x40];
2416};
2417
2418enum {
2419	MLX5_ACCESS_MODE_PA        = 0x0,
2420	MLX5_ACCESS_MODE_MTT       = 0x1,
2421	MLX5_ACCESS_MODE_KLM       = 0x2,
2422};
2423
2424struct mlx5_ifc_mkc_bits {
2425	u8         reserved_0[0x1];
2426	u8         free[0x1];
2427	u8         reserved_1[0xd];
2428	u8         small_fence_on_rdma_read_response[0x1];
2429	u8         umr_en[0x1];
2430	u8         a[0x1];
2431	u8         rw[0x1];
2432	u8         rr[0x1];
2433	u8         lw[0x1];
2434	u8         lr[0x1];
2435	u8         access_mode[0x2];
2436	u8         reserved_2[0x8];
2437
2438	u8         qpn[0x18];
2439	u8         mkey_7_0[0x8];
2440
2441	u8         reserved_3[0x20];
2442
2443	u8         length64[0x1];
2444	u8         bsf_en[0x1];
2445	u8         sync_umr[0x1];
2446	u8         reserved_4[0x2];
2447	u8         expected_sigerr_count[0x1];
2448	u8         reserved_5[0x1];
2449	u8         en_rinval[0x1];
2450	u8         pd[0x18];
2451
2452	u8         start_addr[0x40];
2453
2454	u8         len[0x40];
2455
2456	u8         bsf_octword_size[0x20];
2457
2458	u8         reserved_6[0x80];
2459
2460	u8         translations_octword_size[0x20];
2461
2462	u8         reserved_7[0x1b];
2463	u8         log_page_size[0x5];
2464
2465	u8         reserved_8[0x20];
2466};
2467
2468struct mlx5_ifc_pkey_bits {
2469	u8         reserved_0[0x10];
2470	u8         pkey[0x10];
2471};
2472
2473struct mlx5_ifc_array128_auto_bits {
2474	u8         array128_auto[16][0x8];
2475};
2476
2477enum {
2478	MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID           = 0x0,
2479	MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID           = 0x1,
2480	MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY  = 0x2,
2481};
2482
2483enum {
2484	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP                      = 0x1,
2485	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING                    = 0x2,
2486	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED                   = 0x3,
2487	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING  = 0x4,
2488	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP                     = 0x5,
2489	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY          = 0x6,
2490	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST                    = 0x7,
2491};
2492
2493enum {
2494	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN    = 0x0,
2495	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP      = 0x1,
2496	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW  = 0x2,
2497};
2498
2499enum {
2500	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN    = 0x1,
2501	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT    = 0x2,
2502	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM     = 0x3,
2503	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE  = 0x4,
2504};
2505
2506enum {
2507	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN    = 0x1,
2508	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT    = 0x2,
2509	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM     = 0x3,
2510	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE  = 0x4,
2511};
2512
2513struct mlx5_ifc_hca_vport_context_bits {
2514	u8         field_select[0x20];
2515
2516	u8         reserved_0[0xe0];
2517
2518	u8         sm_virt_aware[0x1];
2519	u8         has_smi[0x1];
2520	u8         has_raw[0x1];
2521	u8         grh_required[0x1];
2522	u8         reserved_1[0x1];
2523	u8         min_wqe_inline_mode[0x3];
2524	u8         reserved_2[0x8];
2525	u8         port_physical_state[0x4];
2526	u8         vport_state_policy[0x4];
2527	u8         port_state[0x4];
2528	u8         vport_state[0x4];
2529
2530	u8         reserved_3[0x20];
2531
2532	u8         system_image_guid[0x40];
2533
2534	u8         port_guid[0x40];
2535
2536	u8         node_guid[0x40];
2537
2538	u8         cap_mask1[0x20];
2539
2540	u8         cap_mask1_field_select[0x20];
2541
2542	u8         cap_mask2[0x20];
2543
2544	u8         cap_mask2_field_select[0x20];
2545
2546	u8         reserved_4[0x80];
2547
2548	u8         lid[0x10];
2549	u8         reserved_5[0x4];
2550	u8         init_type_reply[0x4];
2551	u8         lmc[0x3];
2552	u8         subnet_timeout[0x5];
2553
2554	u8         sm_lid[0x10];
2555	u8         sm_sl[0x4];
2556	u8         reserved_6[0xc];
2557
2558	u8         qkey_violation_counter[0x10];
2559	u8         pkey_violation_counter[0x10];
2560
2561	u8         reserved_7[0xca0];
2562};
2563
2564union mlx5_ifc_hca_cap_union_bits {
2565	struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2566	struct mlx5_ifc_odp_cap_bits odp_cap;
2567	struct mlx5_ifc_atomic_caps_bits atomic_caps;
2568	struct mlx5_ifc_roce_cap_bits roce_cap;
2569	struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2570	struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2571	struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2572	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2573	struct mlx5_ifc_snapshot_cap_bits snapshot_cap;
2574	struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap;
2575	struct mlx5_ifc_qos_cap_bits qos_cap;
2576	u8         reserved_0[0x8000];
2577};
2578
2579enum {
2580	MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0,
2581	MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1,
2582};
2583
2584struct mlx5_ifc_flow_table_context_bits {
2585	u8         encap_en[0x1];
2586	u8         decap_en[0x1];
2587	u8         reserved_at_2[0x2];
2588	u8         table_miss_action[0x4];
2589	u8         level[0x8];
2590	u8         reserved_at_10[0x8];
2591	u8         log_size[0x8];
2592
2593	u8         reserved_at_20[0x8];
2594	u8         table_miss_id[0x18];
2595
2596	u8         reserved_at_40[0x8];
2597	u8         lag_master_next_table_id[0x18];
2598
2599	u8         reserved_at_60[0xe0];
2600};
2601
2602struct mlx5_ifc_esw_vport_context_bits {
2603	u8         reserved_0[0x3];
2604	u8         vport_svlan_strip[0x1];
2605	u8         vport_cvlan_strip[0x1];
2606	u8         vport_svlan_insert[0x1];
2607	u8         vport_cvlan_insert[0x2];
2608	u8         reserved_1[0x18];
2609
2610	u8         reserved_2[0x20];
2611
2612	u8         svlan_cfi[0x1];
2613	u8         svlan_pcp[0x3];
2614	u8         svlan_id[0xc];
2615	u8         cvlan_cfi[0x1];
2616	u8         cvlan_pcp[0x3];
2617	u8         cvlan_id[0xc];
2618
2619	u8         reserved_3[0x7a0];
2620};
2621
2622enum {
2623	MLX5_EQC_STATUS_OK                = 0x0,
2624	MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2625};
2626
2627enum {
2628	MLX5_EQ_STATE_ARMED = 0x9,
2629	MLX5_EQ_STATE_FIRED = 0xa,
2630};
2631
2632struct mlx5_ifc_eqc_bits {
2633	u8         status[0x4];
2634	u8         reserved_0[0x9];
2635	u8         ec[0x1];
2636	u8         oi[0x1];
2637	u8         reserved_1[0x5];
2638	u8         st[0x4];
2639	u8         reserved_2[0x8];
2640
2641	u8         reserved_3[0x20];
2642
2643	u8         reserved_4[0x14];
2644	u8         page_offset[0x6];
2645	u8         reserved_5[0x6];
2646
2647	u8         reserved_6[0x3];
2648	u8         log_eq_size[0x5];
2649	u8         uar_page[0x18];
2650
2651	u8         reserved_7[0x20];
2652
2653	u8         reserved_8[0x18];
2654	u8         intr[0x8];
2655
2656	u8         reserved_9[0x3];
2657	u8         log_page_size[0x5];
2658	u8         reserved_10[0x18];
2659
2660	u8         reserved_11[0x60];
2661
2662	u8         reserved_12[0x8];
2663	u8         consumer_counter[0x18];
2664
2665	u8         reserved_13[0x8];
2666	u8         producer_counter[0x18];
2667
2668	u8         reserved_14[0x80];
2669};
2670
2671enum {
2672	MLX5_DCTC_STATE_ACTIVE    = 0x0,
2673	MLX5_DCTC_STATE_DRAINING  = 0x1,
2674	MLX5_DCTC_STATE_DRAINED   = 0x2,
2675};
2676
2677enum {
2678	MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2679	MLX5_DCTC_CS_RES_NA         = 0x1,
2680	MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2681};
2682
2683enum {
2684	MLX5_DCTC_MTU_256_BYTES  = 0x1,
2685	MLX5_DCTC_MTU_512_BYTES  = 0x2,
2686	MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2687	MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2688	MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2689};
2690
2691struct mlx5_ifc_dctc_bits {
2692	u8         reserved_0[0x4];
2693	u8         state[0x4];
2694	u8         reserved_1[0x18];
2695
2696	u8         reserved_2[0x8];
2697	u8         user_index[0x18];
2698
2699	u8         reserved_3[0x8];
2700	u8         cqn[0x18];
2701
2702	u8         counter_set_id[0x8];
2703	u8         atomic_mode[0x4];
2704	u8         rre[0x1];
2705	u8         rwe[0x1];
2706	u8         rae[0x1];
2707	u8         atomic_like_write_en[0x1];
2708	u8         latency_sensitive[0x1];
2709	u8         rlky[0x1];
2710	u8         reserved_4[0xe];
2711
2712	u8         reserved_5[0x8];
2713	u8         cs_res[0x8];
2714	u8         reserved_6[0x3];
2715	u8         min_rnr_nak[0x5];
2716	u8         reserved_7[0x8];
2717
2718	u8         reserved_8[0x8];
2719	u8         srqn[0x18];
2720
2721	u8         reserved_9[0x8];
2722	u8         pd[0x18];
2723
2724	u8         tclass[0x8];
2725	u8         reserved_10[0x4];
2726	u8         flow_label[0x14];
2727
2728	u8         dc_access_key[0x40];
2729
2730	u8         reserved_11[0x5];
2731	u8         mtu[0x3];
2732	u8         port[0x8];
2733	u8         pkey_index[0x10];
2734
2735	u8         reserved_12[0x8];
2736	u8         my_addr_index[0x8];
2737	u8         reserved_13[0x8];
2738	u8         hop_limit[0x8];
2739
2740	u8         dc_access_key_violation_count[0x20];
2741
2742	u8         reserved_14[0x14];
2743	u8         dei_cfi[0x1];
2744	u8         eth_prio[0x3];
2745	u8         ecn[0x2];
2746	u8         dscp[0x6];
2747
2748	u8         reserved_15[0x40];
2749};
2750
2751enum {
2752	MLX5_CQC_STATUS_OK             = 0x0,
2753	MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2754	MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2755};
2756
2757enum {
2758	CQE_SIZE_64                = 0x0,
2759	CQE_SIZE_128               = 0x1,
2760};
2761
2762enum {
2763	MLX5_CQ_PERIOD_MODE_START_FROM_EQE  = 0x0,
2764	MLX5_CQ_PERIOD_MODE_START_FROM_CQE  = 0x1,
2765};
2766
2767enum {
2768	MLX5_CQ_STATE_SOLICITED_ARMED                     = 0x6,
2769	MLX5_CQ_STATE_ARMED                               = 0x9,
2770	MLX5_CQ_STATE_FIRED                               = 0xa,
2771};
2772
2773struct mlx5_ifc_cqc_bits {
2774	u8         status[0x4];
2775	u8         reserved_0[0x4];
2776	u8         cqe_sz[0x3];
2777	u8         cc[0x1];
2778	u8         reserved_1[0x1];
2779	u8         scqe_break_moderation_en[0x1];
2780	u8         oi[0x1];
2781	u8         cq_period_mode[0x2];
2782	u8         cqe_compression_en[0x1];
2783	u8         mini_cqe_res_format[0x2];
2784	u8         st[0x4];
2785	u8         reserved_2[0x8];
2786
2787	u8         reserved_3[0x20];
2788
2789	u8         reserved_4[0x14];
2790	u8         page_offset[0x6];
2791	u8         reserved_5[0x6];
2792
2793	u8         reserved_6[0x3];
2794	u8         log_cq_size[0x5];
2795	u8         uar_page[0x18];
2796
2797	u8         reserved_7[0x4];
2798	u8         cq_period[0xc];
2799	u8         cq_max_count[0x10];
2800
2801	u8         reserved_8[0x18];
2802	u8         c_eqn[0x8];
2803
2804	u8         reserved_9[0x3];
2805	u8         log_page_size[0x5];
2806	u8         reserved_10[0x18];
2807
2808	u8         reserved_11[0x20];
2809
2810	u8         reserved_12[0x8];
2811	u8         last_notified_index[0x18];
2812
2813	u8         reserved_13[0x8];
2814	u8         last_solicit_index[0x18];
2815
2816	u8         reserved_14[0x8];
2817	u8         consumer_counter[0x18];
2818
2819	u8         reserved_15[0x8];
2820	u8         producer_counter[0x18];
2821
2822	u8         reserved_16[0x40];
2823
2824	u8         dbr_addr[0x40];
2825};
2826
2827union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2828	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2829	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2830	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2831	u8         reserved_0[0x800];
2832};
2833
2834struct mlx5_ifc_query_adapter_param_block_bits {
2835	u8         reserved_0[0xc0];
2836
2837	u8         reserved_1[0x8];
2838	u8         ieee_vendor_id[0x18];
2839
2840	u8         reserved_2[0x10];
2841	u8         vsd_vendor_id[0x10];
2842
2843	u8         vsd[208][0x8];
2844
2845	u8         vsd_contd_psid[16][0x8];
2846};
2847
2848union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2849	struct mlx5_ifc_modify_field_select_bits modify_field_select;
2850	struct mlx5_ifc_resize_field_select_bits resize_field_select;
2851	u8         reserved_0[0x20];
2852};
2853
2854union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2855	struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2856	struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2857	struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2858	u8         reserved_0[0x20];
2859};
2860
2861struct mlx5_ifc_bufferx_reg_bits {
2862	u8         reserved_0[0x6];
2863	u8         lossy[0x1];
2864	u8         epsb[0x1];
2865	u8         reserved_1[0xc];
2866	u8         size[0xc];
2867
2868	u8         xoff_threshold[0x10];
2869	u8         xon_threshold[0x10];
2870};
2871
2872struct mlx5_ifc_config_item_bits {
2873	u8         valid[0x2];
2874	u8         reserved_0[0x2];
2875	u8         header_type[0x2];
2876	u8         reserved_1[0x2];
2877	u8         default_location[0x1];
2878	u8         reserved_2[0x7];
2879	u8         version[0x4];
2880	u8         reserved_3[0x3];
2881	u8         length[0x9];
2882
2883	u8         type[0x20];
2884
2885	u8         reserved_4[0x10];
2886	u8         crc16[0x10];
2887};
2888
2889struct mlx5_ifc_nodnic_port_config_reg_bits {
2890	struct mlx5_ifc_nodnic_event_word_bits event;
2891
2892	u8         network_en[0x1];
2893	u8         dma_en[0x1];
2894	u8         promisc_en[0x1];
2895	u8         promisc_multicast_en[0x1];
2896	u8         reserved_0[0x17];
2897	u8         receive_filter_en[0x5];
2898
2899	u8         reserved_1[0x10];
2900	u8         mac_47_32[0x10];
2901
2902	u8         mac_31_0[0x20];
2903
2904	u8         receive_filters_mgid_mac[64][0x8];
2905
2906	u8         gid[16][0x8];
2907
2908	u8         reserved_2[0x10];
2909	u8         lid[0x10];
2910
2911	u8         reserved_3[0xc];
2912	u8         sm_sl[0x4];
2913	u8         sm_lid[0x10];
2914
2915	u8         completion_address_63_32[0x20];
2916
2917	u8         completion_address_31_12[0x14];
2918	u8         reserved_4[0x6];
2919	u8         log_cq_size[0x6];
2920
2921	u8         working_buffer_address_63_32[0x20];
2922
2923	u8         working_buffer_address_31_12[0x14];
2924	u8         reserved_5[0xc];
2925
2926	struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq;
2927
2928	u8         pkey_index[0x10];
2929	u8         pkey[0x10];
2930
2931	struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0;
2932
2933	struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1;
2934
2935	struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0;
2936
2937	struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1;
2938
2939	u8         reserved_6[0x400];
2940};
2941
2942union mlx5_ifc_event_auto_bits {
2943	struct mlx5_ifc_comp_event_bits comp_event;
2944	struct mlx5_ifc_dct_events_bits dct_events;
2945	struct mlx5_ifc_qp_events_bits qp_events;
2946	struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2947	struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2948	struct mlx5_ifc_cq_error_bits cq_error;
2949	struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2950	struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2951	struct mlx5_ifc_gpio_event_bits gpio_event;
2952	struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2953	struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2954	struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2955	struct mlx5_ifc_pages_req_event_bits pages_req_event;
2956	struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event;
2957	u8         reserved_0[0xe0];
2958};
2959
2960struct mlx5_ifc_health_buffer_bits {
2961	u8         reserved_0[0x100];
2962
2963	u8         assert_existptr[0x20];
2964
2965	u8         assert_callra[0x20];
2966
2967	u8         reserved_1[0x40];
2968
2969	u8         fw_version[0x20];
2970
2971	u8         hw_id[0x20];
2972
2973	u8         reserved_2[0x20];
2974
2975	u8         irisc_index[0x8];
2976	u8         synd[0x8];
2977	u8         ext_synd[0x10];
2978};
2979
2980struct mlx5_ifc_register_loopback_control_bits {
2981	u8         no_lb[0x1];
2982	u8         reserved_0[0x7];
2983	u8         port[0x8];
2984	u8         reserved_1[0x10];
2985
2986	u8         reserved_2[0x60];
2987};
2988
2989struct mlx5_ifc_lrh_bits {
2990	u8	vl[4];
2991	u8	lver[4];
2992	u8	sl[4];
2993	u8	reserved2[2];
2994	u8	lnh[2];
2995	u8	dlid[16];
2996	u8	reserved5[5];
2997	u8	pkt_len[11];
2998	u8	slid[16];
2999};
3000
3001struct mlx5_ifc_icmd_set_wol_rol_out_bits {
3002	u8         reserved_0[0x40];
3003
3004	u8         reserved_1[0x10];
3005	u8         rol_mode[0x8];
3006	u8         wol_mode[0x8];
3007};
3008
3009struct mlx5_ifc_icmd_set_wol_rol_in_bits {
3010	u8         reserved_0[0x40];
3011
3012	u8         rol_mode_valid[0x1];
3013	u8         wol_mode_valid[0x1];
3014	u8         reserved_1[0xe];
3015	u8         rol_mode[0x8];
3016	u8         wol_mode[0x8];
3017
3018	u8         reserved_2[0x7a0];
3019};
3020
3021struct mlx5_ifc_icmd_set_virtual_mac_in_bits {
3022	u8         virtual_mac_en[0x1];
3023	u8         mac_aux_v[0x1];
3024	u8         reserved_0[0x1e];
3025
3026	u8         reserved_1[0x40];
3027
3028	struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3029
3030	u8         reserved_2[0x760];
3031};
3032
3033struct mlx5_ifc_icmd_query_virtual_mac_out_bits {
3034	u8         virtual_mac_en[0x1];
3035	u8         mac_aux_v[0x1];
3036	u8         reserved_0[0x1e];
3037
3038	struct mlx5_ifc_mac_address_layout_bits permanent_mac;
3039
3040	struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3041
3042	u8         reserved_1[0x760];
3043};
3044
3045struct mlx5_ifc_icmd_query_fw_info_out_bits {
3046	struct mlx5_ifc_fw_version_bits fw_version;
3047
3048	u8         reserved_0[0x10];
3049	u8         hash_signature[0x10];
3050
3051	u8         psid[16][0x8];
3052
3053	u8         reserved_1[0x6e0];
3054};
3055
3056struct mlx5_ifc_icmd_query_cap_in_bits {
3057	u8         reserved_0[0x10];
3058	u8         capability_group[0x10];
3059};
3060
3061struct mlx5_ifc_icmd_query_cap_general_bits {
3062	u8         nv_access[0x1];
3063	u8         fw_info_psid[0x1];
3064	u8         reserved_0[0x1e];
3065
3066	u8         reserved_1[0x16];
3067	u8         rol_s[0x1];
3068	u8         rol_g[0x1];
3069	u8         reserved_2[0x1];
3070	u8         wol_s[0x1];
3071	u8         wol_g[0x1];
3072	u8         wol_a[0x1];
3073	u8         wol_b[0x1];
3074	u8         wol_m[0x1];
3075	u8         wol_u[0x1];
3076	u8         wol_p[0x1];
3077};
3078
3079struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits {
3080	u8         status[0x8];
3081	u8         reserved_0[0x18];
3082
3083	u8         reserved_1[0x7e0];
3084};
3085
3086struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits {
3087	u8         status[0x8];
3088	u8         reserved_0[0x18];
3089
3090	u8         reserved_1[0x7e0];
3091};
3092
3093struct mlx5_ifc_icmd_ocbb_init_in_bits {
3094	u8         address_hi[0x20];
3095
3096	u8         address_lo[0x20];
3097
3098	u8         reserved_0[0x7c0];
3099};
3100
3101struct mlx5_ifc_icmd_init_ocsd_in_bits {
3102	u8         reserved_0[0x20];
3103
3104	u8         address_hi[0x20];
3105
3106	u8         address_lo[0x20];
3107
3108	u8         reserved_1[0x7a0];
3109};
3110
3111struct mlx5_ifc_icmd_access_reg_out_bits {
3112	u8         reserved_0[0x11];
3113	u8         status[0x7];
3114	u8         reserved_1[0x8];
3115
3116	u8         register_id[0x10];
3117	u8         reserved_2[0x10];
3118
3119	u8         reserved_3[0x40];
3120
3121	u8         reserved_4[0x5];
3122	u8         len[0xb];
3123	u8         reserved_5[0x10];
3124
3125	u8         register_data[0][0x20];
3126};
3127
3128enum {
3129	MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY  = 0x1,
3130	MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE  = 0x2,
3131};
3132
3133struct mlx5_ifc_icmd_access_reg_in_bits {
3134	u8         constant_1[0x5];
3135	u8         constant_2[0xb];
3136	u8         reserved_0[0x10];
3137
3138	u8         register_id[0x10];
3139	u8         reserved_1[0x1];
3140	u8         method[0x7];
3141	u8         constant_3[0x8];
3142
3143	u8         reserved_2[0x40];
3144
3145	u8         constant_4[0x5];
3146	u8         len[0xb];
3147	u8         reserved_3[0x10];
3148
3149	u8         register_data[0][0x20];
3150};
3151
3152struct mlx5_ifc_teardown_hca_out_bits {
3153	u8         status[0x8];
3154	u8         reserved_0[0x18];
3155
3156	u8         syndrome[0x20];
3157
3158	u8         reserved_1[0x40];
3159};
3160
3161enum {
3162	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3163	MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE     = 0x1,
3164};
3165
3166struct mlx5_ifc_teardown_hca_in_bits {
3167	u8         opcode[0x10];
3168	u8         reserved_0[0x10];
3169
3170	u8         reserved_1[0x10];
3171	u8         op_mod[0x10];
3172
3173	u8         reserved_2[0x10];
3174	u8         profile[0x10];
3175
3176	u8         reserved_3[0x20];
3177};
3178
3179struct mlx5_ifc_set_delay_drop_params_out_bits {
3180	u8         status[0x8];
3181	u8         reserved_at_8[0x18];
3182
3183	u8         syndrome[0x20];
3184
3185	u8         reserved_at_40[0x40];
3186};
3187
3188struct mlx5_ifc_set_delay_drop_params_in_bits {
3189	u8         opcode[0x10];
3190	u8         reserved_at_10[0x10];
3191
3192	u8         reserved_at_20[0x10];
3193	u8         op_mod[0x10];
3194
3195	u8         reserved_at_40[0x20];
3196
3197	u8         reserved_at_60[0x10];
3198	u8         delay_drop_timeout[0x10];
3199};
3200
3201struct mlx5_ifc_query_delay_drop_params_out_bits {
3202	u8         status[0x8];
3203	u8         reserved_at_8[0x18];
3204
3205	u8         syndrome[0x20];
3206
3207	u8         reserved_at_40[0x20];
3208
3209	u8         reserved_at_60[0x10];
3210	u8         delay_drop_timeout[0x10];
3211};
3212
3213struct mlx5_ifc_query_delay_drop_params_in_bits {
3214	u8         opcode[0x10];
3215	u8         reserved_at_10[0x10];
3216
3217	u8         reserved_at_20[0x10];
3218	u8         op_mod[0x10];
3219
3220	u8         reserved_at_40[0x40];
3221};
3222
3223struct mlx5_ifc_suspend_qp_out_bits {
3224	u8         status[0x8];
3225	u8         reserved_0[0x18];
3226
3227	u8         syndrome[0x20];
3228
3229	u8         reserved_1[0x40];
3230};
3231
3232struct mlx5_ifc_suspend_qp_in_bits {
3233	u8         opcode[0x10];
3234	u8         reserved_0[0x10];
3235
3236	u8         reserved_1[0x10];
3237	u8         op_mod[0x10];
3238
3239	u8         reserved_2[0x8];
3240	u8         qpn[0x18];
3241
3242	u8         reserved_3[0x20];
3243};
3244
3245struct mlx5_ifc_sqerr2rts_qp_out_bits {
3246	u8         status[0x8];
3247	u8         reserved_0[0x18];
3248
3249	u8         syndrome[0x20];
3250
3251	u8         reserved_1[0x40];
3252};
3253
3254struct mlx5_ifc_sqerr2rts_qp_in_bits {
3255	u8         opcode[0x10];
3256	u8         reserved_0[0x10];
3257
3258	u8         reserved_1[0x10];
3259	u8         op_mod[0x10];
3260
3261	u8         reserved_2[0x8];
3262	u8         qpn[0x18];
3263
3264	u8         reserved_3[0x20];
3265
3266	u8         opt_param_mask[0x20];
3267
3268	u8         reserved_4[0x20];
3269
3270	struct mlx5_ifc_qpc_bits qpc;
3271
3272	u8         reserved_5[0x80];
3273};
3274
3275struct mlx5_ifc_sqd2rts_qp_out_bits {
3276	u8         status[0x8];
3277	u8         reserved_0[0x18];
3278
3279	u8         syndrome[0x20];
3280
3281	u8         reserved_1[0x40];
3282};
3283
3284struct mlx5_ifc_sqd2rts_qp_in_bits {
3285	u8         opcode[0x10];
3286	u8         reserved_0[0x10];
3287
3288	u8         reserved_1[0x10];
3289	u8         op_mod[0x10];
3290
3291	u8         reserved_2[0x8];
3292	u8         qpn[0x18];
3293
3294	u8         reserved_3[0x20];
3295
3296	u8         opt_param_mask[0x20];
3297
3298	u8         reserved_4[0x20];
3299
3300	struct mlx5_ifc_qpc_bits qpc;
3301
3302	u8         reserved_5[0x80];
3303};
3304
3305struct mlx5_ifc_set_wol_rol_out_bits {
3306	u8         status[0x8];
3307	u8         reserved_0[0x18];
3308
3309	u8         syndrome[0x20];
3310
3311	u8         reserved_1[0x40];
3312};
3313
3314struct mlx5_ifc_set_wol_rol_in_bits {
3315	u8         opcode[0x10];
3316	u8         reserved_0[0x10];
3317
3318	u8         reserved_1[0x10];
3319	u8         op_mod[0x10];
3320
3321	u8         rol_mode_valid[0x1];
3322	u8         wol_mode_valid[0x1];
3323	u8         reserved_2[0xe];
3324	u8         rol_mode[0x8];
3325	u8         wol_mode[0x8];
3326
3327	u8         reserved_3[0x20];
3328};
3329
3330struct mlx5_ifc_set_roce_address_out_bits {
3331	u8         status[0x8];
3332	u8         reserved_0[0x18];
3333
3334	u8         syndrome[0x20];
3335
3336	u8         reserved_1[0x40];
3337};
3338
3339struct mlx5_ifc_set_roce_address_in_bits {
3340	u8         opcode[0x10];
3341	u8         reserved_0[0x10];
3342
3343	u8         reserved_1[0x10];
3344	u8         op_mod[0x10];
3345
3346	u8         roce_address_index[0x10];
3347	u8         reserved_2[0x10];
3348
3349	u8         reserved_3[0x20];
3350
3351	struct mlx5_ifc_roce_addr_layout_bits roce_address;
3352};
3353
3354struct mlx5_ifc_set_rdb_out_bits {
3355	u8         status[0x8];
3356	u8         reserved_0[0x18];
3357
3358	u8         syndrome[0x20];
3359
3360	u8         reserved_1[0x40];
3361};
3362
3363struct mlx5_ifc_set_rdb_in_bits {
3364	u8         opcode[0x10];
3365	u8         reserved_0[0x10];
3366
3367	u8         reserved_1[0x10];
3368	u8         op_mod[0x10];
3369
3370	u8         reserved_2[0x8];
3371	u8         qpn[0x18];
3372
3373	u8         reserved_3[0x18];
3374	u8         rdb_list_size[0x8];
3375
3376	struct mlx5_ifc_rdbc_bits rdb_context[0];
3377};
3378
3379struct mlx5_ifc_set_mad_demux_out_bits {
3380	u8         status[0x8];
3381	u8         reserved_0[0x18];
3382
3383	u8         syndrome[0x20];
3384
3385	u8         reserved_1[0x40];
3386};
3387
3388enum {
3389	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3390	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3391};
3392
3393struct mlx5_ifc_set_mad_demux_in_bits {
3394	u8         opcode[0x10];
3395	u8         reserved_0[0x10];
3396
3397	u8         reserved_1[0x10];
3398	u8         op_mod[0x10];
3399
3400	u8         reserved_2[0x20];
3401
3402	u8         reserved_3[0x6];
3403	u8         demux_mode[0x2];
3404	u8         reserved_4[0x18];
3405};
3406
3407struct mlx5_ifc_set_l2_table_entry_out_bits {
3408	u8         status[0x8];
3409	u8         reserved_0[0x18];
3410
3411	u8         syndrome[0x20];
3412
3413	u8         reserved_1[0x40];
3414};
3415
3416struct mlx5_ifc_set_l2_table_entry_in_bits {
3417	u8         opcode[0x10];
3418	u8         reserved_0[0x10];
3419
3420	u8         reserved_1[0x10];
3421	u8         op_mod[0x10];
3422
3423	u8         reserved_2[0x60];
3424
3425	u8         reserved_3[0x8];
3426	u8         table_index[0x18];
3427
3428	u8         reserved_4[0x20];
3429
3430	u8         reserved_5[0x13];
3431	u8         vlan_valid[0x1];
3432	u8         vlan[0xc];
3433
3434	struct mlx5_ifc_mac_address_layout_bits mac_address;
3435
3436	u8         reserved_6[0xc0];
3437};
3438
3439struct mlx5_ifc_set_issi_out_bits {
3440	u8         status[0x8];
3441	u8         reserved_0[0x18];
3442
3443	u8         syndrome[0x20];
3444
3445	u8         reserved_1[0x40];
3446};
3447
3448struct mlx5_ifc_set_issi_in_bits {
3449	u8         opcode[0x10];
3450	u8         reserved_0[0x10];
3451
3452	u8         reserved_1[0x10];
3453	u8         op_mod[0x10];
3454
3455	u8         reserved_2[0x10];
3456	u8         current_issi[0x10];
3457
3458	u8         reserved_3[0x20];
3459};
3460
3461struct mlx5_ifc_set_hca_cap_out_bits {
3462	u8         status[0x8];
3463	u8         reserved_0[0x18];
3464
3465	u8         syndrome[0x20];
3466
3467	u8         reserved_1[0x40];
3468};
3469
3470struct mlx5_ifc_set_hca_cap_in_bits {
3471	u8         opcode[0x10];
3472	u8         reserved_0[0x10];
3473
3474	u8         reserved_1[0x10];
3475	u8         op_mod[0x10];
3476
3477	u8         reserved_2[0x40];
3478
3479	union mlx5_ifc_hca_cap_union_bits capability;
3480};
3481
3482enum {
3483	MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION			= 0x0,
3484	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG		= 0x1,
3485	MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST	= 0x2,
3486	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS		= 0x3
3487};
3488
3489struct mlx5_ifc_set_flow_table_root_out_bits {
3490	u8         status[0x8];
3491	u8         reserved_0[0x18];
3492
3493	u8         syndrome[0x20];
3494
3495	u8         reserved_1[0x40];
3496};
3497
3498struct mlx5_ifc_set_flow_table_root_in_bits {
3499	u8         opcode[0x10];
3500	u8         reserved_0[0x10];
3501
3502	u8         reserved_1[0x10];
3503	u8         op_mod[0x10];
3504
3505	u8         other_vport[0x1];
3506	u8         reserved_2[0xf];
3507	u8         vport_number[0x10];
3508
3509	u8         reserved_3[0x20];
3510
3511	u8         table_type[0x8];
3512	u8         reserved_4[0x18];
3513
3514	u8         reserved_5[0x8];
3515	u8         table_id[0x18];
3516
3517	u8         reserved_6[0x8];
3518	u8         underlay_qpn[0x18];
3519
3520	u8         reserved_7[0x120];
3521};
3522
3523struct mlx5_ifc_set_fte_out_bits {
3524	u8         status[0x8];
3525	u8         reserved_0[0x18];
3526
3527	u8         syndrome[0x20];
3528
3529	u8         reserved_1[0x40];
3530};
3531
3532struct mlx5_ifc_set_fte_in_bits {
3533	u8         opcode[0x10];
3534	u8         reserved_0[0x10];
3535
3536	u8         reserved_1[0x10];
3537	u8         op_mod[0x10];
3538
3539	u8         other_vport[0x1];
3540	u8         reserved_2[0xf];
3541	u8         vport_number[0x10];
3542
3543	u8         reserved_3[0x20];
3544
3545	u8         table_type[0x8];
3546	u8         reserved_4[0x18];
3547
3548	u8         reserved_5[0x8];
3549	u8         table_id[0x18];
3550
3551	u8         reserved_6[0x18];
3552	u8         modify_enable_mask[0x8];
3553
3554	u8         reserved_7[0x20];
3555
3556	u8         flow_index[0x20];
3557
3558	u8         reserved_8[0xe0];
3559
3560	struct mlx5_ifc_flow_context_bits flow_context;
3561};
3562
3563struct mlx5_ifc_set_driver_version_out_bits {
3564	u8         status[0x8];
3565	u8         reserved_0[0x18];
3566
3567	u8         syndrome[0x20];
3568
3569	u8         reserved_1[0x40];
3570};
3571
3572struct mlx5_ifc_set_driver_version_in_bits {
3573	u8         opcode[0x10];
3574	u8         reserved_0[0x10];
3575
3576	u8         reserved_1[0x10];
3577	u8         op_mod[0x10];
3578
3579	u8         reserved_2[0x40];
3580
3581	u8         driver_version[64][0x8];
3582};
3583
3584struct mlx5_ifc_set_dc_cnak_trace_out_bits {
3585	u8         status[0x8];
3586	u8         reserved_0[0x18];
3587
3588	u8         syndrome[0x20];
3589
3590	u8         reserved_1[0x40];
3591};
3592
3593struct mlx5_ifc_set_dc_cnak_trace_in_bits {
3594	u8         opcode[0x10];
3595	u8         reserved_0[0x10];
3596
3597	u8         reserved_1[0x10];
3598	u8         op_mod[0x10];
3599
3600	u8         enable[0x1];
3601	u8         reserved_2[0x1f];
3602
3603	u8         reserved_3[0x160];
3604
3605	struct mlx5_ifc_cmd_pas_bits pas;
3606};
3607
3608struct mlx5_ifc_set_burst_size_out_bits {
3609	u8         status[0x8];
3610	u8         reserved_0[0x18];
3611
3612	u8         syndrome[0x20];
3613
3614	u8         reserved_1[0x40];
3615};
3616
3617struct mlx5_ifc_set_burst_size_in_bits {
3618	u8         opcode[0x10];
3619	u8         reserved_0[0x10];
3620
3621	u8         reserved_1[0x10];
3622	u8         op_mod[0x10];
3623
3624	u8         reserved_2[0x20];
3625
3626	u8         reserved_3[0x9];
3627	u8         device_burst_size[0x17];
3628};
3629
3630struct mlx5_ifc_rts2rts_qp_out_bits {
3631	u8         status[0x8];
3632	u8         reserved_0[0x18];
3633
3634	u8         syndrome[0x20];
3635
3636	u8         reserved_1[0x40];
3637};
3638
3639struct mlx5_ifc_rts2rts_qp_in_bits {
3640	u8         opcode[0x10];
3641	u8         reserved_0[0x10];
3642
3643	u8         reserved_1[0x10];
3644	u8         op_mod[0x10];
3645
3646	u8         reserved_2[0x8];
3647	u8         qpn[0x18];
3648
3649	u8         reserved_3[0x20];
3650
3651	u8         opt_param_mask[0x20];
3652
3653	u8         reserved_4[0x20];
3654
3655	struct mlx5_ifc_qpc_bits qpc;
3656
3657	u8         reserved_5[0x80];
3658};
3659
3660struct mlx5_ifc_rtr2rts_qp_out_bits {
3661	u8         status[0x8];
3662	u8         reserved_0[0x18];
3663
3664	u8         syndrome[0x20];
3665
3666	u8         reserved_1[0x40];
3667};
3668
3669struct mlx5_ifc_rtr2rts_qp_in_bits {
3670	u8         opcode[0x10];
3671	u8         reserved_0[0x10];
3672
3673	u8         reserved_1[0x10];
3674	u8         op_mod[0x10];
3675
3676	u8         reserved_2[0x8];
3677	u8         qpn[0x18];
3678
3679	u8         reserved_3[0x20];
3680
3681	u8         opt_param_mask[0x20];
3682
3683	u8         reserved_4[0x20];
3684
3685	struct mlx5_ifc_qpc_bits qpc;
3686
3687	u8         reserved_5[0x80];
3688};
3689
3690struct mlx5_ifc_rst2init_qp_out_bits {
3691	u8         status[0x8];
3692	u8         reserved_0[0x18];
3693
3694	u8         syndrome[0x20];
3695
3696	u8         reserved_1[0x40];
3697};
3698
3699struct mlx5_ifc_rst2init_qp_in_bits {
3700	u8         opcode[0x10];
3701	u8         reserved_0[0x10];
3702
3703	u8         reserved_1[0x10];
3704	u8         op_mod[0x10];
3705
3706	u8         reserved_2[0x8];
3707	u8         qpn[0x18];
3708
3709	u8         reserved_3[0x20];
3710
3711	u8         opt_param_mask[0x20];
3712
3713	u8         reserved_4[0x20];
3714
3715	struct mlx5_ifc_qpc_bits qpc;
3716
3717	u8         reserved_5[0x80];
3718};
3719
3720struct mlx5_ifc_resume_qp_out_bits {
3721	u8         status[0x8];
3722	u8         reserved_0[0x18];
3723
3724	u8         syndrome[0x20];
3725
3726	u8         reserved_1[0x40];
3727};
3728
3729struct mlx5_ifc_resume_qp_in_bits {
3730	u8         opcode[0x10];
3731	u8         reserved_0[0x10];
3732
3733	u8         reserved_1[0x10];
3734	u8         op_mod[0x10];
3735
3736	u8         reserved_2[0x8];
3737	u8         qpn[0x18];
3738
3739	u8         reserved_3[0x20];
3740};
3741
3742struct mlx5_ifc_query_xrc_srq_out_bits {
3743	u8         status[0x8];
3744	u8         reserved_0[0x18];
3745
3746	u8         syndrome[0x20];
3747
3748	u8         reserved_1[0x40];
3749
3750	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3751
3752	u8         reserved_2[0x600];
3753
3754	u8         pas[0][0x40];
3755};
3756
3757struct mlx5_ifc_query_xrc_srq_in_bits {
3758	u8         opcode[0x10];
3759	u8         reserved_0[0x10];
3760
3761	u8         reserved_1[0x10];
3762	u8         op_mod[0x10];
3763
3764	u8         reserved_2[0x8];
3765	u8         xrc_srqn[0x18];
3766
3767	u8         reserved_3[0x20];
3768};
3769
3770struct mlx5_ifc_query_wol_rol_out_bits {
3771	u8         status[0x8];
3772	u8         reserved_0[0x18];
3773
3774	u8         syndrome[0x20];
3775
3776	u8         reserved_1[0x10];
3777	u8         rol_mode[0x8];
3778	u8         wol_mode[0x8];
3779
3780	u8         reserved_2[0x20];
3781};
3782
3783struct mlx5_ifc_query_wol_rol_in_bits {
3784	u8         opcode[0x10];
3785	u8         reserved_0[0x10];
3786
3787	u8         reserved_1[0x10];
3788	u8         op_mod[0x10];
3789
3790	u8         reserved_2[0x40];
3791};
3792
3793enum {
3794	MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3795	MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3796};
3797
3798struct mlx5_ifc_query_vport_state_out_bits {
3799	u8         status[0x8];
3800	u8         reserved_0[0x18];
3801
3802	u8         syndrome[0x20];
3803
3804	u8         reserved_1[0x20];
3805
3806	u8         reserved_2[0x18];
3807	u8         admin_state[0x4];
3808	u8         state[0x4];
3809};
3810
3811enum {
3812	MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3813	MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3814	MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK      = 0x2,
3815};
3816
3817struct mlx5_ifc_query_vport_state_in_bits {
3818	u8         opcode[0x10];
3819	u8         reserved_0[0x10];
3820
3821	u8         reserved_1[0x10];
3822	u8         op_mod[0x10];
3823
3824	u8         other_vport[0x1];
3825	u8         reserved_2[0xf];
3826	u8         vport_number[0x10];
3827
3828	u8         reserved_3[0x20];
3829};
3830
3831struct mlx5_ifc_query_vport_counter_out_bits {
3832	u8         status[0x8];
3833	u8         reserved_0[0x18];
3834
3835	u8         syndrome[0x20];
3836
3837	u8         reserved_1[0x40];
3838
3839	struct mlx5_ifc_traffic_counter_bits received_errors;
3840
3841	struct mlx5_ifc_traffic_counter_bits transmit_errors;
3842
3843	struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3844
3845	struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3846
3847	struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3848
3849	struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3850
3851	struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3852
3853	struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3854
3855	struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3856
3857	struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3858
3859	struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3860
3861	struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3862
3863	u8         reserved_2[0xa00];
3864};
3865
3866enum {
3867	MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3868};
3869
3870struct mlx5_ifc_query_vport_counter_in_bits {
3871	u8         opcode[0x10];
3872	u8         reserved_0[0x10];
3873
3874	u8         reserved_1[0x10];
3875	u8         op_mod[0x10];
3876
3877	u8         other_vport[0x1];
3878	u8         reserved_2[0xb];
3879	u8         port_num[0x4];
3880	u8         vport_number[0x10];
3881
3882	u8         reserved_3[0x60];
3883
3884	u8         clear[0x1];
3885	u8         reserved_4[0x1f];
3886
3887	u8         reserved_5[0x20];
3888};
3889
3890struct mlx5_ifc_query_tis_out_bits {
3891	u8         status[0x8];
3892	u8         reserved_0[0x18];
3893
3894	u8         syndrome[0x20];
3895
3896	u8         reserved_1[0x40];
3897
3898	struct mlx5_ifc_tisc_bits tis_context;
3899};
3900
3901struct mlx5_ifc_query_tis_in_bits {
3902	u8         opcode[0x10];
3903	u8         reserved_0[0x10];
3904
3905	u8         reserved_1[0x10];
3906	u8         op_mod[0x10];
3907
3908	u8         reserved_2[0x8];
3909	u8         tisn[0x18];
3910
3911	u8         reserved_3[0x20];
3912};
3913
3914struct mlx5_ifc_query_tir_out_bits {
3915	u8         status[0x8];
3916	u8         reserved_0[0x18];
3917
3918	u8         syndrome[0x20];
3919
3920	u8         reserved_1[0xc0];
3921
3922	struct mlx5_ifc_tirc_bits tir_context;
3923};
3924
3925struct mlx5_ifc_query_tir_in_bits {
3926	u8         opcode[0x10];
3927	u8         reserved_0[0x10];
3928
3929	u8         reserved_1[0x10];
3930	u8         op_mod[0x10];
3931
3932	u8         reserved_2[0x8];
3933	u8         tirn[0x18];
3934
3935	u8         reserved_3[0x20];
3936};
3937
3938struct mlx5_ifc_query_srq_out_bits {
3939	u8         status[0x8];
3940	u8         reserved_0[0x18];
3941
3942	u8         syndrome[0x20];
3943
3944	u8         reserved_1[0x40];
3945
3946	struct mlx5_ifc_srqc_bits srq_context_entry;
3947
3948	u8         reserved_2[0x600];
3949
3950	u8         pas[0][0x40];
3951};
3952
3953struct mlx5_ifc_query_srq_in_bits {
3954	u8         opcode[0x10];
3955	u8         reserved_0[0x10];
3956
3957	u8         reserved_1[0x10];
3958	u8         op_mod[0x10];
3959
3960	u8         reserved_2[0x8];
3961	u8         srqn[0x18];
3962
3963	u8         reserved_3[0x20];
3964};
3965
3966struct mlx5_ifc_query_sq_out_bits {
3967	u8         status[0x8];
3968	u8         reserved_0[0x18];
3969
3970	u8         syndrome[0x20];
3971
3972	u8         reserved_1[0xc0];
3973
3974	struct mlx5_ifc_sqc_bits sq_context;
3975};
3976
3977struct mlx5_ifc_query_sq_in_bits {
3978	u8         opcode[0x10];
3979	u8         reserved_0[0x10];
3980
3981	u8         reserved_1[0x10];
3982	u8         op_mod[0x10];
3983
3984	u8         reserved_2[0x8];
3985	u8         sqn[0x18];
3986
3987	u8         reserved_3[0x20];
3988};
3989
3990struct mlx5_ifc_query_special_contexts_out_bits {
3991	u8         status[0x8];
3992	u8         reserved_0[0x18];
3993
3994	u8         syndrome[0x20];
3995
3996	u8	   dump_fill_mkey[0x20];
3997
3998	u8         resd_lkey[0x20];
3999};
4000
4001struct mlx5_ifc_query_special_contexts_in_bits {
4002	u8         opcode[0x10];
4003	u8         reserved_0[0x10];
4004
4005	u8         reserved_1[0x10];
4006	u8         op_mod[0x10];
4007
4008	u8         reserved_2[0x40];
4009};
4010
4011struct mlx5_ifc_query_scheduling_element_out_bits {
4012	u8         status[0x8];
4013	u8         reserved_at_8[0x18];
4014
4015	u8         syndrome[0x20];
4016
4017	u8         reserved_at_40[0xc0];
4018
4019	struct mlx5_ifc_scheduling_context_bits scheduling_context;
4020
4021	u8         reserved_at_300[0x100];
4022};
4023
4024enum {
4025	MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2,
4026};
4027
4028struct mlx5_ifc_query_scheduling_element_in_bits {
4029	u8         opcode[0x10];
4030	u8         reserved_at_10[0x10];
4031
4032	u8         reserved_at_20[0x10];
4033	u8         op_mod[0x10];
4034
4035	u8         scheduling_hierarchy[0x8];
4036	u8         reserved_at_48[0x18];
4037
4038	u8         scheduling_element_id[0x20];
4039
4040	u8         reserved_at_80[0x180];
4041};
4042
4043struct mlx5_ifc_query_rqt_out_bits {
4044	u8         status[0x8];
4045	u8         reserved_0[0x18];
4046
4047	u8         syndrome[0x20];
4048
4049	u8         reserved_1[0xc0];
4050
4051	struct mlx5_ifc_rqtc_bits rqt_context;
4052};
4053
4054struct mlx5_ifc_query_rqt_in_bits {
4055	u8         opcode[0x10];
4056	u8         reserved_0[0x10];
4057
4058	u8         reserved_1[0x10];
4059	u8         op_mod[0x10];
4060
4061	u8         reserved_2[0x8];
4062	u8         rqtn[0x18];
4063
4064	u8         reserved_3[0x20];
4065};
4066
4067struct mlx5_ifc_query_rq_out_bits {
4068	u8         status[0x8];
4069	u8         reserved_0[0x18];
4070
4071	u8         syndrome[0x20];
4072
4073	u8         reserved_1[0xc0];
4074
4075	struct mlx5_ifc_rqc_bits rq_context;
4076};
4077
4078struct mlx5_ifc_query_rq_in_bits {
4079	u8         opcode[0x10];
4080	u8         reserved_0[0x10];
4081
4082	u8         reserved_1[0x10];
4083	u8         op_mod[0x10];
4084
4085	u8         reserved_2[0x8];
4086	u8         rqn[0x18];
4087
4088	u8         reserved_3[0x20];
4089};
4090
4091struct mlx5_ifc_query_roce_address_out_bits {
4092	u8         status[0x8];
4093	u8         reserved_0[0x18];
4094
4095	u8         syndrome[0x20];
4096
4097	u8         reserved_1[0x40];
4098
4099	struct mlx5_ifc_roce_addr_layout_bits roce_address;
4100};
4101
4102struct mlx5_ifc_query_roce_address_in_bits {
4103	u8         opcode[0x10];
4104	u8         reserved_0[0x10];
4105
4106	u8         reserved_1[0x10];
4107	u8         op_mod[0x10];
4108
4109	u8         roce_address_index[0x10];
4110	u8         reserved_2[0x10];
4111
4112	u8         reserved_3[0x20];
4113};
4114
4115struct mlx5_ifc_query_rmp_out_bits {
4116	u8         status[0x8];
4117	u8         reserved_0[0x18];
4118
4119	u8         syndrome[0x20];
4120
4121	u8         reserved_1[0xc0];
4122
4123	struct mlx5_ifc_rmpc_bits rmp_context;
4124};
4125
4126struct mlx5_ifc_query_rmp_in_bits {
4127	u8         opcode[0x10];
4128	u8         reserved_0[0x10];
4129
4130	u8         reserved_1[0x10];
4131	u8         op_mod[0x10];
4132
4133	u8         reserved_2[0x8];
4134	u8         rmpn[0x18];
4135
4136	u8         reserved_3[0x20];
4137};
4138
4139struct mlx5_ifc_query_rdb_out_bits {
4140	u8         status[0x8];
4141	u8         reserved_0[0x18];
4142
4143	u8         syndrome[0x20];
4144
4145	u8         reserved_1[0x20];
4146
4147	u8         reserved_2[0x18];
4148	u8         rdb_list_size[0x8];
4149
4150	struct mlx5_ifc_rdbc_bits rdb_context[0];
4151};
4152
4153struct mlx5_ifc_query_rdb_in_bits {
4154	u8         opcode[0x10];
4155	u8         reserved_0[0x10];
4156
4157	u8         reserved_1[0x10];
4158	u8         op_mod[0x10];
4159
4160	u8         reserved_2[0x8];
4161	u8         qpn[0x18];
4162
4163	u8         reserved_3[0x20];
4164};
4165
4166struct mlx5_ifc_query_qp_out_bits {
4167	u8         status[0x8];
4168	u8         reserved_0[0x18];
4169
4170	u8         syndrome[0x20];
4171
4172	u8         reserved_1[0x40];
4173
4174	u8         opt_param_mask[0x20];
4175
4176	u8         reserved_2[0x20];
4177
4178	struct mlx5_ifc_qpc_bits qpc;
4179
4180	u8         reserved_3[0x80];
4181
4182	u8         pas[0][0x40];
4183};
4184
4185struct mlx5_ifc_query_qp_in_bits {
4186	u8         opcode[0x10];
4187	u8         reserved_0[0x10];
4188
4189	u8         reserved_1[0x10];
4190	u8         op_mod[0x10];
4191
4192	u8         reserved_2[0x8];
4193	u8         qpn[0x18];
4194
4195	u8         reserved_3[0x20];
4196};
4197
4198struct mlx5_ifc_query_q_counter_out_bits {
4199	u8         status[0x8];
4200	u8         reserved_0[0x18];
4201
4202	u8         syndrome[0x20];
4203
4204	u8         reserved_1[0x40];
4205
4206	u8         rx_write_requests[0x20];
4207
4208	u8         reserved_2[0x20];
4209
4210	u8         rx_read_requests[0x20];
4211
4212	u8         reserved_3[0x20];
4213
4214	u8         rx_atomic_requests[0x20];
4215
4216	u8         reserved_4[0x20];
4217
4218	u8         rx_dct_connect[0x20];
4219
4220	u8         reserved_5[0x20];
4221
4222	u8         out_of_buffer[0x20];
4223
4224	u8         reserved_7[0x20];
4225
4226	u8         out_of_sequence[0x20];
4227
4228	u8         reserved_8[0x20];
4229
4230	u8         duplicate_request[0x20];
4231
4232	u8         reserved_9[0x20];
4233
4234	u8         rnr_nak_retry_err[0x20];
4235
4236	u8         reserved_10[0x20];
4237
4238	u8         packet_seq_err[0x20];
4239
4240	u8         reserved_11[0x20];
4241
4242	u8         implied_nak_seq_err[0x20];
4243
4244	u8         reserved_12[0x20];
4245
4246	u8         local_ack_timeout_err[0x20];
4247
4248	u8         reserved_13[0x20];
4249
4250	u8         resp_rnr_nak[0x20];
4251
4252	u8         reserved_14[0x20];
4253
4254	u8         req_rnr_retries_exceeded[0x20];
4255
4256	u8         reserved_15[0x460];
4257};
4258
4259struct mlx5_ifc_query_q_counter_in_bits {
4260	u8         opcode[0x10];
4261	u8         reserved_0[0x10];
4262
4263	u8         reserved_1[0x10];
4264	u8         op_mod[0x10];
4265
4266	u8         reserved_2[0x80];
4267
4268	u8         clear[0x1];
4269	u8         reserved_3[0x1f];
4270
4271	u8         reserved_4[0x18];
4272	u8         counter_set_id[0x8];
4273};
4274
4275struct mlx5_ifc_query_pages_out_bits {
4276	u8         status[0x8];
4277	u8         reserved_0[0x18];
4278
4279	u8         syndrome[0x20];
4280
4281	u8         reserved_1[0x10];
4282	u8         function_id[0x10];
4283
4284	u8         num_pages[0x20];
4285};
4286
4287enum {
4288	MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES	  = 0x1,
4289	MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES	  = 0x2,
4290	MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4291};
4292
4293struct mlx5_ifc_query_pages_in_bits {
4294	u8         opcode[0x10];
4295	u8         reserved_0[0x10];
4296
4297	u8         reserved_1[0x10];
4298	u8         op_mod[0x10];
4299
4300	u8         reserved_2[0x10];
4301	u8         function_id[0x10];
4302
4303	u8         reserved_3[0x20];
4304};
4305
4306struct mlx5_ifc_query_nic_vport_context_out_bits {
4307	u8         status[0x8];
4308	u8         reserved_0[0x18];
4309
4310	u8         syndrome[0x20];
4311
4312	u8         reserved_1[0x40];
4313
4314	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4315};
4316
4317struct mlx5_ifc_query_nic_vport_context_in_bits {
4318	u8         opcode[0x10];
4319	u8         reserved_0[0x10];
4320
4321	u8         reserved_1[0x10];
4322	u8         op_mod[0x10];
4323
4324	u8         other_vport[0x1];
4325	u8         reserved_2[0xf];
4326	u8         vport_number[0x10];
4327
4328	u8         reserved_3[0x5];
4329	u8         allowed_list_type[0x3];
4330	u8         reserved_4[0x18];
4331};
4332
4333struct mlx5_ifc_query_mkey_out_bits {
4334	u8         status[0x8];
4335	u8         reserved_0[0x18];
4336
4337	u8         syndrome[0x20];
4338
4339	u8         reserved_1[0x40];
4340
4341	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4342
4343	u8         reserved_2[0x600];
4344
4345	u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4346
4347	u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4348};
4349
4350struct mlx5_ifc_query_mkey_in_bits {
4351	u8         opcode[0x10];
4352	u8         reserved_0[0x10];
4353
4354	u8         reserved_1[0x10];
4355	u8         op_mod[0x10];
4356
4357	u8         reserved_2[0x8];
4358	u8         mkey_index[0x18];
4359
4360	u8         pg_access[0x1];
4361	u8         reserved_3[0x1f];
4362};
4363
4364struct mlx5_ifc_query_mad_demux_out_bits {
4365	u8         status[0x8];
4366	u8         reserved_0[0x18];
4367
4368	u8         syndrome[0x20];
4369
4370	u8         reserved_1[0x40];
4371
4372	u8         mad_dumux_parameters_block[0x20];
4373};
4374
4375struct mlx5_ifc_query_mad_demux_in_bits {
4376	u8         opcode[0x10];
4377	u8         reserved_0[0x10];
4378
4379	u8         reserved_1[0x10];
4380	u8         op_mod[0x10];
4381
4382	u8         reserved_2[0x40];
4383};
4384
4385struct mlx5_ifc_query_l2_table_entry_out_bits {
4386	u8         status[0x8];
4387	u8         reserved_0[0x18];
4388
4389	u8         syndrome[0x20];
4390
4391	u8         reserved_1[0xa0];
4392
4393	u8         reserved_2[0x13];
4394	u8         vlan_valid[0x1];
4395	u8         vlan[0xc];
4396
4397	struct mlx5_ifc_mac_address_layout_bits mac_address;
4398
4399	u8         reserved_3[0xc0];
4400};
4401
4402struct mlx5_ifc_query_l2_table_entry_in_bits {
4403	u8         opcode[0x10];
4404	u8         reserved_0[0x10];
4405
4406	u8         reserved_1[0x10];
4407	u8         op_mod[0x10];
4408
4409	u8         reserved_2[0x60];
4410
4411	u8         reserved_3[0x8];
4412	u8         table_index[0x18];
4413
4414	u8         reserved_4[0x140];
4415};
4416
4417struct mlx5_ifc_query_issi_out_bits {
4418	u8         status[0x8];
4419	u8         reserved_0[0x18];
4420
4421	u8         syndrome[0x20];
4422
4423	u8         reserved_1[0x10];
4424	u8         current_issi[0x10];
4425
4426	u8         reserved_2[0xa0];
4427
4428	u8         supported_issi_reserved[76][0x8];
4429	u8         supported_issi_dw0[0x20];
4430};
4431
4432struct mlx5_ifc_query_issi_in_bits {
4433	u8         opcode[0x10];
4434	u8         reserved_0[0x10];
4435
4436	u8         reserved_1[0x10];
4437	u8         op_mod[0x10];
4438
4439	u8         reserved_2[0x40];
4440};
4441
4442struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4443	u8         status[0x8];
4444	u8         reserved_0[0x18];
4445
4446	u8         syndrome[0x20];
4447
4448	u8         reserved_1[0x40];
4449
4450	struct mlx5_ifc_pkey_bits pkey[0];
4451};
4452
4453struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4454	u8         opcode[0x10];
4455	u8         reserved_0[0x10];
4456
4457	u8         reserved_1[0x10];
4458	u8         op_mod[0x10];
4459
4460	u8         other_vport[0x1];
4461	u8         reserved_2[0xb];
4462	u8         port_num[0x4];
4463	u8         vport_number[0x10];
4464
4465	u8         reserved_3[0x10];
4466	u8         pkey_index[0x10];
4467};
4468
4469struct mlx5_ifc_query_hca_vport_gid_out_bits {
4470	u8         status[0x8];
4471	u8         reserved_0[0x18];
4472
4473	u8         syndrome[0x20];
4474
4475	u8         reserved_1[0x20];
4476
4477	u8         gids_num[0x10];
4478	u8         reserved_2[0x10];
4479
4480	struct mlx5_ifc_array128_auto_bits gid[0];
4481};
4482
4483struct mlx5_ifc_query_hca_vport_gid_in_bits {
4484	u8         opcode[0x10];
4485	u8         reserved_0[0x10];
4486
4487	u8         reserved_1[0x10];
4488	u8         op_mod[0x10];
4489
4490	u8         other_vport[0x1];
4491	u8         reserved_2[0xb];
4492	u8         port_num[0x4];
4493	u8         vport_number[0x10];
4494
4495	u8         reserved_3[0x10];
4496	u8         gid_index[0x10];
4497};
4498
4499struct mlx5_ifc_query_hca_vport_context_out_bits {
4500	u8         status[0x8];
4501	u8         reserved_0[0x18];
4502
4503	u8         syndrome[0x20];
4504
4505	u8         reserved_1[0x40];
4506
4507	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4508};
4509
4510struct mlx5_ifc_query_hca_vport_context_in_bits {
4511	u8         opcode[0x10];
4512	u8         reserved_0[0x10];
4513
4514	u8         reserved_1[0x10];
4515	u8         op_mod[0x10];
4516
4517	u8         other_vport[0x1];
4518	u8         reserved_2[0xb];
4519	u8         port_num[0x4];
4520	u8         vport_number[0x10];
4521
4522	u8         reserved_3[0x20];
4523};
4524
4525struct mlx5_ifc_query_hca_cap_out_bits {
4526	u8         status[0x8];
4527	u8         reserved_0[0x18];
4528
4529	u8         syndrome[0x20];
4530
4531	u8         reserved_1[0x40];
4532
4533	union mlx5_ifc_hca_cap_union_bits capability;
4534};
4535
4536struct mlx5_ifc_query_hca_cap_in_bits {
4537	u8         opcode[0x10];
4538	u8         reserved_0[0x10];
4539
4540	u8         reserved_1[0x10];
4541	u8         op_mod[0x10];
4542
4543	u8         reserved_2[0x40];
4544};
4545
4546struct mlx5_ifc_query_flow_table_out_bits {
4547	u8         status[0x8];
4548	u8         reserved_at_8[0x18];
4549
4550	u8         syndrome[0x20];
4551
4552	u8         reserved_at_40[0x80];
4553
4554	struct mlx5_ifc_flow_table_context_bits flow_table_context;
4555};
4556
4557struct mlx5_ifc_query_flow_table_in_bits {
4558	u8         opcode[0x10];
4559	u8         reserved_0[0x10];
4560
4561	u8         reserved_1[0x10];
4562	u8         op_mod[0x10];
4563
4564	u8         other_vport[0x1];
4565	u8         reserved_2[0xf];
4566	u8         vport_number[0x10];
4567
4568	u8         reserved_3[0x20];
4569
4570	u8         table_type[0x8];
4571	u8         reserved_4[0x18];
4572
4573	u8         reserved_5[0x8];
4574	u8         table_id[0x18];
4575
4576	u8         reserved_6[0x140];
4577};
4578
4579struct mlx5_ifc_query_fte_out_bits {
4580	u8         status[0x8];
4581	u8         reserved_0[0x18];
4582
4583	u8         syndrome[0x20];
4584
4585	u8         reserved_1[0x1c0];
4586
4587	struct mlx5_ifc_flow_context_bits flow_context;
4588};
4589
4590struct mlx5_ifc_query_fte_in_bits {
4591	u8         opcode[0x10];
4592	u8         reserved_0[0x10];
4593
4594	u8         reserved_1[0x10];
4595	u8         op_mod[0x10];
4596
4597	u8         other_vport[0x1];
4598	u8         reserved_2[0xf];
4599	u8         vport_number[0x10];
4600
4601	u8         reserved_3[0x20];
4602
4603	u8         table_type[0x8];
4604	u8         reserved_4[0x18];
4605
4606	u8         reserved_5[0x8];
4607	u8         table_id[0x18];
4608
4609	u8         reserved_6[0x40];
4610
4611	u8         flow_index[0x20];
4612
4613	u8         reserved_7[0xe0];
4614};
4615
4616enum {
4617	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4618	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4619	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4620};
4621
4622struct mlx5_ifc_query_flow_group_out_bits {
4623	u8         status[0x8];
4624	u8         reserved_0[0x18];
4625
4626	u8         syndrome[0x20];
4627
4628	u8         reserved_1[0xa0];
4629
4630	u8         start_flow_index[0x20];
4631
4632	u8         reserved_2[0x20];
4633
4634	u8         end_flow_index[0x20];
4635
4636	u8         reserved_3[0xa0];
4637
4638	u8         reserved_4[0x18];
4639	u8         match_criteria_enable[0x8];
4640
4641	struct mlx5_ifc_fte_match_param_bits match_criteria;
4642
4643	u8         reserved_5[0xe00];
4644};
4645
4646struct mlx5_ifc_query_flow_group_in_bits {
4647	u8         opcode[0x10];
4648	u8         reserved_0[0x10];
4649
4650	u8         reserved_1[0x10];
4651	u8         op_mod[0x10];
4652
4653	u8         other_vport[0x1];
4654	u8         reserved_2[0xf];
4655	u8         vport_number[0x10];
4656
4657	u8         reserved_3[0x20];
4658
4659	u8         table_type[0x8];
4660	u8         reserved_4[0x18];
4661
4662	u8         reserved_5[0x8];
4663	u8         table_id[0x18];
4664
4665	u8         group_id[0x20];
4666
4667	u8         reserved_6[0x120];
4668};
4669
4670struct mlx5_ifc_query_flow_counter_out_bits {
4671	u8         status[0x8];
4672	u8         reserved_at_8[0x18];
4673
4674	u8         syndrome[0x20];
4675
4676	u8         reserved_at_40[0x40];
4677
4678	struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4679};
4680
4681struct mlx5_ifc_query_flow_counter_in_bits {
4682	u8         opcode[0x10];
4683	u8         reserved_at_10[0x10];
4684
4685	u8         reserved_at_20[0x10];
4686	u8         op_mod[0x10];
4687
4688	u8         reserved_at_40[0x80];
4689
4690	u8         clear[0x1];
4691	u8         reserved_at_c1[0xf];
4692	u8         num_of_counters[0x10];
4693
4694	u8         reserved_at_e0[0x10];
4695	u8         flow_counter_id[0x10];
4696};
4697
4698struct mlx5_ifc_query_esw_vport_context_out_bits {
4699	u8         status[0x8];
4700	u8         reserved_0[0x18];
4701
4702	u8         syndrome[0x20];
4703
4704	u8         reserved_1[0x40];
4705
4706	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4707};
4708
4709struct mlx5_ifc_query_esw_vport_context_in_bits {
4710	u8         opcode[0x10];
4711	u8         reserved_0[0x10];
4712
4713	u8         reserved_1[0x10];
4714	u8         op_mod[0x10];
4715
4716	u8         other_vport[0x1];
4717	u8         reserved_2[0xf];
4718	u8         vport_number[0x10];
4719
4720	u8         reserved_3[0x20];
4721};
4722
4723struct mlx5_ifc_query_eq_out_bits {
4724	u8         status[0x8];
4725	u8         reserved_0[0x18];
4726
4727	u8         syndrome[0x20];
4728
4729	u8         reserved_1[0x40];
4730
4731	struct mlx5_ifc_eqc_bits eq_context_entry;
4732
4733	u8         reserved_2[0x40];
4734
4735	u8         event_bitmask[0x40];
4736
4737	u8         reserved_3[0x580];
4738
4739	u8         pas[0][0x40];
4740};
4741
4742struct mlx5_ifc_query_eq_in_bits {
4743	u8         opcode[0x10];
4744	u8         reserved_0[0x10];
4745
4746	u8         reserved_1[0x10];
4747	u8         op_mod[0x10];
4748
4749	u8         reserved_2[0x18];
4750	u8         eq_number[0x8];
4751
4752	u8         reserved_3[0x20];
4753};
4754
4755struct mlx5_ifc_query_dct_out_bits {
4756	u8         status[0x8];
4757	u8         reserved_0[0x18];
4758
4759	u8         syndrome[0x20];
4760
4761	u8         reserved_1[0x40];
4762
4763	struct mlx5_ifc_dctc_bits dct_context_entry;
4764
4765	u8         reserved_2[0x180];
4766};
4767
4768struct mlx5_ifc_query_dct_in_bits {
4769	u8         opcode[0x10];
4770	u8         reserved_0[0x10];
4771
4772	u8         reserved_1[0x10];
4773	u8         op_mod[0x10];
4774
4775	u8         reserved_2[0x8];
4776	u8         dctn[0x18];
4777
4778	u8         reserved_3[0x20];
4779};
4780
4781struct mlx5_ifc_query_dc_cnak_trace_out_bits {
4782	u8         status[0x8];
4783	u8         reserved_0[0x18];
4784
4785	u8         syndrome[0x20];
4786
4787	u8         enable[0x1];
4788	u8         reserved_1[0x1f];
4789
4790	u8         reserved_2[0x160];
4791
4792	struct mlx5_ifc_cmd_pas_bits pas;
4793};
4794
4795struct mlx5_ifc_query_dc_cnak_trace_in_bits {
4796	u8         opcode[0x10];
4797	u8         reserved_0[0x10];
4798
4799	u8         reserved_1[0x10];
4800	u8         op_mod[0x10];
4801
4802	u8         reserved_2[0x40];
4803};
4804
4805struct mlx5_ifc_query_cq_out_bits {
4806	u8         status[0x8];
4807	u8         reserved_0[0x18];
4808
4809	u8         syndrome[0x20];
4810
4811	u8         reserved_1[0x40];
4812
4813	struct mlx5_ifc_cqc_bits cq_context;
4814
4815	u8         reserved_2[0x600];
4816
4817	u8         pas[0][0x40];
4818};
4819
4820struct mlx5_ifc_query_cq_in_bits {
4821	u8         opcode[0x10];
4822	u8         reserved_0[0x10];
4823
4824	u8         reserved_1[0x10];
4825	u8         op_mod[0x10];
4826
4827	u8         reserved_2[0x8];
4828	u8         cqn[0x18];
4829
4830	u8         reserved_3[0x20];
4831};
4832
4833struct mlx5_ifc_query_cong_status_out_bits {
4834	u8         status[0x8];
4835	u8         reserved_0[0x18];
4836
4837	u8         syndrome[0x20];
4838
4839	u8         reserved_1[0x20];
4840
4841	u8         enable[0x1];
4842	u8         tag_enable[0x1];
4843	u8         reserved_2[0x1e];
4844};
4845
4846struct mlx5_ifc_query_cong_status_in_bits {
4847	u8         opcode[0x10];
4848	u8         reserved_0[0x10];
4849
4850	u8         reserved_1[0x10];
4851	u8         op_mod[0x10];
4852
4853	u8         reserved_2[0x18];
4854	u8         priority[0x4];
4855	u8         cong_protocol[0x4];
4856
4857	u8         reserved_3[0x20];
4858};
4859
4860struct mlx5_ifc_query_cong_statistics_out_bits {
4861	u8         status[0x8];
4862	u8         reserved_0[0x18];
4863
4864	u8         syndrome[0x20];
4865
4866	u8         reserved_1[0x40];
4867
4868	u8         cur_flows[0x20];
4869
4870	u8         sum_flows[0x20];
4871
4872	u8         cnp_ignored_high[0x20];
4873
4874	u8         cnp_ignored_low[0x20];
4875
4876	u8         cnp_handled_high[0x20];
4877
4878	u8         cnp_handled_low[0x20];
4879
4880	u8         reserved_2[0x100];
4881
4882	u8         time_stamp_high[0x20];
4883
4884	u8         time_stamp_low[0x20];
4885
4886	u8         accumulators_period[0x20];
4887
4888	u8         ecn_marked_roce_packets_high[0x20];
4889
4890	u8         ecn_marked_roce_packets_low[0x20];
4891
4892	u8         cnps_sent_high[0x20];
4893
4894	u8         cnps_sent_low[0x20];
4895
4896	u8         reserved_3[0x560];
4897};
4898
4899struct mlx5_ifc_query_cong_statistics_in_bits {
4900	u8         opcode[0x10];
4901	u8         reserved_0[0x10];
4902
4903	u8         reserved_1[0x10];
4904	u8         op_mod[0x10];
4905
4906	u8         clear[0x1];
4907	u8         reserved_2[0x1f];
4908
4909	u8         reserved_3[0x20];
4910};
4911
4912struct mlx5_ifc_query_cong_params_out_bits {
4913	u8         status[0x8];
4914	u8         reserved_0[0x18];
4915
4916	u8         syndrome[0x20];
4917
4918	u8         reserved_1[0x40];
4919
4920	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4921};
4922
4923struct mlx5_ifc_query_cong_params_in_bits {
4924	u8         opcode[0x10];
4925	u8         reserved_0[0x10];
4926
4927	u8         reserved_1[0x10];
4928	u8         op_mod[0x10];
4929
4930	u8         reserved_2[0x1c];
4931	u8         cong_protocol[0x4];
4932
4933	u8         reserved_3[0x20];
4934};
4935
4936struct mlx5_ifc_query_burst_size_out_bits {
4937	u8         status[0x8];
4938	u8         reserved_0[0x18];
4939
4940	u8         syndrome[0x20];
4941
4942	u8         reserved_1[0x20];
4943
4944	u8         reserved_2[0x9];
4945	u8         device_burst_size[0x17];
4946};
4947
4948struct mlx5_ifc_query_burst_size_in_bits {
4949	u8         opcode[0x10];
4950	u8         reserved_0[0x10];
4951
4952	u8         reserved_1[0x10];
4953	u8         op_mod[0x10];
4954
4955	u8         reserved_2[0x40];
4956};
4957
4958struct mlx5_ifc_query_adapter_out_bits {
4959	u8         status[0x8];
4960	u8         reserved_0[0x18];
4961
4962	u8         syndrome[0x20];
4963
4964	u8         reserved_1[0x40];
4965
4966	struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4967};
4968
4969struct mlx5_ifc_query_adapter_in_bits {
4970	u8         opcode[0x10];
4971	u8         reserved_0[0x10];
4972
4973	u8         reserved_1[0x10];
4974	u8         op_mod[0x10];
4975
4976	u8         reserved_2[0x40];
4977};
4978
4979struct mlx5_ifc_qp_2rst_out_bits {
4980	u8         status[0x8];
4981	u8         reserved_0[0x18];
4982
4983	u8         syndrome[0x20];
4984
4985	u8         reserved_1[0x40];
4986};
4987
4988struct mlx5_ifc_qp_2rst_in_bits {
4989	u8         opcode[0x10];
4990	u8         reserved_0[0x10];
4991
4992	u8         reserved_1[0x10];
4993	u8         op_mod[0x10];
4994
4995	u8         reserved_2[0x8];
4996	u8         qpn[0x18];
4997
4998	u8         reserved_3[0x20];
4999};
5000
5001struct mlx5_ifc_qp_2err_out_bits {
5002	u8         status[0x8];
5003	u8         reserved_0[0x18];
5004
5005	u8         syndrome[0x20];
5006
5007	u8         reserved_1[0x40];
5008};
5009
5010struct mlx5_ifc_qp_2err_in_bits {
5011	u8         opcode[0x10];
5012	u8         reserved_0[0x10];
5013
5014	u8         reserved_1[0x10];
5015	u8         op_mod[0x10];
5016
5017	u8         reserved_2[0x8];
5018	u8         qpn[0x18];
5019
5020	u8         reserved_3[0x20];
5021};
5022
5023struct mlx5_ifc_para_vport_element_bits {
5024	u8         reserved_at_0[0xc];
5025	u8         traffic_class[0x4];
5026	u8         qos_para_vport_number[0x10];
5027};
5028
5029struct mlx5_ifc_page_fault_resume_out_bits {
5030	u8         status[0x8];
5031	u8         reserved_0[0x18];
5032
5033	u8         syndrome[0x20];
5034
5035	u8         reserved_1[0x40];
5036};
5037
5038struct mlx5_ifc_page_fault_resume_in_bits {
5039	u8         opcode[0x10];
5040	u8         reserved_0[0x10];
5041
5042	u8         reserved_1[0x10];
5043	u8         op_mod[0x10];
5044
5045	u8         error[0x1];
5046	u8         reserved_2[0x4];
5047	u8         rdma[0x1];
5048	u8         read_write[0x1];
5049	u8         req_res[0x1];
5050	u8         qpn[0x18];
5051
5052	u8         reserved_3[0x20];
5053};
5054
5055struct mlx5_ifc_nop_out_bits {
5056	u8         status[0x8];
5057	u8         reserved_0[0x18];
5058
5059	u8         syndrome[0x20];
5060
5061	u8         reserved_1[0x40];
5062};
5063
5064struct mlx5_ifc_nop_in_bits {
5065	u8         opcode[0x10];
5066	u8         reserved_0[0x10];
5067
5068	u8         reserved_1[0x10];
5069	u8         op_mod[0x10];
5070
5071	u8         reserved_2[0x40];
5072};
5073
5074struct mlx5_ifc_modify_vport_state_out_bits {
5075	u8         status[0x8];
5076	u8         reserved_0[0x18];
5077
5078	u8         syndrome[0x20];
5079
5080	u8         reserved_1[0x40];
5081};
5082
5083enum {
5084	MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT  = 0x0,
5085	MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT  = 0x1,
5086	MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK     = 0x2,
5087};
5088
5089enum {
5090	MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN    = 0x0,
5091	MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP      = 0x1,
5092	MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW  = 0x2,
5093};
5094
5095struct mlx5_ifc_modify_vport_state_in_bits {
5096	u8         opcode[0x10];
5097	u8         reserved_0[0x10];
5098
5099	u8         reserved_1[0x10];
5100	u8         op_mod[0x10];
5101
5102	u8         other_vport[0x1];
5103	u8         reserved_2[0xf];
5104	u8         vport_number[0x10];
5105
5106	u8         reserved_3[0x18];
5107	u8         admin_state[0x4];
5108	u8         reserved_4[0x4];
5109};
5110
5111struct mlx5_ifc_modify_tis_out_bits {
5112	u8         status[0x8];
5113	u8         reserved_0[0x18];
5114
5115	u8         syndrome[0x20];
5116
5117	u8         reserved_1[0x40];
5118};
5119
5120struct mlx5_ifc_modify_tis_bitmask_bits {
5121	u8         reserved_at_0[0x20];
5122
5123	u8         reserved_at_20[0x1d];
5124	u8         lag_tx_port_affinity[0x1];
5125	u8         strict_lag_tx_port_affinity[0x1];
5126	u8         prio[0x1];
5127};
5128
5129struct mlx5_ifc_modify_tis_in_bits {
5130	u8         opcode[0x10];
5131	u8         reserved_0[0x10];
5132
5133	u8         reserved_1[0x10];
5134	u8         op_mod[0x10];
5135
5136	u8         reserved_2[0x8];
5137	u8         tisn[0x18];
5138
5139	u8         reserved_3[0x20];
5140
5141	struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5142
5143	u8         reserved_4[0x40];
5144
5145	struct mlx5_ifc_tisc_bits ctx;
5146};
5147
5148struct mlx5_ifc_modify_tir_out_bits {
5149	u8         status[0x8];
5150	u8         reserved_0[0x18];
5151
5152	u8         syndrome[0x20];
5153
5154	u8         reserved_1[0x40];
5155};
5156
5157enum
5158{
5159	MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0,
5160	MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER =		0x1 << 1
5161};
5162
5163struct mlx5_ifc_modify_tir_in_bits {
5164	u8         opcode[0x10];
5165	u8         reserved_0[0x10];
5166
5167	u8         reserved_1[0x10];
5168	u8         op_mod[0x10];
5169
5170	u8         reserved_2[0x8];
5171	u8         tirn[0x18];
5172
5173	u8         reserved_3[0x20];
5174
5175	u8         modify_bitmask[0x40];
5176
5177	u8         reserved_4[0x40];
5178
5179	struct mlx5_ifc_tirc_bits tir_context;
5180};
5181
5182struct mlx5_ifc_modify_sq_out_bits {
5183	u8         status[0x8];
5184	u8         reserved_0[0x18];
5185
5186	u8         syndrome[0x20];
5187
5188	u8         reserved_1[0x40];
5189};
5190
5191struct mlx5_ifc_modify_sq_in_bits {
5192	u8         opcode[0x10];
5193	u8         reserved_0[0x10];
5194
5195	u8         reserved_1[0x10];
5196	u8         op_mod[0x10];
5197
5198	u8         sq_state[0x4];
5199	u8         reserved_2[0x4];
5200	u8         sqn[0x18];
5201
5202	u8         reserved_3[0x20];
5203
5204	u8         modify_bitmask[0x40];
5205
5206	u8         reserved_4[0x40];
5207
5208	struct mlx5_ifc_sqc_bits ctx;
5209};
5210
5211struct mlx5_ifc_modify_scheduling_element_out_bits {
5212	u8         status[0x8];
5213	u8         reserved_at_8[0x18];
5214
5215	u8         syndrome[0x20];
5216
5217	u8         reserved_at_40[0x1c0];
5218};
5219
5220enum {
5221	MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
5222};
5223
5224enum {
5225	MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE        = 0x1,
5226	MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW  = 0x2,
5227};
5228
5229struct mlx5_ifc_modify_scheduling_element_in_bits {
5230	u8         opcode[0x10];
5231	u8         reserved_at_10[0x10];
5232
5233	u8         reserved_at_20[0x10];
5234	u8         op_mod[0x10];
5235
5236	u8         scheduling_hierarchy[0x8];
5237	u8         reserved_at_48[0x18];
5238
5239	u8         scheduling_element_id[0x20];
5240
5241	u8         reserved_at_80[0x20];
5242
5243	u8         modify_bitmask[0x20];
5244
5245	u8         reserved_at_c0[0x40];
5246
5247	struct mlx5_ifc_scheduling_context_bits scheduling_context;
5248
5249	u8         reserved_at_300[0x100];
5250};
5251
5252struct mlx5_ifc_modify_rqt_out_bits {
5253	u8         status[0x8];
5254	u8         reserved_0[0x18];
5255
5256	u8         syndrome[0x20];
5257
5258	u8         reserved_1[0x40];
5259};
5260
5261struct mlx5_ifc_modify_rqt_in_bits {
5262	u8         opcode[0x10];
5263	u8         reserved_0[0x10];
5264
5265	u8         reserved_1[0x10];
5266	u8         op_mod[0x10];
5267
5268	u8         reserved_2[0x8];
5269	u8         rqtn[0x18];
5270
5271	u8         reserved_3[0x20];
5272
5273	u8         modify_bitmask[0x40];
5274
5275	u8         reserved_4[0x40];
5276
5277	struct mlx5_ifc_rqtc_bits ctx;
5278};
5279
5280struct mlx5_ifc_modify_rq_out_bits {
5281	u8         status[0x8];
5282	u8         reserved_0[0x18];
5283
5284	u8         syndrome[0x20];
5285
5286	u8         reserved_1[0x40];
5287};
5288
5289enum {
5290	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5291	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
5292};
5293
5294struct mlx5_ifc_modify_rq_in_bits {
5295	u8         opcode[0x10];
5296	u8         reserved_0[0x10];
5297
5298	u8         reserved_1[0x10];
5299	u8         op_mod[0x10];
5300
5301	u8         rq_state[0x4];
5302	u8         reserved_2[0x4];
5303	u8         rqn[0x18];
5304
5305	u8         reserved_3[0x20];
5306
5307	u8         modify_bitmask[0x40];
5308
5309	u8         reserved_4[0x40];
5310
5311	struct mlx5_ifc_rqc_bits ctx;
5312};
5313
5314struct mlx5_ifc_modify_rmp_out_bits {
5315	u8         status[0x8];
5316	u8         reserved_0[0x18];
5317
5318	u8         syndrome[0x20];
5319
5320	u8         reserved_1[0x40];
5321};
5322
5323struct mlx5_ifc_rmp_bitmask_bits {
5324	u8	   reserved[0x20];
5325
5326	u8         reserved1[0x1f];
5327	u8         lwm[0x1];
5328};
5329
5330struct mlx5_ifc_modify_rmp_in_bits {
5331	u8         opcode[0x10];
5332	u8         reserved_0[0x10];
5333
5334	u8         reserved_1[0x10];
5335	u8         op_mod[0x10];
5336
5337	u8         rmp_state[0x4];
5338	u8         reserved_2[0x4];
5339	u8         rmpn[0x18];
5340
5341	u8         reserved_3[0x20];
5342
5343	struct mlx5_ifc_rmp_bitmask_bits bitmask;
5344
5345	u8         reserved_4[0x40];
5346
5347	struct mlx5_ifc_rmpc_bits ctx;
5348};
5349
5350struct mlx5_ifc_modify_nic_vport_context_out_bits {
5351	u8         status[0x8];
5352	u8         reserved_0[0x18];
5353
5354	u8         syndrome[0x20];
5355
5356	u8         reserved_1[0x40];
5357};
5358
5359struct mlx5_ifc_modify_nic_vport_field_select_bits {
5360	u8         reserved_0[0x14];
5361	u8         disable_uc_local_lb[0x1];
5362	u8         disable_mc_local_lb[0x1];
5363	u8         node_guid[0x1];
5364	u8         port_guid[0x1];
5365	u8         min_wqe_inline_mode[0x1];
5366	u8         mtu[0x1];
5367	u8         change_event[0x1];
5368	u8         promisc[0x1];
5369	u8         permanent_address[0x1];
5370	u8         addresses_list[0x1];
5371	u8         roce_en[0x1];
5372	u8         reserved_1[0x1];
5373};
5374
5375struct mlx5_ifc_modify_nic_vport_context_in_bits {
5376	u8         opcode[0x10];
5377	u8         reserved_0[0x10];
5378
5379	u8         reserved_1[0x10];
5380	u8         op_mod[0x10];
5381
5382	u8         other_vport[0x1];
5383	u8         reserved_2[0xf];
5384	u8         vport_number[0x10];
5385
5386	struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5387
5388	u8         reserved_3[0x780];
5389
5390	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5391};
5392
5393struct mlx5_ifc_modify_hca_vport_context_out_bits {
5394	u8         status[0x8];
5395	u8         reserved_0[0x18];
5396
5397	u8         syndrome[0x20];
5398
5399	u8         reserved_1[0x40];
5400};
5401
5402struct mlx5_ifc_grh_bits {
5403	u8	ip_version[4];
5404	u8	traffic_class[8];
5405	u8	flow_label[20];
5406	u8	payload_length[16];
5407	u8	next_header[8];
5408	u8	hop_limit[8];
5409	u8	sgid[128];
5410	u8	dgid[128];
5411};
5412
5413struct mlx5_ifc_bth_bits {
5414	u8	opcode[8];
5415	u8	se[1];
5416	u8	migreq[1];
5417	u8	pad_count[2];
5418	u8	tver[4];
5419	u8	p_key[16];
5420	u8	reserved8[8];
5421	u8	dest_qp[24];
5422	u8	ack_req[1];
5423	u8	reserved7[7];
5424	u8	psn[24];
5425};
5426
5427struct mlx5_ifc_aeth_bits {
5428	u8	syndrome[8];
5429	u8	msn[24];
5430};
5431
5432struct mlx5_ifc_dceth_bits {
5433	u8	reserved0[8];
5434	u8	session_id[24];
5435	u8	reserved1[8];
5436	u8	dci_dct[24];
5437};
5438
5439struct mlx5_ifc_modify_hca_vport_context_in_bits {
5440	u8         opcode[0x10];
5441	u8         reserved_0[0x10];
5442
5443	u8         reserved_1[0x10];
5444	u8         op_mod[0x10];
5445
5446	u8         other_vport[0x1];
5447	u8         reserved_2[0xb];
5448	u8         port_num[0x4];
5449	u8         vport_number[0x10];
5450
5451	u8         reserved_3[0x20];
5452
5453	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5454};
5455
5456struct mlx5_ifc_modify_flow_table_out_bits {
5457	u8         status[0x8];
5458	u8         reserved_at_8[0x18];
5459
5460	u8         syndrome[0x20];
5461
5462	u8         reserved_at_40[0x40];
5463};
5464
5465enum {
5466	MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1,
5467	MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000,
5468};
5469
5470struct mlx5_ifc_modify_flow_table_in_bits {
5471	u8         opcode[0x10];
5472	u8         reserved_at_10[0x10];
5473
5474	u8         reserved_at_20[0x10];
5475	u8         op_mod[0x10];
5476
5477	u8         other_vport[0x1];
5478	u8         reserved_at_41[0xf];
5479	u8         vport_number[0x10];
5480
5481	u8         reserved_at_60[0x10];
5482	u8         modify_field_select[0x10];
5483
5484	u8         table_type[0x8];
5485	u8         reserved_at_88[0x18];
5486
5487	u8         reserved_at_a0[0x8];
5488	u8         table_id[0x18];
5489
5490	struct mlx5_ifc_flow_table_context_bits flow_table_context;
5491};
5492
5493struct mlx5_ifc_modify_esw_vport_context_out_bits {
5494	u8         status[0x8];
5495	u8         reserved_0[0x18];
5496
5497	u8         syndrome[0x20];
5498
5499	u8         reserved_1[0x40];
5500};
5501
5502struct mlx5_ifc_esw_vport_context_fields_select_bits {
5503	u8         reserved[0x1c];
5504	u8         vport_cvlan_insert[0x1];
5505	u8         vport_svlan_insert[0x1];
5506	u8         vport_cvlan_strip[0x1];
5507	u8         vport_svlan_strip[0x1];
5508};
5509
5510struct mlx5_ifc_modify_esw_vport_context_in_bits {
5511	u8         opcode[0x10];
5512	u8         reserved_0[0x10];
5513
5514	u8         reserved_1[0x10];
5515	u8         op_mod[0x10];
5516
5517	u8         other_vport[0x1];
5518	u8         reserved_2[0xf];
5519	u8         vport_number[0x10];
5520
5521	struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5522
5523	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5524};
5525
5526struct mlx5_ifc_modify_cq_out_bits {
5527	u8         status[0x8];
5528	u8         reserved_0[0x18];
5529
5530	u8         syndrome[0x20];
5531
5532	u8         reserved_1[0x40];
5533};
5534
5535enum {
5536	MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5537	MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5538};
5539
5540struct mlx5_ifc_modify_cq_in_bits {
5541	u8         opcode[0x10];
5542	u8         reserved_0[0x10];
5543
5544	u8         reserved_1[0x10];
5545	u8         op_mod[0x10];
5546
5547	u8         reserved_2[0x8];
5548	u8         cqn[0x18];
5549
5550	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5551
5552	struct mlx5_ifc_cqc_bits cq_context;
5553
5554	u8         reserved_3[0x600];
5555
5556	u8         pas[0][0x40];
5557};
5558
5559struct mlx5_ifc_modify_cong_status_out_bits {
5560	u8         status[0x8];
5561	u8         reserved_0[0x18];
5562
5563	u8         syndrome[0x20];
5564
5565	u8         reserved_1[0x40];
5566};
5567
5568struct mlx5_ifc_modify_cong_status_in_bits {
5569	u8         opcode[0x10];
5570	u8         reserved_0[0x10];
5571
5572	u8         reserved_1[0x10];
5573	u8         op_mod[0x10];
5574
5575	u8         reserved_2[0x18];
5576	u8         priority[0x4];
5577	u8         cong_protocol[0x4];
5578
5579	u8         enable[0x1];
5580	u8         tag_enable[0x1];
5581	u8         reserved_3[0x1e];
5582};
5583
5584struct mlx5_ifc_modify_cong_params_out_bits {
5585	u8         status[0x8];
5586	u8         reserved_0[0x18];
5587
5588	u8         syndrome[0x20];
5589
5590	u8         reserved_1[0x40];
5591};
5592
5593struct mlx5_ifc_modify_cong_params_in_bits {
5594	u8         opcode[0x10];
5595	u8         reserved_0[0x10];
5596
5597	u8         reserved_1[0x10];
5598	u8         op_mod[0x10];
5599
5600	u8         reserved_2[0x1c];
5601	u8         cong_protocol[0x4];
5602
5603	union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5604
5605	u8         reserved_3[0x80];
5606
5607	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5608};
5609
5610struct mlx5_ifc_manage_pages_out_bits {
5611	u8         status[0x8];
5612	u8         reserved_0[0x18];
5613
5614	u8         syndrome[0x20];
5615
5616	u8         output_num_entries[0x20];
5617
5618	u8         reserved_1[0x20];
5619
5620	u8         pas[0][0x40];
5621};
5622
5623enum {
5624	MLX5_PAGES_CANT_GIVE                            = 0x0,
5625	MLX5_PAGES_GIVE                                 = 0x1,
5626	MLX5_PAGES_TAKE                                 = 0x2,
5627};
5628
5629struct mlx5_ifc_manage_pages_in_bits {
5630	u8         opcode[0x10];
5631	u8         reserved_0[0x10];
5632
5633	u8         reserved_1[0x10];
5634	u8         op_mod[0x10];
5635
5636	u8         reserved_2[0x10];
5637	u8         function_id[0x10];
5638
5639	u8         input_num_entries[0x20];
5640
5641	u8         pas[0][0x40];
5642};
5643
5644struct mlx5_ifc_mad_ifc_out_bits {
5645	u8         status[0x8];
5646	u8         reserved_0[0x18];
5647
5648	u8         syndrome[0x20];
5649
5650	u8         reserved_1[0x40];
5651
5652	u8         response_mad_packet[256][0x8];
5653};
5654
5655struct mlx5_ifc_mad_ifc_in_bits {
5656	u8         opcode[0x10];
5657	u8         reserved_0[0x10];
5658
5659	u8         reserved_1[0x10];
5660	u8         op_mod[0x10];
5661
5662	u8         remote_lid[0x10];
5663	u8         reserved_2[0x8];
5664	u8         port[0x8];
5665
5666	u8         reserved_3[0x20];
5667
5668	u8         mad[256][0x8];
5669};
5670
5671struct mlx5_ifc_init_hca_out_bits {
5672	u8         status[0x8];
5673	u8         reserved_0[0x18];
5674
5675	u8         syndrome[0x20];
5676
5677	u8         reserved_1[0x40];
5678};
5679
5680enum {
5681	MLX5_INIT_HCA_IN_OP_MOD_INIT      = 0x0,
5682	MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT  = 0x1,
5683};
5684
5685struct mlx5_ifc_init_hca_in_bits {
5686	u8         opcode[0x10];
5687	u8         reserved_0[0x10];
5688
5689	u8         reserved_1[0x10];
5690	u8         op_mod[0x10];
5691
5692	u8         reserved_2[0x40];
5693};
5694
5695struct mlx5_ifc_init2rtr_qp_out_bits {
5696	u8         status[0x8];
5697	u8         reserved_0[0x18];
5698
5699	u8         syndrome[0x20];
5700
5701	u8         reserved_1[0x40];
5702};
5703
5704struct mlx5_ifc_init2rtr_qp_in_bits {
5705	u8         opcode[0x10];
5706	u8         reserved_0[0x10];
5707
5708	u8         reserved_1[0x10];
5709	u8         op_mod[0x10];
5710
5711	u8         reserved_2[0x8];
5712	u8         qpn[0x18];
5713
5714	u8         reserved_3[0x20];
5715
5716	u8         opt_param_mask[0x20];
5717
5718	u8         reserved_4[0x20];
5719
5720	struct mlx5_ifc_qpc_bits qpc;
5721
5722	u8         reserved_5[0x80];
5723};
5724
5725struct mlx5_ifc_init2init_qp_out_bits {
5726	u8         status[0x8];
5727	u8         reserved_0[0x18];
5728
5729	u8         syndrome[0x20];
5730
5731	u8         reserved_1[0x40];
5732};
5733
5734struct mlx5_ifc_init2init_qp_in_bits {
5735	u8         opcode[0x10];
5736	u8         reserved_0[0x10];
5737
5738	u8         reserved_1[0x10];
5739	u8         op_mod[0x10];
5740
5741	u8         reserved_2[0x8];
5742	u8         qpn[0x18];
5743
5744	u8         reserved_3[0x20];
5745
5746	u8         opt_param_mask[0x20];
5747
5748	u8         reserved_4[0x20];
5749
5750	struct mlx5_ifc_qpc_bits qpc;
5751
5752	u8         reserved_5[0x80];
5753};
5754
5755struct mlx5_ifc_get_dropped_packet_log_out_bits {
5756	u8         status[0x8];
5757	u8         reserved_0[0x18];
5758
5759	u8         syndrome[0x20];
5760
5761	u8         reserved_1[0x40];
5762
5763	u8         packet_headers_log[128][0x8];
5764
5765	u8         packet_syndrome[64][0x8];
5766};
5767
5768struct mlx5_ifc_get_dropped_packet_log_in_bits {
5769	u8         opcode[0x10];
5770	u8         reserved_0[0x10];
5771
5772	u8         reserved_1[0x10];
5773	u8         op_mod[0x10];
5774
5775	u8         reserved_2[0x40];
5776};
5777
5778struct mlx5_ifc_gen_eqe_in_bits {
5779	u8         opcode[0x10];
5780	u8         reserved_0[0x10];
5781
5782	u8         reserved_1[0x10];
5783	u8         op_mod[0x10];
5784
5785	u8         reserved_2[0x18];
5786	u8         eq_number[0x8];
5787
5788	u8         reserved_3[0x20];
5789
5790	u8         eqe[64][0x8];
5791};
5792
5793struct mlx5_ifc_gen_eq_out_bits {
5794	u8         status[0x8];
5795	u8         reserved_0[0x18];
5796
5797	u8         syndrome[0x20];
5798
5799	u8         reserved_1[0x40];
5800};
5801
5802struct mlx5_ifc_enable_hca_out_bits {
5803	u8         status[0x8];
5804	u8         reserved_0[0x18];
5805
5806	u8         syndrome[0x20];
5807
5808	u8         reserved_1[0x20];
5809};
5810
5811struct mlx5_ifc_enable_hca_in_bits {
5812	u8         opcode[0x10];
5813	u8         reserved_0[0x10];
5814
5815	u8         reserved_1[0x10];
5816	u8         op_mod[0x10];
5817
5818	u8         reserved_2[0x10];
5819	u8         function_id[0x10];
5820
5821	u8         reserved_3[0x20];
5822};
5823
5824struct mlx5_ifc_drain_dct_out_bits {
5825	u8         status[0x8];
5826	u8         reserved_0[0x18];
5827
5828	u8         syndrome[0x20];
5829
5830	u8         reserved_1[0x40];
5831};
5832
5833struct mlx5_ifc_drain_dct_in_bits {
5834	u8         opcode[0x10];
5835	u8         reserved_0[0x10];
5836
5837	u8         reserved_1[0x10];
5838	u8         op_mod[0x10];
5839
5840	u8         reserved_2[0x8];
5841	u8         dctn[0x18];
5842
5843	u8         reserved_3[0x20];
5844};
5845
5846struct mlx5_ifc_disable_hca_out_bits {
5847	u8         status[0x8];
5848	u8         reserved_0[0x18];
5849
5850	u8         syndrome[0x20];
5851
5852	u8         reserved_1[0x20];
5853};
5854
5855struct mlx5_ifc_disable_hca_in_bits {
5856	u8         opcode[0x10];
5857	u8         reserved_0[0x10];
5858
5859	u8         reserved_1[0x10];
5860	u8         op_mod[0x10];
5861
5862	u8         reserved_2[0x10];
5863	u8         function_id[0x10];
5864
5865	u8         reserved_3[0x20];
5866};
5867
5868struct mlx5_ifc_detach_from_mcg_out_bits {
5869	u8         status[0x8];
5870	u8         reserved_0[0x18];
5871
5872	u8         syndrome[0x20];
5873
5874	u8         reserved_1[0x40];
5875};
5876
5877struct mlx5_ifc_detach_from_mcg_in_bits {
5878	u8         opcode[0x10];
5879	u8         reserved_0[0x10];
5880
5881	u8         reserved_1[0x10];
5882	u8         op_mod[0x10];
5883
5884	u8         reserved_2[0x8];
5885	u8         qpn[0x18];
5886
5887	u8         reserved_3[0x20];
5888
5889	u8         multicast_gid[16][0x8];
5890};
5891
5892struct mlx5_ifc_destroy_xrc_srq_out_bits {
5893	u8         status[0x8];
5894	u8         reserved_0[0x18];
5895
5896	u8         syndrome[0x20];
5897
5898	u8         reserved_1[0x40];
5899};
5900
5901struct mlx5_ifc_destroy_xrc_srq_in_bits {
5902	u8         opcode[0x10];
5903	u8         reserved_0[0x10];
5904
5905	u8         reserved_1[0x10];
5906	u8         op_mod[0x10];
5907
5908	u8         reserved_2[0x8];
5909	u8         xrc_srqn[0x18];
5910
5911	u8         reserved_3[0x20];
5912};
5913
5914struct mlx5_ifc_destroy_tis_out_bits {
5915	u8         status[0x8];
5916	u8         reserved_0[0x18];
5917
5918	u8         syndrome[0x20];
5919
5920	u8         reserved_1[0x40];
5921};
5922
5923struct mlx5_ifc_destroy_tis_in_bits {
5924	u8         opcode[0x10];
5925	u8         reserved_0[0x10];
5926
5927	u8         reserved_1[0x10];
5928	u8         op_mod[0x10];
5929
5930	u8         reserved_2[0x8];
5931	u8         tisn[0x18];
5932
5933	u8         reserved_3[0x20];
5934};
5935
5936struct mlx5_ifc_destroy_tir_out_bits {
5937	u8         status[0x8];
5938	u8         reserved_0[0x18];
5939
5940	u8         syndrome[0x20];
5941
5942	u8         reserved_1[0x40];
5943};
5944
5945struct mlx5_ifc_destroy_tir_in_bits {
5946	u8         opcode[0x10];
5947	u8         reserved_0[0x10];
5948
5949	u8         reserved_1[0x10];
5950	u8         op_mod[0x10];
5951
5952	u8         reserved_2[0x8];
5953	u8         tirn[0x18];
5954
5955	u8         reserved_3[0x20];
5956};
5957
5958struct mlx5_ifc_destroy_srq_out_bits {
5959	u8         status[0x8];
5960	u8         reserved_0[0x18];
5961
5962	u8         syndrome[0x20];
5963
5964	u8         reserved_1[0x40];
5965};
5966
5967struct mlx5_ifc_destroy_srq_in_bits {
5968	u8         opcode[0x10];
5969	u8         reserved_0[0x10];
5970
5971	u8         reserved_1[0x10];
5972	u8         op_mod[0x10];
5973
5974	u8         reserved_2[0x8];
5975	u8         srqn[0x18];
5976
5977	u8         reserved_3[0x20];
5978};
5979
5980struct mlx5_ifc_destroy_sq_out_bits {
5981	u8         status[0x8];
5982	u8         reserved_0[0x18];
5983
5984	u8         syndrome[0x20];
5985
5986	u8         reserved_1[0x40];
5987};
5988
5989struct mlx5_ifc_destroy_sq_in_bits {
5990	u8         opcode[0x10];
5991	u8         reserved_0[0x10];
5992
5993	u8         reserved_1[0x10];
5994	u8         op_mod[0x10];
5995
5996	u8         reserved_2[0x8];
5997	u8         sqn[0x18];
5998
5999	u8         reserved_3[0x20];
6000};
6001
6002struct mlx5_ifc_destroy_scheduling_element_out_bits {
6003	u8         status[0x8];
6004	u8         reserved_at_8[0x18];
6005
6006	u8         syndrome[0x20];
6007
6008	u8         reserved_at_40[0x1c0];
6009};
6010
6011enum {
6012	MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
6013};
6014
6015struct mlx5_ifc_destroy_scheduling_element_in_bits {
6016	u8         opcode[0x10];
6017	u8         reserved_at_10[0x10];
6018
6019	u8         reserved_at_20[0x10];
6020	u8         op_mod[0x10];
6021
6022	u8         scheduling_hierarchy[0x8];
6023	u8         reserved_at_48[0x18];
6024
6025	u8         scheduling_element_id[0x20];
6026
6027	u8         reserved_at_80[0x180];
6028};
6029
6030struct mlx5_ifc_destroy_rqt_out_bits {
6031	u8         status[0x8];
6032	u8         reserved_0[0x18];
6033
6034	u8         syndrome[0x20];
6035
6036	u8         reserved_1[0x40];
6037};
6038
6039struct mlx5_ifc_destroy_rqt_in_bits {
6040	u8         opcode[0x10];
6041	u8         reserved_0[0x10];
6042
6043	u8         reserved_1[0x10];
6044	u8         op_mod[0x10];
6045
6046	u8         reserved_2[0x8];
6047	u8         rqtn[0x18];
6048
6049	u8         reserved_3[0x20];
6050};
6051
6052struct mlx5_ifc_destroy_rq_out_bits {
6053	u8         status[0x8];
6054	u8         reserved_0[0x18];
6055
6056	u8         syndrome[0x20];
6057
6058	u8         reserved_1[0x40];
6059};
6060
6061struct mlx5_ifc_destroy_rq_in_bits {
6062	u8         opcode[0x10];
6063	u8         reserved_0[0x10];
6064
6065	u8         reserved_1[0x10];
6066	u8         op_mod[0x10];
6067
6068	u8         reserved_2[0x8];
6069	u8         rqn[0x18];
6070
6071	u8         reserved_3[0x20];
6072};
6073
6074struct mlx5_ifc_destroy_rmp_out_bits {
6075	u8         status[0x8];
6076	u8         reserved_0[0x18];
6077
6078	u8         syndrome[0x20];
6079
6080	u8         reserved_1[0x40];
6081};
6082
6083struct mlx5_ifc_destroy_rmp_in_bits {
6084	u8         opcode[0x10];
6085	u8         reserved_0[0x10];
6086
6087	u8         reserved_1[0x10];
6088	u8         op_mod[0x10];
6089
6090	u8         reserved_2[0x8];
6091	u8         rmpn[0x18];
6092
6093	u8         reserved_3[0x20];
6094};
6095
6096struct mlx5_ifc_destroy_qp_out_bits {
6097	u8         status[0x8];
6098	u8         reserved_0[0x18];
6099
6100	u8         syndrome[0x20];
6101
6102	u8         reserved_1[0x40];
6103};
6104
6105struct mlx5_ifc_destroy_qp_in_bits {
6106	u8         opcode[0x10];
6107	u8         reserved_0[0x10];
6108
6109	u8         reserved_1[0x10];
6110	u8         op_mod[0x10];
6111
6112	u8         reserved_2[0x8];
6113	u8         qpn[0x18];
6114
6115	u8         reserved_3[0x20];
6116};
6117
6118struct mlx5_ifc_destroy_qos_para_vport_out_bits {
6119	u8         status[0x8];
6120	u8         reserved_at_8[0x18];
6121
6122	u8         syndrome[0x20];
6123
6124	u8         reserved_at_40[0x1c0];
6125};
6126
6127struct mlx5_ifc_destroy_qos_para_vport_in_bits {
6128	u8         opcode[0x10];
6129	u8         reserved_at_10[0x10];
6130
6131	u8         reserved_at_20[0x10];
6132	u8         op_mod[0x10];
6133
6134	u8         reserved_at_40[0x20];
6135
6136	u8         reserved_at_60[0x10];
6137	u8         qos_para_vport_number[0x10];
6138
6139	u8         reserved_at_80[0x180];
6140};
6141
6142struct mlx5_ifc_destroy_psv_out_bits {
6143	u8         status[0x8];
6144	u8         reserved_0[0x18];
6145
6146	u8         syndrome[0x20];
6147
6148	u8         reserved_1[0x40];
6149};
6150
6151struct mlx5_ifc_destroy_psv_in_bits {
6152	u8         opcode[0x10];
6153	u8         reserved_0[0x10];
6154
6155	u8         reserved_1[0x10];
6156	u8         op_mod[0x10];
6157
6158	u8         reserved_2[0x8];
6159	u8         psvn[0x18];
6160
6161	u8         reserved_3[0x20];
6162};
6163
6164struct mlx5_ifc_destroy_mkey_out_bits {
6165	u8         status[0x8];
6166	u8         reserved_0[0x18];
6167
6168	u8         syndrome[0x20];
6169
6170	u8         reserved_1[0x40];
6171};
6172
6173struct mlx5_ifc_destroy_mkey_in_bits {
6174	u8         opcode[0x10];
6175	u8         reserved_0[0x10];
6176
6177	u8         reserved_1[0x10];
6178	u8         op_mod[0x10];
6179
6180	u8         reserved_2[0x8];
6181	u8         mkey_index[0x18];
6182
6183	u8         reserved_3[0x20];
6184};
6185
6186struct mlx5_ifc_destroy_flow_table_out_bits {
6187	u8         status[0x8];
6188	u8         reserved_0[0x18];
6189
6190	u8         syndrome[0x20];
6191
6192	u8         reserved_1[0x40];
6193};
6194
6195struct mlx5_ifc_destroy_flow_table_in_bits {
6196	u8         opcode[0x10];
6197	u8         reserved_0[0x10];
6198
6199	u8         reserved_1[0x10];
6200	u8         op_mod[0x10];
6201
6202	u8         other_vport[0x1];
6203	u8         reserved_2[0xf];
6204	u8         vport_number[0x10];
6205
6206	u8         reserved_3[0x20];
6207
6208	u8         table_type[0x8];
6209	u8         reserved_4[0x18];
6210
6211	u8         reserved_5[0x8];
6212	u8         table_id[0x18];
6213
6214	u8         reserved_6[0x140];
6215};
6216
6217struct mlx5_ifc_destroy_flow_group_out_bits {
6218	u8         status[0x8];
6219	u8         reserved_0[0x18];
6220
6221	u8         syndrome[0x20];
6222
6223	u8         reserved_1[0x40];
6224};
6225
6226struct mlx5_ifc_destroy_flow_group_in_bits {
6227	u8         opcode[0x10];
6228	u8         reserved_0[0x10];
6229
6230	u8         reserved_1[0x10];
6231	u8         op_mod[0x10];
6232
6233	u8         other_vport[0x1];
6234	u8         reserved_2[0xf];
6235	u8         vport_number[0x10];
6236
6237	u8         reserved_3[0x20];
6238
6239	u8         table_type[0x8];
6240	u8         reserved_4[0x18];
6241
6242	u8         reserved_5[0x8];
6243	u8         table_id[0x18];
6244
6245	u8         group_id[0x20];
6246
6247	u8         reserved_6[0x120];
6248};
6249
6250struct mlx5_ifc_destroy_eq_out_bits {
6251	u8         status[0x8];
6252	u8         reserved_0[0x18];
6253
6254	u8         syndrome[0x20];
6255
6256	u8         reserved_1[0x40];
6257};
6258
6259struct mlx5_ifc_destroy_eq_in_bits {
6260	u8         opcode[0x10];
6261	u8         reserved_0[0x10];
6262
6263	u8         reserved_1[0x10];
6264	u8         op_mod[0x10];
6265
6266	u8         reserved_2[0x18];
6267	u8         eq_number[0x8];
6268
6269	u8         reserved_3[0x20];
6270};
6271
6272struct mlx5_ifc_destroy_dct_out_bits {
6273	u8         status[0x8];
6274	u8         reserved_0[0x18];
6275
6276	u8         syndrome[0x20];
6277
6278	u8         reserved_1[0x40];
6279};
6280
6281struct mlx5_ifc_destroy_dct_in_bits {
6282	u8         opcode[0x10];
6283	u8         reserved_0[0x10];
6284
6285	u8         reserved_1[0x10];
6286	u8         op_mod[0x10];
6287
6288	u8         reserved_2[0x8];
6289	u8         dctn[0x18];
6290
6291	u8         reserved_3[0x20];
6292};
6293
6294struct mlx5_ifc_destroy_cq_out_bits {
6295	u8         status[0x8];
6296	u8         reserved_0[0x18];
6297
6298	u8         syndrome[0x20];
6299
6300	u8         reserved_1[0x40];
6301};
6302
6303struct mlx5_ifc_destroy_cq_in_bits {
6304	u8         opcode[0x10];
6305	u8         reserved_0[0x10];
6306
6307	u8         reserved_1[0x10];
6308	u8         op_mod[0x10];
6309
6310	u8         reserved_2[0x8];
6311	u8         cqn[0x18];
6312
6313	u8         reserved_3[0x20];
6314};
6315
6316struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6317	u8         status[0x8];
6318	u8         reserved_0[0x18];
6319
6320	u8         syndrome[0x20];
6321
6322	u8         reserved_1[0x40];
6323};
6324
6325struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6326	u8         opcode[0x10];
6327	u8         reserved_0[0x10];
6328
6329	u8         reserved_1[0x10];
6330	u8         op_mod[0x10];
6331
6332	u8         reserved_2[0x20];
6333
6334	u8         reserved_3[0x10];
6335	u8         vxlan_udp_port[0x10];
6336};
6337
6338struct mlx5_ifc_delete_l2_table_entry_out_bits {
6339	u8         status[0x8];
6340	u8         reserved_0[0x18];
6341
6342	u8         syndrome[0x20];
6343
6344	u8         reserved_1[0x40];
6345};
6346
6347struct mlx5_ifc_delete_l2_table_entry_in_bits {
6348	u8         opcode[0x10];
6349	u8         reserved_0[0x10];
6350
6351	u8         reserved_1[0x10];
6352	u8         op_mod[0x10];
6353
6354	u8         reserved_2[0x60];
6355
6356	u8         reserved_3[0x8];
6357	u8         table_index[0x18];
6358
6359	u8         reserved_4[0x140];
6360};
6361
6362struct mlx5_ifc_delete_fte_out_bits {
6363	u8         status[0x8];
6364	u8         reserved_0[0x18];
6365
6366	u8         syndrome[0x20];
6367
6368	u8         reserved_1[0x40];
6369};
6370
6371struct mlx5_ifc_delete_fte_in_bits {
6372	u8         opcode[0x10];
6373	u8         reserved_0[0x10];
6374
6375	u8         reserved_1[0x10];
6376	u8         op_mod[0x10];
6377
6378	u8         other_vport[0x1];
6379	u8         reserved_2[0xf];
6380	u8         vport_number[0x10];
6381
6382	u8         reserved_3[0x20];
6383
6384	u8         table_type[0x8];
6385	u8         reserved_4[0x18];
6386
6387	u8         reserved_5[0x8];
6388	u8         table_id[0x18];
6389
6390	u8         reserved_6[0x40];
6391
6392	u8         flow_index[0x20];
6393
6394	u8         reserved_7[0xe0];
6395};
6396
6397struct mlx5_ifc_dealloc_xrcd_out_bits {
6398	u8         status[0x8];
6399	u8         reserved_0[0x18];
6400
6401	u8         syndrome[0x20];
6402
6403	u8         reserved_1[0x40];
6404};
6405
6406struct mlx5_ifc_dealloc_xrcd_in_bits {
6407	u8         opcode[0x10];
6408	u8         reserved_0[0x10];
6409
6410	u8         reserved_1[0x10];
6411	u8         op_mod[0x10];
6412
6413	u8         reserved_2[0x8];
6414	u8         xrcd[0x18];
6415
6416	u8         reserved_3[0x20];
6417};
6418
6419struct mlx5_ifc_dealloc_uar_out_bits {
6420	u8         status[0x8];
6421	u8         reserved_0[0x18];
6422
6423	u8         syndrome[0x20];
6424
6425	u8         reserved_1[0x40];
6426};
6427
6428struct mlx5_ifc_dealloc_uar_in_bits {
6429	u8         opcode[0x10];
6430	u8         reserved_0[0x10];
6431
6432	u8         reserved_1[0x10];
6433	u8         op_mod[0x10];
6434
6435	u8         reserved_2[0x8];
6436	u8         uar[0x18];
6437
6438	u8         reserved_3[0x20];
6439};
6440
6441struct mlx5_ifc_dealloc_transport_domain_out_bits {
6442	u8         status[0x8];
6443	u8         reserved_0[0x18];
6444
6445	u8         syndrome[0x20];
6446
6447	u8         reserved_1[0x40];
6448};
6449
6450struct mlx5_ifc_dealloc_transport_domain_in_bits {
6451	u8         opcode[0x10];
6452	u8         reserved_0[0x10];
6453
6454	u8         reserved_1[0x10];
6455	u8         op_mod[0x10];
6456
6457	u8         reserved_2[0x8];
6458	u8         transport_domain[0x18];
6459
6460	u8         reserved_3[0x20];
6461};
6462
6463struct mlx5_ifc_dealloc_q_counter_out_bits {
6464	u8         status[0x8];
6465	u8         reserved_0[0x18];
6466
6467	u8         syndrome[0x20];
6468
6469	u8         reserved_1[0x40];
6470};
6471
6472struct mlx5_ifc_counter_id_bits {
6473	u8         reserved[0x10];
6474	u8         counter_id[0x10];
6475};
6476
6477struct mlx5_ifc_diagnostic_params_context_bits {
6478	u8         num_of_counters[0x10];
6479	u8         reserved_2[0x8];
6480	u8         log_num_of_samples[0x8];
6481
6482	u8         single[0x1];
6483	u8         repetitive[0x1];
6484	u8         sync[0x1];
6485	u8         clear[0x1];
6486	u8         on_demand[0x1];
6487	u8         enable[0x1];
6488	u8         reserved_3[0x12];
6489	u8         log_sample_period[0x8];
6490
6491	u8         reserved_4[0x80];
6492
6493	struct mlx5_ifc_counter_id_bits counter_id[0];
6494};
6495
6496struct mlx5_ifc_set_diagnostic_params_in_bits {
6497	u8         opcode[0x10];
6498	u8         reserved_0[0x10];
6499
6500	u8         reserved_1[0x10];
6501	u8         op_mod[0x10];
6502
6503	struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx;
6504};
6505
6506struct mlx5_ifc_set_diagnostic_params_out_bits {
6507	u8         status[0x8];
6508	u8         reserved_0[0x18];
6509
6510	u8         syndrome[0x20];
6511
6512	u8         reserved_1[0x40];
6513};
6514
6515struct mlx5_ifc_query_diagnostic_counters_in_bits {
6516	u8         opcode[0x10];
6517	u8         reserved_0[0x10];
6518
6519	u8         reserved_1[0x10];
6520	u8         op_mod[0x10];
6521
6522	u8         num_of_samples[0x10];
6523	u8         sample_index[0x10];
6524
6525	u8         reserved_2[0x20];
6526};
6527
6528struct mlx5_ifc_diagnostic_counter_bits {
6529	u8         counter_id[0x10];
6530	u8         sample_id[0x10];
6531
6532	u8         time_stamp_31_0[0x20];
6533
6534	u8         counter_value_h[0x20];
6535
6536	u8         counter_value_l[0x20];
6537};
6538
6539struct mlx5_ifc_query_diagnostic_counters_out_bits {
6540	u8         status[0x8];
6541	u8         reserved_0[0x18];
6542
6543	u8         syndrome[0x20];
6544
6545	u8         reserved_1[0x40];
6546
6547	struct mlx5_ifc_diagnostic_counter_bits diag_counter[0];
6548};
6549
6550struct mlx5_ifc_dealloc_q_counter_in_bits {
6551	u8         opcode[0x10];
6552	u8         reserved_0[0x10];
6553
6554	u8         reserved_1[0x10];
6555	u8         op_mod[0x10];
6556
6557	u8         reserved_2[0x18];
6558	u8         counter_set_id[0x8];
6559
6560	u8         reserved_3[0x20];
6561};
6562
6563struct mlx5_ifc_dealloc_pd_out_bits {
6564	u8         status[0x8];
6565	u8         reserved_0[0x18];
6566
6567	u8         syndrome[0x20];
6568
6569	u8         reserved_1[0x40];
6570};
6571
6572struct mlx5_ifc_dealloc_pd_in_bits {
6573	u8         opcode[0x10];
6574	u8         reserved_0[0x10];
6575
6576	u8         reserved_1[0x10];
6577	u8         op_mod[0x10];
6578
6579	u8         reserved_2[0x8];
6580	u8         pd[0x18];
6581
6582	u8         reserved_3[0x20];
6583};
6584
6585struct mlx5_ifc_dealloc_flow_counter_out_bits {
6586	u8         status[0x8];
6587	u8         reserved_0[0x18];
6588
6589	u8         syndrome[0x20];
6590
6591	u8         reserved_1[0x40];
6592};
6593
6594struct mlx5_ifc_dealloc_flow_counter_in_bits {
6595	u8         opcode[0x10];
6596	u8         reserved_0[0x10];
6597
6598	u8         reserved_1[0x10];
6599	u8         op_mod[0x10];
6600
6601	u8         reserved_2[0x10];
6602	u8         flow_counter_id[0x10];
6603
6604	u8         reserved_3[0x20];
6605};
6606
6607struct mlx5_ifc_deactivate_tracer_out_bits {
6608	u8         status[0x8];
6609	u8         reserved_0[0x18];
6610
6611	u8         syndrome[0x20];
6612
6613	u8         reserved_1[0x40];
6614};
6615
6616struct mlx5_ifc_deactivate_tracer_in_bits {
6617	u8         opcode[0x10];
6618	u8         reserved_0[0x10];
6619
6620	u8         reserved_1[0x10];
6621	u8         op_mod[0x10];
6622
6623	u8         mkey[0x20];
6624
6625	u8         reserved_2[0x20];
6626};
6627
6628struct mlx5_ifc_create_xrc_srq_out_bits {
6629	u8         status[0x8];
6630	u8         reserved_0[0x18];
6631
6632	u8         syndrome[0x20];
6633
6634	u8         reserved_1[0x8];
6635	u8         xrc_srqn[0x18];
6636
6637	u8         reserved_2[0x20];
6638};
6639
6640struct mlx5_ifc_create_xrc_srq_in_bits {
6641	u8         opcode[0x10];
6642	u8         reserved_0[0x10];
6643
6644	u8         reserved_1[0x10];
6645	u8         op_mod[0x10];
6646
6647	u8         reserved_2[0x40];
6648
6649	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6650
6651	u8         reserved_3[0x600];
6652
6653	u8         pas[0][0x40];
6654};
6655
6656struct mlx5_ifc_create_tis_out_bits {
6657	u8         status[0x8];
6658	u8         reserved_0[0x18];
6659
6660	u8         syndrome[0x20];
6661
6662	u8         reserved_1[0x8];
6663	u8         tisn[0x18];
6664
6665	u8         reserved_2[0x20];
6666};
6667
6668struct mlx5_ifc_create_tis_in_bits {
6669	u8         opcode[0x10];
6670	u8         reserved_0[0x10];
6671
6672	u8         reserved_1[0x10];
6673	u8         op_mod[0x10];
6674
6675	u8         reserved_2[0xc0];
6676
6677	struct mlx5_ifc_tisc_bits ctx;
6678};
6679
6680struct mlx5_ifc_create_tir_out_bits {
6681	u8         status[0x8];
6682	u8         reserved_0[0x18];
6683
6684	u8         syndrome[0x20];
6685
6686	u8         reserved_1[0x8];
6687	u8         tirn[0x18];
6688
6689	u8         reserved_2[0x20];
6690};
6691
6692struct mlx5_ifc_create_tir_in_bits {
6693	u8         opcode[0x10];
6694	u8         reserved_0[0x10];
6695
6696	u8         reserved_1[0x10];
6697	u8         op_mod[0x10];
6698
6699	u8         reserved_2[0xc0];
6700
6701	struct mlx5_ifc_tirc_bits tir_context;
6702};
6703
6704struct mlx5_ifc_create_srq_out_bits {
6705	u8         status[0x8];
6706	u8         reserved_0[0x18];
6707
6708	u8         syndrome[0x20];
6709
6710	u8         reserved_1[0x8];
6711	u8         srqn[0x18];
6712
6713	u8         reserved_2[0x20];
6714};
6715
6716struct mlx5_ifc_create_srq_in_bits {
6717	u8         opcode[0x10];
6718	u8         reserved_0[0x10];
6719
6720	u8         reserved_1[0x10];
6721	u8         op_mod[0x10];
6722
6723	u8         reserved_2[0x40];
6724
6725	struct mlx5_ifc_srqc_bits srq_context_entry;
6726
6727	u8         reserved_3[0x600];
6728
6729	u8         pas[0][0x40];
6730};
6731
6732struct mlx5_ifc_create_sq_out_bits {
6733	u8         status[0x8];
6734	u8         reserved_0[0x18];
6735
6736	u8         syndrome[0x20];
6737
6738	u8         reserved_1[0x8];
6739	u8         sqn[0x18];
6740
6741	u8         reserved_2[0x20];
6742};
6743
6744struct mlx5_ifc_create_sq_in_bits {
6745	u8         opcode[0x10];
6746	u8         reserved_0[0x10];
6747
6748	u8         reserved_1[0x10];
6749	u8         op_mod[0x10];
6750
6751	u8         reserved_2[0xc0];
6752
6753	struct mlx5_ifc_sqc_bits ctx;
6754};
6755
6756struct mlx5_ifc_create_scheduling_element_out_bits {
6757	u8         status[0x8];
6758	u8         reserved_at_8[0x18];
6759
6760	u8         syndrome[0x20];
6761
6762	u8         reserved_at_40[0x40];
6763
6764	u8         scheduling_element_id[0x20];
6765
6766	u8         reserved_at_a0[0x160];
6767};
6768
6769enum {
6770	MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
6771};
6772
6773struct mlx5_ifc_create_scheduling_element_in_bits {
6774	u8         opcode[0x10];
6775	u8         reserved_at_10[0x10];
6776
6777	u8         reserved_at_20[0x10];
6778	u8         op_mod[0x10];
6779
6780	u8         scheduling_hierarchy[0x8];
6781	u8         reserved_at_48[0x18];
6782
6783	u8         reserved_at_60[0xa0];
6784
6785	struct mlx5_ifc_scheduling_context_bits scheduling_context;
6786
6787	u8         reserved_at_300[0x100];
6788};
6789
6790struct mlx5_ifc_create_rqt_out_bits {
6791	u8         status[0x8];
6792	u8         reserved_0[0x18];
6793
6794	u8         syndrome[0x20];
6795
6796	u8         reserved_1[0x8];
6797	u8         rqtn[0x18];
6798
6799	u8         reserved_2[0x20];
6800};
6801
6802struct mlx5_ifc_create_rqt_in_bits {
6803	u8         opcode[0x10];
6804	u8         reserved_0[0x10];
6805
6806	u8         reserved_1[0x10];
6807	u8         op_mod[0x10];
6808
6809	u8         reserved_2[0xc0];
6810
6811	struct mlx5_ifc_rqtc_bits rqt_context;
6812};
6813
6814struct mlx5_ifc_create_rq_out_bits {
6815	u8         status[0x8];
6816	u8         reserved_0[0x18];
6817
6818	u8         syndrome[0x20];
6819
6820	u8         reserved_1[0x8];
6821	u8         rqn[0x18];
6822
6823	u8         reserved_2[0x20];
6824};
6825
6826struct mlx5_ifc_create_rq_in_bits {
6827	u8         opcode[0x10];
6828	u8         reserved_0[0x10];
6829
6830	u8         reserved_1[0x10];
6831	u8         op_mod[0x10];
6832
6833	u8         reserved_2[0xc0];
6834
6835	struct mlx5_ifc_rqc_bits ctx;
6836};
6837
6838struct mlx5_ifc_create_rmp_out_bits {
6839	u8         status[0x8];
6840	u8         reserved_0[0x18];
6841
6842	u8         syndrome[0x20];
6843
6844	u8         reserved_1[0x8];
6845	u8         rmpn[0x18];
6846
6847	u8         reserved_2[0x20];
6848};
6849
6850struct mlx5_ifc_create_rmp_in_bits {
6851	u8         opcode[0x10];
6852	u8         reserved_0[0x10];
6853
6854	u8         reserved_1[0x10];
6855	u8         op_mod[0x10];
6856
6857	u8         reserved_2[0xc0];
6858
6859	struct mlx5_ifc_rmpc_bits ctx;
6860};
6861
6862struct mlx5_ifc_create_qp_out_bits {
6863	u8         status[0x8];
6864	u8         reserved_0[0x18];
6865
6866	u8         syndrome[0x20];
6867
6868	u8         reserved_1[0x8];
6869	u8         qpn[0x18];
6870
6871	u8         reserved_2[0x20];
6872};
6873
6874struct mlx5_ifc_create_qp_in_bits {
6875	u8         opcode[0x10];
6876	u8         reserved_0[0x10];
6877
6878	u8         reserved_1[0x10];
6879	u8         op_mod[0x10];
6880
6881	u8         reserved_2[0x8];
6882	u8         input_qpn[0x18];
6883
6884	u8         reserved_3[0x20];
6885
6886	u8         opt_param_mask[0x20];
6887
6888	u8         reserved_4[0x20];
6889
6890	struct mlx5_ifc_qpc_bits qpc;
6891
6892	u8         reserved_5[0x80];
6893
6894	u8         pas[0][0x40];
6895};
6896
6897struct mlx5_ifc_create_qos_para_vport_out_bits {
6898	u8         status[0x8];
6899	u8         reserved_at_8[0x18];
6900
6901	u8         syndrome[0x20];
6902
6903	u8         reserved_at_40[0x20];
6904
6905	u8         reserved_at_60[0x10];
6906	u8         qos_para_vport_number[0x10];
6907
6908	u8         reserved_at_80[0x180];
6909};
6910
6911struct mlx5_ifc_create_qos_para_vport_in_bits {
6912	u8         opcode[0x10];
6913	u8         reserved_at_10[0x10];
6914
6915	u8         reserved_at_20[0x10];
6916	u8         op_mod[0x10];
6917
6918	u8         reserved_at_40[0x1c0];
6919};
6920
6921struct mlx5_ifc_create_psv_out_bits {
6922	u8         status[0x8];
6923	u8         reserved_0[0x18];
6924
6925	u8         syndrome[0x20];
6926
6927	u8         reserved_1[0x40];
6928
6929	u8         reserved_2[0x8];
6930	u8         psv0_index[0x18];
6931
6932	u8         reserved_3[0x8];
6933	u8         psv1_index[0x18];
6934
6935	u8         reserved_4[0x8];
6936	u8         psv2_index[0x18];
6937
6938	u8         reserved_5[0x8];
6939	u8         psv3_index[0x18];
6940};
6941
6942struct mlx5_ifc_create_psv_in_bits {
6943	u8         opcode[0x10];
6944	u8         reserved_0[0x10];
6945
6946	u8         reserved_1[0x10];
6947	u8         op_mod[0x10];
6948
6949	u8         num_psv[0x4];
6950	u8         reserved_2[0x4];
6951	u8         pd[0x18];
6952
6953	u8         reserved_3[0x20];
6954};
6955
6956struct mlx5_ifc_create_mkey_out_bits {
6957	u8         status[0x8];
6958	u8         reserved_0[0x18];
6959
6960	u8         syndrome[0x20];
6961
6962	u8         reserved_1[0x8];
6963	u8         mkey_index[0x18];
6964
6965	u8         reserved_2[0x20];
6966};
6967
6968struct mlx5_ifc_create_mkey_in_bits {
6969	u8         opcode[0x10];
6970	u8         reserved_0[0x10];
6971
6972	u8         reserved_1[0x10];
6973	u8         op_mod[0x10];
6974
6975	u8         reserved_2[0x20];
6976
6977	u8         pg_access[0x1];
6978	u8         reserved_3[0x1f];
6979
6980	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6981
6982	u8         reserved_4[0x80];
6983
6984	u8         translations_octword_actual_size[0x20];
6985
6986	u8         reserved_5[0x560];
6987
6988	u8         klm_pas_mtt[0][0x20];
6989};
6990
6991struct mlx5_ifc_create_flow_table_out_bits {
6992	u8         status[0x8];
6993	u8         reserved_0[0x18];
6994
6995	u8         syndrome[0x20];
6996
6997	u8         reserved_1[0x8];
6998	u8         table_id[0x18];
6999
7000	u8         reserved_2[0x20];
7001};
7002
7003struct mlx5_ifc_create_flow_table_in_bits {
7004	u8         opcode[0x10];
7005	u8         reserved_at_10[0x10];
7006
7007	u8         reserved_at_20[0x10];
7008	u8         op_mod[0x10];
7009
7010	u8         other_vport[0x1];
7011	u8         reserved_at_41[0xf];
7012	u8         vport_number[0x10];
7013
7014	u8         reserved_at_60[0x20];
7015
7016	u8         table_type[0x8];
7017	u8         reserved_at_88[0x18];
7018
7019	u8         reserved_at_a0[0x20];
7020
7021	struct mlx5_ifc_flow_table_context_bits flow_table_context;
7022};
7023
7024struct mlx5_ifc_create_flow_group_out_bits {
7025	u8         status[0x8];
7026	u8         reserved_0[0x18];
7027
7028	u8         syndrome[0x20];
7029
7030	u8         reserved_1[0x8];
7031	u8         group_id[0x18];
7032
7033	u8         reserved_2[0x20];
7034};
7035
7036enum {
7037	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
7038	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
7039	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
7040};
7041
7042struct mlx5_ifc_create_flow_group_in_bits {
7043	u8         opcode[0x10];
7044	u8         reserved_0[0x10];
7045
7046	u8         reserved_1[0x10];
7047	u8         op_mod[0x10];
7048
7049	u8         other_vport[0x1];
7050	u8         reserved_2[0xf];
7051	u8         vport_number[0x10];
7052
7053	u8         reserved_3[0x20];
7054
7055	u8         table_type[0x8];
7056	u8         reserved_4[0x18];
7057
7058	u8         reserved_5[0x8];
7059	u8         table_id[0x18];
7060
7061	u8         reserved_6[0x20];
7062
7063	u8         start_flow_index[0x20];
7064
7065	u8         reserved_7[0x20];
7066
7067	u8         end_flow_index[0x20];
7068
7069	u8         reserved_8[0xa0];
7070
7071	u8         reserved_9[0x18];
7072	u8         match_criteria_enable[0x8];
7073
7074	struct mlx5_ifc_fte_match_param_bits match_criteria;
7075
7076	u8         reserved_10[0xe00];
7077};
7078
7079struct mlx5_ifc_create_eq_out_bits {
7080	u8         status[0x8];
7081	u8         reserved_0[0x18];
7082
7083	u8         syndrome[0x20];
7084
7085	u8         reserved_1[0x18];
7086	u8         eq_number[0x8];
7087
7088	u8         reserved_2[0x20];
7089};
7090
7091struct mlx5_ifc_create_eq_in_bits {
7092	u8         opcode[0x10];
7093	u8         reserved_0[0x10];
7094
7095	u8         reserved_1[0x10];
7096	u8         op_mod[0x10];
7097
7098	u8         reserved_2[0x40];
7099
7100	struct mlx5_ifc_eqc_bits eq_context_entry;
7101
7102	u8         reserved_3[0x40];
7103
7104	u8         event_bitmask[0x40];
7105
7106	u8         reserved_4[0x580];
7107
7108	u8         pas[0][0x40];
7109};
7110
7111struct mlx5_ifc_create_dct_out_bits {
7112	u8         status[0x8];
7113	u8         reserved_0[0x18];
7114
7115	u8         syndrome[0x20];
7116
7117	u8         reserved_1[0x8];
7118	u8         dctn[0x18];
7119
7120	u8         reserved_2[0x20];
7121};
7122
7123struct mlx5_ifc_create_dct_in_bits {
7124	u8         opcode[0x10];
7125	u8         reserved_0[0x10];
7126
7127	u8         reserved_1[0x10];
7128	u8         op_mod[0x10];
7129
7130	u8         reserved_2[0x40];
7131
7132	struct mlx5_ifc_dctc_bits dct_context_entry;
7133
7134	u8         reserved_3[0x180];
7135};
7136
7137struct mlx5_ifc_create_cq_out_bits {
7138	u8         status[0x8];
7139	u8         reserved_0[0x18];
7140
7141	u8         syndrome[0x20];
7142
7143	u8         reserved_1[0x8];
7144	u8         cqn[0x18];
7145
7146	u8         reserved_2[0x20];
7147};
7148
7149struct mlx5_ifc_create_cq_in_bits {
7150	u8         opcode[0x10];
7151	u8         reserved_0[0x10];
7152
7153	u8         reserved_1[0x10];
7154	u8         op_mod[0x10];
7155
7156	u8         reserved_2[0x40];
7157
7158	struct mlx5_ifc_cqc_bits cq_context;
7159
7160	u8         reserved_3[0x600];
7161
7162	u8         pas[0][0x40];
7163};
7164
7165struct mlx5_ifc_config_int_moderation_out_bits {
7166	u8         status[0x8];
7167	u8         reserved_0[0x18];
7168
7169	u8         syndrome[0x20];
7170
7171	u8         reserved_1[0x4];
7172	u8         min_delay[0xc];
7173	u8         int_vector[0x10];
7174
7175	u8         reserved_2[0x20];
7176};
7177
7178enum {
7179	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7180	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7181};
7182
7183struct mlx5_ifc_config_int_moderation_in_bits {
7184	u8         opcode[0x10];
7185	u8         reserved_0[0x10];
7186
7187	u8         reserved_1[0x10];
7188	u8         op_mod[0x10];
7189
7190	u8         reserved_2[0x4];
7191	u8         min_delay[0xc];
7192	u8         int_vector[0x10];
7193
7194	u8         reserved_3[0x20];
7195};
7196
7197struct mlx5_ifc_attach_to_mcg_out_bits {
7198	u8         status[0x8];
7199	u8         reserved_0[0x18];
7200
7201	u8         syndrome[0x20];
7202
7203	u8         reserved_1[0x40];
7204};
7205
7206struct mlx5_ifc_attach_to_mcg_in_bits {
7207	u8         opcode[0x10];
7208	u8         reserved_0[0x10];
7209
7210	u8         reserved_1[0x10];
7211	u8         op_mod[0x10];
7212
7213	u8         reserved_2[0x8];
7214	u8         qpn[0x18];
7215
7216	u8         reserved_3[0x20];
7217
7218	u8         multicast_gid[16][0x8];
7219};
7220
7221struct mlx5_ifc_arm_xrc_srq_out_bits {
7222	u8         status[0x8];
7223	u8         reserved_0[0x18];
7224
7225	u8         syndrome[0x20];
7226
7227	u8         reserved_1[0x40];
7228};
7229
7230enum {
7231	MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7232};
7233
7234struct mlx5_ifc_arm_xrc_srq_in_bits {
7235	u8         opcode[0x10];
7236	u8         reserved_0[0x10];
7237
7238	u8         reserved_1[0x10];
7239	u8         op_mod[0x10];
7240
7241	u8         reserved_2[0x8];
7242	u8         xrc_srqn[0x18];
7243
7244	u8         reserved_3[0x10];
7245	u8         lwm[0x10];
7246};
7247
7248struct mlx5_ifc_arm_rq_out_bits {
7249	u8         status[0x8];
7250	u8         reserved_0[0x18];
7251
7252	u8         syndrome[0x20];
7253
7254	u8         reserved_1[0x40];
7255};
7256
7257enum {
7258	MLX5_ARM_RQ_IN_OP_MOD_SRQ  = 0x1,
7259};
7260
7261struct mlx5_ifc_arm_rq_in_bits {
7262	u8         opcode[0x10];
7263	u8         reserved_0[0x10];
7264
7265	u8         reserved_1[0x10];
7266	u8         op_mod[0x10];
7267
7268	u8         reserved_2[0x8];
7269	u8         srq_number[0x18];
7270
7271	u8         reserved_3[0x10];
7272	u8         lwm[0x10];
7273};
7274
7275struct mlx5_ifc_arm_dct_out_bits {
7276	u8         status[0x8];
7277	u8         reserved_0[0x18];
7278
7279	u8         syndrome[0x20];
7280
7281	u8         reserved_1[0x40];
7282};
7283
7284struct mlx5_ifc_arm_dct_in_bits {
7285	u8         opcode[0x10];
7286	u8         reserved_0[0x10];
7287
7288	u8         reserved_1[0x10];
7289	u8         op_mod[0x10];
7290
7291	u8         reserved_2[0x8];
7292	u8         dctn[0x18];
7293
7294	u8         reserved_3[0x20];
7295};
7296
7297struct mlx5_ifc_alloc_xrcd_out_bits {
7298	u8         status[0x8];
7299	u8         reserved_0[0x18];
7300
7301	u8         syndrome[0x20];
7302
7303	u8         reserved_1[0x8];
7304	u8         xrcd[0x18];
7305
7306	u8         reserved_2[0x20];
7307};
7308
7309struct mlx5_ifc_alloc_xrcd_in_bits {
7310	u8         opcode[0x10];
7311	u8         reserved_0[0x10];
7312
7313	u8         reserved_1[0x10];
7314	u8         op_mod[0x10];
7315
7316	u8         reserved_2[0x40];
7317};
7318
7319struct mlx5_ifc_alloc_uar_out_bits {
7320	u8         status[0x8];
7321	u8         reserved_0[0x18];
7322
7323	u8         syndrome[0x20];
7324
7325	u8         reserved_1[0x8];
7326	u8         uar[0x18];
7327
7328	u8         reserved_2[0x20];
7329};
7330
7331struct mlx5_ifc_alloc_uar_in_bits {
7332	u8         opcode[0x10];
7333	u8         reserved_0[0x10];
7334
7335	u8         reserved_1[0x10];
7336	u8         op_mod[0x10];
7337
7338	u8         reserved_2[0x40];
7339};
7340
7341struct mlx5_ifc_alloc_transport_domain_out_bits {
7342	u8         status[0x8];
7343	u8         reserved_0[0x18];
7344
7345	u8         syndrome[0x20];
7346
7347	u8         reserved_1[0x8];
7348	u8         transport_domain[0x18];
7349
7350	u8         reserved_2[0x20];
7351};
7352
7353struct mlx5_ifc_alloc_transport_domain_in_bits {
7354	u8         opcode[0x10];
7355	u8         reserved_0[0x10];
7356
7357	u8         reserved_1[0x10];
7358	u8         op_mod[0x10];
7359
7360	u8         reserved_2[0x40];
7361};
7362
7363struct mlx5_ifc_alloc_q_counter_out_bits {
7364	u8         status[0x8];
7365	u8         reserved_0[0x18];
7366
7367	u8         syndrome[0x20];
7368
7369	u8         reserved_1[0x18];
7370	u8         counter_set_id[0x8];
7371
7372	u8         reserved_2[0x20];
7373};
7374
7375struct mlx5_ifc_alloc_q_counter_in_bits {
7376	u8         opcode[0x10];
7377	u8         reserved_0[0x10];
7378
7379	u8         reserved_1[0x10];
7380	u8         op_mod[0x10];
7381
7382	u8         reserved_2[0x40];
7383};
7384
7385struct mlx5_ifc_alloc_pd_out_bits {
7386	u8         status[0x8];
7387	u8         reserved_0[0x18];
7388
7389	u8         syndrome[0x20];
7390
7391	u8         reserved_1[0x8];
7392	u8         pd[0x18];
7393
7394	u8         reserved_2[0x20];
7395};
7396
7397struct mlx5_ifc_alloc_pd_in_bits {
7398	u8         opcode[0x10];
7399	u8         reserved_0[0x10];
7400
7401	u8         reserved_1[0x10];
7402	u8         op_mod[0x10];
7403
7404	u8         reserved_2[0x40];
7405};
7406
7407struct mlx5_ifc_alloc_flow_counter_out_bits {
7408	u8         status[0x8];
7409	u8         reserved_0[0x18];
7410
7411	u8         syndrome[0x20];
7412
7413	u8         reserved_1[0x10];
7414	u8         flow_counter_id[0x10];
7415
7416	u8         reserved_2[0x20];
7417};
7418
7419struct mlx5_ifc_alloc_flow_counter_in_bits {
7420	u8         opcode[0x10];
7421	u8         reserved_0[0x10];
7422
7423	u8         reserved_1[0x10];
7424	u8         op_mod[0x10];
7425
7426	u8         reserved_2[0x40];
7427};
7428
7429struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7430	u8         status[0x8];
7431	u8         reserved_0[0x18];
7432
7433	u8         syndrome[0x20];
7434
7435	u8         reserved_1[0x40];
7436};
7437
7438struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7439	u8         opcode[0x10];
7440	u8         reserved_0[0x10];
7441
7442	u8         reserved_1[0x10];
7443	u8         op_mod[0x10];
7444
7445	u8         reserved_2[0x20];
7446
7447	u8         reserved_3[0x10];
7448	u8         vxlan_udp_port[0x10];
7449};
7450
7451struct mlx5_ifc_activate_tracer_out_bits {
7452	u8         status[0x8];
7453	u8         reserved_0[0x18];
7454
7455	u8         syndrome[0x20];
7456
7457	u8         reserved_1[0x40];
7458};
7459
7460struct mlx5_ifc_activate_tracer_in_bits {
7461	u8         opcode[0x10];
7462	u8         reserved_0[0x10];
7463
7464	u8         reserved_1[0x10];
7465	u8         op_mod[0x10];
7466
7467	u8         mkey[0x20];
7468
7469	u8         reserved_2[0x20];
7470};
7471
7472struct mlx5_ifc_set_rate_limit_out_bits {
7473	u8         status[0x8];
7474	u8         reserved_at_8[0x18];
7475
7476	u8         syndrome[0x20];
7477
7478	u8         reserved_at_40[0x40];
7479};
7480
7481struct mlx5_ifc_set_rate_limit_in_bits {
7482	u8         opcode[0x10];
7483	u8         reserved_at_10[0x10];
7484
7485	u8         reserved_at_20[0x10];
7486	u8         op_mod[0x10];
7487
7488	u8         reserved_at_40[0x10];
7489	u8         rate_limit_index[0x10];
7490
7491	u8         reserved_at_60[0x20];
7492
7493	u8         rate_limit[0x20];
7494	u8         burst_upper_bound[0x20];
7495};
7496
7497struct mlx5_ifc_access_register_out_bits {
7498	u8         status[0x8];
7499	u8         reserved_0[0x18];
7500
7501	u8         syndrome[0x20];
7502
7503	u8         reserved_1[0x40];
7504
7505	u8         register_data[0][0x20];
7506};
7507
7508enum {
7509	MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7510	MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7511};
7512
7513struct mlx5_ifc_access_register_in_bits {
7514	u8         opcode[0x10];
7515	u8         reserved_0[0x10];
7516
7517	u8         reserved_1[0x10];
7518	u8         op_mod[0x10];
7519
7520	u8         reserved_2[0x10];
7521	u8         register_id[0x10];
7522
7523	u8         argument[0x20];
7524
7525	u8         register_data[0][0x20];
7526};
7527
7528struct mlx5_ifc_sltp_reg_bits {
7529	u8         status[0x4];
7530	u8         version[0x4];
7531	u8         local_port[0x8];
7532	u8         pnat[0x2];
7533	u8         reserved_0[0x2];
7534	u8         lane[0x4];
7535	u8         reserved_1[0x8];
7536
7537	u8         reserved_2[0x20];
7538
7539	u8         reserved_3[0x7];
7540	u8         polarity[0x1];
7541	u8         ob_tap0[0x8];
7542	u8         ob_tap1[0x8];
7543	u8         ob_tap2[0x8];
7544
7545	u8         reserved_4[0xc];
7546	u8         ob_preemp_mode[0x4];
7547	u8         ob_reg[0x8];
7548	u8         ob_bias[0x8];
7549
7550	u8         reserved_5[0x20];
7551};
7552
7553struct mlx5_ifc_slrp_reg_bits {
7554	u8         status[0x4];
7555	u8         version[0x4];
7556	u8         local_port[0x8];
7557	u8         pnat[0x2];
7558	u8         reserved_0[0x2];
7559	u8         lane[0x4];
7560	u8         reserved_1[0x8];
7561
7562	u8         ib_sel[0x2];
7563	u8         reserved_2[0x11];
7564	u8         dp_sel[0x1];
7565	u8         dp90sel[0x4];
7566	u8         mix90phase[0x8];
7567
7568	u8         ffe_tap0[0x8];
7569	u8         ffe_tap1[0x8];
7570	u8         ffe_tap2[0x8];
7571	u8         ffe_tap3[0x8];
7572
7573	u8         ffe_tap4[0x8];
7574	u8         ffe_tap5[0x8];
7575	u8         ffe_tap6[0x8];
7576	u8         ffe_tap7[0x8];
7577
7578	u8         ffe_tap8[0x8];
7579	u8         mixerbias_tap_amp[0x8];
7580	u8         reserved_3[0x7];
7581	u8         ffe_tap_en[0x9];
7582
7583	u8         ffe_tap_offset0[0x8];
7584	u8         ffe_tap_offset1[0x8];
7585	u8         slicer_offset0[0x10];
7586
7587	u8         mixer_offset0[0x10];
7588	u8         mixer_offset1[0x10];
7589
7590	u8         mixerbgn_inp[0x8];
7591	u8         mixerbgn_inn[0x8];
7592	u8         mixerbgn_refp[0x8];
7593	u8         mixerbgn_refn[0x8];
7594
7595	u8         sel_slicer_lctrl_h[0x1];
7596	u8         sel_slicer_lctrl_l[0x1];
7597	u8         reserved_4[0x1];
7598	u8         ref_mixer_vreg[0x5];
7599	u8         slicer_gctrl[0x8];
7600	u8         lctrl_input[0x8];
7601	u8         mixer_offset_cm1[0x8];
7602
7603	u8         common_mode[0x6];
7604	u8         reserved_5[0x1];
7605	u8         mixer_offset_cm0[0x9];
7606	u8         reserved_6[0x7];
7607	u8         slicer_offset_cm[0x9];
7608};
7609
7610struct mlx5_ifc_slrg_reg_bits {
7611	u8         status[0x4];
7612	u8         version[0x4];
7613	u8         local_port[0x8];
7614	u8         pnat[0x2];
7615	u8         reserved_0[0x2];
7616	u8         lane[0x4];
7617	u8         reserved_1[0x8];
7618
7619	u8         time_to_link_up[0x10];
7620	u8         reserved_2[0xc];
7621	u8         grade_lane_speed[0x4];
7622
7623	u8         grade_version[0x8];
7624	u8         grade[0x18];
7625
7626	u8         reserved_3[0x4];
7627	u8         height_grade_type[0x4];
7628	u8         height_grade[0x18];
7629
7630	u8         height_dz[0x10];
7631	u8         height_dv[0x10];
7632
7633	u8         reserved_4[0x10];
7634	u8         height_sigma[0x10];
7635
7636	u8         reserved_5[0x20];
7637
7638	u8         reserved_6[0x4];
7639	u8         phase_grade_type[0x4];
7640	u8         phase_grade[0x18];
7641
7642	u8         reserved_7[0x8];
7643	u8         phase_eo_pos[0x8];
7644	u8         reserved_8[0x8];
7645	u8         phase_eo_neg[0x8];
7646
7647	u8         ffe_set_tested[0x10];
7648	u8         test_errors_per_lane[0x10];
7649};
7650
7651struct mlx5_ifc_pvlc_reg_bits {
7652	u8         reserved_0[0x8];
7653	u8         local_port[0x8];
7654	u8         reserved_1[0x10];
7655
7656	u8         reserved_2[0x1c];
7657	u8         vl_hw_cap[0x4];
7658
7659	u8         reserved_3[0x1c];
7660	u8         vl_admin[0x4];
7661
7662	u8         reserved_4[0x1c];
7663	u8         vl_operational[0x4];
7664};
7665
7666struct mlx5_ifc_pude_reg_bits {
7667	u8         swid[0x8];
7668	u8         local_port[0x8];
7669	u8         reserved_0[0x4];
7670	u8         admin_status[0x4];
7671	u8         reserved_1[0x4];
7672	u8         oper_status[0x4];
7673
7674	u8         reserved_2[0x60];
7675};
7676
7677enum {
7678	MLX5_PTYS_REG_PROTO_MASK_INFINIBAND  = 0x1,
7679	MLX5_PTYS_REG_PROTO_MASK_ETHERNET    = 0x4,
7680};
7681
7682struct mlx5_ifc_ptys_reg_bits {
7683	u8         reserved_0[0x1];
7684	u8         an_disable_admin[0x1];
7685	u8         an_disable_cap[0x1];
7686	u8         reserved_1[0x4];
7687	u8         force_tx_aba_param[0x1];
7688	u8         local_port[0x8];
7689	u8         reserved_2[0xd];
7690	u8         proto_mask[0x3];
7691
7692	u8         an_status[0x4];
7693	u8         reserved_3[0xc];
7694	u8         data_rate_oper[0x10];
7695
7696	u8         fc_proto_capability[0x20];
7697
7698	u8         eth_proto_capability[0x20];
7699
7700	u8         ib_link_width_capability[0x10];
7701	u8         ib_proto_capability[0x10];
7702
7703	u8         fc_proto_admin[0x20];
7704
7705	u8         eth_proto_admin[0x20];
7706
7707	u8         ib_link_width_admin[0x10];
7708	u8         ib_proto_admin[0x10];
7709
7710	u8         fc_proto_oper[0x20];
7711
7712	u8         eth_proto_oper[0x20];
7713
7714	u8         ib_link_width_oper[0x10];
7715	u8         ib_proto_oper[0x10];
7716
7717	u8         reserved_4[0x20];
7718
7719	u8         eth_proto_lp_advertise[0x20];
7720
7721	u8         reserved_5[0x60];
7722};
7723
7724struct mlx5_ifc_ptas_reg_bits {
7725	u8         reserved_0[0x20];
7726
7727	u8         algorithm_options[0x10];
7728	u8         reserved_1[0x4];
7729	u8         repetitions_mode[0x4];
7730	u8         num_of_repetitions[0x8];
7731
7732	u8         grade_version[0x8];
7733	u8         height_grade_type[0x4];
7734	u8         phase_grade_type[0x4];
7735	u8         height_grade_weight[0x8];
7736	u8         phase_grade_weight[0x8];
7737
7738	u8         gisim_measure_bits[0x10];
7739	u8         adaptive_tap_measure_bits[0x10];
7740
7741	u8         ber_bath_high_error_threshold[0x10];
7742	u8         ber_bath_mid_error_threshold[0x10];
7743
7744	u8         ber_bath_low_error_threshold[0x10];
7745	u8         one_ratio_high_threshold[0x10];
7746
7747	u8         one_ratio_high_mid_threshold[0x10];
7748	u8         one_ratio_low_mid_threshold[0x10];
7749
7750	u8         one_ratio_low_threshold[0x10];
7751	u8         ndeo_error_threshold[0x10];
7752
7753	u8         mixer_offset_step_size[0x10];
7754	u8         reserved_2[0x8];
7755	u8         mix90_phase_for_voltage_bath[0x8];
7756
7757	u8         mixer_offset_start[0x10];
7758	u8         mixer_offset_end[0x10];
7759
7760	u8         reserved_3[0x15];
7761	u8         ber_test_time[0xb];
7762};
7763
7764struct mlx5_ifc_pspa_reg_bits {
7765	u8         swid[0x8];
7766	u8         local_port[0x8];
7767	u8         sub_port[0x8];
7768	u8         reserved_0[0x8];
7769
7770	u8         reserved_1[0x20];
7771};
7772
7773struct mlx5_ifc_ppsc_reg_bits {
7774	u8         reserved_0[0x8];
7775	u8         local_port[0x8];
7776	u8         reserved_1[0x10];
7777
7778	u8         reserved_2[0x60];
7779
7780	u8         reserved_3[0x1c];
7781	u8         wrps_admin[0x4];
7782
7783	u8         reserved_4[0x1c];
7784	u8         wrps_status[0x4];
7785
7786	u8         up_th_vld[0x1];
7787	u8         down_th_vld[0x1];
7788	u8         reserved_5[0x6];
7789	u8         up_threshold[0x8];
7790	u8         reserved_6[0x8];
7791	u8         down_threshold[0x8];
7792
7793	u8         reserved_7[0x20];
7794
7795	u8         reserved_8[0x1c];
7796	u8         srps_admin[0x4];
7797
7798	u8         reserved_9[0x60];
7799};
7800
7801struct mlx5_ifc_pplr_reg_bits {
7802	u8         reserved_0[0x8];
7803	u8         local_port[0x8];
7804	u8         reserved_1[0x10];
7805
7806	u8         reserved_2[0x8];
7807	u8         lb_cap[0x8];
7808	u8         reserved_3[0x8];
7809	u8         lb_en[0x8];
7810};
7811
7812struct mlx5_ifc_pplm_reg_bits {
7813	u8         reserved_0[0x8];
7814	u8         local_port[0x8];
7815	u8         reserved_1[0x10];
7816
7817	u8         reserved_2[0x20];
7818
7819	u8         port_profile_mode[0x8];
7820	u8         static_port_profile[0x8];
7821	u8         active_port_profile[0x8];
7822	u8         reserved_3[0x8];
7823
7824	u8         retransmission_active[0x8];
7825	u8         fec_mode_active[0x18];
7826
7827	u8         reserved_4[0x10];
7828	u8         v_100g_fec_override_cap[0x4];
7829	u8         v_50g_fec_override_cap[0x4];
7830	u8         v_25g_fec_override_cap[0x4];
7831	u8         v_10g_40g_fec_override_cap[0x4];
7832
7833	u8         reserved_5[0x10];
7834	u8         v_100g_fec_override_admin[0x4];
7835	u8         v_50g_fec_override_admin[0x4];
7836	u8         v_25g_fec_override_admin[0x4];
7837	u8         v_10g_40g_fec_override_admin[0x4];
7838};
7839
7840struct mlx5_ifc_ppll_reg_bits {
7841	u8         num_pll_groups[0x8];
7842	u8         pll_group[0x8];
7843	u8         reserved_0[0x4];
7844	u8         num_plls[0x4];
7845	u8         reserved_1[0x8];
7846
7847	u8         reserved_2[0x1f];
7848	u8         ae[0x1];
7849
7850	u8         pll_status[4][0x40];
7851};
7852
7853struct mlx5_ifc_ppad_reg_bits {
7854	u8         reserved_0[0x3];
7855	u8         single_mac[0x1];
7856	u8         reserved_1[0x4];
7857	u8         local_port[0x8];
7858	u8         mac_47_32[0x10];
7859
7860	u8         mac_31_0[0x20];
7861
7862	u8         reserved_2[0x40];
7863};
7864
7865struct mlx5_ifc_pmtu_reg_bits {
7866	u8         reserved_0[0x8];
7867	u8         local_port[0x8];
7868	u8         reserved_1[0x10];
7869
7870	u8         max_mtu[0x10];
7871	u8         reserved_2[0x10];
7872
7873	u8         admin_mtu[0x10];
7874	u8         reserved_3[0x10];
7875
7876	u8         oper_mtu[0x10];
7877	u8         reserved_4[0x10];
7878};
7879
7880struct mlx5_ifc_pmpr_reg_bits {
7881	u8         reserved_0[0x8];
7882	u8         module[0x8];
7883	u8         reserved_1[0x10];
7884
7885	u8         reserved_2[0x18];
7886	u8         attenuation_5g[0x8];
7887
7888	u8         reserved_3[0x18];
7889	u8         attenuation_7g[0x8];
7890
7891	u8         reserved_4[0x18];
7892	u8         attenuation_12g[0x8];
7893};
7894
7895struct mlx5_ifc_pmpe_reg_bits {
7896	u8         reserved_0[0x8];
7897	u8         module[0x8];
7898	u8         reserved_1[0xc];
7899	u8         module_status[0x4];
7900
7901	u8         reserved_2[0x14];
7902	u8         error_type[0x4];
7903	u8         reserved_3[0x8];
7904
7905	u8         reserved_4[0x40];
7906};
7907
7908struct mlx5_ifc_pmpc_reg_bits {
7909	u8         module_state_updated[32][0x8];
7910};
7911
7912struct mlx5_ifc_pmlpn_reg_bits {
7913	u8         reserved_0[0x4];
7914	u8         mlpn_status[0x4];
7915	u8         local_port[0x8];
7916	u8         reserved_1[0x10];
7917
7918	u8         e[0x1];
7919	u8         reserved_2[0x1f];
7920};
7921
7922struct mlx5_ifc_pmlp_reg_bits {
7923	u8         rxtx[0x1];
7924	u8         reserved_0[0x7];
7925	u8         local_port[0x8];
7926	u8         reserved_1[0x8];
7927	u8         width[0x8];
7928
7929	u8         lane0_module_mapping[0x20];
7930
7931	u8         lane1_module_mapping[0x20];
7932
7933	u8         lane2_module_mapping[0x20];
7934
7935	u8         lane3_module_mapping[0x20];
7936
7937	u8         reserved_2[0x160];
7938};
7939
7940struct mlx5_ifc_pmaos_reg_bits {
7941	u8         reserved_0[0x8];
7942	u8         module[0x8];
7943	u8         reserved_1[0x4];
7944	u8         admin_status[0x4];
7945	u8         reserved_2[0x4];
7946	u8         oper_status[0x4];
7947
7948	u8         ase[0x1];
7949	u8         ee[0x1];
7950	u8         reserved_3[0x12];
7951	u8         error_type[0x4];
7952	u8         reserved_4[0x6];
7953	u8         e[0x2];
7954
7955	u8         reserved_5[0x40];
7956};
7957
7958struct mlx5_ifc_plpc_reg_bits {
7959	u8         reserved_0[0x4];
7960	u8         profile_id[0xc];
7961	u8         reserved_1[0x4];
7962	u8         proto_mask[0x4];
7963	u8         reserved_2[0x8];
7964
7965	u8         reserved_3[0x10];
7966	u8         lane_speed[0x10];
7967
7968	u8         reserved_4[0x17];
7969	u8         lpbf[0x1];
7970	u8         fec_mode_policy[0x8];
7971
7972	u8         retransmission_capability[0x8];
7973	u8         fec_mode_capability[0x18];
7974
7975	u8         retransmission_support_admin[0x8];
7976	u8         fec_mode_support_admin[0x18];
7977
7978	u8         retransmission_request_admin[0x8];
7979	u8         fec_mode_request_admin[0x18];
7980
7981	u8         reserved_5[0x80];
7982};
7983
7984struct mlx5_ifc_pll_status_data_bits {
7985	u8         reserved_0[0x1];
7986	u8         lock_cal[0x1];
7987	u8         lock_status[0x2];
7988	u8         reserved_1[0x2];
7989	u8         algo_f_ctrl[0xa];
7990	u8         analog_algo_num_var[0x6];
7991	u8         f_ctrl_measure[0xa];
7992
7993	u8         reserved_2[0x2];
7994	u8         analog_var[0x6];
7995	u8         reserved_3[0x2];
7996	u8         high_var[0x6];
7997	u8         reserved_4[0x2];
7998	u8         low_var[0x6];
7999	u8         reserved_5[0x2];
8000	u8         mid_val[0x6];
8001};
8002
8003struct mlx5_ifc_plib_reg_bits {
8004	u8         reserved_0[0x8];
8005	u8         local_port[0x8];
8006	u8         reserved_1[0x8];
8007	u8         ib_port[0x8];
8008
8009	u8         reserved_2[0x60];
8010};
8011
8012struct mlx5_ifc_plbf_reg_bits {
8013	u8         reserved_0[0x8];
8014	u8         local_port[0x8];
8015	u8         reserved_1[0xd];
8016	u8         lbf_mode[0x3];
8017
8018	u8         reserved_2[0x20];
8019};
8020
8021struct mlx5_ifc_pipg_reg_bits {
8022	u8         reserved_0[0x8];
8023	u8         local_port[0x8];
8024	u8         reserved_1[0x10];
8025
8026	u8         dic[0x1];
8027	u8         reserved_2[0x19];
8028	u8         ipg[0x4];
8029	u8         reserved_3[0x2];
8030};
8031
8032struct mlx5_ifc_pifr_reg_bits {
8033	u8         reserved_0[0x8];
8034	u8         local_port[0x8];
8035	u8         reserved_1[0x10];
8036
8037	u8         reserved_2[0xe0];
8038
8039	u8         port_filter[8][0x20];
8040
8041	u8         port_filter_update_en[8][0x20];
8042};
8043
8044struct mlx5_ifc_phys_layer_cntrs_bits {
8045	u8         time_since_last_clear_high[0x20];
8046
8047	u8         time_since_last_clear_low[0x20];
8048
8049	u8         symbol_errors_high[0x20];
8050
8051	u8         symbol_errors_low[0x20];
8052
8053	u8         sync_headers_errors_high[0x20];
8054
8055	u8         sync_headers_errors_low[0x20];
8056
8057	u8         edpl_bip_errors_lane0_high[0x20];
8058
8059	u8         edpl_bip_errors_lane0_low[0x20];
8060
8061	u8         edpl_bip_errors_lane1_high[0x20];
8062
8063	u8         edpl_bip_errors_lane1_low[0x20];
8064
8065	u8         edpl_bip_errors_lane2_high[0x20];
8066
8067	u8         edpl_bip_errors_lane2_low[0x20];
8068
8069	u8         edpl_bip_errors_lane3_high[0x20];
8070
8071	u8         edpl_bip_errors_lane3_low[0x20];
8072
8073	u8         fc_fec_corrected_blocks_lane0_high[0x20];
8074
8075	u8         fc_fec_corrected_blocks_lane0_low[0x20];
8076
8077	u8         fc_fec_corrected_blocks_lane1_high[0x20];
8078
8079	u8         fc_fec_corrected_blocks_lane1_low[0x20];
8080
8081	u8         fc_fec_corrected_blocks_lane2_high[0x20];
8082
8083	u8         fc_fec_corrected_blocks_lane2_low[0x20];
8084
8085	u8         fc_fec_corrected_blocks_lane3_high[0x20];
8086
8087	u8         fc_fec_corrected_blocks_lane3_low[0x20];
8088
8089	u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
8090
8091	u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
8092
8093	u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
8094
8095	u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
8096
8097	u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
8098
8099	u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
8100
8101	u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
8102
8103	u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
8104
8105	u8         rs_fec_corrected_blocks_high[0x20];
8106
8107	u8         rs_fec_corrected_blocks_low[0x20];
8108
8109	u8         rs_fec_uncorrectable_blocks_high[0x20];
8110
8111	u8         rs_fec_uncorrectable_blocks_low[0x20];
8112
8113	u8         rs_fec_no_errors_blocks_high[0x20];
8114
8115	u8         rs_fec_no_errors_blocks_low[0x20];
8116
8117	u8         rs_fec_single_error_blocks_high[0x20];
8118
8119	u8         rs_fec_single_error_blocks_low[0x20];
8120
8121	u8         rs_fec_corrected_symbols_total_high[0x20];
8122
8123	u8         rs_fec_corrected_symbols_total_low[0x20];
8124
8125	u8         rs_fec_corrected_symbols_lane0_high[0x20];
8126
8127	u8         rs_fec_corrected_symbols_lane0_low[0x20];
8128
8129	u8         rs_fec_corrected_symbols_lane1_high[0x20];
8130
8131	u8         rs_fec_corrected_symbols_lane1_low[0x20];
8132
8133	u8         rs_fec_corrected_symbols_lane2_high[0x20];
8134
8135	u8         rs_fec_corrected_symbols_lane2_low[0x20];
8136
8137	u8         rs_fec_corrected_symbols_lane3_high[0x20];
8138
8139	u8         rs_fec_corrected_symbols_lane3_low[0x20];
8140
8141	u8         link_down_events[0x20];
8142
8143	u8         successful_recovery_events[0x20];
8144
8145	u8         reserved_0[0x180];
8146};
8147
8148struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
8149	u8	   symbol_error_counter[0x10];
8150
8151	u8         link_error_recovery_counter[0x8];
8152
8153	u8         link_downed_counter[0x8];
8154
8155	u8         port_rcv_errors[0x10];
8156
8157	u8         port_rcv_remote_physical_errors[0x10];
8158
8159	u8         port_rcv_switch_relay_errors[0x10];
8160
8161	u8         port_xmit_discards[0x10];
8162
8163	u8         port_xmit_constraint_errors[0x8];
8164
8165	u8         port_rcv_constraint_errors[0x8];
8166
8167	u8         reserved_at_70[0x8];
8168
8169	u8         link_overrun_errors[0x8];
8170
8171	u8	   reserved_at_80[0x10];
8172
8173	u8         vl_15_dropped[0x10];
8174
8175	u8	   reserved_at_a0[0xa0];
8176};
8177
8178struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
8179	u8         time_since_last_clear_high[0x20];
8180
8181	u8         time_since_last_clear_low[0x20];
8182
8183	u8         phy_received_bits_high[0x20];
8184
8185	u8         phy_received_bits_low[0x20];
8186
8187	u8         phy_symbol_errors_high[0x20];
8188
8189	u8         phy_symbol_errors_low[0x20];
8190
8191	u8         phy_corrected_bits_high[0x20];
8192
8193	u8         phy_corrected_bits_low[0x20];
8194
8195	u8         phy_corrected_bits_lane0_high[0x20];
8196
8197	u8         phy_corrected_bits_lane0_low[0x20];
8198
8199	u8         phy_corrected_bits_lane1_high[0x20];
8200
8201	u8         phy_corrected_bits_lane1_low[0x20];
8202
8203	u8         phy_corrected_bits_lane2_high[0x20];
8204
8205	u8         phy_corrected_bits_lane2_low[0x20];
8206
8207	u8         phy_corrected_bits_lane3_high[0x20];
8208
8209	u8         phy_corrected_bits_lane3_low[0x20];
8210
8211	u8         reserved_at_200[0x5c0];
8212};
8213
8214struct mlx5_ifc_infiniband_port_cntrs_bits {
8215	u8         symbol_error_counter[0x10];
8216	u8         link_error_recovery_counter[0x8];
8217	u8         link_downed_counter[0x8];
8218
8219	u8         port_rcv_errors[0x10];
8220	u8         port_rcv_remote_physical_errors[0x10];
8221
8222	u8         port_rcv_switch_relay_errors[0x10];
8223	u8         port_xmit_discards[0x10];
8224
8225	u8         port_xmit_constraint_errors[0x8];
8226	u8         port_rcv_constraint_errors[0x8];
8227	u8         reserved_0[0x8];
8228	u8         local_link_integrity_errors[0x4];
8229	u8         excessive_buffer_overrun_errors[0x4];
8230
8231	u8         reserved_1[0x10];
8232	u8         vl_15_dropped[0x10];
8233
8234	u8         port_xmit_data[0x20];
8235
8236	u8         port_rcv_data[0x20];
8237
8238	u8         port_xmit_pkts[0x20];
8239
8240	u8         port_rcv_pkts[0x20];
8241
8242	u8         port_xmit_wait[0x20];
8243
8244	u8         reserved_2[0x680];
8245};
8246
8247struct mlx5_ifc_phrr_reg_bits {
8248	u8         clr[0x1];
8249	u8         reserved_0[0x7];
8250	u8         local_port[0x8];
8251	u8         reserved_1[0x10];
8252
8253	u8         hist_group[0x8];
8254	u8         reserved_2[0x10];
8255	u8         hist_id[0x8];
8256
8257	u8         reserved_3[0x40];
8258
8259	u8         time_since_last_clear_high[0x20];
8260
8261	u8         time_since_last_clear_low[0x20];
8262
8263	u8         bin[10][0x20];
8264};
8265
8266struct mlx5_ifc_phbr_for_prio_reg_bits {
8267	u8         reserved_0[0x18];
8268	u8         prio[0x8];
8269};
8270
8271struct mlx5_ifc_phbr_for_port_tclass_reg_bits {
8272	u8         reserved_0[0x18];
8273	u8         tclass[0x8];
8274};
8275
8276struct mlx5_ifc_phbr_binding_reg_bits {
8277	u8         opcode[0x4];
8278	u8         reserved_0[0x4];
8279	u8         local_port[0x8];
8280	u8         pnat[0x2];
8281	u8         reserved_1[0xe];
8282
8283	u8         hist_group[0x8];
8284	u8         reserved_2[0x10];
8285	u8         hist_id[0x8];
8286
8287	u8         reserved_3[0x10];
8288	u8         hist_type[0x10];
8289
8290	u8         hist_parameters[0x20];
8291
8292	u8         hist_min_value[0x20];
8293
8294	u8         hist_max_value[0x20];
8295
8296	u8         sample_time[0x20];
8297};
8298
8299enum {
8300	MLX5_PFCC_REG_PPAN_DISABLED  = 0x0,
8301	MLX5_PFCC_REG_PPAN_ENABLED   = 0x1,
8302};
8303
8304struct mlx5_ifc_pfcc_reg_bits {
8305	u8         dcbx_operation_type[0x2];
8306	u8         cap_local_admin[0x1];
8307	u8         cap_remote_admin[0x1];
8308	u8         reserved_0[0x4];
8309	u8         local_port[0x8];
8310	u8         pnat[0x2];
8311	u8         reserved_1[0xc];
8312	u8         shl_cap[0x1];
8313	u8         shl_opr[0x1];
8314
8315	u8         ppan[0x4];
8316	u8         reserved_2[0x4];
8317	u8         prio_mask_tx[0x8];
8318	u8         reserved_3[0x8];
8319	u8         prio_mask_rx[0x8];
8320
8321	u8         pptx[0x1];
8322	u8         aptx[0x1];
8323	u8         reserved_4[0x6];
8324	u8         pfctx[0x8];
8325	u8         reserved_5[0x8];
8326	u8         cbftx[0x8];
8327
8328	u8         pprx[0x1];
8329	u8         aprx[0x1];
8330	u8         reserved_6[0x6];
8331	u8         pfcrx[0x8];
8332	u8         reserved_7[0x8];
8333	u8         cbfrx[0x8];
8334
8335	u8         device_stall_minor_watermark[0x10];
8336	u8         device_stall_critical_watermark[0x10];
8337
8338	u8         reserved_8[0x60];
8339};
8340
8341struct mlx5_ifc_pelc_reg_bits {
8342	u8         op[0x4];
8343	u8         reserved_0[0x4];
8344	u8         local_port[0x8];
8345	u8         reserved_1[0x10];
8346
8347	u8         op_admin[0x8];
8348	u8         op_capability[0x8];
8349	u8         op_request[0x8];
8350	u8         op_active[0x8];
8351
8352	u8         admin[0x40];
8353
8354	u8         capability[0x40];
8355
8356	u8         request[0x40];
8357
8358	u8         active[0x40];
8359
8360	u8         reserved_2[0x80];
8361};
8362
8363struct mlx5_ifc_peir_reg_bits {
8364	u8         reserved_0[0x8];
8365	u8         local_port[0x8];
8366	u8         reserved_1[0x10];
8367
8368	u8         reserved_2[0xc];
8369	u8         error_count[0x4];
8370	u8         reserved_3[0x10];
8371
8372	u8         reserved_4[0xc];
8373	u8         lane[0x4];
8374	u8         reserved_5[0x8];
8375	u8         error_type[0x8];
8376};
8377
8378struct mlx5_ifc_pcap_reg_bits {
8379	u8         reserved_0[0x8];
8380	u8         local_port[0x8];
8381	u8         reserved_1[0x10];
8382
8383	u8         port_capability_mask[4][0x20];
8384};
8385
8386struct mlx5_ifc_pbmc_reg_bits {
8387	u8         reserved_0[0x8];
8388	u8         local_port[0x8];
8389	u8         reserved_1[0x10];
8390
8391	u8         xoff_timer_value[0x10];
8392	u8         xoff_refresh[0x10];
8393
8394	u8         reserved_2[0x10];
8395	u8         port_buffer_size[0x10];
8396
8397	struct mlx5_ifc_bufferx_reg_bits buffer[10];
8398
8399	u8         reserved_3[0x40];
8400
8401	u8         port_shared_buffer[0x40];
8402};
8403
8404struct mlx5_ifc_paos_reg_bits {
8405	u8         swid[0x8];
8406	u8         local_port[0x8];
8407	u8         reserved_0[0x4];
8408	u8         admin_status[0x4];
8409	u8         reserved_1[0x4];
8410	u8         oper_status[0x4];
8411
8412	u8         ase[0x1];
8413	u8         ee[0x1];
8414	u8         reserved_2[0x1c];
8415	u8         e[0x2];
8416
8417	u8         reserved_3[0x40];
8418};
8419
8420struct mlx5_ifc_pamp_reg_bits {
8421	u8         reserved_0[0x8];
8422	u8         opamp_group[0x8];
8423	u8         reserved_1[0xc];
8424	u8         opamp_group_type[0x4];
8425
8426	u8         start_index[0x10];
8427	u8         reserved_2[0x4];
8428	u8         num_of_indices[0xc];
8429
8430	u8         index_data[18][0x10];
8431};
8432
8433struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits {
8434	u8         llr_rx_cells_high[0x20];
8435
8436	u8         llr_rx_cells_low[0x20];
8437
8438	u8         llr_rx_error_high[0x20];
8439
8440	u8         llr_rx_error_low[0x20];
8441
8442	u8         llr_rx_crc_error_high[0x20];
8443
8444	u8         llr_rx_crc_error_low[0x20];
8445
8446	u8         llr_tx_cells_high[0x20];
8447
8448	u8         llr_tx_cells_low[0x20];
8449
8450	u8         llr_tx_ret_cells_high[0x20];
8451
8452	u8         llr_tx_ret_cells_low[0x20];
8453
8454	u8         llr_tx_ret_events_high[0x20];
8455
8456	u8         llr_tx_ret_events_low[0x20];
8457
8458	u8         reserved_0[0x640];
8459};
8460
8461struct mlx5_ifc_lane_2_module_mapping_bits {
8462	u8         reserved_0[0x6];
8463	u8         rx_lane[0x2];
8464	u8         reserved_1[0x6];
8465	u8         tx_lane[0x2];
8466	u8         reserved_2[0x8];
8467	u8         module[0x8];
8468};
8469
8470struct mlx5_ifc_eth_per_traffic_class_layout_bits {
8471	u8         transmit_queue_high[0x20];
8472
8473	u8         transmit_queue_low[0x20];
8474
8475	u8         reserved_0[0x780];
8476};
8477
8478struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits {
8479	u8         no_buffer_discard_uc_high[0x20];
8480
8481	u8         no_buffer_discard_uc_low[0x20];
8482
8483	u8         wred_discard_high[0x20];
8484
8485	u8         wred_discard_low[0x20];
8486
8487	u8         reserved_0[0x740];
8488};
8489
8490struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
8491	u8         rx_octets_high[0x20];
8492
8493	u8         rx_octets_low[0x20];
8494
8495	u8         reserved_0[0xc0];
8496
8497	u8         rx_frames_high[0x20];
8498
8499	u8         rx_frames_low[0x20];
8500
8501	u8         tx_octets_high[0x20];
8502
8503	u8         tx_octets_low[0x20];
8504
8505	u8         reserved_1[0xc0];
8506
8507	u8         tx_frames_high[0x20];
8508
8509	u8         tx_frames_low[0x20];
8510
8511	u8         rx_pause_high[0x20];
8512
8513	u8         rx_pause_low[0x20];
8514
8515	u8         rx_pause_duration_high[0x20];
8516
8517	u8         rx_pause_duration_low[0x20];
8518
8519	u8         tx_pause_high[0x20];
8520
8521	u8         tx_pause_low[0x20];
8522
8523	u8         tx_pause_duration_high[0x20];
8524
8525	u8         tx_pause_duration_low[0x20];
8526
8527	u8         rx_pause_transition_high[0x20];
8528
8529	u8         rx_pause_transition_low[0x20];
8530
8531	u8         rx_discards_high[0x20];
8532
8533	u8         rx_discards_low[0x20];
8534
8535	u8         device_stall_minor_watermark_cnt_high[0x20];
8536
8537	u8         device_stall_minor_watermark_cnt_low[0x20];
8538
8539	u8         device_stall_critical_watermark_cnt_high[0x20];
8540
8541	u8         device_stall_critical_watermark_cnt_low[0x20];
8542
8543	u8         reserved_2[0x340];
8544};
8545
8546struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
8547	u8         port_transmit_wait_high[0x20];
8548
8549	u8         port_transmit_wait_low[0x20];
8550
8551	u8         ecn_marked_high[0x20];
8552
8553	u8         ecn_marked_low[0x20];
8554
8555	u8         no_buffer_discard_mc_high[0x20];
8556
8557	u8         no_buffer_discard_mc_low[0x20];
8558
8559	u8         reserved_0[0x700];
8560};
8561
8562struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
8563	u8         a_frames_transmitted_ok_high[0x20];
8564
8565	u8         a_frames_transmitted_ok_low[0x20];
8566
8567	u8         a_frames_received_ok_high[0x20];
8568
8569	u8         a_frames_received_ok_low[0x20];
8570
8571	u8         a_frame_check_sequence_errors_high[0x20];
8572
8573	u8         a_frame_check_sequence_errors_low[0x20];
8574
8575	u8         a_alignment_errors_high[0x20];
8576
8577	u8         a_alignment_errors_low[0x20];
8578
8579	u8         a_octets_transmitted_ok_high[0x20];
8580
8581	u8         a_octets_transmitted_ok_low[0x20];
8582
8583	u8         a_octets_received_ok_high[0x20];
8584
8585	u8         a_octets_received_ok_low[0x20];
8586
8587	u8         a_multicast_frames_xmitted_ok_high[0x20];
8588
8589	u8         a_multicast_frames_xmitted_ok_low[0x20];
8590
8591	u8         a_broadcast_frames_xmitted_ok_high[0x20];
8592
8593	u8         a_broadcast_frames_xmitted_ok_low[0x20];
8594
8595	u8         a_multicast_frames_received_ok_high[0x20];
8596
8597	u8         a_multicast_frames_received_ok_low[0x20];
8598
8599	u8         a_broadcast_frames_recieved_ok_high[0x20];
8600
8601	u8         a_broadcast_frames_recieved_ok_low[0x20];
8602
8603	u8         a_in_range_length_errors_high[0x20];
8604
8605	u8         a_in_range_length_errors_low[0x20];
8606
8607	u8         a_out_of_range_length_field_high[0x20];
8608
8609	u8         a_out_of_range_length_field_low[0x20];
8610
8611	u8         a_frame_too_long_errors_high[0x20];
8612
8613	u8         a_frame_too_long_errors_low[0x20];
8614
8615	u8         a_symbol_error_during_carrier_high[0x20];
8616
8617	u8         a_symbol_error_during_carrier_low[0x20];
8618
8619	u8         a_mac_control_frames_transmitted_high[0x20];
8620
8621	u8         a_mac_control_frames_transmitted_low[0x20];
8622
8623	u8         a_mac_control_frames_received_high[0x20];
8624
8625	u8         a_mac_control_frames_received_low[0x20];
8626
8627	u8         a_unsupported_opcodes_received_high[0x20];
8628
8629	u8         a_unsupported_opcodes_received_low[0x20];
8630
8631	u8         a_pause_mac_ctrl_frames_received_high[0x20];
8632
8633	u8         a_pause_mac_ctrl_frames_received_low[0x20];
8634
8635	u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
8636
8637	u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
8638
8639	u8         reserved_0[0x300];
8640};
8641
8642struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
8643	u8         dot3stats_alignment_errors_high[0x20];
8644
8645	u8         dot3stats_alignment_errors_low[0x20];
8646
8647	u8         dot3stats_fcs_errors_high[0x20];
8648
8649	u8         dot3stats_fcs_errors_low[0x20];
8650
8651	u8         dot3stats_single_collision_frames_high[0x20];
8652
8653	u8         dot3stats_single_collision_frames_low[0x20];
8654
8655	u8         dot3stats_multiple_collision_frames_high[0x20];
8656
8657	u8         dot3stats_multiple_collision_frames_low[0x20];
8658
8659	u8         dot3stats_sqe_test_errors_high[0x20];
8660
8661	u8         dot3stats_sqe_test_errors_low[0x20];
8662
8663	u8         dot3stats_deferred_transmissions_high[0x20];
8664
8665	u8         dot3stats_deferred_transmissions_low[0x20];
8666
8667	u8         dot3stats_late_collisions_high[0x20];
8668
8669	u8         dot3stats_late_collisions_low[0x20];
8670
8671	u8         dot3stats_excessive_collisions_high[0x20];
8672
8673	u8         dot3stats_excessive_collisions_low[0x20];
8674
8675	u8         dot3stats_internal_mac_transmit_errors_high[0x20];
8676
8677	u8         dot3stats_internal_mac_transmit_errors_low[0x20];
8678
8679	u8         dot3stats_carrier_sense_errors_high[0x20];
8680
8681	u8         dot3stats_carrier_sense_errors_low[0x20];
8682
8683	u8         dot3stats_frame_too_longs_high[0x20];
8684
8685	u8         dot3stats_frame_too_longs_low[0x20];
8686
8687	u8         dot3stats_internal_mac_receive_errors_high[0x20];
8688
8689	u8         dot3stats_internal_mac_receive_errors_low[0x20];
8690
8691	u8         dot3stats_symbol_errors_high[0x20];
8692
8693	u8         dot3stats_symbol_errors_low[0x20];
8694
8695	u8         dot3control_in_unknown_opcodes_high[0x20];
8696
8697	u8         dot3control_in_unknown_opcodes_low[0x20];
8698
8699	u8         dot3in_pause_frames_high[0x20];
8700
8701	u8         dot3in_pause_frames_low[0x20];
8702
8703	u8         dot3out_pause_frames_high[0x20];
8704
8705	u8         dot3out_pause_frames_low[0x20];
8706
8707	u8         reserved_0[0x3c0];
8708};
8709
8710struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
8711	u8         if_in_octets_high[0x20];
8712
8713	u8         if_in_octets_low[0x20];
8714
8715	u8         if_in_ucast_pkts_high[0x20];
8716
8717	u8         if_in_ucast_pkts_low[0x20];
8718
8719	u8         if_in_discards_high[0x20];
8720
8721	u8         if_in_discards_low[0x20];
8722
8723	u8         if_in_errors_high[0x20];
8724
8725	u8         if_in_errors_low[0x20];
8726
8727	u8         if_in_unknown_protos_high[0x20];
8728
8729	u8         if_in_unknown_protos_low[0x20];
8730
8731	u8         if_out_octets_high[0x20];
8732
8733	u8         if_out_octets_low[0x20];
8734
8735	u8         if_out_ucast_pkts_high[0x20];
8736
8737	u8         if_out_ucast_pkts_low[0x20];
8738
8739	u8         if_out_discards_high[0x20];
8740
8741	u8         if_out_discards_low[0x20];
8742
8743	u8         if_out_errors_high[0x20];
8744
8745	u8         if_out_errors_low[0x20];
8746
8747	u8         if_in_multicast_pkts_high[0x20];
8748
8749	u8         if_in_multicast_pkts_low[0x20];
8750
8751	u8         if_in_broadcast_pkts_high[0x20];
8752
8753	u8         if_in_broadcast_pkts_low[0x20];
8754
8755	u8         if_out_multicast_pkts_high[0x20];
8756
8757	u8         if_out_multicast_pkts_low[0x20];
8758
8759	u8         if_out_broadcast_pkts_high[0x20];
8760
8761	u8         if_out_broadcast_pkts_low[0x20];
8762
8763	u8         reserved_0[0x480];
8764};
8765
8766struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
8767	u8         ether_stats_drop_events_high[0x20];
8768
8769	u8         ether_stats_drop_events_low[0x20];
8770
8771	u8         ether_stats_octets_high[0x20];
8772
8773	u8         ether_stats_octets_low[0x20];
8774
8775	u8         ether_stats_pkts_high[0x20];
8776
8777	u8         ether_stats_pkts_low[0x20];
8778
8779	u8         ether_stats_broadcast_pkts_high[0x20];
8780
8781	u8         ether_stats_broadcast_pkts_low[0x20];
8782
8783	u8         ether_stats_multicast_pkts_high[0x20];
8784
8785	u8         ether_stats_multicast_pkts_low[0x20];
8786
8787	u8         ether_stats_crc_align_errors_high[0x20];
8788
8789	u8         ether_stats_crc_align_errors_low[0x20];
8790
8791	u8         ether_stats_undersize_pkts_high[0x20];
8792
8793	u8         ether_stats_undersize_pkts_low[0x20];
8794
8795	u8         ether_stats_oversize_pkts_high[0x20];
8796
8797	u8         ether_stats_oversize_pkts_low[0x20];
8798
8799	u8         ether_stats_fragments_high[0x20];
8800
8801	u8         ether_stats_fragments_low[0x20];
8802
8803	u8         ether_stats_jabbers_high[0x20];
8804
8805	u8         ether_stats_jabbers_low[0x20];
8806
8807	u8         ether_stats_collisions_high[0x20];
8808
8809	u8         ether_stats_collisions_low[0x20];
8810
8811	u8         ether_stats_pkts64octets_high[0x20];
8812
8813	u8         ether_stats_pkts64octets_low[0x20];
8814
8815	u8         ether_stats_pkts65to127octets_high[0x20];
8816
8817	u8         ether_stats_pkts65to127octets_low[0x20];
8818
8819	u8         ether_stats_pkts128to255octets_high[0x20];
8820
8821	u8         ether_stats_pkts128to255octets_low[0x20];
8822
8823	u8         ether_stats_pkts256to511octets_high[0x20];
8824
8825	u8         ether_stats_pkts256to511octets_low[0x20];
8826
8827	u8         ether_stats_pkts512to1023octets_high[0x20];
8828
8829	u8         ether_stats_pkts512to1023octets_low[0x20];
8830
8831	u8         ether_stats_pkts1024to1518octets_high[0x20];
8832
8833	u8         ether_stats_pkts1024to1518octets_low[0x20];
8834
8835	u8         ether_stats_pkts1519to2047octets_high[0x20];
8836
8837	u8         ether_stats_pkts1519to2047octets_low[0x20];
8838
8839	u8         ether_stats_pkts2048to4095octets_high[0x20];
8840
8841	u8         ether_stats_pkts2048to4095octets_low[0x20];
8842
8843	u8         ether_stats_pkts4096to8191octets_high[0x20];
8844
8845	u8         ether_stats_pkts4096to8191octets_low[0x20];
8846
8847	u8         ether_stats_pkts8192to10239octets_high[0x20];
8848
8849	u8         ether_stats_pkts8192to10239octets_low[0x20];
8850
8851	u8         reserved_0[0x280];
8852};
8853
8854struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits {
8855	u8         symbol_error_counter[0x10];
8856	u8         link_error_recovery_counter[0x8];
8857	u8         link_downed_counter[0x8];
8858
8859	u8         port_rcv_errors[0x10];
8860	u8         port_rcv_remote_physical_errors[0x10];
8861
8862	u8         port_rcv_switch_relay_errors[0x10];
8863	u8         port_xmit_discards[0x10];
8864
8865	u8         port_xmit_constraint_errors[0x8];
8866	u8         port_rcv_constraint_errors[0x8];
8867	u8         reserved_0[0x8];
8868	u8         local_link_integrity_errors[0x4];
8869	u8         excessive_buffer_overrun_errors[0x4];
8870
8871	u8         reserved_1[0x10];
8872	u8         vl_15_dropped[0x10];
8873
8874	u8         port_xmit_data[0x20];
8875
8876	u8         port_rcv_data[0x20];
8877
8878	u8         port_xmit_pkts[0x20];
8879
8880	u8         port_rcv_pkts[0x20];
8881
8882	u8         port_xmit_wait[0x20];
8883
8884	u8         reserved_2[0x680];
8885};
8886
8887struct mlx5_ifc_trc_tlb_reg_bits {
8888	u8         reserved_0[0x80];
8889
8890	u8         tlb_addr[0][0x40];
8891};
8892
8893struct mlx5_ifc_trc_read_fifo_reg_bits {
8894	u8         reserved_0[0x10];
8895	u8         requested_event_num[0x10];
8896
8897	u8         reserved_1[0x20];
8898
8899	u8         reserved_2[0x10];
8900	u8         acual_event_num[0x10];
8901
8902	u8         reserved_3[0x20];
8903
8904	u8         event[0][0x40];
8905};
8906
8907struct mlx5_ifc_trc_lock_reg_bits {
8908	u8         reserved_0[0x1f];
8909	u8         lock[0x1];
8910
8911	u8         reserved_1[0x60];
8912};
8913
8914struct mlx5_ifc_trc_filter_reg_bits {
8915	u8         status[0x1];
8916	u8         reserved_0[0xf];
8917	u8         filter_index[0x10];
8918
8919	u8         reserved_1[0x20];
8920
8921	u8         filter_val[0x20];
8922
8923	u8         reserved_2[0x1a0];
8924};
8925
8926struct mlx5_ifc_trc_event_reg_bits {
8927	u8         status[0x1];
8928	u8         reserved_0[0xf];
8929	u8         event_index[0x10];
8930
8931	u8         reserved_1[0x20];
8932
8933	u8         event_id[0x20];
8934
8935	u8         event_selector_val[0x10];
8936	u8         event_selector_size[0x10];
8937
8938	u8         reserved_2[0x180];
8939};
8940
8941struct mlx5_ifc_trc_conf_reg_bits {
8942	u8         limit_en[0x1];
8943	u8         reserved_0[0x3];
8944	u8         dump_mode[0x4];
8945	u8         reserved_1[0x15];
8946	u8         state[0x3];
8947
8948	u8         reserved_2[0x20];
8949
8950	u8         limit_event_index[0x20];
8951
8952	u8         mkey[0x20];
8953
8954	u8         fifo_ready_ev_num[0x20];
8955
8956	u8         reserved_3[0x160];
8957};
8958
8959struct mlx5_ifc_trc_cap_reg_bits {
8960	u8         reserved_0[0x18];
8961	u8         dump_mode[0x8];
8962
8963	u8         reserved_1[0x20];
8964
8965	u8         num_of_events[0x10];
8966	u8         num_of_filters[0x10];
8967
8968	u8         fifo_size[0x20];
8969
8970	u8         tlb_size[0x10];
8971	u8         event_size[0x10];
8972
8973	u8         reserved_2[0x160];
8974};
8975
8976struct mlx5_ifc_set_node_in_bits {
8977	u8         node_description[64][0x8];
8978};
8979
8980struct mlx5_ifc_register_power_settings_bits {
8981	u8         reserved_0[0x18];
8982	u8         power_settings_level[0x8];
8983
8984	u8         reserved_1[0x60];
8985};
8986
8987struct mlx5_ifc_register_host_endianess_bits {
8988	u8         he[0x1];
8989	u8         reserved_0[0x1f];
8990
8991	u8         reserved_1[0x60];
8992};
8993
8994struct mlx5_ifc_register_diag_buffer_ctrl_bits {
8995	u8         physical_address[0x40];
8996};
8997
8998struct mlx5_ifc_qtct_reg_bits {
8999	u8         operation_type[0x2];
9000	u8         cap_local_admin[0x1];
9001	u8         cap_remote_admin[0x1];
9002	u8         reserved_0[0x4];
9003	u8         port_number[0x8];
9004	u8         reserved_1[0xd];
9005	u8         prio[0x3];
9006
9007	u8         reserved_2[0x1d];
9008	u8         tclass[0x3];
9009};
9010
9011struct mlx5_ifc_qpdp_reg_bits {
9012	u8         reserved_0[0x8];
9013	u8         port_number[0x8];
9014	u8         reserved_1[0x10];
9015
9016	u8         reserved_2[0x1d];
9017	u8         pprio[0x3];
9018};
9019
9020struct mlx5_ifc_port_info_ro_fields_param_bits {
9021	u8         reserved_0[0x8];
9022	u8         port[0x8];
9023	u8         max_gid[0x10];
9024
9025	u8         reserved_1[0x20];
9026
9027	u8         port_guid[0x40];
9028};
9029
9030struct mlx5_ifc_nvqc_reg_bits {
9031	u8         type[0x20];
9032
9033	u8         reserved_0[0x18];
9034	u8         version[0x4];
9035	u8         reserved_1[0x2];
9036	u8         support_wr[0x1];
9037	u8         support_rd[0x1];
9038};
9039
9040struct mlx5_ifc_nvia_reg_bits {
9041	u8         reserved_0[0x1d];
9042	u8         target[0x3];
9043
9044	u8         reserved_1[0x20];
9045};
9046
9047struct mlx5_ifc_nvdi_reg_bits {
9048	struct mlx5_ifc_config_item_bits configuration_item_header;
9049};
9050
9051struct mlx5_ifc_nvda_reg_bits {
9052	struct mlx5_ifc_config_item_bits configuration_item_header;
9053
9054	u8         configuration_item_data[0x20];
9055};
9056
9057struct mlx5_ifc_node_info_ro_fields_param_bits {
9058	u8         system_image_guid[0x40];
9059
9060	u8         reserved_0[0x40];
9061
9062	u8         node_guid[0x40];
9063
9064	u8         reserved_1[0x10];
9065	u8         max_pkey[0x10];
9066
9067	u8         reserved_2[0x20];
9068};
9069
9070struct mlx5_ifc_ets_tcn_config_reg_bits {
9071	u8         g[0x1];
9072	u8         b[0x1];
9073	u8         r[0x1];
9074	u8         reserved_0[0x9];
9075	u8         group[0x4];
9076	u8         reserved_1[0x9];
9077	u8         bw_allocation[0x7];
9078
9079	u8         reserved_2[0xc];
9080	u8         max_bw_units[0x4];
9081	u8         reserved_3[0x8];
9082	u8         max_bw_value[0x8];
9083};
9084
9085struct mlx5_ifc_ets_global_config_reg_bits {
9086	u8         reserved_0[0x2];
9087	u8         r[0x1];
9088	u8         reserved_1[0x1d];
9089
9090	u8         reserved_2[0xc];
9091	u8         max_bw_units[0x4];
9092	u8         reserved_3[0x8];
9093	u8         max_bw_value[0x8];
9094};
9095
9096struct mlx5_ifc_qetc_reg_bits {
9097	u8                                         reserved_at_0[0x8];
9098	u8                                         port_number[0x8];
9099	u8                                         reserved_at_10[0x30];
9100
9101	struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
9102	struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9103};
9104
9105struct mlx5_ifc_nodnic_mac_filters_bits {
9106	struct mlx5_ifc_mac_address_layout_bits mac_filter0;
9107
9108	struct mlx5_ifc_mac_address_layout_bits mac_filter1;
9109
9110	struct mlx5_ifc_mac_address_layout_bits mac_filter2;
9111
9112	struct mlx5_ifc_mac_address_layout_bits mac_filter3;
9113
9114	struct mlx5_ifc_mac_address_layout_bits mac_filter4;
9115
9116	u8         reserved_0[0xc0];
9117};
9118
9119struct mlx5_ifc_nodnic_gid_filters_bits {
9120	u8         mgid_filter0[16][0x8];
9121
9122	u8         mgid_filter1[16][0x8];
9123
9124	u8         mgid_filter2[16][0x8];
9125
9126	u8         mgid_filter3[16][0x8];
9127};
9128
9129enum {
9130	MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT  = 0x0,
9131	MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT    = 0x1,
9132};
9133
9134enum {
9135	MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE  = 0x0,
9136	MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE     = 0x1,
9137};
9138
9139struct mlx5_ifc_nodnic_config_reg_bits {
9140	u8         no_dram_nic_revision[0x8];
9141	u8         hardware_format[0x8];
9142	u8         support_receive_filter[0x1];
9143	u8         support_promisc_filter[0x1];
9144	u8         support_promisc_multicast_filter[0x1];
9145	u8         reserved_0[0x2];
9146	u8         log_working_buffer_size[0x3];
9147	u8         log_pkey_table_size[0x4];
9148	u8         reserved_1[0x3];
9149	u8         num_ports[0x1];
9150
9151	u8         reserved_2[0x2];
9152	u8         log_max_ring_size[0x6];
9153	u8         reserved_3[0x18];
9154
9155	u8         lkey[0x20];
9156
9157	u8         cqe_format[0x4];
9158	u8         reserved_4[0x1c];
9159
9160	u8         node_guid[0x40];
9161
9162	u8         reserved_5[0x740];
9163
9164	struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings;
9165
9166	struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings;
9167};
9168
9169struct mlx5_ifc_vlan_layout_bits {
9170	u8         reserved_0[0x14];
9171	u8         vlan[0xc];
9172
9173	u8         reserved_1[0x20];
9174};
9175
9176struct mlx5_ifc_umr_pointer_desc_argument_bits {
9177	u8         reserved_0[0x20];
9178
9179	u8         mkey[0x20];
9180
9181	u8         addressh_63_32[0x20];
9182
9183	u8         addressl_31_0[0x20];
9184};
9185
9186struct mlx5_ifc_ud_adrs_vector_bits {
9187	u8         dc_key[0x40];
9188
9189	u8         ext[0x1];
9190	u8         reserved_0[0x7];
9191	u8         destination_qp_dct[0x18];
9192
9193	u8         static_rate[0x4];
9194	u8         sl_eth_prio[0x4];
9195	u8         fl[0x1];
9196	u8         mlid[0x7];
9197	u8         rlid_udp_sport[0x10];
9198
9199	u8         reserved_1[0x20];
9200
9201	u8         rmac_47_16[0x20];
9202
9203	u8         rmac_15_0[0x10];
9204	u8         tclass[0x8];
9205	u8         hop_limit[0x8];
9206
9207	u8         reserved_2[0x1];
9208	u8         grh[0x1];
9209	u8         reserved_3[0x2];
9210	u8         src_addr_index[0x8];
9211	u8         flow_label[0x14];
9212
9213	u8         rgid_rip[16][0x8];
9214};
9215
9216struct mlx5_ifc_port_module_event_bits {
9217	u8         reserved_0[0x8];
9218	u8         module[0x8];
9219	u8         reserved_1[0xc];
9220	u8         module_status[0x4];
9221
9222	u8         reserved_2[0x14];
9223	u8         error_type[0x4];
9224	u8         reserved_3[0x8];
9225
9226	u8         reserved_4[0xa0];
9227};
9228
9229struct mlx5_ifc_icmd_control_bits {
9230	u8         opcode[0x10];
9231	u8         status[0x8];
9232	u8         reserved_0[0x7];
9233	u8         busy[0x1];
9234};
9235
9236struct mlx5_ifc_eqe_bits {
9237	u8         reserved_0[0x8];
9238	u8         event_type[0x8];
9239	u8         reserved_1[0x8];
9240	u8         event_sub_type[0x8];
9241
9242	u8         reserved_2[0xe0];
9243
9244	union mlx5_ifc_event_auto_bits event_data;
9245
9246	u8         reserved_3[0x10];
9247	u8         signature[0x8];
9248	u8         reserved_4[0x7];
9249	u8         owner[0x1];
9250};
9251
9252enum {
9253	MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
9254};
9255
9256struct mlx5_ifc_cmd_queue_entry_bits {
9257	u8         type[0x8];
9258	u8         reserved_0[0x18];
9259
9260	u8         input_length[0x20];
9261
9262	u8         input_mailbox_pointer_63_32[0x20];
9263
9264	u8         input_mailbox_pointer_31_9[0x17];
9265	u8         reserved_1[0x9];
9266
9267	u8         command_input_inline_data[16][0x8];
9268
9269	u8         command_output_inline_data[16][0x8];
9270
9271	u8         output_mailbox_pointer_63_32[0x20];
9272
9273	u8         output_mailbox_pointer_31_9[0x17];
9274	u8         reserved_2[0x9];
9275
9276	u8         output_length[0x20];
9277
9278	u8         token[0x8];
9279	u8         signature[0x8];
9280	u8         reserved_3[0x8];
9281	u8         status[0x7];
9282	u8         ownership[0x1];
9283};
9284
9285struct mlx5_ifc_cmd_out_bits {
9286	u8         status[0x8];
9287	u8         reserved_0[0x18];
9288
9289	u8         syndrome[0x20];
9290
9291	u8         command_output[0x20];
9292};
9293
9294struct mlx5_ifc_cmd_in_bits {
9295	u8         opcode[0x10];
9296	u8         reserved_0[0x10];
9297
9298	u8         reserved_1[0x10];
9299	u8         op_mod[0x10];
9300
9301	u8         command[0][0x20];
9302};
9303
9304struct mlx5_ifc_cmd_if_box_bits {
9305	u8         mailbox_data[512][0x8];
9306
9307	u8         reserved_0[0x180];
9308
9309	u8         next_pointer_63_32[0x20];
9310
9311	u8         next_pointer_31_10[0x16];
9312	u8         reserved_1[0xa];
9313
9314	u8         block_number[0x20];
9315
9316	u8         reserved_2[0x8];
9317	u8         token[0x8];
9318	u8         ctrl_signature[0x8];
9319	u8         signature[0x8];
9320};
9321
9322struct mlx5_ifc_mtt_bits {
9323	u8         ptag_63_32[0x20];
9324
9325	u8         ptag_31_8[0x18];
9326	u8         reserved_0[0x6];
9327	u8         wr_en[0x1];
9328	u8         rd_en[0x1];
9329};
9330
9331/* Vendor Specific Capabilities, VSC */
9332enum {
9333	MLX5_VSC_DOMAIN_ICMD			= 0x1,
9334	MLX5_VSC_DOMAIN_PROTECTED_CRSPACE	= 0x6,
9335	MLX5_VSC_DOMAIN_SEMAPHORES		= 0xA,
9336};
9337
9338struct mlx5_ifc_vendor_specific_cap_bits {
9339	u8         type[0x8];
9340	u8         length[0x8];
9341	u8         next_pointer[0x8];
9342	u8         capability_id[0x8];
9343
9344	u8         status[0x3];
9345	u8         reserved_0[0xd];
9346	u8         space[0x10];
9347
9348	u8         counter[0x20];
9349
9350	u8         semaphore[0x20];
9351
9352	u8         flag[0x1];
9353	u8         reserved_1[0x1];
9354	u8         address[0x1e];
9355
9356	u8         data[0x20];
9357};
9358
9359enum {
9360	MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
9361	MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
9362	MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
9363};
9364
9365enum {
9366	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
9367	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
9368	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
9369};
9370
9371enum {
9372	MLX5_HEALTH_SYNDR_FW_ERR                                      = 0x1,
9373	MLX5_HEALTH_SYNDR_IRISC_ERR                                   = 0x7,
9374	MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR                        = 0x8,
9375	MLX5_HEALTH_SYNDR_CRC_ERR                                     = 0x9,
9376	MLX5_HEALTH_SYNDR_FETCH_PCI_ERR                               = 0xa,
9377	MLX5_HEALTH_SYNDR_HW_FTL_ERR                                  = 0xb,
9378	MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR                        = 0xc,
9379	MLX5_HEALTH_SYNDR_EQ_ERR                                      = 0xd,
9380	MLX5_HEALTH_SYNDR_EQ_INV                                      = 0xe,
9381	MLX5_HEALTH_SYNDR_FFSER_ERR                                   = 0xf,
9382	MLX5_HEALTH_SYNDR_HIGH_TEMP                                   = 0x10,
9383};
9384
9385struct mlx5_ifc_initial_seg_bits {
9386	u8         fw_rev_minor[0x10];
9387	u8         fw_rev_major[0x10];
9388
9389	u8         cmd_interface_rev[0x10];
9390	u8         fw_rev_subminor[0x10];
9391
9392	u8         reserved_0[0x40];
9393
9394	u8         cmdq_phy_addr_63_32[0x20];
9395
9396	u8         cmdq_phy_addr_31_12[0x14];
9397	u8         reserved_1[0x2];
9398	u8         nic_interface[0x2];
9399	u8         log_cmdq_size[0x4];
9400	u8         log_cmdq_stride[0x4];
9401
9402	u8         command_doorbell_vector[0x20];
9403
9404	u8         reserved_2[0xf00];
9405
9406	u8         initializing[0x1];
9407	u8         reserved_3[0x4];
9408	u8         nic_interface_supported[0x3];
9409	u8         reserved_4[0x18];
9410
9411	struct mlx5_ifc_health_buffer_bits health_buffer;
9412
9413	u8         no_dram_nic_offset[0x20];
9414
9415	u8         reserved_5[0x6de0];
9416
9417	u8         internal_timer_h[0x20];
9418
9419	u8         internal_timer_l[0x20];
9420
9421	u8         reserved_6[0x20];
9422
9423	u8         reserved_7[0x1f];
9424	u8         clear_int[0x1];
9425
9426	u8         health_syndrome[0x8];
9427	u8         health_counter[0x18];
9428
9429	u8         reserved_8[0x17fc0];
9430};
9431
9432union mlx5_ifc_icmd_interface_document_bits {
9433	struct mlx5_ifc_fw_version_bits fw_version;
9434	struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in;
9435	struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out;
9436	struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in;
9437	struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in;
9438	struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out;
9439	struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out;
9440	struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general;
9441	struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in;
9442	struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out;
9443	struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out;
9444	struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in;
9445	struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in;
9446	struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out;
9447	u8         reserved_0[0x42c0];
9448};
9449
9450union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
9451	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9452	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9453	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9454	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9455	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9456	struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
9457	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9458	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9459	struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
9460	struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs;
9461	u8         reserved_0[0x7c0];
9462};
9463
9464struct mlx5_ifc_ppcnt_reg_bits {
9465	u8         swid[0x8];
9466	u8         local_port[0x8];
9467	u8         pnat[0x2];
9468	u8         reserved_0[0x8];
9469	u8         grp[0x6];
9470
9471	u8         clr[0x1];
9472	u8         reserved_1[0x1c];
9473	u8         prio_tc[0x3];
9474
9475	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9476};
9477
9478struct mlx5_ifc_pcie_performance_counters_data_layout_bits {
9479	u8         life_time_counter_high[0x20];
9480
9481	u8         life_time_counter_low[0x20];
9482
9483	u8         rx_errors[0x20];
9484
9485	u8         tx_errors[0x20];
9486
9487	u8         l0_to_recovery_eieos[0x20];
9488
9489	u8         l0_to_recovery_ts[0x20];
9490
9491	u8         l0_to_recovery_framing[0x20];
9492
9493	u8         l0_to_recovery_retrain[0x20];
9494
9495	u8         crc_error_dllp[0x20];
9496
9497	u8         crc_error_tlp[0x20];
9498
9499	u8         reserved_0[0x680];
9500};
9501
9502struct mlx5_ifc_pcie_timers_and_states_data_layout_bits {
9503	u8         life_time_counter_high[0x20];
9504
9505	u8         life_time_counter_low[0x20];
9506
9507	u8         time_to_boot_image_start[0x20];
9508
9509	u8         time_to_link_image[0x20];
9510
9511	u8         calibration_time[0x20];
9512
9513	u8         time_to_first_perst[0x20];
9514
9515	u8         time_to_detect_state[0x20];
9516
9517	u8         time_to_l0[0x20];
9518
9519	u8         time_to_crs_en[0x20];
9520
9521	u8         time_to_plastic_image_start[0x20];
9522
9523	u8         time_to_iron_image_start[0x20];
9524
9525	u8         perst_handler[0x20];
9526
9527	u8         times_in_l1[0x20];
9528
9529	u8         times_in_l23[0x20];
9530
9531	u8         dl_down[0x20];
9532
9533	u8         config_cycle1usec[0x20];
9534
9535	u8         config_cycle2to7usec[0x20];
9536
9537	u8         config_cycle8to15usec[0x20];
9538
9539	u8         config_cycle16to63usec[0x20];
9540
9541	u8         config_cycle64usec[0x20];
9542
9543	u8         correctable_err_msg_sent[0x20];
9544
9545	u8         non_fatal_err_msg_sent[0x20];
9546
9547	u8         fatal_err_msg_sent[0x20];
9548
9549	u8         reserved_0[0x4e0];
9550};
9551
9552struct mlx5_ifc_pcie_lanes_counters_data_layout_bits {
9553	u8         life_time_counter_high[0x20];
9554
9555	u8         life_time_counter_low[0x20];
9556
9557	u8         error_counter_lane0[0x20];
9558
9559	u8         error_counter_lane1[0x20];
9560
9561	u8         error_counter_lane2[0x20];
9562
9563	u8         error_counter_lane3[0x20];
9564
9565	u8         error_counter_lane4[0x20];
9566
9567	u8         error_counter_lane5[0x20];
9568
9569	u8         error_counter_lane6[0x20];
9570
9571	u8         error_counter_lane7[0x20];
9572
9573	u8         error_counter_lane8[0x20];
9574
9575	u8         error_counter_lane9[0x20];
9576
9577	u8         error_counter_lane10[0x20];
9578
9579	u8         error_counter_lane11[0x20];
9580
9581	u8         error_counter_lane12[0x20];
9582
9583	u8         error_counter_lane13[0x20];
9584
9585	u8         error_counter_lane14[0x20];
9586
9587	u8         error_counter_lane15[0x20];
9588
9589	u8         reserved_0[0x580];
9590};
9591
9592union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits {
9593	struct mlx5_ifc_pcie_performance_counters_data_layout_bits pcie_performance_counters_data_layout;
9594	struct mlx5_ifc_pcie_timers_and_states_data_layout_bits pcie_timers_and_states_data_layout;
9595	struct mlx5_ifc_pcie_lanes_counters_data_layout_bits pcie_lanes_counters_data_layout;
9596	u8         reserved_0[0xf8];
9597};
9598
9599struct mlx5_ifc_mpcnt_reg_bits {
9600	u8         reserved_0[0x8];
9601	u8         pcie_index[0x8];
9602	u8         reserved_1[0xa];
9603	u8         grp[0x6];
9604
9605	u8         clr[0x1];
9606	u8         reserved_2[0x1f];
9607
9608	union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits counter_set;
9609};
9610
9611union mlx5_ifc_ports_control_registers_document_bits {
9612	struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data;
9613	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9614	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9615	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9616	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9617	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9618	struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
9619	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9620	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9621	struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout;
9622	struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout;
9623	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9624	struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date;
9625	struct mlx5_ifc_pamp_reg_bits pamp_reg;
9626	struct mlx5_ifc_paos_reg_bits paos_reg;
9627	struct mlx5_ifc_pbmc_reg_bits pbmc_reg;
9628	struct mlx5_ifc_pcap_reg_bits pcap_reg;
9629	struct mlx5_ifc_peir_reg_bits peir_reg;
9630	struct mlx5_ifc_pelc_reg_bits pelc_reg;
9631	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
9632	struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg;
9633	struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg;
9634	struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg;
9635	struct mlx5_ifc_phrr_reg_bits phrr_reg;
9636	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9637	struct mlx5_ifc_pifr_reg_bits pifr_reg;
9638	struct mlx5_ifc_pipg_reg_bits pipg_reg;
9639	struct mlx5_ifc_plbf_reg_bits plbf_reg;
9640	struct mlx5_ifc_plib_reg_bits plib_reg;
9641	struct mlx5_ifc_pll_status_data_bits pll_status_data;
9642	struct mlx5_ifc_plpc_reg_bits plpc_reg;
9643	struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9644	struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9645	struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9646	struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9647	struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9648	struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9649	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9650	struct mlx5_ifc_ppad_reg_bits ppad_reg;
9651	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
9652	struct mlx5_ifc_ppll_reg_bits ppll_reg;
9653	struct mlx5_ifc_pplm_reg_bits pplm_reg;
9654	struct mlx5_ifc_pplr_reg_bits pplr_reg;
9655	struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9656	struct mlx5_ifc_pspa_reg_bits pspa_reg;
9657	struct mlx5_ifc_ptas_reg_bits ptas_reg;
9658	struct mlx5_ifc_ptys_reg_bits ptys_reg;
9659	struct mlx5_ifc_pude_reg_bits pude_reg;
9660	struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9661	struct mlx5_ifc_slrg_reg_bits slrg_reg;
9662	struct mlx5_ifc_slrp_reg_bits slrp_reg;
9663	struct mlx5_ifc_sltp_reg_bits sltp_reg;
9664	u8         reserved_0[0x7880];
9665};
9666
9667union mlx5_ifc_debug_enhancements_document_bits {
9668	struct mlx5_ifc_health_buffer_bits health_buffer;
9669	u8         reserved_0[0x200];
9670};
9671
9672union mlx5_ifc_no_dram_nic_document_bits {
9673	struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg;
9674	struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word;
9675	struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word;
9676	struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters;
9677	struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters;
9678	struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg;
9679	struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg;
9680	struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell;
9681	u8         reserved_0[0x3160];
9682};
9683
9684union mlx5_ifc_uplink_pci_interface_document_bits {
9685	struct mlx5_ifc_initial_seg_bits initial_seg;
9686	struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap;
9687	u8         reserved_0[0x20120];
9688};
9689
9690
9691#endif /* MLX5_IFC_H */
9692