cmd.h revision 341966 
1/*-
2 * Copyright (c) 2017, Mellanox Technologies, Ltd.  All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses.  You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 *     Redistribution and use in source and binary forms, with or
11 *     without modification, are permitted provided that the following
12 *     conditions are met:
13 *
14 *      - Redistributions of source code must retain the above
15 *        copyright notice, this list of conditions and the following
16 *        disclaimer.
17 *
18 *      - Redistributions in binary form must reproduce the above
19 *        copyright notice, this list of conditions and the following
20 *        disclaimer in the documentation and/or other materials
21 *        provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_fpga/cmd.h 341966 2018-12-12 12:54:43Z hselasky $
33 */
34
35#ifndef __MLX5_FPGA_H__
36#define __MLX5_FPGA_H__
37
38#include <linux/in6.h>
39#include <dev/mlx5/driver.h>
40#include <dev/mlx5/mlx5io.h>
41
42enum mlx5_fpga_qpc_field_select {
43	MLX5_FPGA_QPC_STATE = BIT(0),
44};
45
46struct mlx5_fpga_qp_counters {
47	u64 rx_ack_packets;
48	u64 rx_send_packets;
49	u64 tx_ack_packets;
50	u64 tx_send_packets;
51	u64 rx_total_drop;
52};
53
54struct mlx5_fpga_shell_counters {
55	u64 ddr_read_requests;
56	u64 ddr_write_requests;
57	u64 ddr_read_bytes;
58	u64 ddr_write_bytes;
59};
60
61int mlx5_fpga_caps(struct mlx5_core_dev *dev);
62int mlx5_fpga_query(struct mlx5_core_dev *dev, struct mlx5_fpga_query *query);
63int mlx5_fpga_query_mtmp(struct mlx5_core_dev *dev,
64			 struct mlx5_fpga_temperature *temp);
65int mlx5_fpga_ctrl_op(struct mlx5_core_dev *dev, u8 op);
66int mlx5_fpga_access_reg(struct mlx5_core_dev *dev, u8 size, u64 addr,
67			 void *buf, bool write);
68int mlx5_fpga_sbu_caps(struct mlx5_core_dev *dev, void *caps, int size);
69int mlx5_fpga_load(struct mlx5_core_dev *dev, enum mlx5_fpga_image image);
70int mlx5_fpga_image_select(struct mlx5_core_dev *dev,
71			   enum mlx5_fpga_image image);
72int mlx5_fpga_ctrl_connect(struct mlx5_core_dev *dev,
73			   enum mlx5_fpga_connect *connect);
74int mlx5_fpga_shell_counters(struct mlx5_core_dev *dev, bool clear,
75			     struct mlx5_fpga_shell_counters *data);
76
77int mlx5_fpga_create_qp(struct mlx5_core_dev *dev, void *fpga_qpc,
78			u32 *fpga_qpn);
79int mlx5_fpga_modify_qp(struct mlx5_core_dev *dev, u32 fpga_qpn,
80			enum mlx5_fpga_qpc_field_select fields, void *fpga_qpc);
81int mlx5_fpga_query_qp(struct mlx5_core_dev *dev, u32 fpga_qpn, void *fpga_qpc);
82int mlx5_fpga_query_qp_counters(struct mlx5_core_dev *dev, u32 fpga_qpn,
83				bool clear, struct mlx5_fpga_qp_counters *data);
84int mlx5_fpga_destroy_qp(struct mlx5_core_dev *dev, u32 fpga_qpn);
85
86#endif /* __MLX5_FPGA_H__ */
87