1352981Shselasky/*- 2369094Shselasky * Copyright (c) 2018-2019 Mellanox Technologies. All rights reserved. 3352981Shselasky * 4352981Shselasky * Redistribution and use in source and binary forms, with or without 5352981Shselasky * modification, are permitted provided that the following conditions 6352981Shselasky * are met: 7352981Shselasky * 1. Redistributions of source code must retain the above copyright 8352981Shselasky * notice, this list of conditions and the following disclaimer. 9352981Shselasky * 2. Redistributions in binary form must reproduce the above copyright 10352981Shselasky * notice, this list of conditions and the following disclaimer in the 11352981Shselasky * documentation and/or other materials provided with the distribution. 12352981Shselasky * 13352981Shselasky * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14352981Shselasky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15352981Shselasky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16352981Shselasky * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17352981Shselasky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18352981Shselasky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19352981Shselasky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20352981Shselasky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21352981Shselasky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22352981Shselasky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23352981Shselasky * SUCH DAMAGE. 24352981Shselasky * 25352981Shselasky * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_en/port_buffer.h 369094 2021-01-22 12:49:45Z hselasky $ 26352981Shselasky */ 27352981Shselasky 28352981Shselasky#ifndef __MLX5_EN_PORT_BUFFER_H__ 29352981Shselasky#define __MLX5_EN_PORT_BUFFER_H__ 30352981Shselasky 31352981Shselasky#include "en.h" 32352981Shselasky#include <dev/mlx5/port.h> 33352981Shselasky 34352981Shselasky#define MLX5E_MAX_BUFFER 8 35352981Shselasky#define MLX5E_BUFFER_CELL_SHIFT 7 36352981Shselasky#define MLX5E_DEFAULT_CABLE_LEN 7 /* 7 meters */ 37352981Shselasky 38352981Shselasky#define MLX5_BUFFER_SUPPORTED(mdev) (MLX5_CAP_GEN(mdev, pcam_reg) && \ 39352981Shselasky MLX5_CAP_PCAM_REG(mdev, pbmc) && \ 40352981Shselasky MLX5_CAP_PCAM_REG(mdev, pptb)) 41352981Shselasky 42352981Shselaskyenum { 43352981Shselasky MLX5E_PORT_BUFFER_CABLE_LEN = BIT(0), 44352981Shselasky MLX5E_PORT_BUFFER_PFC = BIT(1), 45352981Shselasky MLX5E_PORT_BUFFER_PRIO2BUFFER = BIT(2), 46352981Shselasky MLX5E_PORT_BUFFER_SIZE = BIT(3), 47352981Shselasky}; 48352981Shselasky 49352981Shselaskystruct mlx5e_bufferx_reg { 50352981Shselasky u8 lossy; 51352981Shselasky u8 epsb; 52352981Shselasky u32 size; 53352981Shselasky u32 xoff; 54352981Shselasky u32 xon; 55352981Shselasky}; 56352981Shselasky 57352981Shselaskystruct mlx5e_port_buffer { 58352981Shselasky u32 port_buffer_size; 59352981Shselasky u32 spare_buffer_size; 60352981Shselasky struct mlx5e_bufferx_reg buffer[MLX5E_MAX_BUFFER]; 61352981Shselasky}; 62352981Shselasky 63352981Shselasky#define IEEE_8021QAZ_MAX_TCS 8 64352981Shselasky 65352981Shselaskystruct ieee_pfc { 66352981Shselasky __u8 pfc_cap; 67352981Shselasky __u8 pfc_en; 68352981Shselasky __u8 mbc; 69352981Shselasky __u16 delay; 70352981Shselasky __u64 requests[IEEE_8021QAZ_MAX_TCS]; 71352981Shselasky __u64 indications[IEEE_8021QAZ_MAX_TCS]; 72352981Shselasky}; 73352981Shselasky 74352981Shselaskyint mlx5e_port_manual_buffer_config(struct mlx5e_priv *priv, 75352981Shselasky u32 change, unsigned int mtu, 76352981Shselasky struct ieee_pfc *pfc, 77352981Shselasky u32 *buffer_size, 78352981Shselasky u8 *prio2buffer); 79352981Shselasky 80352981Shselaskyint mlx5e_port_query_buffer(struct mlx5e_priv *priv, 81352981Shselasky struct mlx5e_port_buffer *port_buffer); 82352981Shselasky#endif 83