mlx5_en_main.c revision 331575
1/*- 2 * Copyright (c) 2015 Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_en/mlx5_en_main.c 331575 2018-03-26 20:10:49Z hselasky $ 26 */ 27 28#include "en.h" 29 30#include <sys/sockio.h> 31#include <machine/atomic.h> 32 33#define ETH_DRIVER_VERSION "3.1.0-dev" 34char mlx5e_version[] = "Mellanox Ethernet driver" 35 " (" ETH_DRIVER_VERSION ")"; 36 37struct mlx5e_channel_param { 38 struct mlx5e_rq_param rq; 39 struct mlx5e_sq_param sq; 40 struct mlx5e_cq_param rx_cq; 41 struct mlx5e_cq_param tx_cq; 42}; 43 44static const struct { 45 u32 subtype; 46 u64 baudrate; 47} mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = { 48 49 [MLX5E_1000BASE_CX_SGMII] = { 50 .subtype = IFM_1000_CX_SGMII, 51 .baudrate = IF_Mbps(1000ULL), 52 }, 53 [MLX5E_1000BASE_KX] = { 54 .subtype = IFM_1000_KX, 55 .baudrate = IF_Mbps(1000ULL), 56 }, 57 [MLX5E_10GBASE_CX4] = { 58 .subtype = IFM_10G_CX4, 59 .baudrate = IF_Gbps(10ULL), 60 }, 61 [MLX5E_10GBASE_KX4] = { 62 .subtype = IFM_10G_KX4, 63 .baudrate = IF_Gbps(10ULL), 64 }, 65 [MLX5E_10GBASE_KR] = { 66 .subtype = IFM_10G_KR, 67 .baudrate = IF_Gbps(10ULL), 68 }, 69 [MLX5E_20GBASE_KR2] = { 70 .subtype = IFM_20G_KR2, 71 .baudrate = IF_Gbps(20ULL), 72 }, 73 [MLX5E_40GBASE_CR4] = { 74 .subtype = IFM_40G_CR4, 75 .baudrate = IF_Gbps(40ULL), 76 }, 77 [MLX5E_40GBASE_KR4] = { 78 .subtype = IFM_40G_KR4, 79 .baudrate = IF_Gbps(40ULL), 80 }, 81 [MLX5E_56GBASE_R4] = { 82 .subtype = IFM_56G_R4, 83 .baudrate = IF_Gbps(56ULL), 84 }, 85 [MLX5E_10GBASE_CR] = { 86 .subtype = IFM_10G_CR1, 87 .baudrate = IF_Gbps(10ULL), 88 }, 89 [MLX5E_10GBASE_SR] = { 90 .subtype = IFM_10G_SR, 91 .baudrate = IF_Gbps(10ULL), 92 }, 93 [MLX5E_10GBASE_LR] = { 94 .subtype = IFM_10G_LR, 95 .baudrate = IF_Gbps(10ULL), 96 }, 97 [MLX5E_40GBASE_SR4] = { 98 .subtype = IFM_40G_SR4, 99 .baudrate = IF_Gbps(40ULL), 100 }, 101 [MLX5E_40GBASE_LR4] = { 102 .subtype = IFM_40G_LR4, 103 .baudrate = IF_Gbps(40ULL), 104 }, 105 [MLX5E_100GBASE_CR4] = { 106 .subtype = IFM_100G_CR4, 107 .baudrate = IF_Gbps(100ULL), 108 }, 109 [MLX5E_100GBASE_SR4] = { 110 .subtype = IFM_100G_SR4, 111 .baudrate = IF_Gbps(100ULL), 112 }, 113 [MLX5E_100GBASE_KR4] = { 114 .subtype = IFM_100G_KR4, 115 .baudrate = IF_Gbps(100ULL), 116 }, 117 [MLX5E_100GBASE_LR4] = { 118 .subtype = IFM_100G_LR4, 119 .baudrate = IF_Gbps(100ULL), 120 }, 121 [MLX5E_100BASE_TX] = { 122 .subtype = IFM_100_TX, 123 .baudrate = IF_Mbps(100ULL), 124 }, 125 [MLX5E_100BASE_T] = { 126 .subtype = IFM_100_T, 127 .baudrate = IF_Mbps(100ULL), 128 }, 129 [MLX5E_10GBASE_T] = { 130 .subtype = IFM_10G_T, 131 .baudrate = IF_Gbps(10ULL), 132 }, 133 [MLX5E_25GBASE_CR] = { 134 .subtype = IFM_25G_CR, 135 .baudrate = IF_Gbps(25ULL), 136 }, 137 [MLX5E_25GBASE_KR] = { 138 .subtype = IFM_25G_KR, 139 .baudrate = IF_Gbps(25ULL), 140 }, 141 [MLX5E_25GBASE_SR] = { 142 .subtype = IFM_25G_SR, 143 .baudrate = IF_Gbps(25ULL), 144 }, 145 [MLX5E_50GBASE_CR2] = { 146 .subtype = IFM_50G_CR2, 147 .baudrate = IF_Gbps(50ULL), 148 }, 149 [MLX5E_50GBASE_KR2] = { 150 .subtype = IFM_50G_KR2, 151 .baudrate = IF_Gbps(50ULL), 152 }, 153}; 154 155MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet"); 156 157static void 158mlx5e_update_carrier(struct mlx5e_priv *priv) 159{ 160 struct mlx5_core_dev *mdev = priv->mdev; 161 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 162 u32 eth_proto_oper; 163 int error; 164 u8 port_state; 165 u8 i; 166 167 port_state = mlx5_query_vport_state(mdev, 168 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0); 169 170 if (port_state == VPORT_STATE_UP) { 171 priv->media_status_last |= IFM_ACTIVE; 172 } else { 173 priv->media_status_last &= ~IFM_ACTIVE; 174 priv->media_active_last = IFM_ETHER; 175 if_link_state_change(priv->ifp, LINK_STATE_DOWN); 176 return; 177 } 178 179 error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN); 180 if (error) { 181 priv->media_active_last = IFM_ETHER; 182 priv->ifp->if_baudrate = 1; 183 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n", 184 __func__, error); 185 return; 186 } 187 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper); 188 189 for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) { 190 if (mlx5e_mode_table[i].baudrate == 0) 191 continue; 192 if (MLX5E_PROT_MASK(i) & eth_proto_oper) { 193 priv->ifp->if_baudrate = 194 mlx5e_mode_table[i].baudrate; 195 priv->media_active_last = 196 mlx5e_mode_table[i].subtype | IFM_ETHER | IFM_FDX; 197 } 198 } 199 if_link_state_change(priv->ifp, LINK_STATE_UP); 200} 201 202static void 203mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr) 204{ 205 struct mlx5e_priv *priv = dev->if_softc; 206 207 ifmr->ifm_status = priv->media_status_last; 208 ifmr->ifm_active = priv->media_active_last | 209 (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) | 210 (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0); 211 212} 213 214static u32 215mlx5e_find_link_mode(u32 subtype) 216{ 217 u32 i; 218 u32 link_mode = 0; 219 220 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) { 221 if (mlx5e_mode_table[i].baudrate == 0) 222 continue; 223 if (mlx5e_mode_table[i].subtype == subtype) 224 link_mode |= MLX5E_PROT_MASK(i); 225 } 226 227 return (link_mode); 228} 229 230static int 231mlx5e_media_change(struct ifnet *dev) 232{ 233 struct mlx5e_priv *priv = dev->if_softc; 234 struct mlx5_core_dev *mdev = priv->mdev; 235 u32 eth_proto_cap; 236 u32 link_mode; 237 int was_opened; 238 int locked; 239 int error; 240 241 locked = PRIV_LOCKED(priv); 242 if (!locked) 243 PRIV_LOCK(priv); 244 245 if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) { 246 error = EINVAL; 247 goto done; 248 } 249 link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media)); 250 251 /* query supported capabilities */ 252 error = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN); 253 if (error != 0) { 254 if_printf(dev, "Query port media capability failed\n"); 255 goto done; 256 } 257 /* check for autoselect */ 258 if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) { 259 link_mode = eth_proto_cap; 260 if (link_mode == 0) { 261 if_printf(dev, "Port media capability is zero\n"); 262 error = EINVAL; 263 goto done; 264 } 265 } else { 266 link_mode = link_mode & eth_proto_cap; 267 if (link_mode == 0) { 268 if_printf(dev, "Not supported link mode requested\n"); 269 error = EINVAL; 270 goto done; 271 } 272 } 273 /* update pauseframe control bits */ 274 priv->params.rx_pauseframe_control = 275 (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0; 276 priv->params.tx_pauseframe_control = 277 (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0; 278 279 /* check if device is opened */ 280 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 281 282 /* reconfigure the hardware */ 283 mlx5_set_port_status(mdev, MLX5_PORT_DOWN); 284 mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN); 285 mlx5_set_port_pause(mdev, 1, 286 priv->params.rx_pauseframe_control, 287 priv->params.tx_pauseframe_control); 288 if (was_opened) 289 mlx5_set_port_status(mdev, MLX5_PORT_UP); 290 291done: 292 if (!locked) 293 PRIV_UNLOCK(priv); 294 return (error); 295} 296 297static void 298mlx5e_update_carrier_work(struct work_struct *work) 299{ 300 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 301 update_carrier_work); 302 303 PRIV_LOCK(priv); 304 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) 305 mlx5e_update_carrier(priv); 306 PRIV_UNLOCK(priv); 307} 308 309/* 310 * This function reads the physical port counters from the firmware 311 * using a pre-defined layout defined by various MLX5E_PPORT_XXX() 312 * macros. The output is converted from big-endian 64-bit values into 313 * host endian ones and stored in the "priv->stats.pport" structure. 314 */ 315static void 316mlx5e_update_pport_counters(struct mlx5e_priv *priv) 317{ 318 struct mlx5_core_dev *mdev = priv->mdev; 319 struct mlx5e_pport_stats *s = &priv->stats.pport; 320 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug; 321 u32 *in; 322 u32 *out; 323 const u64 *ptr; 324 unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 325 unsigned x; 326 unsigned y; 327 328 /* allocate firmware request structures */ 329 in = mlx5_vzalloc(sz); 330 out = mlx5_vzalloc(sz); 331 if (in == NULL || out == NULL) 332 goto free_out; 333 334 /* 335 * Get pointer to the 64-bit counter set which is located at a 336 * fixed offset in the output firmware request structure: 337 */ 338 ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set); 339 340 MLX5_SET(ppcnt_reg, in, local_port, 1); 341 342 /* read IEEE802_3 counter group using predefined counter layout */ 343 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP); 344 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 345 for (x = y = 0; x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++) 346 s->arg[y] = be64toh(ptr[x]); 347 348 /* read RFC2819 counter group using predefined counter layout */ 349 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP); 350 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 351 for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++) 352 s->arg[y] = be64toh(ptr[x]); 353 for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM + 354 MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++) 355 s_debug->arg[y] = be64toh(ptr[x]); 356 357 /* read RFC2863 counter group using predefined counter layout */ 358 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP); 359 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 360 for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++) 361 s_debug->arg[y] = be64toh(ptr[x]); 362 363 /* read physical layer stats counter group using predefined counter layout */ 364 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP); 365 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 366 for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++) 367 s_debug->arg[y] = be64toh(ptr[x]); 368free_out: 369 /* free firmware request structures */ 370 kvfree(in); 371 kvfree(out); 372} 373 374/* 375 * This function is called regularly to collect all statistics 376 * counters from the firmware. The values can be viewed through the 377 * sysctl interface. Execution is serialized using the priv's global 378 * configuration lock. 379 */ 380static void 381mlx5e_update_stats_work(struct work_struct *work) 382{ 383 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 384 update_stats_work); 385 struct mlx5_core_dev *mdev = priv->mdev; 386 struct mlx5e_vport_stats *s = &priv->stats.vport; 387 struct mlx5e_rq_stats *rq_stats; 388 struct mlx5e_sq_stats *sq_stats; 389 struct buf_ring *sq_br; 390#if (__FreeBSD_version < 1100000) 391 struct ifnet *ifp = priv->ifp; 392#endif 393 394 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)]; 395 u32 *out; 396 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out); 397 u64 tso_packets = 0; 398 u64 tso_bytes = 0; 399 u64 tx_queue_dropped = 0; 400 u64 tx_defragged = 0; 401 u64 tx_offload_none = 0; 402 u64 lro_packets = 0; 403 u64 lro_bytes = 0; 404 u64 sw_lro_queued = 0; 405 u64 sw_lro_flushed = 0; 406 u64 rx_csum_none = 0; 407 u64 rx_wqe_err = 0; 408 u32 rx_out_of_buffer = 0; 409 int i; 410 int j; 411 412 PRIV_LOCK(priv); 413 out = mlx5_vzalloc(outlen); 414 if (out == NULL) 415 goto free_out; 416 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 417 goto free_out; 418 419 /* Collect firts the SW counters and then HW for consistency */ 420 for (i = 0; i < priv->params.num_channels; i++) { 421 struct mlx5e_rq *rq = &priv->channel[i]->rq; 422 423 rq_stats = &priv->channel[i]->rq.stats; 424 425 /* collect stats from LRO */ 426 rq_stats->sw_lro_queued = rq->lro.lro_queued; 427 rq_stats->sw_lro_flushed = rq->lro.lro_flushed; 428 sw_lro_queued += rq_stats->sw_lro_queued; 429 sw_lro_flushed += rq_stats->sw_lro_flushed; 430 lro_packets += rq_stats->lro_packets; 431 lro_bytes += rq_stats->lro_bytes; 432 rx_csum_none += rq_stats->csum_none; 433 rx_wqe_err += rq_stats->wqe_err; 434 435 for (j = 0; j < priv->num_tc; j++) { 436 sq_stats = &priv->channel[i]->sq[j].stats; 437 sq_br = priv->channel[i]->sq[j].br; 438 439 tso_packets += sq_stats->tso_packets; 440 tso_bytes += sq_stats->tso_bytes; 441 tx_queue_dropped += sq_stats->dropped; 442 if (sq_br != NULL) 443 tx_queue_dropped += sq_br->br_drops; 444 tx_defragged += sq_stats->defragged; 445 tx_offload_none += sq_stats->csum_offload_none; 446 } 447 } 448 449 /* update counters */ 450 s->tso_packets = tso_packets; 451 s->tso_bytes = tso_bytes; 452 s->tx_queue_dropped = tx_queue_dropped; 453 s->tx_defragged = tx_defragged; 454 s->lro_packets = lro_packets; 455 s->lro_bytes = lro_bytes; 456 s->sw_lro_queued = sw_lro_queued; 457 s->sw_lro_flushed = sw_lro_flushed; 458 s->rx_csum_none = rx_csum_none; 459 s->rx_wqe_err = rx_wqe_err; 460 461 /* HW counters */ 462 memset(in, 0, sizeof(in)); 463 464 MLX5_SET(query_vport_counter_in, in, opcode, 465 MLX5_CMD_OP_QUERY_VPORT_COUNTER); 466 MLX5_SET(query_vport_counter_in, in, op_mod, 0); 467 MLX5_SET(query_vport_counter_in, in, other_vport, 0); 468 469 memset(out, 0, outlen); 470 471 /* get number of out-of-buffer drops first */ 472 if (mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id, 473 &rx_out_of_buffer)) 474 goto free_out; 475 476 /* accumulate difference into a 64-bit counter */ 477 s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer - s->rx_out_of_buffer_prev); 478 s->rx_out_of_buffer_prev = rx_out_of_buffer; 479 480 /* get port statistics */ 481 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen)) 482 goto free_out; 483 484#define MLX5_GET_CTR(out, x) \ 485 MLX5_GET64(query_vport_counter_out, out, x) 486 487 s->rx_error_packets = 488 MLX5_GET_CTR(out, received_errors.packets); 489 s->rx_error_bytes = 490 MLX5_GET_CTR(out, received_errors.octets); 491 s->tx_error_packets = 492 MLX5_GET_CTR(out, transmit_errors.packets); 493 s->tx_error_bytes = 494 MLX5_GET_CTR(out, transmit_errors.octets); 495 496 s->rx_unicast_packets = 497 MLX5_GET_CTR(out, received_eth_unicast.packets); 498 s->rx_unicast_bytes = 499 MLX5_GET_CTR(out, received_eth_unicast.octets); 500 s->tx_unicast_packets = 501 MLX5_GET_CTR(out, transmitted_eth_unicast.packets); 502 s->tx_unicast_bytes = 503 MLX5_GET_CTR(out, transmitted_eth_unicast.octets); 504 505 s->rx_multicast_packets = 506 MLX5_GET_CTR(out, received_eth_multicast.packets); 507 s->rx_multicast_bytes = 508 MLX5_GET_CTR(out, received_eth_multicast.octets); 509 s->tx_multicast_packets = 510 MLX5_GET_CTR(out, transmitted_eth_multicast.packets); 511 s->tx_multicast_bytes = 512 MLX5_GET_CTR(out, transmitted_eth_multicast.octets); 513 514 s->rx_broadcast_packets = 515 MLX5_GET_CTR(out, received_eth_broadcast.packets); 516 s->rx_broadcast_bytes = 517 MLX5_GET_CTR(out, received_eth_broadcast.octets); 518 s->tx_broadcast_packets = 519 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets); 520 s->tx_broadcast_bytes = 521 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets); 522 523 s->rx_packets = 524 s->rx_unicast_packets + 525 s->rx_multicast_packets + 526 s->rx_broadcast_packets - 527 s->rx_out_of_buffer; 528 s->rx_bytes = 529 s->rx_unicast_bytes + 530 s->rx_multicast_bytes + 531 s->rx_broadcast_bytes; 532 s->tx_packets = 533 s->tx_unicast_packets + 534 s->tx_multicast_packets + 535 s->tx_broadcast_packets; 536 s->tx_bytes = 537 s->tx_unicast_bytes + 538 s->tx_multicast_bytes + 539 s->tx_broadcast_bytes; 540 541 /* Update calculated offload counters */ 542 s->tx_csum_offload = s->tx_packets - tx_offload_none; 543 s->rx_csum_good = s->rx_packets - s->rx_csum_none; 544 545 /* Get physical port counters */ 546 mlx5e_update_pport_counters(priv); 547 548#if (__FreeBSD_version < 1100000) 549 /* no get_counters interface in fbsd 10 */ 550 ifp->if_ipackets = s->rx_packets; 551 ifp->if_ierrors = s->rx_error_packets + 552 priv->stats.pport.alignment_err + 553 priv->stats.pport.check_seq_err + 554 priv->stats.pport.crc_align_errors + 555 priv->stats.pport.in_range_len_errors + 556 priv->stats.pport.jabbers + 557 priv->stats.pport.out_of_range_len + 558 priv->stats.pport.oversize_pkts + 559 priv->stats.pport.symbol_err + 560 priv->stats.pport.too_long_errors + 561 priv->stats.pport.undersize_pkts + 562 priv->stats.pport.unsupported_op_rx; 563 ifp->if_iqdrops = s->rx_out_of_buffer + 564 priv->stats.pport.drop_events; 565 ifp->if_opackets = s->tx_packets; 566 ifp->if_oerrors = s->tx_error_packets; 567 ifp->if_snd.ifq_drops = s->tx_queue_dropped; 568 ifp->if_ibytes = s->rx_bytes; 569 ifp->if_obytes = s->tx_bytes; 570 ifp->if_collisions = 571 priv->stats.pport.collisions; 572#endif 573 574free_out: 575 kvfree(out); 576 577 /* Update diagnostics, if any */ 578 if (priv->params_ethtool.diag_pci_enable || 579 priv->params_ethtool.diag_general_enable) { 580 int error = mlx5_core_get_diagnostics_full(mdev, 581 priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL, 582 priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL); 583 if (error != 0) 584 if_printf(priv->ifp, "Failed reading diagnostics: %d\n", error); 585 } 586 PRIV_UNLOCK(priv); 587} 588 589static void 590mlx5e_update_stats(void *arg) 591{ 592 struct mlx5e_priv *priv = arg; 593 594 schedule_work(&priv->update_stats_work); 595 596 callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv); 597} 598 599static void 600mlx5e_async_event_sub(struct mlx5e_priv *priv, 601 enum mlx5_dev_event event) 602{ 603 switch (event) { 604 case MLX5_DEV_EVENT_PORT_UP: 605 case MLX5_DEV_EVENT_PORT_DOWN: 606 schedule_work(&priv->update_carrier_work); 607 break; 608 609 default: 610 break; 611 } 612} 613 614static void 615mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv, 616 enum mlx5_dev_event event, unsigned long param) 617{ 618 struct mlx5e_priv *priv = vpriv; 619 620 mtx_lock(&priv->async_events_mtx); 621 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state)) 622 mlx5e_async_event_sub(priv, event); 623 mtx_unlock(&priv->async_events_mtx); 624} 625 626static void 627mlx5e_enable_async_events(struct mlx5e_priv *priv) 628{ 629 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); 630} 631 632static void 633mlx5e_disable_async_events(struct mlx5e_priv *priv) 634{ 635 mtx_lock(&priv->async_events_mtx); 636 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); 637 mtx_unlock(&priv->async_events_mtx); 638} 639 640static const char *mlx5e_rq_stats_desc[] = { 641 MLX5E_RQ_STATS(MLX5E_STATS_DESC) 642}; 643 644static int 645mlx5e_create_rq(struct mlx5e_channel *c, 646 struct mlx5e_rq_param *param, 647 struct mlx5e_rq *rq) 648{ 649 struct mlx5e_priv *priv = c->priv; 650 struct mlx5_core_dev *mdev = priv->mdev; 651 char buffer[16]; 652 void *rqc = param->rqc; 653 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); 654 int wq_sz; 655 int err; 656 int i; 657 658 /* Create DMA descriptor TAG */ 659 if ((err = -bus_dma_tag_create( 660 bus_get_dma_tag(mdev->pdev->dev.bsddev), 661 1, /* any alignment */ 662 0, /* no boundary */ 663 BUS_SPACE_MAXADDR, /* lowaddr */ 664 BUS_SPACE_MAXADDR, /* highaddr */ 665 NULL, NULL, /* filter, filterarg */ 666 MJUM16BYTES, /* maxsize */ 667 1, /* nsegments */ 668 MJUM16BYTES, /* maxsegsize */ 669 0, /* flags */ 670 NULL, NULL, /* lockfunc, lockfuncarg */ 671 &rq->dma_tag))) 672 goto done; 673 674 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq, 675 &rq->wq_ctrl); 676 if (err) 677 goto err_free_dma_tag; 678 679 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR]; 680 681 if (priv->params.hw_lro_en) { 682 rq->wqe_sz = priv->params.lro_wqe_sz; 683 } else { 684 rq->wqe_sz = MLX5E_SW2MB_MTU(priv->ifp->if_mtu); 685 } 686 if (rq->wqe_sz > MJUM16BYTES) { 687 err = -ENOMEM; 688 goto err_rq_wq_destroy; 689 } else if (rq->wqe_sz > MJUM9BYTES) { 690 rq->wqe_sz = MJUM16BYTES; 691 } else if (rq->wqe_sz > MJUMPAGESIZE) { 692 rq->wqe_sz = MJUM9BYTES; 693 } else if (rq->wqe_sz > MCLBYTES) { 694 rq->wqe_sz = MJUMPAGESIZE; 695 } else { 696 rq->wqe_sz = MCLBYTES; 697 } 698 699 wq_sz = mlx5_wq_ll_get_size(&rq->wq); 700 701 err = -tcp_lro_init_args(&rq->lro, c->ifp, TCP_LRO_ENTRIES, wq_sz); 702 if (err) 703 goto err_rq_wq_destroy; 704 705 rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO); 706 for (i = 0; i != wq_sz; i++) { 707 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i); 708 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN; 709 710 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map); 711 if (err != 0) { 712 while (i--) 713 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map); 714 goto err_rq_mbuf_free; 715 } 716 wqe->data.lkey = c->mkey_be; 717 wqe->data.byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING); 718 } 719 720 rq->ifp = c->ifp; 721 rq->channel = c; 722 rq->ix = c->ix; 723 724 snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix); 725 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 726 buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM, 727 rq->stats.arg); 728 return (0); 729 730err_rq_mbuf_free: 731 free(rq->mbuf, M_MLX5EN); 732 tcp_lro_free(&rq->lro); 733err_rq_wq_destroy: 734 mlx5_wq_destroy(&rq->wq_ctrl); 735err_free_dma_tag: 736 bus_dma_tag_destroy(rq->dma_tag); 737done: 738 return (err); 739} 740 741static void 742mlx5e_destroy_rq(struct mlx5e_rq *rq) 743{ 744 int wq_sz; 745 int i; 746 747 /* destroy all sysctl nodes */ 748 sysctl_ctx_free(&rq->stats.ctx); 749 750 /* free leftover LRO packets, if any */ 751 tcp_lro_free(&rq->lro); 752 753 wq_sz = mlx5_wq_ll_get_size(&rq->wq); 754 for (i = 0; i != wq_sz; i++) { 755 if (rq->mbuf[i].mbuf != NULL) { 756 bus_dmamap_unload(rq->dma_tag, 757 rq->mbuf[i].dma_map); 758 m_freem(rq->mbuf[i].mbuf); 759 } 760 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map); 761 } 762 free(rq->mbuf, M_MLX5EN); 763 mlx5_wq_destroy(&rq->wq_ctrl); 764} 765 766static int 767mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param) 768{ 769 struct mlx5e_channel *c = rq->channel; 770 struct mlx5e_priv *priv = c->priv; 771 struct mlx5_core_dev *mdev = priv->mdev; 772 773 void *in; 774 void *rqc; 775 void *wq; 776 int inlen; 777 int err; 778 779 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + 780 sizeof(u64) * rq->wq_ctrl.buf.npages; 781 in = mlx5_vzalloc(inlen); 782 if (in == NULL) 783 return (-ENOMEM); 784 785 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 786 wq = MLX5_ADDR_OF(rqc, rqc, wq); 787 788 memcpy(rqc, param->rqc, sizeof(param->rqc)); 789 790 MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn); 791 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 792 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 793 if (priv->counter_set_id >= 0) 794 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id); 795 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift - 796 PAGE_SHIFT); 797 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma); 798 799 mlx5_fill_page_array(&rq->wq_ctrl.buf, 800 (__be64 *) MLX5_ADDR_OF(wq, wq, pas)); 801 802 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn); 803 804 kvfree(in); 805 806 return (err); 807} 808 809static int 810mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state) 811{ 812 struct mlx5e_channel *c = rq->channel; 813 struct mlx5e_priv *priv = c->priv; 814 struct mlx5_core_dev *mdev = priv->mdev; 815 816 void *in; 817 void *rqc; 818 int inlen; 819 int err; 820 821 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 822 in = mlx5_vzalloc(inlen); 823 if (in == NULL) 824 return (-ENOMEM); 825 826 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 827 828 MLX5_SET(modify_rq_in, in, rqn, rq->rqn); 829 MLX5_SET(modify_rq_in, in, rq_state, curr_state); 830 MLX5_SET(rqc, rqc, state, next_state); 831 832 err = mlx5_core_modify_rq(mdev, in, inlen); 833 834 kvfree(in); 835 836 return (err); 837} 838 839static void 840mlx5e_disable_rq(struct mlx5e_rq *rq) 841{ 842 struct mlx5e_channel *c = rq->channel; 843 struct mlx5e_priv *priv = c->priv; 844 struct mlx5_core_dev *mdev = priv->mdev; 845 846 mlx5_core_destroy_rq(mdev, rq->rqn); 847} 848 849static int 850mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq) 851{ 852 struct mlx5e_channel *c = rq->channel; 853 struct mlx5e_priv *priv = c->priv; 854 struct mlx5_wq_ll *wq = &rq->wq; 855 int i; 856 857 for (i = 0; i < 1000; i++) { 858 if (wq->cur_sz >= priv->params.min_rx_wqes) 859 return (0); 860 861 msleep(4); 862 } 863 return (-ETIMEDOUT); 864} 865 866static int 867mlx5e_open_rq(struct mlx5e_channel *c, 868 struct mlx5e_rq_param *param, 869 struct mlx5e_rq *rq) 870{ 871 int err; 872 873 err = mlx5e_create_rq(c, param, rq); 874 if (err) 875 return (err); 876 877 err = mlx5e_enable_rq(rq, param); 878 if (err) 879 goto err_destroy_rq; 880 881 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 882 if (err) 883 goto err_disable_rq; 884 885 c->rq.enabled = 1; 886 887 return (0); 888 889err_disable_rq: 890 mlx5e_disable_rq(rq); 891err_destroy_rq: 892 mlx5e_destroy_rq(rq); 893 894 return (err); 895} 896 897static void 898mlx5e_close_rq(struct mlx5e_rq *rq) 899{ 900 mtx_lock(&rq->mtx); 901 rq->enabled = 0; 902 callout_stop(&rq->watchdog); 903 mtx_unlock(&rq->mtx); 904 905 callout_drain(&rq->watchdog); 906 907 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 908} 909 910static void 911mlx5e_close_rq_wait(struct mlx5e_rq *rq) 912{ 913 /* wait till RQ is empty */ 914 while (!mlx5_wq_ll_is_empty(&rq->wq)) { 915 msleep(4); 916 rq->cq.mcq.comp(&rq->cq.mcq); 917 } 918 919 mlx5e_disable_rq(rq); 920 mlx5e_destroy_rq(rq); 921} 922 923void 924mlx5e_free_sq_db(struct mlx5e_sq *sq) 925{ 926 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 927 int x; 928 929 for (x = 0; x != wq_sz; x++) 930 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map); 931 free(sq->mbuf, M_MLX5EN); 932} 933 934int 935mlx5e_alloc_sq_db(struct mlx5e_sq *sq) 936{ 937 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 938 int err; 939 int x; 940 941 sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO); 942 943 /* Create DMA descriptor MAPs */ 944 for (x = 0; x != wq_sz; x++) { 945 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map); 946 if (err != 0) { 947 while (x--) 948 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map); 949 free(sq->mbuf, M_MLX5EN); 950 return (err); 951 } 952 } 953 return (0); 954} 955 956static const char *mlx5e_sq_stats_desc[] = { 957 MLX5E_SQ_STATS(MLX5E_STATS_DESC) 958}; 959 960static int 961mlx5e_create_sq(struct mlx5e_channel *c, 962 int tc, 963 struct mlx5e_sq_param *param, 964 struct mlx5e_sq *sq) 965{ 966 struct mlx5e_priv *priv = c->priv; 967 struct mlx5_core_dev *mdev = priv->mdev; 968 char buffer[16]; 969 970 void *sqc = param->sqc; 971 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq); 972#ifdef RSS 973 cpuset_t cpu_mask; 974 int cpu_id; 975#endif 976 int err; 977 978 /* Create DMA descriptor TAG */ 979 if ((err = -bus_dma_tag_create( 980 bus_get_dma_tag(mdev->pdev->dev.bsddev), 981 1, /* any alignment */ 982 0, /* no boundary */ 983 BUS_SPACE_MAXADDR, /* lowaddr */ 984 BUS_SPACE_MAXADDR, /* highaddr */ 985 NULL, NULL, /* filter, filterarg */ 986 MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */ 987 MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */ 988 MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */ 989 0, /* flags */ 990 NULL, NULL, /* lockfunc, lockfuncarg */ 991 &sq->dma_tag))) 992 goto done; 993 994 err = mlx5_alloc_map_uar(mdev, &sq->uar); 995 if (err) 996 goto err_free_dma_tag; 997 998 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, 999 &sq->wq_ctrl); 1000 if (err) 1001 goto err_unmap_free_uar; 1002 1003 sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; 1004 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2; 1005 1006 err = mlx5e_alloc_sq_db(sq); 1007 if (err) 1008 goto err_sq_wq_destroy; 1009 1010 sq->mkey_be = c->mkey_be; 1011 sq->ifp = priv->ifp; 1012 sq->priv = priv; 1013 sq->tc = tc; 1014 1015 /* check if we should allocate a second packet buffer */ 1016 if (priv->params_ethtool.tx_bufring_disable == 0) { 1017 sq->br = buf_ring_alloc(MLX5E_SQ_TX_QUEUE_SIZE, M_MLX5EN, 1018 M_WAITOK, &sq->lock); 1019 if (sq->br == NULL) { 1020 if_printf(c->ifp, "%s: Failed allocating sq drbr buffer\n", 1021 __func__); 1022 err = -ENOMEM; 1023 goto err_free_sq_db; 1024 } 1025 1026 sq->sq_tq = taskqueue_create_fast("mlx5e_que", M_WAITOK, 1027 taskqueue_thread_enqueue, &sq->sq_tq); 1028 if (sq->sq_tq == NULL) { 1029 if_printf(c->ifp, "%s: Failed allocating taskqueue\n", 1030 __func__); 1031 err = -ENOMEM; 1032 goto err_free_drbr; 1033 } 1034 1035 TASK_INIT(&sq->sq_task, 0, mlx5e_tx_que, sq); 1036#ifdef RSS 1037 cpu_id = rss_getcpu(c->ix % rss_getnumbuckets()); 1038 CPU_SETOF(cpu_id, &cpu_mask); 1039 taskqueue_start_threads_cpuset(&sq->sq_tq, 1, PI_NET, &cpu_mask, 1040 "%s TX SQ%d.%d CPU%d", c->ifp->if_xname, c->ix, tc, cpu_id); 1041#else 1042 taskqueue_start_threads(&sq->sq_tq, 1, PI_NET, 1043 "%s TX SQ%d.%d", c->ifp->if_xname, c->ix, tc); 1044#endif 1045 } 1046 snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc); 1047 mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 1048 buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM, 1049 sq->stats.arg); 1050 1051 return (0); 1052 1053err_free_drbr: 1054 buf_ring_free(sq->br, M_MLX5EN); 1055err_free_sq_db: 1056 mlx5e_free_sq_db(sq); 1057err_sq_wq_destroy: 1058 mlx5_wq_destroy(&sq->wq_ctrl); 1059 1060err_unmap_free_uar: 1061 mlx5_unmap_free_uar(mdev, &sq->uar); 1062 1063err_free_dma_tag: 1064 bus_dma_tag_destroy(sq->dma_tag); 1065done: 1066 return (err); 1067} 1068 1069static void 1070mlx5e_destroy_sq(struct mlx5e_sq *sq) 1071{ 1072 /* destroy all sysctl nodes */ 1073 sysctl_ctx_free(&sq->stats.ctx); 1074 1075 mlx5e_free_sq_db(sq); 1076 mlx5_wq_destroy(&sq->wq_ctrl); 1077 mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar); 1078 if (sq->sq_tq != NULL) { 1079 taskqueue_drain(sq->sq_tq, &sq->sq_task); 1080 taskqueue_free(sq->sq_tq); 1081 } 1082 if (sq->br != NULL) 1083 buf_ring_free(sq->br, M_MLX5EN); 1084} 1085 1086int 1087mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param, 1088 int tis_num) 1089{ 1090 void *in; 1091 void *sqc; 1092 void *wq; 1093 int inlen; 1094 int err; 1095 1096 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + 1097 sizeof(u64) * sq->wq_ctrl.buf.npages; 1098 in = mlx5_vzalloc(inlen); 1099 if (in == NULL) 1100 return (-ENOMEM); 1101 1102 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1103 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1104 1105 memcpy(sqc, param->sqc, sizeof(param->sqc)); 1106 1107 MLX5_SET(sqc, sqc, tis_num_0, tis_num); 1108 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn); 1109 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1110 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1111 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1112 1113 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1114 MLX5_SET(wq, wq, uar_page, sq->uar.index); 1115 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift - 1116 PAGE_SHIFT); 1117 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma); 1118 1119 mlx5_fill_page_array(&sq->wq_ctrl.buf, 1120 (__be64 *) MLX5_ADDR_OF(wq, wq, pas)); 1121 1122 err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn); 1123 1124 kvfree(in); 1125 1126 return (err); 1127} 1128 1129int 1130mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state) 1131{ 1132 void *in; 1133 void *sqc; 1134 int inlen; 1135 int err; 1136 1137 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 1138 in = mlx5_vzalloc(inlen); 1139 if (in == NULL) 1140 return (-ENOMEM); 1141 1142 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1143 1144 MLX5_SET(modify_sq_in, in, sqn, sq->sqn); 1145 MLX5_SET(modify_sq_in, in, sq_state, curr_state); 1146 MLX5_SET(sqc, sqc, state, next_state); 1147 1148 err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen); 1149 1150 kvfree(in); 1151 1152 return (err); 1153} 1154 1155void 1156mlx5e_disable_sq(struct mlx5e_sq *sq) 1157{ 1158 1159 mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn); 1160} 1161 1162static int 1163mlx5e_open_sq(struct mlx5e_channel *c, 1164 int tc, 1165 struct mlx5e_sq_param *param, 1166 struct mlx5e_sq *sq) 1167{ 1168 int err; 1169 1170 err = mlx5e_create_sq(c, tc, param, sq); 1171 if (err) 1172 return (err); 1173 1174 err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]); 1175 if (err) 1176 goto err_destroy_sq; 1177 1178 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY); 1179 if (err) 1180 goto err_disable_sq; 1181 1182 atomic_store_rel_int(&sq->queue_state, MLX5E_SQ_READY); 1183 1184 return (0); 1185 1186err_disable_sq: 1187 mlx5e_disable_sq(sq); 1188err_destroy_sq: 1189 mlx5e_destroy_sq(sq); 1190 1191 return (err); 1192} 1193 1194static void 1195mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep) 1196{ 1197 /* fill up remainder with NOPs */ 1198 while (sq->cev_counter != 0) { 1199 while (!mlx5e_sq_has_room_for(sq, 1)) { 1200 if (can_sleep != 0) { 1201 mtx_unlock(&sq->lock); 1202 msleep(4); 1203 mtx_lock(&sq->lock); 1204 } else { 1205 goto done; 1206 } 1207 } 1208 /* send a single NOP */ 1209 mlx5e_send_nop(sq, 1); 1210 wmb(); 1211 } 1212done: 1213 /* Check if we need to write the doorbell */ 1214 if (likely(sq->doorbell.d64 != 0)) { 1215 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0); 1216 sq->doorbell.d64 = 0; 1217 } 1218} 1219 1220void 1221mlx5e_sq_cev_timeout(void *arg) 1222{ 1223 struct mlx5e_sq *sq = arg; 1224 1225 mtx_assert(&sq->lock, MA_OWNED); 1226 1227 /* check next state */ 1228 switch (sq->cev_next_state) { 1229 case MLX5E_CEV_STATE_SEND_NOPS: 1230 /* fill TX ring with NOPs, if any */ 1231 mlx5e_sq_send_nops_locked(sq, 0); 1232 1233 /* check if completed */ 1234 if (sq->cev_counter == 0) { 1235 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL; 1236 return; 1237 } 1238 break; 1239 default: 1240 /* send NOPs on next timeout */ 1241 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS; 1242 break; 1243 } 1244 1245 /* restart timer */ 1246 callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq); 1247} 1248 1249void 1250mlx5e_drain_sq(struct mlx5e_sq *sq) 1251{ 1252 int error; 1253 1254 /* 1255 * Check if already stopped. 1256 * 1257 * NOTE: The "stopped" variable is only written when both the 1258 * priv's configuration lock and the SQ's lock is locked. It 1259 * can therefore safely be read when only one of the two locks 1260 * is locked. This function is always called when the priv's 1261 * configuration lock is locked. 1262 */ 1263 if (sq->stopped != 0) 1264 return; 1265 1266 mtx_lock(&sq->lock); 1267 1268 /* don't put more packets into the SQ */ 1269 sq->stopped = 1; 1270 1271 /* teardown event factor timer, if any */ 1272 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS; 1273 callout_stop(&sq->cev_callout); 1274 1275 /* send dummy NOPs in order to flush the transmit ring */ 1276 mlx5e_sq_send_nops_locked(sq, 1); 1277 mtx_unlock(&sq->lock); 1278 1279 /* make sure it is safe to free the callout */ 1280 callout_drain(&sq->cev_callout); 1281 1282 /* wait till SQ is empty or link is down */ 1283 mtx_lock(&sq->lock); 1284 while (sq->cc != sq->pc && 1285 (sq->priv->media_status_last & IFM_ACTIVE) != 0) { 1286 mtx_unlock(&sq->lock); 1287 msleep(1); 1288 sq->cq.mcq.comp(&sq->cq.mcq); 1289 mtx_lock(&sq->lock); 1290 } 1291 mtx_unlock(&sq->lock); 1292 1293 /* error out remaining requests */ 1294 error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR); 1295 if (error != 0) { 1296 if_printf(sq->ifp, 1297 "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error); 1298 } 1299 1300 /* wait till SQ is empty */ 1301 mtx_lock(&sq->lock); 1302 while (sq->cc != sq->pc) { 1303 mtx_unlock(&sq->lock); 1304 msleep(1); 1305 sq->cq.mcq.comp(&sq->cq.mcq); 1306 mtx_lock(&sq->lock); 1307 } 1308 mtx_unlock(&sq->lock); 1309} 1310 1311static void 1312mlx5e_close_sq_wait(struct mlx5e_sq *sq) 1313{ 1314 1315 mlx5e_drain_sq(sq); 1316 mlx5e_disable_sq(sq); 1317 mlx5e_destroy_sq(sq); 1318} 1319 1320static int 1321mlx5e_create_cq(struct mlx5e_priv *priv, 1322 struct mlx5e_cq_param *param, 1323 struct mlx5e_cq *cq, 1324 mlx5e_cq_comp_t *comp, 1325 int eq_ix) 1326{ 1327 struct mlx5_core_dev *mdev = priv->mdev; 1328 struct mlx5_core_cq *mcq = &cq->mcq; 1329 int eqn_not_used; 1330 int irqn; 1331 int err; 1332 u32 i; 1333 1334 param->wq.buf_numa_node = 0; 1335 param->wq.db_numa_node = 0; 1336 1337 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, 1338 &cq->wq_ctrl); 1339 if (err) 1340 return (err); 1341 1342 mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn); 1343 1344 mcq->cqe_sz = 64; 1345 mcq->set_ci_db = cq->wq_ctrl.db.db; 1346 mcq->arm_db = cq->wq_ctrl.db.db + 1; 1347 *mcq->set_ci_db = 0; 1348 *mcq->arm_db = 0; 1349 mcq->vector = eq_ix; 1350 mcq->comp = comp; 1351 mcq->event = mlx5e_cq_error_event; 1352 mcq->irqn = irqn; 1353 mcq->uar = &priv->cq_uar; 1354 1355 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { 1356 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); 1357 1358 cqe->op_own = 0xf1; 1359 } 1360 1361 cq->priv = priv; 1362 1363 return (0); 1364} 1365 1366static void 1367mlx5e_destroy_cq(struct mlx5e_cq *cq) 1368{ 1369 mlx5_wq_destroy(&cq->wq_ctrl); 1370} 1371 1372static int 1373mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix) 1374{ 1375 struct mlx5_core_cq *mcq = &cq->mcq; 1376 void *in; 1377 void *cqc; 1378 int inlen; 1379 int irqn_not_used; 1380 int eqn; 1381 int err; 1382 1383 inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 1384 sizeof(u64) * cq->wq_ctrl.buf.npages; 1385 in = mlx5_vzalloc(inlen); 1386 if (in == NULL) 1387 return (-ENOMEM); 1388 1389 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1390 1391 memcpy(cqc, param->cqc, sizeof(param->cqc)); 1392 1393 mlx5_fill_page_array(&cq->wq_ctrl.buf, 1394 (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas)); 1395 1396 mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used); 1397 1398 MLX5_SET(cqc, cqc, c_eqn, eqn); 1399 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index); 1400 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - 1401 PAGE_SHIFT); 1402 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); 1403 1404 err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen); 1405 1406 kvfree(in); 1407 1408 if (err) 1409 return (err); 1410 1411 mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock)); 1412 1413 return (0); 1414} 1415 1416static void 1417mlx5e_disable_cq(struct mlx5e_cq *cq) 1418{ 1419 1420 mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq); 1421} 1422 1423int 1424mlx5e_open_cq(struct mlx5e_priv *priv, 1425 struct mlx5e_cq_param *param, 1426 struct mlx5e_cq *cq, 1427 mlx5e_cq_comp_t *comp, 1428 int eq_ix) 1429{ 1430 int err; 1431 1432 err = mlx5e_create_cq(priv, param, cq, comp, eq_ix); 1433 if (err) 1434 return (err); 1435 1436 err = mlx5e_enable_cq(cq, param, eq_ix); 1437 if (err) 1438 goto err_destroy_cq; 1439 1440 return (0); 1441 1442err_destroy_cq: 1443 mlx5e_destroy_cq(cq); 1444 1445 return (err); 1446} 1447 1448void 1449mlx5e_close_cq(struct mlx5e_cq *cq) 1450{ 1451 mlx5e_disable_cq(cq); 1452 mlx5e_destroy_cq(cq); 1453} 1454 1455static int 1456mlx5e_open_tx_cqs(struct mlx5e_channel *c, 1457 struct mlx5e_channel_param *cparam) 1458{ 1459 int err; 1460 int tc; 1461 1462 for (tc = 0; tc < c->num_tc; tc++) { 1463 /* open completion queue */ 1464 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq, 1465 &mlx5e_tx_cq_comp, c->ix); 1466 if (err) 1467 goto err_close_tx_cqs; 1468 } 1469 return (0); 1470 1471err_close_tx_cqs: 1472 for (tc--; tc >= 0; tc--) 1473 mlx5e_close_cq(&c->sq[tc].cq); 1474 1475 return (err); 1476} 1477 1478static void 1479mlx5e_close_tx_cqs(struct mlx5e_channel *c) 1480{ 1481 int tc; 1482 1483 for (tc = 0; tc < c->num_tc; tc++) 1484 mlx5e_close_cq(&c->sq[tc].cq); 1485} 1486 1487static int 1488mlx5e_open_sqs(struct mlx5e_channel *c, 1489 struct mlx5e_channel_param *cparam) 1490{ 1491 int err; 1492 int tc; 1493 1494 for (tc = 0; tc < c->num_tc; tc++) { 1495 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]); 1496 if (err) 1497 goto err_close_sqs; 1498 } 1499 1500 return (0); 1501 1502err_close_sqs: 1503 for (tc--; tc >= 0; tc--) 1504 mlx5e_close_sq_wait(&c->sq[tc]); 1505 1506 return (err); 1507} 1508 1509static void 1510mlx5e_close_sqs_wait(struct mlx5e_channel *c) 1511{ 1512 int tc; 1513 1514 for (tc = 0; tc < c->num_tc; tc++) 1515 mlx5e_close_sq_wait(&c->sq[tc]); 1516} 1517 1518static void 1519mlx5e_chan_mtx_init(struct mlx5e_channel *c) 1520{ 1521 int tc; 1522 1523 mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF); 1524 1525 callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0); 1526 1527 for (tc = 0; tc < c->num_tc; tc++) { 1528 struct mlx5e_sq *sq = c->sq + tc; 1529 1530 mtx_init(&sq->lock, "mlx5tx", 1531 MTX_NETWORK_LOCK " TX", MTX_DEF); 1532 mtx_init(&sq->comp_lock, "mlx5comp", 1533 MTX_NETWORK_LOCK " TX", MTX_DEF); 1534 1535 callout_init_mtx(&sq->cev_callout, &sq->lock, 0); 1536 1537 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact; 1538 1539 /* ensure the TX completion event factor is not zero */ 1540 if (sq->cev_factor == 0) 1541 sq->cev_factor = 1; 1542 } 1543} 1544 1545static void 1546mlx5e_chan_mtx_destroy(struct mlx5e_channel *c) 1547{ 1548 int tc; 1549 1550 mtx_destroy(&c->rq.mtx); 1551 1552 for (tc = 0; tc < c->num_tc; tc++) { 1553 mtx_destroy(&c->sq[tc].lock); 1554 mtx_destroy(&c->sq[tc].comp_lock); 1555 } 1556} 1557 1558static int 1559mlx5e_open_channel(struct mlx5e_priv *priv, int ix, 1560 struct mlx5e_channel_param *cparam, 1561 struct mlx5e_channel *volatile *cp) 1562{ 1563 struct mlx5e_channel *c; 1564 int err; 1565 1566 c = malloc(sizeof(*c), M_MLX5EN, M_WAITOK | M_ZERO); 1567 c->priv = priv; 1568 c->ix = ix; 1569 c->cpu = 0; 1570 c->ifp = priv->ifp; 1571 c->mkey_be = cpu_to_be32(priv->mr.key); 1572 c->num_tc = priv->num_tc; 1573 1574 /* init mutexes */ 1575 mlx5e_chan_mtx_init(c); 1576 1577 /* open transmit completion queue */ 1578 err = mlx5e_open_tx_cqs(c, cparam); 1579 if (err) 1580 goto err_free; 1581 1582 /* open receive completion queue */ 1583 err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq, 1584 &mlx5e_rx_cq_comp, c->ix); 1585 if (err) 1586 goto err_close_tx_cqs; 1587 1588 err = mlx5e_open_sqs(c, cparam); 1589 if (err) 1590 goto err_close_rx_cq; 1591 1592 err = mlx5e_open_rq(c, &cparam->rq, &c->rq); 1593 if (err) 1594 goto err_close_sqs; 1595 1596 /* store channel pointer */ 1597 *cp = c; 1598 1599 /* poll receive queue initially */ 1600 c->rq.cq.mcq.comp(&c->rq.cq.mcq); 1601 1602 return (0); 1603 1604err_close_sqs: 1605 mlx5e_close_sqs_wait(c); 1606 1607err_close_rx_cq: 1608 mlx5e_close_cq(&c->rq.cq); 1609 1610err_close_tx_cqs: 1611 mlx5e_close_tx_cqs(c); 1612 1613err_free: 1614 /* destroy mutexes */ 1615 mlx5e_chan_mtx_destroy(c); 1616 free(c, M_MLX5EN); 1617 return (err); 1618} 1619 1620static void 1621mlx5e_close_channel(struct mlx5e_channel *volatile *pp) 1622{ 1623 struct mlx5e_channel *c = *pp; 1624 1625 /* check if channel is already closed */ 1626 if (c == NULL) 1627 return; 1628 mlx5e_close_rq(&c->rq); 1629} 1630 1631static void 1632mlx5e_close_channel_wait(struct mlx5e_channel *volatile *pp) 1633{ 1634 struct mlx5e_channel *c = *pp; 1635 1636 /* check if channel is already closed */ 1637 if (c == NULL) 1638 return; 1639 /* ensure channel pointer is no longer used */ 1640 *pp = NULL; 1641 1642 mlx5e_close_rq_wait(&c->rq); 1643 mlx5e_close_sqs_wait(c); 1644 mlx5e_close_cq(&c->rq.cq); 1645 mlx5e_close_tx_cqs(c); 1646 /* destroy mutexes */ 1647 mlx5e_chan_mtx_destroy(c); 1648 free(c, M_MLX5EN); 1649} 1650 1651static void 1652mlx5e_build_rq_param(struct mlx5e_priv *priv, 1653 struct mlx5e_rq_param *param) 1654{ 1655 void *rqc = param->rqc; 1656 void *wq = MLX5_ADDR_OF(rqc, rqc, wq); 1657 1658 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); 1659 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1660 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe))); 1661 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size); 1662 MLX5_SET(wq, wq, pd, priv->pdn); 1663 1664 param->wq.buf_numa_node = 0; 1665 param->wq.db_numa_node = 0; 1666 param->wq.linear = 1; 1667} 1668 1669static void 1670mlx5e_build_sq_param(struct mlx5e_priv *priv, 1671 struct mlx5e_sq_param *param) 1672{ 1673 void *sqc = param->sqc; 1674 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 1675 1676 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size); 1677 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1678 MLX5_SET(wq, wq, pd, priv->pdn); 1679 1680 param->wq.buf_numa_node = 0; 1681 param->wq.db_numa_node = 0; 1682 param->wq.linear = 1; 1683} 1684 1685static void 1686mlx5e_build_common_cq_param(struct mlx5e_priv *priv, 1687 struct mlx5e_cq_param *param) 1688{ 1689 void *cqc = param->cqc; 1690 1691 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index); 1692} 1693 1694static void 1695mlx5e_build_rx_cq_param(struct mlx5e_priv *priv, 1696 struct mlx5e_cq_param *param) 1697{ 1698 void *cqc = param->cqc; 1699 1700 1701 /* 1702 * TODO The sysctl to control on/off is a bool value for now, which means 1703 * we only support CSUM, once HASH is implemnted we'll need to address that. 1704 */ 1705 if (priv->params.cqe_zipping_en) { 1706 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM); 1707 MLX5_SET(cqc, cqc, cqe_compression_en, 1); 1708 } 1709 1710 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size); 1711 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec); 1712 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts); 1713 1714 switch (priv->params.rx_cq_moderation_mode) { 1715 case 0: 1716 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 1717 break; 1718 default: 1719 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 1720 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 1721 else 1722 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 1723 break; 1724 } 1725 1726 mlx5e_build_common_cq_param(priv, param); 1727} 1728 1729static void 1730mlx5e_build_tx_cq_param(struct mlx5e_priv *priv, 1731 struct mlx5e_cq_param *param) 1732{ 1733 void *cqc = param->cqc; 1734 1735 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size); 1736 MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec); 1737 MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts); 1738 1739 switch (priv->params.tx_cq_moderation_mode) { 1740 case 0: 1741 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 1742 break; 1743 default: 1744 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 1745 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 1746 else 1747 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 1748 break; 1749 } 1750 1751 mlx5e_build_common_cq_param(priv, param); 1752} 1753 1754static void 1755mlx5e_build_channel_param(struct mlx5e_priv *priv, 1756 struct mlx5e_channel_param *cparam) 1757{ 1758 memset(cparam, 0, sizeof(*cparam)); 1759 1760 mlx5e_build_rq_param(priv, &cparam->rq); 1761 mlx5e_build_sq_param(priv, &cparam->sq); 1762 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq); 1763 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq); 1764} 1765 1766static int 1767mlx5e_open_channels(struct mlx5e_priv *priv) 1768{ 1769 struct mlx5e_channel_param cparam; 1770 void *ptr; 1771 int err; 1772 int i; 1773 int j; 1774 1775 priv->channel = malloc(priv->params.num_channels * 1776 sizeof(struct mlx5e_channel *), M_MLX5EN, M_WAITOK | M_ZERO); 1777 1778 mlx5e_build_channel_param(priv, &cparam); 1779 for (i = 0; i < priv->params.num_channels; i++) { 1780 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]); 1781 if (err) 1782 goto err_close_channels; 1783 } 1784 1785 for (j = 0; j < priv->params.num_channels; j++) { 1786 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq); 1787 if (err) 1788 goto err_close_channels; 1789 } 1790 1791 return (0); 1792 1793err_close_channels: 1794 for (i--; i >= 0; i--) { 1795 mlx5e_close_channel(&priv->channel[i]); 1796 mlx5e_close_channel_wait(&priv->channel[i]); 1797 } 1798 1799 /* remove "volatile" attribute from "channel" pointer */ 1800 ptr = __DECONST(void *, priv->channel); 1801 priv->channel = NULL; 1802 1803 free(ptr, M_MLX5EN); 1804 1805 return (err); 1806} 1807 1808static void 1809mlx5e_close_channels(struct mlx5e_priv *priv) 1810{ 1811 void *ptr; 1812 int i; 1813 1814 if (priv->channel == NULL) 1815 return; 1816 1817 for (i = 0; i < priv->params.num_channels; i++) 1818 mlx5e_close_channel(&priv->channel[i]); 1819 for (i = 0; i < priv->params.num_channels; i++) 1820 mlx5e_close_channel_wait(&priv->channel[i]); 1821 1822 /* remove "volatile" attribute from "channel" pointer */ 1823 ptr = __DECONST(void *, priv->channel); 1824 priv->channel = NULL; 1825 1826 free(ptr, M_MLX5EN); 1827} 1828 1829static int 1830mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq) 1831{ 1832 1833 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) { 1834 uint8_t cq_mode; 1835 1836 switch (priv->params.tx_cq_moderation_mode) { 1837 case 0: 1838 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 1839 break; 1840 default: 1841 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE; 1842 break; 1843 } 1844 1845 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq, 1846 priv->params.tx_cq_moderation_usec, 1847 priv->params.tx_cq_moderation_pkts, 1848 cq_mode)); 1849 } 1850 1851 return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq, 1852 priv->params.tx_cq_moderation_usec, 1853 priv->params.tx_cq_moderation_pkts)); 1854} 1855 1856static int 1857mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq) 1858{ 1859 1860 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) { 1861 uint8_t cq_mode; 1862 int retval; 1863 1864 switch (priv->params.rx_cq_moderation_mode) { 1865 case 0: 1866 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 1867 break; 1868 default: 1869 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE; 1870 break; 1871 } 1872 1873 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq, 1874 priv->params.rx_cq_moderation_usec, 1875 priv->params.rx_cq_moderation_pkts, 1876 cq_mode); 1877 1878 return (retval); 1879 } 1880 1881 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq, 1882 priv->params.rx_cq_moderation_usec, 1883 priv->params.rx_cq_moderation_pkts)); 1884} 1885 1886static int 1887mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c) 1888{ 1889 int err; 1890 int i; 1891 1892 if (c == NULL) 1893 return (EINVAL); 1894 1895 err = mlx5e_refresh_rq_params(priv, &c->rq); 1896 if (err) 1897 goto done; 1898 1899 for (i = 0; i != c->num_tc; i++) { 1900 err = mlx5e_refresh_sq_params(priv, &c->sq[i]); 1901 if (err) 1902 goto done; 1903 } 1904done: 1905 return (err); 1906} 1907 1908int 1909mlx5e_refresh_channel_params(struct mlx5e_priv *priv) 1910{ 1911 int i; 1912 1913 if (priv->channel == NULL) 1914 return (EINVAL); 1915 1916 for (i = 0; i < priv->params.num_channels; i++) { 1917 int err; 1918 1919 err = mlx5e_refresh_channel_params_sub(priv, priv->channel[i]); 1920 if (err) 1921 return (err); 1922 } 1923 return (0); 1924} 1925 1926static int 1927mlx5e_open_tis(struct mlx5e_priv *priv, int tc) 1928{ 1929 struct mlx5_core_dev *mdev = priv->mdev; 1930 u32 in[MLX5_ST_SZ_DW(create_tis_in)]; 1931 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1932 1933 memset(in, 0, sizeof(in)); 1934 1935 MLX5_SET(tisc, tisc, prio, tc); 1936 MLX5_SET(tisc, tisc, transport_domain, priv->tdn); 1937 1938 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc])); 1939} 1940 1941static void 1942mlx5e_close_tis(struct mlx5e_priv *priv, int tc) 1943{ 1944 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]); 1945} 1946 1947static int 1948mlx5e_open_tises(struct mlx5e_priv *priv) 1949{ 1950 int num_tc = priv->num_tc; 1951 int err; 1952 int tc; 1953 1954 for (tc = 0; tc < num_tc; tc++) { 1955 err = mlx5e_open_tis(priv, tc); 1956 if (err) 1957 goto err_close_tises; 1958 } 1959 1960 return (0); 1961 1962err_close_tises: 1963 for (tc--; tc >= 0; tc--) 1964 mlx5e_close_tis(priv, tc); 1965 1966 return (err); 1967} 1968 1969static void 1970mlx5e_close_tises(struct mlx5e_priv *priv) 1971{ 1972 int num_tc = priv->num_tc; 1973 int tc; 1974 1975 for (tc = 0; tc < num_tc; tc++) 1976 mlx5e_close_tis(priv, tc); 1977} 1978 1979static int 1980mlx5e_open_rqt(struct mlx5e_priv *priv) 1981{ 1982 struct mlx5_core_dev *mdev = priv->mdev; 1983 u32 *in; 1984 u32 out[MLX5_ST_SZ_DW(create_rqt_out)]; 1985 void *rqtc; 1986 int inlen; 1987 int err; 1988 int sz; 1989 int i; 1990 1991 sz = 1 << priv->params.rx_hash_log_tbl_sz; 1992 1993 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 1994 in = mlx5_vzalloc(inlen); 1995 if (in == NULL) 1996 return (-ENOMEM); 1997 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1998 1999 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 2000 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 2001 2002 for (i = 0; i < sz; i++) { 2003 int ix; 2004#ifdef RSS 2005 ix = rss_get_indirection_to_bucket(i); 2006#else 2007 ix = i; 2008#endif 2009 /* ensure we don't overflow */ 2010 ix %= priv->params.num_channels; 2011 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn); 2012 } 2013 2014 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 2015 2016 memset(out, 0, sizeof(out)); 2017 err = mlx5_cmd_exec_check_status(mdev, in, inlen, out, sizeof(out)); 2018 if (!err) 2019 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn); 2020 2021 kvfree(in); 2022 2023 return (err); 2024} 2025 2026static void 2027mlx5e_close_rqt(struct mlx5e_priv *priv) 2028{ 2029 u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)]; 2030 u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)]; 2031 2032 memset(in, 0, sizeof(in)); 2033 2034 MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT); 2035 MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn); 2036 2037 mlx5_cmd_exec_check_status(priv->mdev, in, sizeof(in), out, 2038 sizeof(out)); 2039} 2040 2041static void 2042mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt) 2043{ 2044 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 2045 __be32 *hkey; 2046 2047 MLX5_SET(tirc, tirc, transport_domain, priv->tdn); 2048 2049#define ROUGH_MAX_L2_L3_HDR_SZ 256 2050 2051#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2052 MLX5_HASH_FIELD_SEL_DST_IP) 2053 2054#define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2055 MLX5_HASH_FIELD_SEL_DST_IP |\ 2056 MLX5_HASH_FIELD_SEL_L4_SPORT |\ 2057 MLX5_HASH_FIELD_SEL_L4_DPORT) 2058 2059#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2060 MLX5_HASH_FIELD_SEL_DST_IP |\ 2061 MLX5_HASH_FIELD_SEL_IPSEC_SPI) 2062 2063 if (priv->params.hw_lro_en) { 2064 MLX5_SET(tirc, tirc, lro_enable_mask, 2065 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO | 2066 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO); 2067 MLX5_SET(tirc, tirc, lro_max_msg_sz, 2068 (priv->params.lro_wqe_sz - 2069 ROUGH_MAX_L2_L3_HDR_SZ) >> 8); 2070 /* TODO: add the option to choose timer value dynamically */ 2071 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, 2072 MLX5_CAP_ETH(priv->mdev, 2073 lro_timer_supported_periods[2])); 2074 } 2075 2076 /* setup parameters for hashing TIR type, if any */ 2077 switch (tt) { 2078 case MLX5E_TT_ANY: 2079 MLX5_SET(tirc, tirc, disp_type, 2080 MLX5_TIRC_DISP_TYPE_DIRECT); 2081 MLX5_SET(tirc, tirc, inline_rqn, 2082 priv->channel[0]->rq.rqn); 2083 break; 2084 default: 2085 MLX5_SET(tirc, tirc, disp_type, 2086 MLX5_TIRC_DISP_TYPE_INDIRECT); 2087 MLX5_SET(tirc, tirc, indirect_table, 2088 priv->rqtn); 2089 MLX5_SET(tirc, tirc, rx_hash_fn, 2090 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ); 2091 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 2092#ifdef RSS 2093 /* 2094 * The FreeBSD RSS implementation does currently not 2095 * support symmetric Toeplitz hashes: 2096 */ 2097 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0); 2098 rss_getkey((uint8_t *)hkey); 2099#else 2100 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 2101 hkey[0] = cpu_to_be32(0xD181C62C); 2102 hkey[1] = cpu_to_be32(0xF7F4DB5B); 2103 hkey[2] = cpu_to_be32(0x1983A2FC); 2104 hkey[3] = cpu_to_be32(0x943E1ADB); 2105 hkey[4] = cpu_to_be32(0xD9389E6B); 2106 hkey[5] = cpu_to_be32(0xD1039C2C); 2107 hkey[6] = cpu_to_be32(0xA74499AD); 2108 hkey[7] = cpu_to_be32(0x593D56D9); 2109 hkey[8] = cpu_to_be32(0xF3253C06); 2110 hkey[9] = cpu_to_be32(0x2ADC1FFC); 2111#endif 2112 break; 2113 } 2114 2115 switch (tt) { 2116 case MLX5E_TT_IPV4_TCP: 2117 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2118 MLX5_L3_PROT_TYPE_IPV4); 2119 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2120 MLX5_L4_PROT_TYPE_TCP); 2121#ifdef RSS 2122 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) { 2123 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2124 MLX5_HASH_IP); 2125 } else 2126#endif 2127 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2128 MLX5_HASH_ALL); 2129 break; 2130 2131 case MLX5E_TT_IPV6_TCP: 2132 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2133 MLX5_L3_PROT_TYPE_IPV6); 2134 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2135 MLX5_L4_PROT_TYPE_TCP); 2136#ifdef RSS 2137 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) { 2138 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2139 MLX5_HASH_IP); 2140 } else 2141#endif 2142 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2143 MLX5_HASH_ALL); 2144 break; 2145 2146 case MLX5E_TT_IPV4_UDP: 2147 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2148 MLX5_L3_PROT_TYPE_IPV4); 2149 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2150 MLX5_L4_PROT_TYPE_UDP); 2151#ifdef RSS 2152 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) { 2153 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2154 MLX5_HASH_IP); 2155 } else 2156#endif 2157 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2158 MLX5_HASH_ALL); 2159 break; 2160 2161 case MLX5E_TT_IPV6_UDP: 2162 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2163 MLX5_L3_PROT_TYPE_IPV6); 2164 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2165 MLX5_L4_PROT_TYPE_UDP); 2166#ifdef RSS 2167 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) { 2168 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2169 MLX5_HASH_IP); 2170 } else 2171#endif 2172 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2173 MLX5_HASH_ALL); 2174 break; 2175 2176 case MLX5E_TT_IPV4_IPSEC_AH: 2177 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2178 MLX5_L3_PROT_TYPE_IPV4); 2179 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2180 MLX5_HASH_IP_IPSEC_SPI); 2181 break; 2182 2183 case MLX5E_TT_IPV6_IPSEC_AH: 2184 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2185 MLX5_L3_PROT_TYPE_IPV6); 2186 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2187 MLX5_HASH_IP_IPSEC_SPI); 2188 break; 2189 2190 case MLX5E_TT_IPV4_IPSEC_ESP: 2191 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2192 MLX5_L3_PROT_TYPE_IPV4); 2193 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2194 MLX5_HASH_IP_IPSEC_SPI); 2195 break; 2196 2197 case MLX5E_TT_IPV6_IPSEC_ESP: 2198 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2199 MLX5_L3_PROT_TYPE_IPV6); 2200 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2201 MLX5_HASH_IP_IPSEC_SPI); 2202 break; 2203 2204 case MLX5E_TT_IPV4: 2205 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2206 MLX5_L3_PROT_TYPE_IPV4); 2207 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2208 MLX5_HASH_IP); 2209 break; 2210 2211 case MLX5E_TT_IPV6: 2212 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2213 MLX5_L3_PROT_TYPE_IPV6); 2214 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2215 MLX5_HASH_IP); 2216 break; 2217 2218 default: 2219 break; 2220 } 2221} 2222 2223static int 2224mlx5e_open_tir(struct mlx5e_priv *priv, int tt) 2225{ 2226 struct mlx5_core_dev *mdev = priv->mdev; 2227 u32 *in; 2228 void *tirc; 2229 int inlen; 2230 int err; 2231 2232 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 2233 in = mlx5_vzalloc(inlen); 2234 if (in == NULL) 2235 return (-ENOMEM); 2236 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context); 2237 2238 mlx5e_build_tir_ctx(priv, tirc, tt); 2239 2240 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]); 2241 2242 kvfree(in); 2243 2244 return (err); 2245} 2246 2247static void 2248mlx5e_close_tir(struct mlx5e_priv *priv, int tt) 2249{ 2250 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]); 2251} 2252 2253static int 2254mlx5e_open_tirs(struct mlx5e_priv *priv) 2255{ 2256 int err; 2257 int i; 2258 2259 for (i = 0; i < MLX5E_NUM_TT; i++) { 2260 err = mlx5e_open_tir(priv, i); 2261 if (err) 2262 goto err_close_tirs; 2263 } 2264 2265 return (0); 2266 2267err_close_tirs: 2268 for (i--; i >= 0; i--) 2269 mlx5e_close_tir(priv, i); 2270 2271 return (err); 2272} 2273 2274static void 2275mlx5e_close_tirs(struct mlx5e_priv *priv) 2276{ 2277 int i; 2278 2279 for (i = 0; i < MLX5E_NUM_TT; i++) 2280 mlx5e_close_tir(priv, i); 2281} 2282 2283/* 2284 * SW MTU does not include headers, 2285 * HW MTU includes all headers and checksums. 2286 */ 2287static int 2288mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu) 2289{ 2290 struct mlx5e_priv *priv = ifp->if_softc; 2291 struct mlx5_core_dev *mdev = priv->mdev; 2292 int hw_mtu; 2293 int err; 2294 2295 err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(sw_mtu)); 2296 if (err) { 2297 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n", 2298 __func__, sw_mtu, err); 2299 return (err); 2300 } 2301 2302 ifp->if_mtu = sw_mtu; 2303 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu); 2304 if (err) { 2305 if_printf(ifp, "Query port MTU, after setting new " 2306 "MTU value, failed\n"); 2307 return (err); 2308 } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) { 2309 err = -E2BIG, 2310 if_printf(ifp, "Port MTU %d is smaller than " 2311 "ifp mtu %d\n", hw_mtu, sw_mtu); 2312 } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) { 2313 err = -EINVAL; 2314 if_printf(ifp, "Port MTU %d is bigger than " 2315 "ifp mtu %d\n", hw_mtu, sw_mtu); 2316 } 2317 priv->params_ethtool.hw_mtu = hw_mtu; 2318 2319 return (err); 2320} 2321 2322int 2323mlx5e_open_locked(struct ifnet *ifp) 2324{ 2325 struct mlx5e_priv *priv = ifp->if_softc; 2326 int err; 2327 u16 set_id; 2328 2329 /* check if already opened */ 2330 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0) 2331 return (0); 2332 2333#ifdef RSS 2334 if (rss_getnumbuckets() > priv->params.num_channels) { 2335 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than " 2336 "channels(%u) available\n", rss_getnumbuckets(), 2337 priv->params.num_channels); 2338 } 2339#endif 2340 err = mlx5e_open_tises(priv); 2341 if (err) { 2342 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n", 2343 __func__, err); 2344 return (err); 2345 } 2346 err = mlx5_vport_alloc_q_counter(priv->mdev, 2347 MLX5_INTERFACE_PROTOCOL_ETH, &set_id); 2348 if (err) { 2349 if_printf(priv->ifp, 2350 "%s: mlx5_vport_alloc_q_counter failed: %d\n", 2351 __func__, err); 2352 goto err_close_tises; 2353 } 2354 /* store counter set ID */ 2355 priv->counter_set_id = set_id; 2356 2357 err = mlx5e_open_channels(priv); 2358 if (err) { 2359 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n", 2360 __func__, err); 2361 goto err_dalloc_q_counter; 2362 } 2363 err = mlx5e_open_rqt(priv); 2364 if (err) { 2365 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n", 2366 __func__, err); 2367 goto err_close_channels; 2368 } 2369 err = mlx5e_open_tirs(priv); 2370 if (err) { 2371 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n", 2372 __func__, err); 2373 goto err_close_rqls; 2374 } 2375 err = mlx5e_open_flow_table(priv); 2376 if (err) { 2377 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n", 2378 __func__, err); 2379 goto err_close_tirs; 2380 } 2381 err = mlx5e_add_all_vlan_rules(priv); 2382 if (err) { 2383 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n", 2384 __func__, err); 2385 goto err_close_flow_table; 2386 } 2387 set_bit(MLX5E_STATE_OPENED, &priv->state); 2388 2389 mlx5e_update_carrier(priv); 2390 mlx5e_set_rx_mode_core(priv); 2391 2392 return (0); 2393 2394err_close_flow_table: 2395 mlx5e_close_flow_table(priv); 2396 2397err_close_tirs: 2398 mlx5e_close_tirs(priv); 2399 2400err_close_rqls: 2401 mlx5e_close_rqt(priv); 2402 2403err_close_channels: 2404 mlx5e_close_channels(priv); 2405 2406err_dalloc_q_counter: 2407 mlx5_vport_dealloc_q_counter(priv->mdev, 2408 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id); 2409 2410err_close_tises: 2411 mlx5e_close_tises(priv); 2412 2413 return (err); 2414} 2415 2416static void 2417mlx5e_open(void *arg) 2418{ 2419 struct mlx5e_priv *priv = arg; 2420 2421 PRIV_LOCK(priv); 2422 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP)) 2423 if_printf(priv->ifp, 2424 "%s: Setting port status to up failed\n", 2425 __func__); 2426 2427 mlx5e_open_locked(priv->ifp); 2428 priv->ifp->if_drv_flags |= IFF_DRV_RUNNING; 2429 PRIV_UNLOCK(priv); 2430} 2431 2432int 2433mlx5e_close_locked(struct ifnet *ifp) 2434{ 2435 struct mlx5e_priv *priv = ifp->if_softc; 2436 2437 /* check if already closed */ 2438 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 2439 return (0); 2440 2441 clear_bit(MLX5E_STATE_OPENED, &priv->state); 2442 2443 mlx5e_set_rx_mode_core(priv); 2444 mlx5e_del_all_vlan_rules(priv); 2445 if_link_state_change(priv->ifp, LINK_STATE_DOWN); 2446 mlx5e_close_flow_table(priv); 2447 mlx5e_close_tirs(priv); 2448 mlx5e_close_rqt(priv); 2449 mlx5e_close_channels(priv); 2450 mlx5_vport_dealloc_q_counter(priv->mdev, 2451 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id); 2452 mlx5e_close_tises(priv); 2453 2454 return (0); 2455} 2456 2457#if (__FreeBSD_version >= 1100000) 2458static uint64_t 2459mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt) 2460{ 2461 struct mlx5e_priv *priv = ifp->if_softc; 2462 u64 retval; 2463 2464 /* PRIV_LOCK(priv); XXX not allowed */ 2465 switch (cnt) { 2466 case IFCOUNTER_IPACKETS: 2467 retval = priv->stats.vport.rx_packets; 2468 break; 2469 case IFCOUNTER_IERRORS: 2470 retval = priv->stats.vport.rx_error_packets + 2471 priv->stats.pport.alignment_err + 2472 priv->stats.pport.check_seq_err + 2473 priv->stats.pport.crc_align_errors + 2474 priv->stats.pport.in_range_len_errors + 2475 priv->stats.pport.jabbers + 2476 priv->stats.pport.out_of_range_len + 2477 priv->stats.pport.oversize_pkts + 2478 priv->stats.pport.symbol_err + 2479 priv->stats.pport.too_long_errors + 2480 priv->stats.pport.undersize_pkts + 2481 priv->stats.pport.unsupported_op_rx; 2482 break; 2483 case IFCOUNTER_IQDROPS: 2484 retval = priv->stats.vport.rx_out_of_buffer + 2485 priv->stats.pport.drop_events; 2486 break; 2487 case IFCOUNTER_OPACKETS: 2488 retval = priv->stats.vport.tx_packets; 2489 break; 2490 case IFCOUNTER_OERRORS: 2491 retval = priv->stats.vport.tx_error_packets; 2492 break; 2493 case IFCOUNTER_IBYTES: 2494 retval = priv->stats.vport.rx_bytes; 2495 break; 2496 case IFCOUNTER_OBYTES: 2497 retval = priv->stats.vport.tx_bytes; 2498 break; 2499 case IFCOUNTER_IMCASTS: 2500 retval = priv->stats.vport.rx_multicast_packets; 2501 break; 2502 case IFCOUNTER_OMCASTS: 2503 retval = priv->stats.vport.tx_multicast_packets; 2504 break; 2505 case IFCOUNTER_OQDROPS: 2506 retval = priv->stats.vport.tx_queue_dropped; 2507 break; 2508 case IFCOUNTER_COLLISIONS: 2509 retval = priv->stats.pport.collisions; 2510 break; 2511 default: 2512 retval = if_get_counter_default(ifp, cnt); 2513 break; 2514 } 2515 /* PRIV_UNLOCK(priv); XXX not allowed */ 2516 return (retval); 2517} 2518#endif 2519 2520static void 2521mlx5e_set_rx_mode(struct ifnet *ifp) 2522{ 2523 struct mlx5e_priv *priv = ifp->if_softc; 2524 2525 schedule_work(&priv->set_rx_mode_work); 2526} 2527 2528static int 2529mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2530{ 2531 struct mlx5e_priv *priv; 2532 struct ifreq *ifr; 2533 struct ifi2creq i2c; 2534 int error = 0; 2535 int mask = 0; 2536 int size_read = 0; 2537 int module_status; 2538 int module_num; 2539 int max_mtu; 2540 uint8_t read_addr; 2541 2542 priv = ifp->if_softc; 2543 2544 /* check if detaching */ 2545 if (priv == NULL || priv->gone != 0) 2546 return (ENXIO); 2547 2548 switch (command) { 2549 case SIOCSIFMTU: 2550 ifr = (struct ifreq *)data; 2551 2552 PRIV_LOCK(priv); 2553 mlx5_query_port_max_mtu(priv->mdev, &max_mtu); 2554 2555 if (ifr->ifr_mtu >= MLX5E_MTU_MIN && 2556 ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) { 2557 int was_opened; 2558 2559 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 2560 if (was_opened) 2561 mlx5e_close_locked(ifp); 2562 2563 /* set new MTU */ 2564 mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu); 2565 2566 if (was_opened) 2567 mlx5e_open_locked(ifp); 2568 } else { 2569 error = EINVAL; 2570 if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n", 2571 MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu)); 2572 } 2573 PRIV_UNLOCK(priv); 2574 break; 2575 case SIOCSIFFLAGS: 2576 if ((ifp->if_flags & IFF_UP) && 2577 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 2578 mlx5e_set_rx_mode(ifp); 2579 break; 2580 } 2581 PRIV_LOCK(priv); 2582 if (ifp->if_flags & IFF_UP) { 2583 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2584 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 2585 mlx5e_open_locked(ifp); 2586 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2587 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP); 2588 } 2589 } else { 2590 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2591 mlx5_set_port_status(priv->mdev, 2592 MLX5_PORT_DOWN); 2593 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0) 2594 mlx5e_close_locked(ifp); 2595 mlx5e_update_carrier(priv); 2596 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2597 } 2598 } 2599 PRIV_UNLOCK(priv); 2600 break; 2601 case SIOCADDMULTI: 2602 case SIOCDELMULTI: 2603 mlx5e_set_rx_mode(ifp); 2604 break; 2605 case SIOCSIFMEDIA: 2606 case SIOCGIFMEDIA: 2607 case SIOCGIFXMEDIA: 2608 ifr = (struct ifreq *)data; 2609 error = ifmedia_ioctl(ifp, ifr, &priv->media, command); 2610 break; 2611 case SIOCSIFCAP: 2612 ifr = (struct ifreq *)data; 2613 PRIV_LOCK(priv); 2614 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2615 2616 if (mask & IFCAP_TXCSUM) { 2617 ifp->if_capenable ^= IFCAP_TXCSUM; 2618 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 2619 2620 if (IFCAP_TSO4 & ifp->if_capenable && 2621 !(IFCAP_TXCSUM & ifp->if_capenable)) { 2622 ifp->if_capenable &= ~IFCAP_TSO4; 2623 ifp->if_hwassist &= ~CSUM_IP_TSO; 2624 if_printf(ifp, 2625 "tso4 disabled due to -txcsum.\n"); 2626 } 2627 } 2628 if (mask & IFCAP_TXCSUM_IPV6) { 2629 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 2630 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 2631 2632 if (IFCAP_TSO6 & ifp->if_capenable && 2633 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 2634 ifp->if_capenable &= ~IFCAP_TSO6; 2635 ifp->if_hwassist &= ~CSUM_IP6_TSO; 2636 if_printf(ifp, 2637 "tso6 disabled due to -txcsum6.\n"); 2638 } 2639 } 2640 if (mask & IFCAP_RXCSUM) 2641 ifp->if_capenable ^= IFCAP_RXCSUM; 2642 if (mask & IFCAP_RXCSUM_IPV6) 2643 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 2644 if (mask & IFCAP_TSO4) { 2645 if (!(IFCAP_TSO4 & ifp->if_capenable) && 2646 !(IFCAP_TXCSUM & ifp->if_capenable)) { 2647 if_printf(ifp, "enable txcsum first.\n"); 2648 error = EAGAIN; 2649 goto out; 2650 } 2651 ifp->if_capenable ^= IFCAP_TSO4; 2652 ifp->if_hwassist ^= CSUM_IP_TSO; 2653 } 2654 if (mask & IFCAP_TSO6) { 2655 if (!(IFCAP_TSO6 & ifp->if_capenable) && 2656 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 2657 if_printf(ifp, "enable txcsum6 first.\n"); 2658 error = EAGAIN; 2659 goto out; 2660 } 2661 ifp->if_capenable ^= IFCAP_TSO6; 2662 ifp->if_hwassist ^= CSUM_IP6_TSO; 2663 } 2664 if (mask & IFCAP_VLAN_HWFILTER) { 2665 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) 2666 mlx5e_disable_vlan_filter(priv); 2667 else 2668 mlx5e_enable_vlan_filter(priv); 2669 2670 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER; 2671 } 2672 if (mask & IFCAP_VLAN_HWTAGGING) 2673 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2674 if (mask & IFCAP_WOL_MAGIC) 2675 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2676 2677 VLAN_CAPABILITIES(ifp); 2678 /* turn off LRO means also turn of HW LRO - if it's on */ 2679 if (mask & IFCAP_LRO) { 2680 int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 2681 bool need_restart = false; 2682 2683 ifp->if_capenable ^= IFCAP_LRO; 2684 if (!(ifp->if_capenable & IFCAP_LRO)) { 2685 if (priv->params.hw_lro_en) { 2686 priv->params.hw_lro_en = false; 2687 need_restart = true; 2688 /* Not sure this is the correct way */ 2689 priv->params_ethtool.hw_lro = priv->params.hw_lro_en; 2690 } 2691 } 2692 if (was_opened && need_restart) { 2693 mlx5e_close_locked(ifp); 2694 mlx5e_open_locked(ifp); 2695 } 2696 } 2697out: 2698 PRIV_UNLOCK(priv); 2699 break; 2700 2701 case SIOCGI2C: 2702 ifr = (struct ifreq *)data; 2703 2704 /* 2705 * Copy from the user-space address ifr_data to the 2706 * kernel-space address i2c 2707 */ 2708 error = copyin(ifr->ifr_data, &i2c, sizeof(i2c)); 2709 if (error) 2710 break; 2711 2712 if (i2c.len > sizeof(i2c.data)) { 2713 error = EINVAL; 2714 break; 2715 } 2716 2717 PRIV_LOCK(priv); 2718 /* Get module_num which is required for the query_eeprom */ 2719 error = mlx5_query_module_num(priv->mdev, &module_num); 2720 if (error) { 2721 if_printf(ifp, "Query module num failed, eeprom " 2722 "reading is not supported\n"); 2723 error = EINVAL; 2724 goto err_i2c; 2725 } 2726 /* Check if module is present before doing an access */ 2727 module_status = mlx5_query_module_status(priv->mdev, module_num); 2728 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED && 2729 module_status != MLX5_MODULE_STATUS_PLUGGED_DISABLED) { 2730 error = EINVAL; 2731 goto err_i2c; 2732 } 2733 /* 2734 * Currently 0XA0 and 0xA2 are the only addresses permitted. 2735 * The internal conversion is as follows: 2736 */ 2737 if (i2c.dev_addr == 0xA0) 2738 read_addr = MLX5E_I2C_ADDR_LOW; 2739 else if (i2c.dev_addr == 0xA2) 2740 read_addr = MLX5E_I2C_ADDR_HIGH; 2741 else { 2742 if_printf(ifp, "Query eeprom failed, " 2743 "Invalid Address: %X\n", i2c.dev_addr); 2744 error = EINVAL; 2745 goto err_i2c; 2746 } 2747 error = mlx5_query_eeprom(priv->mdev, 2748 read_addr, MLX5E_EEPROM_LOW_PAGE, 2749 (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num, 2750 (uint32_t *)i2c.data, &size_read); 2751 if (error) { 2752 if_printf(ifp, "Query eeprom failed, eeprom " 2753 "reading is not supported\n"); 2754 error = EINVAL; 2755 goto err_i2c; 2756 } 2757 2758 if (i2c.len > MLX5_EEPROM_MAX_BYTES) { 2759 error = mlx5_query_eeprom(priv->mdev, 2760 read_addr, MLX5E_EEPROM_LOW_PAGE, 2761 (uint32_t)(i2c.offset + size_read), 2762 (uint32_t)(i2c.len - size_read), module_num, 2763 (uint32_t *)(i2c.data + size_read), &size_read); 2764 } 2765 if (error) { 2766 if_printf(ifp, "Query eeprom failed, eeprom " 2767 "reading is not supported\n"); 2768 error = EINVAL; 2769 goto err_i2c; 2770 } 2771 2772 error = copyout(&i2c, ifr->ifr_data, sizeof(i2c)); 2773err_i2c: 2774 PRIV_UNLOCK(priv); 2775 break; 2776 2777 default: 2778 error = ether_ioctl(ifp, command, data); 2779 break; 2780 } 2781 return (error); 2782} 2783 2784static int 2785mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev) 2786{ 2787 /* 2788 * TODO: uncoment once FW really sets all these bits if 2789 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap || 2790 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap || 2791 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return 2792 * -ENOTSUPP; 2793 */ 2794 2795 /* TODO: add more must-to-have features */ 2796 2797 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) 2798 return (-ENODEV); 2799 2800 return (0); 2801} 2802 2803static void 2804mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev, 2805 struct mlx5e_priv *priv, 2806 int num_comp_vectors) 2807{ 2808 /* 2809 * TODO: Consider link speed for setting "log_sq_size", 2810 * "log_rq_size" and "cq_moderation_xxx": 2811 */ 2812 priv->params.log_sq_size = 2813 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; 2814 priv->params.log_rq_size = 2815 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE; 2816 priv->params.rx_cq_moderation_usec = 2817 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 2818 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE : 2819 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC; 2820 priv->params.rx_cq_moderation_mode = 2821 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0; 2822 priv->params.rx_cq_moderation_pkts = 2823 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS; 2824 priv->params.tx_cq_moderation_usec = 2825 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC; 2826 priv->params.tx_cq_moderation_pkts = 2827 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS; 2828 priv->params.min_rx_wqes = 2829 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES; 2830 priv->params.rx_hash_log_tbl_sz = 2831 (order_base_2(num_comp_vectors) > 2832 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ? 2833 order_base_2(num_comp_vectors) : 2834 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ; 2835 priv->params.num_tc = 1; 2836 priv->params.default_vlan_prio = 0; 2837 priv->counter_set_id = -1; 2838 2839 /* 2840 * hw lro is currently defaulted to off. when it won't anymore we 2841 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)" 2842 */ 2843 priv->params.hw_lro_en = false; 2844 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ; 2845 2846 priv->params.cqe_zipping_en = !!MLX5_CAP_GEN(mdev, cqe_compression); 2847 2848 priv->mdev = mdev; 2849 priv->params.num_channels = num_comp_vectors; 2850 priv->order_base_2_num_channels = order_base_2(num_comp_vectors); 2851 priv->queue_mapping_channel_mask = 2852 roundup_pow_of_two(num_comp_vectors) - 1; 2853 priv->num_tc = priv->params.num_tc; 2854 priv->default_vlan_prio = priv->params.default_vlan_prio; 2855 2856 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work); 2857 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work); 2858 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work); 2859} 2860 2861static int 2862mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn, 2863 struct mlx5_core_mr *mr) 2864{ 2865 struct ifnet *ifp = priv->ifp; 2866 struct mlx5_core_dev *mdev = priv->mdev; 2867 struct mlx5_create_mkey_mbox_in *in; 2868 int err; 2869 2870 in = mlx5_vzalloc(sizeof(*in)); 2871 if (in == NULL) { 2872 if_printf(ifp, "%s: failed to allocate inbox\n", __func__); 2873 return (-ENOMEM); 2874 } 2875 in->seg.flags = MLX5_PERM_LOCAL_WRITE | 2876 MLX5_PERM_LOCAL_READ | 2877 MLX5_ACCESS_MODE_PA; 2878 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64); 2879 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8); 2880 2881 err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL, 2882 NULL); 2883 if (err) 2884 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n", 2885 __func__, err); 2886 2887 kvfree(in); 2888 2889 return (err); 2890} 2891 2892static const char *mlx5e_vport_stats_desc[] = { 2893 MLX5E_VPORT_STATS(MLX5E_STATS_DESC) 2894}; 2895 2896static const char *mlx5e_pport_stats_desc[] = { 2897 MLX5E_PPORT_STATS(MLX5E_STATS_DESC) 2898}; 2899 2900static void 2901mlx5e_priv_mtx_init(struct mlx5e_priv *priv) 2902{ 2903 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF); 2904 sx_init(&priv->state_lock, "mlx5state"); 2905 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0); 2906 MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock); 2907} 2908 2909static void 2910mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv) 2911{ 2912 mtx_destroy(&priv->async_events_mtx); 2913 sx_destroy(&priv->state_lock); 2914} 2915 2916static int 2917sysctl_firmware(SYSCTL_HANDLER_ARGS) 2918{ 2919 /* 2920 * %d.%d%.d the string format. 2921 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536. 2922 * We need at most 5 chars to store that. 2923 * It also has: two "." and NULL at the end, which means we need 18 2924 * (5*3 + 3) chars at most. 2925 */ 2926 char fw[18]; 2927 struct mlx5e_priv *priv = arg1; 2928 int error; 2929 2930 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev), 2931 fw_rev_sub(priv->mdev)); 2932 error = sysctl_handle_string(oidp, fw, sizeof(fw), req); 2933 return (error); 2934} 2935 2936static void 2937mlx5e_disable_tx_dma(struct mlx5e_channel *ch) 2938{ 2939 int i; 2940 2941 for (i = 0; i < ch->num_tc; i++) 2942 mlx5e_drain_sq(&ch->sq[i]); 2943} 2944 2945static void 2946mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq) 2947{ 2948 2949 sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP); 2950 sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8); 2951 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0); 2952 sq->doorbell.d64 = 0; 2953} 2954 2955void 2956mlx5e_resume_sq(struct mlx5e_sq *sq) 2957{ 2958 int err; 2959 2960 /* check if already enabled */ 2961 if (sq->stopped == 0) 2962 return; 2963 2964 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR, 2965 MLX5_SQC_STATE_RST); 2966 if (err != 0) { 2967 if_printf(sq->ifp, 2968 "mlx5e_modify_sq() from ERR to RST failed: %d\n", err); 2969 } 2970 2971 sq->cc = 0; 2972 sq->pc = 0; 2973 2974 /* reset doorbell prior to moving from RST to RDY */ 2975 mlx5e_reset_sq_doorbell_record(sq); 2976 2977 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, 2978 MLX5_SQC_STATE_RDY); 2979 if (err != 0) { 2980 if_printf(sq->ifp, 2981 "mlx5e_modify_sq() from RST to RDY failed: %d\n", err); 2982 } 2983 2984 mtx_lock(&sq->lock); 2985 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL; 2986 sq->stopped = 0; 2987 mtx_unlock(&sq->lock); 2988 2989} 2990 2991static void 2992mlx5e_enable_tx_dma(struct mlx5e_channel *ch) 2993{ 2994 int i; 2995 2996 for (i = 0; i < ch->num_tc; i++) 2997 mlx5e_resume_sq(&ch->sq[i]); 2998} 2999 3000static void 3001mlx5e_disable_rx_dma(struct mlx5e_channel *ch) 3002{ 3003 struct mlx5e_rq *rq = &ch->rq; 3004 int err; 3005 3006 mtx_lock(&rq->mtx); 3007 rq->enabled = 0; 3008 callout_stop(&rq->watchdog); 3009 mtx_unlock(&rq->mtx); 3010 3011 callout_drain(&rq->watchdog); 3012 3013 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 3014 if (err != 0) { 3015 if_printf(rq->ifp, 3016 "mlx5e_modify_rq() from RDY to RST failed: %d\n", err); 3017 } 3018 3019 while (!mlx5_wq_ll_is_empty(&rq->wq)) { 3020 msleep(1); 3021 rq->cq.mcq.comp(&rq->cq.mcq); 3022 } 3023 3024 /* 3025 * Transitioning into RST state will allow the FW to track less ERR state queues, 3026 * thus reducing the recv queue flushing time 3027 */ 3028 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST); 3029 if (err != 0) { 3030 if_printf(rq->ifp, 3031 "mlx5e_modify_rq() from ERR to RST failed: %d\n", err); 3032 } 3033} 3034 3035static void 3036mlx5e_enable_rx_dma(struct mlx5e_channel *ch) 3037{ 3038 struct mlx5e_rq *rq = &ch->rq; 3039 int err; 3040 3041 rq->wq.wqe_ctr = 0; 3042 mlx5_wq_ll_update_db_record(&rq->wq); 3043 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 3044 if (err != 0) { 3045 if_printf(rq->ifp, 3046 "mlx5e_modify_rq() from RST to RDY failed: %d\n", err); 3047 } 3048 3049 rq->enabled = 1; 3050 3051 rq->cq.mcq.comp(&rq->cq.mcq); 3052} 3053 3054void 3055mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value) 3056{ 3057 int i; 3058 3059 if (priv->channel == NULL) 3060 return; 3061 3062 for (i = 0; i < priv->params.num_channels; i++) { 3063 3064 if (!priv->channel[i]) 3065 continue; 3066 3067 if (value) 3068 mlx5e_disable_tx_dma(priv->channel[i]); 3069 else 3070 mlx5e_enable_tx_dma(priv->channel[i]); 3071 } 3072} 3073 3074void 3075mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value) 3076{ 3077 int i; 3078 3079 if (priv->channel == NULL) 3080 return; 3081 3082 for (i = 0; i < priv->params.num_channels; i++) { 3083 3084 if (!priv->channel[i]) 3085 continue; 3086 3087 if (value) 3088 mlx5e_disable_rx_dma(priv->channel[i]); 3089 else 3090 mlx5e_enable_rx_dma(priv->channel[i]); 3091 } 3092} 3093 3094static void 3095mlx5e_add_hw_stats(struct mlx5e_priv *priv) 3096{ 3097 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw), 3098 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0, 3099 sysctl_firmware, "A", "HCA firmware version"); 3100 3101 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw), 3102 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0, 3103 "Board ID"); 3104} 3105 3106static void 3107mlx5e_setup_pauseframes(struct mlx5e_priv *priv) 3108{ 3109#if (__FreeBSD_version < 1100000) 3110 char path[64]; 3111 3112#endif 3113 /* Only receiving pauseframes is enabled by default */ 3114 priv->params.tx_pauseframe_control = 0; 3115 priv->params.rx_pauseframe_control = 1; 3116 3117#if (__FreeBSD_version < 1100000) 3118 /* compute path for sysctl */ 3119 snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control", 3120 device_get_unit(priv->mdev->pdev->dev.bsddev)); 3121 3122 /* try to fetch tunable, if any */ 3123 TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control); 3124 3125 /* compute path for sysctl */ 3126 snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control", 3127 device_get_unit(priv->mdev->pdev->dev.bsddev)); 3128 3129 /* try to fetch tunable, if any */ 3130 TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control); 3131#endif 3132 3133 /* register pausframe SYSCTLs */ 3134 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 3135 OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN, 3136 &priv->params.tx_pauseframe_control, 0, 3137 "Set to enable TX pause frames. Clear to disable."); 3138 3139 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 3140 OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN, 3141 &priv->params.rx_pauseframe_control, 0, 3142 "Set to enable RX pause frames. Clear to disable."); 3143 3144 /* range check */ 3145 priv->params.tx_pauseframe_control = 3146 priv->params.tx_pauseframe_control ? 1 : 0; 3147 priv->params.rx_pauseframe_control = 3148 priv->params.rx_pauseframe_control ? 1 : 0; 3149 3150 /* update firmware */ 3151 mlx5_set_port_pause(priv->mdev, 1, 3152 priv->params.rx_pauseframe_control, 3153 priv->params.tx_pauseframe_control); 3154} 3155 3156static void * 3157mlx5e_create_ifp(struct mlx5_core_dev *mdev) 3158{ 3159 static volatile int mlx5_en_unit; 3160 struct ifnet *ifp; 3161 struct mlx5e_priv *priv; 3162 u8 dev_addr[ETHER_ADDR_LEN] __aligned(4); 3163 struct sysctl_oid_list *child; 3164 int ncv = mdev->priv.eq_table.num_comp_vectors; 3165 char unit[16]; 3166 int err; 3167 int i; 3168 u32 eth_proto_cap; 3169 3170 if (mlx5e_check_required_hca_cap(mdev)) { 3171 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n"); 3172 return (NULL); 3173 } 3174 priv = malloc(sizeof(*priv), M_MLX5EN, M_WAITOK | M_ZERO); 3175 mlx5e_priv_mtx_init(priv); 3176 3177 ifp = priv->ifp = if_alloc(IFT_ETHER); 3178 if (ifp == NULL) { 3179 mlx5_core_err(mdev, "if_alloc() failed\n"); 3180 goto err_free_priv; 3181 } 3182 ifp->if_softc = priv; 3183 if_initname(ifp, "mce", atomic_fetchadd_int(&mlx5_en_unit, 1)); 3184 ifp->if_mtu = ETHERMTU; 3185 ifp->if_init = mlx5e_open; 3186 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3187 ifp->if_ioctl = mlx5e_ioctl; 3188 ifp->if_transmit = mlx5e_xmit; 3189 ifp->if_qflush = if_qflush; 3190#if (__FreeBSD_version >= 1100000) 3191 ifp->if_get_counter = mlx5e_get_counter; 3192#endif 3193 ifp->if_snd.ifq_maxlen = ifqmaxlen; 3194 /* 3195 * Set driver features 3196 */ 3197 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6; 3198 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 3199 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER; 3200 ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU; 3201 ifp->if_capabilities |= IFCAP_LRO; 3202 ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO; 3203 ifp->if_capabilities |= IFCAP_HWSTATS; 3204 3205 /* set TSO limits so that we don't have to drop TX packets */ 3206 ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 3207 ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */; 3208 ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE; 3209 3210 ifp->if_capenable = ifp->if_capabilities; 3211 ifp->if_hwassist = 0; 3212 if (ifp->if_capenable & IFCAP_TSO) 3213 ifp->if_hwassist |= CSUM_TSO; 3214 if (ifp->if_capenable & IFCAP_TXCSUM) 3215 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP); 3216 if (ifp->if_capenable & IFCAP_TXCSUM_IPV6) 3217 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 3218 3219 /* ifnet sysctl tree */ 3220 sysctl_ctx_init(&priv->sysctl_ctx); 3221 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev), 3222 OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name"); 3223 if (priv->sysctl_ifnet == NULL) { 3224 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 3225 goto err_free_sysctl; 3226 } 3227 snprintf(unit, sizeof(unit), "%d", ifp->if_dunit); 3228 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 3229 OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit"); 3230 if (priv->sysctl_ifnet == NULL) { 3231 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 3232 goto err_free_sysctl; 3233 } 3234 3235 /* HW sysctl tree */ 3236 child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev)); 3237 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child, 3238 OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw"); 3239 if (priv->sysctl_hw == NULL) { 3240 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 3241 goto err_free_sysctl; 3242 } 3243 mlx5e_build_ifp_priv(mdev, priv, ncv); 3244 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar); 3245 if (err) { 3246 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n", 3247 __func__, err); 3248 goto err_free_sysctl; 3249 } 3250 err = mlx5_core_alloc_pd(mdev, &priv->pdn); 3251 if (err) { 3252 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n", 3253 __func__, err); 3254 goto err_unmap_free_uar; 3255 } 3256 err = mlx5_alloc_transport_domain(mdev, &priv->tdn); 3257 if (err) { 3258 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n", 3259 __func__, err); 3260 goto err_dealloc_pd; 3261 } 3262 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr); 3263 if (err) { 3264 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n", 3265 __func__, err); 3266 goto err_dealloc_transport_domain; 3267 } 3268 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr); 3269 3270 /* check if we should generate a random MAC address */ 3271 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 && 3272 is_zero_ether_addr(dev_addr)) { 3273 random_ether_addr(dev_addr); 3274 if_printf(ifp, "Assigned random MAC address\n"); 3275 } 3276 3277 /* set default MTU */ 3278 mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu); 3279 3280 /* Set desc */ 3281 device_set_desc(mdev->pdev->dev.bsddev, mlx5e_version); 3282 3283 /* Set default media status */ 3284 priv->media_status_last = IFM_AVALID; 3285 priv->media_active_last = IFM_ETHER | IFM_AUTO | 3286 IFM_ETH_RXPAUSE | IFM_FDX; 3287 3288 /* setup default pauseframes configuration */ 3289 mlx5e_setup_pauseframes(priv); 3290 3291 err = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN); 3292 if (err) { 3293 eth_proto_cap = 0; 3294 if_printf(ifp, "%s: Query port media capability failed, %d\n", 3295 __func__, err); 3296 } 3297 3298 /* Setup supported medias */ 3299 ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK, 3300 mlx5e_media_change, mlx5e_media_status); 3301 3302 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) { 3303 if (mlx5e_mode_table[i].baudrate == 0) 3304 continue; 3305 if (MLX5E_PROT_MASK(i) & eth_proto_cap) { 3306 ifmedia_add(&priv->media, 3307 mlx5e_mode_table[i].subtype | 3308 IFM_ETHER, 0, NULL); 3309 ifmedia_add(&priv->media, 3310 mlx5e_mode_table[i].subtype | 3311 IFM_ETHER | IFM_FDX | 3312 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL); 3313 } 3314 } 3315 3316 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL); 3317 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX | 3318 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL); 3319 3320 /* Set autoselect by default */ 3321 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX | 3322 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE); 3323 ether_ifattach(ifp, dev_addr); 3324 3325 /* Register for VLAN events */ 3326 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config, 3327 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST); 3328 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig, 3329 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST); 3330 3331 /* Link is down by default */ 3332 if_link_state_change(ifp, LINK_STATE_DOWN); 3333 3334 mlx5e_enable_async_events(priv); 3335 3336 mlx5e_add_hw_stats(priv); 3337 3338 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 3339 "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM, 3340 priv->stats.vport.arg); 3341 3342 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 3343 "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM, 3344 priv->stats.pport.arg); 3345 3346 mlx5e_create_ethtool(priv); 3347 3348 mtx_lock(&priv->async_events_mtx); 3349 mlx5e_update_stats(priv); 3350 mtx_unlock(&priv->async_events_mtx); 3351 3352 return (priv); 3353 3354err_dealloc_transport_domain: 3355 mlx5_dealloc_transport_domain(mdev, priv->tdn); 3356 3357err_dealloc_pd: 3358 mlx5_core_dealloc_pd(mdev, priv->pdn); 3359 3360err_unmap_free_uar: 3361 mlx5_unmap_free_uar(mdev, &priv->cq_uar); 3362 3363err_free_sysctl: 3364 sysctl_ctx_free(&priv->sysctl_ctx); 3365 3366 if_free(ifp); 3367 3368err_free_priv: 3369 mlx5e_priv_mtx_destroy(priv); 3370 free(priv, M_MLX5EN); 3371 return (NULL); 3372} 3373 3374static void 3375mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv) 3376{ 3377 struct mlx5e_priv *priv = vpriv; 3378 struct ifnet *ifp = priv->ifp; 3379 3380 /* don't allow more IOCTLs */ 3381 priv->gone = 1; 3382 3383 /* 3384 * Clear the device description to avoid use after free, 3385 * because the bsddev is not destroyed when this module is 3386 * unloaded: 3387 */ 3388 device_set_desc(mdev->pdev->dev.bsddev, NULL); 3389 3390 /* XXX wait a bit to allow IOCTL handlers to complete */ 3391 pause("W", hz); 3392 3393 /* stop watchdog timer */ 3394 callout_drain(&priv->watchdog); 3395 3396 if (priv->vlan_attach != NULL) 3397 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach); 3398 if (priv->vlan_detach != NULL) 3399 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach); 3400 3401 /* make sure device gets closed */ 3402 PRIV_LOCK(priv); 3403 mlx5e_close_locked(ifp); 3404 PRIV_UNLOCK(priv); 3405 3406 /* unregister device */ 3407 ifmedia_removeall(&priv->media); 3408 ether_ifdetach(ifp); 3409 if_free(ifp); 3410 3411 /* destroy all remaining sysctl nodes */ 3412 if (priv->sysctl_debug) 3413 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx); 3414 sysctl_ctx_free(&priv->stats.vport.ctx); 3415 sysctl_ctx_free(&priv->stats.pport.ctx); 3416 sysctl_ctx_free(&priv->sysctl_ctx); 3417 3418 mlx5_core_destroy_mkey(priv->mdev, &priv->mr); 3419 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn); 3420 mlx5_core_dealloc_pd(priv->mdev, priv->pdn); 3421 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar); 3422 mlx5e_disable_async_events(priv); 3423 flush_scheduled_work(); 3424 mlx5e_priv_mtx_destroy(priv); 3425 free(priv, M_MLX5EN); 3426} 3427 3428static void * 3429mlx5e_get_ifp(void *vpriv) 3430{ 3431 struct mlx5e_priv *priv = vpriv; 3432 3433 return (priv->ifp); 3434} 3435 3436static struct mlx5_interface mlx5e_interface = { 3437 .add = mlx5e_create_ifp, 3438 .remove = mlx5e_destroy_ifp, 3439 .event = mlx5e_async_event, 3440 .protocol = MLX5_INTERFACE_PROTOCOL_ETH, 3441 .get_dev = mlx5e_get_ifp, 3442}; 3443 3444void 3445mlx5e_init(void) 3446{ 3447 mlx5_register_interface(&mlx5e_interface); 3448} 3449 3450void 3451mlx5e_cleanup(void) 3452{ 3453 mlx5_unregister_interface(&mlx5e_interface); 3454} 3455 3456module_init_order(mlx5e_init, SI_ORDER_THIRD); 3457module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD); 3458 3459#if (__FreeBSD_version >= 1100000) 3460MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1); 3461#endif 3462MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1); 3463MODULE_VERSION(mlx5en, 1); 3464