mlx5_en_main.c revision 308679
1258945Sroberto/*- 2280849Scy * Copyright (c) 2015 Mellanox Technologies. All rights reserved. 3258945Sroberto * 4258945Sroberto * Redistribution and use in source and binary forms, with or without 5258945Sroberto * modification, are permitted provided that the following conditions 6258945Sroberto * are met: 7258945Sroberto * 1. Redistributions of source code must retain the above copyright 8258945Sroberto * notice, this list of conditions and the following disclaimer. 9258945Sroberto * 2. Redistributions in binary form must reproduce the above copyright 10258945Sroberto * notice, this list of conditions and the following disclaimer in the 11258945Sroberto * documentation and/or other materials provided with the distribution. 12258945Sroberto * 13258945Sroberto * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14258945Sroberto * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15258945Sroberto * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16258945Sroberto * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17258945Sroberto * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18280849Scy * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19258945Sroberto * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20258945Sroberto * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21258945Sroberto * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22258945Sroberto * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23258945Sroberto * SUCH DAMAGE. 24258945Sroberto * 25258945Sroberto * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_en/mlx5_en_main.c 308679 2016-11-15 08:54:03Z hselasky $ 26258945Sroberto */ 27258945Sroberto 28258945Sroberto#include "en.h" 29258945Sroberto 30258945Sroberto#include <sys/sockio.h> 31258945Sroberto#include <machine/atomic.h> 32258945Sroberto 33258945Sroberto#define ETH_DRIVER_VERSION "3.1.0-dev" 34258945Srobertochar mlx5e_version[] = "Mellanox Ethernet driver" 35258945Sroberto " (" ETH_DRIVER_VERSION ")"; 36258945Sroberto 37258945Srobertostruct mlx5e_channel_param { 38258945Sroberto struct mlx5e_rq_param rq; 39258945Sroberto struct mlx5e_sq_param sq; 40258945Sroberto struct mlx5e_cq_param rx_cq; 41258945Sroberto struct mlx5e_cq_param tx_cq; 42258945Sroberto}; 43280849Scy 44280849Scystatic const struct { 45280849Scy u32 subtype; 46280849Scy u64 baudrate; 47280849Scy} mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = { 48280849Scy 49280849Scy [MLX5E_1000BASE_CX_SGMII] = { 50280849Scy .subtype = IFM_1000_CX_SGMII, 51280849Scy .baudrate = IF_Mbps(1000ULL), 52280849Scy }, 53280849Scy [MLX5E_1000BASE_KX] = { 54280849Scy .subtype = IFM_1000_KX, 55280849Scy .baudrate = IF_Mbps(1000ULL), 56280849Scy }, 57280849Scy [MLX5E_10GBASE_CX4] = { 58280849Scy .subtype = IFM_10G_CX4, 59280849Scy .baudrate = IF_Gbps(10ULL), 60280849Scy }, 61280849Scy [MLX5E_10GBASE_KX4] = { 62280849Scy .subtype = IFM_10G_KX4, 63280849Scy .baudrate = IF_Gbps(10ULL), 64280849Scy }, 65280849Scy [MLX5E_10GBASE_KR] = { 66280849Scy .subtype = IFM_10G_KR, 67258945Sroberto .baudrate = IF_Gbps(10ULL), 68258945Sroberto }, 69258945Sroberto [MLX5E_20GBASE_KR2] = { 70258945Sroberto .subtype = IFM_20G_KR2, 71258945Sroberto .baudrate = IF_Gbps(20ULL), 72258945Sroberto }, 73258945Sroberto [MLX5E_40GBASE_CR4] = { 74258945Sroberto .subtype = IFM_40G_CR4, 75258945Sroberto .baudrate = IF_Gbps(40ULL), 76258945Sroberto }, 77258945Sroberto [MLX5E_40GBASE_KR4] = { 78258945Sroberto .subtype = IFM_40G_KR4, 79258945Sroberto .baudrate = IF_Gbps(40ULL), 80258945Sroberto }, 81258945Sroberto [MLX5E_56GBASE_R4] = { 82258945Sroberto .subtype = IFM_56G_R4, 83258945Sroberto .baudrate = IF_Gbps(56ULL), 84258945Sroberto }, 85258945Sroberto [MLX5E_10GBASE_CR] = { 86258945Sroberto .subtype = IFM_10G_CR1, 87258945Sroberto .baudrate = IF_Gbps(10ULL), 88258945Sroberto }, 89258945Sroberto [MLX5E_10GBASE_SR] = { 90258945Sroberto .subtype = IFM_10G_SR, 91280849Scy .baudrate = IF_Gbps(10ULL), 92258945Sroberto }, 93258945Sroberto [MLX5E_10GBASE_LR] = { 94258945Sroberto .subtype = IFM_10G_LR, 95258945Sroberto .baudrate = IF_Gbps(10ULL), 96258945Sroberto }, 97258945Sroberto [MLX5E_40GBASE_SR4] = { 98258945Sroberto .subtype = IFM_40G_SR4, 99258945Sroberto .baudrate = IF_Gbps(40ULL), 100280849Scy }, 101280849Scy [MLX5E_40GBASE_LR4] = { 102280849Scy .subtype = IFM_40G_LR4, 103280849Scy .baudrate = IF_Gbps(40ULL), 104258945Sroberto }, 105280849Scy [MLX5E_100GBASE_CR4] = { 106280849Scy .subtype = IFM_100G_CR4, 107258945Sroberto .baudrate = IF_Gbps(100ULL), 108258945Sroberto }, 109258945Sroberto [MLX5E_100GBASE_SR4] = { 110258945Sroberto .subtype = IFM_100G_SR4, 111258945Sroberto .baudrate = IF_Gbps(100ULL), 112258945Sroberto }, 113258945Sroberto [MLX5E_100GBASE_KR4] = { 114258945Sroberto .subtype = IFM_100G_KR4, 115258945Sroberto .baudrate = IF_Gbps(100ULL), 116258945Sroberto }, 117258945Sroberto [MLX5E_100GBASE_LR4] = { 118258945Sroberto .subtype = IFM_100G_LR4, 119280849Scy .baudrate = IF_Gbps(100ULL), 120280849Scy }, 121280849Scy [MLX5E_100BASE_TX] = { 122258945Sroberto .subtype = IFM_100_TX, 123258945Sroberto .baudrate = IF_Mbps(100ULL), 124258945Sroberto }, 125280849Scy [MLX5E_100BASE_T] = { 126258945Sroberto .subtype = IFM_100_T, 127258945Sroberto .baudrate = IF_Mbps(100ULL), 128258945Sroberto }, 129258945Sroberto [MLX5E_10GBASE_T] = { 130258945Sroberto .subtype = IFM_10G_T, 131258945Sroberto .baudrate = IF_Gbps(10ULL), 132258945Sroberto }, 133280849Scy [MLX5E_25GBASE_CR] = { 134280849Scy .subtype = IFM_25G_CR, 135280849Scy .baudrate = IF_Gbps(25ULL), 136258945Sroberto }, 137280849Scy [MLX5E_25GBASE_KR] = { 138258945Sroberto .subtype = IFM_25G_KR, 139258945Sroberto .baudrate = IF_Gbps(25ULL), 140258945Sroberto }, 141258945Sroberto [MLX5E_25GBASE_SR] = { 142258945Sroberto .subtype = IFM_25G_SR, 143258945Sroberto .baudrate = IF_Gbps(25ULL), 144258945Sroberto }, 145258945Sroberto [MLX5E_50GBASE_CR2] = { 146280849Scy .subtype = IFM_50G_CR2, 147280849Scy .baudrate = IF_Gbps(50ULL), 148280849Scy }, 149280849Scy [MLX5E_50GBASE_KR2] = { 150258945Sroberto .subtype = IFM_50G_KR2, 151258945Sroberto .baudrate = IF_Gbps(50ULL), 152258945Sroberto }, 153280849Scy}; 154258945Sroberto 155258945SrobertoMALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet"); 156280849Scy 157258945Srobertostatic void 158258945Srobertomlx5e_update_carrier(struct mlx5e_priv *priv) 159280849Scy{ 160258945Sroberto struct mlx5_core_dev *mdev = priv->mdev; 161258945Sroberto u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 162258945Sroberto u32 eth_proto_oper; 163258945Sroberto int error; 164258945Sroberto u8 port_state; 165258945Sroberto u8 i; 166258945Sroberto 167258945Sroberto port_state = mlx5_query_vport_state(mdev, 168280849Scy MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0); 169280849Scy 170280849Scy if (port_state == VPORT_STATE_UP) { 171258945Sroberto priv->media_status_last |= IFM_ACTIVE; 172280849Scy } else { 173280849Scy priv->media_status_last &= ~IFM_ACTIVE; 174280849Scy priv->media_active_last = IFM_ETHER; 175280849Scy if_link_state_change(priv->ifp, LINK_STATE_DOWN); 176280849Scy return; 177280849Scy } 178280849Scy 179280849Scy error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN); 180280849Scy if (error) { 181280849Scy priv->media_active_last = IFM_ETHER; 182280849Scy priv->ifp->if_baudrate = 1; 183280849Scy if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n", 184280849Scy __func__, error); 185280849Scy return; 186280849Scy } 187280849Scy eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper); 188280849Scy 189280849Scy for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) { 190280849Scy if (mlx5e_mode_table[i].baudrate == 0) 191280849Scy continue; 192280849Scy if (MLX5E_PROT_MASK(i) & eth_proto_oper) { 193280849Scy priv->ifp->if_baudrate = 194280849Scy mlx5e_mode_table[i].baudrate; 195280849Scy priv->media_active_last = 196280849Scy mlx5e_mode_table[i].subtype | IFM_ETHER | IFM_FDX; 197280849Scy } 198280849Scy } 199280849Scy if_link_state_change(priv->ifp, LINK_STATE_UP); 200280849Scy} 201280849Scy 202280849Scystatic void 203280849Scymlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr) 204280849Scy{ 205280849Scy struct mlx5e_priv *priv = dev->if_softc; 206280849Scy 207280849Scy ifmr->ifm_status = priv->media_status_last; 208280849Scy ifmr->ifm_active = priv->media_active_last | 209280849Scy (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) | 210280849Scy (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0); 211280849Scy 212280849Scy} 213280849Scy 214280849Scystatic u32 215280849Scymlx5e_find_link_mode(u32 subtype) 216280849Scy{ 217280849Scy u32 i; 218280849Scy u32 link_mode = 0; 219280849Scy 220280849Scy for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) { 221280849Scy if (mlx5e_mode_table[i].baudrate == 0) 222280849Scy continue; 223280849Scy if (mlx5e_mode_table[i].subtype == subtype) 224280849Scy link_mode |= MLX5E_PROT_MASK(i); 225280849Scy } 226280849Scy 227280849Scy return (link_mode); 228280849Scy} 229280849Scy 230280849Scystatic int 231280849Scymlx5e_media_change(struct ifnet *dev) 232280849Scy{ 233280849Scy struct mlx5e_priv *priv = dev->if_softc; 234280849Scy struct mlx5_core_dev *mdev = priv->mdev; 235280849Scy u32 eth_proto_cap; 236280849Scy u32 link_mode; 237280849Scy int was_opened; 238280849Scy int locked; 239280849Scy int error; 240280849Scy 241280849Scy locked = PRIV_LOCKED(priv); 242280849Scy if (!locked) 243280849Scy PRIV_LOCK(priv); 244280849Scy 245280849Scy if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) { 246280849Scy error = EINVAL; 247280849Scy goto done; 248280849Scy } 249280849Scy link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media)); 250280849Scy 251280849Scy /* query supported capabilities */ 252280849Scy error = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN); 253280849Scy if (error != 0) { 254280849Scy if_printf(dev, "Query port media capability failed\n"); 255280849Scy goto done; 256280849Scy } 257280849Scy /* check for autoselect */ 258280849Scy if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) { 259280849Scy link_mode = eth_proto_cap; 260280849Scy if (link_mode == 0) { 261280849Scy if_printf(dev, "Port media capability is zero\n"); 262280849Scy error = EINVAL; 263280849Scy goto done; 264280849Scy } 265280849Scy } else { 266280849Scy link_mode = link_mode & eth_proto_cap; 267280849Scy if (link_mode == 0) { 268280849Scy if_printf(dev, "Not supported link mode requested\n"); 269280849Scy error = EINVAL; 270280849Scy goto done; 271280849Scy } 272280849Scy } 273280849Scy /* update pauseframe control bits */ 274280849Scy priv->params.rx_pauseframe_control = 275280849Scy (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0; 276280849Scy priv->params.tx_pauseframe_control = 277280849Scy (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0; 278280849Scy 279280849Scy /* check if device is opened */ 280280849Scy was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 281280849Scy 282280849Scy /* reconfigure the hardware */ 283280849Scy mlx5_set_port_status(mdev, MLX5_PORT_DOWN); 284280849Scy mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN); 285280849Scy mlx5_set_port_pause(mdev, 1, 286280849Scy priv->params.rx_pauseframe_control, 287280849Scy priv->params.tx_pauseframe_control); 288280849Scy if (was_opened) 289280849Scy mlx5_set_port_status(mdev, MLX5_PORT_UP); 290280849Scy 291280849Scydone: 292258945Sroberto if (!locked) 293258945Sroberto PRIV_UNLOCK(priv); 294258945Sroberto return (error); 295258945Sroberto} 296258945Sroberto 297280849Scystatic void 298280849Scymlx5e_update_carrier_work(struct work_struct *work) 299258945Sroberto{ 300258945Sroberto struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 301258945Sroberto update_carrier_work); 302258945Sroberto 303258945Sroberto PRIV_LOCK(priv); 304258945Sroberto if (test_bit(MLX5E_STATE_OPENED, &priv->state)) 305258945Sroberto mlx5e_update_carrier(priv); 306258945Sroberto PRIV_UNLOCK(priv); 307258945Sroberto} 308258945Sroberto 309280849Scystatic void 310258945Srobertomlx5e_update_pport_counters(struct mlx5e_priv *priv) 311258945Sroberto{ 312258945Sroberto struct mlx5_core_dev *mdev = priv->mdev; 313258945Sroberto struct mlx5e_pport_stats *s = &priv->stats.pport; 314258945Sroberto struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug; 315258945Sroberto u32 *in; 316258945Sroberto u32 *out; 317258945Sroberto u64 *ptr; 318258945Sroberto unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 319280849Scy unsigned x; 320258945Sroberto unsigned y; 321258945Sroberto 322258945Sroberto in = mlx5_vzalloc(sz); 323280849Scy out = mlx5_vzalloc(sz); 324280849Scy if (in == NULL || out == NULL) 325258945Sroberto goto free_out; 326258945Sroberto 327258945Sroberto ptr = (uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set); 328280849Scy 329280849Scy MLX5_SET(ppcnt_reg, in, local_port, 1); 330280849Scy 331258945Sroberto MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP); 332293423Sdelphij mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 333280849Scy for (x = y = 0; x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++) 334258945Sroberto s->arg[y] = be64toh(ptr[x]); 335258945Sroberto 336258945Sroberto MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP); 337258945Sroberto mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 338258945Sroberto for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++) 339258945Sroberto s->arg[y] = be64toh(ptr[x]); 340258945Sroberto for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM + 341258945Sroberto MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++) 342258945Sroberto s_debug->arg[y] = be64toh(ptr[x]); 343258945Sroberto 344258945Sroberto MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP); 345258945Sroberto mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 346258945Sroberto for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++) 347258945Sroberto s_debug->arg[y] = be64toh(ptr[x]); 348258945Sroberto 349280849Scy MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP); 350280849Scy mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 351280849Scy for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++) 352258945Sroberto s_debug->arg[y] = be64toh(ptr[x]); 353258945Srobertofree_out: 354258945Sroberto kvfree(in); 355258945Sroberto kvfree(out); 356258945Sroberto} 357258945Sroberto 358258945Srobertostatic void 359258945Srobertomlx5e_update_stats_work(struct work_struct *work) 360258945Sroberto{ 361258945Sroberto struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 362258945Sroberto update_stats_work); 363280849Scy struct mlx5_core_dev *mdev = priv->mdev; 364280849Scy struct mlx5e_vport_stats *s = &priv->stats.vport; 365280849Scy struct mlx5e_rq_stats *rq_stats; 366258945Sroberto struct mlx5e_sq_stats *sq_stats; 367258945Sroberto struct buf_ring *sq_br; 368258945Sroberto#if (__FreeBSD_version < 1100000) 369258945Sroberto struct ifnet *ifp = priv->ifp; 370258945Sroberto#endif 371258945Sroberto 372258945Sroberto u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)]; 373258945Sroberto u32 *out; 374258945Sroberto int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out); 375258945Sroberto u64 tso_packets = 0; 376258945Sroberto u64 tso_bytes = 0; 377258945Sroberto u64 tx_queue_dropped = 0; 378258945Sroberto u64 tx_defragged = 0; 379258945Sroberto u64 tx_offload_none = 0; 380258945Sroberto u64 lro_packets = 0; 381258945Sroberto u64 lro_bytes = 0; 382258945Sroberto u64 sw_lro_queued = 0; 383280849Scy u64 sw_lro_flushed = 0; 384280849Scy u64 rx_csum_none = 0; 385280849Scy u64 rx_wqe_err = 0; 386280849Scy u32 rx_out_of_buffer = 0; 387258945Sroberto int i; 388258945Sroberto int j; 389258945Sroberto 390258945Sroberto PRIV_LOCK(priv); 391280849Scy out = mlx5_vzalloc(outlen); 392280849Scy if (out == NULL) 393280849Scy goto free_out; 394258945Sroberto if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 395258945Sroberto goto free_out; 396258945Sroberto 397258945Sroberto /* Collect firts the SW counters and then HW for consistency */ 398258945Sroberto for (i = 0; i < priv->params.num_channels; i++) { 399258945Sroberto struct mlx5e_rq *rq = &priv->channel[i]->rq; 400258945Sroberto 401258945Sroberto rq_stats = &priv->channel[i]->rq.stats; 402258945Sroberto 403258945Sroberto /* collect stats from LRO */ 404258945Sroberto rq_stats->sw_lro_queued = rq->lro.lro_queued; 405258945Sroberto rq_stats->sw_lro_flushed = rq->lro.lro_flushed; 406258945Sroberto sw_lro_queued += rq_stats->sw_lro_queued; 407258945Sroberto sw_lro_flushed += rq_stats->sw_lro_flushed; 408280849Scy lro_packets += rq_stats->lro_packets; 409258945Sroberto lro_bytes += rq_stats->lro_bytes; 410258945Sroberto rx_csum_none += rq_stats->csum_none; 411258945Sroberto rx_wqe_err += rq_stats->wqe_err; 412280849Scy 413258945Sroberto for (j = 0; j < priv->num_tc; j++) { 414258945Sroberto sq_stats = &priv->channel[i]->sq[j].stats; 415258945Sroberto sq_br = priv->channel[i]->sq[j].br; 416258945Sroberto 417258945Sroberto tso_packets += sq_stats->tso_packets; 418258945Sroberto tso_bytes += sq_stats->tso_bytes; 419258945Sroberto tx_queue_dropped += sq_stats->dropped; 420258945Sroberto tx_queue_dropped += sq_br->br_drops; 421258945Sroberto tx_defragged += sq_stats->defragged; 422258945Sroberto tx_offload_none += sq_stats->csum_offload_none; 423258945Sroberto } 424258945Sroberto } 425258945Sroberto 426258945Sroberto /* update counters */ 427258945Sroberto s->tso_packets = tso_packets; 428258945Sroberto s->tso_bytes = tso_bytes; 429258945Sroberto s->tx_queue_dropped = tx_queue_dropped; 430258945Sroberto s->tx_defragged = tx_defragged; 431258945Sroberto s->lro_packets = lro_packets; 432258945Sroberto s->lro_bytes = lro_bytes; 433280849Scy s->sw_lro_queued = sw_lro_queued; 434258945Sroberto s->sw_lro_flushed = sw_lro_flushed; 435258945Sroberto s->rx_csum_none = rx_csum_none; 436258945Sroberto s->rx_wqe_err = rx_wqe_err; 437258945Sroberto 438258945Sroberto /* HW counters */ 439258945Sroberto memset(in, 0, sizeof(in)); 440258945Sroberto 441258945Sroberto MLX5_SET(query_vport_counter_in, in, opcode, 442258945Sroberto MLX5_CMD_OP_QUERY_VPORT_COUNTER); 443258945Sroberto MLX5_SET(query_vport_counter_in, in, op_mod, 0); 444258945Sroberto MLX5_SET(query_vport_counter_in, in, other_vport, 0); 445258945Sroberto 446258945Sroberto memset(out, 0, outlen); 447258945Sroberto 448258945Sroberto /* get number of out-of-buffer drops first */ 449280849Scy if (mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id, 450280849Scy &rx_out_of_buffer)) 451280849Scy goto free_out; 452280849Scy 453280849Scy /* accumulate difference into a 64-bit counter */ 454258945Sroberto s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer - s->rx_out_of_buffer_prev); 455280849Scy s->rx_out_of_buffer_prev = rx_out_of_buffer; 456280849Scy 457280849Scy /* get port statistics */ 458280849Scy if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen)) 459280849Scy goto free_out; 460258945Sroberto 461258945Sroberto#define MLX5_GET_CTR(out, x) \ 462258945Sroberto MLX5_GET64(query_vport_counter_out, out, x) 463258945Sroberto 464258945Sroberto s->rx_error_packets = 465258945Sroberto MLX5_GET_CTR(out, received_errors.packets); 466258945Sroberto s->rx_error_bytes = 467280849Scy MLX5_GET_CTR(out, received_errors.octets); 468280849Scy s->tx_error_packets = 469280849Scy MLX5_GET_CTR(out, transmit_errors.packets); 470280849Scy s->tx_error_bytes = 471280849Scy MLX5_GET_CTR(out, transmit_errors.octets); 472258945Sroberto 473258945Sroberto s->rx_unicast_packets = 474258945Sroberto MLX5_GET_CTR(out, received_eth_unicast.packets); 475258945Sroberto s->rx_unicast_bytes = 476280849Scy MLX5_GET_CTR(out, received_eth_unicast.octets); 477258945Sroberto s->tx_unicast_packets = 478258945Sroberto MLX5_GET_CTR(out, transmitted_eth_unicast.packets); 479258945Sroberto s->tx_unicast_bytes = 480258945Sroberto MLX5_GET_CTR(out, transmitted_eth_unicast.octets); 481258945Sroberto 482258945Sroberto s->rx_multicast_packets = 483258945Sroberto MLX5_GET_CTR(out, received_eth_multicast.packets); 484258945Sroberto s->rx_multicast_bytes = 485258945Sroberto MLX5_GET_CTR(out, received_eth_multicast.octets); 486258945Sroberto s->tx_multicast_packets = 487258945Sroberto MLX5_GET_CTR(out, transmitted_eth_multicast.packets); 488258945Sroberto s->tx_multicast_bytes = 489258945Sroberto MLX5_GET_CTR(out, transmitted_eth_multicast.octets); 490258945Sroberto 491258945Sroberto s->rx_broadcast_packets = 492258945Sroberto MLX5_GET_CTR(out, received_eth_broadcast.packets); 493258945Sroberto s->rx_broadcast_bytes = 494258945Sroberto MLX5_GET_CTR(out, received_eth_broadcast.octets); 495258945Sroberto s->tx_broadcast_packets = 496258945Sroberto MLX5_GET_CTR(out, transmitted_eth_broadcast.packets); 497258945Sroberto s->tx_broadcast_bytes = 498258945Sroberto MLX5_GET_CTR(out, transmitted_eth_broadcast.octets); 499258945Sroberto 500258945Sroberto s->rx_packets = 501258945Sroberto s->rx_unicast_packets + 502258945Sroberto s->rx_multicast_packets + 503258945Sroberto s->rx_broadcast_packets - 504280849Scy s->rx_out_of_buffer; 505280849Scy s->rx_bytes = 506280849Scy s->rx_unicast_bytes + 507258945Sroberto s->rx_multicast_bytes + 508258945Sroberto s->rx_broadcast_bytes; 509258945Sroberto s->tx_packets = 510258945Sroberto s->tx_unicast_packets + 511258945Sroberto s->tx_multicast_packets + 512258945Sroberto s->tx_broadcast_packets; 513258945Sroberto s->tx_bytes = 514280849Scy s->tx_unicast_bytes + 515258945Sroberto s->tx_multicast_bytes + 516258945Sroberto s->tx_broadcast_bytes; 517258945Sroberto 518258945Sroberto /* Update calculated offload counters */ 519258945Sroberto s->tx_csum_offload = s->tx_packets - tx_offload_none; 520258945Sroberto s->rx_csum_good = s->rx_packets - s->rx_csum_none; 521258945Sroberto 522258945Sroberto /* Update per port counters */ 523258945Sroberto mlx5e_update_pport_counters(priv); 524258945Sroberto 525258945Sroberto#if (__FreeBSD_version < 1100000) 526258945Sroberto /* no get_counters interface in fbsd 10 */ 527258945Sroberto ifp->if_ipackets = s->rx_packets; 528258945Sroberto ifp->if_ierrors = s->rx_error_packets; 529258945Sroberto ifp->if_iqdrops = s->rx_out_of_buffer; 530280849Scy ifp->if_opackets = s->tx_packets; 531258945Sroberto ifp->if_oerrors = s->tx_error_packets; 532258945Sroberto ifp->if_snd.ifq_drops = s->tx_queue_dropped; 533258945Sroberto ifp->if_ibytes = s->rx_bytes; 534258945Sroberto ifp->if_obytes = s->tx_bytes; 535258945Sroberto#endif 536258945Sroberto 537258945Srobertofree_out: 538258945Sroberto kvfree(out); 539258945Sroberto PRIV_UNLOCK(priv); 540258945Sroberto} 541258945Sroberto 542258945Srobertostatic void 543258945Srobertomlx5e_update_stats(void *arg) 544258945Sroberto{ 545258945Sroberto struct mlx5e_priv *priv = arg; 546258945Sroberto 547258945Sroberto schedule_work(&priv->update_stats_work); 548258945Sroberto 549258945Sroberto callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv); 550258945Sroberto} 551258945Sroberto 552258945Srobertostatic void 553258945Srobertomlx5e_async_event_sub(struct mlx5e_priv *priv, 554258945Sroberto enum mlx5_dev_event event) 555258945Sroberto{ 556258945Sroberto switch (event) { 557258945Sroberto case MLX5_DEV_EVENT_PORT_UP: 558258945Sroberto case MLX5_DEV_EVENT_PORT_DOWN: 559280849Scy schedule_work(&priv->update_carrier_work); 560280849Scy break; 561280849Scy 562258945Sroberto default: 563258945Sroberto break; 564258945Sroberto } 565258945Sroberto} 566258945Sroberto 567258945Srobertostatic void 568258945Srobertomlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv, 569258945Sroberto enum mlx5_dev_event event, unsigned long param) 570258945Sroberto{ 571258945Sroberto struct mlx5e_priv *priv = vpriv; 572258945Sroberto 573258945Sroberto mtx_lock(&priv->async_events_mtx); 574258945Sroberto if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state)) 575258945Sroberto mlx5e_async_event_sub(priv, event); 576258945Sroberto mtx_unlock(&priv->async_events_mtx); 577258945Sroberto} 578258945Sroberto 579258945Srobertostatic void 580258945Srobertomlx5e_enable_async_events(struct mlx5e_priv *priv) 581258945Sroberto{ 582258945Sroberto set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); 583258945Sroberto} 584258945Sroberto 585258945Srobertostatic void 586258945Srobertomlx5e_disable_async_events(struct mlx5e_priv *priv) 587258945Sroberto{ 588258945Sroberto mtx_lock(&priv->async_events_mtx); 589258945Sroberto clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); 590258945Sroberto mtx_unlock(&priv->async_events_mtx); 591258945Sroberto} 592258945Sroberto 593258945Srobertostatic const char *mlx5e_rq_stats_desc[] = { 594258945Sroberto MLX5E_RQ_STATS(MLX5E_STATS_DESC) 595258945Sroberto}; 596258945Sroberto 597258945Srobertostatic int 598258945Srobertomlx5e_create_rq(struct mlx5e_channel *c, 599258945Sroberto struct mlx5e_rq_param *param, 600258945Sroberto struct mlx5e_rq *rq) 601280849Scy{ 602280849Scy struct mlx5e_priv *priv = c->priv; 603258945Sroberto struct mlx5_core_dev *mdev = priv->mdev; 604280849Scy char buffer[16]; 605258945Sroberto void *rqc = param->rqc; 606258945Sroberto void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); 607258945Sroberto int wq_sz; 608258945Sroberto int err; 609258945Sroberto int i; 610258945Sroberto 611258945Sroberto /* Create DMA descriptor TAG */ 612280849Scy if ((err = -bus_dma_tag_create( 613258945Sroberto bus_get_dma_tag(mdev->pdev->dev.bsddev), 614258945Sroberto 1, /* any alignment */ 615258945Sroberto 0, /* no boundary */ 616258945Sroberto BUS_SPACE_MAXADDR, /* lowaddr */ 617258945Sroberto BUS_SPACE_MAXADDR, /* highaddr */ 618258945Sroberto NULL, NULL, /* filter, filterarg */ 619258945Sroberto MJUM16BYTES, /* maxsize */ 620258945Sroberto 1, /* nsegments */ 621258945Sroberto MJUM16BYTES, /* maxsegsize */ 622258945Sroberto 0, /* flags */ 623258945Sroberto NULL, NULL, /* lockfunc, lockfuncarg */ 624258945Sroberto &rq->dma_tag))) 625258945Sroberto goto done; 626258945Sroberto 627258945Sroberto err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq, 628258945Sroberto &rq->wq_ctrl); 629258945Sroberto if (err) 630258945Sroberto goto err_free_dma_tag; 631258945Sroberto 632258945Sroberto rq->wq.db = &rq->wq.db[MLX5_RCV_DBR]; 633258945Sroberto 634258945Sroberto if (priv->params.hw_lro_en) { 635258945Sroberto rq->wqe_sz = priv->params.lro_wqe_sz; 636258945Sroberto } else { 637258945Sroberto rq->wqe_sz = MLX5E_SW2MB_MTU(priv->ifp->if_mtu); 638280849Scy } 639258945Sroberto if (rq->wqe_sz > MJUM16BYTES) { 640258945Sroberto err = -ENOMEM; 641258945Sroberto goto err_rq_wq_destroy; 642258945Sroberto } else if (rq->wqe_sz > MJUM9BYTES) { 643258945Sroberto rq->wqe_sz = MJUM16BYTES; 644258945Sroberto } else if (rq->wqe_sz > MJUMPAGESIZE) { 645258945Sroberto rq->wqe_sz = MJUM9BYTES; 646258945Sroberto } else if (rq->wqe_sz > MCLBYTES) { 647258945Sroberto rq->wqe_sz = MJUMPAGESIZE; 648258945Sroberto } else { 649258945Sroberto rq->wqe_sz = MCLBYTES; 650258945Sroberto } 651258945Sroberto 652258945Sroberto wq_sz = mlx5_wq_ll_get_size(&rq->wq); 653258945Sroberto 654258945Sroberto err = -tcp_lro_init_args(&rq->lro, c->ifp, TCP_LRO_ENTRIES, wq_sz); 655258945Sroberto if (err) 656258945Sroberto goto err_rq_wq_destroy; 657258945Sroberto 658258945Sroberto rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO); 659258945Sroberto if (rq->mbuf == NULL) { 660258945Sroberto err = -ENOMEM; 661258945Sroberto goto err_lro_init; 662258945Sroberto } 663258945Sroberto for (i = 0; i != wq_sz; i++) { 664258945Sroberto struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i); 665258945Sroberto uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN; 666258945Sroberto 667258945Sroberto err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map); 668258945Sroberto if (err != 0) { 669258945Sroberto while (i--) 670258945Sroberto bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map); 671258945Sroberto goto err_rq_mbuf_free; 672258945Sroberto } 673258945Sroberto wqe->data.lkey = c->mkey_be; 674258945Sroberto wqe->data.byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING); 675258945Sroberto } 676258945Sroberto 677280849Scy rq->ifp = c->ifp; 678280849Scy rq->channel = c; 679280849Scy rq->ix = c->ix; 680258945Sroberto 681280849Scy snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix); 682258945Sroberto mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 683258945Sroberto buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM, 684258945Sroberto rq->stats.arg); 685258945Sroberto return (0); 686258945Sroberto 687258945Srobertoerr_rq_mbuf_free: 688258945Sroberto free(rq->mbuf, M_MLX5EN); 689258945Srobertoerr_lro_init: 690258945Sroberto tcp_lro_free(&rq->lro); 691258945Srobertoerr_rq_wq_destroy: 692258945Sroberto mlx5_wq_destroy(&rq->wq_ctrl); 693258945Srobertoerr_free_dma_tag: 694258945Sroberto bus_dma_tag_destroy(rq->dma_tag); 695258945Srobertodone: 696258945Sroberto return (err); 697258945Sroberto} 698258945Sroberto 699258945Srobertostatic void 700258945Srobertomlx5e_destroy_rq(struct mlx5e_rq *rq) 701258945Sroberto{ 702258945Sroberto int wq_sz; 703258945Sroberto int i; 704258945Sroberto 705258945Sroberto /* destroy all sysctl nodes */ 706258945Sroberto sysctl_ctx_free(&rq->stats.ctx); 707258945Sroberto 708258945Sroberto /* free leftover LRO packets, if any */ 709280849Scy tcp_lro_free(&rq->lro); 710280849Scy 711280849Scy wq_sz = mlx5_wq_ll_get_size(&rq->wq); 712258945Sroberto for (i = 0; i != wq_sz; i++) { 713258945Sroberto if (rq->mbuf[i].mbuf != NULL) { 714258945Sroberto bus_dmamap_unload(rq->dma_tag, 715258945Sroberto rq->mbuf[i].dma_map); 716258945Sroberto m_freem(rq->mbuf[i].mbuf); 717258945Sroberto } 718258945Sroberto bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map); 719280849Scy } 720258945Sroberto free(rq->mbuf, M_MLX5EN); 721258945Sroberto mlx5_wq_destroy(&rq->wq_ctrl); 722280849Scy} 723280849Scy 724280849Scystatic int 725258945Srobertomlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param) 726258945Sroberto{ 727258945Sroberto struct mlx5e_channel *c = rq->channel; 728258945Sroberto struct mlx5e_priv *priv = c->priv; 729258945Sroberto struct mlx5_core_dev *mdev = priv->mdev; 730258945Sroberto 731258945Sroberto void *in; 732258945Sroberto void *rqc; 733258945Sroberto void *wq; 734258945Sroberto int inlen; 735258945Sroberto int err; 736258945Sroberto 737258945Sroberto inlen = MLX5_ST_SZ_BYTES(create_rq_in) + 738258945Sroberto sizeof(u64) * rq->wq_ctrl.buf.npages; 739258945Sroberto in = mlx5_vzalloc(inlen); 740258945Sroberto if (in == NULL) 741258945Sroberto return (-ENOMEM); 742258945Sroberto 743258945Sroberto rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 744258945Sroberto wq = MLX5_ADDR_OF(rqc, rqc, wq); 745258945Sroberto 746258945Sroberto memcpy(rqc, param->rqc, sizeof(param->rqc)); 747258945Sroberto 748258945Sroberto MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn); 749258945Sroberto MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 750258945Sroberto MLX5_SET(rqc, rqc, flush_in_error_en, 1); 751258945Sroberto if (priv->counter_set_id >= 0) 752258945Sroberto MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id); 753258945Sroberto MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift - 754258945Sroberto PAGE_SHIFT); 755258945Sroberto MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma); 756258945Sroberto 757258945Sroberto mlx5_fill_page_array(&rq->wq_ctrl.buf, 758258945Sroberto (__be64 *) MLX5_ADDR_OF(wq, wq, pas)); 759258945Sroberto 760258945Sroberto err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn); 761258945Sroberto 762258945Sroberto kvfree(in); 763258945Sroberto 764258945Sroberto return (err); 765280849Scy} 766280849Scy 767280849Scystatic int 768280849Scymlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state) 769258945Sroberto{ 770258945Sroberto struct mlx5e_channel *c = rq->channel; 771258945Sroberto struct mlx5e_priv *priv = c->priv; 772258945Sroberto struct mlx5_core_dev *mdev = priv->mdev; 773258945Sroberto 774258945Sroberto void *in; 775258945Sroberto void *rqc; 776280849Scy int inlen; 777280849Scy int err; 778258945Sroberto 779258945Sroberto inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 780280849Scy in = mlx5_vzalloc(inlen); 781280849Scy if (in == NULL) 782280849Scy return (-ENOMEM); 783258945Sroberto 784258945Sroberto rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 785258945Sroberto 786258945Sroberto MLX5_SET(modify_rq_in, in, rqn, rq->rqn); 787258945Sroberto MLX5_SET(modify_rq_in, in, rq_state, curr_state); 788258945Sroberto MLX5_SET(rqc, rqc, state, next_state); 789258945Sroberto 790280849Scy err = mlx5_core_modify_rq(mdev, in, inlen); 791280849Scy 792258945Sroberto kvfree(in); 793258945Sroberto 794280849Scy return (err); 795280849Scy} 796280849Scy 797258945Srobertostatic void 798280849Scymlx5e_disable_rq(struct mlx5e_rq *rq) 799258945Sroberto{ 800258945Sroberto struct mlx5e_channel *c = rq->channel; 801258945Sroberto struct mlx5e_priv *priv = c->priv; 802258945Sroberto struct mlx5_core_dev *mdev = priv->mdev; 803258945Sroberto 804258945Sroberto mlx5_core_destroy_rq(mdev, rq->rqn); 805258945Sroberto} 806258945Sroberto 807258945Srobertostatic int 808258945Srobertomlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq) 809258945Sroberto{ 810258945Sroberto struct mlx5e_channel *c = rq->channel; 811258945Sroberto struct mlx5e_priv *priv = c->priv; 812258945Sroberto struct mlx5_wq_ll *wq = &rq->wq; 813258945Sroberto int i; 814258945Sroberto 815258945Sroberto for (i = 0; i < 1000; i++) { 816258945Sroberto if (wq->cur_sz >= priv->params.min_rx_wqes) 817258945Sroberto return (0); 818258945Sroberto 819258945Sroberto msleep(4); 820258945Sroberto } 821258945Sroberto return (-ETIMEDOUT); 822258945Sroberto} 823258945Sroberto 824258945Srobertostatic int 825258945Srobertomlx5e_open_rq(struct mlx5e_channel *c, 826258945Sroberto struct mlx5e_rq_param *param, 827258945Sroberto struct mlx5e_rq *rq) 828258945Sroberto{ 829258945Sroberto int err; 830258945Sroberto 831258945Sroberto err = mlx5e_create_rq(c, param, rq); 832258945Sroberto if (err) 833258945Sroberto return (err); 834280849Scy 835280849Scy err = mlx5e_enable_rq(rq, param); 836280849Scy if (err) 837258945Sroberto goto err_destroy_rq; 838258945Sroberto 839258945Sroberto err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 840258945Sroberto if (err) 841258945Sroberto goto err_disable_rq; 842258945Sroberto 843258945Sroberto c->rq.enabled = 1; 844258945Sroberto 845258945Sroberto return (0); 846258945Sroberto 847258945Srobertoerr_disable_rq: 848258945Sroberto mlx5e_disable_rq(rq); 849258945Srobertoerr_destroy_rq: 850258945Sroberto mlx5e_destroy_rq(rq); 851258945Sroberto 852258945Sroberto return (err); 853280849Scy} 854280849Scy 855258945Srobertostatic void 856258945Srobertomlx5e_close_rq(struct mlx5e_rq *rq) 857258945Sroberto{ 858258945Sroberto mtx_lock(&rq->mtx); 859258945Sroberto rq->enabled = 0; 860258945Sroberto callout_stop(&rq->watchdog); 861258945Sroberto mtx_unlock(&rq->mtx); 862258945Sroberto 863258945Sroberto callout_drain(&rq->watchdog); 864258945Sroberto 865258945Sroberto mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 866280849Scy} 867280849Scy 868280849Scystatic void 869258945Srobertomlx5e_close_rq_wait(struct mlx5e_rq *rq) 870258945Sroberto{ 871258945Sroberto /* wait till RQ is empty */ 872258945Sroberto while (!mlx5_wq_ll_is_empty(&rq->wq)) { 873258945Sroberto msleep(4); 874258945Sroberto rq->cq.mcq.comp(&rq->cq.mcq); 875258945Sroberto } 876258945Sroberto 877258945Sroberto mlx5e_disable_rq(rq); 878258945Sroberto mlx5e_destroy_rq(rq); 879258945Sroberto} 880258945Sroberto 881258945Srobertovoid 882258945Srobertomlx5e_free_sq_db(struct mlx5e_sq *sq) 883280849Scy{ 884280849Scy int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 885280849Scy int x; 886280849Scy 887280849Scy for (x = 0; x != wq_sz; x++) 888280849Scy bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map); 889258945Sroberto free(sq->mbuf, M_MLX5EN); 890258945Sroberto} 891258945Sroberto 892280849Scyint 893280849Scymlx5e_alloc_sq_db(struct mlx5e_sq *sq) 894280849Scy{ 895280849Scy int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 896280849Scy int err; 897280849Scy int x; 898258945Sroberto 899258945Sroberto sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO); 900258945Sroberto if (sq->mbuf == NULL) 901280849Scy return (-ENOMEM); 902280849Scy 903280849Scy /* Create DMA descriptor MAPs */ 904280849Scy for (x = 0; x != wq_sz; x++) { 905258945Sroberto err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map); 906258945Sroberto if (err != 0) { 907258945Sroberto while (x--) 908258945Sroberto bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map); 909258945Sroberto free(sq->mbuf, M_MLX5EN); 910258945Sroberto return (err); 911258945Sroberto } 912258945Sroberto } 913258945Sroberto return (0); 914258945Sroberto} 915258945Sroberto 916280849Scystatic const char *mlx5e_sq_stats_desc[] = { 917280849Scy MLX5E_SQ_STATS(MLX5E_STATS_DESC) 918280849Scy}; 919280849Scy 920280849Scystatic int 921280849Scymlx5e_create_sq(struct mlx5e_channel *c, 922280849Scy int tc, 923280849Scy struct mlx5e_sq_param *param, 924280849Scy struct mlx5e_sq *sq) 925280849Scy{ 926280849Scy struct mlx5e_priv *priv = c->priv; 927280849Scy struct mlx5_core_dev *mdev = priv->mdev; 928280849Scy char buffer[16]; 929280849Scy 930280849Scy void *sqc = param->sqc; 931280849Scy void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq); 932280849Scy#ifdef RSS 933280849Scy cpuset_t cpu_mask; 934280849Scy int cpu_id; 935280849Scy#endif 936280849Scy int err; 937280849Scy 938280849Scy /* Create DMA descriptor TAG */ 939280849Scy if ((err = -bus_dma_tag_create( 940280849Scy bus_get_dma_tag(mdev->pdev->dev.bsddev), 941280849Scy 1, /* any alignment */ 942280849Scy 0, /* no boundary */ 943280849Scy BUS_SPACE_MAXADDR, /* lowaddr */ 944280849Scy BUS_SPACE_MAXADDR, /* highaddr */ 945280849Scy NULL, NULL, /* filter, filterarg */ 946280849Scy MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */ 947280849Scy MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */ 948280849Scy MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */ 949280849Scy 0, /* flags */ 950280849Scy NULL, NULL, /* lockfunc, lockfuncarg */ 951280849Scy &sq->dma_tag))) 952280849Scy goto done; 953280849Scy 954280849Scy err = mlx5_alloc_map_uar(mdev, &sq->uar); 955280849Scy if (err) 956280849Scy goto err_free_dma_tag; 957280849Scy 958280849Scy err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, 959280849Scy &sq->wq_ctrl); 960280849Scy if (err) 961280849Scy goto err_unmap_free_uar; 962280849Scy 963280849Scy sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; 964280849Scy sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2; 965280849Scy 966280849Scy err = mlx5e_alloc_sq_db(sq); 967280849Scy if (err) 968280849Scy goto err_sq_wq_destroy; 969280849Scy 970280849Scy sq->mkey_be = c->mkey_be; 971280849Scy sq->ifp = priv->ifp; 972280849Scy sq->priv = priv; 973280849Scy sq->tc = tc; 974280849Scy 975280849Scy sq->br = buf_ring_alloc(MLX5E_SQ_TX_QUEUE_SIZE, M_MLX5EN, 976280849Scy M_WAITOK, &sq->lock); 977258945Sroberto if (sq->br == NULL) { 978280849Scy if_printf(c->ifp, "%s: Failed allocating sq drbr buffer\n", 979280849Scy __func__); 980280849Scy err = -ENOMEM; 981258945Sroberto goto err_free_sq_db; 982280849Scy } 983280849Scy 984280849Scy sq->sq_tq = taskqueue_create_fast("mlx5e_que", M_WAITOK, 985258945Sroberto taskqueue_thread_enqueue, &sq->sq_tq); 986258945Sroberto if (sq->sq_tq == NULL) { 987258945Sroberto if_printf(c->ifp, "%s: Failed allocating taskqueue\n", 988258945Sroberto __func__); 989258945Sroberto err = -ENOMEM; 990258945Sroberto goto err_free_drbr; 991258945Sroberto } 992258945Sroberto 993258945Sroberto TASK_INIT(&sq->sq_task, 0, mlx5e_tx_que, sq); 994258945Sroberto#ifdef RSS 995258945Sroberto cpu_id = rss_getcpu(c->ix % rss_getnumbuckets()); 996258945Sroberto CPU_SETOF(cpu_id, &cpu_mask); 997258945Sroberto taskqueue_start_threads_cpuset(&sq->sq_tq, 1, PI_NET, &cpu_mask, 998258945Sroberto "%s TX SQ%d.%d CPU%d", c->ifp->if_xname, c->ix, tc, cpu_id); 999258945Sroberto#else 1000258945Sroberto taskqueue_start_threads(&sq->sq_tq, 1, PI_NET, 1001258945Sroberto "%s TX SQ%d.%d", c->ifp->if_xname, c->ix, tc); 1002258945Sroberto#endif 1003258945Sroberto snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc); 1004258945Sroberto mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 1005258945Sroberto buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM, 1006258945Sroberto sq->stats.arg); 1007258945Sroberto 1008258945Sroberto return (0); 1009258945Sroberto 1010258945Srobertoerr_free_drbr: 1011258945Sroberto buf_ring_free(sq->br, M_MLX5EN); 1012258945Srobertoerr_free_sq_db: 1013258945Sroberto mlx5e_free_sq_db(sq); 1014258945Srobertoerr_sq_wq_destroy: 1015258945Sroberto mlx5_wq_destroy(&sq->wq_ctrl); 1016258945Sroberto 1017258945Srobertoerr_unmap_free_uar: 1018258945Sroberto mlx5_unmap_free_uar(mdev, &sq->uar); 1019258945Sroberto 1020258945Srobertoerr_free_dma_tag: 1021258945Sroberto bus_dma_tag_destroy(sq->dma_tag); 1022258945Srobertodone: 1023258945Sroberto return (err); 1024258945Sroberto} 1025258945Sroberto 1026258945Srobertostatic void 1027258945Srobertomlx5e_destroy_sq(struct mlx5e_sq *sq) 1028258945Sroberto{ 1029258945Sroberto /* destroy all sysctl nodes */ 1030258945Sroberto sysctl_ctx_free(&sq->stats.ctx); 1031258945Sroberto 1032258945Sroberto mlx5e_free_sq_db(sq); 1033258945Sroberto mlx5_wq_destroy(&sq->wq_ctrl); 1034258945Sroberto mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar); 1035258945Sroberto taskqueue_drain(sq->sq_tq, &sq->sq_task); 1036258945Sroberto taskqueue_free(sq->sq_tq); 1037258945Sroberto buf_ring_free(sq->br, M_MLX5EN); 1038280849Scy} 1039280849Scy 1040280849Scyint 1041258945Srobertomlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param, 1042258945Sroberto int tis_num) 1043280849Scy{ 1044258945Sroberto void *in; 1045280849Scy void *sqc; 1046258945Sroberto void *wq; 1047258945Sroberto int inlen; 1048258945Sroberto int err; 1049258945Sroberto 1050258945Sroberto inlen = MLX5_ST_SZ_BYTES(create_sq_in) + 1051258945Sroberto sizeof(u64) * sq->wq_ctrl.buf.npages; 1052280849Scy in = mlx5_vzalloc(inlen); 1053280849Scy if (in == NULL) 1054280849Scy return (-ENOMEM); 1055258945Sroberto 1056280849Scy sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1057280849Scy wq = MLX5_ADDR_OF(sqc, sqc, wq); 1058258945Sroberto 1059258945Sroberto memcpy(sqc, param->sqc, sizeof(param->sqc)); 1060258945Sroberto 1061258945Sroberto MLX5_SET(sqc, sqc, tis_num_0, tis_num); 1062258945Sroberto MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn); 1063258945Sroberto MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1064258945Sroberto MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1065258945Sroberto MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1066258945Sroberto 1067280849Scy MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1068258945Sroberto MLX5_SET(wq, wq, uar_page, sq->uar.index); 1069280849Scy MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift - 1070258945Sroberto PAGE_SHIFT); 1071280849Scy MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma); 1072258945Sroberto 1073258945Sroberto mlx5_fill_page_array(&sq->wq_ctrl.buf, 1074258945Sroberto (__be64 *) MLX5_ADDR_OF(wq, wq, pas)); 1075280849Scy 1076258945Sroberto err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn); 1077258945Sroberto 1078258945Sroberto kvfree(in); 1079258945Sroberto 1080258945Sroberto return (err); 1081258945Sroberto} 1082258945Sroberto 1083258945Srobertoint 1084258945Srobertomlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state) 1085258945Sroberto{ 1086258945Sroberto void *in; 1087258945Sroberto void *sqc; 1088258945Sroberto int inlen; 1089258945Sroberto int err; 1090258945Sroberto 1091258945Sroberto inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 1092258945Sroberto in = mlx5_vzalloc(inlen); 1093258945Sroberto if (in == NULL) 1094258945Sroberto return (-ENOMEM); 1095258945Sroberto 1096258945Sroberto sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1097258945Sroberto 1098258945Sroberto MLX5_SET(modify_sq_in, in, sqn, sq->sqn); 1099258945Sroberto MLX5_SET(modify_sq_in, in, sq_state, curr_state); 1100258945Sroberto MLX5_SET(sqc, sqc, state, next_state); 1101258945Sroberto 1102258945Sroberto err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen); 1103258945Sroberto 1104258945Sroberto kvfree(in); 1105258945Sroberto 1106258945Sroberto return (err); 1107258945Sroberto} 1108258945Sroberto 1109258945Srobertovoid 1110258945Srobertomlx5e_disable_sq(struct mlx5e_sq *sq) 1111258945Sroberto{ 1112258945Sroberto 1113280849Scy mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn); 1114280849Scy} 1115280849Scy 1116258945Srobertostatic int 1117258945Srobertomlx5e_open_sq(struct mlx5e_channel *c, 1118258945Sroberto int tc, 1119280849Scy struct mlx5e_sq_param *param, 1120258945Sroberto struct mlx5e_sq *sq) 1121280849Scy{ 1122258945Sroberto int err; 1123258945Sroberto 1124258945Sroberto err = mlx5e_create_sq(c, tc, param, sq); 1125258945Sroberto if (err) 1126258945Sroberto return (err); 1127258945Sroberto 1128258945Sroberto err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]); 1129258945Sroberto if (err) 1130258945Sroberto goto err_destroy_sq; 1131258945Sroberto 1132258945Sroberto err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY); 1133258945Sroberto if (err) 1134258945Sroberto goto err_disable_sq; 1135258945Sroberto 1136258945Sroberto atomic_store_rel_int(&sq->queue_state, MLX5E_SQ_READY); 1137258945Sroberto 1138258945Sroberto return (0); 1139258945Sroberto 1140258945Srobertoerr_disable_sq: 1141258945Sroberto mlx5e_disable_sq(sq); 1142258945Srobertoerr_destroy_sq: 1143258945Sroberto mlx5e_destroy_sq(sq); 1144258945Sroberto 1145258945Sroberto return (err); 1146258945Sroberto} 1147258945Sroberto 1148258945Srobertostatic void 1149258945Srobertomlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep) 1150258945Sroberto{ 1151258945Sroberto /* fill up remainder with NOPs */ 1152258945Sroberto while (sq->cev_counter != 0) { 1153258945Sroberto while (!mlx5e_sq_has_room_for(sq, 1)) { 1154258945Sroberto if (can_sleep != 0) { 1155258945Sroberto mtx_unlock(&sq->lock); 1156258945Sroberto msleep(4); 1157258945Sroberto mtx_lock(&sq->lock); 1158258945Sroberto } else { 1159258945Sroberto goto done; 1160258945Sroberto } 1161258945Sroberto } 1162258945Sroberto /* send a single NOP */ 1163258945Sroberto mlx5e_send_nop(sq, 1); 1164258945Sroberto wmb(); 1165258945Sroberto } 1166258945Srobertodone: 1167258945Sroberto /* Check if we need to write the doorbell */ 1168258945Sroberto if (likely(sq->doorbell.d64 != 0)) { 1169258945Sroberto mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0); 1170258945Sroberto sq->doorbell.d64 = 0; 1171258945Sroberto } 1172258945Sroberto return; 1173258945Sroberto} 1174258945Sroberto 1175258945Srobertovoid 1176258945Srobertomlx5e_sq_cev_timeout(void *arg) 1177258945Sroberto{ 1178258945Sroberto struct mlx5e_sq *sq = arg; 1179258945Sroberto 1180258945Sroberto mtx_assert(&sq->lock, MA_OWNED); 1181258945Sroberto 1182258945Sroberto /* check next state */ 1183258945Sroberto switch (sq->cev_next_state) { 1184258945Sroberto case MLX5E_CEV_STATE_SEND_NOPS: 1185258945Sroberto /* fill TX ring with NOPs, if any */ 1186258945Sroberto mlx5e_sq_send_nops_locked(sq, 0); 1187258945Sroberto 1188258945Sroberto /* check if completed */ 1189258945Sroberto if (sq->cev_counter == 0) { 1190258945Sroberto sq->cev_next_state = MLX5E_CEV_STATE_INITIAL; 1191258945Sroberto return; 1192258945Sroberto } 1193258945Sroberto break; 1194258945Sroberto default: 1195258945Sroberto /* send NOPs on next timeout */ 1196258945Sroberto sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS; 1197258945Sroberto break; 1198258945Sroberto } 1199258945Sroberto 1200258945Sroberto /* restart timer */ 1201258945Sroberto callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq); 1202258945Sroberto} 1203258945Sroberto 1204258945Srobertovoid 1205258945Srobertomlx5e_drain_sq(struct mlx5e_sq *sq) 1206280849Scy{ 1207258945Sroberto 1208258945Sroberto mtx_lock(&sq->lock); 1209258945Sroberto /* teardown event factor timer, if any */ 1210280849Scy sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS; 1211280849Scy callout_stop(&sq->cev_callout); 1212280849Scy 1213258945Sroberto /* send dummy NOPs in order to flush the transmit ring */ 1214280849Scy mlx5e_sq_send_nops_locked(sq, 1); 1215258945Sroberto mtx_unlock(&sq->lock); 1216258945Sroberto 1217258945Sroberto /* make sure it is safe to free the callout */ 1218258945Sroberto callout_drain(&sq->cev_callout); 1219258945Sroberto 1220258945Sroberto /* error out remaining requests */ 1221258945Sroberto mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR); 1222258945Sroberto 1223258945Sroberto /* wait till SQ is empty */ 1224258945Sroberto mtx_lock(&sq->lock); 1225258945Sroberto while (sq->cc != sq->pc) { 1226258945Sroberto mtx_unlock(&sq->lock); 1227258945Sroberto msleep(4); 1228258945Sroberto sq->cq.mcq.comp(&sq->cq.mcq); 1229258945Sroberto mtx_lock(&sq->lock); 1230258945Sroberto } 1231258945Sroberto mtx_unlock(&sq->lock); 1232258945Sroberto} 1233258945Sroberto 1234258945Srobertostatic void 1235280849Scymlx5e_close_sq_wait(struct mlx5e_sq *sq) 1236280849Scy{ 1237258945Sroberto 1238280849Scy mlx5e_drain_sq(sq); 1239280849Scy mlx5e_disable_sq(sq); 1240280849Scy mlx5e_destroy_sq(sq); 1241280849Scy} 1242258945Sroberto 1243258945Srobertostatic int 1244258945Srobertomlx5e_create_cq(struct mlx5e_priv *priv, 1245280849Scy struct mlx5e_cq_param *param, 1246280849Scy struct mlx5e_cq *cq, 1247280849Scy mlx5e_cq_comp_t *comp, 1248280849Scy int eq_ix) 1249280849Scy{ 1250280849Scy struct mlx5_core_dev *mdev = priv->mdev; 1251280849Scy struct mlx5_core_cq *mcq = &cq->mcq; 1252280849Scy int eqn_not_used; 1253280849Scy int irqn; 1254280849Scy int err; 1255280849Scy u32 i; 1256280849Scy 1257280849Scy param->wq.buf_numa_node = 0; 1258280849Scy param->wq.db_numa_node = 0; 1259258945Sroberto 1260280849Scy err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, 1261280849Scy &cq->wq_ctrl); 1262280849Scy if (err) 1263280849Scy return (err); 1264280849Scy 1265280849Scy mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn); 1266280849Scy 1267258945Sroberto mcq->cqe_sz = 64; 1268280849Scy mcq->set_ci_db = cq->wq_ctrl.db.db; 1269258945Sroberto mcq->arm_db = cq->wq_ctrl.db.db + 1; 1270258945Sroberto *mcq->set_ci_db = 0; 1271258945Sroberto *mcq->arm_db = 0; 1272280849Scy mcq->vector = eq_ix; 1273258945Sroberto mcq->comp = comp; 1274258945Sroberto mcq->event = mlx5e_cq_error_event; 1275258945Sroberto mcq->irqn = irqn; 1276258945Sroberto mcq->uar = &priv->cq_uar; 1277258945Sroberto 1278280849Scy for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { 1279258945Sroberto struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); 1280258945Sroberto 1281258945Sroberto cqe->op_own = 0xf1; 1282258945Sroberto } 1283258945Sroberto 1284258945Sroberto cq->priv = priv; 1285258945Sroberto 1286258945Sroberto return (0); 1287258945Sroberto} 1288280849Scy 1289280849Scystatic void 1290280849Scymlx5e_destroy_cq(struct mlx5e_cq *cq) 1291280849Scy{ 1292258945Sroberto mlx5_wq_destroy(&cq->wq_ctrl); 1293258945Sroberto} 1294280849Scy 1295258945Srobertostatic int 1296258945Srobertomlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix) 1297280849Scy{ 1298258945Sroberto struct mlx5_core_cq *mcq = &cq->mcq; 1299258945Sroberto void *in; 1300280849Scy void *cqc; 1301280849Scy int inlen; 1302258945Sroberto int irqn_not_used; 1303258945Sroberto int eqn; 1304280849Scy int err; 1305258945Sroberto 1306280849Scy inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 1307280849Scy sizeof(u64) * cq->wq_ctrl.buf.npages; 1308280849Scy in = mlx5_vzalloc(inlen); 1309280849Scy if (in == NULL) 1310280849Scy return (-ENOMEM); 1311258945Sroberto 1312258945Sroberto cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1313258945Sroberto 1314280849Scy memcpy(cqc, param->cqc, sizeof(param->cqc)); 1315280849Scy 1316280849Scy mlx5_fill_page_array(&cq->wq_ctrl.buf, 1317280849Scy (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas)); 1318258945Sroberto 1319258945Sroberto mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used); 1320280849Scy 1321280849Scy MLX5_SET(cqc, cqc, c_eqn, eqn); 1322280849Scy MLX5_SET(cqc, cqc, uar_page, mcq->uar->index); 1323258945Sroberto MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - 1324258945Sroberto PAGE_SHIFT); 1325258945Sroberto MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); 1326280849Scy 1327258945Sroberto err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen); 1328258945Sroberto 1329258945Sroberto kvfree(in); 1330258945Sroberto 1331258945Sroberto if (err) 1332258945Sroberto return (err); 1333258945Sroberto 1334258945Sroberto mlx5e_cq_arm(cq); 1335280849Scy 1336258945Sroberto return (0); 1337258945Sroberto} 1338280849Scy 1339258945Srobertostatic void 1340280849Scymlx5e_disable_cq(struct mlx5e_cq *cq) 1341258945Sroberto{ 1342280849Scy 1343280849Scy mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq); 1344258945Sroberto} 1345280849Scy 1346258945Srobertoint 1347258945Srobertomlx5e_open_cq(struct mlx5e_priv *priv, 1348280849Scy struct mlx5e_cq_param *param, 1349258945Sroberto struct mlx5e_cq *cq, 1350258945Sroberto mlx5e_cq_comp_t *comp, 1351258945Sroberto int eq_ix) 1352258945Sroberto{ 1353280849Scy int err; 1354280849Scy 1355280849Scy err = mlx5e_create_cq(priv, param, cq, comp, eq_ix); 1356280849Scy if (err) 1357258945Sroberto return (err); 1358258945Sroberto 1359258945Sroberto err = mlx5e_enable_cq(cq, param, eq_ix); 1360258945Sroberto if (err) 1361280849Scy goto err_destroy_cq; 1362258945Sroberto 1363280849Scy return (0); 1364258945Sroberto 1365258945Srobertoerr_destroy_cq: 1366258945Sroberto mlx5e_destroy_cq(cq); 1367258945Sroberto 1368258945Sroberto return (err); 1369258945Sroberto} 1370258945Sroberto 1371258945Srobertovoid 1372258945Srobertomlx5e_close_cq(struct mlx5e_cq *cq) 1373258945Sroberto{ 1374258945Sroberto mlx5e_disable_cq(cq); 1375258945Sroberto mlx5e_destroy_cq(cq); 1376258945Sroberto} 1377258945Sroberto 1378258945Srobertostatic int 1379258945Srobertomlx5e_open_tx_cqs(struct mlx5e_channel *c, 1380258945Sroberto struct mlx5e_channel_param *cparam) 1381258945Sroberto{ 1382258945Sroberto int err; 1383258945Sroberto int tc; 1384258945Sroberto 1385258945Sroberto for (tc = 0; tc < c->num_tc; tc++) { 1386258945Sroberto /* open completion queue */ 1387280849Scy err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq, 1388280849Scy &mlx5e_tx_cq_comp, c->ix); 1389280849Scy if (err) 1390280849Scy goto err_close_tx_cqs; 1391280849Scy } 1392280849Scy return (0); 1393280849Scy 1394280849Scyerr_close_tx_cqs: 1395280849Scy for (tc--; tc >= 0; tc--) 1396258945Sroberto mlx5e_close_cq(&c->sq[tc].cq); 1397258945Sroberto 1398258945Sroberto return (err); 1399258945Sroberto} 1400258945Sroberto 1401280849Scystatic void 1402258945Srobertomlx5e_close_tx_cqs(struct mlx5e_channel *c) 1403258945Sroberto{ 1404280849Scy int tc; 1405258945Sroberto 1406258945Sroberto for (tc = 0; tc < c->num_tc; tc++) 1407258945Sroberto mlx5e_close_cq(&c->sq[tc].cq); 1408258945Sroberto} 1409280849Scy 1410258945Srobertostatic int 1411258945Srobertomlx5e_open_sqs(struct mlx5e_channel *c, 1412258945Sroberto struct mlx5e_channel_param *cparam) 1413258945Sroberto{ 1414258945Sroberto int err; 1415258945Sroberto int tc; 1416258945Sroberto 1417258945Sroberto for (tc = 0; tc < c->num_tc; tc++) { 1418258945Sroberto err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]); 1419258945Sroberto if (err) 1420258945Sroberto goto err_close_sqs; 1421258945Sroberto } 1422258945Sroberto 1423258945Sroberto return (0); 1424258945Sroberto 1425258945Srobertoerr_close_sqs: 1426258945Sroberto for (tc--; tc >= 0; tc--) 1427258945Sroberto mlx5e_close_sq_wait(&c->sq[tc]); 1428280849Scy 1429280849Scy return (err); 1430258945Sroberto} 1431280849Scy 1432258945Srobertostatic void 1433280849Scymlx5e_close_sqs_wait(struct mlx5e_channel *c) 1434258945Sroberto{ 1435280849Scy int tc; 1436258945Sroberto 1437258945Sroberto for (tc = 0; tc < c->num_tc; tc++) 1438258945Sroberto mlx5e_close_sq_wait(&c->sq[tc]); 1439280849Scy} 1440280849Scy 1441280849Scystatic void 1442258945Srobertomlx5e_chan_mtx_init(struct mlx5e_channel *c) 1443258945Sroberto{ 1444258945Sroberto int tc; 1445258945Sroberto 1446258945Sroberto mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF); 1447280849Scy 1448258945Sroberto callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0); 1449258945Sroberto 1450258945Sroberto for (tc = 0; tc < c->num_tc; tc++) { 1451258945Sroberto struct mlx5e_sq *sq = c->sq + tc; 1452258945Sroberto 1453258945Sroberto mtx_init(&sq->lock, "mlx5tx", MTX_NETWORK_LOCK, MTX_DEF); 1454258945Sroberto mtx_init(&sq->comp_lock, "mlx5comp", MTX_NETWORK_LOCK, 1455280849Scy MTX_DEF); 1456280849Scy 1457280849Scy callout_init_mtx(&sq->cev_callout, &sq->lock, 0); 1458280849Scy 1459258945Sroberto sq->cev_factor = c->priv->params_ethtool.tx_completion_fact; 1460258945Sroberto 1461258945Sroberto /* ensure the TX completion event factor is not zero */ 1462258945Sroberto if (sq->cev_factor == 0) 1463258945Sroberto sq->cev_factor = 1; 1464258945Sroberto } 1465258945Sroberto} 1466293423Sdelphij 1467258945Srobertostatic void 1468258945Srobertomlx5e_chan_mtx_destroy(struct mlx5e_channel *c) 1469280849Scy{ 1470258945Sroberto int tc; 1471280849Scy 1472258945Sroberto mtx_destroy(&c->rq.mtx); 1473280849Scy 1474280849Scy for (tc = 0; tc < c->num_tc; tc++) { 1475280849Scy mtx_destroy(&c->sq[tc].lock); 1476258945Sroberto mtx_destroy(&c->sq[tc].comp_lock); 1477258945Sroberto } 1478258945Sroberto} 1479280849Scy 1480258945Srobertostatic int 1481258945Srobertomlx5e_open_channel(struct mlx5e_priv *priv, int ix, 1482258945Sroberto struct mlx5e_channel_param *cparam, 1483258945Sroberto struct mlx5e_channel *volatile *cp) 1484258945Sroberto{ 1485258945Sroberto struct mlx5e_channel *c; 1486258945Sroberto int err; 1487258945Sroberto 1488258945Sroberto c = malloc(sizeof(*c), M_MLX5EN, M_WAITOK | M_ZERO); 1489258945Sroberto if (c == NULL) 1490258945Sroberto return (-ENOMEM); 1491258945Sroberto 1492258945Sroberto c->priv = priv; 1493258945Sroberto c->ix = ix; 1494258945Sroberto c->cpu = 0; 1495258945Sroberto c->ifp = priv->ifp; 1496258945Sroberto c->mkey_be = cpu_to_be32(priv->mr.key); 1497258945Sroberto c->num_tc = priv->num_tc; 1498258945Sroberto 1499258945Sroberto /* init mutexes */ 1500258945Sroberto mlx5e_chan_mtx_init(c); 1501258945Sroberto 1502258945Sroberto /* open transmit completion queue */ 1503258945Sroberto err = mlx5e_open_tx_cqs(c, cparam); 1504258945Sroberto if (err) 1505258945Sroberto goto err_free; 1506258945Sroberto 1507258945Sroberto /* open receive completion queue */ 1508280849Scy err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq, 1509280849Scy &mlx5e_rx_cq_comp, c->ix); 1510280849Scy if (err) 1511280849Scy goto err_close_tx_cqs; 1512280849Scy 1513258945Sroberto err = mlx5e_open_sqs(c, cparam); 1514258945Sroberto if (err) 1515258945Sroberto goto err_close_rx_cq; 1516258945Sroberto 1517258945Sroberto err = mlx5e_open_rq(c, &cparam->rq, &c->rq); 1518258945Sroberto if (err) 1519258945Sroberto goto err_close_sqs; 1520258945Sroberto 1521280849Scy /* store channel pointer */ 1522258945Sroberto *cp = c; 1523258945Sroberto 1524280849Scy /* poll receive queue initially */ 1525258945Sroberto c->rq.cq.mcq.comp(&c->rq.cq.mcq); 1526258945Sroberto 1527258945Sroberto return (0); 1528258945Sroberto 1529258945Srobertoerr_close_sqs: 1530258945Sroberto mlx5e_close_sqs_wait(c); 1531258945Sroberto 1532258945Srobertoerr_close_rx_cq: 1533258945Sroberto mlx5e_close_cq(&c->rq.cq); 1534258945Sroberto 1535258945Srobertoerr_close_tx_cqs: 1536258945Sroberto mlx5e_close_tx_cqs(c); 1537258945Sroberto 1538280849Scyerr_free: 1539258945Sroberto /* destroy mutexes */ 1540258945Sroberto mlx5e_chan_mtx_destroy(c); 1541258945Sroberto free(c, M_MLX5EN); 1542258945Sroberto return (err); 1543280849Scy} 1544280849Scy 1545280849Scystatic void 1546258945Srobertomlx5e_close_channel(struct mlx5e_channel *volatile *pp) 1547258945Sroberto{ 1548280849Scy struct mlx5e_channel *c = *pp; 1549258945Sroberto 1550280849Scy /* check if channel is already closed */ 1551280849Scy if (c == NULL) 1552280849Scy return; 1553280849Scy mlx5e_close_rq(&c->rq); 1554258945Sroberto} 1555258945Sroberto 1556258945Srobertostatic void 1557258945Srobertomlx5e_close_channel_wait(struct mlx5e_channel *volatile *pp) 1558258945Sroberto{ 1559258945Sroberto struct mlx5e_channel *c = *pp; 1560280849Scy 1561280849Scy /* check if channel is already closed */ 1562293423Sdelphij if (c == NULL) 1563280849Scy return; 1564280849Scy /* ensure channel pointer is no longer used */ 1565280849Scy *pp = NULL; 1566280849Scy 1567280849Scy mlx5e_close_rq_wait(&c->rq); 1568280849Scy mlx5e_close_sqs_wait(c); 1569280849Scy mlx5e_close_cq(&c->rq.cq); 1570280849Scy mlx5e_close_tx_cqs(c); 1571293423Sdelphij /* destroy mutexes */ 1572280849Scy mlx5e_chan_mtx_destroy(c); 1573280849Scy free(c, M_MLX5EN); 1574280849Scy} 1575280849Scy 1576280849Scystatic void 1577280849Scymlx5e_build_rq_param(struct mlx5e_priv *priv, 1578280849Scy struct mlx5e_rq_param *param) 1579280849Scy{ 1580258945Sroberto void *rqc = param->rqc; 1581280849Scy void *wq = MLX5_ADDR_OF(rqc, rqc, wq); 1582293423Sdelphij 1583280849Scy MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); 1584280849Scy MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1585280849Scy MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe))); 1586280849Scy MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size); 1587280849Scy MLX5_SET(wq, wq, pd, priv->pdn); 1588280849Scy 1589280849Scy param->wq.buf_numa_node = 0; 1590258945Sroberto param->wq.db_numa_node = 0; 1591280849Scy param->wq.linear = 1; 1592280849Scy} 1593280849Scy 1594280849Scystatic void 1595280849Scymlx5e_build_sq_param(struct mlx5e_priv *priv, 1596280849Scy struct mlx5e_sq_param *param) 1597258945Sroberto{ 1598258945Sroberto void *sqc = param->sqc; 1599258945Sroberto void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 1600280849Scy 1601293423Sdelphij MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size); 1602258945Sroberto MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1603280849Scy MLX5_SET(wq, wq, pd, priv->pdn); 1604280849Scy 1605280849Scy param->wq.buf_numa_node = 0; 1606280849Scy param->wq.db_numa_node = 0; 1607280849Scy param->wq.linear = 1; 1608258945Sroberto} 1609258945Sroberto 1610258945Srobertostatic void 1611258945Srobertomlx5e_build_common_cq_param(struct mlx5e_priv *priv, 1612258945Sroberto struct mlx5e_cq_param *param) 1613258945Sroberto{ 1614258945Sroberto void *cqc = param->cqc; 1615280849Scy 1616280849Scy MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index); 1617280849Scy} 1618293423Sdelphij 1619280849Scystatic void 1620280849Scymlx5e_build_rx_cq_param(struct mlx5e_priv *priv, 1621280849Scy struct mlx5e_cq_param *param) 1622280849Scy{ 1623280849Scy void *cqc = param->cqc; 1624280849Scy 1625280849Scy 1626258945Sroberto /* 1627280849Scy * TODO The sysctl to control on/off is a bool value for now, which means 1628280849Scy * we only support CSUM, once HASH is implemnted we'll need to address that. 1629293423Sdelphij */ 1630280849Scy if (priv->params.cqe_zipping_en) { 1631280849Scy MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM); 1632280849Scy MLX5_SET(cqc, cqc, cqe_compression_en, 1); 1633280849Scy } 1634280849Scy 1635280849Scy MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size); 1636280849Scy MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec); 1637280849Scy MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts); 1638280849Scy 1639280849Scy switch (priv->params.rx_cq_moderation_mode) { 1640280849Scy case 0: 1641280849Scy MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 1642280849Scy break; 1643280849Scy default: 1644280849Scy if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 1645258945Sroberto MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 1646258945Sroberto else 1647258945Sroberto MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 1648258945Sroberto break; 1649258945Sroberto } 1650258945Sroberto 1651258945Sroberto mlx5e_build_common_cq_param(priv, param); 1652258945Sroberto} 1653258945Sroberto 1654258945Srobertostatic void 1655258945Srobertomlx5e_build_tx_cq_param(struct mlx5e_priv *priv, 1656258945Sroberto struct mlx5e_cq_param *param) 1657280849Scy{ 1658258945Sroberto void *cqc = param->cqc; 1659258945Sroberto 1660258945Sroberto MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size); 1661258945Sroberto MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec); 1662280849Scy MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts); 1663280849Scy 1664280849Scy switch (priv->params.tx_cq_moderation_mode) { 1665280849Scy case 0: 1666280849Scy MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 1667280849Scy break; 1668258945Sroberto default: 1669258945Sroberto if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 1670258945Sroberto MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 1671258945Sroberto else 1672258945Sroberto MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 1673258945Sroberto break; 1674258945Sroberto } 1675280849Scy 1676258945Sroberto mlx5e_build_common_cq_param(priv, param); 1677258945Sroberto} 1678258945Sroberto 1679280849Scystatic void 1680280849Scymlx5e_build_channel_param(struct mlx5e_priv *priv, 1681280849Scy struct mlx5e_channel_param *cparam) 1682280849Scy{ 1683280849Scy memset(cparam, 0, sizeof(*cparam)); 1684258945Sroberto 1685280849Scy mlx5e_build_rq_param(priv, &cparam->rq); 1686280849Scy mlx5e_build_sq_param(priv, &cparam->sq); 1687280849Scy mlx5e_build_rx_cq_param(priv, &cparam->rx_cq); 1688280849Scy mlx5e_build_tx_cq_param(priv, &cparam->tx_cq); 1689280849Scy} 1690280849Scy 1691280849Scystatic int 1692280849Scymlx5e_open_channels(struct mlx5e_priv *priv) 1693280849Scy{ 1694280849Scy struct mlx5e_channel_param cparam; 1695280849Scy void *ptr; 1696280849Scy int err; 1697280849Scy int i; 1698280849Scy int j; 1699280849Scy 1700280849Scy priv->channel = malloc(priv->params.num_channels * 1701280849Scy sizeof(struct mlx5e_channel *), M_MLX5EN, M_WAITOK | M_ZERO); 1702280849Scy if (priv->channel == NULL) 1703280849Scy return (-ENOMEM); 1704280849Scy 1705280849Scy mlx5e_build_channel_param(priv, &cparam); 1706280849Scy for (i = 0; i < priv->params.num_channels; i++) { 1707280849Scy err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]); 1708280849Scy if (err) 1709280849Scy goto err_close_channels; 1710280849Scy } 1711280849Scy 1712280849Scy for (j = 0; j < priv->params.num_channels; j++) { 1713280849Scy err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq); 1714280849Scy if (err) 1715280849Scy goto err_close_channels; 1716280849Scy } 1717280849Scy 1718280849Scy return (0); 1719280849Scy 1720280849Scyerr_close_channels: 1721280849Scy for (i--; i >= 0; i--) { 1722280849Scy mlx5e_close_channel(&priv->channel[i]); 1723280849Scy mlx5e_close_channel_wait(&priv->channel[i]); 1724280849Scy } 1725280849Scy 1726280849Scy /* remove "volatile" attribute from "channel" pointer */ 1727280849Scy ptr = __DECONST(void *, priv->channel); 1728280849Scy priv->channel = NULL; 1729280849Scy 1730280849Scy free(ptr, M_MLX5EN); 1731280849Scy 1732280849Scy return (err); 1733280849Scy} 1734258945Sroberto 1735280849Scystatic void 1736280849Scymlx5e_close_channels(struct mlx5e_priv *priv) 1737280849Scy{ 1738258945Sroberto void *ptr; 1739258945Sroberto int i; 1740258945Sroberto 1741258945Sroberto if (priv->channel == NULL) 1742258945Sroberto return; 1743258945Sroberto 1744258945Sroberto for (i = 0; i < priv->params.num_channels; i++) 1745258945Sroberto mlx5e_close_channel(&priv->channel[i]); 1746258945Sroberto for (i = 0; i < priv->params.num_channels; i++) 1747258945Sroberto mlx5e_close_channel_wait(&priv->channel[i]); 1748258945Sroberto 1749258945Sroberto /* remove "volatile" attribute from "channel" pointer */ 1750258945Sroberto ptr = __DECONST(void *, priv->channel); 1751258945Sroberto priv->channel = NULL; 1752258945Sroberto 1753258945Sroberto free(ptr, M_MLX5EN); 1754258945Sroberto} 1755258945Sroberto 1756258945Srobertostatic int 1757258945Srobertomlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq) 1758258945Sroberto{ 1759258945Sroberto return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq, 1760258945Sroberto priv->params.tx_cq_moderation_usec, 1761258945Sroberto priv->params.tx_cq_moderation_pkts)); 1762258945Sroberto} 1763258945Sroberto 1764258945Srobertostatic int 1765258945Srobertomlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq) 1766258945Sroberto{ 1767258945Sroberto return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq, 1768258945Sroberto priv->params.rx_cq_moderation_usec, 1769258945Sroberto priv->params.rx_cq_moderation_pkts)); 1770258945Sroberto} 1771258945Sroberto 1772258945Srobertostatic int 1773258945Srobertomlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c) 1774258945Sroberto{ 1775258945Sroberto int err; 1776258945Sroberto int i; 1777258945Sroberto 1778258945Sroberto if (c == NULL) 1779258945Sroberto return (EINVAL); 1780258945Sroberto 1781258945Sroberto err = mlx5e_refresh_rq_params(priv, &c->rq); 1782258945Sroberto if (err) 1783258945Sroberto goto done; 1784258945Sroberto 1785258945Sroberto for (i = 0; i != c->num_tc; i++) { 1786258945Sroberto err = mlx5e_refresh_sq_params(priv, &c->sq[i]); 1787258945Sroberto if (err) 1788258945Sroberto goto done; 1789258945Sroberto } 1790258945Srobertodone: 1791258945Sroberto return (err); 1792258945Sroberto} 1793258945Sroberto 1794258945Srobertoint 1795258945Srobertomlx5e_refresh_channel_params(struct mlx5e_priv *priv) 1796258945Sroberto{ 1797258945Sroberto int i; 1798258945Sroberto 1799258945Sroberto if (priv->channel == NULL) 1800258945Sroberto return (EINVAL); 1801258945Sroberto 1802258945Sroberto for (i = 0; i < priv->params.num_channels; i++) { 1803258945Sroberto int err; 1804258945Sroberto 1805258945Sroberto err = mlx5e_refresh_channel_params_sub(priv, priv->channel[i]); 1806258945Sroberto if (err) 1807258945Sroberto return (err); 1808258945Sroberto } 1809258945Sroberto return (0); 1810258945Sroberto} 1811258945Sroberto 1812258945Srobertostatic int 1813280849Scymlx5e_open_tis(struct mlx5e_priv *priv, int tc) 1814{ 1815 struct mlx5_core_dev *mdev = priv->mdev; 1816 u32 in[MLX5_ST_SZ_DW(create_tis_in)]; 1817 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1818 1819 memset(in, 0, sizeof(in)); 1820 1821 MLX5_SET(tisc, tisc, prio, tc); 1822 MLX5_SET(tisc, tisc, transport_domain, priv->tdn); 1823 1824 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc])); 1825} 1826 1827static void 1828mlx5e_close_tis(struct mlx5e_priv *priv, int tc) 1829{ 1830 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]); 1831} 1832 1833static int 1834mlx5e_open_tises(struct mlx5e_priv *priv) 1835{ 1836 int num_tc = priv->num_tc; 1837 int err; 1838 int tc; 1839 1840 for (tc = 0; tc < num_tc; tc++) { 1841 err = mlx5e_open_tis(priv, tc); 1842 if (err) 1843 goto err_close_tises; 1844 } 1845 1846 return (0); 1847 1848err_close_tises: 1849 for (tc--; tc >= 0; tc--) 1850 mlx5e_close_tis(priv, tc); 1851 1852 return (err); 1853} 1854 1855static void 1856mlx5e_close_tises(struct mlx5e_priv *priv) 1857{ 1858 int num_tc = priv->num_tc; 1859 int tc; 1860 1861 for (tc = 0; tc < num_tc; tc++) 1862 mlx5e_close_tis(priv, tc); 1863} 1864 1865static int 1866mlx5e_open_rqt(struct mlx5e_priv *priv) 1867{ 1868 struct mlx5_core_dev *mdev = priv->mdev; 1869 u32 *in; 1870 u32 out[MLX5_ST_SZ_DW(create_rqt_out)]; 1871 void *rqtc; 1872 int inlen; 1873 int err; 1874 int sz; 1875 int i; 1876 1877 sz = 1 << priv->params.rx_hash_log_tbl_sz; 1878 1879 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 1880 in = mlx5_vzalloc(inlen); 1881 if (in == NULL) 1882 return (-ENOMEM); 1883 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1884 1885 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 1886 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 1887 1888 for (i = 0; i < sz; i++) { 1889 int ix; 1890#ifdef RSS 1891 ix = rss_get_indirection_to_bucket(i); 1892#else 1893 ix = i; 1894#endif 1895 /* ensure we don't overflow */ 1896 ix %= priv->params.num_channels; 1897 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn); 1898 } 1899 1900 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1901 1902 memset(out, 0, sizeof(out)); 1903 err = mlx5_cmd_exec_check_status(mdev, in, inlen, out, sizeof(out)); 1904 if (!err) 1905 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn); 1906 1907 kvfree(in); 1908 1909 return (err); 1910} 1911 1912static void 1913mlx5e_close_rqt(struct mlx5e_priv *priv) 1914{ 1915 u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)]; 1916 u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)]; 1917 1918 memset(in, 0, sizeof(in)); 1919 1920 MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT); 1921 MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn); 1922 1923 mlx5_cmd_exec_check_status(priv->mdev, in, sizeof(in), out, 1924 sizeof(out)); 1925} 1926 1927static void 1928mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt) 1929{ 1930 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1931 __be32 *hkey; 1932 1933 MLX5_SET(tirc, tirc, transport_domain, priv->tdn); 1934 1935#define ROUGH_MAX_L2_L3_HDR_SZ 256 1936 1937#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\ 1938 MLX5_HASH_FIELD_SEL_DST_IP) 1939 1940#define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\ 1941 MLX5_HASH_FIELD_SEL_DST_IP |\ 1942 MLX5_HASH_FIELD_SEL_L4_SPORT |\ 1943 MLX5_HASH_FIELD_SEL_L4_DPORT) 1944 1945#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\ 1946 MLX5_HASH_FIELD_SEL_DST_IP |\ 1947 MLX5_HASH_FIELD_SEL_IPSEC_SPI) 1948 1949 if (priv->params.hw_lro_en) { 1950 MLX5_SET(tirc, tirc, lro_enable_mask, 1951 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO | 1952 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO); 1953 MLX5_SET(tirc, tirc, lro_max_msg_sz, 1954 (priv->params.lro_wqe_sz - 1955 ROUGH_MAX_L2_L3_HDR_SZ) >> 8); 1956 /* TODO: add the option to choose timer value dynamically */ 1957 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, 1958 MLX5_CAP_ETH(priv->mdev, 1959 lro_timer_supported_periods[2])); 1960 } 1961 1962 /* setup parameters for hashing TIR type, if any */ 1963 switch (tt) { 1964 case MLX5E_TT_ANY: 1965 MLX5_SET(tirc, tirc, disp_type, 1966 MLX5_TIRC_DISP_TYPE_DIRECT); 1967 MLX5_SET(tirc, tirc, inline_rqn, 1968 priv->channel[0]->rq.rqn); 1969 break; 1970 default: 1971 MLX5_SET(tirc, tirc, disp_type, 1972 MLX5_TIRC_DISP_TYPE_INDIRECT); 1973 MLX5_SET(tirc, tirc, indirect_table, 1974 priv->rqtn); 1975 MLX5_SET(tirc, tirc, rx_hash_fn, 1976 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ); 1977 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1978#ifdef RSS 1979 /* 1980 * The FreeBSD RSS implementation does currently not 1981 * support symmetric Toeplitz hashes: 1982 */ 1983 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0); 1984 rss_getkey((uint8_t *)hkey); 1985#else 1986 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 1987 hkey[0] = cpu_to_be32(0xD181C62C); 1988 hkey[1] = cpu_to_be32(0xF7F4DB5B); 1989 hkey[2] = cpu_to_be32(0x1983A2FC); 1990 hkey[3] = cpu_to_be32(0x943E1ADB); 1991 hkey[4] = cpu_to_be32(0xD9389E6B); 1992 hkey[5] = cpu_to_be32(0xD1039C2C); 1993 hkey[6] = cpu_to_be32(0xA74499AD); 1994 hkey[7] = cpu_to_be32(0x593D56D9); 1995 hkey[8] = cpu_to_be32(0xF3253C06); 1996 hkey[9] = cpu_to_be32(0x2ADC1FFC); 1997#endif 1998 break; 1999 } 2000 2001 switch (tt) { 2002 case MLX5E_TT_IPV4_TCP: 2003 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2004 MLX5_L3_PROT_TYPE_IPV4); 2005 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2006 MLX5_L4_PROT_TYPE_TCP); 2007#ifdef RSS 2008 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) { 2009 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2010 MLX5_HASH_IP); 2011 } else 2012#endif 2013 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2014 MLX5_HASH_ALL); 2015 break; 2016 2017 case MLX5E_TT_IPV6_TCP: 2018 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2019 MLX5_L3_PROT_TYPE_IPV6); 2020 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2021 MLX5_L4_PROT_TYPE_TCP); 2022#ifdef RSS 2023 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) { 2024 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2025 MLX5_HASH_IP); 2026 } else 2027#endif 2028 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2029 MLX5_HASH_ALL); 2030 break; 2031 2032 case MLX5E_TT_IPV4_UDP: 2033 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2034 MLX5_L3_PROT_TYPE_IPV4); 2035 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2036 MLX5_L4_PROT_TYPE_UDP); 2037#ifdef RSS 2038 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) { 2039 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2040 MLX5_HASH_IP); 2041 } else 2042#endif 2043 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2044 MLX5_HASH_ALL); 2045 break; 2046 2047 case MLX5E_TT_IPV6_UDP: 2048 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2049 MLX5_L3_PROT_TYPE_IPV6); 2050 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2051 MLX5_L4_PROT_TYPE_UDP); 2052#ifdef RSS 2053 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) { 2054 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2055 MLX5_HASH_IP); 2056 } else 2057#endif 2058 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2059 MLX5_HASH_ALL); 2060 break; 2061 2062 case MLX5E_TT_IPV4_IPSEC_AH: 2063 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2064 MLX5_L3_PROT_TYPE_IPV4); 2065 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2066 MLX5_HASH_IP_IPSEC_SPI); 2067 break; 2068 2069 case MLX5E_TT_IPV6_IPSEC_AH: 2070 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2071 MLX5_L3_PROT_TYPE_IPV6); 2072 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2073 MLX5_HASH_IP_IPSEC_SPI); 2074 break; 2075 2076 case MLX5E_TT_IPV4_IPSEC_ESP: 2077 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2078 MLX5_L3_PROT_TYPE_IPV4); 2079 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2080 MLX5_HASH_IP_IPSEC_SPI); 2081 break; 2082 2083 case MLX5E_TT_IPV6_IPSEC_ESP: 2084 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2085 MLX5_L3_PROT_TYPE_IPV6); 2086 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2087 MLX5_HASH_IP_IPSEC_SPI); 2088 break; 2089 2090 case MLX5E_TT_IPV4: 2091 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2092 MLX5_L3_PROT_TYPE_IPV4); 2093 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2094 MLX5_HASH_IP); 2095 break; 2096 2097 case MLX5E_TT_IPV6: 2098 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2099 MLX5_L3_PROT_TYPE_IPV6); 2100 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2101 MLX5_HASH_IP); 2102 break; 2103 2104 default: 2105 break; 2106 } 2107} 2108 2109static int 2110mlx5e_open_tir(struct mlx5e_priv *priv, int tt) 2111{ 2112 struct mlx5_core_dev *mdev = priv->mdev; 2113 u32 *in; 2114 void *tirc; 2115 int inlen; 2116 int err; 2117 2118 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 2119 in = mlx5_vzalloc(inlen); 2120 if (in == NULL) 2121 return (-ENOMEM); 2122 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context); 2123 2124 mlx5e_build_tir_ctx(priv, tirc, tt); 2125 2126 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]); 2127 2128 kvfree(in); 2129 2130 return (err); 2131} 2132 2133static void 2134mlx5e_close_tir(struct mlx5e_priv *priv, int tt) 2135{ 2136 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]); 2137} 2138 2139static int 2140mlx5e_open_tirs(struct mlx5e_priv *priv) 2141{ 2142 int err; 2143 int i; 2144 2145 for (i = 0; i < MLX5E_NUM_TT; i++) { 2146 err = mlx5e_open_tir(priv, i); 2147 if (err) 2148 goto err_close_tirs; 2149 } 2150 2151 return (0); 2152 2153err_close_tirs: 2154 for (i--; i >= 0; i--) 2155 mlx5e_close_tir(priv, i); 2156 2157 return (err); 2158} 2159 2160static void 2161mlx5e_close_tirs(struct mlx5e_priv *priv) 2162{ 2163 int i; 2164 2165 for (i = 0; i < MLX5E_NUM_TT; i++) 2166 mlx5e_close_tir(priv, i); 2167} 2168 2169/* 2170 * SW MTU does not include headers, 2171 * HW MTU includes all headers and checksums. 2172 */ 2173static int 2174mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu) 2175{ 2176 struct mlx5e_priv *priv = ifp->if_softc; 2177 struct mlx5_core_dev *mdev = priv->mdev; 2178 int hw_mtu; 2179 int err; 2180 2181 err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(sw_mtu)); 2182 if (err) { 2183 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n", 2184 __func__, sw_mtu, err); 2185 return (err); 2186 } 2187 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu); 2188 if (err) { 2189 if_printf(ifp, "Query port MTU, after setting new " 2190 "MTU value, failed\n"); 2191 } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) { 2192 err = -E2BIG, 2193 if_printf(ifp, "Port MTU %d is smaller than " 2194 "ifp mtu %d\n", hw_mtu, sw_mtu); 2195 } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) { 2196 err = -EINVAL; 2197 if_printf(ifp, "Port MTU %d is bigger than " 2198 "ifp mtu %d\n", hw_mtu, sw_mtu); 2199 } 2200 ifp->if_mtu = sw_mtu; 2201 return (err); 2202} 2203 2204int 2205mlx5e_open_locked(struct ifnet *ifp) 2206{ 2207 struct mlx5e_priv *priv = ifp->if_softc; 2208 int err; 2209 u16 set_id; 2210 2211 /* check if already opened */ 2212 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0) 2213 return (0); 2214 2215#ifdef RSS 2216 if (rss_getnumbuckets() > priv->params.num_channels) { 2217 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than " 2218 "channels(%u) available\n", rss_getnumbuckets(), 2219 priv->params.num_channels); 2220 } 2221#endif 2222 err = mlx5e_open_tises(priv); 2223 if (err) { 2224 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n", 2225 __func__, err); 2226 return (err); 2227 } 2228 err = mlx5_vport_alloc_q_counter(priv->mdev, 2229 MLX5_INTERFACE_PROTOCOL_ETH, &set_id); 2230 if (err) { 2231 if_printf(priv->ifp, 2232 "%s: mlx5_vport_alloc_q_counter failed: %d\n", 2233 __func__, err); 2234 goto err_close_tises; 2235 } 2236 /* store counter set ID */ 2237 priv->counter_set_id = set_id; 2238 2239 err = mlx5e_open_channels(priv); 2240 if (err) { 2241 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n", 2242 __func__, err); 2243 goto err_dalloc_q_counter; 2244 } 2245 err = mlx5e_open_rqt(priv); 2246 if (err) { 2247 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n", 2248 __func__, err); 2249 goto err_close_channels; 2250 } 2251 err = mlx5e_open_tirs(priv); 2252 if (err) { 2253 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n", 2254 __func__, err); 2255 goto err_close_rqls; 2256 } 2257 err = mlx5e_open_flow_table(priv); 2258 if (err) { 2259 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n", 2260 __func__, err); 2261 goto err_close_tirs; 2262 } 2263 err = mlx5e_add_all_vlan_rules(priv); 2264 if (err) { 2265 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n", 2266 __func__, err); 2267 goto err_close_flow_table; 2268 } 2269 set_bit(MLX5E_STATE_OPENED, &priv->state); 2270 2271 mlx5e_update_carrier(priv); 2272 mlx5e_set_rx_mode_core(priv); 2273 2274 return (0); 2275 2276err_close_flow_table: 2277 mlx5e_close_flow_table(priv); 2278 2279err_close_tirs: 2280 mlx5e_close_tirs(priv); 2281 2282err_close_rqls: 2283 mlx5e_close_rqt(priv); 2284 2285err_close_channels: 2286 mlx5e_close_channels(priv); 2287 2288err_dalloc_q_counter: 2289 mlx5_vport_dealloc_q_counter(priv->mdev, 2290 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id); 2291 2292err_close_tises: 2293 mlx5e_close_tises(priv); 2294 2295 return (err); 2296} 2297 2298static void 2299mlx5e_open(void *arg) 2300{ 2301 struct mlx5e_priv *priv = arg; 2302 2303 PRIV_LOCK(priv); 2304 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP)) 2305 if_printf(priv->ifp, 2306 "%s: Setting port status to up failed\n", 2307 __func__); 2308 2309 mlx5e_open_locked(priv->ifp); 2310 priv->ifp->if_drv_flags |= IFF_DRV_RUNNING; 2311 PRIV_UNLOCK(priv); 2312} 2313 2314int 2315mlx5e_close_locked(struct ifnet *ifp) 2316{ 2317 struct mlx5e_priv *priv = ifp->if_softc; 2318 2319 /* check if already closed */ 2320 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 2321 return (0); 2322 2323 clear_bit(MLX5E_STATE_OPENED, &priv->state); 2324 2325 mlx5e_set_rx_mode_core(priv); 2326 mlx5e_del_all_vlan_rules(priv); 2327 if_link_state_change(priv->ifp, LINK_STATE_DOWN); 2328 mlx5e_close_flow_table(priv); 2329 mlx5e_close_tirs(priv); 2330 mlx5e_close_rqt(priv); 2331 mlx5e_close_channels(priv); 2332 mlx5_vport_dealloc_q_counter(priv->mdev, 2333 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id); 2334 mlx5e_close_tises(priv); 2335 2336 return (0); 2337} 2338 2339#if (__FreeBSD_version >= 1100000) 2340static uint64_t 2341mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt) 2342{ 2343 struct mlx5e_priv *priv = ifp->if_softc; 2344 u64 retval; 2345 2346 /* PRIV_LOCK(priv); XXX not allowed */ 2347 switch (cnt) { 2348 case IFCOUNTER_IPACKETS: 2349 retval = priv->stats.vport.rx_packets; 2350 break; 2351 case IFCOUNTER_IERRORS: 2352 retval = priv->stats.vport.rx_error_packets; 2353 break; 2354 case IFCOUNTER_IQDROPS: 2355 retval = priv->stats.vport.rx_out_of_buffer; 2356 break; 2357 case IFCOUNTER_OPACKETS: 2358 retval = priv->stats.vport.tx_packets; 2359 break; 2360 case IFCOUNTER_OERRORS: 2361 retval = priv->stats.vport.tx_error_packets; 2362 break; 2363 case IFCOUNTER_IBYTES: 2364 retval = priv->stats.vport.rx_bytes; 2365 break; 2366 case IFCOUNTER_OBYTES: 2367 retval = priv->stats.vport.tx_bytes; 2368 break; 2369 case IFCOUNTER_IMCASTS: 2370 retval = priv->stats.vport.rx_multicast_packets; 2371 break; 2372 case IFCOUNTER_OMCASTS: 2373 retval = priv->stats.vport.tx_multicast_packets; 2374 break; 2375 case IFCOUNTER_OQDROPS: 2376 retval = priv->stats.vport.tx_queue_dropped; 2377 break; 2378 default: 2379 retval = if_get_counter_default(ifp, cnt); 2380 break; 2381 } 2382 /* PRIV_UNLOCK(priv); XXX not allowed */ 2383 return (retval); 2384} 2385#endif 2386 2387static void 2388mlx5e_set_rx_mode(struct ifnet *ifp) 2389{ 2390 struct mlx5e_priv *priv = ifp->if_softc; 2391 2392 schedule_work(&priv->set_rx_mode_work); 2393} 2394 2395static int 2396mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2397{ 2398 struct mlx5e_priv *priv; 2399 struct ifreq *ifr; 2400 struct ifi2creq i2c; 2401 int error = 0; 2402 int mask = 0; 2403 int size_read = 0; 2404 int module_num; 2405 int max_mtu; 2406 uint8_t read_addr; 2407 2408 priv = ifp->if_softc; 2409 2410 /* check if detaching */ 2411 if (priv == NULL || priv->gone != 0) 2412 return (ENXIO); 2413 2414 switch (command) { 2415 case SIOCSIFMTU: 2416 ifr = (struct ifreq *)data; 2417 2418 PRIV_LOCK(priv); 2419 mlx5_query_port_max_mtu(priv->mdev, &max_mtu); 2420 2421 if (ifr->ifr_mtu >= MLX5E_MTU_MIN && 2422 ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) { 2423 int was_opened; 2424 2425 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 2426 if (was_opened) 2427 mlx5e_close_locked(ifp); 2428 2429 /* set new MTU */ 2430 mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu); 2431 2432 if (was_opened) 2433 mlx5e_open_locked(ifp); 2434 } else { 2435 error = EINVAL; 2436 if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n", 2437 MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu)); 2438 } 2439 PRIV_UNLOCK(priv); 2440 break; 2441 case SIOCSIFFLAGS: 2442 if ((ifp->if_flags & IFF_UP) && 2443 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 2444 mlx5e_set_rx_mode(ifp); 2445 break; 2446 } 2447 PRIV_LOCK(priv); 2448 if (ifp->if_flags & IFF_UP) { 2449 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2450 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 2451 mlx5e_open_locked(ifp); 2452 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2453 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP); 2454 } 2455 } else { 2456 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2457 mlx5_set_port_status(priv->mdev, 2458 MLX5_PORT_DOWN); 2459 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0) 2460 mlx5e_close_locked(ifp); 2461 mlx5e_update_carrier(priv); 2462 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2463 } 2464 } 2465 PRIV_UNLOCK(priv); 2466 break; 2467 case SIOCADDMULTI: 2468 case SIOCDELMULTI: 2469 mlx5e_set_rx_mode(ifp); 2470 break; 2471 case SIOCSIFMEDIA: 2472 case SIOCGIFMEDIA: 2473 case SIOCGIFXMEDIA: 2474 ifr = (struct ifreq *)data; 2475 error = ifmedia_ioctl(ifp, ifr, &priv->media, command); 2476 break; 2477 case SIOCSIFCAP: 2478 ifr = (struct ifreq *)data; 2479 PRIV_LOCK(priv); 2480 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2481 2482 if (mask & IFCAP_TXCSUM) { 2483 ifp->if_capenable ^= IFCAP_TXCSUM; 2484 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 2485 2486 if (IFCAP_TSO4 & ifp->if_capenable && 2487 !(IFCAP_TXCSUM & ifp->if_capenable)) { 2488 ifp->if_capenable &= ~IFCAP_TSO4; 2489 ifp->if_hwassist &= ~CSUM_IP_TSO; 2490 if_printf(ifp, 2491 "tso4 disabled due to -txcsum.\n"); 2492 } 2493 } 2494 if (mask & IFCAP_TXCSUM_IPV6) { 2495 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 2496 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 2497 2498 if (IFCAP_TSO6 & ifp->if_capenable && 2499 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 2500 ifp->if_capenable &= ~IFCAP_TSO6; 2501 ifp->if_hwassist &= ~CSUM_IP6_TSO; 2502 if_printf(ifp, 2503 "tso6 disabled due to -txcsum6.\n"); 2504 } 2505 } 2506 if (mask & IFCAP_RXCSUM) 2507 ifp->if_capenable ^= IFCAP_RXCSUM; 2508 if (mask & IFCAP_RXCSUM_IPV6) 2509 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 2510 if (mask & IFCAP_TSO4) { 2511 if (!(IFCAP_TSO4 & ifp->if_capenable) && 2512 !(IFCAP_TXCSUM & ifp->if_capenable)) { 2513 if_printf(ifp, "enable txcsum first.\n"); 2514 error = EAGAIN; 2515 goto out; 2516 } 2517 ifp->if_capenable ^= IFCAP_TSO4; 2518 ifp->if_hwassist ^= CSUM_IP_TSO; 2519 } 2520 if (mask & IFCAP_TSO6) { 2521 if (!(IFCAP_TSO6 & ifp->if_capenable) && 2522 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 2523 if_printf(ifp, "enable txcsum6 first.\n"); 2524 error = EAGAIN; 2525 goto out; 2526 } 2527 ifp->if_capenable ^= IFCAP_TSO6; 2528 ifp->if_hwassist ^= CSUM_IP6_TSO; 2529 } 2530 if (mask & IFCAP_VLAN_HWFILTER) { 2531 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) 2532 mlx5e_disable_vlan_filter(priv); 2533 else 2534 mlx5e_enable_vlan_filter(priv); 2535 2536 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER; 2537 } 2538 if (mask & IFCAP_VLAN_HWTAGGING) 2539 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2540 if (mask & IFCAP_WOL_MAGIC) 2541 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2542 2543 VLAN_CAPABILITIES(ifp); 2544 /* turn off LRO means also turn of HW LRO - if it's on */ 2545 if (mask & IFCAP_LRO) { 2546 int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 2547 bool need_restart = false; 2548 2549 ifp->if_capenable ^= IFCAP_LRO; 2550 if (!(ifp->if_capenable & IFCAP_LRO)) { 2551 if (priv->params.hw_lro_en) { 2552 priv->params.hw_lro_en = false; 2553 need_restart = true; 2554 /* Not sure this is the correct way */ 2555 priv->params_ethtool.hw_lro = priv->params.hw_lro_en; 2556 } 2557 } 2558 if (was_opened && need_restart) { 2559 mlx5e_close_locked(ifp); 2560 mlx5e_open_locked(ifp); 2561 } 2562 } 2563out: 2564 PRIV_UNLOCK(priv); 2565 break; 2566 2567 case SIOCGI2C: 2568 ifr = (struct ifreq *)data; 2569 2570 /* 2571 * Copy from the user-space address ifr_data to the 2572 * kernel-space address i2c 2573 */ 2574 error = copyin(ifr->ifr_data, &i2c, sizeof(i2c)); 2575 if (error) 2576 break; 2577 2578 if (i2c.len > sizeof(i2c.data)) { 2579 error = EINVAL; 2580 break; 2581 } 2582 2583 PRIV_LOCK(priv); 2584 /* Get module_num which is required for the query_eeprom */ 2585 error = mlx5_query_module_num(priv->mdev, &module_num); 2586 if (error) { 2587 if_printf(ifp, "Query module num failed, eeprom " 2588 "reading is not supported\n"); 2589 error = EINVAL; 2590 goto err_i2c; 2591 } 2592 /* Check if module is present before doing an access */ 2593 if (mlx5_query_module_status(priv->mdev, module_num) != 2594 MLX5_MODULE_STATUS_PLUGGED) { 2595 error = EINVAL; 2596 goto err_i2c; 2597 } 2598 /* 2599 * Currently 0XA0 and 0xA2 are the only addresses permitted. 2600 * The internal conversion is as follows: 2601 */ 2602 if (i2c.dev_addr == 0xA0) 2603 read_addr = MLX5E_I2C_ADDR_LOW; 2604 else if (i2c.dev_addr == 0xA2) 2605 read_addr = MLX5E_I2C_ADDR_HIGH; 2606 else { 2607 if_printf(ifp, "Query eeprom failed, " 2608 "Invalid Address: %X\n", i2c.dev_addr); 2609 error = EINVAL; 2610 goto err_i2c; 2611 } 2612 error = mlx5_query_eeprom(priv->mdev, 2613 read_addr, MLX5E_EEPROM_LOW_PAGE, 2614 (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num, 2615 (uint32_t *)i2c.data, &size_read); 2616 if (error) { 2617 if_printf(ifp, "Query eeprom failed, eeprom " 2618 "reading is not supported\n"); 2619 error = EINVAL; 2620 goto err_i2c; 2621 } 2622 2623 if (i2c.len > MLX5_EEPROM_MAX_BYTES) { 2624 error = mlx5_query_eeprom(priv->mdev, 2625 read_addr, MLX5E_EEPROM_LOW_PAGE, 2626 (uint32_t)(i2c.offset + size_read), 2627 (uint32_t)(i2c.len - size_read), module_num, 2628 (uint32_t *)(i2c.data + size_read), &size_read); 2629 } 2630 if (error) { 2631 if_printf(ifp, "Query eeprom failed, eeprom " 2632 "reading is not supported\n"); 2633 error = EINVAL; 2634 goto err_i2c; 2635 } 2636 2637 error = copyout(&i2c, ifr->ifr_data, sizeof(i2c)); 2638err_i2c: 2639 PRIV_UNLOCK(priv); 2640 break; 2641 2642 default: 2643 error = ether_ioctl(ifp, command, data); 2644 break; 2645 } 2646 return (error); 2647} 2648 2649static int 2650mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev) 2651{ 2652 /* 2653 * TODO: uncoment once FW really sets all these bits if 2654 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap || 2655 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap || 2656 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return 2657 * -ENOTSUPP; 2658 */ 2659 2660 /* TODO: add more must-to-have features */ 2661 2662 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) 2663 return (-ENODEV); 2664 2665 return (0); 2666} 2667 2668static void 2669mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev, 2670 struct mlx5e_priv *priv, 2671 int num_comp_vectors) 2672{ 2673 /* 2674 * TODO: Consider link speed for setting "log_sq_size", 2675 * "log_rq_size" and "cq_moderation_xxx": 2676 */ 2677 priv->params.log_sq_size = 2678 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; 2679 priv->params.log_rq_size = 2680 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE; 2681 priv->params.rx_cq_moderation_usec = 2682 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 2683 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE : 2684 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC; 2685 priv->params.rx_cq_moderation_mode = 2686 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0; 2687 priv->params.rx_cq_moderation_pkts = 2688 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS; 2689 priv->params.tx_cq_moderation_usec = 2690 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC; 2691 priv->params.tx_cq_moderation_pkts = 2692 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS; 2693 priv->params.min_rx_wqes = 2694 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES; 2695 priv->params.rx_hash_log_tbl_sz = 2696 (order_base_2(num_comp_vectors) > 2697 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ? 2698 order_base_2(num_comp_vectors) : 2699 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ; 2700 priv->params.num_tc = 1; 2701 priv->params.default_vlan_prio = 0; 2702 priv->counter_set_id = -1; 2703 2704 /* 2705 * hw lro is currently defaulted to off. when it won't anymore we 2706 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)" 2707 */ 2708 priv->params.hw_lro_en = false; 2709 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ; 2710 2711 priv->params.cqe_zipping_en = !!MLX5_CAP_GEN(mdev, cqe_compression); 2712 2713 priv->mdev = mdev; 2714 priv->params.num_channels = num_comp_vectors; 2715 priv->order_base_2_num_channels = order_base_2(num_comp_vectors); 2716 priv->queue_mapping_channel_mask = 2717 roundup_pow_of_two(num_comp_vectors) - 1; 2718 priv->num_tc = priv->params.num_tc; 2719 priv->default_vlan_prio = priv->params.default_vlan_prio; 2720 2721 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work); 2722 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work); 2723 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work); 2724} 2725 2726static int 2727mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn, 2728 struct mlx5_core_mr *mr) 2729{ 2730 struct ifnet *ifp = priv->ifp; 2731 struct mlx5_core_dev *mdev = priv->mdev; 2732 struct mlx5_create_mkey_mbox_in *in; 2733 int err; 2734 2735 in = mlx5_vzalloc(sizeof(*in)); 2736 if (in == NULL) { 2737 if_printf(ifp, "%s: failed to allocate inbox\n", __func__); 2738 return (-ENOMEM); 2739 } 2740 in->seg.flags = MLX5_PERM_LOCAL_WRITE | 2741 MLX5_PERM_LOCAL_READ | 2742 MLX5_ACCESS_MODE_PA; 2743 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64); 2744 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8); 2745 2746 err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL, 2747 NULL); 2748 if (err) 2749 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n", 2750 __func__, err); 2751 2752 kvfree(in); 2753 2754 return (err); 2755} 2756 2757static const char *mlx5e_vport_stats_desc[] = { 2758 MLX5E_VPORT_STATS(MLX5E_STATS_DESC) 2759}; 2760 2761static const char *mlx5e_pport_stats_desc[] = { 2762 MLX5E_PPORT_STATS(MLX5E_STATS_DESC) 2763}; 2764 2765static void 2766mlx5e_priv_mtx_init(struct mlx5e_priv *priv) 2767{ 2768 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF); 2769 sx_init(&priv->state_lock, "mlx5state"); 2770 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0); 2771 MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock); 2772} 2773 2774static void 2775mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv) 2776{ 2777 mtx_destroy(&priv->async_events_mtx); 2778 sx_destroy(&priv->state_lock); 2779} 2780 2781static int 2782sysctl_firmware(SYSCTL_HANDLER_ARGS) 2783{ 2784 /* 2785 * %d.%d%.d the string format. 2786 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536. 2787 * We need at most 5 chars to store that. 2788 * It also has: two "." and NULL at the end, which means we need 18 2789 * (5*3 + 3) chars at most. 2790 */ 2791 char fw[18]; 2792 struct mlx5e_priv *priv = arg1; 2793 int error; 2794 2795 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev), 2796 fw_rev_sub(priv->mdev)); 2797 error = sysctl_handle_string(oidp, fw, sizeof(fw), req); 2798 return (error); 2799} 2800 2801static void 2802mlx5e_add_hw_stats(struct mlx5e_priv *priv) 2803{ 2804 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw), 2805 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0, 2806 sysctl_firmware, "A", "HCA firmware version"); 2807 2808 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw), 2809 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0, 2810 "Board ID"); 2811} 2812 2813static void 2814mlx5e_setup_pauseframes(struct mlx5e_priv *priv) 2815{ 2816#if (__FreeBSD_version < 1100000) 2817 char path[64]; 2818 2819#endif 2820 /* Only receiving pauseframes is enabled by default */ 2821 priv->params.tx_pauseframe_control = 0; 2822 priv->params.rx_pauseframe_control = 1; 2823 2824#if (__FreeBSD_version < 1100000) 2825 /* compute path for sysctl */ 2826 snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control", 2827 device_get_unit(priv->mdev->pdev->dev.bsddev)); 2828 2829 /* try to fetch tunable, if any */ 2830 TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control); 2831 2832 /* compute path for sysctl */ 2833 snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control", 2834 device_get_unit(priv->mdev->pdev->dev.bsddev)); 2835 2836 /* try to fetch tunable, if any */ 2837 TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control); 2838#endif 2839 2840 /* register pausframe SYSCTLs */ 2841 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 2842 OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN, 2843 &priv->params.tx_pauseframe_control, 0, 2844 "Set to enable TX pause frames. Clear to disable."); 2845 2846 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 2847 OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN, 2848 &priv->params.rx_pauseframe_control, 0, 2849 "Set to enable RX pause frames. Clear to disable."); 2850 2851 /* range check */ 2852 priv->params.tx_pauseframe_control = 2853 priv->params.tx_pauseframe_control ? 1 : 0; 2854 priv->params.rx_pauseframe_control = 2855 priv->params.rx_pauseframe_control ? 1 : 0; 2856 2857 /* update firmware */ 2858 mlx5_set_port_pause(priv->mdev, 1, 2859 priv->params.rx_pauseframe_control, 2860 priv->params.tx_pauseframe_control); 2861} 2862 2863static void * 2864mlx5e_create_ifp(struct mlx5_core_dev *mdev) 2865{ 2866 static volatile int mlx5_en_unit; 2867 struct ifnet *ifp; 2868 struct mlx5e_priv *priv; 2869 u8 dev_addr[ETHER_ADDR_LEN] __aligned(4); 2870 struct sysctl_oid_list *child; 2871 int ncv = mdev->priv.eq_table.num_comp_vectors; 2872 char unit[16]; 2873 int err; 2874 int i; 2875 u32 eth_proto_cap; 2876 2877 if (mlx5e_check_required_hca_cap(mdev)) { 2878 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n"); 2879 return (NULL); 2880 } 2881 priv = malloc(sizeof(*priv), M_MLX5EN, M_WAITOK | M_ZERO); 2882 if (priv == NULL) { 2883 mlx5_core_err(mdev, "malloc() failed\n"); 2884 return (NULL); 2885 } 2886 mlx5e_priv_mtx_init(priv); 2887 2888 ifp = priv->ifp = if_alloc(IFT_ETHER); 2889 if (ifp == NULL) { 2890 mlx5_core_err(mdev, "if_alloc() failed\n"); 2891 goto err_free_priv; 2892 } 2893 ifp->if_softc = priv; 2894 if_initname(ifp, "mce", atomic_fetchadd_int(&mlx5_en_unit, 1)); 2895 ifp->if_mtu = ETHERMTU; 2896 ifp->if_init = mlx5e_open; 2897 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2898 ifp->if_ioctl = mlx5e_ioctl; 2899 ifp->if_transmit = mlx5e_xmit; 2900 ifp->if_qflush = if_qflush; 2901#if (__FreeBSD_version >= 1100000) 2902 ifp->if_get_counter = mlx5e_get_counter; 2903#endif 2904 ifp->if_snd.ifq_maxlen = ifqmaxlen; 2905 /* 2906 * Set driver features 2907 */ 2908 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6; 2909 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 2910 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER; 2911 ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU; 2912 ifp->if_capabilities |= IFCAP_LRO; 2913 ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO; 2914 ifp->if_capabilities |= IFCAP_HWSTATS; 2915 2916 /* set TSO limits so that we don't have to drop TX packets */ 2917 ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 2918 ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */; 2919 ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE; 2920 2921 ifp->if_capenable = ifp->if_capabilities; 2922 ifp->if_hwassist = 0; 2923 if (ifp->if_capenable & IFCAP_TSO) 2924 ifp->if_hwassist |= CSUM_TSO; 2925 if (ifp->if_capenable & IFCAP_TXCSUM) 2926 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP); 2927 if (ifp->if_capenable & IFCAP_TXCSUM_IPV6) 2928 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 2929 2930 /* ifnet sysctl tree */ 2931 sysctl_ctx_init(&priv->sysctl_ctx); 2932 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev), 2933 OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name"); 2934 if (priv->sysctl_ifnet == NULL) { 2935 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 2936 goto err_free_sysctl; 2937 } 2938 snprintf(unit, sizeof(unit), "%d", ifp->if_dunit); 2939 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 2940 OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit"); 2941 if (priv->sysctl_ifnet == NULL) { 2942 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 2943 goto err_free_sysctl; 2944 } 2945 2946 /* HW sysctl tree */ 2947 child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev)); 2948 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child, 2949 OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw"); 2950 if (priv->sysctl_hw == NULL) { 2951 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 2952 goto err_free_sysctl; 2953 } 2954 mlx5e_build_ifp_priv(mdev, priv, ncv); 2955 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar); 2956 if (err) { 2957 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n", 2958 __func__, err); 2959 goto err_free_sysctl; 2960 } 2961 err = mlx5_core_alloc_pd(mdev, &priv->pdn); 2962 if (err) { 2963 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n", 2964 __func__, err); 2965 goto err_unmap_free_uar; 2966 } 2967 err = mlx5_alloc_transport_domain(mdev, &priv->tdn); 2968 if (err) { 2969 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n", 2970 __func__, err); 2971 goto err_dealloc_pd; 2972 } 2973 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr); 2974 if (err) { 2975 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n", 2976 __func__, err); 2977 goto err_dealloc_transport_domain; 2978 } 2979 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr); 2980 2981 /* check if we should generate a random MAC address */ 2982 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 && 2983 is_zero_ether_addr(dev_addr)) { 2984 random_ether_addr(dev_addr); 2985 if_printf(ifp, "Assigned random MAC address\n"); 2986 } 2987 2988 /* set default MTU */ 2989 mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu); 2990 2991 /* Set desc */ 2992 device_set_desc(mdev->pdev->dev.bsddev, mlx5e_version); 2993 2994 /* Set default media status */ 2995 priv->media_status_last = IFM_AVALID; 2996 priv->media_active_last = IFM_ETHER | IFM_AUTO | 2997 IFM_ETH_RXPAUSE | IFM_FDX; 2998 2999 /* setup default pauseframes configuration */ 3000 mlx5e_setup_pauseframes(priv); 3001 3002 err = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN); 3003 if (err) { 3004 eth_proto_cap = 0; 3005 if_printf(ifp, "%s: Query port media capability failed, %d\n", 3006 __func__, err); 3007 } 3008 3009 /* Setup supported medias */ 3010 ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK, 3011 mlx5e_media_change, mlx5e_media_status); 3012 3013 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) { 3014 if (mlx5e_mode_table[i].baudrate == 0) 3015 continue; 3016 if (MLX5E_PROT_MASK(i) & eth_proto_cap) { 3017 ifmedia_add(&priv->media, 3018 mlx5e_mode_table[i].subtype | 3019 IFM_ETHER, 0, NULL); 3020 ifmedia_add(&priv->media, 3021 mlx5e_mode_table[i].subtype | 3022 IFM_ETHER | IFM_FDX | 3023 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL); 3024 } 3025 } 3026 3027 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL); 3028 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX | 3029 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL); 3030 3031 /* Set autoselect by default */ 3032 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX | 3033 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE); 3034 ether_ifattach(ifp, dev_addr); 3035 3036 /* Register for VLAN events */ 3037 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config, 3038 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST); 3039 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig, 3040 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST); 3041 3042 /* Link is down by default */ 3043 if_link_state_change(ifp, LINK_STATE_DOWN); 3044 3045 mlx5e_enable_async_events(priv); 3046 3047 mlx5e_add_hw_stats(priv); 3048 3049 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 3050 "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM, 3051 priv->stats.vport.arg); 3052 3053 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 3054 "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM, 3055 priv->stats.pport.arg); 3056 3057 mlx5e_create_ethtool(priv); 3058 3059 mtx_lock(&priv->async_events_mtx); 3060 mlx5e_update_stats(priv); 3061 mtx_unlock(&priv->async_events_mtx); 3062 3063 return (priv); 3064 3065err_dealloc_transport_domain: 3066 mlx5_dealloc_transport_domain(mdev, priv->tdn); 3067 3068err_dealloc_pd: 3069 mlx5_core_dealloc_pd(mdev, priv->pdn); 3070 3071err_unmap_free_uar: 3072 mlx5_unmap_free_uar(mdev, &priv->cq_uar); 3073 3074err_free_sysctl: 3075 sysctl_ctx_free(&priv->sysctl_ctx); 3076 3077 if_free(ifp); 3078 3079err_free_priv: 3080 mlx5e_priv_mtx_destroy(priv); 3081 free(priv, M_MLX5EN); 3082 return (NULL); 3083} 3084 3085static void 3086mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv) 3087{ 3088 struct mlx5e_priv *priv = vpriv; 3089 struct ifnet *ifp = priv->ifp; 3090 3091 /* don't allow more IOCTLs */ 3092 priv->gone = 1; 3093 3094 /* 3095 * Clear the device description to avoid use after free, 3096 * because the bsddev is not destroyed when this module is 3097 * unloaded: 3098 */ 3099 device_set_desc(mdev->pdev->dev.bsddev, NULL); 3100 3101 /* XXX wait a bit to allow IOCTL handlers to complete */ 3102 pause("W", hz); 3103 3104 /* stop watchdog timer */ 3105 callout_drain(&priv->watchdog); 3106 3107 if (priv->vlan_attach != NULL) 3108 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach); 3109 if (priv->vlan_detach != NULL) 3110 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach); 3111 3112 /* make sure device gets closed */ 3113 PRIV_LOCK(priv); 3114 mlx5e_close_locked(ifp); 3115 PRIV_UNLOCK(priv); 3116 3117 /* unregister device */ 3118 ifmedia_removeall(&priv->media); 3119 ether_ifdetach(ifp); 3120 if_free(ifp); 3121 3122 /* destroy all remaining sysctl nodes */ 3123 if (priv->sysctl_debug) 3124 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx); 3125 sysctl_ctx_free(&priv->stats.vport.ctx); 3126 sysctl_ctx_free(&priv->stats.pport.ctx); 3127 sysctl_ctx_free(&priv->sysctl_ctx); 3128 3129 mlx5_core_destroy_mkey(priv->mdev, &priv->mr); 3130 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn); 3131 mlx5_core_dealloc_pd(priv->mdev, priv->pdn); 3132 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar); 3133 mlx5e_disable_async_events(priv); 3134 flush_scheduled_work(); 3135 mlx5e_priv_mtx_destroy(priv); 3136 free(priv, M_MLX5EN); 3137} 3138 3139static void * 3140mlx5e_get_ifp(void *vpriv) 3141{ 3142 struct mlx5e_priv *priv = vpriv; 3143 3144 return (priv->ifp); 3145} 3146 3147static struct mlx5_interface mlx5e_interface = { 3148 .add = mlx5e_create_ifp, 3149 .remove = mlx5e_destroy_ifp, 3150 .event = mlx5e_async_event, 3151 .protocol = MLX5_INTERFACE_PROTOCOL_ETH, 3152 .get_dev = mlx5e_get_ifp, 3153}; 3154 3155void 3156mlx5e_init(void) 3157{ 3158 mlx5_register_interface(&mlx5e_interface); 3159} 3160 3161void 3162mlx5e_cleanup(void) 3163{ 3164 mlx5_unregister_interface(&mlx5e_interface); 3165} 3166 3167module_init_order(mlx5e_init, SI_ORDER_THIRD); 3168module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD); 3169 3170#if (__FreeBSD_version >= 1100000) 3171MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1); 3172#endif 3173MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1); 3174MODULE_VERSION(mlx5en, 1); 3175