mlx5_en_main.c revision 306233
1/*-
2 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_en/mlx5_en_main.c 306233 2016-09-23 08:17:51Z hselasky $
26 */
27
28#include "en.h"
29
30#include <sys/sockio.h>
31#include <machine/atomic.h>
32
33#define	ETH_DRIVER_VERSION	"3.1.0-dev"
34char mlx5e_version[] = "Mellanox Ethernet driver"
35    " (" ETH_DRIVER_VERSION ")";
36
37struct mlx5e_rq_param {
38	u32	rqc [MLX5_ST_SZ_DW(rqc)];
39	struct mlx5_wq_param wq;
40};
41
42struct mlx5e_sq_param {
43	u32	sqc [MLX5_ST_SZ_DW(sqc)];
44	struct mlx5_wq_param wq;
45};
46
47struct mlx5e_cq_param {
48	u32	cqc [MLX5_ST_SZ_DW(cqc)];
49	struct mlx5_wq_param wq;
50	u16	eq_ix;
51};
52
53struct mlx5e_channel_param {
54	struct mlx5e_rq_param rq;
55	struct mlx5e_sq_param sq;
56	struct mlx5e_cq_param rx_cq;
57	struct mlx5e_cq_param tx_cq;
58};
59
60static const struct {
61	u32	subtype;
62	u64	baudrate;
63}	mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
64
65	[MLX5E_1000BASE_CX_SGMII] = {
66		.subtype = IFM_1000_CX_SGMII,
67		.baudrate = IF_Mbps(1000ULL),
68	},
69	[MLX5E_1000BASE_KX] = {
70		.subtype = IFM_1000_KX,
71		.baudrate = IF_Mbps(1000ULL),
72	},
73	[MLX5E_10GBASE_CX4] = {
74		.subtype = IFM_10G_CX4,
75		.baudrate = IF_Gbps(10ULL),
76	},
77	[MLX5E_10GBASE_KX4] = {
78		.subtype = IFM_10G_KX4,
79		.baudrate = IF_Gbps(10ULL),
80	},
81	[MLX5E_10GBASE_KR] = {
82		.subtype = IFM_10G_KR,
83		.baudrate = IF_Gbps(10ULL),
84	},
85	[MLX5E_20GBASE_KR2] = {
86		.subtype = IFM_20G_KR2,
87		.baudrate = IF_Gbps(20ULL),
88	},
89	[MLX5E_40GBASE_CR4] = {
90		.subtype = IFM_40G_CR4,
91		.baudrate = IF_Gbps(40ULL),
92	},
93	[MLX5E_40GBASE_KR4] = {
94		.subtype = IFM_40G_KR4,
95		.baudrate = IF_Gbps(40ULL),
96	},
97	[MLX5E_56GBASE_R4] = {
98		.subtype = IFM_56G_R4,
99		.baudrate = IF_Gbps(56ULL),
100	},
101	[MLX5E_10GBASE_CR] = {
102		.subtype = IFM_10G_CR1,
103		.baudrate = IF_Gbps(10ULL),
104	},
105	[MLX5E_10GBASE_SR] = {
106		.subtype = IFM_10G_SR,
107		.baudrate = IF_Gbps(10ULL),
108	},
109	[MLX5E_10GBASE_LR] = {
110		.subtype = IFM_10G_LR,
111		.baudrate = IF_Gbps(10ULL),
112	},
113	[MLX5E_40GBASE_SR4] = {
114		.subtype = IFM_40G_SR4,
115		.baudrate = IF_Gbps(40ULL),
116	},
117	[MLX5E_40GBASE_LR4] = {
118		.subtype = IFM_40G_LR4,
119		.baudrate = IF_Gbps(40ULL),
120	},
121	[MLX5E_100GBASE_CR4] = {
122		.subtype = IFM_100G_CR4,
123		.baudrate = IF_Gbps(100ULL),
124	},
125	[MLX5E_100GBASE_SR4] = {
126		.subtype = IFM_100G_SR4,
127		.baudrate = IF_Gbps(100ULL),
128	},
129	[MLX5E_100GBASE_KR4] = {
130		.subtype = IFM_100G_KR4,
131		.baudrate = IF_Gbps(100ULL),
132	},
133	[MLX5E_100GBASE_LR4] = {
134		.subtype = IFM_100G_LR4,
135		.baudrate = IF_Gbps(100ULL),
136	},
137	[MLX5E_100BASE_TX] = {
138		.subtype = IFM_100_TX,
139		.baudrate = IF_Mbps(100ULL),
140	},
141	[MLX5E_100BASE_T] = {
142		.subtype = IFM_100_T,
143		.baudrate = IF_Mbps(100ULL),
144	},
145	[MLX5E_10GBASE_T] = {
146		.subtype = IFM_10G_T,
147		.baudrate = IF_Gbps(10ULL),
148	},
149	[MLX5E_25GBASE_CR] = {
150		.subtype = IFM_25G_CR,
151		.baudrate = IF_Gbps(25ULL),
152	},
153	[MLX5E_25GBASE_KR] = {
154		.subtype = IFM_25G_KR,
155		.baudrate = IF_Gbps(25ULL),
156	},
157	[MLX5E_25GBASE_SR] = {
158		.subtype = IFM_25G_SR,
159		.baudrate = IF_Gbps(25ULL),
160	},
161	[MLX5E_50GBASE_CR2] = {
162		.subtype = IFM_50G_CR2,
163		.baudrate = IF_Gbps(50ULL),
164	},
165	[MLX5E_50GBASE_KR2] = {
166		.subtype = IFM_50G_KR2,
167		.baudrate = IF_Gbps(50ULL),
168	},
169};
170
171MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
172
173static void
174mlx5e_update_carrier(struct mlx5e_priv *priv)
175{
176	struct mlx5_core_dev *mdev = priv->mdev;
177	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
178	u32 eth_proto_oper;
179	int error;
180	u8 port_state;
181	u8 i;
182
183	port_state = mlx5_query_vport_state(mdev,
184	    MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
185
186	if (port_state == VPORT_STATE_UP) {
187		priv->media_status_last |= IFM_ACTIVE;
188	} else {
189		priv->media_status_last &= ~IFM_ACTIVE;
190		priv->media_active_last = IFM_ETHER;
191		if_link_state_change(priv->ifp, LINK_STATE_DOWN);
192		return;
193	}
194
195	error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN);
196	if (error) {
197		priv->media_active_last = IFM_ETHER;
198		priv->ifp->if_baudrate = 1;
199		if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
200		    __func__, error);
201		return;
202	}
203	eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
204
205	for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
206		if (mlx5e_mode_table[i].baudrate == 0)
207			continue;
208		if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
209			priv->ifp->if_baudrate =
210			    mlx5e_mode_table[i].baudrate;
211			priv->media_active_last =
212			    mlx5e_mode_table[i].subtype | IFM_ETHER | IFM_FDX;
213		}
214	}
215	if_link_state_change(priv->ifp, LINK_STATE_UP);
216}
217
218static void
219mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
220{
221	struct mlx5e_priv *priv = dev->if_softc;
222
223	ifmr->ifm_status = priv->media_status_last;
224	ifmr->ifm_active = priv->media_active_last |
225	    (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
226	    (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
227
228}
229
230static u32
231mlx5e_find_link_mode(u32 subtype)
232{
233	u32 i;
234	u32 link_mode = 0;
235
236	for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
237		if (mlx5e_mode_table[i].baudrate == 0)
238			continue;
239		if (mlx5e_mode_table[i].subtype == subtype)
240			link_mode |= MLX5E_PROT_MASK(i);
241	}
242
243	return (link_mode);
244}
245
246static int
247mlx5e_media_change(struct ifnet *dev)
248{
249	struct mlx5e_priv *priv = dev->if_softc;
250	struct mlx5_core_dev *mdev = priv->mdev;
251	u32 eth_proto_cap;
252	u32 link_mode;
253	int was_opened;
254	int locked;
255	int error;
256
257	locked = PRIV_LOCKED(priv);
258	if (!locked)
259		PRIV_LOCK(priv);
260
261	if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
262		error = EINVAL;
263		goto done;
264	}
265	link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
266
267	/* query supported capabilities */
268	error = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
269	if (error != 0) {
270		if_printf(dev, "Query port media capability failed\n");
271		goto done;
272	}
273	/* check for autoselect */
274	if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
275		link_mode = eth_proto_cap;
276		if (link_mode == 0) {
277			if_printf(dev, "Port media capability is zero\n");
278			error = EINVAL;
279			goto done;
280		}
281	} else {
282		link_mode = link_mode & eth_proto_cap;
283		if (link_mode == 0) {
284			if_printf(dev, "Not supported link mode requested\n");
285			error = EINVAL;
286			goto done;
287		}
288	}
289	/* update pauseframe control bits */
290	priv->params.rx_pauseframe_control =
291	    (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
292	priv->params.tx_pauseframe_control =
293	    (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
294
295	/* check if device is opened */
296	was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
297
298	/* reconfigure the hardware */
299	mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
300	mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
301	mlx5_set_port_pause(mdev, 1,
302	    priv->params.rx_pauseframe_control,
303	    priv->params.tx_pauseframe_control);
304	if (was_opened)
305		mlx5_set_port_status(mdev, MLX5_PORT_UP);
306
307done:
308	if (!locked)
309		PRIV_UNLOCK(priv);
310	return (error);
311}
312
313static void
314mlx5e_update_carrier_work(struct work_struct *work)
315{
316	struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
317	    update_carrier_work);
318
319	PRIV_LOCK(priv);
320	if (test_bit(MLX5E_STATE_OPENED, &priv->state))
321		mlx5e_update_carrier(priv);
322	PRIV_UNLOCK(priv);
323}
324
325static void
326mlx5e_update_pport_counters(struct mlx5e_priv *priv)
327{
328	struct mlx5_core_dev *mdev = priv->mdev;
329	struct mlx5e_pport_stats *s = &priv->stats.pport;
330	struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
331	u32 *in;
332	u32 *out;
333	u64 *ptr;
334	unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
335	unsigned x;
336	unsigned y;
337
338	in = mlx5_vzalloc(sz);
339	out = mlx5_vzalloc(sz);
340	if (in == NULL || out == NULL)
341		goto free_out;
342
343	ptr = (uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
344
345	MLX5_SET(ppcnt_reg, in, local_port, 1);
346
347	MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
348	mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
349	for (x = y = 0; x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
350		s->arg[y] = be64toh(ptr[x]);
351
352	MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
353	mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
354	for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
355		s->arg[y] = be64toh(ptr[x]);
356	for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
357	    MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
358		s_debug->arg[y] = be64toh(ptr[x]);
359
360	MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
361	mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
362	for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
363		s_debug->arg[y] = be64toh(ptr[x]);
364
365	MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
366	mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
367	for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
368		s_debug->arg[y] = be64toh(ptr[x]);
369free_out:
370	kvfree(in);
371	kvfree(out);
372}
373
374static void
375mlx5e_update_stats_work(struct work_struct *work)
376{
377	struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
378	    update_stats_work);
379	struct mlx5_core_dev *mdev = priv->mdev;
380	struct mlx5e_vport_stats *s = &priv->stats.vport;
381	struct mlx5e_rq_stats *rq_stats;
382	struct mlx5e_sq_stats *sq_stats;
383	struct buf_ring *sq_br;
384#if (__FreeBSD_version < 1100000)
385	struct ifnet *ifp = priv->ifp;
386#endif
387
388	u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
389	u32 *out;
390	int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
391	u64 tso_packets = 0;
392	u64 tso_bytes = 0;
393	u64 tx_queue_dropped = 0;
394	u64 tx_defragged = 0;
395	u64 tx_offload_none = 0;
396	u64 lro_packets = 0;
397	u64 lro_bytes = 0;
398	u64 sw_lro_queued = 0;
399	u64 sw_lro_flushed = 0;
400	u64 rx_csum_none = 0;
401	u64 rx_wqe_err = 0;
402	u32 rx_out_of_buffer = 0;
403	int i;
404	int j;
405
406	PRIV_LOCK(priv);
407	out = mlx5_vzalloc(outlen);
408	if (out == NULL)
409		goto free_out;
410	if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
411		goto free_out;
412
413	/* Collect firts the SW counters and then HW for consistency */
414	for (i = 0; i < priv->params.num_channels; i++) {
415		struct mlx5e_rq *rq = &priv->channel[i]->rq;
416
417		rq_stats = &priv->channel[i]->rq.stats;
418
419		/* collect stats from LRO */
420		rq_stats->sw_lro_queued = rq->lro.lro_queued;
421		rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
422		sw_lro_queued += rq_stats->sw_lro_queued;
423		sw_lro_flushed += rq_stats->sw_lro_flushed;
424		lro_packets += rq_stats->lro_packets;
425		lro_bytes += rq_stats->lro_bytes;
426		rx_csum_none += rq_stats->csum_none;
427		rx_wqe_err += rq_stats->wqe_err;
428
429		for (j = 0; j < priv->num_tc; j++) {
430			sq_stats = &priv->channel[i]->sq[j].stats;
431			sq_br = priv->channel[i]->sq[j].br;
432
433			tso_packets += sq_stats->tso_packets;
434			tso_bytes += sq_stats->tso_bytes;
435			tx_queue_dropped += sq_stats->dropped;
436			tx_queue_dropped += sq_br->br_drops;
437			tx_defragged += sq_stats->defragged;
438			tx_offload_none += sq_stats->csum_offload_none;
439		}
440	}
441
442	/* update counters */
443	s->tso_packets = tso_packets;
444	s->tso_bytes = tso_bytes;
445	s->tx_queue_dropped = tx_queue_dropped;
446	s->tx_defragged = tx_defragged;
447	s->lro_packets = lro_packets;
448	s->lro_bytes = lro_bytes;
449	s->sw_lro_queued = sw_lro_queued;
450	s->sw_lro_flushed = sw_lro_flushed;
451	s->rx_csum_none = rx_csum_none;
452	s->rx_wqe_err = rx_wqe_err;
453
454	/* HW counters */
455	memset(in, 0, sizeof(in));
456
457	MLX5_SET(query_vport_counter_in, in, opcode,
458	    MLX5_CMD_OP_QUERY_VPORT_COUNTER);
459	MLX5_SET(query_vport_counter_in, in, op_mod, 0);
460	MLX5_SET(query_vport_counter_in, in, other_vport, 0);
461
462	memset(out, 0, outlen);
463
464	/* get number of out-of-buffer drops first */
465	if (mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
466	    &rx_out_of_buffer))
467		goto free_out;
468
469	/* accumulate difference into a 64-bit counter */
470	s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer - s->rx_out_of_buffer_prev);
471	s->rx_out_of_buffer_prev = rx_out_of_buffer;
472
473	/* get port statistics */
474	if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
475		goto free_out;
476
477#define	MLX5_GET_CTR(out, x) \
478	MLX5_GET64(query_vport_counter_out, out, x)
479
480	s->rx_error_packets =
481	    MLX5_GET_CTR(out, received_errors.packets);
482	s->rx_error_bytes =
483	    MLX5_GET_CTR(out, received_errors.octets);
484	s->tx_error_packets =
485	    MLX5_GET_CTR(out, transmit_errors.packets);
486	s->tx_error_bytes =
487	    MLX5_GET_CTR(out, transmit_errors.octets);
488
489	s->rx_unicast_packets =
490	    MLX5_GET_CTR(out, received_eth_unicast.packets);
491	s->rx_unicast_bytes =
492	    MLX5_GET_CTR(out, received_eth_unicast.octets);
493	s->tx_unicast_packets =
494	    MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
495	s->tx_unicast_bytes =
496	    MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
497
498	s->rx_multicast_packets =
499	    MLX5_GET_CTR(out, received_eth_multicast.packets);
500	s->rx_multicast_bytes =
501	    MLX5_GET_CTR(out, received_eth_multicast.octets);
502	s->tx_multicast_packets =
503	    MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
504	s->tx_multicast_bytes =
505	    MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
506
507	s->rx_broadcast_packets =
508	    MLX5_GET_CTR(out, received_eth_broadcast.packets);
509	s->rx_broadcast_bytes =
510	    MLX5_GET_CTR(out, received_eth_broadcast.octets);
511	s->tx_broadcast_packets =
512	    MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
513	s->tx_broadcast_bytes =
514	    MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
515
516	s->rx_packets =
517	    s->rx_unicast_packets +
518	    s->rx_multicast_packets +
519	    s->rx_broadcast_packets -
520	    s->rx_out_of_buffer;
521	s->rx_bytes =
522	    s->rx_unicast_bytes +
523	    s->rx_multicast_bytes +
524	    s->rx_broadcast_bytes;
525	s->tx_packets =
526	    s->tx_unicast_packets +
527	    s->tx_multicast_packets +
528	    s->tx_broadcast_packets;
529	s->tx_bytes =
530	    s->tx_unicast_bytes +
531	    s->tx_multicast_bytes +
532	    s->tx_broadcast_bytes;
533
534	/* Update calculated offload counters */
535	s->tx_csum_offload = s->tx_packets - tx_offload_none;
536	s->rx_csum_good = s->rx_packets - s->rx_csum_none;
537
538	/* Update per port counters */
539	mlx5e_update_pport_counters(priv);
540
541#if (__FreeBSD_version < 1100000)
542	/* no get_counters interface in fbsd 10 */
543	ifp->if_ipackets = s->rx_packets;
544	ifp->if_ierrors = s->rx_error_packets;
545	ifp->if_iqdrops = s->rx_out_of_buffer;
546	ifp->if_opackets = s->tx_packets;
547	ifp->if_oerrors = s->tx_error_packets;
548	ifp->if_snd.ifq_drops = s->tx_queue_dropped;
549	ifp->if_ibytes = s->rx_bytes;
550	ifp->if_obytes = s->tx_bytes;
551#endif
552
553free_out:
554	kvfree(out);
555	PRIV_UNLOCK(priv);
556}
557
558static void
559mlx5e_update_stats(void *arg)
560{
561	struct mlx5e_priv *priv = arg;
562
563	schedule_work(&priv->update_stats_work);
564
565	callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
566}
567
568static void
569mlx5e_async_event_sub(struct mlx5e_priv *priv,
570    enum mlx5_dev_event event)
571{
572	switch (event) {
573	case MLX5_DEV_EVENT_PORT_UP:
574	case MLX5_DEV_EVENT_PORT_DOWN:
575		schedule_work(&priv->update_carrier_work);
576		break;
577
578	default:
579		break;
580	}
581}
582
583static void
584mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
585    enum mlx5_dev_event event, unsigned long param)
586{
587	struct mlx5e_priv *priv = vpriv;
588
589	mtx_lock(&priv->async_events_mtx);
590	if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
591		mlx5e_async_event_sub(priv, event);
592	mtx_unlock(&priv->async_events_mtx);
593}
594
595static void
596mlx5e_enable_async_events(struct mlx5e_priv *priv)
597{
598	set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
599}
600
601static void
602mlx5e_disable_async_events(struct mlx5e_priv *priv)
603{
604	mtx_lock(&priv->async_events_mtx);
605	clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
606	mtx_unlock(&priv->async_events_mtx);
607}
608
609static const char *mlx5e_rq_stats_desc[] = {
610	MLX5E_RQ_STATS(MLX5E_STATS_DESC)
611};
612
613static int
614mlx5e_create_rq(struct mlx5e_channel *c,
615    struct mlx5e_rq_param *param,
616    struct mlx5e_rq *rq)
617{
618	struct mlx5e_priv *priv = c->priv;
619	struct mlx5_core_dev *mdev = priv->mdev;
620	char buffer[16];
621	void *rqc = param->rqc;
622	void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
623	int wq_sz;
624	int err;
625	int i;
626
627	/* Create DMA descriptor TAG */
628	if ((err = -bus_dma_tag_create(
629	    bus_get_dma_tag(mdev->pdev->dev.bsddev),
630	    1,				/* any alignment */
631	    0,				/* no boundary */
632	    BUS_SPACE_MAXADDR,		/* lowaddr */
633	    BUS_SPACE_MAXADDR,		/* highaddr */
634	    NULL, NULL,			/* filter, filterarg */
635	    MJUM16BYTES,		/* maxsize */
636	    1,				/* nsegments */
637	    MJUM16BYTES,		/* maxsegsize */
638	    0,				/* flags */
639	    NULL, NULL,			/* lockfunc, lockfuncarg */
640	    &rq->dma_tag)))
641		goto done;
642
643	err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
644	    &rq->wq_ctrl);
645	if (err)
646		goto err_free_dma_tag;
647
648	rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
649
650	if (priv->params.hw_lro_en) {
651		rq->wqe_sz = priv->params.lro_wqe_sz;
652	} else {
653		rq->wqe_sz = MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
654	}
655	if (rq->wqe_sz > MJUM16BYTES) {
656		err = -ENOMEM;
657		goto err_rq_wq_destroy;
658	} else if (rq->wqe_sz > MJUM9BYTES) {
659		rq->wqe_sz = MJUM16BYTES;
660	} else if (rq->wqe_sz > MJUMPAGESIZE) {
661		rq->wqe_sz = MJUM9BYTES;
662	} else if (rq->wqe_sz > MCLBYTES) {
663		rq->wqe_sz = MJUMPAGESIZE;
664	} else {
665		rq->wqe_sz = MCLBYTES;
666	}
667
668	wq_sz = mlx5_wq_ll_get_size(&rq->wq);
669
670	err = -tcp_lro_init_args(&rq->lro, c->ifp, TCP_LRO_ENTRIES, wq_sz);
671	if (err)
672		goto err_rq_wq_destroy;
673
674	rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
675	if (rq->mbuf == NULL) {
676		err = -ENOMEM;
677		goto err_lro_init;
678	}
679	for (i = 0; i != wq_sz; i++) {
680		struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
681		uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
682
683		err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
684		if (err != 0) {
685			while (i--)
686				bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
687			goto err_rq_mbuf_free;
688		}
689		wqe->data.lkey = c->mkey_be;
690		wqe->data.byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
691	}
692
693	rq->pdev = c->pdev;
694	rq->ifp = c->ifp;
695	rq->channel = c;
696	rq->ix = c->ix;
697
698	snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
699	mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
700	    buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
701	    rq->stats.arg);
702	return (0);
703
704err_rq_mbuf_free:
705	free(rq->mbuf, M_MLX5EN);
706err_lro_init:
707	tcp_lro_free(&rq->lro);
708err_rq_wq_destroy:
709	mlx5_wq_destroy(&rq->wq_ctrl);
710err_free_dma_tag:
711	bus_dma_tag_destroy(rq->dma_tag);
712done:
713	return (err);
714}
715
716static void
717mlx5e_destroy_rq(struct mlx5e_rq *rq)
718{
719	int wq_sz;
720	int i;
721
722	/* destroy all sysctl nodes */
723	sysctl_ctx_free(&rq->stats.ctx);
724
725	/* free leftover LRO packets, if any */
726	tcp_lro_free(&rq->lro);
727
728	wq_sz = mlx5_wq_ll_get_size(&rq->wq);
729	for (i = 0; i != wq_sz; i++) {
730		if (rq->mbuf[i].mbuf != NULL) {
731			bus_dmamap_unload(rq->dma_tag,
732			    rq->mbuf[i].dma_map);
733			m_freem(rq->mbuf[i].mbuf);
734		}
735		bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
736	}
737	free(rq->mbuf, M_MLX5EN);
738	mlx5_wq_destroy(&rq->wq_ctrl);
739}
740
741static int
742mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
743{
744	struct mlx5e_channel *c = rq->channel;
745	struct mlx5e_priv *priv = c->priv;
746	struct mlx5_core_dev *mdev = priv->mdev;
747
748	void *in;
749	void *rqc;
750	void *wq;
751	int inlen;
752	int err;
753
754	inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
755	    sizeof(u64) * rq->wq_ctrl.buf.npages;
756	in = mlx5_vzalloc(inlen);
757	if (in == NULL)
758		return (-ENOMEM);
759
760	rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
761	wq = MLX5_ADDR_OF(rqc, rqc, wq);
762
763	memcpy(rqc, param->rqc, sizeof(param->rqc));
764
765	MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
766	MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
767	MLX5_SET(rqc, rqc, flush_in_error_en, 1);
768	if (priv->counter_set_id >= 0)
769		MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
770	MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
771	    PAGE_SHIFT);
772	MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
773
774	mlx5_fill_page_array(&rq->wq_ctrl.buf,
775	    (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
776
777	err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
778
779	kvfree(in);
780
781	return (err);
782}
783
784static int
785mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
786{
787	struct mlx5e_channel *c = rq->channel;
788	struct mlx5e_priv *priv = c->priv;
789	struct mlx5_core_dev *mdev = priv->mdev;
790
791	void *in;
792	void *rqc;
793	int inlen;
794	int err;
795
796	inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
797	in = mlx5_vzalloc(inlen);
798	if (in == NULL)
799		return (-ENOMEM);
800
801	rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
802
803	MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
804	MLX5_SET(modify_rq_in, in, rq_state, curr_state);
805	MLX5_SET(rqc, rqc, state, next_state);
806
807	err = mlx5_core_modify_rq(mdev, in, inlen);
808
809	kvfree(in);
810
811	return (err);
812}
813
814static void
815mlx5e_disable_rq(struct mlx5e_rq *rq)
816{
817	struct mlx5e_channel *c = rq->channel;
818	struct mlx5e_priv *priv = c->priv;
819	struct mlx5_core_dev *mdev = priv->mdev;
820
821	mlx5_core_destroy_rq(mdev, rq->rqn);
822}
823
824static int
825mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
826{
827	struct mlx5e_channel *c = rq->channel;
828	struct mlx5e_priv *priv = c->priv;
829	struct mlx5_wq_ll *wq = &rq->wq;
830	int i;
831
832	for (i = 0; i < 1000; i++) {
833		if (wq->cur_sz >= priv->params.min_rx_wqes)
834			return (0);
835
836		msleep(4);
837	}
838	return (-ETIMEDOUT);
839}
840
841static int
842mlx5e_open_rq(struct mlx5e_channel *c,
843    struct mlx5e_rq_param *param,
844    struct mlx5e_rq *rq)
845{
846	int err;
847
848	err = mlx5e_create_rq(c, param, rq);
849	if (err)
850		return (err);
851
852	err = mlx5e_enable_rq(rq, param);
853	if (err)
854		goto err_destroy_rq;
855
856	err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
857	if (err)
858		goto err_disable_rq;
859
860	c->rq.enabled = 1;
861
862	return (0);
863
864err_disable_rq:
865	mlx5e_disable_rq(rq);
866err_destroy_rq:
867	mlx5e_destroy_rq(rq);
868
869	return (err);
870}
871
872static void
873mlx5e_close_rq(struct mlx5e_rq *rq)
874{
875	rq->enabled = 0;
876	mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
877}
878
879static void
880mlx5e_close_rq_wait(struct mlx5e_rq *rq)
881{
882	/* wait till RQ is empty */
883	while (!mlx5_wq_ll_is_empty(&rq->wq)) {
884		msleep(4);
885		rq->cq.mcq.comp(&rq->cq.mcq);
886	}
887
888	mlx5e_disable_rq(rq);
889	mlx5e_destroy_rq(rq);
890}
891
892static void
893mlx5e_free_sq_db(struct mlx5e_sq *sq)
894{
895	int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
896	int x;
897
898	for (x = 0; x != wq_sz; x++)
899		bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
900	free(sq->mbuf, M_MLX5EN);
901}
902
903static int
904mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
905{
906	int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
907	int err;
908	int x;
909
910	sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
911	if (sq->mbuf == NULL)
912		return (-ENOMEM);
913
914	/* Create DMA descriptor MAPs */
915	for (x = 0; x != wq_sz; x++) {
916		err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
917		if (err != 0) {
918			while (x--)
919				bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
920			free(sq->mbuf, M_MLX5EN);
921			return (err);
922		}
923	}
924	return (0);
925}
926
927static const char *mlx5e_sq_stats_desc[] = {
928	MLX5E_SQ_STATS(MLX5E_STATS_DESC)
929};
930
931static int
932mlx5e_create_sq(struct mlx5e_channel *c,
933    int tc,
934    struct mlx5e_sq_param *param,
935    struct mlx5e_sq *sq)
936{
937	struct mlx5e_priv *priv = c->priv;
938	struct mlx5_core_dev *mdev = priv->mdev;
939	char buffer[16];
940
941	void *sqc = param->sqc;
942	void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
943#ifdef RSS
944	cpuset_t cpu_mask;
945	int cpu_id;
946#endif
947	int err;
948
949	/* Create DMA descriptor TAG */
950	if ((err = -bus_dma_tag_create(
951	    bus_get_dma_tag(mdev->pdev->dev.bsddev),
952	    1,				/* any alignment */
953	    0,				/* no boundary */
954	    BUS_SPACE_MAXADDR,		/* lowaddr */
955	    BUS_SPACE_MAXADDR,		/* highaddr */
956	    NULL, NULL,			/* filter, filterarg */
957	    MLX5E_MAX_TX_PAYLOAD_SIZE,	/* maxsize */
958	    MLX5E_MAX_TX_MBUF_FRAGS,	/* nsegments */
959	    MLX5E_MAX_TX_MBUF_SIZE,	/* maxsegsize */
960	    0,				/* flags */
961	    NULL, NULL,			/* lockfunc, lockfuncarg */
962	    &sq->dma_tag)))
963		goto done;
964
965	err = mlx5_alloc_map_uar(mdev, &sq->uar);
966	if (err)
967		goto err_free_dma_tag;
968
969	err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
970	    &sq->wq_ctrl);
971	if (err)
972		goto err_unmap_free_uar;
973
974	sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
975	sq->uar_map = sq->uar.map;
976	sq->uar_bf_map = sq->uar.bf_map;
977	sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
978
979	err = mlx5e_alloc_sq_db(sq);
980	if (err)
981		goto err_sq_wq_destroy;
982
983	sq->pdev = c->pdev;
984	sq->mkey_be = c->mkey_be;
985	sq->channel = c;
986	sq->tc = tc;
987
988	sq->br = buf_ring_alloc(MLX5E_SQ_TX_QUEUE_SIZE, M_MLX5EN,
989	    M_WAITOK, &sq->lock);
990	if (sq->br == NULL) {
991		if_printf(c->ifp, "%s: Failed allocating sq drbr buffer\n",
992		    __func__);
993		err = -ENOMEM;
994		goto err_free_sq_db;
995	}
996
997	sq->sq_tq = taskqueue_create_fast("mlx5e_que", M_WAITOK,
998	    taskqueue_thread_enqueue, &sq->sq_tq);
999	if (sq->sq_tq == NULL) {
1000		if_printf(c->ifp, "%s: Failed allocating taskqueue\n",
1001		    __func__);
1002		err = -ENOMEM;
1003		goto err_free_drbr;
1004	}
1005
1006	TASK_INIT(&sq->sq_task, 0, mlx5e_tx_que, sq);
1007#ifdef RSS
1008	cpu_id = rss_getcpu(c->ix % rss_getnumbuckets());
1009	CPU_SETOF(cpu_id, &cpu_mask);
1010	taskqueue_start_threads_cpuset(&sq->sq_tq, 1, PI_NET, &cpu_mask,
1011	    "%s TX SQ%d.%d CPU%d", c->ifp->if_xname, c->ix, tc, cpu_id);
1012#else
1013	taskqueue_start_threads(&sq->sq_tq, 1, PI_NET,
1014	    "%s TX SQ%d.%d", c->ifp->if_xname, c->ix, tc);
1015#endif
1016	snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1017	mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1018	    buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1019	    sq->stats.arg);
1020
1021	return (0);
1022
1023err_free_drbr:
1024	buf_ring_free(sq->br, M_MLX5EN);
1025err_free_sq_db:
1026	mlx5e_free_sq_db(sq);
1027err_sq_wq_destroy:
1028	mlx5_wq_destroy(&sq->wq_ctrl);
1029
1030err_unmap_free_uar:
1031	mlx5_unmap_free_uar(mdev, &sq->uar);
1032
1033err_free_dma_tag:
1034	bus_dma_tag_destroy(sq->dma_tag);
1035done:
1036	return (err);
1037}
1038
1039static void
1040mlx5e_destroy_sq(struct mlx5e_sq *sq)
1041{
1042	struct mlx5e_channel *c = sq->channel;
1043	struct mlx5e_priv *priv = c->priv;
1044
1045	/* destroy all sysctl nodes */
1046	sysctl_ctx_free(&sq->stats.ctx);
1047
1048	mlx5e_free_sq_db(sq);
1049	mlx5_wq_destroy(&sq->wq_ctrl);
1050	mlx5_unmap_free_uar(priv->mdev, &sq->uar);
1051	taskqueue_drain(sq->sq_tq, &sq->sq_task);
1052	taskqueue_free(sq->sq_tq);
1053	buf_ring_free(sq->br, M_MLX5EN);
1054}
1055
1056static int
1057mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
1058{
1059	struct mlx5e_channel *c = sq->channel;
1060	struct mlx5e_priv *priv = c->priv;
1061	struct mlx5_core_dev *mdev = priv->mdev;
1062
1063	void *in;
1064	void *sqc;
1065	void *wq;
1066	int inlen;
1067	int err;
1068
1069	inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1070	    sizeof(u64) * sq->wq_ctrl.buf.npages;
1071	in = mlx5_vzalloc(inlen);
1072	if (in == NULL)
1073		return (-ENOMEM);
1074
1075	sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1076	wq = MLX5_ADDR_OF(sqc, sqc, wq);
1077
1078	memcpy(sqc, param->sqc, sizeof(param->sqc));
1079
1080	MLX5_SET(sqc, sqc, tis_num_0, priv->tisn[sq->tc]);
1081	MLX5_SET(sqc, sqc, cqn, c->sq[sq->tc].cq.mcq.cqn);
1082	MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1083	MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1084	MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1085
1086	MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1087	MLX5_SET(wq, wq, uar_page, sq->uar.index);
1088	MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1089	    PAGE_SHIFT);
1090	MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1091
1092	mlx5_fill_page_array(&sq->wq_ctrl.buf,
1093	    (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1094
1095	err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
1096
1097	kvfree(in);
1098
1099	return (err);
1100}
1101
1102static int
1103mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1104{
1105	struct mlx5e_channel *c = sq->channel;
1106	struct mlx5e_priv *priv = c->priv;
1107	struct mlx5_core_dev *mdev = priv->mdev;
1108
1109	void *in;
1110	void *sqc;
1111	int inlen;
1112	int err;
1113
1114	inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1115	in = mlx5_vzalloc(inlen);
1116	if (in == NULL)
1117		return (-ENOMEM);
1118
1119	sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1120
1121	MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1122	MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1123	MLX5_SET(sqc, sqc, state, next_state);
1124
1125	err = mlx5_core_modify_sq(mdev, in, inlen);
1126
1127	kvfree(in);
1128
1129	return (err);
1130}
1131
1132static void
1133mlx5e_disable_sq(struct mlx5e_sq *sq)
1134{
1135	struct mlx5e_channel *c = sq->channel;
1136	struct mlx5e_priv *priv = c->priv;
1137	struct mlx5_core_dev *mdev = priv->mdev;
1138
1139	mlx5_core_destroy_sq(mdev, sq->sqn);
1140}
1141
1142static int
1143mlx5e_open_sq(struct mlx5e_channel *c,
1144    int tc,
1145    struct mlx5e_sq_param *param,
1146    struct mlx5e_sq *sq)
1147{
1148	int err;
1149
1150	err = mlx5e_create_sq(c, tc, param, sq);
1151	if (err)
1152		return (err);
1153
1154	err = mlx5e_enable_sq(sq, param);
1155	if (err)
1156		goto err_destroy_sq;
1157
1158	err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1159	if (err)
1160		goto err_disable_sq;
1161
1162	atomic_store_rel_int(&sq->queue_state, MLX5E_SQ_READY);
1163
1164	return (0);
1165
1166err_disable_sq:
1167	mlx5e_disable_sq(sq);
1168err_destroy_sq:
1169	mlx5e_destroy_sq(sq);
1170
1171	return (err);
1172}
1173
1174static void
1175mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1176{
1177	/* fill up remainder with NOPs */
1178	while (sq->cev_counter != 0) {
1179		while (!mlx5e_sq_has_room_for(sq, 1)) {
1180			if (can_sleep != 0) {
1181				mtx_unlock(&sq->lock);
1182				msleep(4);
1183				mtx_lock(&sq->lock);
1184			} else {
1185				goto done;
1186			}
1187		}
1188		/* send a single NOP */
1189		mlx5e_send_nop(sq, 1);
1190		wmb();
1191	}
1192done:
1193	/* Check if we need to write the doorbell */
1194	if (likely(sq->doorbell.d64 != 0)) {
1195		mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1196		sq->doorbell.d64 = 0;
1197	}
1198	return;
1199}
1200
1201void
1202mlx5e_sq_cev_timeout(void *arg)
1203{
1204	struct mlx5e_sq *sq = arg;
1205
1206	mtx_assert(&sq->lock, MA_OWNED);
1207
1208	/* check next state */
1209	switch (sq->cev_next_state) {
1210	case MLX5E_CEV_STATE_SEND_NOPS:
1211		/* fill TX ring with NOPs, if any */
1212		mlx5e_sq_send_nops_locked(sq, 0);
1213
1214		/* check if completed */
1215		if (sq->cev_counter == 0) {
1216			sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1217			return;
1218		}
1219		break;
1220	default:
1221		/* send NOPs on next timeout */
1222		sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1223		break;
1224	}
1225
1226	/* restart timer */
1227	callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1228}
1229
1230static void
1231mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1232{
1233
1234	mtx_lock(&sq->lock);
1235	/* teardown event factor timer, if any */
1236	sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1237	callout_stop(&sq->cev_callout);
1238
1239	/* send dummy NOPs in order to flush the transmit ring */
1240	mlx5e_sq_send_nops_locked(sq, 1);
1241	mtx_unlock(&sq->lock);
1242
1243	/* make sure it is safe to free the callout */
1244	callout_drain(&sq->cev_callout);
1245
1246	/* error out remaining requests */
1247	mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1248
1249	/* wait till SQ is empty */
1250	mtx_lock(&sq->lock);
1251	while (sq->cc != sq->pc) {
1252		mtx_unlock(&sq->lock);
1253		msleep(4);
1254		sq->cq.mcq.comp(&sq->cq.mcq);
1255		mtx_lock(&sq->lock);
1256	}
1257	mtx_unlock(&sq->lock);
1258
1259	mlx5e_disable_sq(sq);
1260	mlx5e_destroy_sq(sq);
1261}
1262
1263static int
1264mlx5e_create_cq(struct mlx5e_channel *c,
1265    struct mlx5e_cq_param *param,
1266    struct mlx5e_cq *cq,
1267    mlx5e_cq_comp_t *comp)
1268{
1269	struct mlx5e_priv *priv = c->priv;
1270	struct mlx5_core_dev *mdev = priv->mdev;
1271	struct mlx5_core_cq *mcq = &cq->mcq;
1272	int eqn_not_used;
1273	int irqn;
1274	int err;
1275	u32 i;
1276
1277	param->wq.buf_numa_node = 0;
1278	param->wq.db_numa_node = 0;
1279	param->eq_ix = c->ix;
1280
1281	err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1282	    &cq->wq_ctrl);
1283	if (err)
1284		return (err);
1285
1286	mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1287
1288	mcq->cqe_sz = 64;
1289	mcq->set_ci_db = cq->wq_ctrl.db.db;
1290	mcq->arm_db = cq->wq_ctrl.db.db + 1;
1291	*mcq->set_ci_db = 0;
1292	*mcq->arm_db = 0;
1293	mcq->vector = param->eq_ix;
1294	mcq->comp = comp;
1295	mcq->event = mlx5e_cq_error_event;
1296	mcq->irqn = irqn;
1297	mcq->uar = &priv->cq_uar;
1298
1299	for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1300		struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1301
1302		cqe->op_own = 0xf1;
1303	}
1304
1305	cq->channel = c;
1306
1307	return (0);
1308}
1309
1310static void
1311mlx5e_destroy_cq(struct mlx5e_cq *cq)
1312{
1313	mlx5_wq_destroy(&cq->wq_ctrl);
1314}
1315
1316static int
1317mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param,
1318    u8 moderation_mode)
1319{
1320	struct mlx5e_channel *c = cq->channel;
1321	struct mlx5e_priv *priv = c->priv;
1322	struct mlx5_core_dev *mdev = priv->mdev;
1323	struct mlx5_core_cq *mcq = &cq->mcq;
1324	void *in;
1325	void *cqc;
1326	int inlen;
1327	int irqn_not_used;
1328	int eqn;
1329	int err;
1330
1331	inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1332	    sizeof(u64) * cq->wq_ctrl.buf.npages;
1333	in = mlx5_vzalloc(inlen);
1334	if (in == NULL)
1335		return (-ENOMEM);
1336
1337	cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1338
1339	memcpy(cqc, param->cqc, sizeof(param->cqc));
1340
1341	mlx5_fill_page_array(&cq->wq_ctrl.buf,
1342	    (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1343
1344	mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1345
1346	MLX5_SET(cqc, cqc, cq_period_mode, moderation_mode);
1347	MLX5_SET(cqc, cqc, c_eqn, eqn);
1348	MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1349	MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1350	    PAGE_SHIFT);
1351	MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1352
1353	err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1354
1355	kvfree(in);
1356
1357	if (err)
1358		return (err);
1359
1360	mlx5e_cq_arm(cq);
1361
1362	return (0);
1363}
1364
1365static void
1366mlx5e_disable_cq(struct mlx5e_cq *cq)
1367{
1368	struct mlx5e_channel *c = cq->channel;
1369	struct mlx5e_priv *priv = c->priv;
1370	struct mlx5_core_dev *mdev = priv->mdev;
1371
1372	mlx5_core_destroy_cq(mdev, &cq->mcq);
1373}
1374
1375static int
1376mlx5e_open_cq(struct mlx5e_channel *c,
1377    struct mlx5e_cq_param *param,
1378    struct mlx5e_cq *cq,
1379    mlx5e_cq_comp_t *comp,
1380    u8 moderation_mode)
1381{
1382	int err;
1383
1384	err = mlx5e_create_cq(c, param, cq, comp);
1385	if (err)
1386		return (err);
1387
1388	err = mlx5e_enable_cq(cq, param, moderation_mode);
1389	if (err)
1390		goto err_destroy_cq;
1391
1392	return (0);
1393
1394err_destroy_cq:
1395	mlx5e_destroy_cq(cq);
1396
1397	return (err);
1398}
1399
1400static void
1401mlx5e_close_cq(struct mlx5e_cq *cq)
1402{
1403	mlx5e_disable_cq(cq);
1404	mlx5e_destroy_cq(cq);
1405}
1406
1407static int
1408mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1409    struct mlx5e_channel_param *cparam)
1410{
1411	u8 tx_moderation_mode;
1412	int err;
1413	int tc;
1414
1415	switch (c->priv->params.tx_cq_moderation_mode) {
1416	case 0:
1417		tx_moderation_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1418		break;
1419	default:
1420		if (MLX5_CAP_GEN(c->priv->mdev, cq_period_start_from_cqe))
1421			tx_moderation_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
1422		else
1423			tx_moderation_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1424		break;
1425	}
1426	for (tc = 0; tc < c->num_tc; tc++) {
1427		/* open completion queue */
1428		err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1429		    &mlx5e_tx_cq_comp, tx_moderation_mode);
1430		if (err)
1431			goto err_close_tx_cqs;
1432	}
1433	return (0);
1434
1435err_close_tx_cqs:
1436	for (tc--; tc >= 0; tc--)
1437		mlx5e_close_cq(&c->sq[tc].cq);
1438
1439	return (err);
1440}
1441
1442static void
1443mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1444{
1445	int tc;
1446
1447	for (tc = 0; tc < c->num_tc; tc++)
1448		mlx5e_close_cq(&c->sq[tc].cq);
1449}
1450
1451static int
1452mlx5e_open_sqs(struct mlx5e_channel *c,
1453    struct mlx5e_channel_param *cparam)
1454{
1455	int err;
1456	int tc;
1457
1458	for (tc = 0; tc < c->num_tc; tc++) {
1459		err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1460		if (err)
1461			goto err_close_sqs;
1462	}
1463
1464	return (0);
1465
1466err_close_sqs:
1467	for (tc--; tc >= 0; tc--)
1468		mlx5e_close_sq_wait(&c->sq[tc]);
1469
1470	return (err);
1471}
1472
1473static void
1474mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1475{
1476	int tc;
1477
1478	for (tc = 0; tc < c->num_tc; tc++)
1479		mlx5e_close_sq_wait(&c->sq[tc]);
1480}
1481
1482static void
1483mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1484{
1485	int tc;
1486
1487	mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1488
1489	for (tc = 0; tc < c->num_tc; tc++) {
1490		struct mlx5e_sq *sq = c->sq + tc;
1491
1492		mtx_init(&sq->lock, "mlx5tx", MTX_NETWORK_LOCK, MTX_DEF);
1493		mtx_init(&sq->comp_lock, "mlx5comp", MTX_NETWORK_LOCK,
1494		    MTX_DEF);
1495
1496		callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1497
1498		sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1499
1500		/* ensure the TX completion event factor is not zero */
1501		if (sq->cev_factor == 0)
1502			sq->cev_factor = 1;
1503	}
1504}
1505
1506static void
1507mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1508{
1509	int tc;
1510
1511	mtx_destroy(&c->rq.mtx);
1512
1513	for (tc = 0; tc < c->num_tc; tc++) {
1514		mtx_destroy(&c->sq[tc].lock);
1515		mtx_destroy(&c->sq[tc].comp_lock);
1516	}
1517}
1518
1519static int
1520mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1521    struct mlx5e_channel_param *cparam,
1522    struct mlx5e_channel *volatile *cp)
1523{
1524	struct mlx5e_channel *c;
1525	u8 rx_moderation_mode;
1526	int err;
1527
1528	c = malloc(sizeof(*c), M_MLX5EN, M_WAITOK | M_ZERO);
1529	if (c == NULL)
1530		return (-ENOMEM);
1531
1532	c->priv = priv;
1533	c->ix = ix;
1534	c->cpu = 0;
1535	c->pdev = &priv->mdev->pdev->dev;
1536	c->ifp = priv->ifp;
1537	c->mkey_be = cpu_to_be32(priv->mr.key);
1538	c->num_tc = priv->num_tc;
1539
1540	/* init mutexes */
1541	mlx5e_chan_mtx_init(c);
1542
1543	/* open transmit completion queue */
1544	err = mlx5e_open_tx_cqs(c, cparam);
1545	if (err)
1546		goto err_free;
1547
1548	switch (priv->params.rx_cq_moderation_mode) {
1549	case 0:
1550		rx_moderation_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1551		break;
1552	default:
1553		if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1554			rx_moderation_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
1555		else
1556			rx_moderation_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1557		break;
1558	}
1559
1560	/* open receive completion queue */
1561	err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1562	    &mlx5e_rx_cq_comp, rx_moderation_mode);
1563	if (err)
1564		goto err_close_tx_cqs;
1565
1566	err = mlx5e_open_sqs(c, cparam);
1567	if (err)
1568		goto err_close_rx_cq;
1569
1570	err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1571	if (err)
1572		goto err_close_sqs;
1573
1574	/* store channel pointer */
1575	*cp = c;
1576
1577	/* poll receive queue initially */
1578	c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1579
1580	return (0);
1581
1582err_close_sqs:
1583	mlx5e_close_sqs_wait(c);
1584
1585err_close_rx_cq:
1586	mlx5e_close_cq(&c->rq.cq);
1587
1588err_close_tx_cqs:
1589	mlx5e_close_tx_cqs(c);
1590
1591err_free:
1592	/* destroy mutexes */
1593	mlx5e_chan_mtx_destroy(c);
1594	free(c, M_MLX5EN);
1595	return (err);
1596}
1597
1598static void
1599mlx5e_close_channel(struct mlx5e_channel *volatile *pp)
1600{
1601	struct mlx5e_channel *c = *pp;
1602
1603	/* check if channel is already closed */
1604	if (c == NULL)
1605		return;
1606	mlx5e_close_rq(&c->rq);
1607}
1608
1609static void
1610mlx5e_close_channel_wait(struct mlx5e_channel *volatile *pp)
1611{
1612	struct mlx5e_channel *c = *pp;
1613
1614	/* check if channel is already closed */
1615	if (c == NULL)
1616		return;
1617	/* ensure channel pointer is no longer used */
1618	*pp = NULL;
1619
1620	mlx5e_close_rq_wait(&c->rq);
1621	mlx5e_close_sqs_wait(c);
1622	mlx5e_close_cq(&c->rq.cq);
1623	mlx5e_close_tx_cqs(c);
1624	/* destroy mutexes */
1625	mlx5e_chan_mtx_destroy(c);
1626	free(c, M_MLX5EN);
1627}
1628
1629static void
1630mlx5e_build_rq_param(struct mlx5e_priv *priv,
1631    struct mlx5e_rq_param *param)
1632{
1633	void *rqc = param->rqc;
1634	void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1635
1636	MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1637	MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1638	MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1639	MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1640	MLX5_SET(wq, wq, pd, priv->pdn);
1641
1642	param->wq.buf_numa_node = 0;
1643	param->wq.db_numa_node = 0;
1644	param->wq.linear = 1;
1645}
1646
1647static void
1648mlx5e_build_sq_param(struct mlx5e_priv *priv,
1649    struct mlx5e_sq_param *param)
1650{
1651	void *sqc = param->sqc;
1652	void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1653
1654	MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1655	MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1656	MLX5_SET(wq, wq, pd, priv->pdn);
1657
1658	param->wq.buf_numa_node = 0;
1659	param->wq.db_numa_node = 0;
1660	param->wq.linear = 1;
1661}
1662
1663static void
1664mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1665    struct mlx5e_cq_param *param)
1666{
1667	void *cqc = param->cqc;
1668
1669	MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1670}
1671
1672static void
1673mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1674    struct mlx5e_cq_param *param)
1675{
1676	void *cqc = param->cqc;
1677
1678
1679	/*
1680	 * TODO The sysctl to control on/off is a bool value for now, which means
1681	 * we only support CSUM, once HASH is implemnted we'll need to address that.
1682	 */
1683	if (priv->params.cqe_zipping_en) {
1684		MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1685		MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1686	}
1687
1688	MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1689	MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1690	MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1691
1692	mlx5e_build_common_cq_param(priv, param);
1693}
1694
1695static void
1696mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1697    struct mlx5e_cq_param *param)
1698{
1699	void *cqc = param->cqc;
1700
1701	MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1702	MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
1703	MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
1704
1705	mlx5e_build_common_cq_param(priv, param);
1706}
1707
1708static void
1709mlx5e_build_channel_param(struct mlx5e_priv *priv,
1710    struct mlx5e_channel_param *cparam)
1711{
1712	memset(cparam, 0, sizeof(*cparam));
1713
1714	mlx5e_build_rq_param(priv, &cparam->rq);
1715	mlx5e_build_sq_param(priv, &cparam->sq);
1716	mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1717	mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1718}
1719
1720static int
1721mlx5e_open_channels(struct mlx5e_priv *priv)
1722{
1723	struct mlx5e_channel_param cparam;
1724	void *ptr;
1725	int err;
1726	int i;
1727	int j;
1728
1729	priv->channel = malloc(priv->params.num_channels *
1730	    sizeof(struct mlx5e_channel *), M_MLX5EN, M_WAITOK | M_ZERO);
1731	if (priv->channel == NULL)
1732		return (-ENOMEM);
1733
1734	mlx5e_build_channel_param(priv, &cparam);
1735	for (i = 0; i < priv->params.num_channels; i++) {
1736		err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1737		if (err)
1738			goto err_close_channels;
1739	}
1740
1741	for (j = 0; j < priv->params.num_channels; j++) {
1742		err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1743		if (err)
1744			goto err_close_channels;
1745	}
1746
1747	return (0);
1748
1749err_close_channels:
1750	for (i--; i >= 0; i--) {
1751		mlx5e_close_channel(&priv->channel[i]);
1752		mlx5e_close_channel_wait(&priv->channel[i]);
1753	}
1754
1755	/* remove "volatile" attribute from "channel" pointer */
1756	ptr = __DECONST(void *, priv->channel);
1757	priv->channel = NULL;
1758
1759	free(ptr, M_MLX5EN);
1760
1761	return (err);
1762}
1763
1764static void
1765mlx5e_close_channels(struct mlx5e_priv *priv)
1766{
1767	void *ptr;
1768	int i;
1769
1770	if (priv->channel == NULL)
1771		return;
1772
1773	for (i = 0; i < priv->params.num_channels; i++)
1774		mlx5e_close_channel(&priv->channel[i]);
1775	for (i = 0; i < priv->params.num_channels; i++)
1776		mlx5e_close_channel_wait(&priv->channel[i]);
1777
1778	/* remove "volatile" attribute from "channel" pointer */
1779	ptr = __DECONST(void *, priv->channel);
1780	priv->channel = NULL;
1781
1782	free(ptr, M_MLX5EN);
1783}
1784
1785static int
1786mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
1787{
1788	return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
1789	    priv->params.tx_cq_moderation_usec,
1790	    priv->params.tx_cq_moderation_pkts));
1791}
1792
1793static int
1794mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
1795{
1796	return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
1797	    priv->params.rx_cq_moderation_usec,
1798	    priv->params.rx_cq_moderation_pkts));
1799}
1800
1801static int
1802mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1803{
1804	int err;
1805	int i;
1806
1807	if (c == NULL)
1808		return (EINVAL);
1809
1810	err = mlx5e_refresh_rq_params(priv, &c->rq);
1811	if (err)
1812		goto done;
1813
1814	for (i = 0; i != c->num_tc; i++) {
1815		err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
1816		if (err)
1817			goto done;
1818	}
1819done:
1820	return (err);
1821}
1822
1823int
1824mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
1825{
1826	int i;
1827
1828	if (priv->channel == NULL)
1829		return (EINVAL);
1830
1831	for (i = 0; i < priv->params.num_channels; i++) {
1832		int err;
1833
1834		err = mlx5e_refresh_channel_params_sub(priv, priv->channel[i]);
1835		if (err)
1836			return (err);
1837	}
1838	return (0);
1839}
1840
1841static int
1842mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
1843{
1844	struct mlx5_core_dev *mdev = priv->mdev;
1845	u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1846	void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1847
1848	memset(in, 0, sizeof(in));
1849
1850	MLX5_SET(tisc, tisc, prio, tc);
1851	MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1852
1853	return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
1854}
1855
1856static void
1857mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
1858{
1859	mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1860}
1861
1862static int
1863mlx5e_open_tises(struct mlx5e_priv *priv)
1864{
1865	int num_tc = priv->num_tc;
1866	int err;
1867	int tc;
1868
1869	for (tc = 0; tc < num_tc; tc++) {
1870		err = mlx5e_open_tis(priv, tc);
1871		if (err)
1872			goto err_close_tises;
1873	}
1874
1875	return (0);
1876
1877err_close_tises:
1878	for (tc--; tc >= 0; tc--)
1879		mlx5e_close_tis(priv, tc);
1880
1881	return (err);
1882}
1883
1884static void
1885mlx5e_close_tises(struct mlx5e_priv *priv)
1886{
1887	int num_tc = priv->num_tc;
1888	int tc;
1889
1890	for (tc = 0; tc < num_tc; tc++)
1891		mlx5e_close_tis(priv, tc);
1892}
1893
1894static int
1895mlx5e_open_rqt(struct mlx5e_priv *priv)
1896{
1897	struct mlx5_core_dev *mdev = priv->mdev;
1898	u32 *in;
1899	u32 out[MLX5_ST_SZ_DW(create_rqt_out)];
1900	void *rqtc;
1901	int inlen;
1902	int err;
1903	int sz;
1904	int i;
1905
1906	sz = 1 << priv->params.rx_hash_log_tbl_sz;
1907
1908	inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1909	in = mlx5_vzalloc(inlen);
1910	if (in == NULL)
1911		return (-ENOMEM);
1912	rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1913
1914	MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1915	MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1916
1917	for (i = 0; i < sz; i++) {
1918		int ix;
1919#ifdef RSS
1920		ix = rss_get_indirection_to_bucket(i);
1921#else
1922		ix = i;
1923#endif
1924		/* ensure we don't overflow */
1925		ix %= priv->params.num_channels;
1926		MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn);
1927	}
1928
1929	MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1930
1931	memset(out, 0, sizeof(out));
1932	err = mlx5_cmd_exec_check_status(mdev, in, inlen, out, sizeof(out));
1933	if (!err)
1934		priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
1935
1936	kvfree(in);
1937
1938	return (err);
1939}
1940
1941static void
1942mlx5e_close_rqt(struct mlx5e_priv *priv)
1943{
1944	u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)];
1945	u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)];
1946
1947	memset(in, 0, sizeof(in));
1948
1949	MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
1950	MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
1951
1952	mlx5_cmd_exec_check_status(priv->mdev, in, sizeof(in), out,
1953	    sizeof(out));
1954}
1955
1956static void
1957mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
1958{
1959	void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1960	__be32 *hkey;
1961
1962	MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1963
1964#define	ROUGH_MAX_L2_L3_HDR_SZ 256
1965
1966#define	MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1967			  MLX5_HASH_FIELD_SEL_DST_IP)
1968
1969#define	MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1970			  MLX5_HASH_FIELD_SEL_DST_IP   |\
1971			  MLX5_HASH_FIELD_SEL_L4_SPORT |\
1972			  MLX5_HASH_FIELD_SEL_L4_DPORT)
1973
1974#define	MLX5_HASH_IP_IPSEC_SPI	(MLX5_HASH_FIELD_SEL_SRC_IP   |\
1975				 MLX5_HASH_FIELD_SEL_DST_IP   |\
1976				 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1977
1978	if (priv->params.hw_lro_en) {
1979		MLX5_SET(tirc, tirc, lro_enable_mask,
1980		    MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1981		    MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1982		MLX5_SET(tirc, tirc, lro_max_msg_sz,
1983		    (priv->params.lro_wqe_sz -
1984		    ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1985		/* TODO: add the option to choose timer value dynamically */
1986		MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1987		    MLX5_CAP_ETH(priv->mdev,
1988		    lro_timer_supported_periods[2]));
1989	}
1990
1991	/* setup parameters for hashing TIR type, if any */
1992	switch (tt) {
1993	case MLX5E_TT_ANY:
1994		MLX5_SET(tirc, tirc, disp_type,
1995		    MLX5_TIRC_DISP_TYPE_DIRECT);
1996		MLX5_SET(tirc, tirc, inline_rqn,
1997		    priv->channel[0]->rq.rqn);
1998		break;
1999	default:
2000		MLX5_SET(tirc, tirc, disp_type,
2001		    MLX5_TIRC_DISP_TYPE_INDIRECT);
2002		MLX5_SET(tirc, tirc, indirect_table,
2003		    priv->rqtn);
2004		MLX5_SET(tirc, tirc, rx_hash_fn,
2005		    MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2006		hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2007#ifdef RSS
2008		/*
2009		 * The FreeBSD RSS implementation does currently not
2010		 * support symmetric Toeplitz hashes:
2011		 */
2012		MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2013		rss_getkey((uint8_t *)hkey);
2014#else
2015		MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2016		hkey[0] = cpu_to_be32(0xD181C62C);
2017		hkey[1] = cpu_to_be32(0xF7F4DB5B);
2018		hkey[2] = cpu_to_be32(0x1983A2FC);
2019		hkey[3] = cpu_to_be32(0x943E1ADB);
2020		hkey[4] = cpu_to_be32(0xD9389E6B);
2021		hkey[5] = cpu_to_be32(0xD1039C2C);
2022		hkey[6] = cpu_to_be32(0xA74499AD);
2023		hkey[7] = cpu_to_be32(0x593D56D9);
2024		hkey[8] = cpu_to_be32(0xF3253C06);
2025		hkey[9] = cpu_to_be32(0x2ADC1FFC);
2026#endif
2027		break;
2028	}
2029
2030	switch (tt) {
2031	case MLX5E_TT_IPV4_TCP:
2032		MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2033		    MLX5_L3_PROT_TYPE_IPV4);
2034		MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2035		    MLX5_L4_PROT_TYPE_TCP);
2036#ifdef RSS
2037		if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2038			MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2039			    MLX5_HASH_IP);
2040		} else
2041#endif
2042		MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2043		    MLX5_HASH_ALL);
2044		break;
2045
2046	case MLX5E_TT_IPV6_TCP:
2047		MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2048		    MLX5_L3_PROT_TYPE_IPV6);
2049		MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2050		    MLX5_L4_PROT_TYPE_TCP);
2051#ifdef RSS
2052		if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2053			MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2054			    MLX5_HASH_IP);
2055		} else
2056#endif
2057		MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2058		    MLX5_HASH_ALL);
2059		break;
2060
2061	case MLX5E_TT_IPV4_UDP:
2062		MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2063		    MLX5_L3_PROT_TYPE_IPV4);
2064		MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2065		    MLX5_L4_PROT_TYPE_UDP);
2066#ifdef RSS
2067		if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2068			MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2069			    MLX5_HASH_IP);
2070		} else
2071#endif
2072		MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2073		    MLX5_HASH_ALL);
2074		break;
2075
2076	case MLX5E_TT_IPV6_UDP:
2077		MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2078		    MLX5_L3_PROT_TYPE_IPV6);
2079		MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2080		    MLX5_L4_PROT_TYPE_UDP);
2081#ifdef RSS
2082		if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2083			MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2084			    MLX5_HASH_IP);
2085		} else
2086#endif
2087		MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2088		    MLX5_HASH_ALL);
2089		break;
2090
2091	case MLX5E_TT_IPV4_IPSEC_AH:
2092		MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2093		    MLX5_L3_PROT_TYPE_IPV4);
2094		MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2095		    MLX5_HASH_IP_IPSEC_SPI);
2096		break;
2097
2098	case MLX5E_TT_IPV6_IPSEC_AH:
2099		MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2100		    MLX5_L3_PROT_TYPE_IPV6);
2101		MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2102		    MLX5_HASH_IP_IPSEC_SPI);
2103		break;
2104
2105	case MLX5E_TT_IPV4_IPSEC_ESP:
2106		MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2107		    MLX5_L3_PROT_TYPE_IPV4);
2108		MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2109		    MLX5_HASH_IP_IPSEC_SPI);
2110		break;
2111
2112	case MLX5E_TT_IPV6_IPSEC_ESP:
2113		MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2114		    MLX5_L3_PROT_TYPE_IPV6);
2115		MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2116		    MLX5_HASH_IP_IPSEC_SPI);
2117		break;
2118
2119	case MLX5E_TT_IPV4:
2120		MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2121		    MLX5_L3_PROT_TYPE_IPV4);
2122		MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2123		    MLX5_HASH_IP);
2124		break;
2125
2126	case MLX5E_TT_IPV6:
2127		MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2128		    MLX5_L3_PROT_TYPE_IPV6);
2129		MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2130		    MLX5_HASH_IP);
2131		break;
2132
2133	default:
2134		break;
2135	}
2136}
2137
2138static int
2139mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2140{
2141	struct mlx5_core_dev *mdev = priv->mdev;
2142	u32 *in;
2143	void *tirc;
2144	int inlen;
2145	int err;
2146
2147	inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2148	in = mlx5_vzalloc(inlen);
2149	if (in == NULL)
2150		return (-ENOMEM);
2151	tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2152
2153	mlx5e_build_tir_ctx(priv, tirc, tt);
2154
2155	err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2156
2157	kvfree(in);
2158
2159	return (err);
2160}
2161
2162static void
2163mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2164{
2165	mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2166}
2167
2168static int
2169mlx5e_open_tirs(struct mlx5e_priv *priv)
2170{
2171	int err;
2172	int i;
2173
2174	for (i = 0; i < MLX5E_NUM_TT; i++) {
2175		err = mlx5e_open_tir(priv, i);
2176		if (err)
2177			goto err_close_tirs;
2178	}
2179
2180	return (0);
2181
2182err_close_tirs:
2183	for (i--; i >= 0; i--)
2184		mlx5e_close_tir(priv, i);
2185
2186	return (err);
2187}
2188
2189static void
2190mlx5e_close_tirs(struct mlx5e_priv *priv)
2191{
2192	int i;
2193
2194	for (i = 0; i < MLX5E_NUM_TT; i++)
2195		mlx5e_close_tir(priv, i);
2196}
2197
2198/*
2199 * SW MTU does not include headers,
2200 * HW MTU includes all headers and checksums.
2201 */
2202static int
2203mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2204{
2205	struct mlx5e_priv *priv = ifp->if_softc;
2206	struct mlx5_core_dev *mdev = priv->mdev;
2207	int hw_mtu;
2208	int err;
2209
2210
2211	err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(sw_mtu));
2212	if (err) {
2213		if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2214		    __func__, sw_mtu, err);
2215		return (err);
2216	}
2217	err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2218	if (!err) {
2219		ifp->if_mtu = MLX5E_HW2SW_MTU(hw_mtu);
2220
2221		if (ifp->if_mtu != sw_mtu) {
2222			if_printf(ifp, "Port MTU %d is different than "
2223			    "ifp mtu %d\n", sw_mtu, (int)ifp->if_mtu);
2224		}
2225	} else {
2226		if_printf(ifp, "Query port MTU, after setting new "
2227		    "MTU value, failed\n");
2228		ifp->if_mtu = sw_mtu;
2229	}
2230	return (0);
2231}
2232
2233int
2234mlx5e_open_locked(struct ifnet *ifp)
2235{
2236	struct mlx5e_priv *priv = ifp->if_softc;
2237	int err;
2238	u16 set_id;
2239
2240	/* check if already opened */
2241	if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2242		return (0);
2243
2244#ifdef RSS
2245	if (rss_getnumbuckets() > priv->params.num_channels) {
2246		if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2247		    "channels(%u) available\n", rss_getnumbuckets(),
2248		    priv->params.num_channels);
2249	}
2250#endif
2251	err = mlx5e_open_tises(priv);
2252	if (err) {
2253		if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2254		    __func__, err);
2255		return (err);
2256	}
2257	err = mlx5_vport_alloc_q_counter(priv->mdev,
2258	    MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2259	if (err) {
2260		if_printf(priv->ifp,
2261		    "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2262		    __func__, err);
2263		goto err_close_tises;
2264	}
2265	/* store counter set ID */
2266	priv->counter_set_id = set_id;
2267
2268	err = mlx5e_open_channels(priv);
2269	if (err) {
2270		if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2271		    __func__, err);
2272		goto err_dalloc_q_counter;
2273	}
2274	err = mlx5e_open_rqt(priv);
2275	if (err) {
2276		if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2277		    __func__, err);
2278		goto err_close_channels;
2279	}
2280	err = mlx5e_open_tirs(priv);
2281	if (err) {
2282		if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2283		    __func__, err);
2284		goto err_close_rqls;
2285	}
2286	err = mlx5e_open_flow_table(priv);
2287	if (err) {
2288		if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2289		    __func__, err);
2290		goto err_close_tirs;
2291	}
2292	err = mlx5e_add_all_vlan_rules(priv);
2293	if (err) {
2294		if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2295		    __func__, err);
2296		goto err_close_flow_table;
2297	}
2298	set_bit(MLX5E_STATE_OPENED, &priv->state);
2299
2300	mlx5e_update_carrier(priv);
2301	mlx5e_set_rx_mode_core(priv);
2302
2303	return (0);
2304
2305err_close_flow_table:
2306	mlx5e_close_flow_table(priv);
2307
2308err_close_tirs:
2309	mlx5e_close_tirs(priv);
2310
2311err_close_rqls:
2312	mlx5e_close_rqt(priv);
2313
2314err_close_channels:
2315	mlx5e_close_channels(priv);
2316
2317err_dalloc_q_counter:
2318	mlx5_vport_dealloc_q_counter(priv->mdev,
2319	    MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2320
2321err_close_tises:
2322	mlx5e_close_tises(priv);
2323
2324	return (err);
2325}
2326
2327static void
2328mlx5e_open(void *arg)
2329{
2330	struct mlx5e_priv *priv = arg;
2331
2332	PRIV_LOCK(priv);
2333	if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2334		if_printf(priv->ifp,
2335		    "%s: Setting port status to up failed\n",
2336		    __func__);
2337
2338	mlx5e_open_locked(priv->ifp);
2339	priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2340	PRIV_UNLOCK(priv);
2341}
2342
2343int
2344mlx5e_close_locked(struct ifnet *ifp)
2345{
2346	struct mlx5e_priv *priv = ifp->if_softc;
2347
2348	/* check if already closed */
2349	if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2350		return (0);
2351
2352	clear_bit(MLX5E_STATE_OPENED, &priv->state);
2353
2354	mlx5e_set_rx_mode_core(priv);
2355	mlx5e_del_all_vlan_rules(priv);
2356	if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2357	mlx5e_close_flow_table(priv);
2358	mlx5e_close_tirs(priv);
2359	mlx5e_close_rqt(priv);
2360	mlx5e_close_channels(priv);
2361	mlx5_vport_dealloc_q_counter(priv->mdev,
2362	    MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2363	mlx5e_close_tises(priv);
2364
2365	return (0);
2366}
2367
2368#if (__FreeBSD_version >= 1100000)
2369static uint64_t
2370mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2371{
2372	struct mlx5e_priv *priv = ifp->if_softc;
2373	u64 retval;
2374
2375	/* PRIV_LOCK(priv); XXX not allowed */
2376	switch (cnt) {
2377	case IFCOUNTER_IPACKETS:
2378		retval = priv->stats.vport.rx_packets;
2379		break;
2380	case IFCOUNTER_IERRORS:
2381		retval = priv->stats.vport.rx_error_packets;
2382		break;
2383	case IFCOUNTER_IQDROPS:
2384		retval = priv->stats.vport.rx_out_of_buffer;
2385		break;
2386	case IFCOUNTER_OPACKETS:
2387		retval = priv->stats.vport.tx_packets;
2388		break;
2389	case IFCOUNTER_OERRORS:
2390		retval = priv->stats.vport.tx_error_packets;
2391		break;
2392	case IFCOUNTER_IBYTES:
2393		retval = priv->stats.vport.rx_bytes;
2394		break;
2395	case IFCOUNTER_OBYTES:
2396		retval = priv->stats.vport.tx_bytes;
2397		break;
2398	case IFCOUNTER_IMCASTS:
2399		retval = priv->stats.vport.rx_multicast_packets;
2400		break;
2401	case IFCOUNTER_OMCASTS:
2402		retval = priv->stats.vport.tx_multicast_packets;
2403		break;
2404	case IFCOUNTER_OQDROPS:
2405		retval = priv->stats.vport.tx_queue_dropped;
2406		break;
2407	default:
2408		retval = if_get_counter_default(ifp, cnt);
2409		break;
2410	}
2411	/* PRIV_UNLOCK(priv); XXX not allowed */
2412	return (retval);
2413}
2414#endif
2415
2416static void
2417mlx5e_set_rx_mode(struct ifnet *ifp)
2418{
2419	struct mlx5e_priv *priv = ifp->if_softc;
2420
2421	schedule_work(&priv->set_rx_mode_work);
2422}
2423
2424static int
2425mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2426{
2427	struct mlx5e_priv *priv;
2428	struct ifreq *ifr;
2429	struct ifi2creq i2c;
2430	int error = 0;
2431	int mask = 0;
2432	int size_read = 0;
2433	int module_num;
2434	int max_mtu;
2435	uint8_t read_addr;
2436
2437	priv = ifp->if_softc;
2438
2439	/* check if detaching */
2440	if (priv == NULL || priv->gone != 0)
2441		return (ENXIO);
2442
2443	switch (command) {
2444	case SIOCSIFMTU:
2445		ifr = (struct ifreq *)data;
2446
2447		PRIV_LOCK(priv);
2448		mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2449
2450		if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2451		    ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2452			int was_opened;
2453
2454			was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2455			if (was_opened)
2456				mlx5e_close_locked(ifp);
2457
2458			/* set new MTU */
2459			mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2460
2461			if (was_opened)
2462				mlx5e_open_locked(ifp);
2463		} else {
2464			error = EINVAL;
2465			if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2466			    MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2467		}
2468		PRIV_UNLOCK(priv);
2469		break;
2470	case SIOCSIFFLAGS:
2471		if ((ifp->if_flags & IFF_UP) &&
2472		    (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2473			mlx5e_set_rx_mode(ifp);
2474			break;
2475		}
2476		PRIV_LOCK(priv);
2477		if (ifp->if_flags & IFF_UP) {
2478			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2479				if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2480					mlx5e_open_locked(ifp);
2481				ifp->if_drv_flags |= IFF_DRV_RUNNING;
2482				mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2483			}
2484		} else {
2485			if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2486				mlx5_set_port_status(priv->mdev,
2487				    MLX5_PORT_DOWN);
2488				if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2489					mlx5e_close_locked(ifp);
2490				mlx5e_update_carrier(priv);
2491				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2492			}
2493		}
2494		PRIV_UNLOCK(priv);
2495		break;
2496	case SIOCADDMULTI:
2497	case SIOCDELMULTI:
2498		mlx5e_set_rx_mode(ifp);
2499		break;
2500	case SIOCSIFMEDIA:
2501	case SIOCGIFMEDIA:
2502	case SIOCGIFXMEDIA:
2503		ifr = (struct ifreq *)data;
2504		error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2505		break;
2506	case SIOCSIFCAP:
2507		ifr = (struct ifreq *)data;
2508		PRIV_LOCK(priv);
2509		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2510
2511		if (mask & IFCAP_TXCSUM) {
2512			ifp->if_capenable ^= IFCAP_TXCSUM;
2513			ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2514
2515			if (IFCAP_TSO4 & ifp->if_capenable &&
2516			    !(IFCAP_TXCSUM & ifp->if_capenable)) {
2517				ifp->if_capenable &= ~IFCAP_TSO4;
2518				ifp->if_hwassist &= ~CSUM_IP_TSO;
2519				if_printf(ifp,
2520				    "tso4 disabled due to -txcsum.\n");
2521			}
2522		}
2523		if (mask & IFCAP_TXCSUM_IPV6) {
2524			ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2525			ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2526
2527			if (IFCAP_TSO6 & ifp->if_capenable &&
2528			    !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2529				ifp->if_capenable &= ~IFCAP_TSO6;
2530				ifp->if_hwassist &= ~CSUM_IP6_TSO;
2531				if_printf(ifp,
2532				    "tso6 disabled due to -txcsum6.\n");
2533			}
2534		}
2535		if (mask & IFCAP_RXCSUM)
2536			ifp->if_capenable ^= IFCAP_RXCSUM;
2537		if (mask & IFCAP_RXCSUM_IPV6)
2538			ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2539		if (mask & IFCAP_TSO4) {
2540			if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2541			    !(IFCAP_TXCSUM & ifp->if_capenable)) {
2542				if_printf(ifp, "enable txcsum first.\n");
2543				error = EAGAIN;
2544				goto out;
2545			}
2546			ifp->if_capenable ^= IFCAP_TSO4;
2547			ifp->if_hwassist ^= CSUM_IP_TSO;
2548		}
2549		if (mask & IFCAP_TSO6) {
2550			if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2551			    !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2552				if_printf(ifp, "enable txcsum6 first.\n");
2553				error = EAGAIN;
2554				goto out;
2555			}
2556			ifp->if_capenable ^= IFCAP_TSO6;
2557			ifp->if_hwassist ^= CSUM_IP6_TSO;
2558		}
2559		if (mask & IFCAP_VLAN_HWFILTER) {
2560			if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2561				mlx5e_disable_vlan_filter(priv);
2562			else
2563				mlx5e_enable_vlan_filter(priv);
2564
2565			ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2566		}
2567		if (mask & IFCAP_VLAN_HWTAGGING)
2568			ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2569		if (mask & IFCAP_WOL_MAGIC)
2570			ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2571
2572		VLAN_CAPABILITIES(ifp);
2573		/* turn off LRO means also turn of HW LRO - if it's on */
2574		if (mask & IFCAP_LRO) {
2575			int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2576			bool need_restart = false;
2577
2578			ifp->if_capenable ^= IFCAP_LRO;
2579			if (!(ifp->if_capenable & IFCAP_LRO)) {
2580				if (priv->params.hw_lro_en) {
2581					priv->params.hw_lro_en = false;
2582					need_restart = true;
2583					/* Not sure this is the correct way */
2584					priv->params_ethtool.hw_lro = priv->params.hw_lro_en;
2585				}
2586			}
2587			if (was_opened && need_restart) {
2588				mlx5e_close_locked(ifp);
2589				mlx5e_open_locked(ifp);
2590			}
2591		}
2592out:
2593		PRIV_UNLOCK(priv);
2594		break;
2595
2596	case SIOCGI2C:
2597		ifr = (struct ifreq *)data;
2598
2599		/*
2600		 * Copy from the user-space address ifr_data to the
2601		 * kernel-space address i2c
2602		 */
2603		error = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
2604		if (error)
2605			break;
2606
2607		if (i2c.len > sizeof(i2c.data)) {
2608			error = EINVAL;
2609			break;
2610		}
2611
2612		PRIV_LOCK(priv);
2613		/* Get module_num which is required for the query_eeprom */
2614		error = mlx5_query_module_num(priv->mdev, &module_num);
2615		if (error) {
2616			if_printf(ifp, "Query module num failed, eeprom "
2617			    "reading is not supported\n");
2618			error = EINVAL;
2619			goto err_i2c;
2620		}
2621		/* Check if module is present before doing an access */
2622		if (mlx5_query_module_status(priv->mdev, module_num) !=
2623		    MLX5_MODULE_STATUS_PLUGGED) {
2624			error = EINVAL;
2625			goto err_i2c;
2626		}
2627		/*
2628		 * Currently 0XA0 and 0xA2 are the only addresses permitted.
2629		 * The internal conversion is as follows:
2630		 */
2631		if (i2c.dev_addr == 0xA0)
2632			read_addr = MLX5E_I2C_ADDR_LOW;
2633		else if (i2c.dev_addr == 0xA2)
2634			read_addr = MLX5E_I2C_ADDR_HIGH;
2635		else {
2636			if_printf(ifp, "Query eeprom failed, "
2637			    "Invalid Address: %X\n", i2c.dev_addr);
2638			error = EINVAL;
2639			goto err_i2c;
2640		}
2641		error = mlx5_query_eeprom(priv->mdev,
2642		    read_addr, MLX5E_EEPROM_LOW_PAGE,
2643		    (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
2644		    (uint32_t *)i2c.data, &size_read);
2645		if (error) {
2646			if_printf(ifp, "Query eeprom failed, eeprom "
2647			    "reading is not supported\n");
2648			error = EINVAL;
2649			goto err_i2c;
2650		}
2651
2652		if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
2653			error = mlx5_query_eeprom(priv->mdev,
2654			    read_addr, MLX5E_EEPROM_LOW_PAGE,
2655			    (uint32_t)(i2c.offset + size_read),
2656			    (uint32_t)(i2c.len - size_read), module_num,
2657			    (uint32_t *)(i2c.data + size_read), &size_read);
2658		}
2659		if (error) {
2660			if_printf(ifp, "Query eeprom failed, eeprom "
2661			    "reading is not supported\n");
2662			error = EINVAL;
2663			goto err_i2c;
2664		}
2665
2666		error = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
2667err_i2c:
2668		PRIV_UNLOCK(priv);
2669		break;
2670
2671	default:
2672		error = ether_ioctl(ifp, command, data);
2673		break;
2674	}
2675	return (error);
2676}
2677
2678static int
2679mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2680{
2681	/*
2682	 * TODO: uncoment once FW really sets all these bits if
2683	 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
2684	 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
2685	 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
2686	 * -ENOTSUPP;
2687	 */
2688
2689	/* TODO: add more must-to-have features */
2690
2691	return (0);
2692}
2693
2694static void
2695mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
2696    struct mlx5e_priv *priv,
2697    int num_comp_vectors)
2698{
2699	/*
2700	 * TODO: Consider link speed for setting "log_sq_size",
2701	 * "log_rq_size" and "cq_moderation_xxx":
2702	 */
2703	priv->params.log_sq_size =
2704	    MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2705	priv->params.log_rq_size =
2706	    MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2707	priv->params.rx_cq_moderation_usec =
2708	    MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
2709	    MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
2710	    MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2711	priv->params.rx_cq_moderation_mode =
2712	    MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
2713	priv->params.rx_cq_moderation_pkts =
2714	    MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2715	priv->params.tx_cq_moderation_usec =
2716	    MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2717	priv->params.tx_cq_moderation_pkts =
2718	    MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2719	priv->params.min_rx_wqes =
2720	    MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
2721	priv->params.rx_hash_log_tbl_sz =
2722	    (order_base_2(num_comp_vectors) >
2723	    MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
2724	    order_base_2(num_comp_vectors) :
2725	    MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
2726	priv->params.num_tc = 1;
2727	priv->params.default_vlan_prio = 0;
2728	priv->counter_set_id = -1;
2729
2730	/*
2731	 * hw lro is currently defaulted to off. when it won't anymore we
2732	 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
2733	 */
2734	priv->params.hw_lro_en = false;
2735	priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2736
2737	priv->params.cqe_zipping_en = !!MLX5_CAP_GEN(mdev, cqe_compression);
2738
2739	priv->mdev = mdev;
2740	priv->params.num_channels = num_comp_vectors;
2741	priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
2742	priv->queue_mapping_channel_mask =
2743	    roundup_pow_of_two(num_comp_vectors) - 1;
2744	priv->num_tc = priv->params.num_tc;
2745	priv->default_vlan_prio = priv->params.default_vlan_prio;
2746
2747	INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2748	INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2749	INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2750}
2751
2752static int
2753mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2754    struct mlx5_core_mr *mr)
2755{
2756	struct ifnet *ifp = priv->ifp;
2757	struct mlx5_core_dev *mdev = priv->mdev;
2758	struct mlx5_create_mkey_mbox_in *in;
2759	int err;
2760
2761	in = mlx5_vzalloc(sizeof(*in));
2762	if (in == NULL) {
2763		if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
2764		return (-ENOMEM);
2765	}
2766	in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2767	    MLX5_PERM_LOCAL_READ |
2768	    MLX5_ACCESS_MODE_PA;
2769	in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2770	in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2771
2772	err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
2773	    NULL);
2774	if (err)
2775		if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
2776		    __func__, err);
2777
2778	kvfree(in);
2779
2780	return (err);
2781}
2782
2783static const char *mlx5e_vport_stats_desc[] = {
2784	MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
2785};
2786
2787static const char *mlx5e_pport_stats_desc[] = {
2788	MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
2789};
2790
2791static void
2792mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
2793{
2794	mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
2795	sx_init(&priv->state_lock, "mlx5state");
2796	callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
2797}
2798
2799static void
2800mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
2801{
2802	mtx_destroy(&priv->async_events_mtx);
2803	sx_destroy(&priv->state_lock);
2804}
2805
2806static int
2807sysctl_firmware(SYSCTL_HANDLER_ARGS)
2808{
2809	/*
2810	 * %d.%d%.d the string format.
2811	 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
2812	 * We need at most 5 chars to store that.
2813	 * It also has: two "." and NULL at the end, which means we need 18
2814	 * (5*3 + 3) chars at most.
2815	 */
2816	char fw[18];
2817	struct mlx5e_priv *priv = arg1;
2818	int error;
2819
2820	snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
2821	    fw_rev_sub(priv->mdev));
2822	error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
2823	return (error);
2824}
2825
2826static void
2827mlx5e_add_hw_stats(struct mlx5e_priv *priv)
2828{
2829	SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
2830	    OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
2831	    sysctl_firmware, "A", "HCA firmware version");
2832
2833	SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
2834	    OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
2835	    "Board ID");
2836}
2837
2838static void
2839mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
2840{
2841#if (__FreeBSD_version < 1100000)
2842	char path[64];
2843
2844#endif
2845	/* Only receiving pauseframes is enabled by default */
2846	priv->params.tx_pauseframe_control = 0;
2847	priv->params.rx_pauseframe_control = 1;
2848
2849#if (__FreeBSD_version < 1100000)
2850	/* compute path for sysctl */
2851	snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
2852	    device_get_unit(priv->mdev->pdev->dev.bsddev));
2853
2854	/* try to fetch tunable, if any */
2855	TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
2856
2857	/* compute path for sysctl */
2858	snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
2859	    device_get_unit(priv->mdev->pdev->dev.bsddev));
2860
2861	/* try to fetch tunable, if any */
2862	TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
2863#endif
2864
2865	/* register pausframe SYSCTLs */
2866	SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2867	    OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
2868	    &priv->params.tx_pauseframe_control, 0,
2869	    "Set to enable TX pause frames. Clear to disable.");
2870
2871	SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2872	    OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
2873	    &priv->params.rx_pauseframe_control, 0,
2874	    "Set to enable RX pause frames. Clear to disable.");
2875
2876	/* range check */
2877	priv->params.tx_pauseframe_control =
2878	    priv->params.tx_pauseframe_control ? 1 : 0;
2879	priv->params.rx_pauseframe_control =
2880	    priv->params.rx_pauseframe_control ? 1 : 0;
2881
2882	/* update firmware */
2883	mlx5_set_port_pause(priv->mdev, 1,
2884	    priv->params.rx_pauseframe_control,
2885	    priv->params.tx_pauseframe_control);
2886}
2887
2888static void *
2889mlx5e_create_ifp(struct mlx5_core_dev *mdev)
2890{
2891	static volatile int mlx5_en_unit;
2892	struct ifnet *ifp;
2893	struct mlx5e_priv *priv;
2894	u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
2895	struct sysctl_oid_list *child;
2896	int ncv = mdev->priv.eq_table.num_comp_vectors;
2897	char unit[16];
2898	int err;
2899	int i;
2900	u32 eth_proto_cap;
2901
2902	if (mlx5e_check_required_hca_cap(mdev)) {
2903		mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
2904		return (NULL);
2905	}
2906	priv = malloc(sizeof(*priv), M_MLX5EN, M_WAITOK | M_ZERO);
2907	if (priv == NULL) {
2908		mlx5_core_err(mdev, "malloc() failed\n");
2909		return (NULL);
2910	}
2911	mlx5e_priv_mtx_init(priv);
2912
2913	ifp = priv->ifp = if_alloc(IFT_ETHER);
2914	if (ifp == NULL) {
2915		mlx5_core_err(mdev, "if_alloc() failed\n");
2916		goto err_free_priv;
2917	}
2918	ifp->if_softc = priv;
2919	if_initname(ifp, "mce", atomic_fetchadd_int(&mlx5_en_unit, 1));
2920	ifp->if_mtu = ETHERMTU;
2921	ifp->if_init = mlx5e_open;
2922	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2923	ifp->if_ioctl = mlx5e_ioctl;
2924	ifp->if_transmit = mlx5e_xmit;
2925	ifp->if_qflush = if_qflush;
2926#if (__FreeBSD_version >= 1100000)
2927	ifp->if_get_counter = mlx5e_get_counter;
2928#endif
2929	ifp->if_snd.ifq_maxlen = ifqmaxlen;
2930	/*
2931         * Set driver features
2932         */
2933	ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
2934	ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
2935	ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
2936	ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
2937	ifp->if_capabilities |= IFCAP_LRO;
2938	ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
2939
2940	/* set TSO limits so that we don't have to drop TX packets */
2941	ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
2942	ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
2943	ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
2944
2945	ifp->if_capenable = ifp->if_capabilities;
2946	ifp->if_hwassist = 0;
2947	if (ifp->if_capenable & IFCAP_TSO)
2948		ifp->if_hwassist |= CSUM_TSO;
2949	if (ifp->if_capenable & IFCAP_TXCSUM)
2950		ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2951	if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
2952		ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2953
2954	/* ifnet sysctl tree */
2955	sysctl_ctx_init(&priv->sysctl_ctx);
2956	priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
2957	    OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
2958	if (priv->sysctl_ifnet == NULL) {
2959		mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2960		goto err_free_sysctl;
2961	}
2962	snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
2963	priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2964	    OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
2965	if (priv->sysctl_ifnet == NULL) {
2966		mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2967		goto err_free_sysctl;
2968	}
2969
2970	/* HW sysctl tree */
2971	child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
2972	priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
2973	    OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
2974	if (priv->sysctl_hw == NULL) {
2975		mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2976		goto err_free_sysctl;
2977	}
2978	mlx5e_build_ifp_priv(mdev, priv, ncv);
2979	err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
2980	if (err) {
2981		if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
2982		    __func__, err);
2983		goto err_free_sysctl;
2984	}
2985	err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2986	if (err) {
2987		if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
2988		    __func__, err);
2989		goto err_unmap_free_uar;
2990	}
2991	err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
2992	if (err) {
2993		if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
2994		    __func__, err);
2995		goto err_dealloc_pd;
2996	}
2997	err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
2998	if (err) {
2999		if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
3000		    __func__, err);
3001		goto err_dealloc_transport_domain;
3002	}
3003	mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
3004
3005	/* check if we should generate a random MAC address */
3006	if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
3007	    is_zero_ether_addr(dev_addr)) {
3008		random_ether_addr(dev_addr);
3009		if_printf(ifp, "Assigned random MAC address\n");
3010	}
3011
3012	/* set default MTU */
3013	mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
3014
3015	/* Set desc */
3016	device_set_desc(mdev->pdev->dev.bsddev, mlx5e_version);
3017
3018	/* Set default media status */
3019	priv->media_status_last = IFM_AVALID;
3020	priv->media_active_last = IFM_ETHER | IFM_AUTO |
3021	    IFM_ETH_RXPAUSE | IFM_FDX;
3022
3023	/* setup default pauseframes configuration */
3024	mlx5e_setup_pauseframes(priv);
3025
3026	err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
3027	if (err) {
3028		eth_proto_cap = 0;
3029		if_printf(ifp, "%s: Query port media capability failed, %d\n",
3030		    __func__, err);
3031	}
3032
3033	/* Setup supported medias */
3034	ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3035	    mlx5e_media_change, mlx5e_media_status);
3036
3037	for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3038		if (mlx5e_mode_table[i].baudrate == 0)
3039			continue;
3040		if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3041			ifmedia_add(&priv->media,
3042			    mlx5e_mode_table[i].subtype |
3043			    IFM_ETHER, 0, NULL);
3044			ifmedia_add(&priv->media,
3045			    mlx5e_mode_table[i].subtype |
3046			    IFM_ETHER | IFM_FDX |
3047			    IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3048		}
3049	}
3050
3051	ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3052	ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3053	    IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3054
3055	/* Set autoselect by default */
3056	ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3057	    IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3058	ether_ifattach(ifp, dev_addr);
3059
3060	/* Register for VLAN events */
3061	priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3062	    mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3063	priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3064	    mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3065
3066	/* Link is down by default */
3067	if_link_state_change(ifp, LINK_STATE_DOWN);
3068
3069	mlx5e_enable_async_events(priv);
3070
3071	mlx5e_add_hw_stats(priv);
3072
3073	mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3074	    "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3075	    priv->stats.vport.arg);
3076
3077	mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3078	    "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3079	    priv->stats.pport.arg);
3080
3081	mlx5e_create_ethtool(priv);
3082
3083	mtx_lock(&priv->async_events_mtx);
3084	mlx5e_update_stats(priv);
3085	mtx_unlock(&priv->async_events_mtx);
3086
3087	return (priv);
3088
3089err_dealloc_transport_domain:
3090	mlx5_dealloc_transport_domain(mdev, priv->tdn);
3091
3092err_dealloc_pd:
3093	mlx5_core_dealloc_pd(mdev, priv->pdn);
3094
3095err_unmap_free_uar:
3096	mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3097
3098err_free_sysctl:
3099	sysctl_ctx_free(&priv->sysctl_ctx);
3100
3101	if_free(ifp);
3102
3103err_free_priv:
3104	mlx5e_priv_mtx_destroy(priv);
3105	free(priv, M_MLX5EN);
3106	return (NULL);
3107}
3108
3109static void
3110mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
3111{
3112	struct mlx5e_priv *priv = vpriv;
3113	struct ifnet *ifp = priv->ifp;
3114
3115	/* don't allow more IOCTLs */
3116	priv->gone = 1;
3117
3118	/*
3119	 * Clear the device description to avoid use after free,
3120	 * because the bsddev is not destroyed when this module is
3121	 * unloaded:
3122	 */
3123	device_set_desc(mdev->pdev->dev.bsddev, NULL);
3124
3125	/* XXX wait a bit to allow IOCTL handlers to complete */
3126	pause("W", hz);
3127
3128	/* stop watchdog timer */
3129	callout_drain(&priv->watchdog);
3130
3131	if (priv->vlan_attach != NULL)
3132		EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
3133	if (priv->vlan_detach != NULL)
3134		EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
3135
3136	/* make sure device gets closed */
3137	PRIV_LOCK(priv);
3138	mlx5e_close_locked(ifp);
3139	PRIV_UNLOCK(priv);
3140
3141	/* unregister device */
3142	ifmedia_removeall(&priv->media);
3143	ether_ifdetach(ifp);
3144	if_free(ifp);
3145
3146	/* destroy all remaining sysctl nodes */
3147	if (priv->sysctl_debug)
3148		sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
3149	sysctl_ctx_free(&priv->stats.vport.ctx);
3150	sysctl_ctx_free(&priv->stats.pport.ctx);
3151	sysctl_ctx_free(&priv->sysctl_ctx);
3152
3153	mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3154	mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
3155	mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3156	mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3157	mlx5e_disable_async_events(priv);
3158	flush_scheduled_work();
3159	mlx5e_priv_mtx_destroy(priv);
3160	free(priv, M_MLX5EN);
3161}
3162
3163static void *
3164mlx5e_get_ifp(void *vpriv)
3165{
3166	struct mlx5e_priv *priv = vpriv;
3167
3168	return (priv->ifp);
3169}
3170
3171static struct mlx5_interface mlx5e_interface = {
3172	.add = mlx5e_create_ifp,
3173	.remove = mlx5e_destroy_ifp,
3174	.event = mlx5e_async_event,
3175	.protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3176	.get_dev = mlx5e_get_ifp,
3177};
3178
3179void
3180mlx5e_init(void)
3181{
3182	mlx5_register_interface(&mlx5e_interface);
3183}
3184
3185void
3186mlx5e_cleanup(void)
3187{
3188	mlx5_unregister_interface(&mlx5e_interface);
3189}
3190
3191module_init_order(mlx5e_init, SI_ORDER_THIRD);
3192module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
3193
3194#if (__FreeBSD_version >= 1100000)
3195MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
3196#endif
3197MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
3198MODULE_VERSION(mlx5en, 1);
3199