en.h revision 353252
1/*- 2 * Copyright (c) 2015-2019 Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_en/en.h 353252 2019-10-07 10:16:50Z hselasky $ 26 */ 27 28#ifndef _MLX5_EN_H_ 29#define _MLX5_EN_H_ 30 31#include <linux/kmod.h> 32#include <linux/page.h> 33#include <linux/slab.h> 34#include <linux/if_vlan.h> 35#include <linux/if_ether.h> 36#include <linux/vmalloc.h> 37#include <linux/moduleparam.h> 38#include <linux/delay.h> 39#include <linux/netdevice.h> 40#include <linux/etherdevice.h> 41#include <linux/ktime.h> 42#include <linux/net_dim.h> 43 44#include <netinet/in_systm.h> 45#include <netinet/in.h> 46#include <netinet/if_ether.h> 47#include <netinet/ip.h> 48#include <netinet/ip6.h> 49#include <netinet/tcp.h> 50#include <netinet/tcp_lro.h> 51#include <netinet/udp.h> 52#include <net/ethernet.h> 53#include <sys/buf_ring.h> 54 55#include "opt_rss.h" 56 57#ifdef RSS 58#include <net/rss_config.h> 59#include <netinet/in_rss.h> 60#endif 61 62#include <machine/bus.h> 63 64#include <dev/mlx5/driver.h> 65#include <dev/mlx5/qp.h> 66#include <dev/mlx5/cq.h> 67#include <dev/mlx5/port.h> 68#include <dev/mlx5/vport.h> 69#include <dev/mlx5/diagnostics.h> 70 71#include <dev/mlx5/mlx5_core/wq.h> 72#include <dev/mlx5/mlx5_core/transobj.h> 73#include <dev/mlx5/mlx5_core/mlx5_core.h> 74 75#define MLX5E_MAX_PRIORITY 8 76 77#define MLX5E_MAX_FEC_10X_25X 4 78#define MLX5E_MAX_FEC_50X 4 79 80/* IEEE 802.1Qaz standard supported values */ 81#define IEEE_8021QAZ_MAX_TCS 8 82 83#define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x7 84#define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa 85#define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xe 86 87#define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x7 88#define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa 89#define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xe 90 91#define MLX5E_MAX_BUSDMA_RX_SEGS 15 92 93#ifndef MLX5E_MAX_RX_BYTES 94#define MLX5E_MAX_RX_BYTES MCLBYTES 95#endif 96 97#define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ \ 98 MIN(65535, 7 * MLX5E_MAX_RX_BYTES) 99 100#define MLX5E_DIM_DEFAULT_PROFILE 3 101#define MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO 16 102#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 103#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 104#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 105#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 106#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 107#define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 108#define MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ 0x7 109#define MLX5E_CACHELINE_SIZE CACHE_LINE_SIZE 110#define MLX5E_HW2SW_MTU(hwmtu) \ 111 ((hwmtu) - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 112#define MLX5E_SW2HW_MTU(swmtu) \ 113 ((swmtu) + (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 114#define MLX5E_SW2MB_MTU(swmtu) \ 115 (MLX5E_SW2HW_MTU(swmtu) + MLX5E_NET_IP_ALIGN) 116#define MLX5E_MTU_MIN 72 /* Min MTU allowed by the kernel */ 117#define MLX5E_MTU_MAX MIN(ETHERMTU_JUMBO, MJUM16BYTES) /* Max MTU of Ethernet 118 * jumbo frames */ 119 120#define MLX5E_BUDGET_MAX 8192 /* RX and TX */ 121#define MLX5E_RX_BUDGET_MAX 256 122#define MLX5E_SQ_BF_BUDGET 16 123#define MLX5E_SQ_TX_QUEUE_SIZE 4096 /* SQ drbr queue size */ 124 125#define MLX5E_MAX_TX_NUM_TC 8 /* units */ 126#define MLX5E_MAX_TX_HEADER 128 /* bytes */ 127#define MLX5E_MAX_TX_PAYLOAD_SIZE 65536 /* bytes */ 128#define MLX5E_MAX_TX_MBUF_SIZE 65536 /* bytes */ 129#define MLX5E_MAX_TX_MBUF_FRAGS \ 130 ((MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS) - \ 131 (MLX5E_MAX_TX_HEADER / MLX5_SEND_WQE_DS) - \ 132 1 /* the maximum value of the DS counter is 0x3F and not 0x40 */) /* units */ 133#define MLX5E_MAX_TX_INLINE \ 134 (MLX5E_MAX_TX_HEADER - sizeof(struct mlx5e_tx_wqe) + \ 135 sizeof(((struct mlx5e_tx_wqe *)0)->eth.inline_hdr_start)) /* bytes */ 136 137#define MLX5E_100MB (100000) 138#define MLX5E_1GB (1000000) 139 140#define MLX5E_ZERO(ptr, field) \ 141 memset(&(ptr)->field, 0, \ 142 sizeof(*(ptr)) - __offsetof(__typeof(*(ptr)), field)) 143 144MALLOC_DECLARE(M_MLX5EN); 145 146struct mlx5_core_dev; 147struct mlx5e_cq; 148 149typedef void (mlx5e_cq_comp_t)(struct mlx5_core_cq *); 150 151#define mlx5_en_err(_dev, format, ...) \ 152 if_printf(_dev, "ERR: ""%s:%d:(pid %d): " format, \ 153 __func__, __LINE__, curthread->td_proc->p_pid, \ 154 ##__VA_ARGS__) 155 156#define mlx5_en_warn(_dev, format, ...) \ 157 if_printf(_dev, "WARN: ""%s:%d:(pid %d): " format, \ 158 __func__, __LINE__, curthread->td_proc->p_pid, \ 159 ##__VA_ARGS__) 160 161#define mlx5_en_info(_dev, format, ...) \ 162 if_printf(_dev, "INFO: ""%s:%d:(pid %d): " format, \ 163 __func__, __LINE__, curthread->td_proc->p_pid, \ 164 ##__VA_ARGS__) 165 166#define MLX5E_STATS_COUNT(a, ...) a 167#define MLX5E_STATS_VAR(a, b, c, ...) b c; 168#define MLX5E_STATS_DESC(a, b, c, d, e, ...) d, e, 169 170#define MLX5E_VPORT_STATS(m) \ 171 /* HW counters */ \ 172 m(+1, u64, rx_packets, "rx_packets", "Received packets") \ 173 m(+1, u64, rx_bytes, "rx_bytes", "Received bytes") \ 174 m(+1, u64, tx_packets, "tx_packets", "Transmitted packets") \ 175 m(+1, u64, tx_bytes, "tx_bytes", "Transmitted bytes") \ 176 m(+1, u64, rx_error_packets, "rx_error_packets", "Received error packets") \ 177 m(+1, u64, rx_error_bytes, "rx_error_bytes", "Received error bytes") \ 178 m(+1, u64, tx_error_packets, "tx_error_packets", "Transmitted error packets") \ 179 m(+1, u64, tx_error_bytes, "tx_error_bytes", "Transmitted error bytes") \ 180 m(+1, u64, rx_unicast_packets, "rx_unicast_packets", "Received unicast packets") \ 181 m(+1, u64, rx_unicast_bytes, "rx_unicast_bytes", "Received unicast bytes") \ 182 m(+1, u64, tx_unicast_packets, "tx_unicast_packets", "Transmitted unicast packets") \ 183 m(+1, u64, tx_unicast_bytes, "tx_unicast_bytes", "Transmitted unicast bytes") \ 184 m(+1, u64, rx_multicast_packets, "rx_multicast_packets", "Received multicast packets") \ 185 m(+1, u64, rx_multicast_bytes, "rx_multicast_bytes", "Received multicast bytes") \ 186 m(+1, u64, tx_multicast_packets, "tx_multicast_packets", "Transmitted multicast packets") \ 187 m(+1, u64, tx_multicast_bytes, "tx_multicast_bytes", "Transmitted multicast bytes") \ 188 m(+1, u64, rx_broadcast_packets, "rx_broadcast_packets", "Received broadcast packets") \ 189 m(+1, u64, rx_broadcast_bytes, "rx_broadcast_bytes", "Received broadcast bytes") \ 190 m(+1, u64, tx_broadcast_packets, "tx_broadcast_packets", "Transmitted broadcast packets") \ 191 m(+1, u64, tx_broadcast_bytes, "tx_broadcast_bytes", "Transmitted broadcast bytes") \ 192 m(+1, u64, rx_out_of_buffer, "rx_out_of_buffer", "Receive out of buffer, no recv wqes events") \ 193 /* SW counters */ \ 194 m(+1, u64, tso_packets, "tso_packets", "Transmitted TSO packets") \ 195 m(+1, u64, tso_bytes, "tso_bytes", "Transmitted TSO bytes") \ 196 m(+1, u64, lro_packets, "lro_packets", "Received LRO packets") \ 197 m(+1, u64, lro_bytes, "lro_bytes", "Received LRO bytes") \ 198 m(+1, u64, sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 199 m(+1, u64, sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 200 m(+1, u64, rx_csum_good, "rx_csum_good", "Received checksum valid packets") \ 201 m(+1, u64, rx_csum_none, "rx_csum_none", "Received no checksum packets") \ 202 m(+1, u64, tx_csum_offload, "tx_csum_offload", "Transmit checksum offload packets") \ 203 m(+1, u64, tx_queue_dropped, "tx_queue_dropped", "Transmit queue dropped") \ 204 m(+1, u64, tx_defragged, "tx_defragged", "Transmit queue defragged") \ 205 m(+1, u64, rx_wqe_err, "rx_wqe_err", "Receive WQE errors") \ 206 m(+1, u64, tx_jumbo_packets, "tx_jumbo_packets", "TX packets greater than 1518 octets") \ 207 m(+1, u64, rx_steer_missed_packets, "rx_steer_missed_packets", "RX packets dropped by steering rule(s)") 208 209#define MLX5E_VPORT_STATS_NUM (0 MLX5E_VPORT_STATS(MLX5E_STATS_COUNT)) 210 211struct mlx5e_vport_stats { 212 struct sysctl_ctx_list ctx; 213 u64 arg [0]; 214 MLX5E_VPORT_STATS(MLX5E_STATS_VAR) 215}; 216 217#define MLX5E_PPORT_IEEE802_3_STATS(m) \ 218 m(+1, u64, frames_tx, "frames_tx", "Frames transmitted") \ 219 m(+1, u64, frames_rx, "frames_rx", "Frames received") \ 220 m(+1, u64, check_seq_err, "check_seq_err", "Sequence errors") \ 221 m(+1, u64, alignment_err, "alignment_err", "Alignment errors") \ 222 m(+1, u64, octets_tx, "octets_tx", "Bytes transmitted") \ 223 m(+1, u64, octets_received, "octets_received", "Bytes received") \ 224 m(+1, u64, multicast_xmitted, "multicast_xmitted", "Multicast transmitted") \ 225 m(+1, u64, broadcast_xmitted, "broadcast_xmitted", "Broadcast transmitted") \ 226 m(+1, u64, multicast_rx, "multicast_rx", "Multicast received") \ 227 m(+1, u64, broadcast_rx, "broadcast_rx", "Broadcast received") \ 228 m(+1, u64, in_range_len_errors, "in_range_len_errors", "In range length errors") \ 229 m(+1, u64, out_of_range_len, "out_of_range_len", "Out of range length errors") \ 230 m(+1, u64, too_long_errors, "too_long_errors", "Too long errors") \ 231 m(+1, u64, symbol_err, "symbol_err", "Symbol errors") \ 232 m(+1, u64, mac_control_tx, "mac_control_tx", "MAC control transmitted") \ 233 m(+1, u64, mac_control_rx, "mac_control_rx", "MAC control received") \ 234 m(+1, u64, unsupported_op_rx, "unsupported_op_rx", "Unsupported operation received") \ 235 m(+1, u64, pause_ctrl_rx, "pause_ctrl_rx", "Pause control received") \ 236 m(+1, u64, pause_ctrl_tx, "pause_ctrl_tx", "Pause control transmitted") 237 238#define MLX5E_PPORT_RFC2819_STATS(m) \ 239 m(+1, u64, drop_events, "drop_events", "Dropped events") \ 240 m(+1, u64, octets, "octets", "Octets") \ 241 m(+1, u64, pkts, "pkts", "Packets") \ 242 m(+1, u64, broadcast_pkts, "broadcast_pkts", "Broadcast packets") \ 243 m(+1, u64, multicast_pkts, "multicast_pkts", "Multicast packets") \ 244 m(+1, u64, crc_align_errors, "crc_align_errors", "CRC alignment errors") \ 245 m(+1, u64, undersize_pkts, "undersize_pkts", "Undersized packets") \ 246 m(+1, u64, oversize_pkts, "oversize_pkts", "Oversized packets") \ 247 m(+1, u64, fragments, "fragments", "Fragments") \ 248 m(+1, u64, jabbers, "jabbers", "Jabbers") \ 249 m(+1, u64, collisions, "collisions", "Collisions") 250 251#define MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 252 m(+1, u64, p64octets, "p64octets", "Bytes") \ 253 m(+1, u64, p65to127octets, "p65to127octets", "Bytes") \ 254 m(+1, u64, p128to255octets, "p128to255octets", "Bytes") \ 255 m(+1, u64, p256to511octets, "p256to511octets", "Bytes") \ 256 m(+1, u64, p512to1023octets, "p512to1023octets", "Bytes") \ 257 m(+1, u64, p1024to1518octets, "p1024to1518octets", "Bytes") \ 258 m(+1, u64, p1519to2047octets, "p1519to2047octets", "Bytes") \ 259 m(+1, u64, p2048to4095octets, "p2048to4095octets", "Bytes") \ 260 m(+1, u64, p4096to8191octets, "p4096to8191octets", "Bytes") \ 261 m(+1, u64, p8192to10239octets, "p8192to10239octets", "Bytes") 262 263#define MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 264 m(+1, u64, in_octets, "in_octets", "In octets") \ 265 m(+1, u64, in_ucast_pkts, "in_ucast_pkts", "In unicast packets") \ 266 m(+1, u64, in_discards, "in_discards", "In discards") \ 267 m(+1, u64, in_errors, "in_errors", "In errors") \ 268 m(+1, u64, in_unknown_protos, "in_unknown_protos", "In unknown protocols") \ 269 m(+1, u64, out_octets, "out_octets", "Out octets") \ 270 m(+1, u64, out_ucast_pkts, "out_ucast_pkts", "Out unicast packets") \ 271 m(+1, u64, out_discards, "out_discards", "Out discards") \ 272 m(+1, u64, out_errors, "out_errors", "Out errors") \ 273 m(+1, u64, in_multicast_pkts, "in_multicast_pkts", "In multicast packets") \ 274 m(+1, u64, in_broadcast_pkts, "in_broadcast_pkts", "In broadcast packets") \ 275 m(+1, u64, out_multicast_pkts, "out_multicast_pkts", "Out multicast packets") \ 276 m(+1, u64, out_broadcast_pkts, "out_broadcast_pkts", "Out broadcast packets") 277 278#define MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(m) \ 279 m(+1, u64, port_transmit_wait, "port_transmit_wait", "Port transmit wait") \ 280 m(+1, u64, ecn_marked, "ecn_marked", "ECN marked") \ 281 m(+1, u64, no_buffer_discard_mc, "no_buffer_discard_mc", "No buffer discard mc") \ 282 m(+1, u64, rx_ebp, "rx_ebp", "RX EBP") \ 283 m(+1, u64, tx_ebp, "tx_ebp", "TX EBP") \ 284 m(+1, u64, rx_buffer_almost_full, "rx_buffer_almost_full", "RX buffer almost full") \ 285 m(+1, u64, rx_buffer_full, "rx_buffer_full", "RX buffer full") \ 286 m(+1, u64, rx_icrc_encapsulated, "rx_icrc_encapsulated", "RX ICRC encapsulated") \ 287 m(+1, u64, ex_reserved_0, "ex_reserved_0", "Reserved") \ 288 m(+1, u64, ex_reserved_1, "ex_reserved_1", "Reserved") \ 289 m(+1, u64, tx_stat_p64octets, "tx_stat_p64octets", "Bytes") \ 290 m(+1, u64, tx_stat_p65to127octets, "tx_stat_p65to127octets", "Bytes") \ 291 m(+1, u64, tx_stat_p128to255octets, "tx_stat_p128to255octets", "Bytes") \ 292 m(+1, u64, tx_stat_p256to511octets, "tx_stat_p256to511octets", "Bytes") \ 293 m(+1, u64, tx_stat_p512to1023octets, "tx_stat_p512to1023octets", "Bytes") \ 294 m(+1, u64, tx_stat_p1024to1518octets, "tx_stat_p1024to1518octets", "Bytes") \ 295 m(+1, u64, tx_stat_p1519to2047octets, "tx_stat_p1519to2047octets", "Bytes") \ 296 m(+1, u64, tx_stat_p2048to4095octets, "tx_stat_p2048to4095octets", "Bytes") \ 297 m(+1, u64, tx_stat_p4096to8191octets, "tx_stat_p4096to8191octets", "Bytes") \ 298 m(+1, u64, tx_stat_p8192to10239octets, "tx_stat_p8192to10239octets", "Bytes") 299 300#define MLX5E_PPORT_STATISTICAL_DEBUG(m) \ 301 m(+1, u64, phy_time_since_last_clear, "phy_time_since_last_clear", \ 302 "Time since last clear in milliseconds") \ 303 m(+1, u64, phy_received_bits, "phy_received_bits", \ 304 "Total amount of traffic received in bits before error correction") \ 305 m(+1, u64, phy_symbol_errors, "phy_symbol_errors", \ 306 "Total number of symbol errors before error correction") \ 307 m(+1, u64, phy_corrected_bits, "phy_corrected_bits", \ 308 "Total number of corrected bits ") \ 309 m(+1, u64, phy_corrected_bits_lane0, "phy_corrected_bits_lane0", \ 310 "Total number of corrected bits for lane 0") \ 311 m(+1, u64, phy_corrected_bits_lane1, "phy_corrected_bits_lane1", \ 312 "Total number of corrected bits for lane 1") \ 313 m(+1, u64, phy_corrected_bits_lane2, "phy_corrected_bits_lane2", \ 314 "Total number of corrected bits for lane 2") \ 315 m(+1, u64, phy_corrected_bits_lane3, "phy_corrected_bits_lane3", \ 316 "Total number of corrected bits for lane 3") 317 318#define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \ 319 m(+1, u64, time_since_last_clear, "time_since_last_clear", \ 320 "Time since the last counters clear event (msec)") \ 321 m(+1, u64, symbol_errors, "symbol_errors", "Symbol errors") \ 322 m(+1, u64, sync_headers_errors, "sync_headers_errors", \ 323 "Sync header error counter") \ 324 m(+1, u64, bip_errors_lane0, "edpl_bip_errors_lane0", \ 325 "Indicates the number of PRBS errors on lane 0") \ 326 m(+1, u64, bip_errors_lane1, "edpl_bip_errors_lane1", \ 327 "Indicates the number of PRBS errors on lane 1") \ 328 m(+1, u64, bip_errors_lane2, "edpl_bip_errors_lane2", \ 329 "Indicates the number of PRBS errors on lane 2") \ 330 m(+1, u64, bip_errors_lane3, "edpl_bip_errors_lane3", \ 331 "Indicates the number of PRBS errors on lane 3") \ 332 m(+1, u64, fc_corrected_blocks_lane0, "fc_corrected_blocks_lane0", \ 333 "FEC correctable block counter lane 0") \ 334 m(+1, u64, fc_corrected_blocks_lane1, "fc_corrected_blocks_lane1", \ 335 "FEC correctable block counter lane 1") \ 336 m(+1, u64, fc_corrected_blocks_lane2, "fc_corrected_blocks_lane2", \ 337 "FEC correctable block counter lane 2") \ 338 m(+1, u64, fc_corrected_blocks_lane3, "fc_corrected_blocks_lane3", \ 339 "FEC correctable block counter lane 3") \ 340 m(+1, u64, rs_corrected_blocks, "rs_corrected_blocks", \ 341 "FEC correcable block counter") \ 342 m(+1, u64, rs_uncorrectable_blocks, "rs_uncorrectable_blocks", \ 343 "FEC uncorrecable block counter") \ 344 m(+1, u64, rs_no_errors_blocks, "rs_no_errors_blocks", \ 345 "The number of RS-FEC blocks received that had no errors") \ 346 m(+1, u64, rs_single_error_blocks, "rs_single_error_blocks", \ 347 "The number of corrected RS-FEC blocks received that had" \ 348 "exactly 1 error symbol") \ 349 m(+1, u64, rs_corrected_symbols_total, "rs_corrected_symbols_total", \ 350 "Port FEC corrected symbol counter") \ 351 m(+1, u64, rs_corrected_symbols_lane0, "rs_corrected_symbols_lane0", \ 352 "FEC corrected symbol counter lane 0") \ 353 m(+1, u64, rs_corrected_symbols_lane1, "rs_corrected_symbols_lane1", \ 354 "FEC corrected symbol counter lane 1") \ 355 m(+1, u64, rs_corrected_symbols_lane2, "rs_corrected_symbols_lane2", \ 356 "FEC corrected symbol counter lane 2") \ 357 m(+1, u64, rs_corrected_symbols_lane3, "rs_corrected_symbols_lane3", \ 358 "FEC corrected symbol counter lane 3") 359 360/* Per priority statistics for PFC */ 361#define MLX5E_PPORT_PER_PRIO_STATS_SUB(m,n,p) \ 362 m(n, p, +1, u64, rx_octets, "rx_octets", "Received octets") \ 363 m(n, p, +1, u64, rx_uc_frames, "rx_uc_frames", "Received unicast frames") \ 364 m(n, p, +1, u64, rx_mc_frames, "rx_mc_frames", "Received multicast frames") \ 365 m(n, p, +1, u64, rx_bc_frames, "rx_bc_frames", "Received broadcast frames") \ 366 m(n, p, +1, u64, rx_frames, "rx_frames", "Received frames") \ 367 m(n, p, +1, u64, tx_octets, "tx_octets", "Transmitted octets") \ 368 m(n, p, +1, u64, tx_uc_frames, "tx_uc_frames", "Transmitted unicast frames") \ 369 m(n, p, +1, u64, tx_mc_frames, "tx_mc_frames", "Transmitted multicast frames") \ 370 m(n, p, +1, u64, tx_bc_frames, "tx_bc_frames", "Transmitted broadcast frames") \ 371 m(n, p, +1, u64, tx_frames, "tx_frames", "Transmitted frames") \ 372 m(n, p, +1, u64, rx_pause, "rx_pause", "Received pause frames") \ 373 m(n, p, +1, u64, rx_pause_duration, "rx_pause_duration", \ 374 "Received pause duration") \ 375 m(n, p, +1, u64, tx_pause, "tx_pause", "Transmitted pause frames") \ 376 m(n, p, +1, u64, tx_pause_duration, "tx_pause_duration", \ 377 "Transmitted pause duration") \ 378 m(n, p, +1, u64, rx_pause_transition, "rx_pause_transition", \ 379 "Received pause transitions") \ 380 m(n, p, +1, u64, rx_discards, "rx_discards", "Discarded received frames") \ 381 m(n, p, +1, u64, device_stall_minor_watermark, \ 382 "device_stall_minor_watermark", "Device stall minor watermark") \ 383 m(n, p, +1, u64, device_stall_critical_watermark, \ 384 "device_stall_critical_watermark", "Device stall critical watermark") 385 386#define MLX5E_PPORT_PER_PRIO_STATS_PREFIX(m,p,c,t,f,s,d) \ 387 m(c, t, pri_##p##_##f, "prio" #p "_" s, "Priority " #p " - " d) 388 389#define MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO 8 390 391#define MLX5E_PPORT_PER_PRIO_STATS(m) \ 392 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,0) \ 393 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,1) \ 394 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,2) \ 395 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,3) \ 396 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,4) \ 397 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,5) \ 398 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,6) \ 399 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,7) 400 401#define MLX5E_PCIE_PERFORMANCE_COUNTERS_64(m) \ 402 m(+1, u64, life_time_counter_high, "life_time_counter", \ 403 "Life time counter.", pcie_perf_counters) \ 404 m(+1, u64, tx_overflow_buffer_pkt, "tx_overflow_buffer_pkt", \ 405 "The number of packets dropped due to lack of PCIe buffers " \ 406 "in receive path from NIC port toward the hosts.", \ 407 pcie_perf_counters) \ 408 m(+1, u64, tx_overflow_buffer_marked_pkt, \ 409 "tx_overflow_buffer_marked_pkt", \ 410 "The number of packets marked due to lack of PCIe buffers " \ 411 "in receive path from NIC port toward the hosts.", \ 412 pcie_perf_counters) 413 414#define MLX5E_PCIE_PERFORMANCE_COUNTERS_32(m) \ 415 m(+1, u64, rx_errors, "rx_errors", \ 416 "Number of transitions to recovery due to Framing " \ 417 "errors and CRC errors.", pcie_perf_counters) \ 418 m(+1, u64, tx_errors, "tx_errors", "Number of transitions " \ 419 "to recovery due to EIEOS and TS errors.", pcie_perf_counters) \ 420 m(+1, u64, l0_to_recovery_eieos, "l0_to_recovery_eieos", "Number of " \ 421 "transitions to recovery due to getting EIEOS.", pcie_perf_counters)\ 422 m(+1, u64, l0_to_recovery_ts, "l0_to_recovery_ts", "Number of " \ 423 "transitions to recovery due to getting TS.", pcie_perf_counters) \ 424 m(+1, u64, l0_to_recovery_framing, "l0_to_recovery_framing", "Number "\ 425 "of transitions to recovery due to identifying framing " \ 426 "errors at gen3/4.", pcie_perf_counters) \ 427 m(+1, u64, l0_to_recovery_retrain, "l0_to_recovery_retrain", \ 428 "Number of transitions to recovery due to link retrain request " \ 429 "from data link.", pcie_perf_counters) \ 430 m(+1, u64, crc_error_dllp, "crc_error_dllp", "Number of transitions " \ 431 "to recovery due to identifying CRC DLLP errors.", \ 432 pcie_perf_counters) \ 433 m(+1, u64, crc_error_tlp, "crc_error_tlp", "Number of transitions to "\ 434 "recovery due to identifying CRC TLP errors.", pcie_perf_counters) \ 435 m(+1, u64, outbound_stalled_reads, "outbound_stalled_reads", \ 436 "The percentage of time within the last second that the NIC had " \ 437 "outbound non-posted read requests but could not perform the " \ 438 "operation due to insufficient non-posted credits.", \ 439 pcie_perf_counters) \ 440 m(+1, u64, outbound_stalled_writes, "outbound_stalled_writes", \ 441 "The percentage of time within the last second that the NIC had " \ 442 "outbound posted writes requests but could not perform the " \ 443 "operation due to insufficient posted credits.", \ 444 pcie_perf_counters) \ 445 m(+1, u64, outbound_stalled_reads_events, \ 446 "outbound_stalled_reads_events", "The number of events where " \ 447 "outbound_stalled_reads was above a threshold.", \ 448 pcie_perf_counters) \ 449 m(+1, u64, outbound_stalled_writes_events, \ 450 "outbound_stalled_writes_events", \ 451 "The number of events where outbound_stalled_writes was above " \ 452 "a threshold.", pcie_perf_counters) 453 454#define MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(m) \ 455 m(+1, u64, time_to_boot_image_start, "time_to_boot_image_start", \ 456 "Time from start until FW boot image starts running in usec.", \ 457 pcie_timers_states) \ 458 m(+1, u64, time_to_link_image, "time_to_link_image", \ 459 "Time from start until FW pci_link image starts running in usec.", \ 460 pcie_timers_states) \ 461 m(+1, u64, calibration_time, "calibration_time", \ 462 "Time it took FW to do calibration in usec.", \ 463 pcie_timers_states) \ 464 m(+1, u64, time_to_first_perst, "time_to_first_perst", \ 465 "Time form start until FW handle first perst. in usec.", \ 466 pcie_timers_states) \ 467 m(+1, u64, time_to_detect_state, "time_to_detect_state", \ 468 "Time from start until first transition to LTSSM.Detect_Q in usec", \ 469 pcie_timers_states) \ 470 m(+1, u64, time_to_l0, "time_to_l0", \ 471 "Time from start until first transition to LTSSM.L0 in usec", \ 472 pcie_timers_states) \ 473 m(+1, u64, time_to_crs_en, "time_to_crs_en", \ 474 "Time from start until crs is enabled in usec", \ 475 pcie_timers_states) \ 476 m(+1, u64, time_to_plastic_image_start, "time_to_plastic_image_start",\ 477 "Time form start until FW plastic image starts running in usec.", \ 478 pcie_timers_states) \ 479 m(+1, u64, time_to_iron_image_start, "time_to_iron_image_start", \ 480 "Time form start until FW iron image starts running in usec.", \ 481 pcie_timers_states) \ 482 m(+1, u64, perst_handler, "perst_handler", \ 483 "Number of persts arrived.", pcie_timers_states) \ 484 m(+1, u64, times_in_l1, "times_in_l1", \ 485 "Number of times LTSSM entered L1 flow.", pcie_timers_states) \ 486 m(+1, u64, times_in_l23, "times_in_l23", \ 487 "Number of times LTSSM entered L23 flow.", pcie_timers_states) \ 488 m(+1, u64, dl_down, "dl_down", \ 489 "Number of moves for DL_active to DL_down.", pcie_timers_states) \ 490 m(+1, u64, config_cycle1usec, "config_cycle1usec", \ 491 "Number of configuration requests that firmware " \ 492 "handled in less than 1 usec.", pcie_timers_states) \ 493 m(+1, u64, config_cycle2to7usec, "config_cycle2to7usec", \ 494 "Number of configuration requests that firmware " \ 495 "handled within 2 to 7 usec.", pcie_timers_states) \ 496 m(+1, u64, config_cycle8to15usec, "config_cycle8to15usec", \ 497 "Number of configuration requests that firmware " \ 498 "handled within 8 to 15 usec.", pcie_timers_states) \ 499 m(+1, u64, config_cycle16to63usec, "config_cycle16to63usec", \ 500 "Number of configuration requests that firmware " \ 501 "handled within 16 to 63 usec.", pcie_timers_states) \ 502 m(+1, u64, config_cycle64usec, "config_cycle64usec", \ 503 "Number of configuration requests that firmware " \ 504 "handled took more than 64 usec.", pcie_timers_states) \ 505 m(+1, u64, correctable_err_msg_sent, "correctable_err_msg_sent", \ 506 "Number of correctable error messages sent.", pcie_timers_states) \ 507 m(+1, u64, non_fatal_err_msg_sent, "non_fatal_err_msg_sent", \ 508 "Number of non-Fatal error msg sent.", pcie_timers_states) \ 509 m(+1, u64, fatal_err_msg_sent, "fatal_err_msg_sent", \ 510 "Number of fatal error msg sent.", pcie_timers_states) 511 512#define MLX5E_PCIE_LANE_COUNTERS_32(m) \ 513 m(+1, u64, error_counter_lane0, "error_counter_lane0", \ 514 "Error counter for PCI lane 0", pcie_lanes_counters) \ 515 m(+1, u64, error_counter_lane1, "error_counter_lane1", \ 516 "Error counter for PCI lane 1", pcie_lanes_counters) \ 517 m(+1, u64, error_counter_lane2, "error_counter_lane2", \ 518 "Error counter for PCI lane 2", pcie_lanes_counters) \ 519 m(+1, u64, error_counter_lane3, "error_counter_lane3", \ 520 "Error counter for PCI lane 3", pcie_lanes_counters) \ 521 m(+1, u64, error_counter_lane4, "error_counter_lane4", \ 522 "Error counter for PCI lane 4", pcie_lanes_counters) \ 523 m(+1, u64, error_counter_lane5, "error_counter_lane5", \ 524 "Error counter for PCI lane 5", pcie_lanes_counters) \ 525 m(+1, u64, error_counter_lane6, "error_counter_lane6", \ 526 "Error counter for PCI lane 6", pcie_lanes_counters) \ 527 m(+1, u64, error_counter_lane7, "error_counter_lane7", \ 528 "Error counter for PCI lane 7", pcie_lanes_counters) \ 529 m(+1, u64, error_counter_lane8, "error_counter_lane8", \ 530 "Error counter for PCI lane 8", pcie_lanes_counters) \ 531 m(+1, u64, error_counter_lane9, "error_counter_lane9", \ 532 "Error counter for PCI lane 9", pcie_lanes_counters) \ 533 m(+1, u64, error_counter_lane10, "error_counter_lane10", \ 534 "Error counter for PCI lane 10", pcie_lanes_counters) \ 535 m(+1, u64, error_counter_lane11, "error_counter_lane11", \ 536 "Error counter for PCI lane 11", pcie_lanes_counters) \ 537 m(+1, u64, error_counter_lane12, "error_counter_lane12", \ 538 "Error counter for PCI lane 12", pcie_lanes_counters) \ 539 m(+1, u64, error_counter_lane13, "error_counter_lane13", \ 540 "Error counter for PCI lane 13", pcie_lanes_counters) \ 541 m(+1, u64, error_counter_lane14, "error_counter_lane14", \ 542 "Error counter for PCI lane 14", pcie_lanes_counters) \ 543 m(+1, u64, error_counter_lane15, "error_counter_lane15", \ 544 "Error counter for PCI lane 15", pcie_lanes_counters) 545 546/* 547 * Make sure to update mlx5e_update_pport_counters() 548 * when adding a new MLX5E_PPORT_STATS block 549 */ 550#define MLX5E_PPORT_STATS(m) \ 551 MLX5E_PPORT_PER_PRIO_STATS(m) \ 552 MLX5E_PPORT_IEEE802_3_STATS(m) \ 553 MLX5E_PPORT_RFC2819_STATS(m) 554 555#define MLX5E_PORT_STATS_DEBUG(m) \ 556 MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 557 MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 558 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \ 559 MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(m) \ 560 MLX5E_PPORT_STATISTICAL_DEBUG(m) \ 561 MLX5E_PCIE_PERFORMANCE_COUNTERS_64(m) \ 562 MLX5E_PCIE_PERFORMANCE_COUNTERS_32(m) \ 563 MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(m) \ 564 MLX5E_PCIE_LANE_COUNTERS_32(m) 565 566#define MLX5E_PPORT_IEEE802_3_STATS_NUM \ 567 (0 MLX5E_PPORT_IEEE802_3_STATS(MLX5E_STATS_COUNT)) 568#define MLX5E_PPORT_RFC2819_STATS_NUM \ 569 (0 MLX5E_PPORT_RFC2819_STATS(MLX5E_STATS_COUNT)) 570#define MLX5E_PPORT_STATS_NUM \ 571 (0 MLX5E_PPORT_STATS(MLX5E_STATS_COUNT)) 572 573#define MLX5E_PPORT_PER_PRIO_STATS_NUM \ 574 (0 MLX5E_PPORT_PER_PRIO_STATS(MLX5E_STATS_COUNT)) 575#define MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM \ 576 (0 MLX5E_PPORT_RFC2819_STATS_DEBUG(MLX5E_STATS_COUNT)) 577#define MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM \ 578 (0 MLX5E_PPORT_RFC2863_STATS_DEBUG(MLX5E_STATS_COUNT)) 579#define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM \ 580 (0 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(MLX5E_STATS_COUNT)) 581#define MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM \ 582 (0 MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(MLX5E_STATS_COUNT)) 583#define MLX5E_PPORT_STATISTICAL_DEBUG_NUM \ 584 (0 MLX5E_PPORT_STATISTICAL_DEBUG(MLX5E_STATS_COUNT)) 585#define MLX5E_PORT_STATS_DEBUG_NUM \ 586 (0 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_COUNT)) 587 588struct mlx5e_pport_stats { 589 struct sysctl_ctx_list ctx; 590 u64 arg [0]; 591 MLX5E_PPORT_STATS(MLX5E_STATS_VAR) 592}; 593 594struct mlx5e_port_stats_debug { 595 struct sysctl_ctx_list ctx; 596 u64 arg [0]; 597 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_VAR) 598}; 599 600#define MLX5E_RQ_STATS(m) \ 601 m(+1, u64, packets, "packets", "Received packets") \ 602 m(+1, u64, bytes, "bytes", "Received bytes") \ 603 m(+1, u64, csum_none, "csum_none", "Received packets") \ 604 m(+1, u64, lro_packets, "lro_packets", "Received LRO packets") \ 605 m(+1, u64, lro_bytes, "lro_bytes", "Received LRO bytes") \ 606 m(+1, u64, sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 607 m(+1, u64, sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 608 m(+1, u64, wqe_err, "wqe_err", "Received packets") 609 610#define MLX5E_RQ_STATS_NUM (0 MLX5E_RQ_STATS(MLX5E_STATS_COUNT)) 611 612struct mlx5e_rq_stats { 613 struct sysctl_ctx_list ctx; 614 u64 arg [0]; 615 MLX5E_RQ_STATS(MLX5E_STATS_VAR) 616}; 617 618#define MLX5E_SQ_STATS(m) \ 619 m(+1, u64, packets, "packets", "Transmitted packets") \ 620 m(+1, u64, bytes, "bytes", "Transmitted bytes") \ 621 m(+1, u64, tso_packets, "tso_packets", "Transmitted packets") \ 622 m(+1, u64, tso_bytes, "tso_bytes", "Transmitted bytes") \ 623 m(+1, u64, csum_offload_none, "csum_offload_none", "Transmitted packets") \ 624 m(+1, u64, defragged, "defragged", "Transmitted packets") \ 625 m(+1, u64, dropped, "dropped", "Transmitted packets") \ 626 m(+1, u64, nop, "nop", "Transmitted packets") 627 628#define MLX5E_SQ_STATS_NUM (0 MLX5E_SQ_STATS(MLX5E_STATS_COUNT)) 629 630struct mlx5e_sq_stats { 631 struct sysctl_ctx_list ctx; 632 u64 arg [0]; 633 MLX5E_SQ_STATS(MLX5E_STATS_VAR) 634}; 635 636struct mlx5e_stats { 637 struct mlx5e_vport_stats vport; 638 struct mlx5e_pport_stats pport; 639 struct mlx5e_port_stats_debug port_stats_debug; 640}; 641 642struct mlx5e_rq_param { 643 u32 rqc [MLX5_ST_SZ_DW(rqc)]; 644 struct mlx5_wq_param wq; 645}; 646 647struct mlx5e_sq_param { 648 u32 sqc [MLX5_ST_SZ_DW(sqc)]; 649 struct mlx5_wq_param wq; 650}; 651 652struct mlx5e_cq_param { 653 u32 cqc [MLX5_ST_SZ_DW(cqc)]; 654 struct mlx5_wq_param wq; 655}; 656 657struct mlx5e_params { 658 u8 log_sq_size; 659 u8 log_rq_size; 660 u16 num_channels; 661 u8 default_vlan_prio; 662 u8 num_tc; 663 u8 rx_cq_moderation_mode; 664 u8 tx_cq_moderation_mode; 665 u16 rx_cq_moderation_usec; 666 u16 rx_cq_moderation_pkts; 667 u16 tx_cq_moderation_usec; 668 u16 tx_cq_moderation_pkts; 669 u16 min_rx_wqes; 670 bool hw_lro_en; 671 bool cqe_zipping_en; 672 u32 lro_wqe_sz; 673 u16 rx_hash_log_tbl_sz; 674 u32 tx_pauseframe_control __aligned(4); 675 u32 rx_pauseframe_control __aligned(4); 676 u16 tx_max_inline; 677 u8 tx_min_inline_mode; 678 u8 tx_priority_flow_control; 679 u8 rx_priority_flow_control; 680 u8 channels_rsss; 681}; 682 683#define MLX5E_PARAMS(m) \ 684 m(+1, u64, tx_queue_size_max, "tx_queue_size_max", "Max send queue size") \ 685 m(+1, u64, rx_queue_size_max, "rx_queue_size_max", "Max receive queue size") \ 686 m(+1, u64, tx_queue_size, "tx_queue_size", "Default send queue size") \ 687 m(+1, u64, rx_queue_size, "rx_queue_size", "Default receive queue size") \ 688 m(+1, u64, channels, "channels", "Default number of channels") \ 689 m(+1, u64, channels_rsss, "channels_rsss", "Default channels receive side scaling stride") \ 690 m(+1, u64, coalesce_usecs_max, "coalesce_usecs_max", "Maximum usecs for joining packets") \ 691 m(+1, u64, coalesce_pkts_max, "coalesce_pkts_max", "Maximum packets to join") \ 692 m(+1, u64, rx_coalesce_usecs, "rx_coalesce_usecs", "Limit in usec for joining rx packets") \ 693 m(+1, u64, rx_coalesce_pkts, "rx_coalesce_pkts", "Maximum number of rx packets to join") \ 694 m(+1, u64, rx_coalesce_mode, "rx_coalesce_mode", "0: EQE fixed mode 1: CQE fixed mode 2: EQE auto mode 3: CQE auto mode") \ 695 m(+1, u64, tx_coalesce_usecs, "tx_coalesce_usecs", "Limit in usec for joining tx packets") \ 696 m(+1, u64, tx_coalesce_pkts, "tx_coalesce_pkts", "Maximum number of tx packets to join") \ 697 m(+1, u64, tx_coalesce_mode, "tx_coalesce_mode", "0: EQE mode 1: CQE mode") \ 698 m(+1, u64, tx_completion_fact, "tx_completion_fact", "1..MAX: Completion event ratio") \ 699 m(+1, u64, tx_completion_fact_max, "tx_completion_fact_max", "Maximum completion event ratio") \ 700 m(+1, u64, hw_lro, "hw_lro", "set to enable hw_lro") \ 701 m(+1, u64, cqe_zipping, "cqe_zipping", "0 : CQE zipping disabled") \ 702 m(+1, u64, modify_tx_dma, "modify_tx_dma", "0: Enable TX 1: Disable TX") \ 703 m(+1, u64, modify_rx_dma, "modify_rx_dma", "0: Enable RX 1: Disable RX") \ 704 m(+1, u64, diag_pci_enable, "diag_pci_enable", "0: Disabled 1: Enabled") \ 705 m(+1, u64, diag_general_enable, "diag_general_enable", "0: Disabled 1: Enabled") \ 706 m(+1, u64, hw_mtu, "hw_mtu", "Current hardware MTU value") \ 707 m(+1, u64, mc_local_lb, "mc_local_lb", "0: Local multicast loopback enabled 1: Disabled") \ 708 m(+1, u64, uc_local_lb, "uc_local_lb", "0: Local unicast loopback enabled 1: Disabled") 709 710#define MLX5E_PARAMS_NUM (0 MLX5E_PARAMS(MLX5E_STATS_COUNT)) 711 712struct mlx5e_params_ethtool { 713 u64 arg [0]; 714 MLX5E_PARAMS(MLX5E_STATS_VAR) 715 u64 max_bw_value[IEEE_8021QAZ_MAX_TCS]; 716 u8 max_bw_share[IEEE_8021QAZ_MAX_TCS]; 717 u8 prio_tc[MLX5E_MAX_PRIORITY]; 718 u8 dscp2prio[MLX5_MAX_SUPPORTED_DSCP]; 719 u8 trust_state; 720 u8 fec_mask_10x_25x[MLX5E_MAX_FEC_10X_25X]; 721 u16 fec_mask_50x[MLX5E_MAX_FEC_50X]; 722 u8 fec_avail_10x_25x[MLX5E_MAX_FEC_10X_25X]; 723 u16 fec_avail_50x[MLX5E_MAX_FEC_50X]; 724 u32 fec_mode_active; 725}; 726 727struct mlx5e_cq { 728 /* data path - accessed per cqe */ 729 struct mlx5_cqwq wq; 730 731 /* data path - accessed per HW polling */ 732 struct mlx5_core_cq mcq; 733 734 /* control */ 735 struct mlx5e_priv *priv; 736 struct mlx5_wq_ctrl wq_ctrl; 737} __aligned(MLX5E_CACHELINE_SIZE); 738 739struct mlx5e_rq_mbuf { 740 bus_dmamap_t dma_map; 741 caddr_t data; 742 struct mbuf *mbuf; 743}; 744 745struct mlx5e_rq { 746 /* persistant fields */ 747 struct mtx mtx; 748 struct mlx5e_rq_stats stats; 749 750 /* data path */ 751#define mlx5e_rq_zero_start wq 752 struct mlx5_wq_ll wq; 753 bus_dma_tag_t dma_tag; 754 u32 wqe_sz; 755 u32 nsegs; 756 struct mlx5e_rq_mbuf *mbuf; 757 struct ifnet *ifp; 758 struct mlx5e_cq cq; 759 struct lro_ctrl lro; 760 volatile int enabled; 761 int ix; 762 763 /* Dynamic Interrupt Moderation */ 764 struct net_dim dim; 765 766 /* control */ 767 struct mlx5_wq_ctrl wq_ctrl; 768 u32 rqn; 769 struct mlx5e_channel *channel; 770 struct callout watchdog; 771} __aligned(MLX5E_CACHELINE_SIZE); 772 773struct mlx5e_sq_mbuf { 774 bus_dmamap_t dma_map; 775 struct mbuf *mbuf; 776 u32 num_bytes; 777 u32 num_wqebbs; 778}; 779 780enum { 781 MLX5E_SQ_READY, 782 MLX5E_SQ_FULL 783}; 784 785struct mlx5e_sq { 786 /* persistant fields */ 787 struct mtx lock; 788 struct mtx comp_lock; 789 struct mlx5e_sq_stats stats; 790 791 /* data path */ 792#define mlx5e_sq_zero_start dma_tag 793 bus_dma_tag_t dma_tag; 794 795 /* dirtied @completion */ 796 u16 cc; 797 798 /* dirtied @xmit */ 799 u16 pc __aligned(MLX5E_CACHELINE_SIZE); 800 u16 bf_offset; 801 u16 cev_counter; /* completion event counter */ 802 u16 cev_factor; /* completion event factor */ 803 u16 cev_next_state; /* next completion event state */ 804#define MLX5E_CEV_STATE_INITIAL 0 /* timer not started */ 805#define MLX5E_CEV_STATE_SEND_NOPS 1 /* send NOPs */ 806#define MLX5E_CEV_STATE_HOLD_NOPS 2 /* don't send NOPs yet */ 807 u16 running; /* set if SQ is running */ 808 struct callout cev_callout; 809 union { 810 u32 d32[2]; 811 u64 d64; 812 } doorbell; 813 814 struct mlx5e_cq cq; 815 816 /* pointers to per packet info: write@xmit, read@completion */ 817 struct mlx5e_sq_mbuf *mbuf; 818 struct buf_ring *br; 819 820 /* read only */ 821 struct mlx5_wq_cyc wq; 822 struct mlx5_uar uar; 823 struct ifnet *ifp; 824 u32 sqn; 825 u32 bf_buf_size; 826 u32 mkey_be; 827 u16 max_inline; 828 u8 min_inline_mode; 829 u8 min_insert_caps; 830#define MLX5E_INSERT_VLAN 1 831#define MLX5E_INSERT_NON_VLAN 2 832 833 /* control path */ 834 struct mlx5_wq_ctrl wq_ctrl; 835 struct mlx5e_priv *priv; 836 int tc; 837} __aligned(MLX5E_CACHELINE_SIZE); 838 839static inline bool 840mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) 841{ 842 u16 cc = sq->cc; 843 u16 pc = sq->pc; 844 845 return ((sq->wq.sz_m1 & (cc - pc)) >= n || cc == pc); 846} 847 848struct mlx5e_channel { 849 struct mlx5e_rq rq; 850 struct mlx5e_sq sq[MLX5E_MAX_TX_NUM_TC]; 851 struct ifnet *ifp; 852 struct mlx5e_priv *priv; 853 int ix; 854} __aligned(MLX5E_CACHELINE_SIZE); 855 856enum mlx5e_traffic_types { 857 MLX5E_TT_IPV4_TCP, 858 MLX5E_TT_IPV6_TCP, 859 MLX5E_TT_IPV4_UDP, 860 MLX5E_TT_IPV6_UDP, 861 MLX5E_TT_IPV4_IPSEC_AH, 862 MLX5E_TT_IPV6_IPSEC_AH, 863 MLX5E_TT_IPV4_IPSEC_ESP, 864 MLX5E_TT_IPV6_IPSEC_ESP, 865 MLX5E_TT_IPV4, 866 MLX5E_TT_IPV6, 867 MLX5E_TT_ANY, 868 MLX5E_NUM_TT, 869}; 870 871enum { 872 MLX5E_RQT_SPREADING = 0, 873 MLX5E_RQT_DEFAULT_RQ = 1, 874 MLX5E_NUM_RQT = 2, 875}; 876 877struct mlx5_flow_rule; 878 879struct mlx5e_eth_addr_info { 880 u8 addr [ETH_ALEN + 2]; 881 u32 tt_vec; 882 /* flow table rule per traffic type */ 883 struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT]; 884}; 885 886#define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE) 887 888struct mlx5e_eth_addr_hash_node; 889 890struct mlx5e_eth_addr_hash_head { 891 struct mlx5e_eth_addr_hash_node *lh_first; 892}; 893 894struct mlx5e_eth_addr_db { 895 struct mlx5e_eth_addr_hash_head if_uc[MLX5E_ETH_ADDR_HASH_SIZE]; 896 struct mlx5e_eth_addr_hash_head if_mc[MLX5E_ETH_ADDR_HASH_SIZE]; 897 struct mlx5e_eth_addr_info broadcast; 898 struct mlx5e_eth_addr_info allmulti; 899 struct mlx5e_eth_addr_info promisc; 900 bool broadcast_enabled; 901 bool allmulti_enabled; 902 bool promisc_enabled; 903}; 904 905enum { 906 MLX5E_STATE_ASYNC_EVENTS_ENABLE, 907 MLX5E_STATE_OPENED, 908}; 909 910enum { 911 MLX5_BW_NO_LIMIT = 0, 912 MLX5_100_MBPS_UNIT = 3, 913 MLX5_GBPS_UNIT = 4, 914}; 915 916struct mlx5e_vlan_db { 917 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 918 struct mlx5_flow_rule *active_vlans_ft_rule[VLAN_N_VID]; 919 struct mlx5_flow_rule *untagged_ft_rule; 920 struct mlx5_flow_rule *any_cvlan_ft_rule; 921 struct mlx5_flow_rule *any_svlan_ft_rule; 922 bool filter_disabled; 923}; 924 925struct mlx5e_flow_table { 926 int num_groups; 927 struct mlx5_flow_table *t; 928 struct mlx5_flow_group **g; 929}; 930 931struct mlx5e_flow_tables { 932 struct mlx5_flow_namespace *ns; 933 struct mlx5e_flow_table vlan; 934 struct mlx5e_flow_table main; 935 struct mlx5e_flow_table inner_rss; 936}; 937 938struct mlx5e_dcbx { 939 u32 cable_len; 940 u32 xoff; 941}; 942 943struct mlx5e_priv { 944 struct mlx5_core_dev *mdev; /* must be first */ 945 946 /* priv data path fields - start */ 947 int order_base_2_num_channels; 948 int queue_mapping_channel_mask; 949 int num_tc; 950 int default_vlan_prio; 951 /* priv data path fields - end */ 952 953 unsigned long state; 954 int gone; 955#define PRIV_LOCK(priv) sx_xlock(&(priv)->state_lock) 956#define PRIV_UNLOCK(priv) sx_xunlock(&(priv)->state_lock) 957#define PRIV_LOCKED(priv) sx_xlocked(&(priv)->state_lock) 958#define PRIV_ASSERT_LOCKED(priv) sx_assert(&(priv)->state_lock, SA_XLOCKED) 959 struct sx state_lock; /* Protects Interface state */ 960 struct mlx5_uar cq_uar; 961 u32 pdn; 962 u32 tdn; 963 struct mlx5_core_mr mr; 964 965 u32 tisn[MLX5E_MAX_TX_NUM_TC]; 966 u32 rqtn; 967 u32 tirn[MLX5E_NUM_TT]; 968 969 struct mlx5e_flow_tables fts; 970 struct mlx5e_eth_addr_db eth_addr; 971 struct mlx5e_vlan_db vlan; 972 973 struct mlx5e_params params; 974 struct mlx5e_params_ethtool params_ethtool; 975 union mlx5_core_pci_diagnostics params_pci; 976 union mlx5_core_general_diagnostics params_general; 977 struct mtx async_events_mtx; /* sync hw events */ 978 struct work_struct update_stats_work; 979 struct work_struct update_carrier_work; 980 struct work_struct set_rx_mode_work; 981 MLX5_DECLARE_DOORBELL_LOCK(doorbell_lock) 982 983 struct ifnet *ifp; 984 struct sysctl_ctx_list sysctl_ctx; 985 struct sysctl_oid *sysctl_ifnet; 986 struct sysctl_oid *sysctl_hw; 987 int sysctl_debug; 988 struct mlx5e_stats stats; 989 int counter_set_id; 990 991 struct workqueue_struct *wq; 992 993 eventhandler_tag vlan_detach; 994 eventhandler_tag vlan_attach; 995 struct ifmedia media; 996 int media_status_last; 997 int media_active_last; 998 999 struct callout watchdog; 1000 1001 struct mlx5e_dcbx dcbx; 1002 1003 struct mlx5e_channel channel[]; 1004}; 1005 1006#define MLX5E_NET_IP_ALIGN 2 1007 1008struct mlx5e_tx_wqe { 1009 struct mlx5_wqe_ctrl_seg ctrl; 1010 struct mlx5_wqe_eth_seg eth; 1011}; 1012 1013struct mlx5e_rx_wqe { 1014 struct mlx5_wqe_srq_next_seg next; 1015 struct mlx5_wqe_data_seg data[]; 1016}; 1017 1018/* the size of the structure above must be power of two */ 1019CTASSERT(powerof2(sizeof(struct mlx5e_rx_wqe))); 1020 1021struct mlx5e_eeprom { 1022 int lock_bit; 1023 int i2c_addr; 1024 int page_num; 1025 int device_addr; 1026 int module_num; 1027 int len; 1028 int type; 1029 int page_valid; 1030 u32 *data; 1031}; 1032 1033#define MLX5E_FLD_MAX(typ, fld) ((1ULL << __mlx5_bit_sz(typ, fld)) - 1ULL) 1034 1035int mlx5e_xmit(struct ifnet *, struct mbuf *); 1036 1037int mlx5e_open_locked(struct ifnet *); 1038int mlx5e_close_locked(struct ifnet *); 1039 1040void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, int event); 1041void mlx5e_rx_cq_comp(struct mlx5_core_cq *); 1042void mlx5e_tx_cq_comp(struct mlx5_core_cq *); 1043struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); 1044 1045void mlx5e_dim_work(struct work_struct *); 1046void mlx5e_dim_build_cq_param(struct mlx5e_priv *, struct mlx5e_cq_param *); 1047 1048int mlx5e_open_flow_table(struct mlx5e_priv *priv); 1049void mlx5e_close_flow_table(struct mlx5e_priv *priv); 1050void mlx5e_set_rx_mode_core(struct mlx5e_priv *priv); 1051void mlx5e_set_rx_mode_work(struct work_struct *work); 1052 1053void mlx5e_vlan_rx_add_vid(void *, struct ifnet *, u16); 1054void mlx5e_vlan_rx_kill_vid(void *, struct ifnet *, u16); 1055void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); 1056void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); 1057int mlx5e_add_all_vlan_rules(struct mlx5e_priv *priv); 1058void mlx5e_del_all_vlan_rules(struct mlx5e_priv *priv); 1059 1060static inline void 1061mlx5e_tx_notify_hw(struct mlx5e_sq *sq, u32 *wqe, int bf_sz) 1062{ 1063 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; 1064 1065 /* ensure wqe is visible to device before updating doorbell record */ 1066 wmb(); 1067 1068 *sq->wq.db = cpu_to_be32(sq->pc); 1069 1070 /* 1071 * Ensure the doorbell record is visible to device before ringing 1072 * the doorbell: 1073 */ 1074 wmb(); 1075 1076 if (bf_sz) { 1077 __iowrite64_copy(sq->uar.bf_map + ofst, wqe, bf_sz); 1078 1079 /* flush the write-combining mapped buffer */ 1080 wmb(); 1081 1082 } else { 1083 mlx5_write64(wqe, sq->uar.map + ofst, 1084 MLX5_GET_DOORBELL_LOCK(&sq->priv->doorbell_lock)); 1085 } 1086 1087 sq->bf_offset ^= sq->bf_buf_size; 1088} 1089 1090static inline void 1091mlx5e_cq_arm(struct mlx5e_cq *cq, spinlock_t *dblock) 1092{ 1093 struct mlx5_core_cq *mcq; 1094 1095 mcq = &cq->mcq; 1096 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, dblock, cq->wq.cc); 1097} 1098 1099#define mlx5e_dbg(_IGN, _priv, ...) mlx5_core_dbg((_priv)->mdev, __VA_ARGS__) 1100 1101extern const struct ethtool_ops mlx5e_ethtool_ops; 1102void mlx5e_create_ethtool(struct mlx5e_priv *); 1103void mlx5e_create_stats(struct sysctl_ctx_list *, 1104 struct sysctl_oid_list *, const char *, 1105 const char **, unsigned, u64 *); 1106void mlx5e_send_nop(struct mlx5e_sq *, u32); 1107void mlx5e_sq_cev_timeout(void *); 1108int mlx5e_refresh_channel_params(struct mlx5e_priv *); 1109int mlx5e_open_cq(struct mlx5e_priv *, struct mlx5e_cq_param *, 1110 struct mlx5e_cq *, mlx5e_cq_comp_t *, int eq_ix); 1111void mlx5e_close_cq(struct mlx5e_cq *); 1112void mlx5e_free_sq_db(struct mlx5e_sq *); 1113int mlx5e_alloc_sq_db(struct mlx5e_sq *); 1114int mlx5e_enable_sq(struct mlx5e_sq *, struct mlx5e_sq_param *, int tis_num); 1115int mlx5e_modify_sq(struct mlx5e_sq *, int curr_state, int next_state); 1116void mlx5e_disable_sq(struct mlx5e_sq *); 1117void mlx5e_drain_sq(struct mlx5e_sq *); 1118void mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value); 1119void mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value); 1120void mlx5e_resume_sq(struct mlx5e_sq *sq); 1121void mlx5e_update_sq_inline(struct mlx5e_sq *sq); 1122void mlx5e_refresh_sq_inline(struct mlx5e_priv *priv); 1123int mlx5e_update_buf_lossy(struct mlx5e_priv *priv); 1124int mlx5e_fec_update(struct mlx5e_priv *priv); 1125 1126#endif /* _MLX5_EN_H_ */ 1127