en.h revision 353226
1/*- 2 * Copyright (c) 2015-2019 Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_en/en.h 353226 2019-10-07 09:28:53Z hselasky $ 26 */ 27 28#ifndef _MLX5_EN_H_ 29#define _MLX5_EN_H_ 30 31#include <linux/kmod.h> 32#include <linux/page.h> 33#include <linux/slab.h> 34#include <linux/if_vlan.h> 35#include <linux/if_ether.h> 36#include <linux/vmalloc.h> 37#include <linux/moduleparam.h> 38#include <linux/delay.h> 39#include <linux/netdevice.h> 40#include <linux/etherdevice.h> 41#include <linux/ktime.h> 42#include <linux/net_dim.h> 43 44#include <netinet/in_systm.h> 45#include <netinet/in.h> 46#include <netinet/if_ether.h> 47#include <netinet/ip.h> 48#include <netinet/ip6.h> 49#include <netinet/tcp.h> 50#include <netinet/tcp_lro.h> 51#include <netinet/udp.h> 52#include <net/ethernet.h> 53#include <sys/buf_ring.h> 54 55#include "opt_rss.h" 56 57#ifdef RSS 58#include <net/rss_config.h> 59#include <netinet/in_rss.h> 60#endif 61 62#include <machine/bus.h> 63 64#include <dev/mlx5/driver.h> 65#include <dev/mlx5/qp.h> 66#include <dev/mlx5/cq.h> 67#include <dev/mlx5/port.h> 68#include <dev/mlx5/vport.h> 69#include <dev/mlx5/diagnostics.h> 70 71#include <dev/mlx5/mlx5_core/wq.h> 72#include <dev/mlx5/mlx5_core/transobj.h> 73#include <dev/mlx5/mlx5_core/mlx5_core.h> 74 75#define MLX5E_MAX_PRIORITY 8 76 77/* IEEE 802.1Qaz standard supported values */ 78#define IEEE_8021QAZ_MAX_TCS 8 79 80#define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x7 81#define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa 82#define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xe 83 84#define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x7 85#define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa 86#define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xe 87 88#define MLX5E_MAX_BUSDMA_RX_SEGS 15 89 90#ifndef MLX5E_MAX_RX_BYTES 91#define MLX5E_MAX_RX_BYTES MCLBYTES 92#endif 93 94#define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ \ 95 MIN(65535, 7 * MLX5E_MAX_RX_BYTES) 96 97#define MLX5E_DIM_DEFAULT_PROFILE 3 98#define MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO 16 99#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 100#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 101#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 102#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 103#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 104#define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 105#define MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ 0x7 106#define MLX5E_CACHELINE_SIZE CACHE_LINE_SIZE 107#define MLX5E_HW2SW_MTU(hwmtu) \ 108 ((hwmtu) - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 109#define MLX5E_SW2HW_MTU(swmtu) \ 110 ((swmtu) + (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 111#define MLX5E_SW2MB_MTU(swmtu) \ 112 (MLX5E_SW2HW_MTU(swmtu) + MLX5E_NET_IP_ALIGN) 113#define MLX5E_MTU_MIN 72 /* Min MTU allowed by the kernel */ 114#define MLX5E_MTU_MAX MIN(ETHERMTU_JUMBO, MJUM16BYTES) /* Max MTU of Ethernet 115 * jumbo frames */ 116 117#define MLX5E_BUDGET_MAX 8192 /* RX and TX */ 118#define MLX5E_RX_BUDGET_MAX 256 119#define MLX5E_SQ_BF_BUDGET 16 120#define MLX5E_SQ_TX_QUEUE_SIZE 4096 /* SQ drbr queue size */ 121 122#define MLX5E_MAX_TX_NUM_TC 8 /* units */ 123#define MLX5E_MAX_TX_HEADER 128 /* bytes */ 124#define MLX5E_MAX_TX_PAYLOAD_SIZE 65536 /* bytes */ 125#define MLX5E_MAX_TX_MBUF_SIZE 65536 /* bytes */ 126#define MLX5E_MAX_TX_MBUF_FRAGS \ 127 ((MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS) - \ 128 (MLX5E_MAX_TX_HEADER / MLX5_SEND_WQE_DS) - \ 129 1 /* the maximum value of the DS counter is 0x3F and not 0x40 */) /* units */ 130#define MLX5E_MAX_TX_INLINE \ 131 (MLX5E_MAX_TX_HEADER - sizeof(struct mlx5e_tx_wqe) + \ 132 sizeof(((struct mlx5e_tx_wqe *)0)->eth.inline_hdr_start)) /* bytes */ 133 134#define MLX5E_100MB (100000) 135#define MLX5E_1GB (1000000) 136 137MALLOC_DECLARE(M_MLX5EN); 138 139struct mlx5_core_dev; 140struct mlx5e_cq; 141 142typedef void (mlx5e_cq_comp_t)(struct mlx5_core_cq *); 143 144#define mlx5_en_err(_dev, format, ...) \ 145 if_printf(_dev, "ERR: ""%s:%d:(pid %d): " format, \ 146 __func__, __LINE__, curthread->td_proc->p_pid, \ 147 ##__VA_ARGS__) 148 149#define mlx5_en_warn(_dev, format, ...) \ 150 if_printf(_dev, "WARN: ""%s:%d:(pid %d): " format, \ 151 __func__, __LINE__, curthread->td_proc->p_pid, \ 152 ##__VA_ARGS__) 153 154#define mlx5_en_info(_dev, format, ...) \ 155 if_printf(_dev, "INFO: ""%s:%d:(pid %d): " format, \ 156 __func__, __LINE__, curthread->td_proc->p_pid, \ 157 ##__VA_ARGS__) 158 159#define MLX5E_STATS_COUNT(a, ...) a 160#define MLX5E_STATS_VAR(a, b, c, ...) b c; 161#define MLX5E_STATS_DESC(a, b, c, d, e, ...) d, e, 162 163#define MLX5E_VPORT_STATS(m) \ 164 /* HW counters */ \ 165 m(+1, u64, rx_packets, "rx_packets", "Received packets") \ 166 m(+1, u64, rx_bytes, "rx_bytes", "Received bytes") \ 167 m(+1, u64, tx_packets, "tx_packets", "Transmitted packets") \ 168 m(+1, u64, tx_bytes, "tx_bytes", "Transmitted bytes") \ 169 m(+1, u64, rx_error_packets, "rx_error_packets", "Received error packets") \ 170 m(+1, u64, rx_error_bytes, "rx_error_bytes", "Received error bytes") \ 171 m(+1, u64, tx_error_packets, "tx_error_packets", "Transmitted error packets") \ 172 m(+1, u64, tx_error_bytes, "tx_error_bytes", "Transmitted error bytes") \ 173 m(+1, u64, rx_unicast_packets, "rx_unicast_packets", "Received unicast packets") \ 174 m(+1, u64, rx_unicast_bytes, "rx_unicast_bytes", "Received unicast bytes") \ 175 m(+1, u64, tx_unicast_packets, "tx_unicast_packets", "Transmitted unicast packets") \ 176 m(+1, u64, tx_unicast_bytes, "tx_unicast_bytes", "Transmitted unicast bytes") \ 177 m(+1, u64, rx_multicast_packets, "rx_multicast_packets", "Received multicast packets") \ 178 m(+1, u64, rx_multicast_bytes, "rx_multicast_bytes", "Received multicast bytes") \ 179 m(+1, u64, tx_multicast_packets, "tx_multicast_packets", "Transmitted multicast packets") \ 180 m(+1, u64, tx_multicast_bytes, "tx_multicast_bytes", "Transmitted multicast bytes") \ 181 m(+1, u64, rx_broadcast_packets, "rx_broadcast_packets", "Received broadcast packets") \ 182 m(+1, u64, rx_broadcast_bytes, "rx_broadcast_bytes", "Received broadcast bytes") \ 183 m(+1, u64, tx_broadcast_packets, "tx_broadcast_packets", "Transmitted broadcast packets") \ 184 m(+1, u64, tx_broadcast_bytes, "tx_broadcast_bytes", "Transmitted broadcast bytes") \ 185 m(+1, u64, rx_out_of_buffer, "rx_out_of_buffer", "Receive out of buffer, no recv wqes events") \ 186 /* SW counters */ \ 187 m(+1, u64, tso_packets, "tso_packets", "Transmitted TSO packets") \ 188 m(+1, u64, tso_bytes, "tso_bytes", "Transmitted TSO bytes") \ 189 m(+1, u64, lro_packets, "lro_packets", "Received LRO packets") \ 190 m(+1, u64, lro_bytes, "lro_bytes", "Received LRO bytes") \ 191 m(+1, u64, sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 192 m(+1, u64, sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 193 m(+1, u64, rx_csum_good, "rx_csum_good", "Received checksum valid packets") \ 194 m(+1, u64, rx_csum_none, "rx_csum_none", "Received no checksum packets") \ 195 m(+1, u64, tx_csum_offload, "tx_csum_offload", "Transmit checksum offload packets") \ 196 m(+1, u64, tx_queue_dropped, "tx_queue_dropped", "Transmit queue dropped") \ 197 m(+1, u64, tx_defragged, "tx_defragged", "Transmit queue defragged") \ 198 m(+1, u64, rx_wqe_err, "rx_wqe_err", "Receive WQE errors") \ 199 m(+1, u64, tx_jumbo_packets, "tx_jumbo_packets", "TX packets greater than 1518 octets") \ 200 m(+1, u64, rx_steer_missed_packets, "rx_steer_missed_packets", "RX packets dropped by steering rule(s)") 201 202#define MLX5E_VPORT_STATS_NUM (0 MLX5E_VPORT_STATS(MLX5E_STATS_COUNT)) 203 204struct mlx5e_vport_stats { 205 struct sysctl_ctx_list ctx; 206 u64 arg [0]; 207 MLX5E_VPORT_STATS(MLX5E_STATS_VAR) 208}; 209 210#define MLX5E_PPORT_IEEE802_3_STATS(m) \ 211 m(+1, u64, frames_tx, "frames_tx", "Frames transmitted") \ 212 m(+1, u64, frames_rx, "frames_rx", "Frames received") \ 213 m(+1, u64, check_seq_err, "check_seq_err", "Sequence errors") \ 214 m(+1, u64, alignment_err, "alignment_err", "Alignment errors") \ 215 m(+1, u64, octets_tx, "octets_tx", "Bytes transmitted") \ 216 m(+1, u64, octets_received, "octets_received", "Bytes received") \ 217 m(+1, u64, multicast_xmitted, "multicast_xmitted", "Multicast transmitted") \ 218 m(+1, u64, broadcast_xmitted, "broadcast_xmitted", "Broadcast transmitted") \ 219 m(+1, u64, multicast_rx, "multicast_rx", "Multicast received") \ 220 m(+1, u64, broadcast_rx, "broadcast_rx", "Broadcast received") \ 221 m(+1, u64, in_range_len_errors, "in_range_len_errors", "In range length errors") \ 222 m(+1, u64, out_of_range_len, "out_of_range_len", "Out of range length errors") \ 223 m(+1, u64, too_long_errors, "too_long_errors", "Too long errors") \ 224 m(+1, u64, symbol_err, "symbol_err", "Symbol errors") \ 225 m(+1, u64, mac_control_tx, "mac_control_tx", "MAC control transmitted") \ 226 m(+1, u64, mac_control_rx, "mac_control_rx", "MAC control received") \ 227 m(+1, u64, unsupported_op_rx, "unsupported_op_rx", "Unsupported operation received") \ 228 m(+1, u64, pause_ctrl_rx, "pause_ctrl_rx", "Pause control received") \ 229 m(+1, u64, pause_ctrl_tx, "pause_ctrl_tx", "Pause control transmitted") 230 231#define MLX5E_PPORT_RFC2819_STATS(m) \ 232 m(+1, u64, drop_events, "drop_events", "Dropped events") \ 233 m(+1, u64, octets, "octets", "Octets") \ 234 m(+1, u64, pkts, "pkts", "Packets") \ 235 m(+1, u64, broadcast_pkts, "broadcast_pkts", "Broadcast packets") \ 236 m(+1, u64, multicast_pkts, "multicast_pkts", "Multicast packets") \ 237 m(+1, u64, crc_align_errors, "crc_align_errors", "CRC alignment errors") \ 238 m(+1, u64, undersize_pkts, "undersize_pkts", "Undersized packets") \ 239 m(+1, u64, oversize_pkts, "oversize_pkts", "Oversized packets") \ 240 m(+1, u64, fragments, "fragments", "Fragments") \ 241 m(+1, u64, jabbers, "jabbers", "Jabbers") \ 242 m(+1, u64, collisions, "collisions", "Collisions") 243 244#define MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 245 m(+1, u64, p64octets, "p64octets", "Bytes") \ 246 m(+1, u64, p65to127octets, "p65to127octets", "Bytes") \ 247 m(+1, u64, p128to255octets, "p128to255octets", "Bytes") \ 248 m(+1, u64, p256to511octets, "p256to511octets", "Bytes") \ 249 m(+1, u64, p512to1023octets, "p512to1023octets", "Bytes") \ 250 m(+1, u64, p1024to1518octets, "p1024to1518octets", "Bytes") \ 251 m(+1, u64, p1519to2047octets, "p1519to2047octets", "Bytes") \ 252 m(+1, u64, p2048to4095octets, "p2048to4095octets", "Bytes") \ 253 m(+1, u64, p4096to8191octets, "p4096to8191octets", "Bytes") \ 254 m(+1, u64, p8192to10239octets, "p8192to10239octets", "Bytes") 255 256#define MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 257 m(+1, u64, in_octets, "in_octets", "In octets") \ 258 m(+1, u64, in_ucast_pkts, "in_ucast_pkts", "In unicast packets") \ 259 m(+1, u64, in_discards, "in_discards", "In discards") \ 260 m(+1, u64, in_errors, "in_errors", "In errors") \ 261 m(+1, u64, in_unknown_protos, "in_unknown_protos", "In unknown protocols") \ 262 m(+1, u64, out_octets, "out_octets", "Out octets") \ 263 m(+1, u64, out_ucast_pkts, "out_ucast_pkts", "Out unicast packets") \ 264 m(+1, u64, out_discards, "out_discards", "Out discards") \ 265 m(+1, u64, out_errors, "out_errors", "Out errors") \ 266 m(+1, u64, in_multicast_pkts, "in_multicast_pkts", "In multicast packets") \ 267 m(+1, u64, in_broadcast_pkts, "in_broadcast_pkts", "In broadcast packets") \ 268 m(+1, u64, out_multicast_pkts, "out_multicast_pkts", "Out multicast packets") \ 269 m(+1, u64, out_broadcast_pkts, "out_broadcast_pkts", "Out broadcast packets") 270 271#define MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(m) \ 272 m(+1, u64, port_transmit_wait, "port_transmit_wait", "Port transmit wait") \ 273 m(+1, u64, ecn_marked, "ecn_marked", "ECN marked") \ 274 m(+1, u64, no_buffer_discard_mc, "no_buffer_discard_mc", "No buffer discard mc") \ 275 m(+1, u64, rx_ebp, "rx_ebp", "RX EBP") \ 276 m(+1, u64, tx_ebp, "tx_ebp", "TX EBP") \ 277 m(+1, u64, rx_buffer_almost_full, "rx_buffer_almost_full", "RX buffer almost full") \ 278 m(+1, u64, rx_buffer_full, "rx_buffer_full", "RX buffer full") \ 279 m(+1, u64, rx_icrc_encapsulated, "rx_icrc_encapsulated", "RX ICRC encapsulated") \ 280 m(+1, u64, ex_reserved_0, "ex_reserved_0", "Reserved") \ 281 m(+1, u64, ex_reserved_1, "ex_reserved_1", "Reserved") \ 282 m(+1, u64, tx_stat_p64octets, "tx_stat_p64octets", "Bytes") \ 283 m(+1, u64, tx_stat_p65to127octets, "tx_stat_p65to127octets", "Bytes") \ 284 m(+1, u64, tx_stat_p128to255octets, "tx_stat_p128to255octets", "Bytes") \ 285 m(+1, u64, tx_stat_p256to511octets, "tx_stat_p256to511octets", "Bytes") \ 286 m(+1, u64, tx_stat_p512to1023octets, "tx_stat_p512to1023octets", "Bytes") \ 287 m(+1, u64, tx_stat_p1024to1518octets, "tx_stat_p1024to1518octets", "Bytes") \ 288 m(+1, u64, tx_stat_p1519to2047octets, "tx_stat_p1519to2047octets", "Bytes") \ 289 m(+1, u64, tx_stat_p2048to4095octets, "tx_stat_p2048to4095octets", "Bytes") \ 290 m(+1, u64, tx_stat_p4096to8191octets, "tx_stat_p4096to8191octets", "Bytes") \ 291 m(+1, u64, tx_stat_p8192to10239octets, "tx_stat_p8192to10239octets", "Bytes") 292 293#define MLX5E_PPORT_STATISTICAL_DEBUG(m) \ 294 m(+1, u64, phy_time_since_last_clear, "phy_time_since_last_clear", \ 295 "Time since last clear in milliseconds") \ 296 m(+1, u64, phy_received_bits, "phy_received_bits", \ 297 "Total amount of traffic received in bits before error correction") \ 298 m(+1, u64, phy_symbol_errors, "phy_symbol_errors", \ 299 "Total number of symbol errors before error correction") \ 300 m(+1, u64, phy_corrected_bits, "phy_corrected_bits", \ 301 "Total number of corrected bits ") \ 302 m(+1, u64, phy_corrected_bits_lane0, "phy_corrected_bits_lane0", \ 303 "Total number of corrected bits for lane 0") \ 304 m(+1, u64, phy_corrected_bits_lane1, "phy_corrected_bits_lane1", \ 305 "Total number of corrected bits for lane 1") \ 306 m(+1, u64, phy_corrected_bits_lane2, "phy_corrected_bits_lane2", \ 307 "Total number of corrected bits for lane 2") \ 308 m(+1, u64, phy_corrected_bits_lane3, "phy_corrected_bits_lane3", \ 309 "Total number of corrected bits for lane 3") 310 311#define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \ 312 m(+1, u64, time_since_last_clear, "time_since_last_clear", \ 313 "Time since the last counters clear event (msec)") \ 314 m(+1, u64, symbol_errors, "symbol_errors", "Symbol errors") \ 315 m(+1, u64, sync_headers_errors, "sync_headers_errors", \ 316 "Sync header error counter") \ 317 m(+1, u64, bip_errors_lane0, "edpl_bip_errors_lane0", \ 318 "Indicates the number of PRBS errors on lane 0") \ 319 m(+1, u64, bip_errors_lane1, "edpl_bip_errors_lane1", \ 320 "Indicates the number of PRBS errors on lane 1") \ 321 m(+1, u64, bip_errors_lane2, "edpl_bip_errors_lane2", \ 322 "Indicates the number of PRBS errors on lane 2") \ 323 m(+1, u64, bip_errors_lane3, "edpl_bip_errors_lane3", \ 324 "Indicates the number of PRBS errors on lane 3") \ 325 m(+1, u64, fc_corrected_blocks_lane0, "fc_corrected_blocks_lane0", \ 326 "FEC correctable block counter lane 0") \ 327 m(+1, u64, fc_corrected_blocks_lane1, "fc_corrected_blocks_lane1", \ 328 "FEC correctable block counter lane 1") \ 329 m(+1, u64, fc_corrected_blocks_lane2, "fc_corrected_blocks_lane2", \ 330 "FEC correctable block counter lane 2") \ 331 m(+1, u64, fc_corrected_blocks_lane3, "fc_corrected_blocks_lane3", \ 332 "FEC correctable block counter lane 3") \ 333 m(+1, u64, rs_corrected_blocks, "rs_corrected_blocks", \ 334 "FEC correcable block counter") \ 335 m(+1, u64, rs_uncorrectable_blocks, "rs_uncorrectable_blocks", \ 336 "FEC uncorrecable block counter") \ 337 m(+1, u64, rs_no_errors_blocks, "rs_no_errors_blocks", \ 338 "The number of RS-FEC blocks received that had no errors") \ 339 m(+1, u64, rs_single_error_blocks, "rs_single_error_blocks", \ 340 "The number of corrected RS-FEC blocks received that had" \ 341 "exactly 1 error symbol") \ 342 m(+1, u64, rs_corrected_symbols_total, "rs_corrected_symbols_total", \ 343 "Port FEC corrected symbol counter") \ 344 m(+1, u64, rs_corrected_symbols_lane0, "rs_corrected_symbols_lane0", \ 345 "FEC corrected symbol counter lane 0") \ 346 m(+1, u64, rs_corrected_symbols_lane1, "rs_corrected_symbols_lane1", \ 347 "FEC corrected symbol counter lane 1") \ 348 m(+1, u64, rs_corrected_symbols_lane2, "rs_corrected_symbols_lane2", \ 349 "FEC corrected symbol counter lane 2") \ 350 m(+1, u64, rs_corrected_symbols_lane3, "rs_corrected_symbols_lane3", \ 351 "FEC corrected symbol counter lane 3") 352 353/* Per priority statistics for PFC */ 354#define MLX5E_PPORT_PER_PRIO_STATS_SUB(m,n,p) \ 355 m(n, p, +1, u64, rx_octets, "rx_octets", "Received octets") \ 356 m(n, p, +1, u64, rx_uc_frames, "rx_uc_frames", "Received unicast frames") \ 357 m(n, p, +1, u64, rx_mc_frames, "rx_mc_frames", "Received multicast frames") \ 358 m(n, p, +1, u64, rx_bc_frames, "rx_bc_frames", "Received broadcast frames") \ 359 m(n, p, +1, u64, rx_frames, "rx_frames", "Received frames") \ 360 m(n, p, +1, u64, tx_octets, "tx_octets", "Transmitted octets") \ 361 m(n, p, +1, u64, tx_uc_frames, "tx_uc_frames", "Transmitted unicast frames") \ 362 m(n, p, +1, u64, tx_mc_frames, "tx_mc_frames", "Transmitted multicast frames") \ 363 m(n, p, +1, u64, tx_bc_frames, "tx_bc_frames", "Transmitted broadcast frames") \ 364 m(n, p, +1, u64, tx_frames, "tx_frames", "Transmitted frames") \ 365 m(n, p, +1, u64, rx_pause, "rx_pause", "Received pause frames") \ 366 m(n, p, +1, u64, rx_pause_duration, "rx_pause_duration", \ 367 "Received pause duration") \ 368 m(n, p, +1, u64, tx_pause, "tx_pause", "Transmitted pause frames") \ 369 m(n, p, +1, u64, tx_pause_duration, "tx_pause_duration", \ 370 "Transmitted pause duration") \ 371 m(n, p, +1, u64, rx_pause_transition, "rx_pause_transition", \ 372 "Received pause transitions") \ 373 m(n, p, +1, u64, rx_discards, "rx_discards", "Discarded received frames") \ 374 m(n, p, +1, u64, device_stall_minor_watermark, \ 375 "device_stall_minor_watermark", "Device stall minor watermark") \ 376 m(n, p, +1, u64, device_stall_critical_watermark, \ 377 "device_stall_critical_watermark", "Device stall critical watermark") 378 379#define MLX5E_PPORT_PER_PRIO_STATS_PREFIX(m,p,c,t,f,s,d) \ 380 m(c, t, pri_##p##_##f, "prio" #p "_" s, "Priority " #p " - " d) 381 382#define MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO 8 383 384#define MLX5E_PPORT_PER_PRIO_STATS(m) \ 385 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,0) \ 386 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,1) \ 387 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,2) \ 388 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,3) \ 389 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,4) \ 390 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,5) \ 391 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,6) \ 392 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,7) 393 394#define MLX5E_PCIE_PERFORMANCE_COUNTERS_64(m) \ 395 m(+1, u64, life_time_counter_high, "life_time_counter", \ 396 "Life time counter.", pcie_perf_counters) \ 397 m(+1, u64, tx_overflow_buffer_pkt, "tx_overflow_buffer_pkt", \ 398 "The number of packets dropped due to lack of PCIe buffers " \ 399 "in receive path from NIC port toward the hosts.", \ 400 pcie_perf_counters) \ 401 m(+1, u64, tx_overflow_buffer_marked_pkt, \ 402 "tx_overflow_buffer_marked_pkt", \ 403 "The number of packets marked due to lack of PCIe buffers " \ 404 "in receive path from NIC port toward the hosts.", \ 405 pcie_perf_counters) 406 407#define MLX5E_PCIE_PERFORMANCE_COUNTERS_32(m) \ 408 m(+1, u64, rx_errors, "rx_errors", \ 409 "Number of transitions to recovery due to Framing " \ 410 "errors and CRC errors.", pcie_perf_counters) \ 411 m(+1, u64, tx_errors, "tx_errors", "Number of transitions " \ 412 "to recovery due to EIEOS and TS errors.", pcie_perf_counters) \ 413 m(+1, u64, l0_to_recovery_eieos, "l0_to_recovery_eieos", "Number of " \ 414 "transitions to recovery due to getting EIEOS.", pcie_perf_counters)\ 415 m(+1, u64, l0_to_recovery_ts, "l0_to_recovery_ts", "Number of " \ 416 "transitions to recovery due to getting TS.", pcie_perf_counters) \ 417 m(+1, u64, l0_to_recovery_framing, "l0_to_recovery_framing", "Number "\ 418 "of transitions to recovery due to identifying framing " \ 419 "errors at gen3/4.", pcie_perf_counters) \ 420 m(+1, u64, l0_to_recovery_retrain, "l0_to_recovery_retrain", \ 421 "Number of transitions to recovery due to link retrain request " \ 422 "from data link.", pcie_perf_counters) \ 423 m(+1, u64, crc_error_dllp, "crc_error_dllp", "Number of transitions " \ 424 "to recovery due to identifying CRC DLLP errors.", \ 425 pcie_perf_counters) \ 426 m(+1, u64, crc_error_tlp, "crc_error_tlp", "Number of transitions to "\ 427 "recovery due to identifying CRC TLP errors.", pcie_perf_counters) \ 428 m(+1, u64, outbound_stalled_reads, "outbound_stalled_reads", \ 429 "The percentage of time within the last second that the NIC had " \ 430 "outbound non-posted read requests but could not perform the " \ 431 "operation due to insufficient non-posted credits.", \ 432 pcie_perf_counters) \ 433 m(+1, u64, outbound_stalled_writes, "outbound_stalled_writes", \ 434 "The percentage of time within the last second that the NIC had " \ 435 "outbound posted writes requests but could not perform the " \ 436 "operation due to insufficient posted credits.", \ 437 pcie_perf_counters) \ 438 m(+1, u64, outbound_stalled_reads_events, \ 439 "outbound_stalled_reads_events", "The number of events where " \ 440 "outbound_stalled_reads was above a threshold.", \ 441 pcie_perf_counters) \ 442 m(+1, u64, outbound_stalled_writes_events, \ 443 "outbound_stalled_writes_events", \ 444 "The number of events where outbound_stalled_writes was above " \ 445 "a threshold.", pcie_perf_counters) 446 447#define MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(m) \ 448 m(+1, u64, time_to_boot_image_start, "time_to_boot_image_start", \ 449 "Time from start until FW boot image starts running in usec.", \ 450 pcie_timers_states) \ 451 m(+1, u64, time_to_link_image, "time_to_link_image", \ 452 "Time from start until FW pci_link image starts running in usec.", \ 453 pcie_timers_states) \ 454 m(+1, u64, calibration_time, "calibration_time", \ 455 "Time it took FW to do calibration in usec.", \ 456 pcie_timers_states) \ 457 m(+1, u64, time_to_first_perst, "time_to_first_perst", \ 458 "Time form start until FW handle first perst. in usec.", \ 459 pcie_timers_states) \ 460 m(+1, u64, time_to_detect_state, "time_to_detect_state", \ 461 "Time from start until first transition to LTSSM.Detect_Q in usec", \ 462 pcie_timers_states) \ 463 m(+1, u64, time_to_l0, "time_to_l0", \ 464 "Time from start until first transition to LTSSM.L0 in usec", \ 465 pcie_timers_states) \ 466 m(+1, u64, time_to_crs_en, "time_to_crs_en", \ 467 "Time from start until crs is enabled in usec", \ 468 pcie_timers_states) \ 469 m(+1, u64, time_to_plastic_image_start, "time_to_plastic_image_start",\ 470 "Time form start until FW plastic image starts running in usec.", \ 471 pcie_timers_states) \ 472 m(+1, u64, time_to_iron_image_start, "time_to_iron_image_start", \ 473 "Time form start until FW iron image starts running in usec.", \ 474 pcie_timers_states) \ 475 m(+1, u64, perst_handler, "perst_handler", \ 476 "Number of persts arrived.", pcie_timers_states) \ 477 m(+1, u64, times_in_l1, "times_in_l1", \ 478 "Number of times LTSSM entered L1 flow.", pcie_timers_states) \ 479 m(+1, u64, times_in_l23, "times_in_l23", \ 480 "Number of times LTSSM entered L23 flow.", pcie_timers_states) \ 481 m(+1, u64, dl_down, "dl_down", \ 482 "Number of moves for DL_active to DL_down.", pcie_timers_states) \ 483 m(+1, u64, config_cycle1usec, "config_cycle1usec", \ 484 "Number of configuration requests that firmware " \ 485 "handled in less than 1 usec.", pcie_timers_states) \ 486 m(+1, u64, config_cycle2to7usec, "config_cycle2to7usec", \ 487 "Number of configuration requests that firmware " \ 488 "handled within 2 to 7 usec.", pcie_timers_states) \ 489 m(+1, u64, config_cycle8to15usec, "config_cycle8to15usec", \ 490 "Number of configuration requests that firmware " \ 491 "handled within 8 to 15 usec.", pcie_timers_states) \ 492 m(+1, u64, config_cycle16to63usec, "config_cycle16to63usec", \ 493 "Number of configuration requests that firmware " \ 494 "handled within 16 to 63 usec.", pcie_timers_states) \ 495 m(+1, u64, config_cycle64usec, "config_cycle64usec", \ 496 "Number of configuration requests that firmware " \ 497 "handled took more than 64 usec.", pcie_timers_states) \ 498 m(+1, u64, correctable_err_msg_sent, "correctable_err_msg_sent", \ 499 "Number of correctable error messages sent.", pcie_timers_states) \ 500 m(+1, u64, non_fatal_err_msg_sent, "non_fatal_err_msg_sent", \ 501 "Number of non-Fatal error msg sent.", pcie_timers_states) \ 502 m(+1, u64, fatal_err_msg_sent, "fatal_err_msg_sent", \ 503 "Number of fatal error msg sent.", pcie_timers_states) 504 505#define MLX5E_PCIE_LANE_COUNTERS_32(m) \ 506 m(+1, u64, error_counter_lane0, "error_counter_lane0", \ 507 "Error counter for PCI lane 0", pcie_lanes_counters) \ 508 m(+1, u64, error_counter_lane1, "error_counter_lane1", \ 509 "Error counter for PCI lane 1", pcie_lanes_counters) \ 510 m(+1, u64, error_counter_lane2, "error_counter_lane2", \ 511 "Error counter for PCI lane 2", pcie_lanes_counters) \ 512 m(+1, u64, error_counter_lane3, "error_counter_lane3", \ 513 "Error counter for PCI lane 3", pcie_lanes_counters) \ 514 m(+1, u64, error_counter_lane4, "error_counter_lane4", \ 515 "Error counter for PCI lane 4", pcie_lanes_counters) \ 516 m(+1, u64, error_counter_lane5, "error_counter_lane5", \ 517 "Error counter for PCI lane 5", pcie_lanes_counters) \ 518 m(+1, u64, error_counter_lane6, "error_counter_lane6", \ 519 "Error counter for PCI lane 6", pcie_lanes_counters) \ 520 m(+1, u64, error_counter_lane7, "error_counter_lane7", \ 521 "Error counter for PCI lane 7", pcie_lanes_counters) \ 522 m(+1, u64, error_counter_lane8, "error_counter_lane8", \ 523 "Error counter for PCI lane 8", pcie_lanes_counters) \ 524 m(+1, u64, error_counter_lane9, "error_counter_lane9", \ 525 "Error counter for PCI lane 9", pcie_lanes_counters) \ 526 m(+1, u64, error_counter_lane10, "error_counter_lane10", \ 527 "Error counter for PCI lane 10", pcie_lanes_counters) \ 528 m(+1, u64, error_counter_lane11, "error_counter_lane11", \ 529 "Error counter for PCI lane 11", pcie_lanes_counters) \ 530 m(+1, u64, error_counter_lane12, "error_counter_lane12", \ 531 "Error counter for PCI lane 12", pcie_lanes_counters) \ 532 m(+1, u64, error_counter_lane13, "error_counter_lane13", \ 533 "Error counter for PCI lane 13", pcie_lanes_counters) \ 534 m(+1, u64, error_counter_lane14, "error_counter_lane14", \ 535 "Error counter for PCI lane 14", pcie_lanes_counters) \ 536 m(+1, u64, error_counter_lane15, "error_counter_lane15", \ 537 "Error counter for PCI lane 15", pcie_lanes_counters) 538 539/* 540 * Make sure to update mlx5e_update_pport_counters() 541 * when adding a new MLX5E_PPORT_STATS block 542 */ 543#define MLX5E_PPORT_STATS(m) \ 544 MLX5E_PPORT_PER_PRIO_STATS(m) \ 545 MLX5E_PPORT_IEEE802_3_STATS(m) \ 546 MLX5E_PPORT_RFC2819_STATS(m) 547 548#define MLX5E_PORT_STATS_DEBUG(m) \ 549 MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 550 MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 551 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \ 552 MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(m) \ 553 MLX5E_PPORT_STATISTICAL_DEBUG(m) \ 554 MLX5E_PCIE_PERFORMANCE_COUNTERS_64(m) \ 555 MLX5E_PCIE_PERFORMANCE_COUNTERS_32(m) \ 556 MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(m) \ 557 MLX5E_PCIE_LANE_COUNTERS_32(m) 558 559#define MLX5E_PPORT_IEEE802_3_STATS_NUM \ 560 (0 MLX5E_PPORT_IEEE802_3_STATS(MLX5E_STATS_COUNT)) 561#define MLX5E_PPORT_RFC2819_STATS_NUM \ 562 (0 MLX5E_PPORT_RFC2819_STATS(MLX5E_STATS_COUNT)) 563#define MLX5E_PPORT_STATS_NUM \ 564 (0 MLX5E_PPORT_STATS(MLX5E_STATS_COUNT)) 565 566#define MLX5E_PPORT_PER_PRIO_STATS_NUM \ 567 (0 MLX5E_PPORT_PER_PRIO_STATS(MLX5E_STATS_COUNT)) 568#define MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM \ 569 (0 MLX5E_PPORT_RFC2819_STATS_DEBUG(MLX5E_STATS_COUNT)) 570#define MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM \ 571 (0 MLX5E_PPORT_RFC2863_STATS_DEBUG(MLX5E_STATS_COUNT)) 572#define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM \ 573 (0 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(MLX5E_STATS_COUNT)) 574#define MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM \ 575 (0 MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(MLX5E_STATS_COUNT)) 576#define MLX5E_PPORT_STATISTICAL_DEBUG_NUM \ 577 (0 MLX5E_PPORT_STATISTICAL_DEBUG(MLX5E_STATS_COUNT)) 578#define MLX5E_PORT_STATS_DEBUG_NUM \ 579 (0 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_COUNT)) 580 581struct mlx5e_pport_stats { 582 struct sysctl_ctx_list ctx; 583 u64 arg [0]; 584 MLX5E_PPORT_STATS(MLX5E_STATS_VAR) 585}; 586 587struct mlx5e_port_stats_debug { 588 struct sysctl_ctx_list ctx; 589 u64 arg [0]; 590 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_VAR) 591}; 592 593#define MLX5E_RQ_STATS(m) \ 594 m(+1, u64, packets, "packets", "Received packets") \ 595 m(+1, u64, bytes, "bytes", "Received bytes") \ 596 m(+1, u64, csum_none, "csum_none", "Received packets") \ 597 m(+1, u64, lro_packets, "lro_packets", "Received LRO packets") \ 598 m(+1, u64, lro_bytes, "lro_bytes", "Received LRO bytes") \ 599 m(+1, u64, sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 600 m(+1, u64, sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 601 m(+1, u64, wqe_err, "wqe_err", "Received packets") 602 603#define MLX5E_RQ_STATS_NUM (0 MLX5E_RQ_STATS(MLX5E_STATS_COUNT)) 604 605struct mlx5e_rq_stats { 606 struct sysctl_ctx_list ctx; 607 u64 arg [0]; 608 MLX5E_RQ_STATS(MLX5E_STATS_VAR) 609}; 610 611#define MLX5E_SQ_STATS(m) \ 612 m(+1, u64, packets, "packets", "Transmitted packets") \ 613 m(+1, u64, bytes, "bytes", "Transmitted bytes") \ 614 m(+1, u64, tso_packets, "tso_packets", "Transmitted packets") \ 615 m(+1, u64, tso_bytes, "tso_bytes", "Transmitted bytes") \ 616 m(+1, u64, csum_offload_none, "csum_offload_none", "Transmitted packets") \ 617 m(+1, u64, defragged, "defragged", "Transmitted packets") \ 618 m(+1, u64, dropped, "dropped", "Transmitted packets") \ 619 m(+1, u64, nop, "nop", "Transmitted packets") 620 621#define MLX5E_SQ_STATS_NUM (0 MLX5E_SQ_STATS(MLX5E_STATS_COUNT)) 622 623struct mlx5e_sq_stats { 624 struct sysctl_ctx_list ctx; 625 u64 arg [0]; 626 MLX5E_SQ_STATS(MLX5E_STATS_VAR) 627}; 628 629struct mlx5e_stats { 630 struct mlx5e_vport_stats vport; 631 struct mlx5e_pport_stats pport; 632 struct mlx5e_port_stats_debug port_stats_debug; 633}; 634 635struct mlx5e_rq_param { 636 u32 rqc [MLX5_ST_SZ_DW(rqc)]; 637 struct mlx5_wq_param wq; 638}; 639 640struct mlx5e_sq_param { 641 u32 sqc [MLX5_ST_SZ_DW(sqc)]; 642 struct mlx5_wq_param wq; 643}; 644 645struct mlx5e_cq_param { 646 u32 cqc [MLX5_ST_SZ_DW(cqc)]; 647 struct mlx5_wq_param wq; 648}; 649 650struct mlx5e_params { 651 u8 log_sq_size; 652 u8 log_rq_size; 653 u16 num_channels; 654 u8 default_vlan_prio; 655 u8 num_tc; 656 u8 rx_cq_moderation_mode; 657 u8 tx_cq_moderation_mode; 658 u16 rx_cq_moderation_usec; 659 u16 rx_cq_moderation_pkts; 660 u16 tx_cq_moderation_usec; 661 u16 tx_cq_moderation_pkts; 662 u16 min_rx_wqes; 663 bool hw_lro_en; 664 bool cqe_zipping_en; 665 u32 lro_wqe_sz; 666 u16 rx_hash_log_tbl_sz; 667 u32 tx_pauseframe_control __aligned(4); 668 u32 rx_pauseframe_control __aligned(4); 669 u16 tx_max_inline; 670 u8 tx_min_inline_mode; 671 u8 tx_priority_flow_control; 672 u8 rx_priority_flow_control; 673 u8 channels_rsss; 674}; 675 676#define MLX5E_PARAMS(m) \ 677 m(+1, u64, tx_queue_size_max, "tx_queue_size_max", "Max send queue size") \ 678 m(+1, u64, rx_queue_size_max, "rx_queue_size_max", "Max receive queue size") \ 679 m(+1, u64, tx_queue_size, "tx_queue_size", "Default send queue size") \ 680 m(+1, u64, rx_queue_size, "rx_queue_size", "Default receive queue size") \ 681 m(+1, u64, channels, "channels", "Default number of channels") \ 682 m(+1, u64, channels_rsss, "channels_rsss", "Default channels receive side scaling stride") \ 683 m(+1, u64, coalesce_usecs_max, "coalesce_usecs_max", "Maximum usecs for joining packets") \ 684 m(+1, u64, coalesce_pkts_max, "coalesce_pkts_max", "Maximum packets to join") \ 685 m(+1, u64, rx_coalesce_usecs, "rx_coalesce_usecs", "Limit in usec for joining rx packets") \ 686 m(+1, u64, rx_coalesce_pkts, "rx_coalesce_pkts", "Maximum number of rx packets to join") \ 687 m(+1, u64, rx_coalesce_mode, "rx_coalesce_mode", "0: EQE fixed mode 1: CQE fixed mode 2: EQE auto mode 3: CQE auto mode") \ 688 m(+1, u64, tx_coalesce_usecs, "tx_coalesce_usecs", "Limit in usec for joining tx packets") \ 689 m(+1, u64, tx_coalesce_pkts, "tx_coalesce_pkts", "Maximum number of tx packets to join") \ 690 m(+1, u64, tx_coalesce_mode, "tx_coalesce_mode", "0: EQE mode 1: CQE mode") \ 691 m(+1, u64, tx_completion_fact, "tx_completion_fact", "1..MAX: Completion event ratio") \ 692 m(+1, u64, tx_completion_fact_max, "tx_completion_fact_max", "Maximum completion event ratio") \ 693 m(+1, u64, hw_lro, "hw_lro", "set to enable hw_lro") \ 694 m(+1, u64, cqe_zipping, "cqe_zipping", "0 : CQE zipping disabled") \ 695 m(+1, u64, modify_tx_dma, "modify_tx_dma", "0: Enable TX 1: Disable TX") \ 696 m(+1, u64, modify_rx_dma, "modify_rx_dma", "0: Enable RX 1: Disable RX") \ 697 m(+1, u64, diag_pci_enable, "diag_pci_enable", "0: Disabled 1: Enabled") \ 698 m(+1, u64, diag_general_enable, "diag_general_enable", "0: Disabled 1: Enabled") \ 699 m(+1, u64, hw_mtu, "hw_mtu", "Current hardware MTU value") \ 700 m(+1, u64, mc_local_lb, "mc_local_lb", "0: Local multicast loopback enabled 1: Disabled") \ 701 m(+1, u64, uc_local_lb, "uc_local_lb", "0: Local unicast loopback enabled 1: Disabled") 702 703#define MLX5E_PARAMS_NUM (0 MLX5E_PARAMS(MLX5E_STATS_COUNT)) 704 705struct mlx5e_params_ethtool { 706 u64 arg [0]; 707 MLX5E_PARAMS(MLX5E_STATS_VAR) 708 u64 max_bw_value[IEEE_8021QAZ_MAX_TCS]; 709 u8 max_bw_share[IEEE_8021QAZ_MAX_TCS]; 710 u8 prio_tc[MLX5E_MAX_PRIORITY]; 711 u8 dscp2prio[MLX5_MAX_SUPPORTED_DSCP]; 712 u8 trust_state; 713}; 714 715/* EEPROM Standards for plug in modules */ 716#ifndef MLX5E_ETH_MODULE_SFF_8472 717#define MLX5E_ETH_MODULE_SFF_8472 0x1 718#define MLX5E_ETH_MODULE_SFF_8472_LEN 128 719#endif 720 721#ifndef MLX5E_ETH_MODULE_SFF_8636 722#define MLX5E_ETH_MODULE_SFF_8636 0x2 723#define MLX5E_ETH_MODULE_SFF_8636_LEN 256 724#endif 725 726#ifndef MLX5E_ETH_MODULE_SFF_8436 727#define MLX5E_ETH_MODULE_SFF_8436 0x3 728#define MLX5E_ETH_MODULE_SFF_8436_LEN 256 729#endif 730 731/* EEPROM I2C Addresses */ 732#define MLX5E_I2C_ADDR_LOW 0x50 733#define MLX5E_I2C_ADDR_HIGH 0x51 734 735#define MLX5E_EEPROM_LOW_PAGE 0x0 736#define MLX5E_EEPROM_HIGH_PAGE 0x3 737 738#define MLX5E_EEPROM_HIGH_PAGE_OFFSET 128 739#define MLX5E_EEPROM_PAGE_LENGTH 256 740 741#define MLX5E_EEPROM_INFO_BYTES 0x3 742 743struct mlx5e_cq { 744 /* data path - accessed per cqe */ 745 struct mlx5_cqwq wq; 746 747 /* data path - accessed per HW polling */ 748 struct mlx5_core_cq mcq; 749 750 /* control */ 751 struct mlx5e_priv *priv; 752 struct mlx5_wq_ctrl wq_ctrl; 753} __aligned(MLX5E_CACHELINE_SIZE); 754 755struct mlx5e_rq_mbuf { 756 bus_dmamap_t dma_map; 757 caddr_t data; 758 struct mbuf *mbuf; 759}; 760 761struct mlx5e_rq { 762 /* data path */ 763 struct mlx5_wq_ll wq; 764 struct mtx mtx; 765 bus_dma_tag_t dma_tag; 766 u32 wqe_sz; 767 u32 nsegs; 768 struct mlx5e_rq_mbuf *mbuf; 769 struct ifnet *ifp; 770 struct mlx5e_rq_stats stats; 771 struct mlx5e_cq cq; 772 struct lro_ctrl lro; 773 volatile int enabled; 774 int ix; 775 776 /* Dynamic Interrupt Moderation */ 777 struct net_dim dim; 778 779 /* control */ 780 struct mlx5_wq_ctrl wq_ctrl; 781 u32 rqn; 782 struct mlx5e_channel *channel; 783 struct callout watchdog; 784} __aligned(MLX5E_CACHELINE_SIZE); 785 786struct mlx5e_sq_mbuf { 787 bus_dmamap_t dma_map; 788 struct mbuf *mbuf; 789 u32 num_bytes; 790 u32 num_wqebbs; 791}; 792 793enum { 794 MLX5E_SQ_READY, 795 MLX5E_SQ_FULL 796}; 797 798struct mlx5e_sq { 799 /* data path */ 800 struct mtx lock; 801 bus_dma_tag_t dma_tag; 802 struct mtx comp_lock; 803 804 /* dirtied @completion */ 805 u16 cc; 806 807 /* dirtied @xmit */ 808 u16 pc __aligned(MLX5E_CACHELINE_SIZE); 809 u16 bf_offset; 810 u16 cev_counter; /* completion event counter */ 811 u16 cev_factor; /* completion event factor */ 812 u16 cev_next_state; /* next completion event state */ 813#define MLX5E_CEV_STATE_INITIAL 0 /* timer not started */ 814#define MLX5E_CEV_STATE_SEND_NOPS 1 /* send NOPs */ 815#define MLX5E_CEV_STATE_HOLD_NOPS 2 /* don't send NOPs yet */ 816 u16 running; /* set if SQ is running */ 817 struct callout cev_callout; 818 union { 819 u32 d32[2]; 820 u64 d64; 821 } doorbell; 822 struct mlx5e_sq_stats stats; 823 824 struct mlx5e_cq cq; 825 826 /* pointers to per packet info: write@xmit, read@completion */ 827 struct mlx5e_sq_mbuf *mbuf; 828 struct buf_ring *br; 829 830 /* read only */ 831 struct mlx5_wq_cyc wq; 832 struct mlx5_uar uar; 833 struct ifnet *ifp; 834 u32 sqn; 835 u32 bf_buf_size; 836 u32 mkey_be; 837 u16 max_inline; 838 u8 min_inline_mode; 839 u8 min_insert_caps; 840#define MLX5E_INSERT_VLAN 1 841#define MLX5E_INSERT_NON_VLAN 2 842 843 /* control path */ 844 struct mlx5_wq_ctrl wq_ctrl; 845 struct mlx5e_priv *priv; 846 int tc; 847} __aligned(MLX5E_CACHELINE_SIZE); 848 849static inline bool 850mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) 851{ 852 u16 cc = sq->cc; 853 u16 pc = sq->pc; 854 855 return ((sq->wq.sz_m1 & (cc - pc)) >= n || cc == pc); 856} 857 858struct mlx5e_channel { 859 /* data path */ 860 struct mlx5e_rq rq; 861 struct mlx5e_sq sq[MLX5E_MAX_TX_NUM_TC]; 862 struct ifnet *ifp; 863 u32 mkey_be; 864 u8 num_tc; 865 866 /* control */ 867 struct mlx5e_priv *priv; 868 int ix; 869 int cpu; 870} __aligned(MLX5E_CACHELINE_SIZE); 871 872enum mlx5e_traffic_types { 873 MLX5E_TT_IPV4_TCP, 874 MLX5E_TT_IPV6_TCP, 875 MLX5E_TT_IPV4_UDP, 876 MLX5E_TT_IPV6_UDP, 877 MLX5E_TT_IPV4_IPSEC_AH, 878 MLX5E_TT_IPV6_IPSEC_AH, 879 MLX5E_TT_IPV4_IPSEC_ESP, 880 MLX5E_TT_IPV6_IPSEC_ESP, 881 MLX5E_TT_IPV4, 882 MLX5E_TT_IPV6, 883 MLX5E_TT_ANY, 884 MLX5E_NUM_TT, 885}; 886 887enum { 888 MLX5E_RQT_SPREADING = 0, 889 MLX5E_RQT_DEFAULT_RQ = 1, 890 MLX5E_NUM_RQT = 2, 891}; 892 893struct mlx5_flow_rule; 894 895struct mlx5e_eth_addr_info { 896 u8 addr [ETH_ALEN + 2]; 897 u32 tt_vec; 898 /* flow table rule per traffic type */ 899 struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT]; 900}; 901 902#define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE) 903 904struct mlx5e_eth_addr_hash_node; 905 906struct mlx5e_eth_addr_hash_head { 907 struct mlx5e_eth_addr_hash_node *lh_first; 908}; 909 910struct mlx5e_eth_addr_db { 911 struct mlx5e_eth_addr_hash_head if_uc[MLX5E_ETH_ADDR_HASH_SIZE]; 912 struct mlx5e_eth_addr_hash_head if_mc[MLX5E_ETH_ADDR_HASH_SIZE]; 913 struct mlx5e_eth_addr_info broadcast; 914 struct mlx5e_eth_addr_info allmulti; 915 struct mlx5e_eth_addr_info promisc; 916 bool broadcast_enabled; 917 bool allmulti_enabled; 918 bool promisc_enabled; 919}; 920 921enum { 922 MLX5E_STATE_ASYNC_EVENTS_ENABLE, 923 MLX5E_STATE_OPENED, 924}; 925 926enum { 927 MLX5_BW_NO_LIMIT = 0, 928 MLX5_100_MBPS_UNIT = 3, 929 MLX5_GBPS_UNIT = 4, 930}; 931 932struct mlx5e_vlan_db { 933 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 934 struct mlx5_flow_rule *active_vlans_ft_rule[VLAN_N_VID]; 935 struct mlx5_flow_rule *untagged_ft_rule; 936 struct mlx5_flow_rule *any_cvlan_ft_rule; 937 struct mlx5_flow_rule *any_svlan_ft_rule; 938 bool filter_disabled; 939}; 940 941struct mlx5e_flow_table { 942 int num_groups; 943 struct mlx5_flow_table *t; 944 struct mlx5_flow_group **g; 945}; 946 947struct mlx5e_flow_tables { 948 struct mlx5_flow_namespace *ns; 949 struct mlx5e_flow_table vlan; 950 struct mlx5e_flow_table main; 951 struct mlx5e_flow_table inner_rss; 952}; 953 954struct mlx5e_priv { 955 struct mlx5_core_dev *mdev; /* must be first */ 956 957 /* priv data path fields - start */ 958 int order_base_2_num_channels; 959 int queue_mapping_channel_mask; 960 int num_tc; 961 int default_vlan_prio; 962 /* priv data path fields - end */ 963 964 unsigned long state; 965 int gone; 966#define PRIV_LOCK(priv) sx_xlock(&(priv)->state_lock) 967#define PRIV_UNLOCK(priv) sx_xunlock(&(priv)->state_lock) 968#define PRIV_LOCKED(priv) sx_xlocked(&(priv)->state_lock) 969#define PRIV_ASSERT_LOCKED(priv) sx_assert(&(priv)->state_lock, SA_XLOCKED) 970 struct sx state_lock; /* Protects Interface state */ 971 struct mlx5_uar cq_uar; 972 u32 pdn; 973 u32 tdn; 974 struct mlx5_core_mr mr; 975 976 u32 tisn[MLX5E_MAX_TX_NUM_TC]; 977 u32 rqtn; 978 u32 tirn[MLX5E_NUM_TT]; 979 980 struct mlx5e_flow_tables fts; 981 struct mlx5e_eth_addr_db eth_addr; 982 struct mlx5e_vlan_db vlan; 983 984 struct mlx5e_params params; 985 struct mlx5e_params_ethtool params_ethtool; 986 union mlx5_core_pci_diagnostics params_pci; 987 union mlx5_core_general_diagnostics params_general; 988 struct mtx async_events_mtx; /* sync hw events */ 989 struct work_struct update_stats_work; 990 struct work_struct update_carrier_work; 991 struct work_struct set_rx_mode_work; 992 MLX5_DECLARE_DOORBELL_LOCK(doorbell_lock) 993 994 struct ifnet *ifp; 995 struct sysctl_ctx_list sysctl_ctx; 996 struct sysctl_oid *sysctl_ifnet; 997 struct sysctl_oid *sysctl_hw; 998 int sysctl_debug; 999 struct mlx5e_stats stats; 1000 int counter_set_id; 1001 1002 struct workqueue_struct *wq; 1003 1004 eventhandler_tag vlan_detach; 1005 eventhandler_tag vlan_attach; 1006 struct ifmedia media; 1007 int media_status_last; 1008 int media_active_last; 1009 1010 struct callout watchdog; 1011 1012 struct mlx5e_channel channel[]; 1013}; 1014 1015#define MLX5E_NET_IP_ALIGN 2 1016 1017struct mlx5e_tx_wqe { 1018 struct mlx5_wqe_ctrl_seg ctrl; 1019 struct mlx5_wqe_eth_seg eth; 1020}; 1021 1022struct mlx5e_rx_wqe { 1023 struct mlx5_wqe_srq_next_seg next; 1024 struct mlx5_wqe_data_seg data[]; 1025}; 1026 1027/* the size of the structure above must be power of two */ 1028CTASSERT(powerof2(sizeof(struct mlx5e_rx_wqe))); 1029 1030struct mlx5e_eeprom { 1031 int lock_bit; 1032 int i2c_addr; 1033 int page_num; 1034 int device_addr; 1035 int module_num; 1036 int len; 1037 int type; 1038 int page_valid; 1039 u32 *data; 1040}; 1041 1042#define MLX5E_FLD_MAX(typ, fld) ((1ULL << __mlx5_bit_sz(typ, fld)) - 1ULL) 1043 1044int mlx5e_xmit(struct ifnet *, struct mbuf *); 1045 1046int mlx5e_open_locked(struct ifnet *); 1047int mlx5e_close_locked(struct ifnet *); 1048 1049void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, int event); 1050void mlx5e_rx_cq_comp(struct mlx5_core_cq *); 1051void mlx5e_tx_cq_comp(struct mlx5_core_cq *); 1052struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); 1053 1054void mlx5e_dim_work(struct work_struct *); 1055void mlx5e_dim_build_cq_param(struct mlx5e_priv *, struct mlx5e_cq_param *); 1056 1057int mlx5e_open_flow_table(struct mlx5e_priv *priv); 1058void mlx5e_close_flow_table(struct mlx5e_priv *priv); 1059void mlx5e_set_rx_mode_core(struct mlx5e_priv *priv); 1060void mlx5e_set_rx_mode_work(struct work_struct *work); 1061 1062void mlx5e_vlan_rx_add_vid(void *, struct ifnet *, u16); 1063void mlx5e_vlan_rx_kill_vid(void *, struct ifnet *, u16); 1064void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); 1065void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); 1066int mlx5e_add_all_vlan_rules(struct mlx5e_priv *priv); 1067void mlx5e_del_all_vlan_rules(struct mlx5e_priv *priv); 1068 1069static inline void 1070mlx5e_tx_notify_hw(struct mlx5e_sq *sq, u32 *wqe, int bf_sz) 1071{ 1072 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; 1073 1074 /* ensure wqe is visible to device before updating doorbell record */ 1075 wmb(); 1076 1077 *sq->wq.db = cpu_to_be32(sq->pc); 1078 1079 /* 1080 * Ensure the doorbell record is visible to device before ringing 1081 * the doorbell: 1082 */ 1083 wmb(); 1084 1085 if (bf_sz) { 1086 __iowrite64_copy(sq->uar.bf_map + ofst, wqe, bf_sz); 1087 1088 /* flush the write-combining mapped buffer */ 1089 wmb(); 1090 1091 } else { 1092 mlx5_write64(wqe, sq->uar.map + ofst, 1093 MLX5_GET_DOORBELL_LOCK(&sq->priv->doorbell_lock)); 1094 } 1095 1096 sq->bf_offset ^= sq->bf_buf_size; 1097} 1098 1099static inline void 1100mlx5e_cq_arm(struct mlx5e_cq *cq, spinlock_t *dblock) 1101{ 1102 struct mlx5_core_cq *mcq; 1103 1104 mcq = &cq->mcq; 1105 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, dblock, cq->wq.cc); 1106} 1107 1108extern const struct ethtool_ops mlx5e_ethtool_ops; 1109void mlx5e_create_ethtool(struct mlx5e_priv *); 1110void mlx5e_create_stats(struct sysctl_ctx_list *, 1111 struct sysctl_oid_list *, const char *, 1112 const char **, unsigned, u64 *); 1113void mlx5e_send_nop(struct mlx5e_sq *, u32); 1114void mlx5e_sq_cev_timeout(void *); 1115int mlx5e_refresh_channel_params(struct mlx5e_priv *); 1116int mlx5e_open_cq(struct mlx5e_priv *, struct mlx5e_cq_param *, 1117 struct mlx5e_cq *, mlx5e_cq_comp_t *, int eq_ix); 1118void mlx5e_close_cq(struct mlx5e_cq *); 1119void mlx5e_free_sq_db(struct mlx5e_sq *); 1120int mlx5e_alloc_sq_db(struct mlx5e_sq *); 1121int mlx5e_enable_sq(struct mlx5e_sq *, struct mlx5e_sq_param *, int tis_num); 1122int mlx5e_modify_sq(struct mlx5e_sq *, int curr_state, int next_state); 1123void mlx5e_disable_sq(struct mlx5e_sq *); 1124void mlx5e_drain_sq(struct mlx5e_sq *); 1125void mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value); 1126void mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value); 1127void mlx5e_resume_sq(struct mlx5e_sq *sq); 1128void mlx5e_update_sq_inline(struct mlx5e_sq *sq); 1129void mlx5e_refresh_sq_inline(struct mlx5e_priv *priv); 1130 1131#endif /* _MLX5_EN_H_ */ 1132