en.h revision 347872
1/*- 2 * Copyright (c) 2015-2019 Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_en/en.h 347872 2019-05-16 18:22:46Z hselasky $ 26 */ 27 28#ifndef _MLX5_EN_H_ 29#define _MLX5_EN_H_ 30 31#include <linux/kmod.h> 32#include <linux/page.h> 33#include <linux/slab.h> 34#include <linux/if_vlan.h> 35#include <linux/if_ether.h> 36#include <linux/vmalloc.h> 37#include <linux/moduleparam.h> 38#include <linux/delay.h> 39#include <linux/netdevice.h> 40#include <linux/etherdevice.h> 41#include <linux/ktime.h> 42#include <linux/net_dim.h> 43 44#include <netinet/in_systm.h> 45#include <netinet/in.h> 46#include <netinet/if_ether.h> 47#include <netinet/ip.h> 48#include <netinet/ip6.h> 49#include <netinet/tcp.h> 50#include <netinet/tcp_lro.h> 51#include <netinet/udp.h> 52#include <net/ethernet.h> 53#include <sys/buf_ring.h> 54 55#include "opt_rss.h" 56 57#ifdef RSS 58#include <net/rss_config.h> 59#include <netinet/in_rss.h> 60#endif 61 62#include <machine/bus.h> 63 64#include <dev/mlx5/driver.h> 65#include <dev/mlx5/qp.h> 66#include <dev/mlx5/cq.h> 67#include <dev/mlx5/port.h> 68#include <dev/mlx5/vport.h> 69#include <dev/mlx5/diagnostics.h> 70 71#include <dev/mlx5/mlx5_core/wq.h> 72#include <dev/mlx5/mlx5_core/transobj.h> 73#include <dev/mlx5/mlx5_core/mlx5_core.h> 74 75#define MLX5E_MAX_PRIORITY 8 76 77/* IEEE 802.1Qaz standard supported values */ 78#define IEEE_8021QAZ_MAX_TCS 8 79 80#define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x7 81#define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa 82#define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xe 83 84#define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x7 85#define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa 86#define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xe 87 88#define MLX5E_MAX_BUSDMA_RX_SEGS 15 89 90#define MLX5E_MAX_RX_SEGS 7 91 92#ifndef MLX5E_MAX_RX_BYTES 93#define MLX5E_MAX_RX_BYTES MCLBYTES 94#endif 95 96#if (MLX5E_MAX_RX_SEGS == 1) 97/* FreeBSD HW LRO is limited by 16KB - the size of max mbuf */ 98#define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ MJUM16BYTES 99#else 100#define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ \ 101 MIN(65535, MLX5E_MAX_RX_SEGS * MLX5E_MAX_RX_BYTES) 102#endif 103#define MLX5E_DIM_DEFAULT_PROFILE 3 104#define MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO 16 105#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 106#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 107#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 108#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 109#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 110#define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 111#define MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ 0x7 112#define MLX5E_CACHELINE_SIZE CACHE_LINE_SIZE 113#define MLX5E_HW2SW_MTU(hwmtu) \ 114 ((hwmtu) - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 115#define MLX5E_SW2HW_MTU(swmtu) \ 116 ((swmtu) + (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 117#define MLX5E_SW2MB_MTU(swmtu) \ 118 (MLX5E_SW2HW_MTU(swmtu) + MLX5E_NET_IP_ALIGN) 119#define MLX5E_MTU_MIN 72 /* Min MTU allowed by the kernel */ 120#define MLX5E_MTU_MAX MIN(ETHERMTU_JUMBO, MJUM16BYTES) /* Max MTU of Ethernet 121 * jumbo frames */ 122 123#define MLX5E_BUDGET_MAX 8192 /* RX and TX */ 124#define MLX5E_RX_BUDGET_MAX 256 125#define MLX5E_SQ_BF_BUDGET 16 126#define MLX5E_SQ_TX_QUEUE_SIZE 4096 /* SQ drbr queue size */ 127 128#define MLX5E_MAX_TX_NUM_TC 8 /* units */ 129#define MLX5E_MAX_TX_HEADER 128 /* bytes */ 130#define MLX5E_MAX_TX_PAYLOAD_SIZE 65536 /* bytes */ 131#define MLX5E_MAX_TX_MBUF_SIZE 65536 /* bytes */ 132#define MLX5E_MAX_TX_MBUF_FRAGS \ 133 ((MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS) - \ 134 (MLX5E_MAX_TX_HEADER / MLX5_SEND_WQE_DS) - \ 135 1 /* the maximum value of the DS counter is 0x3F and not 0x40 */) /* units */ 136#define MLX5E_MAX_TX_INLINE \ 137 (MLX5E_MAX_TX_HEADER - sizeof(struct mlx5e_tx_wqe) + \ 138 sizeof(((struct mlx5e_tx_wqe *)0)->eth.inline_hdr_start)) /* bytes */ 139 140#define MLX5E_100MB (100000) 141#define MLX5E_1GB (1000000) 142 143MALLOC_DECLARE(M_MLX5EN); 144 145struct mlx5_core_dev; 146struct mlx5e_cq; 147 148typedef void (mlx5e_cq_comp_t)(struct mlx5_core_cq *); 149 150#define MLX5E_STATS_COUNT(a, ...) a 151#define MLX5E_STATS_VAR(a, b, c, ...) b c; 152#define MLX5E_STATS_DESC(a, b, c, d, e, ...) d, e, 153 154#define MLX5E_VPORT_STATS(m) \ 155 /* HW counters */ \ 156 m(+1, u64, rx_packets, "rx_packets", "Received packets") \ 157 m(+1, u64, rx_bytes, "rx_bytes", "Received bytes") \ 158 m(+1, u64, tx_packets, "tx_packets", "Transmitted packets") \ 159 m(+1, u64, tx_bytes, "tx_bytes", "Transmitted bytes") \ 160 m(+1, u64, rx_error_packets, "rx_error_packets", "Received error packets") \ 161 m(+1, u64, rx_error_bytes, "rx_error_bytes", "Received error bytes") \ 162 m(+1, u64, tx_error_packets, "tx_error_packets", "Transmitted error packets") \ 163 m(+1, u64, tx_error_bytes, "tx_error_bytes", "Transmitted error bytes") \ 164 m(+1, u64, rx_unicast_packets, "rx_unicast_packets", "Received unicast packets") \ 165 m(+1, u64, rx_unicast_bytes, "rx_unicast_bytes", "Received unicast bytes") \ 166 m(+1, u64, tx_unicast_packets, "tx_unicast_packets", "Transmitted unicast packets") \ 167 m(+1, u64, tx_unicast_bytes, "tx_unicast_bytes", "Transmitted unicast bytes") \ 168 m(+1, u64, rx_multicast_packets, "rx_multicast_packets", "Received multicast packets") \ 169 m(+1, u64, rx_multicast_bytes, "rx_multicast_bytes", "Received multicast bytes") \ 170 m(+1, u64, tx_multicast_packets, "tx_multicast_packets", "Transmitted multicast packets") \ 171 m(+1, u64, tx_multicast_bytes, "tx_multicast_bytes", "Transmitted multicast bytes") \ 172 m(+1, u64, rx_broadcast_packets, "rx_broadcast_packets", "Received broadcast packets") \ 173 m(+1, u64, rx_broadcast_bytes, "rx_broadcast_bytes", "Received broadcast bytes") \ 174 m(+1, u64, tx_broadcast_packets, "tx_broadcast_packets", "Transmitted broadcast packets") \ 175 m(+1, u64, tx_broadcast_bytes, "tx_broadcast_bytes", "Transmitted broadcast bytes") \ 176 m(+1, u64, rx_out_of_buffer, "rx_out_of_buffer", "Receive out of buffer, no recv wqes events") \ 177 /* SW counters */ \ 178 m(+1, u64, tso_packets, "tso_packets", "Transmitted TSO packets") \ 179 m(+1, u64, tso_bytes, "tso_bytes", "Transmitted TSO bytes") \ 180 m(+1, u64, lro_packets, "lro_packets", "Received LRO packets") \ 181 m(+1, u64, lro_bytes, "lro_bytes", "Received LRO bytes") \ 182 m(+1, u64, sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 183 m(+1, u64, sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 184 m(+1, u64, rx_csum_good, "rx_csum_good", "Received checksum valid packets") \ 185 m(+1, u64, rx_csum_none, "rx_csum_none", "Received no checksum packets") \ 186 m(+1, u64, tx_csum_offload, "tx_csum_offload", "Transmit checksum offload packets") \ 187 m(+1, u64, tx_queue_dropped, "tx_queue_dropped", "Transmit queue dropped") \ 188 m(+1, u64, tx_defragged, "tx_defragged", "Transmit queue defragged") \ 189 m(+1, u64, rx_wqe_err, "rx_wqe_err", "Receive WQE errors") \ 190 m(+1, u64, tx_jumbo_packets, "tx_jumbo_packets", "TX packets greater than 1518 octets") \ 191 m(+1, u64, rx_steer_missed_packets, "rx_steer_missed_packets", "RX packets dropped by steering rule(s)") 192 193#define MLX5E_VPORT_STATS_NUM (0 MLX5E_VPORT_STATS(MLX5E_STATS_COUNT)) 194 195struct mlx5e_vport_stats { 196 struct sysctl_ctx_list ctx; 197 u64 arg [0]; 198 MLX5E_VPORT_STATS(MLX5E_STATS_VAR) 199}; 200 201#define MLX5E_PPORT_IEEE802_3_STATS(m) \ 202 m(+1, u64, frames_tx, "frames_tx", "Frames transmitted") \ 203 m(+1, u64, frames_rx, "frames_rx", "Frames received") \ 204 m(+1, u64, check_seq_err, "check_seq_err", "Sequence errors") \ 205 m(+1, u64, alignment_err, "alignment_err", "Alignment errors") \ 206 m(+1, u64, octets_tx, "octets_tx", "Bytes transmitted") \ 207 m(+1, u64, octets_received, "octets_received", "Bytes received") \ 208 m(+1, u64, multicast_xmitted, "multicast_xmitted", "Multicast transmitted") \ 209 m(+1, u64, broadcast_xmitted, "broadcast_xmitted", "Broadcast transmitted") \ 210 m(+1, u64, multicast_rx, "multicast_rx", "Multicast received") \ 211 m(+1, u64, broadcast_rx, "broadcast_rx", "Broadcast received") \ 212 m(+1, u64, in_range_len_errors, "in_range_len_errors", "In range length errors") \ 213 m(+1, u64, out_of_range_len, "out_of_range_len", "Out of range length errors") \ 214 m(+1, u64, too_long_errors, "too_long_errors", "Too long errors") \ 215 m(+1, u64, symbol_err, "symbol_err", "Symbol errors") \ 216 m(+1, u64, mac_control_tx, "mac_control_tx", "MAC control transmitted") \ 217 m(+1, u64, mac_control_rx, "mac_control_rx", "MAC control received") \ 218 m(+1, u64, unsupported_op_rx, "unsupported_op_rx", "Unsupported operation received") \ 219 m(+1, u64, pause_ctrl_rx, "pause_ctrl_rx", "Pause control received") \ 220 m(+1, u64, pause_ctrl_tx, "pause_ctrl_tx", "Pause control transmitted") 221 222#define MLX5E_PPORT_RFC2819_STATS(m) \ 223 m(+1, u64, drop_events, "drop_events", "Dropped events") \ 224 m(+1, u64, octets, "octets", "Octets") \ 225 m(+1, u64, pkts, "pkts", "Packets") \ 226 m(+1, u64, broadcast_pkts, "broadcast_pkts", "Broadcast packets") \ 227 m(+1, u64, multicast_pkts, "multicast_pkts", "Multicast packets") \ 228 m(+1, u64, crc_align_errors, "crc_align_errors", "CRC alignment errors") \ 229 m(+1, u64, undersize_pkts, "undersize_pkts", "Undersized packets") \ 230 m(+1, u64, oversize_pkts, "oversize_pkts", "Oversized packets") \ 231 m(+1, u64, fragments, "fragments", "Fragments") \ 232 m(+1, u64, jabbers, "jabbers", "Jabbers") \ 233 m(+1, u64, collisions, "collisions", "Collisions") 234 235#define MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 236 m(+1, u64, p64octets, "p64octets", "Bytes") \ 237 m(+1, u64, p65to127octets, "p65to127octets", "Bytes") \ 238 m(+1, u64, p128to255octets, "p128to255octets", "Bytes") \ 239 m(+1, u64, p256to511octets, "p256to511octets", "Bytes") \ 240 m(+1, u64, p512to1023octets, "p512to1023octets", "Bytes") \ 241 m(+1, u64, p1024to1518octets, "p1024to1518octets", "Bytes") \ 242 m(+1, u64, p1519to2047octets, "p1519to2047octets", "Bytes") \ 243 m(+1, u64, p2048to4095octets, "p2048to4095octets", "Bytes") \ 244 m(+1, u64, p4096to8191octets, "p4096to8191octets", "Bytes") \ 245 m(+1, u64, p8192to10239octets, "p8192to10239octets", "Bytes") 246 247#define MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 248 m(+1, u64, in_octets, "in_octets", "In octets") \ 249 m(+1, u64, in_ucast_pkts, "in_ucast_pkts", "In unicast packets") \ 250 m(+1, u64, in_discards, "in_discards", "In discards") \ 251 m(+1, u64, in_errors, "in_errors", "In errors") \ 252 m(+1, u64, in_unknown_protos, "in_unknown_protos", "In unknown protocols") \ 253 m(+1, u64, out_octets, "out_octets", "Out octets") \ 254 m(+1, u64, out_ucast_pkts, "out_ucast_pkts", "Out unicast packets") \ 255 m(+1, u64, out_discards, "out_discards", "Out discards") \ 256 m(+1, u64, out_errors, "out_errors", "Out errors") \ 257 m(+1, u64, in_multicast_pkts, "in_multicast_pkts", "In multicast packets") \ 258 m(+1, u64, in_broadcast_pkts, "in_broadcast_pkts", "In broadcast packets") \ 259 m(+1, u64, out_multicast_pkts, "out_multicast_pkts", "Out multicast packets") \ 260 m(+1, u64, out_broadcast_pkts, "out_broadcast_pkts", "Out broadcast packets") 261 262#define MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(m) \ 263 m(+1, u64, port_transmit_wait_high, "port_transmit_wait_high", "Port transmit wait high") \ 264 m(+1, u64, ecn_marked, "ecn_marked", "ECN marked") \ 265 m(+1, u64, no_buffer_discard_mc, "no_buffer_discard_mc", "No buffer discard mc") \ 266 m(+1, u64, rx_ebp, "rx_ebp", "RX EBP") \ 267 m(+1, u64, tx_ebp, "tx_ebp", "TX EBP") \ 268 m(+1, u64, rx_buffer_almost_full, "rx_buffer_almost_full", "RX buffer almost full") \ 269 m(+1, u64, rx_buffer_full, "rx_buffer_full", "RX buffer full") \ 270 m(+1, u64, rx_icrc_encapsulated, "rx_icrc_encapsulated", "RX ICRC encapsulated") \ 271 m(+1, u64, ex_reserved_0, "ex_reserved_0", "Reserved") \ 272 m(+1, u64, ex_reserved_1, "ex_reserved_1", "Reserved") \ 273 m(+1, u64, tx_stat_p64octets, "tx_stat_p64octets", "Bytes") \ 274 m(+1, u64, tx_stat_p65to127octets, "tx_stat_p65to127octets", "Bytes") \ 275 m(+1, u64, tx_stat_p128to255octets, "tx_stat_p128to255octets", "Bytes") \ 276 m(+1, u64, tx_stat_p256to511octets, "tx_stat_p256to511octets", "Bytes") \ 277 m(+1, u64, tx_stat_p512to1023octets, "tx_stat_p512to1023octets", "Bytes") \ 278 m(+1, u64, tx_stat_p1024to1518octets, "tx_stat_p1024to1518octets", "Bytes") \ 279 m(+1, u64, tx_stat_p1519to2047octets, "tx_stat_p1519to2047octets", "Bytes") \ 280 m(+1, u64, tx_stat_p2048to4095octets, "tx_stat_p2048to4095octets", "Bytes") \ 281 m(+1, u64, tx_stat_p4096to8191octets, "tx_stat_p4096to8191octets", "Bytes") \ 282 m(+1, u64, tx_stat_p8192to10239octets, "tx_stat_p8192to10239octets", "Bytes") 283 284#define MLX5E_PPORT_STATISTICAL_DEBUG(m) \ 285 m(+1, u64, phy_time_since_last_clear, "phy_time_since_last_clear", \ 286 "Time since last clear in milliseconds") \ 287 m(+1, u64, phy_received_bits, "phy_received_bits", \ 288 "Total amount of traffic received in bits before error correction") \ 289 m(+1, u64, phy_symbol_errors, "phy_symbol_errors", \ 290 "Total number of symbol errors before error correction") \ 291 m(+1, u64, phy_corrected_bits, "phy_corrected_bits", \ 292 "Total number of corrected bits ") \ 293 m(+1, u64, phy_corrected_bits_lane0, "phy_corrected_bits_lane0", \ 294 "Total number of corrected bits for lane 0") \ 295 m(+1, u64, phy_corrected_bits_lane1, "phy_corrected_bits_lane1", \ 296 "Total number of corrected bits for lane 1") \ 297 m(+1, u64, phy_corrected_bits_lane2, "phy_corrected_bits_lane2", \ 298 "Total number of corrected bits for lane 2") \ 299 m(+1, u64, phy_corrected_bits_lane3, "phy_corrected_bits_lane3", \ 300 "Total number of corrected bits for lane 3") 301 302#define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \ 303 m(+1, u64, time_since_last_clear, "time_since_last_clear", \ 304 "Time since the last counters clear event (msec)") \ 305 m(+1, u64, symbol_errors, "symbol_errors", "Symbol errors") \ 306 m(+1, u64, sync_headers_errors, "sync_headers_errors", \ 307 "Sync header error counter") \ 308 m(+1, u64, bip_errors_lane0, "edpl_bip_errors_lane0", \ 309 "Indicates the number of PRBS errors on lane 0") \ 310 m(+1, u64, bip_errors_lane1, "edpl_bip_errors_lane1", \ 311 "Indicates the number of PRBS errors on lane 1") \ 312 m(+1, u64, bip_errors_lane2, "edpl_bip_errors_lane2", \ 313 "Indicates the number of PRBS errors on lane 2") \ 314 m(+1, u64, bip_errors_lane3, "edpl_bip_errors_lane3", \ 315 "Indicates the number of PRBS errors on lane 3") \ 316 m(+1, u64, fc_corrected_blocks_lane0, "fc_corrected_blocks_lane0", \ 317 "FEC correctable block counter lane 0") \ 318 m(+1, u64, fc_corrected_blocks_lane1, "fc_corrected_blocks_lane1", \ 319 "FEC correctable block counter lane 1") \ 320 m(+1, u64, fc_corrected_blocks_lane2, "fc_corrected_blocks_lane2", \ 321 "FEC correctable block counter lane 2") \ 322 m(+1, u64, fc_corrected_blocks_lane3, "fc_corrected_blocks_lane3", \ 323 "FEC correctable block counter lane 3") \ 324 m(+1, u64, rs_corrected_blocks, "rs_corrected_blocks", \ 325 "FEC correcable block counter") \ 326 m(+1, u64, rs_uncorrectable_blocks, "rs_uncorrectable_blocks", \ 327 "FEC uncorrecable block counter") \ 328 m(+1, u64, rs_no_errors_blocks, "rs_no_errors_blocks", \ 329 "The number of RS-FEC blocks received that had no errors") \ 330 m(+1, u64, rs_single_error_blocks, "rs_single_error_blocks", \ 331 "The number of corrected RS-FEC blocks received that had" \ 332 "exactly 1 error symbol") \ 333 m(+1, u64, rs_corrected_symbols_total, "rs_corrected_symbols_total", \ 334 "Port FEC corrected symbol counter") \ 335 m(+1, u64, rs_corrected_symbols_lane0, "rs_corrected_symbols_lane0", \ 336 "FEC corrected symbol counter lane 0") \ 337 m(+1, u64, rs_corrected_symbols_lane1, "rs_corrected_symbols_lane1", \ 338 "FEC corrected symbol counter lane 1") \ 339 m(+1, u64, rs_corrected_symbols_lane2, "rs_corrected_symbols_lane2", \ 340 "FEC corrected symbol counter lane 2") \ 341 m(+1, u64, rs_corrected_symbols_lane3, "rs_corrected_symbols_lane3", \ 342 "FEC corrected symbol counter lane 3") 343 344/* Per priority statistics for PFC */ 345#define MLX5E_PPORT_PER_PRIO_STATS_SUB(m,n,p) \ 346 m(n, p, +1, u64, rx_octets, "rx_octets", "Received octets") \ 347 m(n, p, +1, u64, reserved_0, "reserved_0", "Reserved") \ 348 m(n, p, +1, u64, reserved_1, "reserved_1", "Reserved") \ 349 m(n, p, +1, u64, reserved_2, "reserved_2", "Reserved") \ 350 m(n, p, +1, u64, rx_frames, "rx_frames", "Received frames") \ 351 m(n, p, +1, u64, tx_octets, "tx_octets", "Transmitted octets") \ 352 m(n, p, +1, u64, reserved_3, "reserved_3", "Reserved") \ 353 m(n, p, +1, u64, reserved_4, "reserved_4", "Reserved") \ 354 m(n, p, +1, u64, reserved_5, "reserved_5", "Reserved") \ 355 m(n, p, +1, u64, tx_frames, "tx_frames", "Transmitted frames") \ 356 m(n, p, +1, u64, rx_pause, "rx_pause", "Received pause frames") \ 357 m(n, p, +1, u64, rx_pause_duration, "rx_pause_duration", \ 358 "Received pause duration") \ 359 m(n, p, +1, u64, tx_pause, "tx_pause", "Transmitted pause frames") \ 360 m(n, p, +1, u64, tx_pause_duration, "tx_pause_duration", \ 361 "Transmitted pause duration") \ 362 m(n, p, +1, u64, rx_pause_transition, "rx_pause_transition", \ 363 "Received pause transitions") \ 364 m(n, p, +1, u64, rx_discards, "rx_discards", "Discarded received frames") \ 365 m(n, p, +1, u64, device_stall_minor_watermark, \ 366 "device_stall_minor_watermark", "Device stall minor watermark") \ 367 m(n, p, +1, u64, device_stall_critical_watermark, \ 368 "device_stall_critical_watermark", "Device stall critical watermark") 369 370#define MLX5E_PPORT_PER_PRIO_STATS_PREFIX(m,p,c,t,f,s,d) \ 371 m(c, t, pri_##p##_##f, "prio" #p "_" s, "Priority " #p " - " d) 372 373#define MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO 8 374 375#define MLX5E_PPORT_PER_PRIO_STATS(m) \ 376 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,0) \ 377 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,1) \ 378 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,2) \ 379 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,3) \ 380 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,4) \ 381 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,5) \ 382 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,6) \ 383 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,7) 384 385#define MLX5E_PCIE_PERFORMANCE_COUNTERS_64(m) \ 386 m(+1, u64, life_time_counter_high, "life_time_counter", \ 387 "Life time counter.", pcie_perf_counters) \ 388 m(+1, u64, tx_overflow_buffer_pkt, "tx_overflow_buffer_pkt", \ 389 "The number of packets dropped due to lack of PCIe buffers " \ 390 "in receive path from NIC port toward the hosts.", \ 391 pcie_perf_counters) \ 392 m(+1, u64, tx_overflow_buffer_marked_pkt, \ 393 "tx_overflow_buffer_marked_pkt", \ 394 "The number of packets marked due to lack of PCIe buffers " \ 395 "in receive path from NIC port toward the hosts.", \ 396 pcie_perf_counters) 397 398#define MLX5E_PCIE_PERFORMANCE_COUNTERS_32(m) \ 399 m(+1, u64, rx_errors, "rx_errors", \ 400 "Number of transitions to recovery due to Framing " \ 401 "errors and CRC errors.", pcie_perf_counters) \ 402 m(+1, u64, tx_errors, "tx_errors", "Number of transitions " \ 403 "to recovery due to EIEOS and TS errors.", pcie_perf_counters) \ 404 m(+1, u64, l0_to_recovery_eieos, "l0_to_recovery_eieos", "Number of " \ 405 "transitions to recovery due to getting EIEOS.", pcie_perf_counters)\ 406 m(+1, u64, l0_to_recovery_ts, "l0_to_recovery_ts", "Number of " \ 407 "transitions to recovery due to getting TS.", pcie_perf_counters) \ 408 m(+1, u64, l0_to_recovery_framing, "l0_to_recovery_framing", "Number "\ 409 "of transitions to recovery due to identifying framing " \ 410 "errors at gen3/4.", pcie_perf_counters) \ 411 m(+1, u64, l0_to_recovery_retrain, "l0_to_recovery_retrain", \ 412 "Number of transitions to recovery due to link retrain request " \ 413 "from data link.", pcie_perf_counters) \ 414 m(+1, u64, crc_error_dllp, "crc_error_dllp", "Number of transitions " \ 415 "to recovery due to identifying CRC DLLP errors.", \ 416 pcie_perf_counters) \ 417 m(+1, u64, crc_error_tlp, "crc_error_tlp", "Number of transitions to "\ 418 "recovery due to identifying CRC TLP errors.", pcie_perf_counters) \ 419 m(+1, u64, outbound_stalled_reads, "outbound_stalled_reads", \ 420 "The percentage of time within the last second that the NIC had " \ 421 "outbound non-posted read requests but could not perform the " \ 422 "operation due to insufficient non-posted credits.", \ 423 pcie_perf_counters) \ 424 m(+1, u64, outbound_stalled_writes, "outbound_stalled_writes", \ 425 "The percentage of time within the last second that the NIC had " \ 426 "outbound posted writes requests but could not perform the " \ 427 "operation due to insufficient posted credits.", \ 428 pcie_perf_counters) \ 429 m(+1, u64, outbound_stalled_reads_events, \ 430 "outbound_stalled_reads_events", "The number of events where " \ 431 "outbound_stalled_reads was above a threshold.", \ 432 pcie_perf_counters) \ 433 m(+1, u64, outbound_stalled_writes_events, \ 434 "outbound_stalled_writes_events", \ 435 "The number of events where outbound_stalled_writes was above " \ 436 "a threshold.", pcie_perf_counters) 437 438#define MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(m) \ 439 m(+1, u64, time_to_boot_image_start, "time_to_boot_image_start", \ 440 "Time from start until FW boot image starts running in usec.", \ 441 pcie_timers_states) \ 442 m(+1, u64, time_to_link_image, "time_to_link_image", \ 443 "Time from start until FW pci_link image starts running in usec.", \ 444 pcie_timers_states) \ 445 m(+1, u64, calibration_time, "calibration_time", \ 446 "Time it took FW to do calibration in usec.", \ 447 pcie_timers_states) \ 448 m(+1, u64, time_to_first_perst, "time_to_first_perst", \ 449 "Time form start until FW handle first perst. in usec.", \ 450 pcie_timers_states) \ 451 m(+1, u64, time_to_detect_state, "time_to_detect_state", \ 452 "Time from start until first transition to LTSSM.Detect_Q in usec", \ 453 pcie_timers_states) \ 454 m(+1, u64, time_to_l0, "time_to_l0", \ 455 "Time from start until first transition to LTSSM.L0 in usec", \ 456 pcie_timers_states) \ 457 m(+1, u64, time_to_crs_en, "time_to_crs_en", \ 458 "Time from start until crs is enabled in usec", \ 459 pcie_timers_states) \ 460 m(+1, u64, time_to_plastic_image_start, "time_to_plastic_image_start",\ 461 "Time form start until FW plastic image starts running in usec.", \ 462 pcie_timers_states) \ 463 m(+1, u64, time_to_iron_image_start, "time_to_iron_image_start", \ 464 "Time form start until FW iron image starts running in usec.", \ 465 pcie_timers_states) \ 466 m(+1, u64, perst_handler, "perst_handler", \ 467 "Number of persts arrived.", pcie_timers_states) \ 468 m(+1, u64, times_in_l1, "times_in_l1", \ 469 "Number of times LTSSM entered L1 flow.", pcie_timers_states) \ 470 m(+1, u64, times_in_l23, "times_in_l23", \ 471 "Number of times LTSSM entered L23 flow.", pcie_timers_states) \ 472 m(+1, u64, dl_down, "dl_down", \ 473 "Number of moves for DL_active to DL_down.", pcie_timers_states) \ 474 m(+1, u64, config_cycle1usec, "config_cycle1usec", \ 475 "Number of configuration requests that firmware " \ 476 "handled in less than 1 usec.", pcie_timers_states) \ 477 m(+1, u64, config_cycle2to7usec, "config_cycle2to7usec", \ 478 "Number of configuration requests that firmware " \ 479 "handled within 2 to 7 usec.", pcie_timers_states) \ 480 m(+1, u64, config_cycle8to15usec, "config_cycle8to15usec", \ 481 "Number of configuration requests that firmware " \ 482 "handled within 8 to 15 usec.", pcie_timers_states) \ 483 m(+1, u64, config_cycle16to63usec, "config_cycle16to63usec", \ 484 "Number of configuration requests that firmware " \ 485 "handled within 16 to 63 usec.", pcie_timers_states) \ 486 m(+1, u64, config_cycle64usec, "config_cycle64usec", \ 487 "Number of configuration requests that firmware " \ 488 "handled took more than 64 usec.", pcie_timers_states) \ 489 m(+1, u64, correctable_err_msg_sent, "correctable_err_msg_sent", \ 490 "Number of correctable error messages sent.", pcie_timers_states) \ 491 m(+1, u64, non_fatal_err_msg_sent, "non_fatal_err_msg_sent", \ 492 "Number of non-Fatal error msg sent.", pcie_timers_states) \ 493 m(+1, u64, fatal_err_msg_sent, "fatal_err_msg_sent", \ 494 "Number of fatal error msg sent.", pcie_timers_states) 495 496#define MLX5E_PCIE_LANE_COUNTERS_32(m) \ 497 m(+1, u64, error_counter_lane0, "error_counter_lane0", \ 498 "Error counter for PCI lane 0", pcie_lanes_counters) \ 499 m(+1, u64, error_counter_lane1, "error_counter_lane1", \ 500 "Error counter for PCI lane 1", pcie_lanes_counters) \ 501 m(+1, u64, error_counter_lane2, "error_counter_lane2", \ 502 "Error counter for PCI lane 2", pcie_lanes_counters) \ 503 m(+1, u64, error_counter_lane3, "error_counter_lane3", \ 504 "Error counter for PCI lane 3", pcie_lanes_counters) \ 505 m(+1, u64, error_counter_lane4, "error_counter_lane4", \ 506 "Error counter for PCI lane 4", pcie_lanes_counters) \ 507 m(+1, u64, error_counter_lane5, "error_counter_lane5", \ 508 "Error counter for PCI lane 5", pcie_lanes_counters) \ 509 m(+1, u64, error_counter_lane6, "error_counter_lane6", \ 510 "Error counter for PCI lane 6", pcie_lanes_counters) \ 511 m(+1, u64, error_counter_lane7, "error_counter_lane7", \ 512 "Error counter for PCI lane 7", pcie_lanes_counters) \ 513 m(+1, u64, error_counter_lane8, "error_counter_lane8", \ 514 "Error counter for PCI lane 8", pcie_lanes_counters) \ 515 m(+1, u64, error_counter_lane9, "error_counter_lane9", \ 516 "Error counter for PCI lane 9", pcie_lanes_counters) \ 517 m(+1, u64, error_counter_lane10, "error_counter_lane10", \ 518 "Error counter for PCI lane 10", pcie_lanes_counters) \ 519 m(+1, u64, error_counter_lane11, "error_counter_lane11", \ 520 "Error counter for PCI lane 11", pcie_lanes_counters) \ 521 m(+1, u64, error_counter_lane12, "error_counter_lane12", \ 522 "Error counter for PCI lane 12", pcie_lanes_counters) \ 523 m(+1, u64, error_counter_lane13, "error_counter_lane13", \ 524 "Error counter for PCI lane 13", pcie_lanes_counters) \ 525 m(+1, u64, error_counter_lane14, "error_counter_lane14", \ 526 "Error counter for PCI lane 14", pcie_lanes_counters) \ 527 m(+1, u64, error_counter_lane15, "error_counter_lane15", \ 528 "Error counter for PCI lane 15", pcie_lanes_counters) 529 530/* 531 * Make sure to update mlx5e_update_pport_counters() 532 * when adding a new MLX5E_PPORT_STATS block 533 */ 534#define MLX5E_PPORT_STATS(m) \ 535 MLX5E_PPORT_PER_PRIO_STATS(m) \ 536 MLX5E_PPORT_IEEE802_3_STATS(m) \ 537 MLX5E_PPORT_RFC2819_STATS(m) 538 539#define MLX5E_PORT_STATS_DEBUG(m) \ 540 MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 541 MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 542 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \ 543 MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(m) \ 544 MLX5E_PPORT_STATISTICAL_DEBUG(m) \ 545 MLX5E_PCIE_PERFORMANCE_COUNTERS_64(m) \ 546 MLX5E_PCIE_PERFORMANCE_COUNTERS_32(m) \ 547 MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(m) \ 548 MLX5E_PCIE_LANE_COUNTERS_32(m) 549 550#define MLX5E_PPORT_IEEE802_3_STATS_NUM \ 551 (0 MLX5E_PPORT_IEEE802_3_STATS(MLX5E_STATS_COUNT)) 552#define MLX5E_PPORT_RFC2819_STATS_NUM \ 553 (0 MLX5E_PPORT_RFC2819_STATS(MLX5E_STATS_COUNT)) 554#define MLX5E_PPORT_STATS_NUM \ 555 (0 MLX5E_PPORT_STATS(MLX5E_STATS_COUNT)) 556 557#define MLX5E_PPORT_PER_PRIO_STATS_NUM \ 558 (0 MLX5E_PPORT_PER_PRIO_STATS(MLX5E_STATS_COUNT)) 559#define MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM \ 560 (0 MLX5E_PPORT_RFC2819_STATS_DEBUG(MLX5E_STATS_COUNT)) 561#define MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM \ 562 (0 MLX5E_PPORT_RFC2863_STATS_DEBUG(MLX5E_STATS_COUNT)) 563#define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM \ 564 (0 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(MLX5E_STATS_COUNT)) 565#define MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM \ 566 (0 MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(MLX5E_STATS_COUNT)) 567#define MLX5E_PPORT_STATISTICAL_DEBUG_NUM \ 568 (0 MLX5E_PPORT_STATISTICAL_DEBUG(MLX5E_STATS_COUNT)) 569#define MLX5E_PORT_STATS_DEBUG_NUM \ 570 (0 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_COUNT)) 571 572struct mlx5e_pport_stats { 573 struct sysctl_ctx_list ctx; 574 u64 arg [0]; 575 MLX5E_PPORT_STATS(MLX5E_STATS_VAR) 576}; 577 578struct mlx5e_port_stats_debug { 579 struct sysctl_ctx_list ctx; 580 u64 arg [0]; 581 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_VAR) 582}; 583 584#define MLX5E_RQ_STATS(m) \ 585 m(+1, u64, packets, "packets", "Received packets") \ 586 m(+1, u64, bytes, "bytes", "Received bytes") \ 587 m(+1, u64, csum_none, "csum_none", "Received packets") \ 588 m(+1, u64, lro_packets, "lro_packets", "Received LRO packets") \ 589 m(+1, u64, lro_bytes, "lro_bytes", "Received LRO bytes") \ 590 m(+1, u64, sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 591 m(+1, u64, sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 592 m(+1, u64, wqe_err, "wqe_err", "Received packets") 593 594#define MLX5E_RQ_STATS_NUM (0 MLX5E_RQ_STATS(MLX5E_STATS_COUNT)) 595 596struct mlx5e_rq_stats { 597 struct sysctl_ctx_list ctx; 598 u64 arg [0]; 599 MLX5E_RQ_STATS(MLX5E_STATS_VAR) 600}; 601 602#define MLX5E_SQ_STATS(m) \ 603 m(+1, u64, packets, "packets", "Transmitted packets") \ 604 m(+1, u64, bytes, "bytes", "Transmitted bytes") \ 605 m(+1, u64, tso_packets, "tso_packets", "Transmitted packets") \ 606 m(+1, u64, tso_bytes, "tso_bytes", "Transmitted bytes") \ 607 m(+1, u64, csum_offload_none, "csum_offload_none", "Transmitted packets") \ 608 m(+1, u64, defragged, "defragged", "Transmitted packets") \ 609 m(+1, u64, dropped, "dropped", "Transmitted packets") \ 610 m(+1, u64, nop, "nop", "Transmitted packets") 611 612#define MLX5E_SQ_STATS_NUM (0 MLX5E_SQ_STATS(MLX5E_STATS_COUNT)) 613 614struct mlx5e_sq_stats { 615 struct sysctl_ctx_list ctx; 616 u64 arg [0]; 617 MLX5E_SQ_STATS(MLX5E_STATS_VAR) 618}; 619 620struct mlx5e_stats { 621 struct mlx5e_vport_stats vport; 622 struct mlx5e_pport_stats pport; 623 struct mlx5e_port_stats_debug port_stats_debug; 624}; 625 626struct mlx5e_rq_param { 627 u32 rqc [MLX5_ST_SZ_DW(rqc)]; 628 struct mlx5_wq_param wq; 629}; 630 631struct mlx5e_sq_param { 632 u32 sqc [MLX5_ST_SZ_DW(sqc)]; 633 struct mlx5_wq_param wq; 634}; 635 636struct mlx5e_cq_param { 637 u32 cqc [MLX5_ST_SZ_DW(cqc)]; 638 struct mlx5_wq_param wq; 639}; 640 641struct mlx5e_params { 642 u8 log_sq_size; 643 u8 log_rq_size; 644 u16 num_channels; 645 u8 default_vlan_prio; 646 u8 num_tc; 647 u8 rx_cq_moderation_mode; 648 u8 tx_cq_moderation_mode; 649 u16 rx_cq_moderation_usec; 650 u16 rx_cq_moderation_pkts; 651 u16 tx_cq_moderation_usec; 652 u16 tx_cq_moderation_pkts; 653 u16 min_rx_wqes; 654 bool hw_lro_en; 655 bool cqe_zipping_en; 656 u32 lro_wqe_sz; 657 u16 rx_hash_log_tbl_sz; 658 u32 tx_pauseframe_control __aligned(4); 659 u32 rx_pauseframe_control __aligned(4); 660 u16 tx_max_inline; 661 u8 tx_min_inline_mode; 662 u8 tx_priority_flow_control; 663 u8 rx_priority_flow_control; 664 u8 channels_rsss; 665}; 666 667#define MLX5E_PARAMS(m) \ 668 m(+1, u64, tx_queue_size_max, "tx_queue_size_max", "Max send queue size") \ 669 m(+1, u64, rx_queue_size_max, "rx_queue_size_max", "Max receive queue size") \ 670 m(+1, u64, tx_queue_size, "tx_queue_size", "Default send queue size") \ 671 m(+1, u64, rx_queue_size, "rx_queue_size", "Default receive queue size") \ 672 m(+1, u64, channels, "channels", "Default number of channels") \ 673 m(+1, u64, channels_rsss, "channels_rsss", "Default channels receive side scaling stride") \ 674 m(+1, u64, coalesce_usecs_max, "coalesce_usecs_max", "Maximum usecs for joining packets") \ 675 m(+1, u64, coalesce_pkts_max, "coalesce_pkts_max", "Maximum packets to join") \ 676 m(+1, u64, rx_coalesce_usecs, "rx_coalesce_usecs", "Limit in usec for joining rx packets") \ 677 m(+1, u64, rx_coalesce_pkts, "rx_coalesce_pkts", "Maximum number of rx packets to join") \ 678 m(+1, u64, rx_coalesce_mode, "rx_coalesce_mode", "0: EQE fixed mode 1: CQE fixed mode 2: EQE auto mode 3: CQE auto mode") \ 679 m(+1, u64, tx_coalesce_usecs, "tx_coalesce_usecs", "Limit in usec for joining tx packets") \ 680 m(+1, u64, tx_coalesce_pkts, "tx_coalesce_pkts", "Maximum number of tx packets to join") \ 681 m(+1, u64, tx_coalesce_mode, "tx_coalesce_mode", "0: EQE mode 1: CQE mode") \ 682 m(+1, u64, tx_completion_fact, "tx_completion_fact", "1..MAX: Completion event ratio") \ 683 m(+1, u64, tx_completion_fact_max, "tx_completion_fact_max", "Maximum completion event ratio") \ 684 m(+1, u64, hw_lro, "hw_lro", "set to enable hw_lro") \ 685 m(+1, u64, cqe_zipping, "cqe_zipping", "0 : CQE zipping disabled") \ 686 m(+1, u64, modify_tx_dma, "modify_tx_dma", "0: Enable TX 1: Disable TX") \ 687 m(+1, u64, modify_rx_dma, "modify_rx_dma", "0: Enable RX 1: Disable RX") \ 688 m(+1, u64, diag_pci_enable, "diag_pci_enable", "0: Disabled 1: Enabled") \ 689 m(+1, u64, diag_general_enable, "diag_general_enable", "0: Disabled 1: Enabled") \ 690 m(+1, u64, hw_mtu, "hw_mtu", "Current hardware MTU value") \ 691 m(+1, u64, mc_local_lb, "mc_local_lb", "0: Local multicast loopback enabled 1: Disabled") \ 692 m(+1, u64, uc_local_lb, "uc_local_lb", "0: Local unicast loopback enabled 1: Disabled") 693 694#define MLX5E_PARAMS_NUM (0 MLX5E_PARAMS(MLX5E_STATS_COUNT)) 695 696struct mlx5e_params_ethtool { 697 u64 arg [0]; 698 MLX5E_PARAMS(MLX5E_STATS_VAR) 699 u64 max_bw_value[IEEE_8021QAZ_MAX_TCS]; 700 u8 max_bw_share[IEEE_8021QAZ_MAX_TCS]; 701 u8 prio_tc[MLX5E_MAX_PRIORITY]; 702 u8 dscp2prio[MLX5_MAX_SUPPORTED_DSCP]; 703 u8 trust_state; 704}; 705 706/* EEPROM Standards for plug in modules */ 707#ifndef MLX5E_ETH_MODULE_SFF_8472 708#define MLX5E_ETH_MODULE_SFF_8472 0x1 709#define MLX5E_ETH_MODULE_SFF_8472_LEN 128 710#endif 711 712#ifndef MLX5E_ETH_MODULE_SFF_8636 713#define MLX5E_ETH_MODULE_SFF_8636 0x2 714#define MLX5E_ETH_MODULE_SFF_8636_LEN 256 715#endif 716 717#ifndef MLX5E_ETH_MODULE_SFF_8436 718#define MLX5E_ETH_MODULE_SFF_8436 0x3 719#define MLX5E_ETH_MODULE_SFF_8436_LEN 256 720#endif 721 722/* EEPROM I2C Addresses */ 723#define MLX5E_I2C_ADDR_LOW 0x50 724#define MLX5E_I2C_ADDR_HIGH 0x51 725 726#define MLX5E_EEPROM_LOW_PAGE 0x0 727#define MLX5E_EEPROM_HIGH_PAGE 0x3 728 729#define MLX5E_EEPROM_HIGH_PAGE_OFFSET 128 730#define MLX5E_EEPROM_PAGE_LENGTH 256 731 732#define MLX5E_EEPROM_INFO_BYTES 0x3 733 734struct mlx5e_cq { 735 /* data path - accessed per cqe */ 736 struct mlx5_cqwq wq; 737 738 /* data path - accessed per HW polling */ 739 struct mlx5_core_cq mcq; 740 741 /* control */ 742 struct mlx5e_priv *priv; 743 struct mlx5_wq_ctrl wq_ctrl; 744} __aligned(MLX5E_CACHELINE_SIZE); 745 746struct mlx5e_rq_mbuf { 747 bus_dmamap_t dma_map; 748 caddr_t data; 749 struct mbuf *mbuf; 750}; 751 752struct mlx5e_rq { 753 /* data path */ 754 struct mlx5_wq_ll wq; 755 struct mtx mtx; 756 bus_dma_tag_t dma_tag; 757 u32 wqe_sz; 758 u32 nsegs; 759 struct mlx5e_rq_mbuf *mbuf; 760 struct ifnet *ifp; 761 struct mlx5e_rq_stats stats; 762 struct mlx5e_cq cq; 763 struct lro_ctrl lro; 764 volatile int enabled; 765 int ix; 766 767 /* Dynamic Interrupt Moderation */ 768 struct net_dim dim; 769 770 /* control */ 771 struct mlx5_wq_ctrl wq_ctrl; 772 u32 rqn; 773 struct mlx5e_channel *channel; 774 struct callout watchdog; 775} __aligned(MLX5E_CACHELINE_SIZE); 776 777struct mlx5e_sq_mbuf { 778 bus_dmamap_t dma_map; 779 struct mbuf *mbuf; 780 u32 num_bytes; 781 u32 num_wqebbs; 782}; 783 784enum { 785 MLX5E_SQ_READY, 786 MLX5E_SQ_FULL 787}; 788 789struct mlx5e_sq { 790 /* data path */ 791 struct mtx lock; 792 bus_dma_tag_t dma_tag; 793 struct mtx comp_lock; 794 795 /* dirtied @completion */ 796 u16 cc; 797 798 /* dirtied @xmit */ 799 u16 pc __aligned(MLX5E_CACHELINE_SIZE); 800 u16 bf_offset; 801 u16 cev_counter; /* completion event counter */ 802 u16 cev_factor; /* completion event factor */ 803 u16 cev_next_state; /* next completion event state */ 804#define MLX5E_CEV_STATE_INITIAL 0 /* timer not started */ 805#define MLX5E_CEV_STATE_SEND_NOPS 1 /* send NOPs */ 806#define MLX5E_CEV_STATE_HOLD_NOPS 2 /* don't send NOPs yet */ 807 u16 running; /* set if SQ is running */ 808 struct callout cev_callout; 809 union { 810 u32 d32[2]; 811 u64 d64; 812 } doorbell; 813 struct mlx5e_sq_stats stats; 814 815 struct mlx5e_cq cq; 816 817 /* pointers to per packet info: write@xmit, read@completion */ 818 struct mlx5e_sq_mbuf *mbuf; 819 struct buf_ring *br; 820 821 /* read only */ 822 struct mlx5_wq_cyc wq; 823 struct mlx5_uar uar; 824 struct ifnet *ifp; 825 u32 sqn; 826 u32 bf_buf_size; 827 u32 mkey_be; 828 u16 max_inline; 829 u8 min_inline_mode; 830 u8 min_insert_caps; 831#define MLX5E_INSERT_VLAN 1 832#define MLX5E_INSERT_NON_VLAN 2 833 834 /* control path */ 835 struct mlx5_wq_ctrl wq_ctrl; 836 struct mlx5e_priv *priv; 837 int tc; 838} __aligned(MLX5E_CACHELINE_SIZE); 839 840static inline bool 841mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) 842{ 843 u16 cc = sq->cc; 844 u16 pc = sq->pc; 845 846 return ((sq->wq.sz_m1 & (cc - pc)) >= n || cc == pc); 847} 848 849struct mlx5e_channel { 850 /* data path */ 851 struct mlx5e_rq rq; 852 struct mlx5e_sq sq[MLX5E_MAX_TX_NUM_TC]; 853 struct ifnet *ifp; 854 u32 mkey_be; 855 u8 num_tc; 856 857 /* control */ 858 struct mlx5e_priv *priv; 859 int ix; 860 int cpu; 861} __aligned(MLX5E_CACHELINE_SIZE); 862 863enum mlx5e_traffic_types { 864 MLX5E_TT_IPV4_TCP, 865 MLX5E_TT_IPV6_TCP, 866 MLX5E_TT_IPV4_UDP, 867 MLX5E_TT_IPV6_UDP, 868 MLX5E_TT_IPV4_IPSEC_AH, 869 MLX5E_TT_IPV6_IPSEC_AH, 870 MLX5E_TT_IPV4_IPSEC_ESP, 871 MLX5E_TT_IPV6_IPSEC_ESP, 872 MLX5E_TT_IPV4, 873 MLX5E_TT_IPV6, 874 MLX5E_TT_ANY, 875 MLX5E_NUM_TT, 876}; 877 878enum { 879 MLX5E_RQT_SPREADING = 0, 880 MLX5E_RQT_DEFAULT_RQ = 1, 881 MLX5E_NUM_RQT = 2, 882}; 883 884struct mlx5_flow_rule; 885 886struct mlx5e_eth_addr_info { 887 u8 addr [ETH_ALEN + 2]; 888 u32 tt_vec; 889 /* flow table rule per traffic type */ 890 struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT]; 891}; 892 893#define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE) 894 895struct mlx5e_eth_addr_hash_node; 896 897struct mlx5e_eth_addr_hash_head { 898 struct mlx5e_eth_addr_hash_node *lh_first; 899}; 900 901struct mlx5e_eth_addr_db { 902 struct mlx5e_eth_addr_hash_head if_uc[MLX5E_ETH_ADDR_HASH_SIZE]; 903 struct mlx5e_eth_addr_hash_head if_mc[MLX5E_ETH_ADDR_HASH_SIZE]; 904 struct mlx5e_eth_addr_info broadcast; 905 struct mlx5e_eth_addr_info allmulti; 906 struct mlx5e_eth_addr_info promisc; 907 bool broadcast_enabled; 908 bool allmulti_enabled; 909 bool promisc_enabled; 910}; 911 912enum { 913 MLX5E_STATE_ASYNC_EVENTS_ENABLE, 914 MLX5E_STATE_OPENED, 915}; 916 917enum { 918 MLX5_BW_NO_LIMIT = 0, 919 MLX5_100_MBPS_UNIT = 3, 920 MLX5_GBPS_UNIT = 4, 921}; 922 923struct mlx5e_vlan_db { 924 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 925 struct mlx5_flow_rule *active_vlans_ft_rule[VLAN_N_VID]; 926 struct mlx5_flow_rule *untagged_ft_rule; 927 struct mlx5_flow_rule *any_cvlan_ft_rule; 928 struct mlx5_flow_rule *any_svlan_ft_rule; 929 bool filter_disabled; 930}; 931 932struct mlx5e_flow_table { 933 int num_groups; 934 struct mlx5_flow_table *t; 935 struct mlx5_flow_group **g; 936}; 937 938struct mlx5e_flow_tables { 939 struct mlx5_flow_namespace *ns; 940 struct mlx5e_flow_table vlan; 941 struct mlx5e_flow_table main; 942 struct mlx5e_flow_table inner_rss; 943}; 944 945struct mlx5e_priv { 946 struct mlx5_core_dev *mdev; /* must be first */ 947 948 /* priv data path fields - start */ 949 int order_base_2_num_channels; 950 int queue_mapping_channel_mask; 951 int num_tc; 952 int default_vlan_prio; 953 /* priv data path fields - end */ 954 955 unsigned long state; 956 int gone; 957#define PRIV_LOCK(priv) sx_xlock(&(priv)->state_lock) 958#define PRIV_UNLOCK(priv) sx_xunlock(&(priv)->state_lock) 959#define PRIV_LOCKED(priv) sx_xlocked(&(priv)->state_lock) 960 struct sx state_lock; /* Protects Interface state */ 961 struct mlx5_uar cq_uar; 962 u32 pdn; 963 u32 tdn; 964 struct mlx5_core_mr mr; 965 966 u32 tisn[MLX5E_MAX_TX_NUM_TC]; 967 u32 rqtn; 968 u32 tirn[MLX5E_NUM_TT]; 969 970 struct mlx5e_flow_tables fts; 971 struct mlx5e_eth_addr_db eth_addr; 972 struct mlx5e_vlan_db vlan; 973 974 struct mlx5e_params params; 975 struct mlx5e_params_ethtool params_ethtool; 976 union mlx5_core_pci_diagnostics params_pci; 977 union mlx5_core_general_diagnostics params_general; 978 struct mtx async_events_mtx; /* sync hw events */ 979 struct work_struct update_stats_work; 980 struct work_struct update_carrier_work; 981 struct work_struct set_rx_mode_work; 982 MLX5_DECLARE_DOORBELL_LOCK(doorbell_lock) 983 984 struct ifnet *ifp; 985 struct sysctl_ctx_list sysctl_ctx; 986 struct sysctl_oid *sysctl_ifnet; 987 struct sysctl_oid *sysctl_hw; 988 int sysctl_debug; 989 struct mlx5e_stats stats; 990 int counter_set_id; 991 992 struct workqueue_struct *wq; 993 994 eventhandler_tag vlan_detach; 995 eventhandler_tag vlan_attach; 996 struct ifmedia media; 997 int media_status_last; 998 int media_active_last; 999 1000 struct callout watchdog; 1001 1002 struct mlx5e_channel channel[]; 1003}; 1004 1005#define MLX5E_NET_IP_ALIGN 2 1006 1007struct mlx5e_tx_wqe { 1008 struct mlx5_wqe_ctrl_seg ctrl; 1009 struct mlx5_wqe_eth_seg eth; 1010}; 1011 1012struct mlx5e_rx_wqe { 1013 struct mlx5_wqe_srq_next_seg next; 1014 struct mlx5_wqe_data_seg data[]; 1015}; 1016 1017/* the size of the structure above must be power of two */ 1018CTASSERT(powerof2(sizeof(struct mlx5e_rx_wqe))); 1019 1020struct mlx5e_eeprom { 1021 int lock_bit; 1022 int i2c_addr; 1023 int page_num; 1024 int device_addr; 1025 int module_num; 1026 int len; 1027 int type; 1028 int page_valid; 1029 u32 *data; 1030}; 1031 1032#define MLX5E_FLD_MAX(typ, fld) ((1ULL << __mlx5_bit_sz(typ, fld)) - 1ULL) 1033 1034int mlx5e_xmit(struct ifnet *, struct mbuf *); 1035 1036int mlx5e_open_locked(struct ifnet *); 1037int mlx5e_close_locked(struct ifnet *); 1038 1039void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, int event); 1040void mlx5e_rx_cq_comp(struct mlx5_core_cq *); 1041void mlx5e_tx_cq_comp(struct mlx5_core_cq *); 1042struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); 1043 1044void mlx5e_dim_work(struct work_struct *); 1045void mlx5e_dim_build_cq_param(struct mlx5e_priv *, struct mlx5e_cq_param *); 1046 1047int mlx5e_open_flow_table(struct mlx5e_priv *priv); 1048void mlx5e_close_flow_table(struct mlx5e_priv *priv); 1049void mlx5e_set_rx_mode_core(struct mlx5e_priv *priv); 1050void mlx5e_set_rx_mode_work(struct work_struct *work); 1051 1052void mlx5e_vlan_rx_add_vid(void *, struct ifnet *, u16); 1053void mlx5e_vlan_rx_kill_vid(void *, struct ifnet *, u16); 1054void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); 1055void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); 1056int mlx5e_add_all_vlan_rules(struct mlx5e_priv *priv); 1057void mlx5e_del_all_vlan_rules(struct mlx5e_priv *priv); 1058 1059static inline void 1060mlx5e_tx_notify_hw(struct mlx5e_sq *sq, u32 *wqe, int bf_sz) 1061{ 1062 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; 1063 1064 /* ensure wqe is visible to device before updating doorbell record */ 1065 wmb(); 1066 1067 *sq->wq.db = cpu_to_be32(sq->pc); 1068 1069 /* 1070 * Ensure the doorbell record is visible to device before ringing 1071 * the doorbell: 1072 */ 1073 wmb(); 1074 1075 if (bf_sz) { 1076 __iowrite64_copy(sq->uar.bf_map + ofst, wqe, bf_sz); 1077 1078 /* flush the write-combining mapped buffer */ 1079 wmb(); 1080 1081 } else { 1082 mlx5_write64(wqe, sq->uar.map + ofst, 1083 MLX5_GET_DOORBELL_LOCK(&sq->priv->doorbell_lock)); 1084 } 1085 1086 sq->bf_offset ^= sq->bf_buf_size; 1087} 1088 1089static inline void 1090mlx5e_cq_arm(struct mlx5e_cq *cq, spinlock_t *dblock) 1091{ 1092 struct mlx5_core_cq *mcq; 1093 1094 mcq = &cq->mcq; 1095 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, dblock, cq->wq.cc); 1096} 1097 1098extern const struct ethtool_ops mlx5e_ethtool_ops; 1099void mlx5e_create_ethtool(struct mlx5e_priv *); 1100void mlx5e_create_stats(struct sysctl_ctx_list *, 1101 struct sysctl_oid_list *, const char *, 1102 const char **, unsigned, u64 *); 1103void mlx5e_send_nop(struct mlx5e_sq *, u32); 1104void mlx5e_sq_cev_timeout(void *); 1105int mlx5e_refresh_channel_params(struct mlx5e_priv *); 1106int mlx5e_open_cq(struct mlx5e_priv *, struct mlx5e_cq_param *, 1107 struct mlx5e_cq *, mlx5e_cq_comp_t *, int eq_ix); 1108void mlx5e_close_cq(struct mlx5e_cq *); 1109void mlx5e_free_sq_db(struct mlx5e_sq *); 1110int mlx5e_alloc_sq_db(struct mlx5e_sq *); 1111int mlx5e_enable_sq(struct mlx5e_sq *, struct mlx5e_sq_param *, int tis_num); 1112int mlx5e_modify_sq(struct mlx5e_sq *, int curr_state, int next_state); 1113void mlx5e_disable_sq(struct mlx5e_sq *); 1114void mlx5e_drain_sq(struct mlx5e_sq *); 1115void mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value); 1116void mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value); 1117void mlx5e_resume_sq(struct mlx5e_sq *sq); 1118void mlx5e_update_sq_inline(struct mlx5e_sq *sq); 1119void mlx5e_refresh_sq_inline(struct mlx5e_priv *priv); 1120 1121#endif /* _MLX5_EN_H_ */ 1122