en.h revision 347864
1/*- 2 * Copyright (c) 2015-2019 Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_en/en.h 347864 2019-05-16 18:16:08Z hselasky $ 26 */ 27 28#ifndef _MLX5_EN_H_ 29#define _MLX5_EN_H_ 30 31#include <linux/kmod.h> 32#include <linux/page.h> 33#include <linux/slab.h> 34#include <linux/if_vlan.h> 35#include <linux/if_ether.h> 36#include <linux/vmalloc.h> 37#include <linux/moduleparam.h> 38#include <linux/delay.h> 39#include <linux/netdevice.h> 40#include <linux/etherdevice.h> 41#include <linux/ktime.h> 42#include <linux/net_dim.h> 43 44#include <netinet/in_systm.h> 45#include <netinet/in.h> 46#include <netinet/if_ether.h> 47#include <netinet/ip.h> 48#include <netinet/ip6.h> 49#include <netinet/tcp.h> 50#include <netinet/tcp_lro.h> 51#include <netinet/udp.h> 52#include <net/ethernet.h> 53#include <sys/buf_ring.h> 54 55#include "opt_rss.h" 56 57#ifdef RSS 58#include <net/rss_config.h> 59#include <netinet/in_rss.h> 60#endif 61 62#include <machine/bus.h> 63 64#include <dev/mlx5/driver.h> 65#include <dev/mlx5/qp.h> 66#include <dev/mlx5/cq.h> 67#include <dev/mlx5/port.h> 68#include <dev/mlx5/vport.h> 69#include <dev/mlx5/diagnostics.h> 70 71#include <dev/mlx5/mlx5_core/wq.h> 72#include <dev/mlx5/mlx5_core/transobj.h> 73#include <dev/mlx5/mlx5_core/mlx5_core.h> 74 75#define MLX5E_MAX_PRIORITY 8 76 77/* IEEE 802.1Qaz standard supported values */ 78#define IEEE_8021QAZ_MAX_TCS 8 79 80#define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x7 81#define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa 82#define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xe 83 84#define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x7 85#define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa 86#define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xe 87 88#define MLX5E_MAX_RX_SEGS 7 89 90#ifndef MLX5E_MAX_RX_BYTES 91#define MLX5E_MAX_RX_BYTES MCLBYTES 92#endif 93 94#if (MLX5E_MAX_RX_SEGS == 1) 95/* FreeBSD HW LRO is limited by 16KB - the size of max mbuf */ 96#define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ MJUM16BYTES 97#else 98#define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ \ 99 MIN(65535, MLX5E_MAX_RX_SEGS * MLX5E_MAX_RX_BYTES) 100#endif 101#define MLX5E_DIM_DEFAULT_PROFILE 3 102#define MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO 16 103#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 104#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 105#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 106#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 107#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 108#define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 109#define MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ 0x7 110#define MLX5E_CACHELINE_SIZE CACHE_LINE_SIZE 111#define MLX5E_HW2SW_MTU(hwmtu) \ 112 ((hwmtu) - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 113#define MLX5E_SW2HW_MTU(swmtu) \ 114 ((swmtu) + (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 115#define MLX5E_SW2MB_MTU(swmtu) \ 116 (MLX5E_SW2HW_MTU(swmtu) + MLX5E_NET_IP_ALIGN) 117#define MLX5E_MTU_MIN 72 /* Min MTU allowed by the kernel */ 118#define MLX5E_MTU_MAX MIN(ETHERMTU_JUMBO, MJUM16BYTES) /* Max MTU of Ethernet 119 * jumbo frames */ 120 121#define MLX5E_BUDGET_MAX 8192 /* RX and TX */ 122#define MLX5E_RX_BUDGET_MAX 256 123#define MLX5E_SQ_BF_BUDGET 16 124#define MLX5E_SQ_TX_QUEUE_SIZE 4096 /* SQ drbr queue size */ 125 126#define MLX5E_MAX_TX_NUM_TC 8 /* units */ 127#define MLX5E_MAX_TX_HEADER 128 /* bytes */ 128#define MLX5E_MAX_TX_PAYLOAD_SIZE 65536 /* bytes */ 129#define MLX5E_MAX_TX_MBUF_SIZE 65536 /* bytes */ 130#define MLX5E_MAX_TX_MBUF_FRAGS \ 131 ((MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS) - \ 132 (MLX5E_MAX_TX_HEADER / MLX5_SEND_WQE_DS) - \ 133 1 /* the maximum value of the DS counter is 0x3F and not 0x40 */) /* units */ 134#define MLX5E_MAX_TX_INLINE \ 135 (MLX5E_MAX_TX_HEADER - sizeof(struct mlx5e_tx_wqe) + \ 136 sizeof(((struct mlx5e_tx_wqe *)0)->eth.inline_hdr_start)) /* bytes */ 137 138#define MLX5E_100MB (100000) 139#define MLX5E_1GB (1000000) 140 141MALLOC_DECLARE(M_MLX5EN); 142 143struct mlx5_core_dev; 144struct mlx5e_cq; 145 146typedef void (mlx5e_cq_comp_t)(struct mlx5_core_cq *); 147 148#define MLX5E_STATS_COUNT(a, ...) a 149#define MLX5E_STATS_VAR(a, b, c, ...) b c; 150#define MLX5E_STATS_DESC(a, b, c, d, e, ...) d, e, 151 152#define MLX5E_VPORT_STATS(m) \ 153 /* HW counters */ \ 154 m(+1, u64, rx_packets, "rx_packets", "Received packets") \ 155 m(+1, u64, rx_bytes, "rx_bytes", "Received bytes") \ 156 m(+1, u64, tx_packets, "tx_packets", "Transmitted packets") \ 157 m(+1, u64, tx_bytes, "tx_bytes", "Transmitted bytes") \ 158 m(+1, u64, rx_error_packets, "rx_error_packets", "Received error packets") \ 159 m(+1, u64, rx_error_bytes, "rx_error_bytes", "Received error bytes") \ 160 m(+1, u64, tx_error_packets, "tx_error_packets", "Transmitted error packets") \ 161 m(+1, u64, tx_error_bytes, "tx_error_bytes", "Transmitted error bytes") \ 162 m(+1, u64, rx_unicast_packets, "rx_unicast_packets", "Received unicast packets") \ 163 m(+1, u64, rx_unicast_bytes, "rx_unicast_bytes", "Received unicast bytes") \ 164 m(+1, u64, tx_unicast_packets, "tx_unicast_packets", "Transmitted unicast packets") \ 165 m(+1, u64, tx_unicast_bytes, "tx_unicast_bytes", "Transmitted unicast bytes") \ 166 m(+1, u64, rx_multicast_packets, "rx_multicast_packets", "Received multicast packets") \ 167 m(+1, u64, rx_multicast_bytes, "rx_multicast_bytes", "Received multicast bytes") \ 168 m(+1, u64, tx_multicast_packets, "tx_multicast_packets", "Transmitted multicast packets") \ 169 m(+1, u64, tx_multicast_bytes, "tx_multicast_bytes", "Transmitted multicast bytes") \ 170 m(+1, u64, rx_broadcast_packets, "rx_broadcast_packets", "Received broadcast packets") \ 171 m(+1, u64, rx_broadcast_bytes, "rx_broadcast_bytes", "Received broadcast bytes") \ 172 m(+1, u64, tx_broadcast_packets, "tx_broadcast_packets", "Transmitted broadcast packets") \ 173 m(+1, u64, tx_broadcast_bytes, "tx_broadcast_bytes", "Transmitted broadcast bytes") \ 174 m(+1, u64, rx_out_of_buffer, "rx_out_of_buffer", "Receive out of buffer, no recv wqes events") \ 175 /* SW counters */ \ 176 m(+1, u64, tso_packets, "tso_packets", "Transmitted TSO packets") \ 177 m(+1, u64, tso_bytes, "tso_bytes", "Transmitted TSO bytes") \ 178 m(+1, u64, lro_packets, "lro_packets", "Received LRO packets") \ 179 m(+1, u64, lro_bytes, "lro_bytes", "Received LRO bytes") \ 180 m(+1, u64, sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 181 m(+1, u64, sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 182 m(+1, u64, rx_csum_good, "rx_csum_good", "Received checksum valid packets") \ 183 m(+1, u64, rx_csum_none, "rx_csum_none", "Received no checksum packets") \ 184 m(+1, u64, tx_csum_offload, "tx_csum_offload", "Transmit checksum offload packets") \ 185 m(+1, u64, tx_queue_dropped, "tx_queue_dropped", "Transmit queue dropped") \ 186 m(+1, u64, tx_defragged, "tx_defragged", "Transmit queue defragged") \ 187 m(+1, u64, rx_wqe_err, "rx_wqe_err", "Receive WQE errors") \ 188 m(+1, u64, tx_jumbo_packets, "tx_jumbo_packets", "TX packets greater than 1518 octets") \ 189 m(+1, u64, rx_steer_missed_packets, "rx_steer_missed_packets", "RX packets dropped by steering rule(s)") 190 191#define MLX5E_VPORT_STATS_NUM (0 MLX5E_VPORT_STATS(MLX5E_STATS_COUNT)) 192 193struct mlx5e_vport_stats { 194 struct sysctl_ctx_list ctx; 195 u64 arg [0]; 196 MLX5E_VPORT_STATS(MLX5E_STATS_VAR) 197}; 198 199#define MLX5E_PPORT_IEEE802_3_STATS(m) \ 200 m(+1, u64, frames_tx, "frames_tx", "Frames transmitted") \ 201 m(+1, u64, frames_rx, "frames_rx", "Frames received") \ 202 m(+1, u64, check_seq_err, "check_seq_err", "Sequence errors") \ 203 m(+1, u64, alignment_err, "alignment_err", "Alignment errors") \ 204 m(+1, u64, octets_tx, "octets_tx", "Bytes transmitted") \ 205 m(+1, u64, octets_received, "octets_received", "Bytes received") \ 206 m(+1, u64, multicast_xmitted, "multicast_xmitted", "Multicast transmitted") \ 207 m(+1, u64, broadcast_xmitted, "broadcast_xmitted", "Broadcast transmitted") \ 208 m(+1, u64, multicast_rx, "multicast_rx", "Multicast received") \ 209 m(+1, u64, broadcast_rx, "broadcast_rx", "Broadcast received") \ 210 m(+1, u64, in_range_len_errors, "in_range_len_errors", "In range length errors") \ 211 m(+1, u64, out_of_range_len, "out_of_range_len", "Out of range length errors") \ 212 m(+1, u64, too_long_errors, "too_long_errors", "Too long errors") \ 213 m(+1, u64, symbol_err, "symbol_err", "Symbol errors") \ 214 m(+1, u64, mac_control_tx, "mac_control_tx", "MAC control transmitted") \ 215 m(+1, u64, mac_control_rx, "mac_control_rx", "MAC control received") \ 216 m(+1, u64, unsupported_op_rx, "unsupported_op_rx", "Unsupported operation received") \ 217 m(+1, u64, pause_ctrl_rx, "pause_ctrl_rx", "Pause control received") \ 218 m(+1, u64, pause_ctrl_tx, "pause_ctrl_tx", "Pause control transmitted") 219 220#define MLX5E_PPORT_RFC2819_STATS(m) \ 221 m(+1, u64, drop_events, "drop_events", "Dropped events") \ 222 m(+1, u64, octets, "octets", "Octets") \ 223 m(+1, u64, pkts, "pkts", "Packets") \ 224 m(+1, u64, broadcast_pkts, "broadcast_pkts", "Broadcast packets") \ 225 m(+1, u64, multicast_pkts, "multicast_pkts", "Multicast packets") \ 226 m(+1, u64, crc_align_errors, "crc_align_errors", "CRC alignment errors") \ 227 m(+1, u64, undersize_pkts, "undersize_pkts", "Undersized packets") \ 228 m(+1, u64, oversize_pkts, "oversize_pkts", "Oversized packets") \ 229 m(+1, u64, fragments, "fragments", "Fragments") \ 230 m(+1, u64, jabbers, "jabbers", "Jabbers") \ 231 m(+1, u64, collisions, "collisions", "Collisions") 232 233#define MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 234 m(+1, u64, p64octets, "p64octets", "Bytes") \ 235 m(+1, u64, p65to127octets, "p65to127octets", "Bytes") \ 236 m(+1, u64, p128to255octets, "p128to255octets", "Bytes") \ 237 m(+1, u64, p256to511octets, "p256to511octets", "Bytes") \ 238 m(+1, u64, p512to1023octets, "p512to1023octets", "Bytes") \ 239 m(+1, u64, p1024to1518octets, "p1024to1518octets", "Bytes") \ 240 m(+1, u64, p1519to2047octets, "p1519to2047octets", "Bytes") \ 241 m(+1, u64, p2048to4095octets, "p2048to4095octets", "Bytes") \ 242 m(+1, u64, p4096to8191octets, "p4096to8191octets", "Bytes") \ 243 m(+1, u64, p8192to10239octets, "p8192to10239octets", "Bytes") 244 245#define MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 246 m(+1, u64, in_octets, "in_octets", "In octets") \ 247 m(+1, u64, in_ucast_pkts, "in_ucast_pkts", "In unicast packets") \ 248 m(+1, u64, in_discards, "in_discards", "In discards") \ 249 m(+1, u64, in_errors, "in_errors", "In errors") \ 250 m(+1, u64, in_unknown_protos, "in_unknown_protos", "In unknown protocols") \ 251 m(+1, u64, out_octets, "out_octets", "Out octets") \ 252 m(+1, u64, out_ucast_pkts, "out_ucast_pkts", "Out unicast packets") \ 253 m(+1, u64, out_discards, "out_discards", "Out discards") \ 254 m(+1, u64, out_errors, "out_errors", "Out errors") \ 255 m(+1, u64, in_multicast_pkts, "in_multicast_pkts", "In multicast packets") \ 256 m(+1, u64, in_broadcast_pkts, "in_broadcast_pkts", "In broadcast packets") \ 257 m(+1, u64, out_multicast_pkts, "out_multicast_pkts", "Out multicast packets") \ 258 m(+1, u64, out_broadcast_pkts, "out_broadcast_pkts", "Out broadcast packets") 259 260#define MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(m) \ 261 m(+1, u64, port_transmit_wait_high, "port_transmit_wait_high", "Port transmit wait high") \ 262 m(+1, u64, ecn_marked, "ecn_marked", "ECN marked") \ 263 m(+1, u64, no_buffer_discard_mc, "no_buffer_discard_mc", "No buffer discard mc") \ 264 m(+1, u64, rx_ebp, "rx_ebp", "RX EBP") \ 265 m(+1, u64, tx_ebp, "tx_ebp", "TX EBP") \ 266 m(+1, u64, rx_buffer_almost_full, "rx_buffer_almost_full", "RX buffer almost full") \ 267 m(+1, u64, rx_buffer_full, "rx_buffer_full", "RX buffer full") \ 268 m(+1, u64, rx_icrc_encapsulated, "rx_icrc_encapsulated", "RX ICRC encapsulated") \ 269 m(+1, u64, ex_reserved_0, "ex_reserved_0", "Reserved") \ 270 m(+1, u64, ex_reserved_1, "ex_reserved_1", "Reserved") \ 271 m(+1, u64, tx_stat_p64octets, "tx_stat_p64octets", "Bytes") \ 272 m(+1, u64, tx_stat_p65to127octets, "tx_stat_p65to127octets", "Bytes") \ 273 m(+1, u64, tx_stat_p128to255octets, "tx_stat_p128to255octets", "Bytes") \ 274 m(+1, u64, tx_stat_p256to511octets, "tx_stat_p256to511octets", "Bytes") \ 275 m(+1, u64, tx_stat_p512to1023octets, "tx_stat_p512to1023octets", "Bytes") \ 276 m(+1, u64, tx_stat_p1024to1518octets, "tx_stat_p1024to1518octets", "Bytes") \ 277 m(+1, u64, tx_stat_p1519to2047octets, "tx_stat_p1519to2047octets", "Bytes") \ 278 m(+1, u64, tx_stat_p2048to4095octets, "tx_stat_p2048to4095octets", "Bytes") \ 279 m(+1, u64, tx_stat_p4096to8191octets, "tx_stat_p4096to8191octets", "Bytes") \ 280 m(+1, u64, tx_stat_p8192to10239octets, "tx_stat_p8192to10239octets", "Bytes") 281 282#define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \ 283 m(+1, u64, time_since_last_clear, "time_since_last_clear", \ 284 "Time since the last counters clear event (msec)") \ 285 m(+1, u64, symbol_errors, "symbol_errors", "Symbol errors") \ 286 m(+1, u64, sync_headers_errors, "sync_headers_errors", \ 287 "Sync header error counter") \ 288 m(+1, u64, bip_errors_lane0, "edpl_bip_errors_lane0", \ 289 "Indicates the number of PRBS errors on lane 0") \ 290 m(+1, u64, bip_errors_lane1, "edpl_bip_errors_lane1", \ 291 "Indicates the number of PRBS errors on lane 1") \ 292 m(+1, u64, bip_errors_lane2, "edpl_bip_errors_lane2", \ 293 "Indicates the number of PRBS errors on lane 2") \ 294 m(+1, u64, bip_errors_lane3, "edpl_bip_errors_lane3", \ 295 "Indicates the number of PRBS errors on lane 3") \ 296 m(+1, u64, fc_corrected_blocks_lane0, "fc_corrected_blocks_lane0", \ 297 "FEC correctable block counter lane 0") \ 298 m(+1, u64, fc_corrected_blocks_lane1, "fc_corrected_blocks_lane1", \ 299 "FEC correctable block counter lane 1") \ 300 m(+1, u64, fc_corrected_blocks_lane2, "fc_corrected_blocks_lane2", \ 301 "FEC correctable block counter lane 2") \ 302 m(+1, u64, fc_corrected_blocks_lane3, "fc_corrected_blocks_lane3", \ 303 "FEC correctable block counter lane 3") \ 304 m(+1, u64, rs_corrected_blocks, "rs_corrected_blocks", \ 305 "FEC correcable block counter") \ 306 m(+1, u64, rs_uncorrectable_blocks, "rs_uncorrectable_blocks", \ 307 "FEC uncorrecable block counter") \ 308 m(+1, u64, rs_no_errors_blocks, "rs_no_errors_blocks", \ 309 "The number of RS-FEC blocks received that had no errors") \ 310 m(+1, u64, rs_single_error_blocks, "rs_single_error_blocks", \ 311 "The number of corrected RS-FEC blocks received that had" \ 312 "exactly 1 error symbol") \ 313 m(+1, u64, rs_corrected_symbols_total, "rs_corrected_symbols_total", \ 314 "Port FEC corrected symbol counter") \ 315 m(+1, u64, rs_corrected_symbols_lane0, "rs_corrected_symbols_lane0", \ 316 "FEC corrected symbol counter lane 0") \ 317 m(+1, u64, rs_corrected_symbols_lane1, "rs_corrected_symbols_lane1", \ 318 "FEC corrected symbol counter lane 1") \ 319 m(+1, u64, rs_corrected_symbols_lane2, "rs_corrected_symbols_lane2", \ 320 "FEC corrected symbol counter lane 2") \ 321 m(+1, u64, rs_corrected_symbols_lane3, "rs_corrected_symbols_lane3", \ 322 "FEC corrected symbol counter lane 3") 323 324/* Per priority statistics for PFC */ 325#define MLX5E_PPORT_PER_PRIO_STATS_SUB(m,n,p) \ 326 m(n, p, +1, u64, rx_octets, "rx_octets", "Received octets") \ 327 m(n, p, +1, u64, reserved_0, "reserved_0", "Reserved") \ 328 m(n, p, +1, u64, reserved_1, "reserved_1", "Reserved") \ 329 m(n, p, +1, u64, reserved_2, "reserved_2", "Reserved") \ 330 m(n, p, +1, u64, rx_frames, "rx_frames", "Received frames") \ 331 m(n, p, +1, u64, tx_octets, "tx_octets", "Transmitted octets") \ 332 m(n, p, +1, u64, reserved_3, "reserved_3", "Reserved") \ 333 m(n, p, +1, u64, reserved_4, "reserved_4", "Reserved") \ 334 m(n, p, +1, u64, reserved_5, "reserved_5", "Reserved") \ 335 m(n, p, +1, u64, tx_frames, "tx_frames", "Transmitted frames") \ 336 m(n, p, +1, u64, rx_pause, "rx_pause", "Received pause frames") \ 337 m(n, p, +1, u64, rx_pause_duration, "rx_pause_duration", \ 338 "Received pause duration") \ 339 m(n, p, +1, u64, tx_pause, "tx_pause", "Transmitted pause frames") \ 340 m(n, p, +1, u64, tx_pause_duration, "tx_pause_duration", \ 341 "Transmitted pause duration") \ 342 m(n, p, +1, u64, rx_pause_transition, "rx_pause_transition", \ 343 "Received pause transitions") \ 344 m(n, p, +1, u64, rx_discards, "rx_discards", "Discarded received frames") \ 345 m(n, p, +1, u64, device_stall_minor_watermark, \ 346 "device_stall_minor_watermark", "Device stall minor watermark") \ 347 m(n, p, +1, u64, device_stall_critical_watermark, \ 348 "device_stall_critical_watermark", "Device stall critical watermark") 349 350#define MLX5E_PPORT_PER_PRIO_STATS_PREFIX(m,p,c,t,f,s,d) \ 351 m(c, t, pri_##p##_##f, "prio" #p "_" s, "Priority " #p " - " d) 352 353#define MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO 8 354 355#define MLX5E_PPORT_PER_PRIO_STATS(m) \ 356 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,0) \ 357 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,1) \ 358 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,2) \ 359 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,3) \ 360 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,4) \ 361 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,5) \ 362 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,6) \ 363 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,7) 364 365/* 366 * Make sure to update mlx5e_update_pport_counters() 367 * when adding a new MLX5E_PPORT_STATS block 368 */ 369#define MLX5E_PPORT_STATS(m) \ 370 MLX5E_PPORT_PER_PRIO_STATS(m) \ 371 MLX5E_PPORT_IEEE802_3_STATS(m) \ 372 MLX5E_PPORT_RFC2819_STATS(m) 373 374#define MLX5E_PORT_STATS_DEBUG(m) \ 375 MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 376 MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 377 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \ 378 MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(m) 379 380#define MLX5E_PPORT_IEEE802_3_STATS_NUM \ 381 (0 MLX5E_PPORT_IEEE802_3_STATS(MLX5E_STATS_COUNT)) 382#define MLX5E_PPORT_RFC2819_STATS_NUM \ 383 (0 MLX5E_PPORT_RFC2819_STATS(MLX5E_STATS_COUNT)) 384#define MLX5E_PPORT_STATS_NUM \ 385 (0 MLX5E_PPORT_STATS(MLX5E_STATS_COUNT)) 386 387#define MLX5E_PPORT_PER_PRIO_STATS_NUM \ 388 (0 MLX5E_PPORT_PER_PRIO_STATS(MLX5E_STATS_COUNT)) 389#define MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM \ 390 (0 MLX5E_PPORT_RFC2819_STATS_DEBUG(MLX5E_STATS_COUNT)) 391#define MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM \ 392 (0 MLX5E_PPORT_RFC2863_STATS_DEBUG(MLX5E_STATS_COUNT)) 393#define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM \ 394 (0 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(MLX5E_STATS_COUNT)) 395#define MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM \ 396 (0 MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(MLX5E_STATS_COUNT)) 397#define MLX5E_PORT_STATS_DEBUG_NUM \ 398 (0 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_COUNT)) 399 400struct mlx5e_pport_stats { 401 struct sysctl_ctx_list ctx; 402 u64 arg [0]; 403 MLX5E_PPORT_STATS(MLX5E_STATS_VAR) 404}; 405 406struct mlx5e_port_stats_debug { 407 struct sysctl_ctx_list ctx; 408 u64 arg [0]; 409 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_VAR) 410}; 411 412#define MLX5E_RQ_STATS(m) \ 413 m(+1, u64, packets, "packets", "Received packets") \ 414 m(+1, u64, bytes, "bytes", "Received bytes") \ 415 m(+1, u64, csum_none, "csum_none", "Received packets") \ 416 m(+1, u64, lro_packets, "lro_packets", "Received LRO packets") \ 417 m(+1, u64, lro_bytes, "lro_bytes", "Received LRO bytes") \ 418 m(+1, u64, sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 419 m(+1, u64, sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 420 m(+1, u64, wqe_err, "wqe_err", "Received packets") 421 422#define MLX5E_RQ_STATS_NUM (0 MLX5E_RQ_STATS(MLX5E_STATS_COUNT)) 423 424struct mlx5e_rq_stats { 425 struct sysctl_ctx_list ctx; 426 u64 arg [0]; 427 MLX5E_RQ_STATS(MLX5E_STATS_VAR) 428}; 429 430#define MLX5E_SQ_STATS(m) \ 431 m(+1, u64, packets, "packets", "Transmitted packets") \ 432 m(+1, u64, bytes, "bytes", "Transmitted bytes") \ 433 m(+1, u64, tso_packets, "tso_packets", "Transmitted packets") \ 434 m(+1, u64, tso_bytes, "tso_bytes", "Transmitted bytes") \ 435 m(+1, u64, csum_offload_none, "csum_offload_none", "Transmitted packets") \ 436 m(+1, u64, defragged, "defragged", "Transmitted packets") \ 437 m(+1, u64, dropped, "dropped", "Transmitted packets") \ 438 m(+1, u64, nop, "nop", "Transmitted packets") 439 440#define MLX5E_SQ_STATS_NUM (0 MLX5E_SQ_STATS(MLX5E_STATS_COUNT)) 441 442struct mlx5e_sq_stats { 443 struct sysctl_ctx_list ctx; 444 u64 arg [0]; 445 MLX5E_SQ_STATS(MLX5E_STATS_VAR) 446}; 447 448struct mlx5e_stats { 449 struct mlx5e_vport_stats vport; 450 struct mlx5e_pport_stats pport; 451 struct mlx5e_port_stats_debug port_stats_debug; 452}; 453 454struct mlx5e_rq_param { 455 u32 rqc [MLX5_ST_SZ_DW(rqc)]; 456 struct mlx5_wq_param wq; 457}; 458 459struct mlx5e_sq_param { 460 u32 sqc [MLX5_ST_SZ_DW(sqc)]; 461 struct mlx5_wq_param wq; 462}; 463 464struct mlx5e_cq_param { 465 u32 cqc [MLX5_ST_SZ_DW(cqc)]; 466 struct mlx5_wq_param wq; 467}; 468 469struct mlx5e_params { 470 u8 log_sq_size; 471 u8 log_rq_size; 472 u16 num_channels; 473 u8 default_vlan_prio; 474 u8 num_tc; 475 u8 rx_cq_moderation_mode; 476 u8 tx_cq_moderation_mode; 477 u16 rx_cq_moderation_usec; 478 u16 rx_cq_moderation_pkts; 479 u16 tx_cq_moderation_usec; 480 u16 tx_cq_moderation_pkts; 481 u16 min_rx_wqes; 482 bool hw_lro_en; 483 bool cqe_zipping_en; 484 u32 lro_wqe_sz; 485 u16 rx_hash_log_tbl_sz; 486 u32 tx_pauseframe_control __aligned(4); 487 u32 rx_pauseframe_control __aligned(4); 488 u16 tx_max_inline; 489 u8 tx_min_inline_mode; 490 u8 tx_priority_flow_control; 491 u8 rx_priority_flow_control; 492 u8 channels_rsss; 493}; 494 495#define MLX5E_PARAMS(m) \ 496 m(+1, u64, tx_queue_size_max, "tx_queue_size_max", "Max send queue size") \ 497 m(+1, u64, rx_queue_size_max, "rx_queue_size_max", "Max receive queue size") \ 498 m(+1, u64, tx_queue_size, "tx_queue_size", "Default send queue size") \ 499 m(+1, u64, rx_queue_size, "rx_queue_size", "Default receive queue size") \ 500 m(+1, u64, channels, "channels", "Default number of channels") \ 501 m(+1, u64, channels_rsss, "channels_rsss", "Default channels receive side scaling stride") \ 502 m(+1, u64, coalesce_usecs_max, "coalesce_usecs_max", "Maximum usecs for joining packets") \ 503 m(+1, u64, coalesce_pkts_max, "coalesce_pkts_max", "Maximum packets to join") \ 504 m(+1, u64, rx_coalesce_usecs, "rx_coalesce_usecs", "Limit in usec for joining rx packets") \ 505 m(+1, u64, rx_coalesce_pkts, "rx_coalesce_pkts", "Maximum number of rx packets to join") \ 506 m(+1, u64, rx_coalesce_mode, "rx_coalesce_mode", "0: EQE fixed mode 1: CQE fixed mode 2: EQE auto mode 3: CQE auto mode") \ 507 m(+1, u64, tx_coalesce_usecs, "tx_coalesce_usecs", "Limit in usec for joining tx packets") \ 508 m(+1, u64, tx_coalesce_pkts, "tx_coalesce_pkts", "Maximum number of tx packets to join") \ 509 m(+1, u64, tx_coalesce_mode, "tx_coalesce_mode", "0: EQE mode 1: CQE mode") \ 510 m(+1, u64, tx_completion_fact, "tx_completion_fact", "1..MAX: Completion event ratio") \ 511 m(+1, u64, tx_completion_fact_max, "tx_completion_fact_max", "Maximum completion event ratio") \ 512 m(+1, u64, hw_lro, "hw_lro", "set to enable hw_lro") \ 513 m(+1, u64, cqe_zipping, "cqe_zipping", "0 : CQE zipping disabled") \ 514 m(+1, u64, modify_tx_dma, "modify_tx_dma", "0: Enable TX 1: Disable TX") \ 515 m(+1, u64, modify_rx_dma, "modify_rx_dma", "0: Enable RX 1: Disable RX") \ 516 m(+1, u64, diag_pci_enable, "diag_pci_enable", "0: Disabled 1: Enabled") \ 517 m(+1, u64, diag_general_enable, "diag_general_enable", "0: Disabled 1: Enabled") \ 518 m(+1, u64, hw_mtu, "hw_mtu", "Current hardware MTU value") \ 519 m(+1, u64, mc_local_lb, "mc_local_lb", "0: Local multicast loopback enabled 1: Disabled") \ 520 m(+1, u64, uc_local_lb, "uc_local_lb", "0: Local unicast loopback enabled 1: Disabled") 521 522#define MLX5E_PARAMS_NUM (0 MLX5E_PARAMS(MLX5E_STATS_COUNT)) 523 524struct mlx5e_params_ethtool { 525 u64 arg [0]; 526 MLX5E_PARAMS(MLX5E_STATS_VAR) 527 u64 max_bw_value[IEEE_8021QAZ_MAX_TCS]; 528 u8 max_bw_share[IEEE_8021QAZ_MAX_TCS]; 529 u8 prio_tc[MLX5E_MAX_PRIORITY]; 530 u8 dscp2prio[MLX5_MAX_SUPPORTED_DSCP]; 531 u8 trust_state; 532}; 533 534/* EEPROM Standards for plug in modules */ 535#ifndef MLX5E_ETH_MODULE_SFF_8472 536#define MLX5E_ETH_MODULE_SFF_8472 0x1 537#define MLX5E_ETH_MODULE_SFF_8472_LEN 128 538#endif 539 540#ifndef MLX5E_ETH_MODULE_SFF_8636 541#define MLX5E_ETH_MODULE_SFF_8636 0x2 542#define MLX5E_ETH_MODULE_SFF_8636_LEN 256 543#endif 544 545#ifndef MLX5E_ETH_MODULE_SFF_8436 546#define MLX5E_ETH_MODULE_SFF_8436 0x3 547#define MLX5E_ETH_MODULE_SFF_8436_LEN 256 548#endif 549 550/* EEPROM I2C Addresses */ 551#define MLX5E_I2C_ADDR_LOW 0x50 552#define MLX5E_I2C_ADDR_HIGH 0x51 553 554#define MLX5E_EEPROM_LOW_PAGE 0x0 555#define MLX5E_EEPROM_HIGH_PAGE 0x3 556 557#define MLX5E_EEPROM_HIGH_PAGE_OFFSET 128 558#define MLX5E_EEPROM_PAGE_LENGTH 256 559 560#define MLX5E_EEPROM_INFO_BYTES 0x3 561 562struct mlx5e_cq { 563 /* data path - accessed per cqe */ 564 struct mlx5_cqwq wq; 565 566 /* data path - accessed per HW polling */ 567 struct mlx5_core_cq mcq; 568 569 /* control */ 570 struct mlx5e_priv *priv; 571 struct mlx5_wq_ctrl wq_ctrl; 572} __aligned(MLX5E_CACHELINE_SIZE); 573 574struct mlx5e_rq_mbuf { 575 bus_dmamap_t dma_map; 576 caddr_t data; 577 struct mbuf *mbuf; 578}; 579 580struct mlx5e_rq { 581 /* data path */ 582 struct mlx5_wq_ll wq; 583 struct mtx mtx; 584 bus_dma_tag_t dma_tag; 585 u32 wqe_sz; 586 u32 nsegs; 587 struct mlx5e_rq_mbuf *mbuf; 588 struct ifnet *ifp; 589 struct mlx5e_rq_stats stats; 590 struct mlx5e_cq cq; 591 struct lro_ctrl lro; 592 volatile int enabled; 593 int ix; 594 595 /* Dynamic Interrupt Moderation */ 596 struct net_dim dim; 597 598 /* control */ 599 struct mlx5_wq_ctrl wq_ctrl; 600 u32 rqn; 601 struct mlx5e_channel *channel; 602 struct callout watchdog; 603} __aligned(MLX5E_CACHELINE_SIZE); 604 605struct mlx5e_sq_mbuf { 606 bus_dmamap_t dma_map; 607 struct mbuf *mbuf; 608 u32 num_bytes; 609 u32 num_wqebbs; 610}; 611 612enum { 613 MLX5E_SQ_READY, 614 MLX5E_SQ_FULL 615}; 616 617struct mlx5e_sq { 618 /* data path */ 619 struct mtx lock; 620 bus_dma_tag_t dma_tag; 621 struct mtx comp_lock; 622 623 /* dirtied @completion */ 624 u16 cc; 625 626 /* dirtied @xmit */ 627 u16 pc __aligned(MLX5E_CACHELINE_SIZE); 628 u16 bf_offset; 629 u16 cev_counter; /* completion event counter */ 630 u16 cev_factor; /* completion event factor */ 631 u16 cev_next_state; /* next completion event state */ 632#define MLX5E_CEV_STATE_INITIAL 0 /* timer not started */ 633#define MLX5E_CEV_STATE_SEND_NOPS 1 /* send NOPs */ 634#define MLX5E_CEV_STATE_HOLD_NOPS 2 /* don't send NOPs yet */ 635 u16 running; /* set if SQ is running */ 636 struct callout cev_callout; 637 union { 638 u32 d32[2]; 639 u64 d64; 640 } doorbell; 641 struct mlx5e_sq_stats stats; 642 643 struct mlx5e_cq cq; 644 645 /* pointers to per packet info: write@xmit, read@completion */ 646 struct mlx5e_sq_mbuf *mbuf; 647 struct buf_ring *br; 648 649 /* read only */ 650 struct mlx5_wq_cyc wq; 651 struct mlx5_uar uar; 652 struct ifnet *ifp; 653 u32 sqn; 654 u32 bf_buf_size; 655 u32 mkey_be; 656 u16 max_inline; 657 u8 min_inline_mode; 658 u8 min_insert_caps; 659#define MLX5E_INSERT_VLAN 1 660#define MLX5E_INSERT_NON_VLAN 2 661 662 /* control path */ 663 struct mlx5_wq_ctrl wq_ctrl; 664 struct mlx5e_priv *priv; 665 int tc; 666} __aligned(MLX5E_CACHELINE_SIZE); 667 668static inline bool 669mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) 670{ 671 u16 cc = sq->cc; 672 u16 pc = sq->pc; 673 674 return ((sq->wq.sz_m1 & (cc - pc)) >= n || cc == pc); 675} 676 677struct mlx5e_channel { 678 /* data path */ 679 struct mlx5e_rq rq; 680 struct mlx5e_sq sq[MLX5E_MAX_TX_NUM_TC]; 681 struct ifnet *ifp; 682 u32 mkey_be; 683 u8 num_tc; 684 685 /* control */ 686 struct mlx5e_priv *priv; 687 int ix; 688 int cpu; 689} __aligned(MLX5E_CACHELINE_SIZE); 690 691enum mlx5e_traffic_types { 692 MLX5E_TT_IPV4_TCP, 693 MLX5E_TT_IPV6_TCP, 694 MLX5E_TT_IPV4_UDP, 695 MLX5E_TT_IPV6_UDP, 696 MLX5E_TT_IPV4_IPSEC_AH, 697 MLX5E_TT_IPV6_IPSEC_AH, 698 MLX5E_TT_IPV4_IPSEC_ESP, 699 MLX5E_TT_IPV6_IPSEC_ESP, 700 MLX5E_TT_IPV4, 701 MLX5E_TT_IPV6, 702 MLX5E_TT_ANY, 703 MLX5E_NUM_TT, 704}; 705 706enum { 707 MLX5E_RQT_SPREADING = 0, 708 MLX5E_RQT_DEFAULT_RQ = 1, 709 MLX5E_NUM_RQT = 2, 710}; 711 712struct mlx5_flow_rule; 713 714struct mlx5e_eth_addr_info { 715 u8 addr [ETH_ALEN + 2]; 716 u32 tt_vec; 717 /* flow table rule per traffic type */ 718 struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT]; 719}; 720 721#define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE) 722 723struct mlx5e_eth_addr_hash_node; 724 725struct mlx5e_eth_addr_hash_head { 726 struct mlx5e_eth_addr_hash_node *lh_first; 727}; 728 729struct mlx5e_eth_addr_db { 730 struct mlx5e_eth_addr_hash_head if_uc[MLX5E_ETH_ADDR_HASH_SIZE]; 731 struct mlx5e_eth_addr_hash_head if_mc[MLX5E_ETH_ADDR_HASH_SIZE]; 732 struct mlx5e_eth_addr_info broadcast; 733 struct mlx5e_eth_addr_info allmulti; 734 struct mlx5e_eth_addr_info promisc; 735 bool broadcast_enabled; 736 bool allmulti_enabled; 737 bool promisc_enabled; 738}; 739 740enum { 741 MLX5E_STATE_ASYNC_EVENTS_ENABLE, 742 MLX5E_STATE_OPENED, 743}; 744 745enum { 746 MLX5_BW_NO_LIMIT = 0, 747 MLX5_100_MBPS_UNIT = 3, 748 MLX5_GBPS_UNIT = 4, 749}; 750 751struct mlx5e_vlan_db { 752 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 753 struct mlx5_flow_rule *active_vlans_ft_rule[VLAN_N_VID]; 754 struct mlx5_flow_rule *untagged_ft_rule; 755 struct mlx5_flow_rule *any_cvlan_ft_rule; 756 struct mlx5_flow_rule *any_svlan_ft_rule; 757 bool filter_disabled; 758}; 759 760struct mlx5e_flow_table { 761 int num_groups; 762 struct mlx5_flow_table *t; 763 struct mlx5_flow_group **g; 764}; 765 766struct mlx5e_flow_tables { 767 struct mlx5_flow_namespace *ns; 768 struct mlx5e_flow_table vlan; 769 struct mlx5e_flow_table main; 770 struct mlx5e_flow_table inner_rss; 771}; 772 773struct mlx5e_priv { 774 struct mlx5_core_dev *mdev; /* must be first */ 775 776 /* priv data path fields - start */ 777 int order_base_2_num_channels; 778 int queue_mapping_channel_mask; 779 int num_tc; 780 int default_vlan_prio; 781 /* priv data path fields - end */ 782 783 unsigned long state; 784 int gone; 785#define PRIV_LOCK(priv) sx_xlock(&(priv)->state_lock) 786#define PRIV_UNLOCK(priv) sx_xunlock(&(priv)->state_lock) 787#define PRIV_LOCKED(priv) sx_xlocked(&(priv)->state_lock) 788 struct sx state_lock; /* Protects Interface state */ 789 struct mlx5_uar cq_uar; 790 u32 pdn; 791 u32 tdn; 792 struct mlx5_core_mr mr; 793 794 u32 tisn[MLX5E_MAX_TX_NUM_TC]; 795 u32 rqtn; 796 u32 tirn[MLX5E_NUM_TT]; 797 798 struct mlx5e_flow_tables fts; 799 struct mlx5e_eth_addr_db eth_addr; 800 struct mlx5e_vlan_db vlan; 801 802 struct mlx5e_params params; 803 struct mlx5e_params_ethtool params_ethtool; 804 union mlx5_core_pci_diagnostics params_pci; 805 union mlx5_core_general_diagnostics params_general; 806 struct mtx async_events_mtx; /* sync hw events */ 807 struct work_struct update_stats_work; 808 struct work_struct update_carrier_work; 809 struct work_struct set_rx_mode_work; 810 MLX5_DECLARE_DOORBELL_LOCK(doorbell_lock) 811 812 struct ifnet *ifp; 813 struct sysctl_ctx_list sysctl_ctx; 814 struct sysctl_oid *sysctl_ifnet; 815 struct sysctl_oid *sysctl_hw; 816 int sysctl_debug; 817 struct mlx5e_stats stats; 818 int counter_set_id; 819 820 struct workqueue_struct *wq; 821 822 eventhandler_tag vlan_detach; 823 eventhandler_tag vlan_attach; 824 struct ifmedia media; 825 int media_status_last; 826 int media_active_last; 827 828 struct callout watchdog; 829 830 struct mlx5e_channel channel[]; 831}; 832 833#define MLX5E_NET_IP_ALIGN 2 834 835struct mlx5e_tx_wqe { 836 struct mlx5_wqe_ctrl_seg ctrl; 837 struct mlx5_wqe_eth_seg eth; 838}; 839 840struct mlx5e_rx_wqe { 841 struct mlx5_wqe_srq_next_seg next; 842 struct mlx5_wqe_data_seg data[]; 843}; 844 845/* the size of the structure above must be power of two */ 846CTASSERT(powerof2(sizeof(struct mlx5e_rx_wqe))); 847 848struct mlx5e_eeprom { 849 int lock_bit; 850 int i2c_addr; 851 int page_num; 852 int device_addr; 853 int module_num; 854 int len; 855 int type; 856 int page_valid; 857 u32 *data; 858}; 859 860#define MLX5E_FLD_MAX(typ, fld) ((1ULL << __mlx5_bit_sz(typ, fld)) - 1ULL) 861 862int mlx5e_xmit(struct ifnet *, struct mbuf *); 863 864int mlx5e_open_locked(struct ifnet *); 865int mlx5e_close_locked(struct ifnet *); 866 867void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, int event); 868void mlx5e_rx_cq_comp(struct mlx5_core_cq *); 869void mlx5e_tx_cq_comp(struct mlx5_core_cq *); 870struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); 871 872void mlx5e_dim_work(struct work_struct *); 873void mlx5e_dim_build_cq_param(struct mlx5e_priv *, struct mlx5e_cq_param *); 874 875int mlx5e_open_flow_table(struct mlx5e_priv *priv); 876void mlx5e_close_flow_table(struct mlx5e_priv *priv); 877void mlx5e_set_rx_mode_core(struct mlx5e_priv *priv); 878void mlx5e_set_rx_mode_work(struct work_struct *work); 879 880void mlx5e_vlan_rx_add_vid(void *, struct ifnet *, u16); 881void mlx5e_vlan_rx_kill_vid(void *, struct ifnet *, u16); 882void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); 883void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); 884int mlx5e_add_all_vlan_rules(struct mlx5e_priv *priv); 885void mlx5e_del_all_vlan_rules(struct mlx5e_priv *priv); 886 887static inline void 888mlx5e_tx_notify_hw(struct mlx5e_sq *sq, u32 *wqe, int bf_sz) 889{ 890 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; 891 892 /* ensure wqe is visible to device before updating doorbell record */ 893 wmb(); 894 895 *sq->wq.db = cpu_to_be32(sq->pc); 896 897 /* 898 * Ensure the doorbell record is visible to device before ringing 899 * the doorbell: 900 */ 901 wmb(); 902 903 if (bf_sz) { 904 __iowrite64_copy(sq->uar.bf_map + ofst, wqe, bf_sz); 905 906 /* flush the write-combining mapped buffer */ 907 wmb(); 908 909 } else { 910 mlx5_write64(wqe, sq->uar.map + ofst, 911 MLX5_GET_DOORBELL_LOCK(&sq->priv->doorbell_lock)); 912 } 913 914 sq->bf_offset ^= sq->bf_buf_size; 915} 916 917static inline void 918mlx5e_cq_arm(struct mlx5e_cq *cq, spinlock_t *dblock) 919{ 920 struct mlx5_core_cq *mcq; 921 922 mcq = &cq->mcq; 923 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, dblock, cq->wq.cc); 924} 925 926extern const struct ethtool_ops mlx5e_ethtool_ops; 927void mlx5e_create_ethtool(struct mlx5e_priv *); 928void mlx5e_create_stats(struct sysctl_ctx_list *, 929 struct sysctl_oid_list *, const char *, 930 const char **, unsigned, u64 *); 931void mlx5e_send_nop(struct mlx5e_sq *, u32); 932void mlx5e_sq_cev_timeout(void *); 933int mlx5e_refresh_channel_params(struct mlx5e_priv *); 934int mlx5e_open_cq(struct mlx5e_priv *, struct mlx5e_cq_param *, 935 struct mlx5e_cq *, mlx5e_cq_comp_t *, int eq_ix); 936void mlx5e_close_cq(struct mlx5e_cq *); 937void mlx5e_free_sq_db(struct mlx5e_sq *); 938int mlx5e_alloc_sq_db(struct mlx5e_sq *); 939int mlx5e_enable_sq(struct mlx5e_sq *, struct mlx5e_sq_param *, int tis_num); 940int mlx5e_modify_sq(struct mlx5e_sq *, int curr_state, int next_state); 941void mlx5e_disable_sq(struct mlx5e_sq *); 942void mlx5e_drain_sq(struct mlx5e_sq *); 943void mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value); 944void mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value); 945void mlx5e_resume_sq(struct mlx5e_sq *sq); 946void mlx5e_update_sq_inline(struct mlx5e_sq *sq); 947void mlx5e_refresh_sq_inline(struct mlx5e_priv *priv); 948 949#endif /* _MLX5_EN_H_ */ 950