en.h revision 347796
1/*- 2 * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_en/en.h 347796 2019-05-16 17:09:06Z hselasky $ 26 */ 27 28#ifndef _MLX5_EN_H_ 29#define _MLX5_EN_H_ 30 31#include <linux/kmod.h> 32#include <linux/page.h> 33#include <linux/slab.h> 34#include <linux/if_vlan.h> 35#include <linux/if_ether.h> 36#include <linux/vmalloc.h> 37#include <linux/moduleparam.h> 38#include <linux/delay.h> 39#include <linux/netdevice.h> 40#include <linux/etherdevice.h> 41#include <linux/ktime.h> 42#include <linux/net_dim.h> 43 44#include <netinet/in_systm.h> 45#include <netinet/in.h> 46#include <netinet/if_ether.h> 47#include <netinet/ip.h> 48#include <netinet/ip6.h> 49#include <netinet/tcp.h> 50#include <netinet/tcp_lro.h> 51#include <netinet/udp.h> 52#include <net/ethernet.h> 53#include <sys/buf_ring.h> 54 55#include "opt_rss.h" 56 57#ifdef RSS 58#include <net/rss_config.h> 59#include <netinet/in_rss.h> 60#endif 61 62#include <machine/bus.h> 63 64#include <dev/mlx5/driver.h> 65#include <dev/mlx5/qp.h> 66#include <dev/mlx5/cq.h> 67#include <dev/mlx5/port.h> 68#include <dev/mlx5/vport.h> 69#include <dev/mlx5/diagnostics.h> 70 71#include <dev/mlx5/mlx5_core/wq.h> 72#include <dev/mlx5/mlx5_core/transobj.h> 73#include <dev/mlx5/mlx5_core/mlx5_core.h> 74 75#define IEEE_8021QAZ_MAX_TCS 8 76 77#define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x7 78#define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa 79#define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xe 80 81#define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x7 82#define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa 83#define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xe 84 85#define MLX5E_MAX_RX_SEGS 7 86 87#ifndef MLX5E_MAX_RX_BYTES 88#define MLX5E_MAX_RX_BYTES MCLBYTES 89#endif 90 91#if (MLX5E_MAX_RX_SEGS == 1) 92/* FreeBSD HW LRO is limited by 16KB - the size of max mbuf */ 93#define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ MJUM16BYTES 94#else 95#define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ \ 96 MIN(65535, MLX5E_MAX_RX_SEGS * MLX5E_MAX_RX_BYTES) 97#endif 98#define MLX5E_DIM_DEFAULT_PROFILE 3 99#define MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO 16 100#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 101#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 102#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 103#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 104#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 105#define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 106#define MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ 0x7 107#define MLX5E_CACHELINE_SIZE CACHE_LINE_SIZE 108#define MLX5E_HW2SW_MTU(hwmtu) \ 109 ((hwmtu) - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 110#define MLX5E_SW2HW_MTU(swmtu) \ 111 ((swmtu) + (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 112#define MLX5E_SW2MB_MTU(swmtu) \ 113 (MLX5E_SW2HW_MTU(swmtu) + MLX5E_NET_IP_ALIGN) 114#define MLX5E_MTU_MIN 72 /* Min MTU allowed by the kernel */ 115#define MLX5E_MTU_MAX MIN(ETHERMTU_JUMBO, MJUM16BYTES) /* Max MTU of Ethernet 116 * jumbo frames */ 117 118#define MLX5E_BUDGET_MAX 8192 /* RX and TX */ 119#define MLX5E_RX_BUDGET_MAX 256 120#define MLX5E_SQ_BF_BUDGET 16 121#define MLX5E_SQ_TX_QUEUE_SIZE 4096 /* SQ drbr queue size */ 122 123#define MLX5E_MAX_TX_NUM_TC 8 /* units */ 124#define MLX5E_MAX_TX_HEADER 128 /* bytes */ 125#define MLX5E_MAX_TX_PAYLOAD_SIZE 65536 /* bytes */ 126#define MLX5E_MAX_TX_MBUF_SIZE 65536 /* bytes */ 127#define MLX5E_MAX_TX_MBUF_FRAGS \ 128 ((MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS) - \ 129 (MLX5E_MAX_TX_HEADER / MLX5_SEND_WQE_DS) - \ 130 1 /* the maximum value of the DS counter is 0x3F and not 0x40 */) /* units */ 131#define MLX5E_MAX_TX_INLINE \ 132 (MLX5E_MAX_TX_HEADER - sizeof(struct mlx5e_tx_wqe) + \ 133 sizeof(((struct mlx5e_tx_wqe *)0)->eth.inline_hdr_start)) /* bytes */ 134 135#define MLX5E_100MB (100000) 136#define MLX5E_1GB (1000000) 137 138MALLOC_DECLARE(M_MLX5EN); 139 140struct mlx5_core_dev; 141struct mlx5e_cq; 142 143typedef void (mlx5e_cq_comp_t)(struct mlx5_core_cq *); 144 145#define MLX5E_STATS_COUNT(a,b,c,d) a 146#define MLX5E_STATS_VAR(a,b,c,d) b; 147#define MLX5E_STATS_DESC(a,b,c,d) c, d, 148 149#define MLX5E_VPORT_STATS(m) \ 150 /* HW counters */ \ 151 m(+1, u64 rx_packets, "rx_packets", "Received packets") \ 152 m(+1, u64 rx_bytes, "rx_bytes", "Received bytes") \ 153 m(+1, u64 tx_packets, "tx_packets", "Transmitted packets") \ 154 m(+1, u64 tx_bytes, "tx_bytes", "Transmitted bytes") \ 155 m(+1, u64 rx_error_packets, "rx_error_packets", "Received error packets") \ 156 m(+1, u64 rx_error_bytes, "rx_error_bytes", "Received error bytes") \ 157 m(+1, u64 tx_error_packets, "tx_error_packets", "Transmitted error packets") \ 158 m(+1, u64 tx_error_bytes, "tx_error_bytes", "Transmitted error bytes") \ 159 m(+1, u64 rx_unicast_packets, "rx_unicast_packets", "Received unicast packets") \ 160 m(+1, u64 rx_unicast_bytes, "rx_unicast_bytes", "Received unicast bytes") \ 161 m(+1, u64 tx_unicast_packets, "tx_unicast_packets", "Transmitted unicast packets") \ 162 m(+1, u64 tx_unicast_bytes, "tx_unicast_bytes", "Transmitted unicast bytes") \ 163 m(+1, u64 rx_multicast_packets, "rx_multicast_packets", "Received multicast packets") \ 164 m(+1, u64 rx_multicast_bytes, "rx_multicast_bytes", "Received multicast bytes") \ 165 m(+1, u64 tx_multicast_packets, "tx_multicast_packets", "Transmitted multicast packets") \ 166 m(+1, u64 tx_multicast_bytes, "tx_multicast_bytes", "Transmitted multicast bytes") \ 167 m(+1, u64 rx_broadcast_packets, "rx_broadcast_packets", "Received broadcast packets") \ 168 m(+1, u64 rx_broadcast_bytes, "rx_broadcast_bytes", "Received broadcast bytes") \ 169 m(+1, u64 tx_broadcast_packets, "tx_broadcast_packets", "Transmitted broadcast packets") \ 170 m(+1, u64 tx_broadcast_bytes, "tx_broadcast_bytes", "Transmitted broadcast bytes") \ 171 m(+1, u64 rx_out_of_buffer, "rx_out_of_buffer", "Receive out of buffer, no recv wqes events") \ 172 /* SW counters */ \ 173 m(+1, u64 tso_packets, "tso_packets", "Transmitted TSO packets") \ 174 m(+1, u64 tso_bytes, "tso_bytes", "Transmitted TSO bytes") \ 175 m(+1, u64 lro_packets, "lro_packets", "Received LRO packets") \ 176 m(+1, u64 lro_bytes, "lro_bytes", "Received LRO bytes") \ 177 m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 178 m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 179 m(+1, u64 rx_csum_good, "rx_csum_good", "Received checksum valid packets") \ 180 m(+1, u64 rx_csum_none, "rx_csum_none", "Received no checksum packets") \ 181 m(+1, u64 tx_csum_offload, "tx_csum_offload", "Transmit checksum offload packets") \ 182 m(+1, u64 tx_queue_dropped, "tx_queue_dropped", "Transmit queue dropped") \ 183 m(+1, u64 tx_defragged, "tx_defragged", "Transmit queue defragged") \ 184 m(+1, u64 rx_wqe_err, "rx_wqe_err", "Receive WQE errors") \ 185 m(+1, u64 tx_jumbo_packets, "tx_jumbo_packets", "TX packets greater than 1518 octets") 186 187#define MLX5E_VPORT_STATS_NUM (0 MLX5E_VPORT_STATS(MLX5E_STATS_COUNT)) 188 189struct mlx5e_vport_stats { 190 struct sysctl_ctx_list ctx; 191 u64 arg [0]; 192 MLX5E_VPORT_STATS(MLX5E_STATS_VAR) 193 u32 rx_out_of_buffer_prev; 194}; 195 196#define MLX5E_PPORT_IEEE802_3_STATS(m) \ 197 m(+1, u64 frames_tx, "frames_tx", "Frames transmitted") \ 198 m(+1, u64 frames_rx, "frames_rx", "Frames received") \ 199 m(+1, u64 check_seq_err, "check_seq_err", "Sequence errors") \ 200 m(+1, u64 alignment_err, "alignment_err", "Alignment errors") \ 201 m(+1, u64 octets_tx, "octets_tx", "Bytes transmitted") \ 202 m(+1, u64 octets_received, "octets_received", "Bytes received") \ 203 m(+1, u64 multicast_xmitted, "multicast_xmitted", "Multicast transmitted") \ 204 m(+1, u64 broadcast_xmitted, "broadcast_xmitted", "Broadcast transmitted") \ 205 m(+1, u64 multicast_rx, "multicast_rx", "Multicast received") \ 206 m(+1, u64 broadcast_rx, "broadcast_rx", "Broadcast received") \ 207 m(+1, u64 in_range_len_errors, "in_range_len_errors", "In range length errors") \ 208 m(+1, u64 out_of_range_len, "out_of_range_len", "Out of range length errors") \ 209 m(+1, u64 too_long_errors, "too_long_errors", "Too long errors") \ 210 m(+1, u64 symbol_err, "symbol_err", "Symbol errors") \ 211 m(+1, u64 mac_control_tx, "mac_control_tx", "MAC control transmitted") \ 212 m(+1, u64 mac_control_rx, "mac_control_rx", "MAC control received") \ 213 m(+1, u64 unsupported_op_rx, "unsupported_op_rx", "Unsupported operation received") \ 214 m(+1, u64 pause_ctrl_rx, "pause_ctrl_rx", "Pause control received") \ 215 m(+1, u64 pause_ctrl_tx, "pause_ctrl_tx", "Pause control transmitted") 216 217#define MLX5E_PPORT_RFC2819_STATS(m) \ 218 m(+1, u64 drop_events, "drop_events", "Dropped events") \ 219 m(+1, u64 octets, "octets", "Octets") \ 220 m(+1, u64 pkts, "pkts", "Packets") \ 221 m(+1, u64 broadcast_pkts, "broadcast_pkts", "Broadcast packets") \ 222 m(+1, u64 multicast_pkts, "multicast_pkts", "Multicast packets") \ 223 m(+1, u64 crc_align_errors, "crc_align_errors", "CRC alignment errors") \ 224 m(+1, u64 undersize_pkts, "undersize_pkts", "Undersized packets") \ 225 m(+1, u64 oversize_pkts, "oversize_pkts", "Oversized packets") \ 226 m(+1, u64 fragments, "fragments", "Fragments") \ 227 m(+1, u64 jabbers, "jabbers", "Jabbers") \ 228 m(+1, u64 collisions, "collisions", "Collisions") 229 230#define MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 231 m(+1, u64 p64octets, "p64octets", "Bytes") \ 232 m(+1, u64 p65to127octets, "p65to127octets", "Bytes") \ 233 m(+1, u64 p128to255octets, "p128to255octets", "Bytes") \ 234 m(+1, u64 p256to511octets, "p256to511octets", "Bytes") \ 235 m(+1, u64 p512to1023octets, "p512to1023octets", "Bytes") \ 236 m(+1, u64 p1024to1518octets, "p1024to1518octets", "Bytes") \ 237 m(+1, u64 p1519to2047octets, "p1519to2047octets", "Bytes") \ 238 m(+1, u64 p2048to4095octets, "p2048to4095octets", "Bytes") \ 239 m(+1, u64 p4096to8191octets, "p4096to8191octets", "Bytes") \ 240 m(+1, u64 p8192to10239octets, "p8192to10239octets", "Bytes") 241 242#define MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 243 m(+1, u64 in_octets, "in_octets", "In octets") \ 244 m(+1, u64 in_ucast_pkts, "in_ucast_pkts", "In unicast packets") \ 245 m(+1, u64 in_discards, "in_discards", "In discards") \ 246 m(+1, u64 in_errors, "in_errors", "In errors") \ 247 m(+1, u64 in_unknown_protos, "in_unknown_protos", "In unknown protocols") \ 248 m(+1, u64 out_octets, "out_octets", "Out octets") \ 249 m(+1, u64 out_ucast_pkts, "out_ucast_pkts", "Out unicast packets") \ 250 m(+1, u64 out_discards, "out_discards", "Out discards") \ 251 m(+1, u64 out_errors, "out_errors", "Out errors") \ 252 m(+1, u64 in_multicast_pkts, "in_multicast_pkts", "In multicast packets") \ 253 m(+1, u64 in_broadcast_pkts, "in_broadcast_pkts", "In broadcast packets") \ 254 m(+1, u64 out_multicast_pkts, "out_multicast_pkts", "Out multicast packets") \ 255 m(+1, u64 out_broadcast_pkts, "out_broadcast_pkts", "Out broadcast packets") 256 257#define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \ 258 m(+1, u64 time_since_last_clear, "time_since_last_clear", \ 259 "Time since the last counters clear event (msec)") \ 260 m(+1, u64 symbol_errors, "symbol_errors", "Symbol errors") \ 261 m(+1, u64 sync_headers_errors, "sync_headers_errors", "Sync header error counter") \ 262 m(+1, u64 bip_errors_lane0, "edpl_bip_errors_lane0", \ 263 "Indicates the number of PRBS errors on lane 0") \ 264 m(+1, u64 bip_errors_lane1, "edpl_bip_errors_lane1", \ 265 "Indicates the number of PRBS errors on lane 1") \ 266 m(+1, u64 bip_errors_lane2, "edpl_bip_errors_lane2", \ 267 "Indicates the number of PRBS errors on lane 2") \ 268 m(+1, u64 bip_errors_lane3, "edpl_bip_errors_lane3", \ 269 "Indicates the number of PRBS errors on lane 3") \ 270 m(+1, u64 fc_corrected_blocks_lane0, "fc_corrected_blocks_lane0", \ 271 "FEC correctable block counter lane 0") \ 272 m(+1, u64 fc_corrected_blocks_lane1, "fc_corrected_blocks_lane1", \ 273 "FEC correctable block counter lane 1") \ 274 m(+1, u64 fc_corrected_blocks_lane2, "fc_corrected_blocks_lane2", \ 275 "FEC correctable block counter lane 2") \ 276 m(+1, u64 fc_corrected_blocks_lane3, "fc_corrected_blocks_lane3", \ 277 "FEC correctable block counter lane 3") \ 278 m(+1, u64 rs_corrected_blocks, "rs_corrected_blocks", \ 279 "FEC correcable block counter") \ 280 m(+1, u64 rs_uncorrectable_blocks, "rs_uncorrectable_blocks", \ 281 "FEC uncorrecable block counter") \ 282 m(+1, u64 rs_no_errors_blocks, "rs_no_errors_blocks", \ 283 "The number of RS-FEC blocks received that had no errors") \ 284 m(+1, u64 rs_single_error_blocks, "rs_single_error_blocks", \ 285 "The number of corrected RS-FEC blocks received that had" \ 286 "exactly 1 error symbol") \ 287 m(+1, u64 rs_corrected_symbols_total, "rs_corrected_symbols_total", \ 288 "Port FEC corrected symbol counter") \ 289 m(+1, u64 rs_corrected_symbols_lane0, "rs_corrected_symbols_lane0", \ 290 "FEC corrected symbol counter lane 0") \ 291 m(+1, u64 rs_corrected_symbols_lane1, "rs_corrected_symbols_lane1", \ 292 "FEC corrected symbol counter lane 1") \ 293 m(+1, u64 rs_corrected_symbols_lane2, "rs_corrected_symbols_lane2", \ 294 "FEC corrected symbol counter lane 2") \ 295 m(+1, u64 rs_corrected_symbols_lane3, "rs_corrected_symbols_lane3", \ 296 "FEC corrected symbol counter lane 3") 297 298/* Per priority statistics for PFC */ 299#define MLX5E_PPORT_PER_PRIO_STATS_SUB(m,n,p) \ 300 m(n, p, +1, u64, rx_octets, "rx_octets", "Received octets") \ 301 m(n, p, +1, u64, reserved_0, "reserved_0", "Reserved") \ 302 m(n, p, +1, u64, reserved_1, "reserved_1", "Reserved") \ 303 m(n, p, +1, u64, reserved_2, "reserved_2", "Reserved") \ 304 m(n, p, +1, u64, rx_frames, "rx_frames", "Received frames") \ 305 m(n, p, +1, u64, tx_octets, "tx_octets", "Transmitted octets") \ 306 m(n, p, +1, u64, reserved_3, "reserved_3", "Reserved") \ 307 m(n, p, +1, u64, reserved_4, "reserved_4", "Reserved") \ 308 m(n, p, +1, u64, reserved_5, "reserved_5", "Reserved") \ 309 m(n, p, +1, u64, tx_frames, "tx_frames", "Transmitted frames") \ 310 m(n, p, +1, u64, rx_pause, "rx_pause", "Received pause frames") \ 311 m(n, p, +1, u64, rx_pause_duration, "rx_pause_duration", \ 312 "Received pause duration") \ 313 m(n, p, +1, u64, tx_pause, "tx_pause", "Transmitted pause frames") \ 314 m(n, p, +1, u64, tx_pause_duration, "tx_pause_duration", \ 315 "Transmitted pause duration") \ 316 m(n, p, +1, u64, rx_pause_transition, "rx_pause_transition", \ 317 "Received pause transitions") \ 318 m(n, p, +1, u64, rx_discards, "rx_discards", "Discarded received frames") \ 319 m(n, p, +1, u64, device_stall_minor_watermark, \ 320 "device_stall_minor_watermark", "Device stall minor watermark") \ 321 m(n, p, +1, u64, device_stall_critical_watermark, \ 322 "device_stall_critical_watermark", "Device stall critical watermark") 323 324#define MLX5E_PPORT_PER_PRIO_STATS_PREFIX(m,p,c,t,f,s,d) \ 325 m(c, t pri_##p##_##f, "prio" #p "_" s, "Priority " #p " - " d) 326 327#define MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO 8 328 329#define MLX5E_PPORT_PER_PRIO_STATS(m) \ 330 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,0) \ 331 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,1) \ 332 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,2) \ 333 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,3) \ 334 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,4) \ 335 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,5) \ 336 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,6) \ 337 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,7) 338 339/* 340 * Make sure to update mlx5e_update_pport_counters() 341 * when adding a new MLX5E_PPORT_STATS block 342 */ 343#define MLX5E_PPORT_STATS(m) \ 344 MLX5E_PPORT_PER_PRIO_STATS(m) \ 345 MLX5E_PPORT_IEEE802_3_STATS(m) \ 346 MLX5E_PPORT_RFC2819_STATS(m) 347 348#define MLX5E_PORT_STATS_DEBUG(m) \ 349 MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 350 MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 351 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) 352 353#define MLX5E_PPORT_IEEE802_3_STATS_NUM \ 354 (0 MLX5E_PPORT_IEEE802_3_STATS(MLX5E_STATS_COUNT)) 355#define MLX5E_PPORT_RFC2819_STATS_NUM \ 356 (0 MLX5E_PPORT_RFC2819_STATS(MLX5E_STATS_COUNT)) 357#define MLX5E_PPORT_STATS_NUM \ 358 (0 MLX5E_PPORT_STATS(MLX5E_STATS_COUNT)) 359 360#define MLX5E_PPORT_PER_PRIO_STATS_NUM \ 361 (0 MLX5E_PPORT_PER_PRIO_STATS(MLX5E_STATS_COUNT)) 362#define MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM \ 363 (0 MLX5E_PPORT_RFC2819_STATS_DEBUG(MLX5E_STATS_COUNT)) 364#define MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM \ 365 (0 MLX5E_PPORT_RFC2863_STATS_DEBUG(MLX5E_STATS_COUNT)) 366#define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM \ 367 (0 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(MLX5E_STATS_COUNT)) 368#define MLX5E_PORT_STATS_DEBUG_NUM \ 369 (0 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_COUNT)) 370 371struct mlx5e_pport_stats { 372 struct sysctl_ctx_list ctx; 373 u64 arg [0]; 374 MLX5E_PPORT_STATS(MLX5E_STATS_VAR) 375}; 376 377struct mlx5e_port_stats_debug { 378 struct sysctl_ctx_list ctx; 379 u64 arg [0]; 380 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_VAR) 381}; 382 383#define MLX5E_RQ_STATS(m) \ 384 m(+1, u64 packets, "packets", "Received packets") \ 385 m(+1, u64 bytes, "bytes", "Received bytes") \ 386 m(+1, u64 csum_none, "csum_none", "Received packets") \ 387 m(+1, u64 lro_packets, "lro_packets", "Received LRO packets") \ 388 m(+1, u64 lro_bytes, "lro_bytes", "Received LRO bytes") \ 389 m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 390 m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 391 m(+1, u64 wqe_err, "wqe_err", "Received packets") 392 393#define MLX5E_RQ_STATS_NUM (0 MLX5E_RQ_STATS(MLX5E_STATS_COUNT)) 394 395struct mlx5e_rq_stats { 396 struct sysctl_ctx_list ctx; 397 u64 arg [0]; 398 MLX5E_RQ_STATS(MLX5E_STATS_VAR) 399}; 400 401#define MLX5E_SQ_STATS(m) \ 402 m(+1, u64 packets, "packets", "Transmitted packets") \ 403 m(+1, u64 bytes, "bytes", "Transmitted bytes") \ 404 m(+1, u64 tso_packets, "tso_packets", "Transmitted packets") \ 405 m(+1, u64 tso_bytes, "tso_bytes", "Transmitted bytes") \ 406 m(+1, u64 csum_offload_none, "csum_offload_none", "Transmitted packets") \ 407 m(+1, u64 defragged, "defragged", "Transmitted packets") \ 408 m(+1, u64 dropped, "dropped", "Transmitted packets") \ 409 m(+1, u64 nop, "nop", "Transmitted packets") 410 411#define MLX5E_SQ_STATS_NUM (0 MLX5E_SQ_STATS(MLX5E_STATS_COUNT)) 412 413struct mlx5e_sq_stats { 414 struct sysctl_ctx_list ctx; 415 u64 arg [0]; 416 MLX5E_SQ_STATS(MLX5E_STATS_VAR) 417}; 418 419struct mlx5e_stats { 420 struct mlx5e_vport_stats vport; 421 struct mlx5e_pport_stats pport; 422 struct mlx5e_port_stats_debug port_stats_debug; 423}; 424 425struct mlx5e_rq_param { 426 u32 rqc [MLX5_ST_SZ_DW(rqc)]; 427 struct mlx5_wq_param wq; 428}; 429 430struct mlx5e_sq_param { 431 u32 sqc [MLX5_ST_SZ_DW(sqc)]; 432 struct mlx5_wq_param wq; 433}; 434 435struct mlx5e_cq_param { 436 u32 cqc [MLX5_ST_SZ_DW(cqc)]; 437 struct mlx5_wq_param wq; 438}; 439 440struct mlx5e_params { 441 u8 log_sq_size; 442 u8 log_rq_size; 443 u16 num_channels; 444 u8 default_vlan_prio; 445 u8 num_tc; 446 u8 rx_cq_moderation_mode; 447 u8 tx_cq_moderation_mode; 448 u16 rx_cq_moderation_usec; 449 u16 rx_cq_moderation_pkts; 450 u16 tx_cq_moderation_usec; 451 u16 tx_cq_moderation_pkts; 452 u16 min_rx_wqes; 453 bool hw_lro_en; 454 bool cqe_zipping_en; 455 u32 lro_wqe_sz; 456 u16 rx_hash_log_tbl_sz; 457 u32 tx_pauseframe_control __aligned(4); 458 u32 rx_pauseframe_control __aligned(4); 459 u32 tx_priority_flow_control __aligned(4); 460 u32 rx_priority_flow_control __aligned(4); 461 u16 tx_max_inline; 462 u8 tx_min_inline_mode; 463 u8 channels_rsss; 464}; 465 466#define MLX5E_PARAMS(m) \ 467 m(+1, u64 tx_queue_size_max, "tx_queue_size_max", "Max send queue size") \ 468 m(+1, u64 rx_queue_size_max, "rx_queue_size_max", "Max receive queue size") \ 469 m(+1, u64 tx_queue_size, "tx_queue_size", "Default send queue size") \ 470 m(+1, u64 rx_queue_size, "rx_queue_size", "Default receive queue size") \ 471 m(+1, u64 channels, "channels", "Default number of channels") \ 472 m(+1, u64 channels_rsss, "channels_rsss", "Default channels receive side scaling stride") \ 473 m(+1, u64 coalesce_usecs_max, "coalesce_usecs_max", "Maximum usecs for joining packets") \ 474 m(+1, u64 coalesce_pkts_max, "coalesce_pkts_max", "Maximum packets to join") \ 475 m(+1, u64 rx_coalesce_usecs, "rx_coalesce_usecs", "Limit in usec for joining rx packets") \ 476 m(+1, u64 rx_coalesce_pkts, "rx_coalesce_pkts", "Maximum number of rx packets to join") \ 477 m(+1, u64 rx_coalesce_mode, "rx_coalesce_mode", "0: EQE fixed mode 1: CQE fixed mode 2: EQE auto mode 3: CQE auto mode") \ 478 m(+1, u64 tx_coalesce_usecs, "tx_coalesce_usecs", "Limit in usec for joining tx packets") \ 479 m(+1, u64 tx_coalesce_pkts, "tx_coalesce_pkts", "Maximum number of tx packets to join") \ 480 m(+1, u64 tx_coalesce_mode, "tx_coalesce_mode", "0: EQE mode 1: CQE mode") \ 481 m(+1, u64 tx_completion_fact, "tx_completion_fact", "1..MAX: Completion event ratio") \ 482 m(+1, u64 tx_completion_fact_max, "tx_completion_fact_max", "Maximum completion event ratio") \ 483 m(+1, u64 hw_lro, "hw_lro", "set to enable hw_lro") \ 484 m(+1, u64 cqe_zipping, "cqe_zipping", "0 : CQE zipping disabled") \ 485 m(+1, u64 modify_tx_dma, "modify_tx_dma", "0: Enable TX 1: Disable TX") \ 486 m(+1, u64 modify_rx_dma, "modify_rx_dma", "0: Enable RX 1: Disable RX") \ 487 m(+1, u64 diag_pci_enable, "diag_pci_enable", "0: Disabled 1: Enabled") \ 488 m(+1, u64 diag_general_enable, "diag_general_enable", "0: Disabled 1: Enabled") \ 489 m(+1, u64 hw_mtu, "hw_mtu", "Current hardware MTU value") \ 490 m(+1, u64 mc_local_lb, "mc_local_lb", "0: Local multicast loopback enabled 1: Disabled") \ 491 m(+1, u64 uc_local_lb, "uc_local_lb", "0: Local unicast loopback enabled 1: Disabled") 492 493 494#define MLX5E_PARAMS_NUM (0 MLX5E_PARAMS(MLX5E_STATS_COUNT)) 495 496struct mlx5e_params_ethtool { 497 u64 arg [0]; 498 MLX5E_PARAMS(MLX5E_STATS_VAR) 499 u64 max_bw_value[IEEE_8021QAZ_MAX_TCS]; 500 u8 max_bw_share[IEEE_8021QAZ_MAX_TCS]; 501 u8 prio_tc[IEEE_8021QAZ_MAX_TCS]; 502 u8 dscp2prio[MLX5_MAX_SUPPORTED_DSCP]; 503 u8 trust_state; 504}; 505 506/* EEPROM Standards for plug in modules */ 507#ifndef MLX5E_ETH_MODULE_SFF_8472 508#define MLX5E_ETH_MODULE_SFF_8472 0x1 509#define MLX5E_ETH_MODULE_SFF_8472_LEN 128 510#endif 511 512#ifndef MLX5E_ETH_MODULE_SFF_8636 513#define MLX5E_ETH_MODULE_SFF_8636 0x2 514#define MLX5E_ETH_MODULE_SFF_8636_LEN 256 515#endif 516 517#ifndef MLX5E_ETH_MODULE_SFF_8436 518#define MLX5E_ETH_MODULE_SFF_8436 0x3 519#define MLX5E_ETH_MODULE_SFF_8436_LEN 256 520#endif 521 522/* EEPROM I2C Addresses */ 523#define MLX5E_I2C_ADDR_LOW 0x50 524#define MLX5E_I2C_ADDR_HIGH 0x51 525 526#define MLX5E_EEPROM_LOW_PAGE 0x0 527#define MLX5E_EEPROM_HIGH_PAGE 0x3 528 529#define MLX5E_EEPROM_HIGH_PAGE_OFFSET 128 530#define MLX5E_EEPROM_PAGE_LENGTH 256 531 532#define MLX5E_EEPROM_INFO_BYTES 0x3 533 534struct mlx5e_cq { 535 /* data path - accessed per cqe */ 536 struct mlx5_cqwq wq; 537 538 /* data path - accessed per HW polling */ 539 struct mlx5_core_cq mcq; 540 541 /* control */ 542 struct mlx5e_priv *priv; 543 struct mlx5_wq_ctrl wq_ctrl; 544} __aligned(MLX5E_CACHELINE_SIZE); 545 546struct mlx5e_rq_mbuf { 547 bus_dmamap_t dma_map; 548 caddr_t data; 549 struct mbuf *mbuf; 550}; 551 552struct mlx5e_rq { 553 /* data path */ 554 struct mlx5_wq_ll wq; 555 struct mtx mtx; 556 bus_dma_tag_t dma_tag; 557 u32 wqe_sz; 558 u32 nsegs; 559 struct mlx5e_rq_mbuf *mbuf; 560 struct ifnet *ifp; 561 struct mlx5e_rq_stats stats; 562 struct mlx5e_cq cq; 563 struct lro_ctrl lro; 564 volatile int enabled; 565 int ix; 566 567 /* Dynamic Interrupt Moderation */ 568 struct net_dim dim; 569 570 /* control */ 571 struct mlx5_wq_ctrl wq_ctrl; 572 u32 rqn; 573 struct mlx5e_channel *channel; 574 struct callout watchdog; 575} __aligned(MLX5E_CACHELINE_SIZE); 576 577struct mlx5e_sq_mbuf { 578 bus_dmamap_t dma_map; 579 struct mbuf *mbuf; 580 u32 num_bytes; 581 u32 num_wqebbs; 582}; 583 584enum { 585 MLX5E_SQ_READY, 586 MLX5E_SQ_FULL 587}; 588 589struct mlx5e_sq { 590 /* data path */ 591 struct mtx lock; 592 bus_dma_tag_t dma_tag; 593 struct mtx comp_lock; 594 595 /* dirtied @completion */ 596 u16 cc; 597 598 /* dirtied @xmit */ 599 u16 pc __aligned(MLX5E_CACHELINE_SIZE); 600 u16 bf_offset; 601 u16 cev_counter; /* completion event counter */ 602 u16 cev_factor; /* completion event factor */ 603 u16 cev_next_state; /* next completion event state */ 604#define MLX5E_CEV_STATE_INITIAL 0 /* timer not started */ 605#define MLX5E_CEV_STATE_SEND_NOPS 1 /* send NOPs */ 606#define MLX5E_CEV_STATE_HOLD_NOPS 2 /* don't send NOPs yet */ 607 u16 running; /* set if SQ is running */ 608 struct callout cev_callout; 609 union { 610 u32 d32[2]; 611 u64 d64; 612 } doorbell; 613 struct mlx5e_sq_stats stats; 614 615 struct mlx5e_cq cq; 616 617 /* pointers to per packet info: write@xmit, read@completion */ 618 struct mlx5e_sq_mbuf *mbuf; 619 struct buf_ring *br; 620 621 /* read only */ 622 struct mlx5_wq_cyc wq; 623 struct mlx5_uar uar; 624 struct ifnet *ifp; 625 u32 sqn; 626 u32 bf_buf_size; 627 u32 mkey_be; 628 u16 max_inline; 629 u8 min_inline_mode; 630 u8 min_insert_caps; 631#define MLX5E_INSERT_VLAN 1 632#define MLX5E_INSERT_NON_VLAN 2 633 634 /* control path */ 635 struct mlx5_wq_ctrl wq_ctrl; 636 struct mlx5e_priv *priv; 637 int tc; 638} __aligned(MLX5E_CACHELINE_SIZE); 639 640static inline bool 641mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) 642{ 643 u16 cc = sq->cc; 644 u16 pc = sq->pc; 645 646 return ((sq->wq.sz_m1 & (cc - pc)) >= n || cc == pc); 647} 648 649struct mlx5e_channel { 650 /* data path */ 651 struct mlx5e_rq rq; 652 struct mlx5e_sq sq[MLX5E_MAX_TX_NUM_TC]; 653 struct ifnet *ifp; 654 u32 mkey_be; 655 u8 num_tc; 656 657 /* control */ 658 struct mlx5e_priv *priv; 659 int ix; 660 int cpu; 661} __aligned(MLX5E_CACHELINE_SIZE); 662 663enum mlx5e_traffic_types { 664 MLX5E_TT_IPV4_TCP, 665 MLX5E_TT_IPV6_TCP, 666 MLX5E_TT_IPV4_UDP, 667 MLX5E_TT_IPV6_UDP, 668 MLX5E_TT_IPV4_IPSEC_AH, 669 MLX5E_TT_IPV6_IPSEC_AH, 670 MLX5E_TT_IPV4_IPSEC_ESP, 671 MLX5E_TT_IPV6_IPSEC_ESP, 672 MLX5E_TT_IPV4, 673 MLX5E_TT_IPV6, 674 MLX5E_TT_ANY, 675 MLX5E_NUM_TT, 676}; 677 678enum { 679 MLX5E_RQT_SPREADING = 0, 680 MLX5E_RQT_DEFAULT_RQ = 1, 681 MLX5E_NUM_RQT = 2, 682}; 683 684struct mlx5_flow_rule; 685 686struct mlx5e_eth_addr_info { 687 u8 addr [ETH_ALEN + 2]; 688 u32 tt_vec; 689 /* flow table rule per traffic type */ 690 struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT]; 691}; 692 693#define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE) 694 695struct mlx5e_eth_addr_hash_node; 696 697struct mlx5e_eth_addr_hash_head { 698 struct mlx5e_eth_addr_hash_node *lh_first; 699}; 700 701struct mlx5e_eth_addr_db { 702 struct mlx5e_eth_addr_hash_head if_uc[MLX5E_ETH_ADDR_HASH_SIZE]; 703 struct mlx5e_eth_addr_hash_head if_mc[MLX5E_ETH_ADDR_HASH_SIZE]; 704 struct mlx5e_eth_addr_info broadcast; 705 struct mlx5e_eth_addr_info allmulti; 706 struct mlx5e_eth_addr_info promisc; 707 bool broadcast_enabled; 708 bool allmulti_enabled; 709 bool promisc_enabled; 710}; 711 712enum { 713 MLX5E_STATE_ASYNC_EVENTS_ENABLE, 714 MLX5E_STATE_OPENED, 715}; 716 717enum { 718 MLX5_BW_NO_LIMIT = 0, 719 MLX5_100_MBPS_UNIT = 3, 720 MLX5_GBPS_UNIT = 4, 721}; 722 723struct mlx5e_vlan_db { 724 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 725 struct mlx5_flow_rule *active_vlans_ft_rule[VLAN_N_VID]; 726 struct mlx5_flow_rule *untagged_ft_rule; 727 struct mlx5_flow_rule *any_cvlan_ft_rule; 728 struct mlx5_flow_rule *any_svlan_ft_rule; 729 bool filter_disabled; 730}; 731 732struct mlx5e_flow_table { 733 int num_groups; 734 struct mlx5_flow_table *t; 735 struct mlx5_flow_group **g; 736}; 737 738struct mlx5e_flow_tables { 739 struct mlx5_flow_namespace *ns; 740 struct mlx5e_flow_table vlan; 741 struct mlx5e_flow_table main; 742 struct mlx5e_flow_table inner_rss; 743}; 744 745struct mlx5e_priv { 746 struct mlx5_core_dev *mdev; /* must be first */ 747 748 /* priv data path fields - start */ 749 int order_base_2_num_channels; 750 int queue_mapping_channel_mask; 751 int num_tc; 752 int default_vlan_prio; 753 /* priv data path fields - end */ 754 755 unsigned long state; 756 int gone; 757#define PRIV_LOCK(priv) sx_xlock(&(priv)->state_lock) 758#define PRIV_UNLOCK(priv) sx_xunlock(&(priv)->state_lock) 759#define PRIV_LOCKED(priv) sx_xlocked(&(priv)->state_lock) 760 struct sx state_lock; /* Protects Interface state */ 761 struct mlx5_uar cq_uar; 762 u32 pdn; 763 u32 tdn; 764 struct mlx5_core_mr mr; 765 766 u32 tisn[MLX5E_MAX_TX_NUM_TC]; 767 u32 rqtn; 768 u32 tirn[MLX5E_NUM_TT]; 769 770 struct mlx5e_flow_tables fts; 771 struct mlx5e_eth_addr_db eth_addr; 772 struct mlx5e_vlan_db vlan; 773 774 struct mlx5e_params params; 775 struct mlx5e_params_ethtool params_ethtool; 776 union mlx5_core_pci_diagnostics params_pci; 777 union mlx5_core_general_diagnostics params_general; 778 struct mtx async_events_mtx; /* sync hw events */ 779 struct work_struct update_stats_work; 780 struct work_struct update_carrier_work; 781 struct work_struct set_rx_mode_work; 782 MLX5_DECLARE_DOORBELL_LOCK(doorbell_lock) 783 784 struct ifnet *ifp; 785 struct sysctl_ctx_list sysctl_ctx; 786 struct sysctl_oid *sysctl_ifnet; 787 struct sysctl_oid *sysctl_hw; 788 int sysctl_debug; 789 struct mlx5e_stats stats; 790 int counter_set_id; 791 792 struct workqueue_struct *wq; 793 794 eventhandler_tag vlan_detach; 795 eventhandler_tag vlan_attach; 796 struct ifmedia media; 797 int media_status_last; 798 int media_active_last; 799 800 struct callout watchdog; 801 802 struct mlx5e_channel channel[]; 803}; 804 805#define MLX5E_NET_IP_ALIGN 2 806 807struct mlx5e_tx_wqe { 808 struct mlx5_wqe_ctrl_seg ctrl; 809 struct mlx5_wqe_eth_seg eth; 810}; 811 812struct mlx5e_rx_wqe { 813 struct mlx5_wqe_srq_next_seg next; 814 struct mlx5_wqe_data_seg data[]; 815}; 816 817/* the size of the structure above must be power of two */ 818CTASSERT(powerof2(sizeof(struct mlx5e_rx_wqe))); 819 820struct mlx5e_eeprom { 821 int lock_bit; 822 int i2c_addr; 823 int page_num; 824 int device_addr; 825 int module_num; 826 int len; 827 int type; 828 int page_valid; 829 u32 *data; 830}; 831 832#define MLX5E_FLD_MAX(typ, fld) ((1ULL << __mlx5_bit_sz(typ, fld)) - 1ULL) 833 834int mlx5e_xmit(struct ifnet *, struct mbuf *); 835 836int mlx5e_open_locked(struct ifnet *); 837int mlx5e_close_locked(struct ifnet *); 838 839void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, int event); 840void mlx5e_rx_cq_comp(struct mlx5_core_cq *); 841void mlx5e_tx_cq_comp(struct mlx5_core_cq *); 842struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); 843 844void mlx5e_dim_work(struct work_struct *); 845void mlx5e_dim_build_cq_param(struct mlx5e_priv *, struct mlx5e_cq_param *); 846 847int mlx5e_open_flow_table(struct mlx5e_priv *priv); 848void mlx5e_close_flow_table(struct mlx5e_priv *priv); 849void mlx5e_set_rx_mode_core(struct mlx5e_priv *priv); 850void mlx5e_set_rx_mode_work(struct work_struct *work); 851 852void mlx5e_vlan_rx_add_vid(void *, struct ifnet *, u16); 853void mlx5e_vlan_rx_kill_vid(void *, struct ifnet *, u16); 854void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); 855void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); 856int mlx5e_add_all_vlan_rules(struct mlx5e_priv *priv); 857void mlx5e_del_all_vlan_rules(struct mlx5e_priv *priv); 858 859static inline void 860mlx5e_tx_notify_hw(struct mlx5e_sq *sq, u32 *wqe, int bf_sz) 861{ 862 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; 863 864 /* ensure wqe is visible to device before updating doorbell record */ 865 wmb(); 866 867 *sq->wq.db = cpu_to_be32(sq->pc); 868 869 /* 870 * Ensure the doorbell record is visible to device before ringing 871 * the doorbell: 872 */ 873 wmb(); 874 875 if (bf_sz) { 876 __iowrite64_copy(sq->uar.bf_map + ofst, wqe, bf_sz); 877 878 /* flush the write-combining mapped buffer */ 879 wmb(); 880 881 } else { 882 mlx5_write64(wqe, sq->uar.map + ofst, 883 MLX5_GET_DOORBELL_LOCK(&sq->priv->doorbell_lock)); 884 } 885 886 sq->bf_offset ^= sq->bf_buf_size; 887} 888 889static inline void 890mlx5e_cq_arm(struct mlx5e_cq *cq, spinlock_t *dblock) 891{ 892 struct mlx5_core_cq *mcq; 893 894 mcq = &cq->mcq; 895 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, dblock, cq->wq.cc); 896} 897 898extern const struct ethtool_ops mlx5e_ethtool_ops; 899void mlx5e_create_ethtool(struct mlx5e_priv *); 900void mlx5e_create_stats(struct sysctl_ctx_list *, 901 struct sysctl_oid_list *, const char *, 902 const char **, unsigned, u64 *); 903void mlx5e_send_nop(struct mlx5e_sq *, u32); 904void mlx5e_sq_cev_timeout(void *); 905int mlx5e_refresh_channel_params(struct mlx5e_priv *); 906int mlx5e_open_cq(struct mlx5e_priv *, struct mlx5e_cq_param *, 907 struct mlx5e_cq *, mlx5e_cq_comp_t *, int eq_ix); 908void mlx5e_close_cq(struct mlx5e_cq *); 909void mlx5e_free_sq_db(struct mlx5e_sq *); 910int mlx5e_alloc_sq_db(struct mlx5e_sq *); 911int mlx5e_enable_sq(struct mlx5e_sq *, struct mlx5e_sq_param *, int tis_num); 912int mlx5e_modify_sq(struct mlx5e_sq *, int curr_state, int next_state); 913void mlx5e_disable_sq(struct mlx5e_sq *); 914void mlx5e_drain_sq(struct mlx5e_sq *); 915void mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value); 916void mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value); 917void mlx5e_resume_sq(struct mlx5e_sq *sq); 918void mlx5e_update_sq_inline(struct mlx5e_sq *sq); 919void mlx5e_refresh_sq_inline(struct mlx5e_priv *priv); 920 921#endif /* _MLX5_EN_H_ */ 922