en.h revision 341968
1/*- 2 * Copyright (c) 2015 Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_en/en.h 341968 2018-12-12 12:55:53Z hselasky $ 26 */ 27 28#ifndef _MLX5_EN_H_ 29#define _MLX5_EN_H_ 30 31#include <linux/kmod.h> 32#include <linux/page.h> 33#include <linux/slab.h> 34#include <linux/if_vlan.h> 35#include <linux/if_ether.h> 36#include <linux/vmalloc.h> 37#include <linux/moduleparam.h> 38#include <linux/delay.h> 39#include <linux/netdevice.h> 40#include <linux/etherdevice.h> 41 42#include <netinet/in_systm.h> 43#include <netinet/in.h> 44#include <netinet/if_ether.h> 45#include <netinet/ip.h> 46#include <netinet/ip6.h> 47#include <netinet/tcp.h> 48#include <netinet/tcp_lro.h> 49#include <netinet/udp.h> 50#include <net/ethernet.h> 51#include <sys/buf_ring.h> 52 53#include "opt_rss.h" 54 55#ifdef RSS 56#include <net/rss_config.h> 57#include <netinet/in_rss.h> 58#endif 59 60#include <machine/bus.h> 61 62#include <dev/mlx5/driver.h> 63#include <dev/mlx5/qp.h> 64#include <dev/mlx5/cq.h> 65#include <dev/mlx5/port.h> 66#include <dev/mlx5/vport.h> 67#include <dev/mlx5/diagnostics.h> 68 69#include <dev/mlx5/mlx5_core/wq.h> 70#include <dev/mlx5/mlx5_core/transobj.h> 71#include <dev/mlx5/mlx5_core/mlx5_core.h> 72 73#define IEEE_8021QAZ_MAX_TCS 8 74 75#define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x7 76#define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa 77#define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xe 78 79#define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x7 80#define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa 81#define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xe 82 83#define MLX5E_MAX_RX_SEGS 7 84 85#ifndef MLX5E_MAX_RX_BYTES 86#define MLX5E_MAX_RX_BYTES MCLBYTES 87#endif 88 89#if (MLX5E_MAX_RX_SEGS == 1) 90/* FreeBSD HW LRO is limited by 16KB - the size of max mbuf */ 91#define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ MJUM16BYTES 92#else 93#define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ \ 94 MIN(65535, MLX5E_MAX_RX_SEGS * MLX5E_MAX_RX_BYTES) 95#endif 96#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 97#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 98#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 99#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 100#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 101#define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 102#define MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ 0x7 103#define MLX5E_CACHELINE_SIZE CACHE_LINE_SIZE 104#define MLX5E_HW2SW_MTU(hwmtu) \ 105 ((hwmtu) - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 106#define MLX5E_SW2HW_MTU(swmtu) \ 107 ((swmtu) + (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 108#define MLX5E_SW2MB_MTU(swmtu) \ 109 (MLX5E_SW2HW_MTU(swmtu) + MLX5E_NET_IP_ALIGN) 110#define MLX5E_MTU_MIN 72 /* Min MTU allowed by the kernel */ 111#define MLX5E_MTU_MAX MIN(ETHERMTU_JUMBO, MJUM16BYTES) /* Max MTU of Ethernet 112 * jumbo frames */ 113 114#define MLX5E_BUDGET_MAX 8192 /* RX and TX */ 115#define MLX5E_RX_BUDGET_MAX 256 116#define MLX5E_SQ_BF_BUDGET 16 117#define MLX5E_SQ_TX_QUEUE_SIZE 4096 /* SQ drbr queue size */ 118 119#define MLX5E_MAX_TX_NUM_TC 8 /* units */ 120#define MLX5E_MAX_TX_HEADER 128 /* bytes */ 121#define MLX5E_MAX_TX_PAYLOAD_SIZE 65536 /* bytes */ 122#define MLX5E_MAX_TX_MBUF_SIZE 65536 /* bytes */ 123#define MLX5E_MAX_TX_MBUF_FRAGS \ 124 ((MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS) - \ 125 (MLX5E_MAX_TX_HEADER / MLX5_SEND_WQE_DS) - \ 126 1 /* the maximum value of the DS counter is 0x3F and not 0x40 */) /* units */ 127#define MLX5E_MAX_TX_INLINE \ 128 (MLX5E_MAX_TX_HEADER - sizeof(struct mlx5e_tx_wqe) + \ 129 sizeof(((struct mlx5e_tx_wqe *)0)->eth.inline_hdr_start)) /* bytes */ 130 131#define MLX5E_100MB (100000) 132#define MLX5E_1GB (1000000) 133 134MALLOC_DECLARE(M_MLX5EN); 135 136struct mlx5_core_dev; 137struct mlx5e_cq; 138 139typedef void (mlx5e_cq_comp_t)(struct mlx5_core_cq *); 140 141#define MLX5E_STATS_COUNT(a,b,c,d) a 142#define MLX5E_STATS_VAR(a,b,c,d) b; 143#define MLX5E_STATS_DESC(a,b,c,d) c, d, 144 145#define MLX5E_VPORT_STATS(m) \ 146 /* HW counters */ \ 147 m(+1, u64 rx_packets, "rx_packets", "Received packets") \ 148 m(+1, u64 rx_bytes, "rx_bytes", "Received bytes") \ 149 m(+1, u64 tx_packets, "tx_packets", "Transmitted packets") \ 150 m(+1, u64 tx_bytes, "tx_bytes", "Transmitted bytes") \ 151 m(+1, u64 rx_error_packets, "rx_error_packets", "Received error packets") \ 152 m(+1, u64 rx_error_bytes, "rx_error_bytes", "Received error bytes") \ 153 m(+1, u64 tx_error_packets, "tx_error_packets", "Transmitted error packets") \ 154 m(+1, u64 tx_error_bytes, "tx_error_bytes", "Transmitted error bytes") \ 155 m(+1, u64 rx_unicast_packets, "rx_unicast_packets", "Received unicast packets") \ 156 m(+1, u64 rx_unicast_bytes, "rx_unicast_bytes", "Received unicast bytes") \ 157 m(+1, u64 tx_unicast_packets, "tx_unicast_packets", "Transmitted unicast packets") \ 158 m(+1, u64 tx_unicast_bytes, "tx_unicast_bytes", "Transmitted unicast bytes") \ 159 m(+1, u64 rx_multicast_packets, "rx_multicast_packets", "Received multicast packets") \ 160 m(+1, u64 rx_multicast_bytes, "rx_multicast_bytes", "Received multicast bytes") \ 161 m(+1, u64 tx_multicast_packets, "tx_multicast_packets", "Transmitted multicast packets") \ 162 m(+1, u64 tx_multicast_bytes, "tx_multicast_bytes", "Transmitted multicast bytes") \ 163 m(+1, u64 rx_broadcast_packets, "rx_broadcast_packets", "Received broadcast packets") \ 164 m(+1, u64 rx_broadcast_bytes, "rx_broadcast_bytes", "Received broadcast bytes") \ 165 m(+1, u64 tx_broadcast_packets, "tx_broadcast_packets", "Transmitted broadcast packets") \ 166 m(+1, u64 tx_broadcast_bytes, "tx_broadcast_bytes", "Transmitted broadcast bytes") \ 167 m(+1, u64 rx_out_of_buffer, "rx_out_of_buffer", "Receive out of buffer, no recv wqes events") \ 168 /* SW counters */ \ 169 m(+1, u64 tso_packets, "tso_packets", "Transmitted TSO packets") \ 170 m(+1, u64 tso_bytes, "tso_bytes", "Transmitted TSO bytes") \ 171 m(+1, u64 lro_packets, "lro_packets", "Received LRO packets") \ 172 m(+1, u64 lro_bytes, "lro_bytes", "Received LRO bytes") \ 173 m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 174 m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 175 m(+1, u64 rx_csum_good, "rx_csum_good", "Received checksum valid packets") \ 176 m(+1, u64 rx_csum_none, "rx_csum_none", "Received no checksum packets") \ 177 m(+1, u64 tx_csum_offload, "tx_csum_offload", "Transmit checksum offload packets") \ 178 m(+1, u64 tx_queue_dropped, "tx_queue_dropped", "Transmit queue dropped") \ 179 m(+1, u64 tx_defragged, "tx_defragged", "Transmit queue defragged") \ 180 m(+1, u64 rx_wqe_err, "rx_wqe_err", "Receive WQE errors") \ 181 m(+1, u64 tx_jumbo_packets, "tx_jumbo_packets", "TX packets greater than 1518 octets") 182 183#define MLX5E_VPORT_STATS_NUM (0 MLX5E_VPORT_STATS(MLX5E_STATS_COUNT)) 184 185struct mlx5e_vport_stats { 186 struct sysctl_ctx_list ctx; 187 u64 arg [0]; 188 MLX5E_VPORT_STATS(MLX5E_STATS_VAR) 189 u32 rx_out_of_buffer_prev; 190}; 191 192#define MLX5E_PPORT_IEEE802_3_STATS(m) \ 193 m(+1, u64 frames_tx, "frames_tx", "Frames transmitted") \ 194 m(+1, u64 frames_rx, "frames_rx", "Frames received") \ 195 m(+1, u64 check_seq_err, "check_seq_err", "Sequence errors") \ 196 m(+1, u64 alignment_err, "alignment_err", "Alignment errors") \ 197 m(+1, u64 octets_tx, "octets_tx", "Bytes transmitted") \ 198 m(+1, u64 octets_received, "octets_received", "Bytes received") \ 199 m(+1, u64 multicast_xmitted, "multicast_xmitted", "Multicast transmitted") \ 200 m(+1, u64 broadcast_xmitted, "broadcast_xmitted", "Broadcast transmitted") \ 201 m(+1, u64 multicast_rx, "multicast_rx", "Multicast received") \ 202 m(+1, u64 broadcast_rx, "broadcast_rx", "Broadcast received") \ 203 m(+1, u64 in_range_len_errors, "in_range_len_errors", "In range length errors") \ 204 m(+1, u64 out_of_range_len, "out_of_range_len", "Out of range length errors") \ 205 m(+1, u64 too_long_errors, "too_long_errors", "Too long errors") \ 206 m(+1, u64 symbol_err, "symbol_err", "Symbol errors") \ 207 m(+1, u64 mac_control_tx, "mac_control_tx", "MAC control transmitted") \ 208 m(+1, u64 mac_control_rx, "mac_control_rx", "MAC control received") \ 209 m(+1, u64 unsupported_op_rx, "unsupported_op_rx", "Unsupported operation received") \ 210 m(+1, u64 pause_ctrl_rx, "pause_ctrl_rx", "Pause control received") \ 211 m(+1, u64 pause_ctrl_tx, "pause_ctrl_tx", "Pause control transmitted") 212 213#define MLX5E_PPORT_RFC2819_STATS(m) \ 214 m(+1, u64 drop_events, "drop_events", "Dropped events") \ 215 m(+1, u64 octets, "octets", "Octets") \ 216 m(+1, u64 pkts, "pkts", "Packets") \ 217 m(+1, u64 broadcast_pkts, "broadcast_pkts", "Broadcast packets") \ 218 m(+1, u64 multicast_pkts, "multicast_pkts", "Multicast packets") \ 219 m(+1, u64 crc_align_errors, "crc_align_errors", "CRC alignment errors") \ 220 m(+1, u64 undersize_pkts, "undersize_pkts", "Undersized packets") \ 221 m(+1, u64 oversize_pkts, "oversize_pkts", "Oversized packets") \ 222 m(+1, u64 fragments, "fragments", "Fragments") \ 223 m(+1, u64 jabbers, "jabbers", "Jabbers") \ 224 m(+1, u64 collisions, "collisions", "Collisions") 225 226#define MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 227 m(+1, u64 p64octets, "p64octets", "Bytes") \ 228 m(+1, u64 p65to127octets, "p65to127octets", "Bytes") \ 229 m(+1, u64 p128to255octets, "p128to255octets", "Bytes") \ 230 m(+1, u64 p256to511octets, "p256to511octets", "Bytes") \ 231 m(+1, u64 p512to1023octets, "p512to1023octets", "Bytes") \ 232 m(+1, u64 p1024to1518octets, "p1024to1518octets", "Bytes") \ 233 m(+1, u64 p1519to2047octets, "p1519to2047octets", "Bytes") \ 234 m(+1, u64 p2048to4095octets, "p2048to4095octets", "Bytes") \ 235 m(+1, u64 p4096to8191octets, "p4096to8191octets", "Bytes") \ 236 m(+1, u64 p8192to10239octets, "p8192to10239octets", "Bytes") 237 238#define MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 239 m(+1, u64 in_octets, "in_octets", "In octets") \ 240 m(+1, u64 in_ucast_pkts, "in_ucast_pkts", "In unicast packets") \ 241 m(+1, u64 in_discards, "in_discards", "In discards") \ 242 m(+1, u64 in_errors, "in_errors", "In errors") \ 243 m(+1, u64 in_unknown_protos, "in_unknown_protos", "In unknown protocols") \ 244 m(+1, u64 out_octets, "out_octets", "Out octets") \ 245 m(+1, u64 out_ucast_pkts, "out_ucast_pkts", "Out unicast packets") \ 246 m(+1, u64 out_discards, "out_discards", "Out discards") \ 247 m(+1, u64 out_errors, "out_errors", "Out errors") \ 248 m(+1, u64 in_multicast_pkts, "in_multicast_pkts", "In multicast packets") \ 249 m(+1, u64 in_broadcast_pkts, "in_broadcast_pkts", "In broadcast packets") \ 250 m(+1, u64 out_multicast_pkts, "out_multicast_pkts", "Out multicast packets") \ 251 m(+1, u64 out_broadcast_pkts, "out_broadcast_pkts", "Out broadcast packets") 252 253#define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \ 254 m(+1, u64 time_since_last_clear, "time_since_last_clear", \ 255 "Time since the last counters clear event (msec)") \ 256 m(+1, u64 symbol_errors, "symbol_errors", "Symbol errors") \ 257 m(+1, u64 sync_headers_errors, "sync_headers_errors", "Sync header error counter") \ 258 m(+1, u64 bip_errors_lane0, "edpl_bip_errors_lane0", \ 259 "Indicates the number of PRBS errors on lane 0") \ 260 m(+1, u64 bip_errors_lane1, "edpl_bip_errors_lane1", \ 261 "Indicates the number of PRBS errors on lane 1") \ 262 m(+1, u64 bip_errors_lane2, "edpl_bip_errors_lane2", \ 263 "Indicates the number of PRBS errors on lane 2") \ 264 m(+1, u64 bip_errors_lane3, "edpl_bip_errors_lane3", \ 265 "Indicates the number of PRBS errors on lane 3") \ 266 m(+1, u64 fc_corrected_blocks_lane0, "fc_corrected_blocks_lane0", \ 267 "FEC correctable block counter lane 0") \ 268 m(+1, u64 fc_corrected_blocks_lane1, "fc_corrected_blocks_lane1", \ 269 "FEC correctable block counter lane 1") \ 270 m(+1, u64 fc_corrected_blocks_lane2, "fc_corrected_blocks_lane2", \ 271 "FEC correctable block counter lane 2") \ 272 m(+1, u64 fc_corrected_blocks_lane3, "fc_corrected_blocks_lane3", \ 273 "FEC correctable block counter lane 3") \ 274 m(+1, u64 rs_corrected_blocks, "rs_corrected_blocks", \ 275 "FEC correcable block counter") \ 276 m(+1, u64 rs_uncorrectable_blocks, "rs_uncorrectable_blocks", \ 277 "FEC uncorrecable block counter") \ 278 m(+1, u64 rs_no_errors_blocks, "rs_no_errors_blocks", \ 279 "The number of RS-FEC blocks received that had no errors") \ 280 m(+1, u64 rs_single_error_blocks, "rs_single_error_blocks", \ 281 "The number of corrected RS-FEC blocks received that had" \ 282 "exactly 1 error symbol") \ 283 m(+1, u64 rs_corrected_symbols_total, "rs_corrected_symbols_total", \ 284 "Port FEC corrected symbol counter") \ 285 m(+1, u64 rs_corrected_symbols_lane0, "rs_corrected_symbols_lane0", \ 286 "FEC corrected symbol counter lane 0") \ 287 m(+1, u64 rs_corrected_symbols_lane1, "rs_corrected_symbols_lane1", \ 288 "FEC corrected symbol counter lane 1") \ 289 m(+1, u64 rs_corrected_symbols_lane2, "rs_corrected_symbols_lane2", \ 290 "FEC corrected symbol counter lane 2") \ 291 m(+1, u64 rs_corrected_symbols_lane3, "rs_corrected_symbols_lane3", \ 292 "FEC corrected symbol counter lane 3") 293 294/* Per priority statistics for PFC */ 295#define MLX5E_PPORT_PER_PRIO_STATS_SUB(m,n,p) \ 296 m(n, p, +1, u64, rx_octets, "rx_octets", "Received octets") \ 297 m(n, p, +1, u64, reserved_0, "reserved_0", "Reserved") \ 298 m(n, p, +1, u64, reserved_1, "reserved_1", "Reserved") \ 299 m(n, p, +1, u64, reserved_2, "reserved_2", "Reserved") \ 300 m(n, p, +1, u64, rx_frames, "rx_frames", "Received frames") \ 301 m(n, p, +1, u64, tx_octets, "tx_octets", "Transmitted octets") \ 302 m(n, p, +1, u64, reserved_3, "reserved_3", "Reserved") \ 303 m(n, p, +1, u64, reserved_4, "reserved_4", "Reserved") \ 304 m(n, p, +1, u64, reserved_5, "reserved_5", "Reserved") \ 305 m(n, p, +1, u64, tx_frames, "tx_frames", "Transmitted frames") \ 306 m(n, p, +1, u64, rx_pause, "rx_pause", "Received pause frames") \ 307 m(n, p, +1, u64, rx_pause_duration, "rx_pause_duration", \ 308 "Received pause duration") \ 309 m(n, p, +1, u64, tx_pause, "tx_pause", "Transmitted pause frames") \ 310 m(n, p, +1, u64, tx_pause_duration, "tx_pause_duration", \ 311 "Transmitted pause duration") \ 312 m(n, p, +1, u64, rx_pause_transition, "rx_pause_transition", \ 313 "Received pause transitions") \ 314 m(n, p, +1, u64, rx_discards, "rx_discards", "Discarded received frames") \ 315 m(n, p, +1, u64, device_stall_minor_watermark, \ 316 "device_stall_minor_watermark", "Device stall minor watermark") \ 317 m(n, p, +1, u64, device_stall_critical_watermark, \ 318 "device_stall_critical_watermark", "Device stall critical watermark") 319 320#define MLX5E_PPORT_PER_PRIO_STATS_PREFIX(m,p,c,t,f,s,d) \ 321 m(c, t pri_##p##_##f, "prio" #p "_" s, "Priority " #p " - " d) 322 323#define MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO 8 324 325#define MLX5E_PPORT_PER_PRIO_STATS(m) \ 326 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,0) \ 327 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,1) \ 328 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,2) \ 329 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,3) \ 330 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,4) \ 331 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,5) \ 332 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,6) \ 333 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,7) 334 335/* 336 * Make sure to update mlx5e_update_pport_counters() 337 * when adding a new MLX5E_PPORT_STATS block 338 */ 339#define MLX5E_PPORT_STATS(m) \ 340 MLX5E_PPORT_PER_PRIO_STATS(m) \ 341 MLX5E_PPORT_IEEE802_3_STATS(m) \ 342 MLX5E_PPORT_RFC2819_STATS(m) 343 344#define MLX5E_PORT_STATS_DEBUG(m) \ 345 MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 346 MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 347 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) 348 349#define MLX5E_PPORT_IEEE802_3_STATS_NUM \ 350 (0 MLX5E_PPORT_IEEE802_3_STATS(MLX5E_STATS_COUNT)) 351#define MLX5E_PPORT_RFC2819_STATS_NUM \ 352 (0 MLX5E_PPORT_RFC2819_STATS(MLX5E_STATS_COUNT)) 353#define MLX5E_PPORT_STATS_NUM \ 354 (0 MLX5E_PPORT_STATS(MLX5E_STATS_COUNT)) 355 356#define MLX5E_PPORT_PER_PRIO_STATS_NUM \ 357 (0 MLX5E_PPORT_PER_PRIO_STATS(MLX5E_STATS_COUNT)) 358#define MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM \ 359 (0 MLX5E_PPORT_RFC2819_STATS_DEBUG(MLX5E_STATS_COUNT)) 360#define MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM \ 361 (0 MLX5E_PPORT_RFC2863_STATS_DEBUG(MLX5E_STATS_COUNT)) 362#define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM \ 363 (0 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(MLX5E_STATS_COUNT)) 364#define MLX5E_PORT_STATS_DEBUG_NUM \ 365 (0 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_COUNT)) 366 367struct mlx5e_pport_stats { 368 struct sysctl_ctx_list ctx; 369 u64 arg [0]; 370 MLX5E_PPORT_STATS(MLX5E_STATS_VAR) 371}; 372 373struct mlx5e_port_stats_debug { 374 struct sysctl_ctx_list ctx; 375 u64 arg [0]; 376 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_VAR) 377}; 378 379#define MLX5E_RQ_STATS(m) \ 380 m(+1, u64 packets, "packets", "Received packets") \ 381 m(+1, u64 csum_none, "csum_none", "Received packets") \ 382 m(+1, u64 lro_packets, "lro_packets", "Received packets") \ 383 m(+1, u64 lro_bytes, "lro_bytes", "Received packets") \ 384 m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 385 m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 386 m(+1, u64 wqe_err, "wqe_err", "Received packets") 387 388#define MLX5E_RQ_STATS_NUM (0 MLX5E_RQ_STATS(MLX5E_STATS_COUNT)) 389 390struct mlx5e_rq_stats { 391 struct sysctl_ctx_list ctx; 392 u64 arg [0]; 393 MLX5E_RQ_STATS(MLX5E_STATS_VAR) 394}; 395 396#define MLX5E_SQ_STATS(m) \ 397 m(+1, u64 packets, "packets", "Transmitted packets") \ 398 m(+1, u64 tso_packets, "tso_packets", "Transmitted packets") \ 399 m(+1, u64 tso_bytes, "tso_bytes", "Transmitted bytes") \ 400 m(+1, u64 csum_offload_none, "csum_offload_none", "Transmitted packets") \ 401 m(+1, u64 defragged, "defragged", "Transmitted packets") \ 402 m(+1, u64 dropped, "dropped", "Transmitted packets") \ 403 m(+1, u64 nop, "nop", "Transmitted packets") 404 405#define MLX5E_SQ_STATS_NUM (0 MLX5E_SQ_STATS(MLX5E_STATS_COUNT)) 406 407struct mlx5e_sq_stats { 408 struct sysctl_ctx_list ctx; 409 u64 arg [0]; 410 MLX5E_SQ_STATS(MLX5E_STATS_VAR) 411}; 412 413struct mlx5e_stats { 414 struct mlx5e_vport_stats vport; 415 struct mlx5e_pport_stats pport; 416 struct mlx5e_port_stats_debug port_stats_debug; 417}; 418 419struct mlx5e_rq_param { 420 u32 rqc [MLX5_ST_SZ_DW(rqc)]; 421 struct mlx5_wq_param wq; 422}; 423 424struct mlx5e_sq_param { 425 u32 sqc [MLX5_ST_SZ_DW(sqc)]; 426 struct mlx5_wq_param wq; 427}; 428 429struct mlx5e_cq_param { 430 u32 cqc [MLX5_ST_SZ_DW(cqc)]; 431 struct mlx5_wq_param wq; 432}; 433 434struct mlx5e_params { 435 u8 log_sq_size; 436 u8 log_rq_size; 437 u16 num_channels; 438 u8 default_vlan_prio; 439 u8 num_tc; 440 u8 rx_cq_moderation_mode; 441 u8 tx_cq_moderation_mode; 442 u16 rx_cq_moderation_usec; 443 u16 rx_cq_moderation_pkts; 444 u16 tx_cq_moderation_usec; 445 u16 tx_cq_moderation_pkts; 446 u16 min_rx_wqes; 447 bool hw_lro_en; 448 bool cqe_zipping_en; 449 u32 lro_wqe_sz; 450 u16 rx_hash_log_tbl_sz; 451 u32 tx_pauseframe_control __aligned(4); 452 u32 rx_pauseframe_control __aligned(4); 453 u32 tx_priority_flow_control __aligned(4); 454 u32 rx_priority_flow_control __aligned(4); 455 u16 tx_max_inline; 456 u8 tx_min_inline_mode; 457 u8 channels_rsss; 458}; 459 460#define MLX5E_PARAMS(m) \ 461 m(+1, u64 tx_queue_size_max, "tx_queue_size_max", "Max send queue size") \ 462 m(+1, u64 rx_queue_size_max, "rx_queue_size_max", "Max receive queue size") \ 463 m(+1, u64 tx_queue_size, "tx_queue_size", "Default send queue size") \ 464 m(+1, u64 rx_queue_size, "rx_queue_size", "Default receive queue size") \ 465 m(+1, u64 channels, "channels", "Default number of channels") \ 466 m(+1, u64 channels_rsss, "channels_rsss", "Default channels receive side scaling stride") \ 467 m(+1, u64 coalesce_usecs_max, "coalesce_usecs_max", "Maximum usecs for joining packets") \ 468 m(+1, u64 coalesce_pkts_max, "coalesce_pkts_max", "Maximum packets to join") \ 469 m(+1, u64 rx_coalesce_usecs, "rx_coalesce_usecs", "Limit in usec for joining rx packets") \ 470 m(+1, u64 rx_coalesce_pkts, "rx_coalesce_pkts", "Maximum number of rx packets to join") \ 471 m(+1, u64 rx_coalesce_mode, "rx_coalesce_mode", "0: EQE mode 1: CQE mode") \ 472 m(+1, u64 tx_coalesce_usecs, "tx_coalesce_usecs", "Limit in usec for joining tx packets") \ 473 m(+1, u64 tx_coalesce_pkts, "tx_coalesce_pkts", "Maximum number of tx packets to join") \ 474 m(+1, u64 tx_coalesce_mode, "tx_coalesce_mode", "0: EQE mode 1: CQE mode") \ 475 m(+1, u64 tx_bufring_disable, "tx_bufring_disable", "0: Enable bufring 1: Disable bufring") \ 476 m(+1, u64 tx_completion_fact, "tx_completion_fact", "1..MAX: Completion event ratio") \ 477 m(+1, u64 tx_completion_fact_max, "tx_completion_fact_max", "Maximum completion event ratio") \ 478 m(+1, u64 hw_lro, "hw_lro", "set to enable hw_lro") \ 479 m(+1, u64 cqe_zipping, "cqe_zipping", "0 : CQE zipping disabled") \ 480 m(+1, u64 modify_tx_dma, "modify_tx_dma", "0: Enable TX 1: Disable TX") \ 481 m(+1, u64 modify_rx_dma, "modify_rx_dma", "0: Enable RX 1: Disable RX") \ 482 m(+1, u64 diag_pci_enable, "diag_pci_enable", "0: Disabled 1: Enabled") \ 483 m(+1, u64 diag_general_enable, "diag_general_enable", "0: Disabled 1: Enabled") \ 484 m(+1, u64 hw_mtu, "hw_mtu", "Current hardware MTU value") \ 485 m(+1, u64 mc_local_lb, "mc_local_lb", "0: Local multicast loopback enabled 1: Disabled") \ 486 m(+1, u64 uc_local_lb, "uc_local_lb", "0: Local unicast loopback enabled 1: Disabled") 487 488 489#define MLX5E_PARAMS_NUM (0 MLX5E_PARAMS(MLX5E_STATS_COUNT)) 490 491struct mlx5e_params_ethtool { 492 u64 arg [0]; 493 MLX5E_PARAMS(MLX5E_STATS_VAR) 494 u64 max_bw_value[IEEE_8021QAZ_MAX_TCS]; 495 u8 max_bw_share[IEEE_8021QAZ_MAX_TCS]; 496 u8 prio_tc[IEEE_8021QAZ_MAX_TCS]; 497 u8 dscp2prio[MLX5_MAX_SUPPORTED_DSCP]; 498 u8 trust_state; 499}; 500 501/* EEPROM Standards for plug in modules */ 502#ifndef MLX5E_ETH_MODULE_SFF_8472 503#define MLX5E_ETH_MODULE_SFF_8472 0x1 504#define MLX5E_ETH_MODULE_SFF_8472_LEN 128 505#endif 506 507#ifndef MLX5E_ETH_MODULE_SFF_8636 508#define MLX5E_ETH_MODULE_SFF_8636 0x2 509#define MLX5E_ETH_MODULE_SFF_8636_LEN 256 510#endif 511 512#ifndef MLX5E_ETH_MODULE_SFF_8436 513#define MLX5E_ETH_MODULE_SFF_8436 0x3 514#define MLX5E_ETH_MODULE_SFF_8436_LEN 256 515#endif 516 517/* EEPROM I2C Addresses */ 518#define MLX5E_I2C_ADDR_LOW 0x50 519#define MLX5E_I2C_ADDR_HIGH 0x51 520 521#define MLX5E_EEPROM_LOW_PAGE 0x0 522#define MLX5E_EEPROM_HIGH_PAGE 0x3 523 524#define MLX5E_EEPROM_HIGH_PAGE_OFFSET 128 525#define MLX5E_EEPROM_PAGE_LENGTH 256 526 527#define MLX5E_EEPROM_INFO_BYTES 0x3 528 529struct mlx5e_cq { 530 /* data path - accessed per cqe */ 531 struct mlx5_cqwq wq; 532 533 /* data path - accessed per HW polling */ 534 struct mlx5_core_cq mcq; 535 536 /* control */ 537 struct mlx5e_priv *priv; 538 struct mlx5_wq_ctrl wq_ctrl; 539} __aligned(MLX5E_CACHELINE_SIZE); 540 541struct mlx5e_rq_mbuf { 542 bus_dmamap_t dma_map; 543 caddr_t data; 544 struct mbuf *mbuf; 545}; 546 547struct mlx5e_rq { 548 /* data path */ 549 struct mlx5_wq_ll wq; 550 struct mtx mtx; 551 bus_dma_tag_t dma_tag; 552 u32 wqe_sz; 553 u32 nsegs; 554 struct mlx5e_rq_mbuf *mbuf; 555 struct ifnet *ifp; 556 struct mlx5e_rq_stats stats; 557 struct mlx5e_cq cq; 558 struct lro_ctrl lro; 559 volatile int enabled; 560 int ix; 561 562 /* control */ 563 struct mlx5_wq_ctrl wq_ctrl; 564 u32 rqn; 565 struct mlx5e_channel *channel; 566 struct callout watchdog; 567} __aligned(MLX5E_CACHELINE_SIZE); 568 569struct mlx5e_sq_mbuf { 570 bus_dmamap_t dma_map; 571 struct mbuf *mbuf; 572 u32 num_bytes; 573 u32 num_wqebbs; 574}; 575 576enum { 577 MLX5E_SQ_READY, 578 MLX5E_SQ_FULL 579}; 580 581struct mlx5e_sq { 582 /* data path */ 583 struct mtx lock; 584 bus_dma_tag_t dma_tag; 585 struct mtx comp_lock; 586 587 /* dirtied @completion */ 588 u16 cc; 589 590 /* dirtied @xmit */ 591 u16 pc __aligned(MLX5E_CACHELINE_SIZE); 592 u16 bf_offset; 593 u16 cev_counter; /* completion event counter */ 594 u16 cev_factor; /* completion event factor */ 595 u16 cev_next_state; /* next completion event state */ 596#define MLX5E_CEV_STATE_INITIAL 0 /* timer not started */ 597#define MLX5E_CEV_STATE_SEND_NOPS 1 /* send NOPs */ 598#define MLX5E_CEV_STATE_HOLD_NOPS 2 /* don't send NOPs yet */ 599 u16 stopped; /* set if SQ is stopped */ 600 struct callout cev_callout; 601 union { 602 u32 d32[2]; 603 u64 d64; 604 } doorbell; 605 struct mlx5e_sq_stats stats; 606 607 struct mlx5e_cq cq; 608 struct task sq_task; 609 struct taskqueue *sq_tq; 610 611 /* pointers to per packet info: write@xmit, read@completion */ 612 struct mlx5e_sq_mbuf *mbuf; 613 struct buf_ring *br; 614 615 /* read only */ 616 struct mlx5_wq_cyc wq; 617 struct mlx5_uar uar; 618 struct ifnet *ifp; 619 u32 sqn; 620 u32 bf_buf_size; 621 u32 mkey_be; 622 u16 max_inline; 623 u8 min_inline_mode; 624 u8 vlan_inline_cap; 625 626 /* control path */ 627 struct mlx5_wq_ctrl wq_ctrl; 628 struct mlx5e_priv *priv; 629 int tc; 630 unsigned int queue_state; 631} __aligned(MLX5E_CACHELINE_SIZE); 632 633static inline bool 634mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) 635{ 636 u16 cc = sq->cc; 637 u16 pc = sq->pc; 638 639 return ((sq->wq.sz_m1 & (cc - pc)) >= n || cc == pc); 640} 641 642struct mlx5e_channel { 643 /* data path */ 644 struct mlx5e_rq rq; 645 struct mlx5e_sq sq[MLX5E_MAX_TX_NUM_TC]; 646 struct ifnet *ifp; 647 u32 mkey_be; 648 u8 num_tc; 649 650 /* control */ 651 struct mlx5e_priv *priv; 652 int ix; 653 int cpu; 654} __aligned(MLX5E_CACHELINE_SIZE); 655 656enum mlx5e_traffic_types { 657 MLX5E_TT_IPV4_TCP, 658 MLX5E_TT_IPV6_TCP, 659 MLX5E_TT_IPV4_UDP, 660 MLX5E_TT_IPV6_UDP, 661 MLX5E_TT_IPV4_IPSEC_AH, 662 MLX5E_TT_IPV6_IPSEC_AH, 663 MLX5E_TT_IPV4_IPSEC_ESP, 664 MLX5E_TT_IPV6_IPSEC_ESP, 665 MLX5E_TT_IPV4, 666 MLX5E_TT_IPV6, 667 MLX5E_TT_ANY, 668 MLX5E_NUM_TT, 669}; 670 671enum { 672 MLX5E_RQT_SPREADING = 0, 673 MLX5E_RQT_DEFAULT_RQ = 1, 674 MLX5E_NUM_RQT = 2, 675}; 676 677struct mlx5_flow_rule; 678 679struct mlx5e_eth_addr_info { 680 u8 addr [ETH_ALEN + 2]; 681 u32 tt_vec; 682 /* flow table rule per traffic type */ 683 struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT]; 684}; 685 686#define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE) 687 688struct mlx5e_eth_addr_hash_node; 689 690struct mlx5e_eth_addr_hash_head { 691 struct mlx5e_eth_addr_hash_node *lh_first; 692}; 693 694struct mlx5e_eth_addr_db { 695 struct mlx5e_eth_addr_hash_head if_uc[MLX5E_ETH_ADDR_HASH_SIZE]; 696 struct mlx5e_eth_addr_hash_head if_mc[MLX5E_ETH_ADDR_HASH_SIZE]; 697 struct mlx5e_eth_addr_info broadcast; 698 struct mlx5e_eth_addr_info allmulti; 699 struct mlx5e_eth_addr_info promisc; 700 bool broadcast_enabled; 701 bool allmulti_enabled; 702 bool promisc_enabled; 703}; 704 705enum { 706 MLX5E_STATE_ASYNC_EVENTS_ENABLE, 707 MLX5E_STATE_OPENED, 708}; 709 710enum { 711 MLX5_BW_NO_LIMIT = 0, 712 MLX5_100_MBPS_UNIT = 3, 713 MLX5_GBPS_UNIT = 4, 714}; 715 716struct mlx5e_vlan_db { 717 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 718 struct mlx5_flow_rule *active_vlans_ft_rule[VLAN_N_VID]; 719 struct mlx5_flow_rule *untagged_ft_rule; 720 struct mlx5_flow_rule *any_cvlan_ft_rule; 721 struct mlx5_flow_rule *any_svlan_ft_rule; 722 bool filter_disabled; 723}; 724 725struct mlx5e_flow_table { 726 int num_groups; 727 struct mlx5_flow_table *t; 728 struct mlx5_flow_group **g; 729}; 730 731struct mlx5e_flow_tables { 732 struct mlx5_flow_namespace *ns; 733 struct mlx5e_flow_table vlan; 734 struct mlx5e_flow_table main; 735 struct mlx5e_flow_table inner_rss; 736}; 737 738struct mlx5e_priv { 739 struct mlx5_core_dev *mdev; /* must be first */ 740 741 /* priv data path fields - start */ 742 int order_base_2_num_channels; 743 int queue_mapping_channel_mask; 744 int num_tc; 745 int default_vlan_prio; 746 /* priv data path fields - end */ 747 748 unsigned long state; 749 int gone; 750#define PRIV_LOCK(priv) sx_xlock(&(priv)->state_lock) 751#define PRIV_UNLOCK(priv) sx_xunlock(&(priv)->state_lock) 752#define PRIV_LOCKED(priv) sx_xlocked(&(priv)->state_lock) 753 struct sx state_lock; /* Protects Interface state */ 754 struct mlx5_uar cq_uar; 755 u32 pdn; 756 u32 tdn; 757 struct mlx5_core_mr mr; 758 759 struct mlx5e_channel *volatile *channel; 760 u32 tisn[MLX5E_MAX_TX_NUM_TC]; 761 u32 rqtn; 762 u32 tirn[MLX5E_NUM_TT]; 763 764 struct mlx5e_flow_tables fts; 765 struct mlx5e_eth_addr_db eth_addr; 766 struct mlx5e_vlan_db vlan; 767 768 struct mlx5e_params params; 769 struct mlx5e_params_ethtool params_ethtool; 770 union mlx5_core_pci_diagnostics params_pci; 771 union mlx5_core_general_diagnostics params_general; 772 struct mtx async_events_mtx; /* sync hw events */ 773 struct work_struct update_stats_work; 774 struct work_struct update_carrier_work; 775 struct work_struct set_rx_mode_work; 776 MLX5_DECLARE_DOORBELL_LOCK(doorbell_lock) 777 778 struct ifnet *ifp; 779 struct sysctl_ctx_list sysctl_ctx; 780 struct sysctl_oid *sysctl_ifnet; 781 struct sysctl_oid *sysctl_hw; 782 int sysctl_debug; 783 struct mlx5e_stats stats; 784 struct sysctl_ctx_list sysctl_ctx_channel_debug; 785 int counter_set_id; 786 787 struct workqueue_struct *wq; 788 789 eventhandler_tag vlan_detach; 790 eventhandler_tag vlan_attach; 791 struct ifmedia media; 792 int media_status_last; 793 int media_active_last; 794 795 struct callout watchdog; 796}; 797 798#define MLX5E_NET_IP_ALIGN 2 799 800struct mlx5e_tx_wqe { 801 struct mlx5_wqe_ctrl_seg ctrl; 802 struct mlx5_wqe_eth_seg eth; 803}; 804 805struct mlx5e_rx_wqe { 806 struct mlx5_wqe_srq_next_seg next; 807 struct mlx5_wqe_data_seg data[]; 808}; 809 810/* the size of the structure above must be power of two */ 811CTASSERT(powerof2(sizeof(struct mlx5e_rx_wqe))); 812 813struct mlx5e_eeprom { 814 int lock_bit; 815 int i2c_addr; 816 int page_num; 817 int device_addr; 818 int module_num; 819 int len; 820 int type; 821 int page_valid; 822 u32 *data; 823}; 824 825#define MLX5E_FLD_MAX(typ, fld) ((1ULL << __mlx5_bit_sz(typ, fld)) - 1ULL) 826 827int mlx5e_xmit(struct ifnet *, struct mbuf *); 828 829int mlx5e_open_locked(struct ifnet *); 830int mlx5e_close_locked(struct ifnet *); 831 832void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, int event); 833void mlx5e_rx_cq_comp(struct mlx5_core_cq *); 834void mlx5e_tx_cq_comp(struct mlx5_core_cq *); 835struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); 836void mlx5e_tx_que(void *context, int pending); 837 838int mlx5e_open_flow_table(struct mlx5e_priv *priv); 839void mlx5e_close_flow_table(struct mlx5e_priv *priv); 840void mlx5e_set_rx_mode_core(struct mlx5e_priv *priv); 841void mlx5e_set_rx_mode_work(struct work_struct *work); 842 843void mlx5e_vlan_rx_add_vid(void *, struct ifnet *, u16); 844void mlx5e_vlan_rx_kill_vid(void *, struct ifnet *, u16); 845void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); 846void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); 847int mlx5e_add_all_vlan_rules(struct mlx5e_priv *priv); 848void mlx5e_del_all_vlan_rules(struct mlx5e_priv *priv); 849 850static inline void 851mlx5e_tx_notify_hw(struct mlx5e_sq *sq, u32 *wqe, int bf_sz) 852{ 853 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; 854 855 /* ensure wqe is visible to device before updating doorbell record */ 856 wmb(); 857 858 *sq->wq.db = cpu_to_be32(sq->pc); 859 860 /* 861 * Ensure the doorbell record is visible to device before ringing 862 * the doorbell: 863 */ 864 wmb(); 865 866 if (bf_sz) { 867 __iowrite64_copy(sq->uar.bf_map + ofst, wqe, bf_sz); 868 869 /* flush the write-combining mapped buffer */ 870 wmb(); 871 872 } else { 873 mlx5_write64(wqe, sq->uar.map + ofst, 874 MLX5_GET_DOORBELL_LOCK(&sq->priv->doorbell_lock)); 875 } 876 877 sq->bf_offset ^= sq->bf_buf_size; 878} 879 880static inline void 881mlx5e_cq_arm(struct mlx5e_cq *cq, spinlock_t *dblock) 882{ 883 struct mlx5_core_cq *mcq; 884 885 mcq = &cq->mcq; 886 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, dblock, cq->wq.cc); 887} 888 889extern const struct ethtool_ops mlx5e_ethtool_ops; 890void mlx5e_create_ethtool(struct mlx5e_priv *); 891void mlx5e_create_stats(struct sysctl_ctx_list *, 892 struct sysctl_oid_list *, const char *, 893 const char **, unsigned, u64 *); 894void mlx5e_send_nop(struct mlx5e_sq *, u32); 895void mlx5e_sq_cev_timeout(void *); 896int mlx5e_refresh_channel_params(struct mlx5e_priv *); 897int mlx5e_open_cq(struct mlx5e_priv *, struct mlx5e_cq_param *, 898 struct mlx5e_cq *, mlx5e_cq_comp_t *, int eq_ix); 899void mlx5e_close_cq(struct mlx5e_cq *); 900void mlx5e_free_sq_db(struct mlx5e_sq *); 901int mlx5e_alloc_sq_db(struct mlx5e_sq *); 902int mlx5e_enable_sq(struct mlx5e_sq *, struct mlx5e_sq_param *, int tis_num); 903int mlx5e_modify_sq(struct mlx5e_sq *, int curr_state, int next_state); 904void mlx5e_disable_sq(struct mlx5e_sq *); 905void mlx5e_drain_sq(struct mlx5e_sq *); 906void mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value); 907void mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value); 908void mlx5e_resume_sq(struct mlx5e_sq *sq); 909u8 mlx5e_params_calculate_tx_min_inline(struct mlx5_core_dev *mdev); 910 911#endif /* _MLX5_EN_H_ */ 912