en.h revision 331569
1/*- 2 * Copyright (c) 2015 Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_en/en.h 331569 2018-03-26 20:00:30Z hselasky $ 26 */ 27 28#ifndef _MLX5_EN_H_ 29#define _MLX5_EN_H_ 30 31#include <linux/kmod.h> 32#include <linux/page.h> 33#include <linux/slab.h> 34#include <linux/if_vlan.h> 35#include <linux/if_ether.h> 36#include <linux/vmalloc.h> 37#include <linux/moduleparam.h> 38#include <linux/delay.h> 39#include <linux/netdevice.h> 40#include <linux/etherdevice.h> 41 42#include <netinet/in_systm.h> 43#include <netinet/in.h> 44#include <netinet/if_ether.h> 45#include <netinet/ip.h> 46#include <netinet/ip6.h> 47#include <netinet/tcp.h> 48#include <netinet/tcp_lro.h> 49#include <netinet/udp.h> 50#include <net/ethernet.h> 51#include <sys/buf_ring.h> 52 53#include "opt_rss.h" 54 55#ifdef RSS 56#include <net/rss_config.h> 57#include <netinet/in_rss.h> 58#endif 59 60#include <machine/bus.h> 61 62#include <dev/mlx5/driver.h> 63#include <dev/mlx5/qp.h> 64#include <dev/mlx5/cq.h> 65#include <dev/mlx5/vport.h> 66#include <dev/mlx5/diagnostics.h> 67 68#include <dev/mlx5/mlx5_core/wq.h> 69#include <dev/mlx5/mlx5_core/transobj.h> 70#include <dev/mlx5/mlx5_core/mlx5_core.h> 71 72#define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x7 73#define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa 74#define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xe 75 76#define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x7 77#define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa 78#define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xe 79 80/* freeBSD HW LRO is limited by 16KB - the size of max mbuf */ 81#define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ MJUM16BYTES 82#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 83#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 84#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 85#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 86#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 87#define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 88#define MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ 0x7 89#define MLX5E_CACHELINE_SIZE CACHE_LINE_SIZE 90#define MLX5E_HW2SW_MTU(hwmtu) \ 91 ((hwmtu) - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 92#define MLX5E_SW2HW_MTU(swmtu) \ 93 ((swmtu) + (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 94#define MLX5E_SW2MB_MTU(swmtu) \ 95 (MLX5E_SW2HW_MTU(swmtu) + MLX5E_NET_IP_ALIGN) 96#define MLX5E_MTU_MIN 72 /* Min MTU allowed by the kernel */ 97#define MLX5E_MTU_MAX MIN(ETHERMTU_JUMBO, MJUM16BYTES) /* Max MTU of Ethernet 98 * jumbo frames */ 99 100#define MLX5E_BUDGET_MAX 8192 /* RX and TX */ 101#define MLX5E_RX_BUDGET_MAX 256 102#define MLX5E_SQ_BF_BUDGET 16 103#define MLX5E_SQ_TX_QUEUE_SIZE 4096 /* SQ drbr queue size */ 104 105#define MLX5E_MAX_TX_NUM_TC 8 /* units */ 106#define MLX5E_MAX_TX_HEADER 128 /* bytes */ 107#define MLX5E_MAX_TX_PAYLOAD_SIZE 65536 /* bytes */ 108#define MLX5E_MAX_TX_MBUF_SIZE 65536 /* bytes */ 109#define MLX5E_MAX_TX_MBUF_FRAGS \ 110 ((MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS) - \ 111 (MLX5E_MAX_TX_HEADER / MLX5_SEND_WQE_DS)) /* units */ 112#define MLX5E_MAX_TX_INLINE \ 113 (MLX5E_MAX_TX_HEADER - sizeof(struct mlx5e_tx_wqe) + \ 114 sizeof(((struct mlx5e_tx_wqe *)0)->eth.inline_hdr_start)) /* bytes */ 115 116MALLOC_DECLARE(M_MLX5EN); 117 118struct mlx5_core_dev; 119struct mlx5e_cq; 120 121typedef void (mlx5e_cq_comp_t)(struct mlx5_core_cq *); 122 123#define MLX5E_STATS_COUNT(a,b,c,d) a 124#define MLX5E_STATS_VAR(a,b,c,d) b; 125#define MLX5E_STATS_DESC(a,b,c,d) c, d, 126 127#define MLX5E_VPORT_STATS(m) \ 128 /* HW counters */ \ 129 m(+1, u64 rx_packets, "rx_packets", "Received packets") \ 130 m(+1, u64 rx_bytes, "rx_bytes", "Received bytes") \ 131 m(+1, u64 tx_packets, "tx_packets", "Transmitted packets") \ 132 m(+1, u64 tx_bytes, "tx_bytes", "Transmitted bytes") \ 133 m(+1, u64 rx_error_packets, "rx_error_packets", "Received error packets") \ 134 m(+1, u64 rx_error_bytes, "rx_error_bytes", "Received error bytes") \ 135 m(+1, u64 tx_error_packets, "tx_error_packets", "Transmitted error packets") \ 136 m(+1, u64 tx_error_bytes, "tx_error_bytes", "Transmitted error bytes") \ 137 m(+1, u64 rx_unicast_packets, "rx_unicast_packets", "Received unicast packets") \ 138 m(+1, u64 rx_unicast_bytes, "rx_unicast_bytes", "Received unicast bytes") \ 139 m(+1, u64 tx_unicast_packets, "tx_unicast_packets", "Transmitted unicast packets") \ 140 m(+1, u64 tx_unicast_bytes, "tx_unicast_bytes", "Transmitted unicast bytes") \ 141 m(+1, u64 rx_multicast_packets, "rx_multicast_packets", "Received multicast packets") \ 142 m(+1, u64 rx_multicast_bytes, "rx_multicast_bytes", "Received multicast bytes") \ 143 m(+1, u64 tx_multicast_packets, "tx_multicast_packets", "Transmitted multicast packets") \ 144 m(+1, u64 tx_multicast_bytes, "tx_multicast_bytes", "Transmitted multicast bytes") \ 145 m(+1, u64 rx_broadcast_packets, "rx_broadcast_packets", "Received broadcast packets") \ 146 m(+1, u64 rx_broadcast_bytes, "rx_broadcast_bytes", "Received broadcast bytes") \ 147 m(+1, u64 tx_broadcast_packets, "tx_broadcast_packets", "Transmitted broadcast packets") \ 148 m(+1, u64 tx_broadcast_bytes, "tx_broadcast_bytes", "Transmitted broadcast bytes") \ 149 m(+1, u64 rx_out_of_buffer, "rx_out_of_buffer", "Receive out of buffer, no recv wqes events") \ 150 /* SW counters */ \ 151 m(+1, u64 tso_packets, "tso_packets", "Transmitted TSO packets") \ 152 m(+1, u64 tso_bytes, "tso_bytes", "Transmitted TSO bytes") \ 153 m(+1, u64 lro_packets, "lro_packets", "Received LRO packets") \ 154 m(+1, u64 lro_bytes, "lro_bytes", "Received LRO bytes") \ 155 m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 156 m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 157 m(+1, u64 rx_csum_good, "rx_csum_good", "Received checksum valid packets") \ 158 m(+1, u64 rx_csum_none, "rx_csum_none", "Received no checksum packets") \ 159 m(+1, u64 tx_csum_offload, "tx_csum_offload", "Transmit checksum offload packets") \ 160 m(+1, u64 tx_queue_dropped, "tx_queue_dropped", "Transmit queue dropped") \ 161 m(+1, u64 tx_defragged, "tx_defragged", "Transmit queue defragged") \ 162 m(+1, u64 rx_wqe_err, "rx_wqe_err", "Receive WQE errors") 163 164#define MLX5E_VPORT_STATS_NUM (0 MLX5E_VPORT_STATS(MLX5E_STATS_COUNT)) 165 166struct mlx5e_vport_stats { 167 struct sysctl_ctx_list ctx; 168 u64 arg [0]; 169 MLX5E_VPORT_STATS(MLX5E_STATS_VAR) 170 u32 rx_out_of_buffer_prev; 171}; 172 173#define MLX5E_PPORT_IEEE802_3_STATS(m) \ 174 m(+1, u64 frames_tx, "frames_tx", "Frames transmitted") \ 175 m(+1, u64 frames_rx, "frames_rx", "Frames received") \ 176 m(+1, u64 check_seq_err, "check_seq_err", "Sequence errors") \ 177 m(+1, u64 alignment_err, "alignment_err", "Alignment errors") \ 178 m(+1, u64 octets_tx, "octets_tx", "Bytes transmitted") \ 179 m(+1, u64 octets_received, "octets_received", "Bytes received") \ 180 m(+1, u64 multicast_xmitted, "multicast_xmitted", "Multicast transmitted") \ 181 m(+1, u64 broadcast_xmitted, "broadcast_xmitted", "Broadcast transmitted") \ 182 m(+1, u64 multicast_rx, "multicast_rx", "Multicast received") \ 183 m(+1, u64 broadcast_rx, "broadcast_rx", "Broadcast received") \ 184 m(+1, u64 in_range_len_errors, "in_range_len_errors", "In range length errors") \ 185 m(+1, u64 out_of_range_len, "out_of_range_len", "Out of range length errors") \ 186 m(+1, u64 too_long_errors, "too_long_errors", "Too long errors") \ 187 m(+1, u64 symbol_err, "symbol_err", "Symbol errors") \ 188 m(+1, u64 mac_control_tx, "mac_control_tx", "MAC control transmitted") \ 189 m(+1, u64 mac_control_rx, "mac_control_rx", "MAC control received") \ 190 m(+1, u64 unsupported_op_rx, "unsupported_op_rx", "Unsupported operation received") \ 191 m(+1, u64 pause_ctrl_rx, "pause_ctrl_rx", "Pause control received") \ 192 m(+1, u64 pause_ctrl_tx, "pause_ctrl_tx", "Pause control transmitted") 193 194#define MLX5E_PPORT_RFC2819_STATS(m) \ 195 m(+1, u64 drop_events, "drop_events", "Dropped events") \ 196 m(+1, u64 octets, "octets", "Octets") \ 197 m(+1, u64 pkts, "pkts", "Packets") \ 198 m(+1, u64 broadcast_pkts, "broadcast_pkts", "Broadcast packets") \ 199 m(+1, u64 multicast_pkts, "multicast_pkts", "Multicast packets") \ 200 m(+1, u64 crc_align_errors, "crc_align_errors", "CRC alignment errors") \ 201 m(+1, u64 undersize_pkts, "undersize_pkts", "Undersized packets") \ 202 m(+1, u64 oversize_pkts, "oversize_pkts", "Oversized packets") \ 203 m(+1, u64 fragments, "fragments", "Fragments") \ 204 m(+1, u64 jabbers, "jabbers", "Jabbers") \ 205 m(+1, u64 collisions, "collisions", "Collisions") 206 207#define MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 208 m(+1, u64 p64octets, "p64octets", "Bytes") \ 209 m(+1, u64 p65to127octets, "p65to127octets", "Bytes") \ 210 m(+1, u64 p128to255octets, "p128to255octets", "Bytes") \ 211 m(+1, u64 p256to511octets, "p256to511octets", "Bytes") \ 212 m(+1, u64 p512to1023octets, "p512to1023octets", "Bytes") \ 213 m(+1, u64 p1024to1518octets, "p1024to1518octets", "Bytes") \ 214 m(+1, u64 p1519to2047octets, "p1519to2047octets", "Bytes") \ 215 m(+1, u64 p2048to4095octets, "p2048to4095octets", "Bytes") \ 216 m(+1, u64 p4096to8191octets, "p4096to8191octets", "Bytes") \ 217 m(+1, u64 p8192to10239octets, "p8192to10239octets", "Bytes") 218 219#define MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 220 m(+1, u64 in_octets, "in_octets", "In octets") \ 221 m(+1, u64 in_ucast_pkts, "in_ucast_pkts", "In unicast packets") \ 222 m(+1, u64 in_discards, "in_discards", "In discards") \ 223 m(+1, u64 in_errors, "in_errors", "In errors") \ 224 m(+1, u64 in_unknown_protos, "in_unknown_protos", "In unknown protocols") \ 225 m(+1, u64 out_octets, "out_octets", "Out octets") \ 226 m(+1, u64 out_ucast_pkts, "out_ucast_pkts", "Out unicast packets") \ 227 m(+1, u64 out_discards, "out_discards", "Out discards") \ 228 m(+1, u64 out_errors, "out_errors", "Out errors") \ 229 m(+1, u64 in_multicast_pkts, "in_multicast_pkts", "In multicast packets") \ 230 m(+1, u64 in_broadcast_pkts, "in_broadcast_pkts", "In broadcast packets") \ 231 m(+1, u64 out_multicast_pkts, "out_multicast_pkts", "Out multicast packets") \ 232 m(+1, u64 out_broadcast_pkts, "out_broadcast_pkts", "Out broadcast packets") 233 234#define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \ 235 m(+1, u64 time_since_last_clear, "time_since_last_clear", \ 236 "Time since the last counters clear event (msec)") \ 237 m(+1, u64 symbol_errors, "symbol_errors", "Symbol errors") \ 238 m(+1, u64 sync_headers_errors, "sync_headers_errors", "Sync header error counter") \ 239 m(+1, u64 bip_errors_lane0, "edpl_bip_errors_lane0", \ 240 "Indicates the number of PRBS errors on lane 0") \ 241 m(+1, u64 bip_errors_lane1, "edpl_bip_errors_lane1", \ 242 "Indicates the number of PRBS errors on lane 1") \ 243 m(+1, u64 bip_errors_lane2, "edpl_bip_errors_lane2", \ 244 "Indicates the number of PRBS errors on lane 2") \ 245 m(+1, u64 bip_errors_lane3, "edpl_bip_errors_lane3", \ 246 "Indicates the number of PRBS errors on lane 3") \ 247 m(+1, u64 fc_corrected_blocks_lane0, "fc_corrected_blocks_lane0", \ 248 "FEC correctable block counter lane 0") \ 249 m(+1, u64 fc_corrected_blocks_lane1, "fc_corrected_blocks_lane1", \ 250 "FEC correctable block counter lane 1") \ 251 m(+1, u64 fc_corrected_blocks_lane2, "fc_corrected_blocks_lane2", \ 252 "FEC correctable block counter lane 2") \ 253 m(+1, u64 fc_corrected_blocks_lane3, "fc_corrected_blocks_lane3", \ 254 "FEC correctable block counter lane 3") \ 255 m(+1, u64 rs_corrected_blocks, "rs_corrected_blocks", \ 256 "FEC correcable block counter") \ 257 m(+1, u64 rs_uncorrectable_blocks, "rs_uncorrectable_blocks", \ 258 "FEC uncorrecable block counter") \ 259 m(+1, u64 rs_no_errors_blocks, "rs_no_errors_blocks", \ 260 "The number of RS-FEC blocks received that had no errors") \ 261 m(+1, u64 rs_single_error_blocks, "rs_single_error_blocks", \ 262 "The number of corrected RS-FEC blocks received that had" \ 263 "exactly 1 error symbol") \ 264 m(+1, u64 rs_corrected_symbols_total, "rs_corrected_symbols_total", \ 265 "Port FEC corrected symbol counter") \ 266 m(+1, u64 rs_corrected_symbols_lane0, "rs_corrected_symbols_lane0", \ 267 "FEC corrected symbol counter lane 0") \ 268 m(+1, u64 rs_corrected_symbols_lane1, "rs_corrected_symbols_lane1", \ 269 "FEC corrected symbol counter lane 1") \ 270 m(+1, u64 rs_corrected_symbols_lane2, "rs_corrected_symbols_lane2", \ 271 "FEC corrected symbol counter lane 2") \ 272 m(+1, u64 rs_corrected_symbols_lane3, "rs_corrected_symbols_lane3", \ 273 "FEC corrected symbol counter lane 3") \ 274 275/* 276 * Make sure to update mlx5e_update_pport_counters() 277 * when adding a new MLX5E_PPORT_STATS block 278 */ 279#define MLX5E_PPORT_STATS(m) \ 280 MLX5E_PPORT_IEEE802_3_STATS(m) \ 281 MLX5E_PPORT_RFC2819_STATS(m) 282 283#define MLX5E_PORT_STATS_DEBUG(m) \ 284 MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 285 MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 286 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) 287 288#define MLX5E_PPORT_IEEE802_3_STATS_NUM \ 289 (0 MLX5E_PPORT_IEEE802_3_STATS(MLX5E_STATS_COUNT)) 290#define MLX5E_PPORT_RFC2819_STATS_NUM \ 291 (0 MLX5E_PPORT_RFC2819_STATS(MLX5E_STATS_COUNT)) 292#define MLX5E_PPORT_STATS_NUM \ 293 (0 MLX5E_PPORT_STATS(MLX5E_STATS_COUNT)) 294 295#define MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM \ 296 (0 MLX5E_PPORT_RFC2819_STATS_DEBUG(MLX5E_STATS_COUNT)) 297#define MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM \ 298 (0 MLX5E_PPORT_RFC2863_STATS_DEBUG(MLX5E_STATS_COUNT)) 299#define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM \ 300 (0 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(MLX5E_STATS_COUNT)) 301#define MLX5E_PORT_STATS_DEBUG_NUM \ 302 (0 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_COUNT)) 303 304struct mlx5e_pport_stats { 305 struct sysctl_ctx_list ctx; 306 u64 arg [0]; 307 MLX5E_PPORT_STATS(MLX5E_STATS_VAR) 308}; 309 310struct mlx5e_port_stats_debug { 311 struct sysctl_ctx_list ctx; 312 u64 arg [0]; 313 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_VAR) 314}; 315 316#define MLX5E_RQ_STATS(m) \ 317 m(+1, u64 packets, "packets", "Received packets") \ 318 m(+1, u64 csum_none, "csum_none", "Received packets") \ 319 m(+1, u64 lro_packets, "lro_packets", "Received packets") \ 320 m(+1, u64 lro_bytes, "lro_bytes", "Received packets") \ 321 m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 322 m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 323 m(+1, u64 wqe_err, "wqe_err", "Received packets") 324 325#define MLX5E_RQ_STATS_NUM (0 MLX5E_RQ_STATS(MLX5E_STATS_COUNT)) 326 327struct mlx5e_rq_stats { 328 struct sysctl_ctx_list ctx; 329 u64 arg [0]; 330 MLX5E_RQ_STATS(MLX5E_STATS_VAR) 331}; 332 333#define MLX5E_SQ_STATS(m) \ 334 m(+1, u64 packets, "packets", "Transmitted packets") \ 335 m(+1, u64 tso_packets, "tso_packets", "Transmitted packets") \ 336 m(+1, u64 tso_bytes, "tso_bytes", "Transmitted bytes") \ 337 m(+1, u64 csum_offload_none, "csum_offload_none", "Transmitted packets") \ 338 m(+1, u64 defragged, "defragged", "Transmitted packets") \ 339 m(+1, u64 dropped, "dropped", "Transmitted packets") \ 340 m(+1, u64 nop, "nop", "Transmitted packets") 341 342#define MLX5E_SQ_STATS_NUM (0 MLX5E_SQ_STATS(MLX5E_STATS_COUNT)) 343 344struct mlx5e_sq_stats { 345 struct sysctl_ctx_list ctx; 346 u64 arg [0]; 347 MLX5E_SQ_STATS(MLX5E_STATS_VAR) 348}; 349 350struct mlx5e_stats { 351 struct mlx5e_vport_stats vport; 352 struct mlx5e_pport_stats pport; 353 struct mlx5e_port_stats_debug port_stats_debug; 354}; 355 356struct mlx5e_rq_param { 357 u32 rqc [MLX5_ST_SZ_DW(rqc)]; 358 struct mlx5_wq_param wq; 359}; 360 361struct mlx5e_sq_param { 362 u32 sqc [MLX5_ST_SZ_DW(sqc)]; 363 struct mlx5_wq_param wq; 364}; 365 366struct mlx5e_cq_param { 367 u32 cqc [MLX5_ST_SZ_DW(cqc)]; 368 struct mlx5_wq_param wq; 369}; 370 371struct mlx5e_params { 372 u8 log_sq_size; 373 u8 log_rq_size; 374 u16 num_channels; 375 u8 default_vlan_prio; 376 u8 num_tc; 377 u8 rx_cq_moderation_mode; 378 u8 tx_cq_moderation_mode; 379 u16 rx_cq_moderation_usec; 380 u16 rx_cq_moderation_pkts; 381 u16 tx_cq_moderation_usec; 382 u16 tx_cq_moderation_pkts; 383 u16 min_rx_wqes; 384 bool hw_lro_en; 385 bool cqe_zipping_en; 386 u32 lro_wqe_sz; 387 u16 rx_hash_log_tbl_sz; 388 u32 tx_pauseframe_control; 389 u32 rx_pauseframe_control; 390}; 391 392#define MLX5E_PARAMS(m) \ 393 m(+1, u64 tx_queue_size_max, "tx_queue_size_max", "Max send queue size") \ 394 m(+1, u64 rx_queue_size_max, "rx_queue_size_max", "Max receive queue size") \ 395 m(+1, u64 tx_queue_size, "tx_queue_size", "Default send queue size") \ 396 m(+1, u64 rx_queue_size, "rx_queue_size", "Default receive queue size") \ 397 m(+1, u64 channels, "channels", "Default number of channels") \ 398 m(+1, u64 coalesce_usecs_max, "coalesce_usecs_max", "Maximum usecs for joining packets") \ 399 m(+1, u64 coalesce_pkts_max, "coalesce_pkts_max", "Maximum packets to join") \ 400 m(+1, u64 rx_coalesce_usecs, "rx_coalesce_usecs", "Limit in usec for joining rx packets") \ 401 m(+1, u64 rx_coalesce_pkts, "rx_coalesce_pkts", "Maximum number of rx packets to join") \ 402 m(+1, u64 rx_coalesce_mode, "rx_coalesce_mode", "0: EQE mode 1: CQE mode") \ 403 m(+1, u64 tx_coalesce_usecs, "tx_coalesce_usecs", "Limit in usec for joining tx packets") \ 404 m(+1, u64 tx_coalesce_pkts, "tx_coalesce_pkts", "Maximum number of tx packets to join") \ 405 m(+1, u64 tx_coalesce_mode, "tx_coalesce_mode", "0: EQE mode 1: CQE mode") \ 406 m(+1, u64 tx_bufring_disable, "tx_bufring_disable", "0: Enable bufring 1: Disable bufring") \ 407 m(+1, u64 tx_completion_fact, "tx_completion_fact", "1..MAX: Completion event ratio") \ 408 m(+1, u64 tx_completion_fact_max, "tx_completion_fact_max", "Maximum completion event ratio") \ 409 m(+1, u64 hw_lro, "hw_lro", "set to enable hw_lro") \ 410 m(+1, u64 cqe_zipping, "cqe_zipping", "0 : CQE zipping disabled") \ 411 m(+1, u64 modify_tx_dma, "modify_tx_dma", "0: Enable TX 1: Disable TX") \ 412 m(+1, u64 modify_rx_dma, "modify_rx_dma", "0: Enable RX 1: Disable RX") \ 413 m(+1, u64 diag_pci_enable, "diag_pci_enable", "0: Disabled 1: Enabled") \ 414 m(+1, u64 diag_general_enable, "diag_general_enable", "0: Disabled 1: Enabled") \ 415 m(+1, u64 mc_local_lb, "mc_local_lb", "0: Local multicast loopback enabled 1: Disabled") \ 416 m(+1, u64 uc_local_lb, "uc_local_lb", "0: Local unicast loopback enabled 1: Disabled") 417 418#define MLX5E_PARAMS_NUM (0 MLX5E_PARAMS(MLX5E_STATS_COUNT)) 419 420struct mlx5e_params_ethtool { 421 u64 arg [0]; 422 MLX5E_PARAMS(MLX5E_STATS_VAR) 423}; 424 425/* EEPROM Standards for plug in modules */ 426#ifndef MLX5E_ETH_MODULE_SFF_8472 427#define MLX5E_ETH_MODULE_SFF_8472 0x1 428#define MLX5E_ETH_MODULE_SFF_8472_LEN 128 429#endif 430 431#ifndef MLX5E_ETH_MODULE_SFF_8636 432#define MLX5E_ETH_MODULE_SFF_8636 0x2 433#define MLX5E_ETH_MODULE_SFF_8636_LEN 256 434#endif 435 436#ifndef MLX5E_ETH_MODULE_SFF_8436 437#define MLX5E_ETH_MODULE_SFF_8436 0x3 438#define MLX5E_ETH_MODULE_SFF_8436_LEN 256 439#endif 440 441/* EEPROM I2C Addresses */ 442#define MLX5E_I2C_ADDR_LOW 0x50 443#define MLX5E_I2C_ADDR_HIGH 0x51 444 445#define MLX5E_EEPROM_LOW_PAGE 0x0 446#define MLX5E_EEPROM_HIGH_PAGE 0x3 447 448#define MLX5E_EEPROM_HIGH_PAGE_OFFSET 128 449#define MLX5E_EEPROM_PAGE_LENGTH 256 450 451#define MLX5E_EEPROM_INFO_BYTES 0x3 452 453struct mlx5e_cq { 454 /* data path - accessed per cqe */ 455 struct mlx5_cqwq wq; 456 457 /* data path - accessed per HW polling */ 458 struct mlx5_core_cq mcq; 459 460 /* control */ 461 struct mlx5e_priv *priv; 462 struct mlx5_wq_ctrl wq_ctrl; 463} __aligned(MLX5E_CACHELINE_SIZE); 464 465struct mlx5e_rq_mbuf { 466 bus_dmamap_t dma_map; 467 caddr_t data; 468 struct mbuf *mbuf; 469}; 470 471struct mlx5e_rq { 472 /* data path */ 473 struct mlx5_wq_ll wq; 474 struct mtx mtx; 475 bus_dma_tag_t dma_tag; 476 u32 wqe_sz; 477 struct mlx5e_rq_mbuf *mbuf; 478 struct ifnet *ifp; 479 struct mlx5e_rq_stats stats; 480 struct mlx5e_cq cq; 481 struct lro_ctrl lro; 482 volatile int enabled; 483 int ix; 484 485 /* control */ 486 struct mlx5_wq_ctrl wq_ctrl; 487 u32 rqn; 488 struct mlx5e_channel *channel; 489 struct callout watchdog; 490} __aligned(MLX5E_CACHELINE_SIZE); 491 492struct mlx5e_sq_mbuf { 493 bus_dmamap_t dma_map; 494 struct mbuf *mbuf; 495 u32 num_bytes; 496 u32 num_wqebbs; 497}; 498 499enum { 500 MLX5E_SQ_READY, 501 MLX5E_SQ_FULL 502}; 503 504struct mlx5e_sq { 505 /* data path */ 506 struct mtx lock; 507 bus_dma_tag_t dma_tag; 508 struct mtx comp_lock; 509 510 /* dirtied @completion */ 511 u16 cc; 512 513 /* dirtied @xmit */ 514 u16 pc __aligned(MLX5E_CACHELINE_SIZE); 515 u16 bf_offset; 516 u16 cev_counter; /* completion event counter */ 517 u16 cev_factor; /* completion event factor */ 518 u16 cev_next_state; /* next completion event state */ 519#define MLX5E_CEV_STATE_INITIAL 0 /* timer not started */ 520#define MLX5E_CEV_STATE_SEND_NOPS 1 /* send NOPs */ 521#define MLX5E_CEV_STATE_HOLD_NOPS 2 /* don't send NOPs yet */ 522 u16 stopped; /* set if SQ is stopped */ 523 struct callout cev_callout; 524 union { 525 u32 d32[2]; 526 u64 d64; 527 } doorbell; 528 struct mlx5e_sq_stats stats; 529 530 struct mlx5e_cq cq; 531 struct task sq_task; 532 struct taskqueue *sq_tq; 533 534 /* pointers to per packet info: write@xmit, read@completion */ 535 struct mlx5e_sq_mbuf *mbuf; 536 struct buf_ring *br; 537 538 /* read only */ 539 struct mlx5_wq_cyc wq; 540 struct mlx5_uar uar; 541 struct ifnet *ifp; 542 u32 sqn; 543 u32 bf_buf_size; 544 u32 mkey_be; 545 546 /* control path */ 547 struct mlx5_wq_ctrl wq_ctrl; 548 struct mlx5e_priv *priv; 549 int tc; 550 unsigned int queue_state; 551} __aligned(MLX5E_CACHELINE_SIZE); 552 553static inline bool 554mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) 555{ 556 u16 cc = sq->cc; 557 u16 pc = sq->pc; 558 559 return ((sq->wq.sz_m1 & (cc - pc)) >= n || cc == pc); 560} 561 562struct mlx5e_channel { 563 /* data path */ 564 struct mlx5e_rq rq; 565 struct mlx5e_sq sq[MLX5E_MAX_TX_NUM_TC]; 566 struct ifnet *ifp; 567 u32 mkey_be; 568 u8 num_tc; 569 570 /* control */ 571 struct mlx5e_priv *priv; 572 int ix; 573 int cpu; 574} __aligned(MLX5E_CACHELINE_SIZE); 575 576enum mlx5e_traffic_types { 577 MLX5E_TT_IPV4_TCP, 578 MLX5E_TT_IPV6_TCP, 579 MLX5E_TT_IPV4_UDP, 580 MLX5E_TT_IPV6_UDP, 581 MLX5E_TT_IPV4_IPSEC_AH, 582 MLX5E_TT_IPV6_IPSEC_AH, 583 MLX5E_TT_IPV4_IPSEC_ESP, 584 MLX5E_TT_IPV6_IPSEC_ESP, 585 MLX5E_TT_IPV4, 586 MLX5E_TT_IPV6, 587 MLX5E_TT_ANY, 588 MLX5E_NUM_TT, 589}; 590 591enum { 592 MLX5E_RQT_SPREADING = 0, 593 MLX5E_RQT_DEFAULT_RQ = 1, 594 MLX5E_NUM_RQT = 2, 595}; 596 597struct mlx5_flow_rule; 598 599struct mlx5e_eth_addr_info { 600 u8 addr [ETH_ALEN + 2]; 601 u32 tt_vec; 602 /* flow table rule per traffic type */ 603 struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT]; 604}; 605 606#define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE) 607 608struct mlx5e_eth_addr_hash_node; 609 610struct mlx5e_eth_addr_hash_head { 611 struct mlx5e_eth_addr_hash_node *lh_first; 612}; 613 614struct mlx5e_eth_addr_db { 615 struct mlx5e_eth_addr_hash_head if_uc[MLX5E_ETH_ADDR_HASH_SIZE]; 616 struct mlx5e_eth_addr_hash_head if_mc[MLX5E_ETH_ADDR_HASH_SIZE]; 617 struct mlx5e_eth_addr_info broadcast; 618 struct mlx5e_eth_addr_info allmulti; 619 struct mlx5e_eth_addr_info promisc; 620 bool broadcast_enabled; 621 bool allmulti_enabled; 622 bool promisc_enabled; 623}; 624 625enum { 626 MLX5E_STATE_ASYNC_EVENTS_ENABLE, 627 MLX5E_STATE_OPENED, 628}; 629 630struct mlx5e_vlan_db { 631 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 632 struct mlx5_flow_rule *active_vlans_ft_rule[VLAN_N_VID]; 633 struct mlx5_flow_rule *untagged_ft_rule; 634 struct mlx5_flow_rule *any_cvlan_ft_rule; 635 struct mlx5_flow_rule *any_svlan_ft_rule; 636 bool filter_disabled; 637}; 638 639struct mlx5e_flow_table { 640 int num_groups; 641 struct mlx5_flow_table *t; 642 struct mlx5_flow_group **g; 643}; 644 645struct mlx5e_flow_tables { 646 struct mlx5_flow_namespace *ns; 647 struct mlx5e_flow_table vlan; 648 struct mlx5e_flow_table main; 649 struct mlx5e_flow_table inner_rss; 650}; 651 652struct mlx5e_priv { 653 struct mlx5_core_dev *mdev; /* must be first */ 654 655 /* priv data path fields - start */ 656 int order_base_2_num_channels; 657 int queue_mapping_channel_mask; 658 int num_tc; 659 int default_vlan_prio; 660 /* priv data path fields - end */ 661 662 unsigned long state; 663 int gone; 664#define PRIV_LOCK(priv) sx_xlock(&(priv)->state_lock) 665#define PRIV_UNLOCK(priv) sx_xunlock(&(priv)->state_lock) 666#define PRIV_LOCKED(priv) sx_xlocked(&(priv)->state_lock) 667 struct sx state_lock; /* Protects Interface state */ 668 struct mlx5_uar cq_uar; 669 u32 pdn; 670 u32 tdn; 671 struct mlx5_core_mr mr; 672 673 struct mlx5e_channel *volatile *channel; 674 u32 tisn[MLX5E_MAX_TX_NUM_TC]; 675 u32 rqtn; 676 u32 tirn[MLX5E_NUM_TT]; 677 678 struct mlx5e_flow_tables fts; 679 struct mlx5e_eth_addr_db eth_addr; 680 struct mlx5e_vlan_db vlan; 681 682 struct mlx5e_params params; 683 struct mlx5e_params_ethtool params_ethtool; 684 union mlx5_core_pci_diagnostics params_pci; 685 union mlx5_core_general_diagnostics params_general; 686 struct mtx async_events_mtx; /* sync hw events */ 687 struct work_struct update_stats_work; 688 struct work_struct update_carrier_work; 689 struct work_struct set_rx_mode_work; 690 MLX5_DECLARE_DOORBELL_LOCK(doorbell_lock) 691 692 struct ifnet *ifp; 693 struct sysctl_ctx_list sysctl_ctx; 694 struct sysctl_oid *sysctl_ifnet; 695 struct sysctl_oid *sysctl_hw; 696 int sysctl_debug; 697 struct mlx5e_stats stats; 698 int counter_set_id; 699 700 eventhandler_tag vlan_detach; 701 eventhandler_tag vlan_attach; 702 struct ifmedia media; 703 int media_status_last; 704 int media_active_last; 705 706 struct callout watchdog; 707}; 708 709#define MLX5E_NET_IP_ALIGN 2 710 711struct mlx5e_tx_wqe { 712 struct mlx5_wqe_ctrl_seg ctrl; 713 struct mlx5_wqe_eth_seg eth; 714}; 715 716struct mlx5e_rx_wqe { 717 struct mlx5_wqe_srq_next_seg next; 718 struct mlx5_wqe_data_seg data; 719}; 720 721struct mlx5e_eeprom { 722 int lock_bit; 723 int i2c_addr; 724 int page_num; 725 int device_addr; 726 int module_num; 727 int len; 728 int type; 729 int page_valid; 730 u32 *data; 731}; 732 733enum mlx5e_link_mode { 734 MLX5E_1000BASE_CX_SGMII = 0, 735 MLX5E_1000BASE_KX = 1, 736 MLX5E_10GBASE_CX4 = 2, 737 MLX5E_10GBASE_KX4 = 3, 738 MLX5E_10GBASE_KR = 4, 739 MLX5E_20GBASE_KR2 = 5, 740 MLX5E_40GBASE_CR4 = 6, 741 MLX5E_40GBASE_KR4 = 7, 742 MLX5E_56GBASE_R4 = 8, 743 MLX5E_10GBASE_CR = 12, 744 MLX5E_10GBASE_SR = 13, 745 MLX5E_10GBASE_LR = 14, 746 MLX5E_40GBASE_SR4 = 15, 747 MLX5E_40GBASE_LR4 = 16, 748 MLX5E_100GBASE_CR4 = 20, 749 MLX5E_100GBASE_SR4 = 21, 750 MLX5E_100GBASE_KR4 = 22, 751 MLX5E_100GBASE_LR4 = 23, 752 MLX5E_100BASE_TX = 24, 753 MLX5E_100BASE_T = 25, 754 MLX5E_10GBASE_T = 26, 755 MLX5E_25GBASE_CR = 27, 756 MLX5E_25GBASE_KR = 28, 757 MLX5E_25GBASE_SR = 29, 758 MLX5E_50GBASE_CR2 = 30, 759 MLX5E_50GBASE_KR2 = 31, 760 MLX5E_LINK_MODES_NUMBER, 761}; 762 763#define MLX5E_PROT_MASK(link_mode) (1 << (link_mode)) 764#define MLX5E_FLD_MAX(typ, fld) ((1ULL << __mlx5_bit_sz(typ, fld)) - 1ULL) 765 766int mlx5e_xmit(struct ifnet *, struct mbuf *); 767 768int mlx5e_open_locked(struct ifnet *); 769int mlx5e_close_locked(struct ifnet *); 770 771void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, int event); 772void mlx5e_rx_cq_comp(struct mlx5_core_cq *); 773void mlx5e_tx_cq_comp(struct mlx5_core_cq *); 774struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); 775void mlx5e_tx_que(void *context, int pending); 776 777int mlx5e_open_flow_table(struct mlx5e_priv *priv); 778void mlx5e_close_flow_table(struct mlx5e_priv *priv); 779void mlx5e_set_rx_mode_core(struct mlx5e_priv *priv); 780void mlx5e_set_rx_mode_work(struct work_struct *work); 781 782void mlx5e_vlan_rx_add_vid(void *, struct ifnet *, u16); 783void mlx5e_vlan_rx_kill_vid(void *, struct ifnet *, u16); 784void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); 785void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); 786int mlx5e_add_all_vlan_rules(struct mlx5e_priv *priv); 787void mlx5e_del_all_vlan_rules(struct mlx5e_priv *priv); 788 789static inline void 790mlx5e_tx_notify_hw(struct mlx5e_sq *sq, u32 *wqe, int bf_sz) 791{ 792 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; 793 794 /* ensure wqe is visible to device before updating doorbell record */ 795 wmb(); 796 797 *sq->wq.db = cpu_to_be32(sq->pc); 798 799 /* 800 * Ensure the doorbell record is visible to device before ringing 801 * the doorbell: 802 */ 803 wmb(); 804 805 if (bf_sz) { 806 __iowrite64_copy(sq->uar.bf_map + ofst, wqe, bf_sz); 807 808 /* flush the write-combining mapped buffer */ 809 wmb(); 810 811 } else { 812 mlx5_write64(wqe, sq->uar.map + ofst, 813 MLX5_GET_DOORBELL_LOCK(&sq->priv->doorbell_lock)); 814 } 815 816 sq->bf_offset ^= sq->bf_buf_size; 817} 818 819static inline void 820mlx5e_cq_arm(struct mlx5e_cq *cq, spinlock_t *dblock) 821{ 822 struct mlx5_core_cq *mcq; 823 824 mcq = &cq->mcq; 825 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, dblock, cq->wq.cc); 826} 827 828extern const struct ethtool_ops mlx5e_ethtool_ops; 829void mlx5e_create_ethtool(struct mlx5e_priv *); 830void mlx5e_create_stats(struct sysctl_ctx_list *, 831 struct sysctl_oid_list *, const char *, 832 const char **, unsigned, u64 *); 833void mlx5e_send_nop(struct mlx5e_sq *, u32); 834void mlx5e_sq_cev_timeout(void *); 835int mlx5e_refresh_channel_params(struct mlx5e_priv *); 836int mlx5e_open_cq(struct mlx5e_priv *, struct mlx5e_cq_param *, 837 struct mlx5e_cq *, mlx5e_cq_comp_t *, int eq_ix); 838void mlx5e_close_cq(struct mlx5e_cq *); 839void mlx5e_free_sq_db(struct mlx5e_sq *); 840int mlx5e_alloc_sq_db(struct mlx5e_sq *); 841int mlx5e_enable_sq(struct mlx5e_sq *, struct mlx5e_sq_param *, int tis_num); 842int mlx5e_modify_sq(struct mlx5e_sq *, int curr_state, int next_state); 843void mlx5e_disable_sq(struct mlx5e_sq *); 844void mlx5e_drain_sq(struct mlx5e_sq *); 845void mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value); 846void mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value); 847void mlx5e_resume_sq(struct mlx5e_sq *sq); 848 849#endif /* _MLX5_EN_H_ */ 850