1290650Shselasky/*- 2347864Shselasky * Copyright (c) 2015-2019 Mellanox Technologies. All rights reserved. 3290650Shselasky * 4290650Shselasky * Redistribution and use in source and binary forms, with or without 5290650Shselasky * modification, are permitted provided that the following conditions 6290650Shselasky * are met: 7290650Shselasky * 1. Redistributions of source code must retain the above copyright 8290650Shselasky * notice, this list of conditions and the following disclaimer. 9290650Shselasky * 2. Redistributions in binary form must reproduce the above copyright 10290650Shselasky * notice, this list of conditions and the following disclaimer in the 11290650Shselasky * documentation and/or other materials provided with the distribution. 12290650Shselasky * 13290650Shselasky * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14290650Shselasky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15290650Shselasky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16290650Shselasky * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17290650Shselasky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18290650Shselasky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19290650Shselasky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20290650Shselasky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21290650Shselasky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22290650Shselasky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23290650Shselasky * SUCH DAMAGE. 24290650Shselasky * 25290650Shselasky * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_en/en.h 369088 2021-01-22 12:49:25Z git2svn $ 26290650Shselasky */ 27290650Shselasky 28290650Shselasky#ifndef _MLX5_EN_H_ 29290650Shselasky#define _MLX5_EN_H_ 30290650Shselasky 31290650Shselasky#include <linux/kmod.h> 32290650Shselasky#include <linux/page.h> 33290650Shselasky#include <linux/slab.h> 34290650Shselasky#include <linux/if_vlan.h> 35290650Shselasky#include <linux/if_ether.h> 36290650Shselasky#include <linux/vmalloc.h> 37290650Shselasky#include <linux/moduleparam.h> 38290650Shselasky#include <linux/delay.h> 39290650Shselasky#include <linux/netdevice.h> 40290650Shselasky#include <linux/etherdevice.h> 41347796Shselasky#include <linux/ktime.h> 42347796Shselasky#include <linux/net_dim.h> 43290650Shselasky 44290650Shselasky#include <netinet/in_systm.h> 45290650Shselasky#include <netinet/in.h> 46290650Shselasky#include <netinet/if_ether.h> 47290650Shselasky#include <netinet/ip.h> 48290650Shselasky#include <netinet/ip6.h> 49290650Shselasky#include <netinet/tcp.h> 50290650Shselasky#include <netinet/tcp_lro.h> 51290650Shselasky#include <netinet/udp.h> 52290650Shselasky#include <net/ethernet.h> 53290650Shselasky#include <sys/buf_ring.h> 54290650Shselasky 55291938Shselasky#include "opt_rss.h" 56291938Shselasky 57291938Shselasky#ifdef RSS 58291938Shselasky#include <net/rss_config.h> 59291938Shselasky#include <netinet/in_rss.h> 60291938Shselasky#endif 61291938Shselasky 62290650Shselasky#include <machine/bus.h> 63290650Shselasky 64290650Shselasky#include <dev/mlx5/driver.h> 65290650Shselasky#include <dev/mlx5/qp.h> 66290650Shselasky#include <dev/mlx5/cq.h> 67331576Shselasky#include <dev/mlx5/port.h> 68290650Shselasky#include <dev/mlx5/vport.h> 69322006Shselasky#include <dev/mlx5/diagnostics.h> 70290650Shselasky 71290650Shselasky#include <dev/mlx5/mlx5_core/wq.h> 72290650Shselasky#include <dev/mlx5/mlx5_core/transobj.h> 73290650Shselasky#include <dev/mlx5/mlx5_core/mlx5_core.h> 74290650Shselasky 75347810Shselasky#define MLX5E_MAX_PRIORITY 8 76347810Shselasky 77353244Shselasky#define MLX5E_MAX_FEC_10X_25X 4 78353244Shselasky#define MLX5E_MAX_FEC_50X 4 79353244Shselasky 80347810Shselasky/* IEEE 802.1Qaz standard supported values */ 81331577Shselasky#define IEEE_8021QAZ_MAX_TCS 8 82331577Shselasky 83290650Shselasky#define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x7 84290650Shselasky#define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa 85304996Shselasky#define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xe 86290650Shselasky 87290650Shselasky#define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x7 88290650Shselasky#define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa 89304996Shselasky#define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xe 90290650Shselasky 91347872Shselasky#define MLX5E_MAX_BUSDMA_RX_SEGS 15 92347872Shselasky 93337110Shselasky#ifndef MLX5E_MAX_RX_BYTES 94337110Shselasky#define MLX5E_MAX_RX_BYTES MCLBYTES 95337110Shselasky#endif 96337110Shselasky 97337110Shselasky#define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ \ 98347873Shselasky MIN(65535, 7 * MLX5E_MAX_RX_BYTES) 99347873Shselasky 100347796Shselasky#define MLX5E_DIM_DEFAULT_PROFILE 3 101347796Shselasky#define MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO 16 102290650Shselasky#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 103291070Shselasky#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 104290650Shselasky#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 105290650Shselasky#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 106290650Shselasky#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 107290650Shselasky#define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 108290650Shselasky#define MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ 0x7 109290650Shselasky#define MLX5E_CACHELINE_SIZE CACHE_LINE_SIZE 110290650Shselasky#define MLX5E_HW2SW_MTU(hwmtu) \ 111290650Shselasky ((hwmtu) - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 112290650Shselasky#define MLX5E_SW2HW_MTU(swmtu) \ 113290650Shselasky ((swmtu) + (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 114290650Shselasky#define MLX5E_SW2MB_MTU(swmtu) \ 115290650Shselasky (MLX5E_SW2HW_MTU(swmtu) + MLX5E_NET_IP_ALIGN) 116291070Shselasky#define MLX5E_MTU_MIN 72 /* Min MTU allowed by the kernel */ 117291070Shselasky#define MLX5E_MTU_MAX MIN(ETHERMTU_JUMBO, MJUM16BYTES) /* Max MTU of Ethernet 118291070Shselasky * jumbo frames */ 119290650Shselasky 120290650Shselasky#define MLX5E_BUDGET_MAX 8192 /* RX and TX */ 121290650Shselasky#define MLX5E_RX_BUDGET_MAX 256 122290650Shselasky#define MLX5E_SQ_BF_BUDGET 16 123291070Shselasky#define MLX5E_SQ_TX_QUEUE_SIZE 4096 /* SQ drbr queue size */ 124290650Shselasky 125290650Shselasky#define MLX5E_MAX_TX_NUM_TC 8 /* units */ 126290650Shselasky#define MLX5E_MAX_TX_HEADER 128 /* bytes */ 127290650Shselasky#define MLX5E_MAX_TX_PAYLOAD_SIZE 65536 /* bytes */ 128290650Shselasky#define MLX5E_MAX_TX_MBUF_SIZE 65536 /* bytes */ 129290650Shselasky#define MLX5E_MAX_TX_MBUF_FRAGS \ 130290650Shselasky ((MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS) - \ 131338548Shselasky (MLX5E_MAX_TX_HEADER / MLX5_SEND_WQE_DS) - \ 132338548Shselasky 1 /* the maximum value of the DS counter is 0x3F and not 0x40 */) /* units */ 133290650Shselasky#define MLX5E_MAX_TX_INLINE \ 134290650Shselasky (MLX5E_MAX_TX_HEADER - sizeof(struct mlx5e_tx_wqe) + \ 135290650Shselasky sizeof(((struct mlx5e_tx_wqe *)0)->eth.inline_hdr_start)) /* bytes */ 136290650Shselasky 137331577Shselasky#define MLX5E_100MB (100000) 138331577Shselasky#define MLX5E_1GB (1000000) 139331577Shselasky 140353252Shselasky#define MLX5E_ZERO(ptr, field) \ 141353252Shselasky memset(&(ptr)->field, 0, \ 142353252Shselasky sizeof(*(ptr)) - __offsetof(__typeof(*(ptr)), field)) 143353252Shselasky 144290650ShselaskyMALLOC_DECLARE(M_MLX5EN); 145290650Shselasky 146290650Shselaskystruct mlx5_core_dev; 147290650Shselaskystruct mlx5e_cq; 148290650Shselasky 149290650Shselaskytypedef void (mlx5e_cq_comp_t)(struct mlx5_core_cq *); 150290650Shselasky 151353226Shselasky#define mlx5_en_err(_dev, format, ...) \ 152353226Shselasky if_printf(_dev, "ERR: ""%s:%d:(pid %d): " format, \ 153353226Shselasky __func__, __LINE__, curthread->td_proc->p_pid, \ 154353226Shselasky ##__VA_ARGS__) 155353226Shselasky 156353226Shselasky#define mlx5_en_warn(_dev, format, ...) \ 157353226Shselasky if_printf(_dev, "WARN: ""%s:%d:(pid %d): " format, \ 158353226Shselasky __func__, __LINE__, curthread->td_proc->p_pid, \ 159353226Shselasky ##__VA_ARGS__) 160353226Shselasky 161353226Shselasky#define mlx5_en_info(_dev, format, ...) \ 162353226Shselasky if_printf(_dev, "INFO: ""%s:%d:(pid %d): " format, \ 163353226Shselasky __func__, __LINE__, curthread->td_proc->p_pid, \ 164353226Shselasky ##__VA_ARGS__) 165353226Shselasky 166347864Shselasky#define MLX5E_STATS_COUNT(a, ...) a 167347864Shselasky#define MLX5E_STATS_VAR(a, b, c, ...) b c; 168347864Shselasky#define MLX5E_STATS_DESC(a, b, c, d, e, ...) d, e, 169290650Shselasky 170290650Shselasky#define MLX5E_VPORT_STATS(m) \ 171290650Shselasky /* HW counters */ \ 172347864Shselasky m(+1, u64, rx_packets, "rx_packets", "Received packets") \ 173347864Shselasky m(+1, u64, rx_bytes, "rx_bytes", "Received bytes") \ 174347864Shselasky m(+1, u64, tx_packets, "tx_packets", "Transmitted packets") \ 175347864Shselasky m(+1, u64, tx_bytes, "tx_bytes", "Transmitted bytes") \ 176347864Shselasky m(+1, u64, rx_error_packets, "rx_error_packets", "Received error packets") \ 177347864Shselasky m(+1, u64, rx_error_bytes, "rx_error_bytes", "Received error bytes") \ 178347864Shselasky m(+1, u64, tx_error_packets, "tx_error_packets", "Transmitted error packets") \ 179347864Shselasky m(+1, u64, tx_error_bytes, "tx_error_bytes", "Transmitted error bytes") \ 180347864Shselasky m(+1, u64, rx_unicast_packets, "rx_unicast_packets", "Received unicast packets") \ 181347864Shselasky m(+1, u64, rx_unicast_bytes, "rx_unicast_bytes", "Received unicast bytes") \ 182347864Shselasky m(+1, u64, tx_unicast_packets, "tx_unicast_packets", "Transmitted unicast packets") \ 183347864Shselasky m(+1, u64, tx_unicast_bytes, "tx_unicast_bytes", "Transmitted unicast bytes") \ 184347864Shselasky m(+1, u64, rx_multicast_packets, "rx_multicast_packets", "Received multicast packets") \ 185347864Shselasky m(+1, u64, rx_multicast_bytes, "rx_multicast_bytes", "Received multicast bytes") \ 186347864Shselasky m(+1, u64, tx_multicast_packets, "tx_multicast_packets", "Transmitted multicast packets") \ 187347864Shselasky m(+1, u64, tx_multicast_bytes, "tx_multicast_bytes", "Transmitted multicast bytes") \ 188347864Shselasky m(+1, u64, rx_broadcast_packets, "rx_broadcast_packets", "Received broadcast packets") \ 189347864Shselasky m(+1, u64, rx_broadcast_bytes, "rx_broadcast_bytes", "Received broadcast bytes") \ 190347864Shselasky m(+1, u64, tx_broadcast_packets, "tx_broadcast_packets", "Transmitted broadcast packets") \ 191347864Shselasky m(+1, u64, tx_broadcast_bytes, "tx_broadcast_bytes", "Transmitted broadcast bytes") \ 192347864Shselasky m(+1, u64, rx_out_of_buffer, "rx_out_of_buffer", "Receive out of buffer, no recv wqes events") \ 193290650Shselasky /* SW counters */ \ 194347864Shselasky m(+1, u64, tso_packets, "tso_packets", "Transmitted TSO packets") \ 195347864Shselasky m(+1, u64, tso_bytes, "tso_bytes", "Transmitted TSO bytes") \ 196347864Shselasky m(+1, u64, lro_packets, "lro_packets", "Received LRO packets") \ 197347864Shselasky m(+1, u64, lro_bytes, "lro_bytes", "Received LRO bytes") \ 198347864Shselasky m(+1, u64, sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 199347864Shselasky m(+1, u64, sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 200347864Shselasky m(+1, u64, rx_csum_good, "rx_csum_good", "Received checksum valid packets") \ 201347864Shselasky m(+1, u64, rx_csum_none, "rx_csum_none", "Received no checksum packets") \ 202347864Shselasky m(+1, u64, tx_csum_offload, "tx_csum_offload", "Transmit checksum offload packets") \ 203347864Shselasky m(+1, u64, tx_queue_dropped, "tx_queue_dropped", "Transmit queue dropped") \ 204347864Shselasky m(+1, u64, tx_defragged, "tx_defragged", "Transmit queue defragged") \ 205347864Shselasky m(+1, u64, rx_wqe_err, "rx_wqe_err", "Receive WQE errors") \ 206347864Shselasky m(+1, u64, tx_jumbo_packets, "tx_jumbo_packets", "TX packets greater than 1518 octets") \ 207347864Shselasky m(+1, u64, rx_steer_missed_packets, "rx_steer_missed_packets", "RX packets dropped by steering rule(s)") 208290650Shselasky 209290650Shselasky#define MLX5E_VPORT_STATS_NUM (0 MLX5E_VPORT_STATS(MLX5E_STATS_COUNT)) 210290650Shselasky 211290650Shselaskystruct mlx5e_vport_stats { 212291070Shselasky struct sysctl_ctx_list ctx; 213290650Shselasky u64 arg [0]; 214290650Shselasky MLX5E_VPORT_STATS(MLX5E_STATS_VAR) 215290650Shselasky}; 216290650Shselasky 217290650Shselasky#define MLX5E_PPORT_IEEE802_3_STATS(m) \ 218347864Shselasky m(+1, u64, frames_tx, "frames_tx", "Frames transmitted") \ 219347864Shselasky m(+1, u64, frames_rx, "frames_rx", "Frames received") \ 220347864Shselasky m(+1, u64, check_seq_err, "check_seq_err", "Sequence errors") \ 221347864Shselasky m(+1, u64, alignment_err, "alignment_err", "Alignment errors") \ 222347864Shselasky m(+1, u64, octets_tx, "octets_tx", "Bytes transmitted") \ 223347864Shselasky m(+1, u64, octets_received, "octets_received", "Bytes received") \ 224347864Shselasky m(+1, u64, multicast_xmitted, "multicast_xmitted", "Multicast transmitted") \ 225347864Shselasky m(+1, u64, broadcast_xmitted, "broadcast_xmitted", "Broadcast transmitted") \ 226347864Shselasky m(+1, u64, multicast_rx, "multicast_rx", "Multicast received") \ 227347864Shselasky m(+1, u64, broadcast_rx, "broadcast_rx", "Broadcast received") \ 228347864Shselasky m(+1, u64, in_range_len_errors, "in_range_len_errors", "In range length errors") \ 229347864Shselasky m(+1, u64, out_of_range_len, "out_of_range_len", "Out of range length errors") \ 230347864Shselasky m(+1, u64, too_long_errors, "too_long_errors", "Too long errors") \ 231347864Shselasky m(+1, u64, symbol_err, "symbol_err", "Symbol errors") \ 232347864Shselasky m(+1, u64, mac_control_tx, "mac_control_tx", "MAC control transmitted") \ 233347864Shselasky m(+1, u64, mac_control_rx, "mac_control_rx", "MAC control received") \ 234347864Shselasky m(+1, u64, unsupported_op_rx, "unsupported_op_rx", "Unsupported operation received") \ 235347864Shselasky m(+1, u64, pause_ctrl_rx, "pause_ctrl_rx", "Pause control received") \ 236347864Shselasky m(+1, u64, pause_ctrl_tx, "pause_ctrl_tx", "Pause control transmitted") 237290650Shselasky 238290650Shselasky#define MLX5E_PPORT_RFC2819_STATS(m) \ 239347864Shselasky m(+1, u64, drop_events, "drop_events", "Dropped events") \ 240347864Shselasky m(+1, u64, octets, "octets", "Octets") \ 241347864Shselasky m(+1, u64, pkts, "pkts", "Packets") \ 242347864Shselasky m(+1, u64, broadcast_pkts, "broadcast_pkts", "Broadcast packets") \ 243347864Shselasky m(+1, u64, multicast_pkts, "multicast_pkts", "Multicast packets") \ 244347864Shselasky m(+1, u64, crc_align_errors, "crc_align_errors", "CRC alignment errors") \ 245347864Shselasky m(+1, u64, undersize_pkts, "undersize_pkts", "Undersized packets") \ 246347864Shselasky m(+1, u64, oversize_pkts, "oversize_pkts", "Oversized packets") \ 247347864Shselasky m(+1, u64, fragments, "fragments", "Fragments") \ 248347864Shselasky m(+1, u64, jabbers, "jabbers", "Jabbers") \ 249347864Shselasky m(+1, u64, collisions, "collisions", "Collisions") 250290650Shselasky 251290650Shselasky#define MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 252347864Shselasky m(+1, u64, p64octets, "p64octets", "Bytes") \ 253347864Shselasky m(+1, u64, p65to127octets, "p65to127octets", "Bytes") \ 254347864Shselasky m(+1, u64, p128to255octets, "p128to255octets", "Bytes") \ 255347864Shselasky m(+1, u64, p256to511octets, "p256to511octets", "Bytes") \ 256347864Shselasky m(+1, u64, p512to1023octets, "p512to1023octets", "Bytes") \ 257347864Shselasky m(+1, u64, p1024to1518octets, "p1024to1518octets", "Bytes") \ 258347864Shselasky m(+1, u64, p1519to2047octets, "p1519to2047octets", "Bytes") \ 259347864Shselasky m(+1, u64, p2048to4095octets, "p2048to4095octets", "Bytes") \ 260347864Shselasky m(+1, u64, p4096to8191octets, "p4096to8191octets", "Bytes") \ 261347864Shselasky m(+1, u64, p8192to10239octets, "p8192to10239octets", "Bytes") 262290650Shselasky 263290650Shselasky#define MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 264347864Shselasky m(+1, u64, in_octets, "in_octets", "In octets") \ 265347864Shselasky m(+1, u64, in_ucast_pkts, "in_ucast_pkts", "In unicast packets") \ 266347864Shselasky m(+1, u64, in_discards, "in_discards", "In discards") \ 267347864Shselasky m(+1, u64, in_errors, "in_errors", "In errors") \ 268347864Shselasky m(+1, u64, in_unknown_protos, "in_unknown_protos", "In unknown protocols") \ 269347864Shselasky m(+1, u64, out_octets, "out_octets", "Out octets") \ 270347864Shselasky m(+1, u64, out_ucast_pkts, "out_ucast_pkts", "Out unicast packets") \ 271347864Shselasky m(+1, u64, out_discards, "out_discards", "Out discards") \ 272347864Shselasky m(+1, u64, out_errors, "out_errors", "Out errors") \ 273347864Shselasky m(+1, u64, in_multicast_pkts, "in_multicast_pkts", "In multicast packets") \ 274347864Shselasky m(+1, u64, in_broadcast_pkts, "in_broadcast_pkts", "In broadcast packets") \ 275347864Shselasky m(+1, u64, out_multicast_pkts, "out_multicast_pkts", "Out multicast packets") \ 276347864Shselasky m(+1, u64, out_broadcast_pkts, "out_broadcast_pkts", "Out broadcast packets") 277290650Shselasky 278347804Shselasky#define MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(m) \ 279353204Shselasky m(+1, u64, port_transmit_wait, "port_transmit_wait", "Port transmit wait") \ 280347864Shselasky m(+1, u64, ecn_marked, "ecn_marked", "ECN marked") \ 281347864Shselasky m(+1, u64, no_buffer_discard_mc, "no_buffer_discard_mc", "No buffer discard mc") \ 282347864Shselasky m(+1, u64, rx_ebp, "rx_ebp", "RX EBP") \ 283347864Shselasky m(+1, u64, tx_ebp, "tx_ebp", "TX EBP") \ 284347864Shselasky m(+1, u64, rx_buffer_almost_full, "rx_buffer_almost_full", "RX buffer almost full") \ 285347864Shselasky m(+1, u64, rx_buffer_full, "rx_buffer_full", "RX buffer full") \ 286347864Shselasky m(+1, u64, rx_icrc_encapsulated, "rx_icrc_encapsulated", "RX ICRC encapsulated") \ 287347864Shselasky m(+1, u64, ex_reserved_0, "ex_reserved_0", "Reserved") \ 288347864Shselasky m(+1, u64, ex_reserved_1, "ex_reserved_1", "Reserved") \ 289347864Shselasky m(+1, u64, tx_stat_p64octets, "tx_stat_p64octets", "Bytes") \ 290347864Shselasky m(+1, u64, tx_stat_p65to127octets, "tx_stat_p65to127octets", "Bytes") \ 291347864Shselasky m(+1, u64, tx_stat_p128to255octets, "tx_stat_p128to255octets", "Bytes") \ 292347864Shselasky m(+1, u64, tx_stat_p256to511octets, "tx_stat_p256to511octets", "Bytes") \ 293347864Shselasky m(+1, u64, tx_stat_p512to1023octets, "tx_stat_p512to1023octets", "Bytes") \ 294347864Shselasky m(+1, u64, tx_stat_p1024to1518octets, "tx_stat_p1024to1518octets", "Bytes") \ 295347864Shselasky m(+1, u64, tx_stat_p1519to2047octets, "tx_stat_p1519to2047octets", "Bytes") \ 296347864Shselasky m(+1, u64, tx_stat_p2048to4095octets, "tx_stat_p2048to4095octets", "Bytes") \ 297347864Shselasky m(+1, u64, tx_stat_p4096to8191octets, "tx_stat_p4096to8191octets", "Bytes") \ 298347864Shselasky m(+1, u64, tx_stat_p8192to10239octets, "tx_stat_p8192to10239octets", "Bytes") 299347804Shselasky 300347866Shselasky#define MLX5E_PPORT_STATISTICAL_DEBUG(m) \ 301347866Shselasky m(+1, u64, phy_time_since_last_clear, "phy_time_since_last_clear", \ 302347866Shselasky "Time since last clear in milliseconds") \ 303347866Shselasky m(+1, u64, phy_received_bits, "phy_received_bits", \ 304347866Shselasky "Total amount of traffic received in bits before error correction") \ 305347866Shselasky m(+1, u64, phy_symbol_errors, "phy_symbol_errors", \ 306347866Shselasky "Total number of symbol errors before error correction") \ 307347866Shselasky m(+1, u64, phy_corrected_bits, "phy_corrected_bits", \ 308347866Shselasky "Total number of corrected bits ") \ 309347866Shselasky m(+1, u64, phy_corrected_bits_lane0, "phy_corrected_bits_lane0", \ 310347866Shselasky "Total number of corrected bits for lane 0") \ 311347866Shselasky m(+1, u64, phy_corrected_bits_lane1, "phy_corrected_bits_lane1", \ 312347866Shselasky "Total number of corrected bits for lane 1") \ 313347866Shselasky m(+1, u64, phy_corrected_bits_lane2, "phy_corrected_bits_lane2", \ 314347866Shselasky "Total number of corrected bits for lane 2") \ 315347866Shselasky m(+1, u64, phy_corrected_bits_lane3, "phy_corrected_bits_lane3", \ 316347866Shselasky "Total number of corrected bits for lane 3") 317347866Shselasky 318347864Shselasky#define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \ 319347864Shselasky m(+1, u64, time_since_last_clear, "time_since_last_clear", \ 320347864Shselasky "Time since the last counters clear event (msec)") \ 321347864Shselasky m(+1, u64, symbol_errors, "symbol_errors", "Symbol errors") \ 322347864Shselasky m(+1, u64, sync_headers_errors, "sync_headers_errors", \ 323347864Shselasky "Sync header error counter") \ 324347864Shselasky m(+1, u64, bip_errors_lane0, "edpl_bip_errors_lane0", \ 325347864Shselasky "Indicates the number of PRBS errors on lane 0") \ 326347864Shselasky m(+1, u64, bip_errors_lane1, "edpl_bip_errors_lane1", \ 327347864Shselasky "Indicates the number of PRBS errors on lane 1") \ 328347864Shselasky m(+1, u64, bip_errors_lane2, "edpl_bip_errors_lane2", \ 329347864Shselasky "Indicates the number of PRBS errors on lane 2") \ 330347864Shselasky m(+1, u64, bip_errors_lane3, "edpl_bip_errors_lane3", \ 331347864Shselasky "Indicates the number of PRBS errors on lane 3") \ 332347864Shselasky m(+1, u64, fc_corrected_blocks_lane0, "fc_corrected_blocks_lane0", \ 333347864Shselasky "FEC correctable block counter lane 0") \ 334347864Shselasky m(+1, u64, fc_corrected_blocks_lane1, "fc_corrected_blocks_lane1", \ 335347864Shselasky "FEC correctable block counter lane 1") \ 336347864Shselasky m(+1, u64, fc_corrected_blocks_lane2, "fc_corrected_blocks_lane2", \ 337347864Shselasky "FEC correctable block counter lane 2") \ 338347864Shselasky m(+1, u64, fc_corrected_blocks_lane3, "fc_corrected_blocks_lane3", \ 339347864Shselasky "FEC correctable block counter lane 3") \ 340347864Shselasky m(+1, u64, rs_corrected_blocks, "rs_corrected_blocks", \ 341347864Shselasky "FEC correcable block counter") \ 342347864Shselasky m(+1, u64, rs_uncorrectable_blocks, "rs_uncorrectable_blocks", \ 343347864Shselasky "FEC uncorrecable block counter") \ 344347864Shselasky m(+1, u64, rs_no_errors_blocks, "rs_no_errors_blocks", \ 345347864Shselasky "The number of RS-FEC blocks received that had no errors") \ 346347864Shselasky m(+1, u64, rs_single_error_blocks, "rs_single_error_blocks", \ 347347864Shselasky "The number of corrected RS-FEC blocks received that had" \ 348347864Shselasky "exactly 1 error symbol") \ 349347864Shselasky m(+1, u64, rs_corrected_symbols_total, "rs_corrected_symbols_total", \ 350347864Shselasky "Port FEC corrected symbol counter") \ 351347864Shselasky m(+1, u64, rs_corrected_symbols_lane0, "rs_corrected_symbols_lane0", \ 352347864Shselasky "FEC corrected symbol counter lane 0") \ 353347864Shselasky m(+1, u64, rs_corrected_symbols_lane1, "rs_corrected_symbols_lane1", \ 354347864Shselasky "FEC corrected symbol counter lane 1") \ 355347864Shselasky m(+1, u64, rs_corrected_symbols_lane2, "rs_corrected_symbols_lane2", \ 356347864Shselasky "FEC corrected symbol counter lane 2") \ 357347864Shselasky m(+1, u64, rs_corrected_symbols_lane3, "rs_corrected_symbols_lane3", \ 358347864Shselasky "FEC corrected symbol counter lane 3") 359290650Shselasky 360331583Shselasky/* Per priority statistics for PFC */ 361331583Shselasky#define MLX5E_PPORT_PER_PRIO_STATS_SUB(m,n,p) \ 362331583Shselasky m(n, p, +1, u64, rx_octets, "rx_octets", "Received octets") \ 363353204Shselasky m(n, p, +1, u64, rx_uc_frames, "rx_uc_frames", "Received unicast frames") \ 364353204Shselasky m(n, p, +1, u64, rx_mc_frames, "rx_mc_frames", "Received multicast frames") \ 365353204Shselasky m(n, p, +1, u64, rx_bc_frames, "rx_bc_frames", "Received broadcast frames") \ 366331583Shselasky m(n, p, +1, u64, rx_frames, "rx_frames", "Received frames") \ 367331583Shselasky m(n, p, +1, u64, tx_octets, "tx_octets", "Transmitted octets") \ 368353204Shselasky m(n, p, +1, u64, tx_uc_frames, "tx_uc_frames", "Transmitted unicast frames") \ 369353204Shselasky m(n, p, +1, u64, tx_mc_frames, "tx_mc_frames", "Transmitted multicast frames") \ 370353204Shselasky m(n, p, +1, u64, tx_bc_frames, "tx_bc_frames", "Transmitted broadcast frames") \ 371331583Shselasky m(n, p, +1, u64, tx_frames, "tx_frames", "Transmitted frames") \ 372331583Shselasky m(n, p, +1, u64, rx_pause, "rx_pause", "Received pause frames") \ 373331583Shselasky m(n, p, +1, u64, rx_pause_duration, "rx_pause_duration", \ 374331583Shselasky "Received pause duration") \ 375331583Shselasky m(n, p, +1, u64, tx_pause, "tx_pause", "Transmitted pause frames") \ 376331583Shselasky m(n, p, +1, u64, tx_pause_duration, "tx_pause_duration", \ 377331583Shselasky "Transmitted pause duration") \ 378331583Shselasky m(n, p, +1, u64, rx_pause_transition, "rx_pause_transition", \ 379331583Shselasky "Received pause transitions") \ 380331583Shselasky m(n, p, +1, u64, rx_discards, "rx_discards", "Discarded received frames") \ 381331583Shselasky m(n, p, +1, u64, device_stall_minor_watermark, \ 382331583Shselasky "device_stall_minor_watermark", "Device stall minor watermark") \ 383331583Shselasky m(n, p, +1, u64, device_stall_critical_watermark, \ 384331583Shselasky "device_stall_critical_watermark", "Device stall critical watermark") 385331583Shselasky 386331583Shselasky#define MLX5E_PPORT_PER_PRIO_STATS_PREFIX(m,p,c,t,f,s,d) \ 387347864Shselasky m(c, t, pri_##p##_##f, "prio" #p "_" s, "Priority " #p " - " d) 388331583Shselasky 389331583Shselasky#define MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO 8 390331583Shselasky 391331583Shselasky#define MLX5E_PPORT_PER_PRIO_STATS(m) \ 392331583Shselasky MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,0) \ 393331583Shselasky MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,1) \ 394331583Shselasky MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,2) \ 395331583Shselasky MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,3) \ 396331583Shselasky MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,4) \ 397331583Shselasky MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,5) \ 398331583Shselasky MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,6) \ 399331583Shselasky MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,7) 400331583Shselasky 401347865Shselasky#define MLX5E_PCIE_PERFORMANCE_COUNTERS_64(m) \ 402347865Shselasky m(+1, u64, life_time_counter_high, "life_time_counter", \ 403347865Shselasky "Life time counter.", pcie_perf_counters) \ 404347865Shselasky m(+1, u64, tx_overflow_buffer_pkt, "tx_overflow_buffer_pkt", \ 405347865Shselasky "The number of packets dropped due to lack of PCIe buffers " \ 406347865Shselasky "in receive path from NIC port toward the hosts.", \ 407347865Shselasky pcie_perf_counters) \ 408347865Shselasky m(+1, u64, tx_overflow_buffer_marked_pkt, \ 409347865Shselasky "tx_overflow_buffer_marked_pkt", \ 410347865Shselasky "The number of packets marked due to lack of PCIe buffers " \ 411347865Shselasky "in receive path from NIC port toward the hosts.", \ 412347865Shselasky pcie_perf_counters) 413347865Shselasky 414347865Shselasky#define MLX5E_PCIE_PERFORMANCE_COUNTERS_32(m) \ 415347865Shselasky m(+1, u64, rx_errors, "rx_errors", \ 416347865Shselasky "Number of transitions to recovery due to Framing " \ 417347865Shselasky "errors and CRC errors.", pcie_perf_counters) \ 418347865Shselasky m(+1, u64, tx_errors, "tx_errors", "Number of transitions " \ 419347865Shselasky "to recovery due to EIEOS and TS errors.", pcie_perf_counters) \ 420347865Shselasky m(+1, u64, l0_to_recovery_eieos, "l0_to_recovery_eieos", "Number of " \ 421347865Shselasky "transitions to recovery due to getting EIEOS.", pcie_perf_counters)\ 422347865Shselasky m(+1, u64, l0_to_recovery_ts, "l0_to_recovery_ts", "Number of " \ 423347865Shselasky "transitions to recovery due to getting TS.", pcie_perf_counters) \ 424347865Shselasky m(+1, u64, l0_to_recovery_framing, "l0_to_recovery_framing", "Number "\ 425347865Shselasky "of transitions to recovery due to identifying framing " \ 426347865Shselasky "errors at gen3/4.", pcie_perf_counters) \ 427347865Shselasky m(+1, u64, l0_to_recovery_retrain, "l0_to_recovery_retrain", \ 428347865Shselasky "Number of transitions to recovery due to link retrain request " \ 429347865Shselasky "from data link.", pcie_perf_counters) \ 430347865Shselasky m(+1, u64, crc_error_dllp, "crc_error_dllp", "Number of transitions " \ 431347865Shselasky "to recovery due to identifying CRC DLLP errors.", \ 432347865Shselasky pcie_perf_counters) \ 433347865Shselasky m(+1, u64, crc_error_tlp, "crc_error_tlp", "Number of transitions to "\ 434347865Shselasky "recovery due to identifying CRC TLP errors.", pcie_perf_counters) \ 435347865Shselasky m(+1, u64, outbound_stalled_reads, "outbound_stalled_reads", \ 436347865Shselasky "The percentage of time within the last second that the NIC had " \ 437347865Shselasky "outbound non-posted read requests but could not perform the " \ 438347865Shselasky "operation due to insufficient non-posted credits.", \ 439347865Shselasky pcie_perf_counters) \ 440347865Shselasky m(+1, u64, outbound_stalled_writes, "outbound_stalled_writes", \ 441347865Shselasky "The percentage of time within the last second that the NIC had " \ 442347865Shselasky "outbound posted writes requests but could not perform the " \ 443347865Shselasky "operation due to insufficient posted credits.", \ 444347865Shselasky pcie_perf_counters) \ 445347865Shselasky m(+1, u64, outbound_stalled_reads_events, \ 446347865Shselasky "outbound_stalled_reads_events", "The number of events where " \ 447347865Shselasky "outbound_stalled_reads was above a threshold.", \ 448347865Shselasky pcie_perf_counters) \ 449347865Shselasky m(+1, u64, outbound_stalled_writes_events, \ 450347865Shselasky "outbound_stalled_writes_events", \ 451347865Shselasky "The number of events where outbound_stalled_writes was above " \ 452347865Shselasky "a threshold.", pcie_perf_counters) 453347865Shselasky 454347865Shselasky#define MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(m) \ 455347865Shselasky m(+1, u64, time_to_boot_image_start, "time_to_boot_image_start", \ 456347865Shselasky "Time from start until FW boot image starts running in usec.", \ 457347865Shselasky pcie_timers_states) \ 458347865Shselasky m(+1, u64, time_to_link_image, "time_to_link_image", \ 459347865Shselasky "Time from start until FW pci_link image starts running in usec.", \ 460347865Shselasky pcie_timers_states) \ 461347865Shselasky m(+1, u64, calibration_time, "calibration_time", \ 462347865Shselasky "Time it took FW to do calibration in usec.", \ 463347865Shselasky pcie_timers_states) \ 464347865Shselasky m(+1, u64, time_to_first_perst, "time_to_first_perst", \ 465347865Shselasky "Time form start until FW handle first perst. in usec.", \ 466347865Shselasky pcie_timers_states) \ 467347865Shselasky m(+1, u64, time_to_detect_state, "time_to_detect_state", \ 468347865Shselasky "Time from start until first transition to LTSSM.Detect_Q in usec", \ 469347865Shselasky pcie_timers_states) \ 470347865Shselasky m(+1, u64, time_to_l0, "time_to_l0", \ 471347865Shselasky "Time from start until first transition to LTSSM.L0 in usec", \ 472347865Shselasky pcie_timers_states) \ 473347865Shselasky m(+1, u64, time_to_crs_en, "time_to_crs_en", \ 474347865Shselasky "Time from start until crs is enabled in usec", \ 475347865Shselasky pcie_timers_states) \ 476347865Shselasky m(+1, u64, time_to_plastic_image_start, "time_to_plastic_image_start",\ 477347865Shselasky "Time form start until FW plastic image starts running in usec.", \ 478347865Shselasky pcie_timers_states) \ 479347865Shselasky m(+1, u64, time_to_iron_image_start, "time_to_iron_image_start", \ 480347865Shselasky "Time form start until FW iron image starts running in usec.", \ 481347865Shselasky pcie_timers_states) \ 482347865Shselasky m(+1, u64, perst_handler, "perst_handler", \ 483347865Shselasky "Number of persts arrived.", pcie_timers_states) \ 484347865Shselasky m(+1, u64, times_in_l1, "times_in_l1", \ 485347865Shselasky "Number of times LTSSM entered L1 flow.", pcie_timers_states) \ 486347865Shselasky m(+1, u64, times_in_l23, "times_in_l23", \ 487347865Shselasky "Number of times LTSSM entered L23 flow.", pcie_timers_states) \ 488347865Shselasky m(+1, u64, dl_down, "dl_down", \ 489347865Shselasky "Number of moves for DL_active to DL_down.", pcie_timers_states) \ 490347865Shselasky m(+1, u64, config_cycle1usec, "config_cycle1usec", \ 491347865Shselasky "Number of configuration requests that firmware " \ 492347865Shselasky "handled in less than 1 usec.", pcie_timers_states) \ 493347865Shselasky m(+1, u64, config_cycle2to7usec, "config_cycle2to7usec", \ 494347865Shselasky "Number of configuration requests that firmware " \ 495347865Shselasky "handled within 2 to 7 usec.", pcie_timers_states) \ 496347865Shselasky m(+1, u64, config_cycle8to15usec, "config_cycle8to15usec", \ 497347865Shselasky "Number of configuration requests that firmware " \ 498347865Shselasky "handled within 8 to 15 usec.", pcie_timers_states) \ 499347865Shselasky m(+1, u64, config_cycle16to63usec, "config_cycle16to63usec", \ 500347865Shselasky "Number of configuration requests that firmware " \ 501347865Shselasky "handled within 16 to 63 usec.", pcie_timers_states) \ 502347865Shselasky m(+1, u64, config_cycle64usec, "config_cycle64usec", \ 503347865Shselasky "Number of configuration requests that firmware " \ 504347865Shselasky "handled took more than 64 usec.", pcie_timers_states) \ 505347865Shselasky m(+1, u64, correctable_err_msg_sent, "correctable_err_msg_sent", \ 506347865Shselasky "Number of correctable error messages sent.", pcie_timers_states) \ 507347865Shselasky m(+1, u64, non_fatal_err_msg_sent, "non_fatal_err_msg_sent", \ 508347865Shselasky "Number of non-Fatal error msg sent.", pcie_timers_states) \ 509347865Shselasky m(+1, u64, fatal_err_msg_sent, "fatal_err_msg_sent", \ 510347865Shselasky "Number of fatal error msg sent.", pcie_timers_states) 511347865Shselasky 512347865Shselasky#define MLX5E_PCIE_LANE_COUNTERS_32(m) \ 513347865Shselasky m(+1, u64, error_counter_lane0, "error_counter_lane0", \ 514347865Shselasky "Error counter for PCI lane 0", pcie_lanes_counters) \ 515347865Shselasky m(+1, u64, error_counter_lane1, "error_counter_lane1", \ 516347865Shselasky "Error counter for PCI lane 1", pcie_lanes_counters) \ 517347865Shselasky m(+1, u64, error_counter_lane2, "error_counter_lane2", \ 518347865Shselasky "Error counter for PCI lane 2", pcie_lanes_counters) \ 519347865Shselasky m(+1, u64, error_counter_lane3, "error_counter_lane3", \ 520347865Shselasky "Error counter for PCI lane 3", pcie_lanes_counters) \ 521347865Shselasky m(+1, u64, error_counter_lane4, "error_counter_lane4", \ 522347865Shselasky "Error counter for PCI lane 4", pcie_lanes_counters) \ 523347865Shselasky m(+1, u64, error_counter_lane5, "error_counter_lane5", \ 524347865Shselasky "Error counter for PCI lane 5", pcie_lanes_counters) \ 525347865Shselasky m(+1, u64, error_counter_lane6, "error_counter_lane6", \ 526347865Shselasky "Error counter for PCI lane 6", pcie_lanes_counters) \ 527347865Shselasky m(+1, u64, error_counter_lane7, "error_counter_lane7", \ 528347865Shselasky "Error counter for PCI lane 7", pcie_lanes_counters) \ 529347865Shselasky m(+1, u64, error_counter_lane8, "error_counter_lane8", \ 530347865Shselasky "Error counter for PCI lane 8", pcie_lanes_counters) \ 531347865Shselasky m(+1, u64, error_counter_lane9, "error_counter_lane9", \ 532347865Shselasky "Error counter for PCI lane 9", pcie_lanes_counters) \ 533347865Shselasky m(+1, u64, error_counter_lane10, "error_counter_lane10", \ 534347865Shselasky "Error counter for PCI lane 10", pcie_lanes_counters) \ 535347865Shselasky m(+1, u64, error_counter_lane11, "error_counter_lane11", \ 536347865Shselasky "Error counter for PCI lane 11", pcie_lanes_counters) \ 537347865Shselasky m(+1, u64, error_counter_lane12, "error_counter_lane12", \ 538347865Shselasky "Error counter for PCI lane 12", pcie_lanes_counters) \ 539347865Shselasky m(+1, u64, error_counter_lane13, "error_counter_lane13", \ 540347865Shselasky "Error counter for PCI lane 13", pcie_lanes_counters) \ 541347865Shselasky m(+1, u64, error_counter_lane14, "error_counter_lane14", \ 542347865Shselasky "Error counter for PCI lane 14", pcie_lanes_counters) \ 543347865Shselasky m(+1, u64, error_counter_lane15, "error_counter_lane15", \ 544347865Shselasky "Error counter for PCI lane 15", pcie_lanes_counters) 545347865Shselasky 546290650Shselasky/* 547290650Shselasky * Make sure to update mlx5e_update_pport_counters() 548290650Shselasky * when adding a new MLX5E_PPORT_STATS block 549290650Shselasky */ 550290650Shselasky#define MLX5E_PPORT_STATS(m) \ 551331583Shselasky MLX5E_PPORT_PER_PRIO_STATS(m) \ 552290650Shselasky MLX5E_PPORT_IEEE802_3_STATS(m) \ 553291069Shselasky MLX5E_PPORT_RFC2819_STATS(m) 554290650Shselasky 555290650Shselasky#define MLX5E_PORT_STATS_DEBUG(m) \ 556290650Shselasky MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 557290650Shselasky MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 558347804Shselasky MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \ 559347865Shselasky MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(m) \ 560347866Shselasky MLX5E_PPORT_STATISTICAL_DEBUG(m) \ 561347865Shselasky MLX5E_PCIE_PERFORMANCE_COUNTERS_64(m) \ 562347865Shselasky MLX5E_PCIE_PERFORMANCE_COUNTERS_32(m) \ 563347865Shselasky MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(m) \ 564347865Shselasky MLX5E_PCIE_LANE_COUNTERS_32(m) 565290650Shselasky 566290650Shselasky#define MLX5E_PPORT_IEEE802_3_STATS_NUM \ 567290650Shselasky (0 MLX5E_PPORT_IEEE802_3_STATS(MLX5E_STATS_COUNT)) 568290650Shselasky#define MLX5E_PPORT_RFC2819_STATS_NUM \ 569290650Shselasky (0 MLX5E_PPORT_RFC2819_STATS(MLX5E_STATS_COUNT)) 570290650Shselasky#define MLX5E_PPORT_STATS_NUM \ 571290650Shselasky (0 MLX5E_PPORT_STATS(MLX5E_STATS_COUNT)) 572290650Shselasky 573331583Shselasky#define MLX5E_PPORT_PER_PRIO_STATS_NUM \ 574331583Shselasky (0 MLX5E_PPORT_PER_PRIO_STATS(MLX5E_STATS_COUNT)) 575290650Shselasky#define MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM \ 576290650Shselasky (0 MLX5E_PPORT_RFC2819_STATS_DEBUG(MLX5E_STATS_COUNT)) 577290650Shselasky#define MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM \ 578290650Shselasky (0 MLX5E_PPORT_RFC2863_STATS_DEBUG(MLX5E_STATS_COUNT)) 579291070Shselasky#define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM \ 580290650Shselasky (0 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(MLX5E_STATS_COUNT)) 581347804Shselasky#define MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM \ 582347804Shselasky (0 MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(MLX5E_STATS_COUNT)) 583347866Shselasky#define MLX5E_PPORT_STATISTICAL_DEBUG_NUM \ 584347866Shselasky (0 MLX5E_PPORT_STATISTICAL_DEBUG(MLX5E_STATS_COUNT)) 585290650Shselasky#define MLX5E_PORT_STATS_DEBUG_NUM \ 586290650Shselasky (0 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_COUNT)) 587290650Shselasky 588290650Shselaskystruct mlx5e_pport_stats { 589291070Shselasky struct sysctl_ctx_list ctx; 590290650Shselasky u64 arg [0]; 591290650Shselasky MLX5E_PPORT_STATS(MLX5E_STATS_VAR) 592290650Shselasky}; 593290650Shselasky 594290650Shselaskystruct mlx5e_port_stats_debug { 595291070Shselasky struct sysctl_ctx_list ctx; 596290650Shselasky u64 arg [0]; 597290650Shselasky MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_VAR) 598290650Shselasky}; 599290650Shselasky 600290650Shselasky#define MLX5E_RQ_STATS(m) \ 601347864Shselasky m(+1, u64, packets, "packets", "Received packets") \ 602347864Shselasky m(+1, u64, bytes, "bytes", "Received bytes") \ 603347864Shselasky m(+1, u64, csum_none, "csum_none", "Received packets") \ 604347864Shselasky m(+1, u64, lro_packets, "lro_packets", "Received LRO packets") \ 605347864Shselasky m(+1, u64, lro_bytes, "lro_bytes", "Received LRO bytes") \ 606347864Shselasky m(+1, u64, sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 607347864Shselasky m(+1, u64, sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 608347864Shselasky m(+1, u64, wqe_err, "wqe_err", "Received packets") 609290650Shselasky 610290650Shselasky#define MLX5E_RQ_STATS_NUM (0 MLX5E_RQ_STATS(MLX5E_STATS_COUNT)) 611290650Shselasky 612290650Shselaskystruct mlx5e_rq_stats { 613291070Shselasky struct sysctl_ctx_list ctx; 614290650Shselasky u64 arg [0]; 615290650Shselasky MLX5E_RQ_STATS(MLX5E_STATS_VAR) 616290650Shselasky}; 617290650Shselasky 618290650Shselasky#define MLX5E_SQ_STATS(m) \ 619347864Shselasky m(+1, u64, packets, "packets", "Transmitted packets") \ 620347864Shselasky m(+1, u64, bytes, "bytes", "Transmitted bytes") \ 621347864Shselasky m(+1, u64, tso_packets, "tso_packets", "Transmitted packets") \ 622347864Shselasky m(+1, u64, tso_bytes, "tso_bytes", "Transmitted bytes") \ 623347864Shselasky m(+1, u64, csum_offload_none, "csum_offload_none", "Transmitted packets") \ 624347864Shselasky m(+1, u64, defragged, "defragged", "Transmitted packets") \ 625347864Shselasky m(+1, u64, dropped, "dropped", "Transmitted packets") \ 626359853Shselasky m(+1, u64, enobuf, "enobuf", "Transmitted packets") \ 627347864Shselasky m(+1, u64, nop, "nop", "Transmitted packets") 628290650Shselasky 629290650Shselasky#define MLX5E_SQ_STATS_NUM (0 MLX5E_SQ_STATS(MLX5E_STATS_COUNT)) 630290650Shselasky 631290650Shselaskystruct mlx5e_sq_stats { 632291070Shselasky struct sysctl_ctx_list ctx; 633290650Shselasky u64 arg [0]; 634290650Shselasky MLX5E_SQ_STATS(MLX5E_STATS_VAR) 635290650Shselasky}; 636290650Shselasky 637290650Shselaskystruct mlx5e_stats { 638290650Shselasky struct mlx5e_vport_stats vport; 639290650Shselasky struct mlx5e_pport_stats pport; 640290650Shselasky struct mlx5e_port_stats_debug port_stats_debug; 641290650Shselasky}; 642290650Shselasky 643306236Shselaskystruct mlx5e_rq_param { 644306236Shselasky u32 rqc [MLX5_ST_SZ_DW(rqc)]; 645306236Shselasky struct mlx5_wq_param wq; 646306236Shselasky}; 647306236Shselasky 648306236Shselaskystruct mlx5e_sq_param { 649306236Shselasky u32 sqc [MLX5_ST_SZ_DW(sqc)]; 650306236Shselasky struct mlx5_wq_param wq; 651306236Shselasky}; 652306236Shselasky 653306236Shselaskystruct mlx5e_cq_param { 654306236Shselasky u32 cqc [MLX5_ST_SZ_DW(cqc)]; 655306236Shselasky struct mlx5_wq_param wq; 656306236Shselasky}; 657306236Shselasky 658290650Shselaskystruct mlx5e_params { 659290650Shselasky u8 log_sq_size; 660290650Shselasky u8 log_rq_size; 661290650Shselasky u16 num_channels; 662290650Shselasky u8 default_vlan_prio; 663290650Shselasky u8 num_tc; 664290650Shselasky u8 rx_cq_moderation_mode; 665291932Shselasky u8 tx_cq_moderation_mode; 666290650Shselasky u16 rx_cq_moderation_usec; 667290650Shselasky u16 rx_cq_moderation_pkts; 668290650Shselasky u16 tx_cq_moderation_usec; 669290650Shselasky u16 tx_cq_moderation_pkts; 670290650Shselasky u16 min_rx_wqes; 671291070Shselasky bool hw_lro_en; 672292838Shselasky bool cqe_zipping_en; 673291070Shselasky u32 lro_wqe_sz; 674290650Shselasky u16 rx_hash_log_tbl_sz; 675331583Shselasky u32 tx_pauseframe_control __aligned(4); 676331583Shselasky u32 rx_pauseframe_control __aligned(4); 677337114Shselasky u16 tx_max_inline; 678337114Shselasky u8 tx_min_inline_mode; 679347810Shselasky u8 tx_priority_flow_control; 680347810Shselasky u8 rx_priority_flow_control; 681338552Shselasky u8 channels_rsss; 682290650Shselasky}; 683290650Shselasky 684290650Shselasky#define MLX5E_PARAMS(m) \ 685347864Shselasky m(+1, u64, tx_queue_size_max, "tx_queue_size_max", "Max send queue size") \ 686347864Shselasky m(+1, u64, rx_queue_size_max, "rx_queue_size_max", "Max receive queue size") \ 687347864Shselasky m(+1, u64, tx_queue_size, "tx_queue_size", "Default send queue size") \ 688347864Shselasky m(+1, u64, rx_queue_size, "rx_queue_size", "Default receive queue size") \ 689347864Shselasky m(+1, u64, channels, "channels", "Default number of channels") \ 690347864Shselasky m(+1, u64, channels_rsss, "channels_rsss", "Default channels receive side scaling stride") \ 691347864Shselasky m(+1, u64, coalesce_usecs_max, "coalesce_usecs_max", "Maximum usecs for joining packets") \ 692347864Shselasky m(+1, u64, coalesce_pkts_max, "coalesce_pkts_max", "Maximum packets to join") \ 693347864Shselasky m(+1, u64, rx_coalesce_usecs, "rx_coalesce_usecs", "Limit in usec for joining rx packets") \ 694347864Shselasky m(+1, u64, rx_coalesce_pkts, "rx_coalesce_pkts", "Maximum number of rx packets to join") \ 695347864Shselasky m(+1, u64, rx_coalesce_mode, "rx_coalesce_mode", "0: EQE fixed mode 1: CQE fixed mode 2: EQE auto mode 3: CQE auto mode") \ 696347864Shselasky m(+1, u64, tx_coalesce_usecs, "tx_coalesce_usecs", "Limit in usec for joining tx packets") \ 697347864Shselasky m(+1, u64, tx_coalesce_pkts, "tx_coalesce_pkts", "Maximum number of tx packets to join") \ 698347864Shselasky m(+1, u64, tx_coalesce_mode, "tx_coalesce_mode", "0: EQE mode 1: CQE mode") \ 699347864Shselasky m(+1, u64, tx_completion_fact, "tx_completion_fact", "1..MAX: Completion event ratio") \ 700347864Shselasky m(+1, u64, tx_completion_fact_max, "tx_completion_fact_max", "Maximum completion event ratio") \ 701347864Shselasky m(+1, u64, hw_lro, "hw_lro", "set to enable hw_lro") \ 702347864Shselasky m(+1, u64, cqe_zipping, "cqe_zipping", "0 : CQE zipping disabled") \ 703347864Shselasky m(+1, u64, modify_tx_dma, "modify_tx_dma", "0: Enable TX 1: Disable TX") \ 704347864Shselasky m(+1, u64, modify_rx_dma, "modify_rx_dma", "0: Enable RX 1: Disable RX") \ 705347864Shselasky m(+1, u64, diag_pci_enable, "diag_pci_enable", "0: Disabled 1: Enabled") \ 706347864Shselasky m(+1, u64, diag_general_enable, "diag_general_enable", "0: Disabled 1: Enabled") \ 707347864Shselasky m(+1, u64, hw_mtu, "hw_mtu", "Current hardware MTU value") \ 708347864Shselasky m(+1, u64, mc_local_lb, "mc_local_lb", "0: Local multicast loopback enabled 1: Disabled") \ 709347864Shselasky m(+1, u64, uc_local_lb, "uc_local_lb", "0: Local unicast loopback enabled 1: Disabled") 710290650Shselasky 711290650Shselasky#define MLX5E_PARAMS_NUM (0 MLX5E_PARAMS(MLX5E_STATS_COUNT)) 712290650Shselasky 713290650Shselaskystruct mlx5e_params_ethtool { 714290650Shselasky u64 arg [0]; 715290650Shselasky MLX5E_PARAMS(MLX5E_STATS_VAR) 716331577Shselasky u64 max_bw_value[IEEE_8021QAZ_MAX_TCS]; 717341968Shselasky u8 max_bw_share[IEEE_8021QAZ_MAX_TCS]; 718347810Shselasky u8 prio_tc[MLX5E_MAX_PRIORITY]; 719337098Shselasky u8 dscp2prio[MLX5_MAX_SUPPORTED_DSCP]; 720337098Shselasky u8 trust_state; 721353244Shselasky u8 fec_mask_10x_25x[MLX5E_MAX_FEC_10X_25X]; 722353244Shselasky u16 fec_mask_50x[MLX5E_MAX_FEC_50X]; 723353244Shselasky u8 fec_avail_10x_25x[MLX5E_MAX_FEC_10X_25X]; 724353244Shselasky u16 fec_avail_50x[MLX5E_MAX_FEC_50X]; 725353244Shselasky u32 fec_mode_active; 726361171Shselasky s32 hw_val_temp[MLX5_MAX_TEMPERATURE]; 727361171Shselasky u32 hw_num_temp; 728290650Shselasky}; 729290650Shselasky 730290650Shselaskystruct mlx5e_cq { 731290650Shselasky /* data path - accessed per cqe */ 732290650Shselasky struct mlx5_cqwq wq; 733290650Shselasky 734290650Shselasky /* data path - accessed per HW polling */ 735290650Shselasky struct mlx5_core_cq mcq; 736290650Shselasky 737290650Shselasky /* control */ 738306234Shselasky struct mlx5e_priv *priv; 739290650Shselasky struct mlx5_wq_ctrl wq_ctrl; 740290650Shselasky} __aligned(MLX5E_CACHELINE_SIZE); 741290650Shselasky 742290650Shselaskystruct mlx5e_rq_mbuf { 743291070Shselasky bus_dmamap_t dma_map; 744291070Shselasky caddr_t data; 745291070Shselasky struct mbuf *mbuf; 746290650Shselasky}; 747290650Shselasky 748290650Shselaskystruct mlx5e_rq { 749353252Shselasky /* persistant fields */ 750353252Shselasky struct mtx mtx; 751353252Shselasky struct mlx5e_rq_stats stats; 752353406Shselasky struct callout watchdog; 753353252Shselasky 754290650Shselasky /* data path */ 755353252Shselasky#define mlx5e_rq_zero_start wq 756290650Shselasky struct mlx5_wq_ll wq; 757290650Shselasky bus_dma_tag_t dma_tag; 758290650Shselasky u32 wqe_sz; 759337110Shselasky u32 nsegs; 760290650Shselasky struct mlx5e_rq_mbuf *mbuf; 761290650Shselasky struct ifnet *ifp; 762290650Shselasky struct mlx5e_cq cq; 763290650Shselasky struct lro_ctrl lro; 764290650Shselasky volatile int enabled; 765290650Shselasky int ix; 766290650Shselasky 767347796Shselasky /* Dynamic Interrupt Moderation */ 768347796Shselasky struct net_dim dim; 769347796Shselasky 770290650Shselasky /* control */ 771290650Shselasky struct mlx5_wq_ctrl wq_ctrl; 772290650Shselasky u32 rqn; 773290650Shselasky struct mlx5e_channel *channel; 774290650Shselasky} __aligned(MLX5E_CACHELINE_SIZE); 775290650Shselasky 776290650Shselaskystruct mlx5e_sq_mbuf { 777290650Shselasky bus_dmamap_t dma_map; 778290650Shselasky struct mbuf *mbuf; 779290650Shselasky u32 num_bytes; 780290650Shselasky u32 num_wqebbs; 781290650Shselasky}; 782290650Shselasky 783290650Shselaskyenum { 784290650Shselasky MLX5E_SQ_READY, 785290650Shselasky MLX5E_SQ_FULL 786290650Shselasky}; 787290650Shselasky 788290650Shselaskystruct mlx5e_sq { 789353252Shselasky /* persistant fields */ 790291070Shselasky struct mtx lock; 791291070Shselasky struct mtx comp_lock; 792353252Shselasky struct mlx5e_sq_stats stats; 793369088Sgit2svn struct callout cev_callout; 794290650Shselasky 795353252Shselasky /* data path */ 796353252Shselasky#define mlx5e_sq_zero_start dma_tag 797353252Shselasky bus_dma_tag_t dma_tag; 798353252Shselasky 799290650Shselasky /* dirtied @completion */ 800290650Shselasky u16 cc; 801290650Shselasky 802290650Shselasky /* dirtied @xmit */ 803290650Shselasky u16 pc __aligned(MLX5E_CACHELINE_SIZE); 804290650Shselasky u16 bf_offset; 805300277Shselasky u16 cev_counter; /* completion event counter */ 806300277Shselasky u16 cev_factor; /* completion event factor */ 807321997Shselasky u16 cev_next_state; /* next completion event state */ 808300277Shselasky#define MLX5E_CEV_STATE_INITIAL 0 /* timer not started */ 809300277Shselasky#define MLX5E_CEV_STATE_SEND_NOPS 1 /* send NOPs */ 810300277Shselasky#define MLX5E_CEV_STATE_HOLD_NOPS 2 /* don't send NOPs yet */ 811341979Shselasky u16 running; /* set if SQ is running */ 812300280Shselasky union { 813300280Shselasky u32 d32[2]; 814300280Shselasky u64 d64; 815300280Shselasky } doorbell; 816290650Shselasky 817291070Shselasky struct mlx5e_cq cq; 818290650Shselasky 819290650Shselasky /* pointers to per packet info: write@xmit, read@completion */ 820291070Shselasky struct mlx5e_sq_mbuf *mbuf; 821290650Shselasky 822290650Shselasky /* read only */ 823291070Shselasky struct mlx5_wq_cyc wq; 824306237Shselasky struct mlx5_uar uar; 825306234Shselasky struct ifnet *ifp; 826290650Shselasky u32 sqn; 827290650Shselasky u32 bf_buf_size; 828290650Shselasky u32 mkey_be; 829337114Shselasky u16 max_inline; 830337114Shselasky u8 min_inline_mode; 831341972Shselasky u8 min_insert_caps; 832341972Shselasky#define MLX5E_INSERT_VLAN 1 833341972Shselasky#define MLX5E_INSERT_NON_VLAN 2 834290650Shselasky 835290650Shselasky /* control path */ 836291070Shselasky struct mlx5_wq_ctrl wq_ctrl; 837306234Shselasky struct mlx5e_priv *priv; 838290650Shselasky int tc; 839290650Shselasky} __aligned(MLX5E_CACHELINE_SIZE); 840290650Shselasky 841290650Shselaskystatic inline bool 842290650Shselaskymlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) 843290650Shselasky{ 844322003Shselasky u16 cc = sq->cc; 845322003Shselasky u16 pc = sq->pc; 846322003Shselasky 847322003Shselasky return ((sq->wq.sz_m1 & (cc - pc)) >= n || cc == pc); 848290650Shselasky} 849290650Shselasky 850290650Shselaskystruct mlx5e_channel { 851290650Shselasky struct mlx5e_rq rq; 852290650Shselasky struct mlx5e_sq sq[MLX5E_MAX_TX_NUM_TC]; 853290650Shselasky struct ifnet *ifp; 854290650Shselasky struct mlx5e_priv *priv; 855290650Shselasky int ix; 856290650Shselasky} __aligned(MLX5E_CACHELINE_SIZE); 857290650Shselasky 858290650Shselaskyenum mlx5e_traffic_types { 859290650Shselasky MLX5E_TT_IPV4_TCP, 860290650Shselasky MLX5E_TT_IPV6_TCP, 861290650Shselasky MLX5E_TT_IPV4_UDP, 862290650Shselasky MLX5E_TT_IPV6_UDP, 863290650Shselasky MLX5E_TT_IPV4_IPSEC_AH, 864290650Shselasky MLX5E_TT_IPV6_IPSEC_AH, 865290650Shselasky MLX5E_TT_IPV4_IPSEC_ESP, 866290650Shselasky MLX5E_TT_IPV6_IPSEC_ESP, 867290650Shselasky MLX5E_TT_IPV4, 868290650Shselasky MLX5E_TT_IPV6, 869290650Shselasky MLX5E_TT_ANY, 870290650Shselasky MLX5E_NUM_TT, 871290650Shselasky}; 872290650Shselasky 873290650Shselaskyenum { 874290650Shselasky MLX5E_RQT_SPREADING = 0, 875290650Shselasky MLX5E_RQT_DEFAULT_RQ = 1, 876290650Shselasky MLX5E_NUM_RQT = 2, 877290650Shselasky}; 878290650Shselasky 879329200Shselaskystruct mlx5_flow_rule; 880329200Shselasky 881290650Shselaskystruct mlx5e_eth_addr_info { 882290650Shselasky u8 addr [ETH_ALEN + 2]; 883290650Shselasky u32 tt_vec; 884329200Shselasky /* flow table rule per traffic type */ 885329200Shselasky struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT]; 886290650Shselasky}; 887290650Shselasky 888290650Shselasky#define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE) 889290650Shselasky 890290650Shselaskystruct mlx5e_eth_addr_hash_node; 891290650Shselasky 892290650Shselaskystruct mlx5e_eth_addr_hash_head { 893290650Shselasky struct mlx5e_eth_addr_hash_node *lh_first; 894290650Shselasky}; 895290650Shselasky 896290650Shselaskystruct mlx5e_eth_addr_db { 897290650Shselasky struct mlx5e_eth_addr_hash_head if_uc[MLX5E_ETH_ADDR_HASH_SIZE]; 898290650Shselasky struct mlx5e_eth_addr_hash_head if_mc[MLX5E_ETH_ADDR_HASH_SIZE]; 899290650Shselasky struct mlx5e_eth_addr_info broadcast; 900290650Shselasky struct mlx5e_eth_addr_info allmulti; 901290650Shselasky struct mlx5e_eth_addr_info promisc; 902290650Shselasky bool broadcast_enabled; 903290650Shselasky bool allmulti_enabled; 904290650Shselasky bool promisc_enabled; 905290650Shselasky}; 906290650Shselasky 907290650Shselaskyenum { 908290650Shselasky MLX5E_STATE_ASYNC_EVENTS_ENABLE, 909290650Shselasky MLX5E_STATE_OPENED, 910290650Shselasky}; 911290650Shselasky 912331577Shselaskyenum { 913331577Shselasky MLX5_BW_NO_LIMIT = 0, 914331577Shselasky MLX5_100_MBPS_UNIT = 3, 915331577Shselasky MLX5_GBPS_UNIT = 4, 916331577Shselasky}; 917331577Shselasky 918290650Shselaskystruct mlx5e_vlan_db { 919290650Shselasky unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 920329200Shselasky struct mlx5_flow_rule *active_vlans_ft_rule[VLAN_N_VID]; 921329200Shselasky struct mlx5_flow_rule *untagged_ft_rule; 922329200Shselasky struct mlx5_flow_rule *any_cvlan_ft_rule; 923329200Shselasky struct mlx5_flow_rule *any_svlan_ft_rule; 924290650Shselasky bool filter_disabled; 925290650Shselasky}; 926290650Shselasky 927290650Shselaskystruct mlx5e_flow_table { 928329200Shselasky int num_groups; 929329200Shselasky struct mlx5_flow_table *t; 930329200Shselasky struct mlx5_flow_group **g; 931290650Shselasky}; 932290650Shselasky 933329200Shselaskystruct mlx5e_flow_tables { 934329200Shselasky struct mlx5_flow_namespace *ns; 935329200Shselasky struct mlx5e_flow_table vlan; 936329200Shselasky struct mlx5e_flow_table main; 937329200Shselasky struct mlx5e_flow_table inner_rss; 938329200Shselasky}; 939329200Shselasky 940353236Shselaskystruct mlx5e_dcbx { 941353236Shselasky u32 cable_len; 942353236Shselasky u32 xoff; 943353236Shselasky}; 944353236Shselasky 945290650Shselaskystruct mlx5e_priv { 946329299Shselasky struct mlx5_core_dev *mdev; /* must be first */ 947329299Shselasky 948290650Shselasky /* priv data path fields - start */ 949290650Shselasky int order_base_2_num_channels; 950290650Shselasky int queue_mapping_channel_mask; 951290650Shselasky int num_tc; 952290650Shselasky int default_vlan_prio; 953290650Shselasky /* priv data path fields - end */ 954290650Shselasky 955290650Shselasky unsigned long state; 956290650Shselasky int gone; 957290650Shselasky#define PRIV_LOCK(priv) sx_xlock(&(priv)->state_lock) 958290650Shselasky#define PRIV_UNLOCK(priv) sx_xunlock(&(priv)->state_lock) 959290650Shselasky#define PRIV_LOCKED(priv) sx_xlocked(&(priv)->state_lock) 960353195Shselasky#define PRIV_ASSERT_LOCKED(priv) sx_assert(&(priv)->state_lock, SA_XLOCKED) 961290650Shselasky struct sx state_lock; /* Protects Interface state */ 962290650Shselasky struct mlx5_uar cq_uar; 963290650Shselasky u32 pdn; 964290650Shselasky u32 tdn; 965290650Shselasky struct mlx5_core_mr mr; 966290650Shselasky 967290650Shselasky u32 tisn[MLX5E_MAX_TX_NUM_TC]; 968290650Shselasky u32 rqtn; 969290650Shselasky u32 tirn[MLX5E_NUM_TT]; 970290650Shselasky 971329200Shselasky struct mlx5e_flow_tables fts; 972290650Shselasky struct mlx5e_eth_addr_db eth_addr; 973290650Shselasky struct mlx5e_vlan_db vlan; 974290650Shselasky 975290650Shselasky struct mlx5e_params params; 976290650Shselasky struct mlx5e_params_ethtool params_ethtool; 977322006Shselasky union mlx5_core_pci_diagnostics params_pci; 978322006Shselasky union mlx5_core_general_diagnostics params_general; 979290650Shselasky struct mtx async_events_mtx; /* sync hw events */ 980290650Shselasky struct work_struct update_stats_work; 981290650Shselasky struct work_struct update_carrier_work; 982290650Shselasky struct work_struct set_rx_mode_work; 983306238Shselasky MLX5_DECLARE_DOORBELL_LOCK(doorbell_lock) 984290650Shselasky 985290650Shselasky struct ifnet *ifp; 986290650Shselasky struct sysctl_ctx_list sysctl_ctx; 987290650Shselasky struct sysctl_oid *sysctl_ifnet; 988290650Shselasky struct sysctl_oid *sysctl_hw; 989290650Shselasky int sysctl_debug; 990290650Shselasky struct mlx5e_stats stats; 991290650Shselasky int counter_set_id; 992290650Shselasky 993331803Shselasky struct workqueue_struct *wq; 994331803Shselasky 995290650Shselasky eventhandler_tag vlan_detach; 996290650Shselasky eventhandler_tag vlan_attach; 997290650Shselasky struct ifmedia media; 998290650Shselasky int media_status_last; 999290650Shselasky int media_active_last; 1000290650Shselasky 1001290650Shselasky struct callout watchdog; 1002341979Shselasky 1003353236Shselasky struct mlx5e_dcbx dcbx; 1004353262Shselasky bool sw_is_port_buf_owner; 1005353236Shselasky 1006341979Shselasky struct mlx5e_channel channel[]; 1007290650Shselasky}; 1008290650Shselasky 1009290650Shselasky#define MLX5E_NET_IP_ALIGN 2 1010290650Shselasky 1011290650Shselaskystruct mlx5e_tx_wqe { 1012290650Shselasky struct mlx5_wqe_ctrl_seg ctrl; 1013290650Shselasky struct mlx5_wqe_eth_seg eth; 1014290650Shselasky}; 1015290650Shselasky 1016290650Shselaskystruct mlx5e_rx_wqe { 1017290650Shselasky struct mlx5_wqe_srq_next_seg next; 1018337110Shselasky struct mlx5_wqe_data_seg data[]; 1019290650Shselasky}; 1020290650Shselasky 1021337110Shselasky/* the size of the structure above must be power of two */ 1022337110ShselaskyCTASSERT(powerof2(sizeof(struct mlx5e_rx_wqe))); 1023337110Shselasky 1024290650Shselaskystruct mlx5e_eeprom { 1025291070Shselasky int lock_bit; 1026291070Shselasky int i2c_addr; 1027291070Shselasky int page_num; 1028291070Shselasky int device_addr; 1029291070Shselasky int module_num; 1030291070Shselasky int len; 1031291070Shselasky int type; 1032291070Shselasky int page_valid; 1033291070Shselasky u32 *data; 1034290650Shselasky}; 1035290650Shselasky 1036290650Shselasky#define MLX5E_FLD_MAX(typ, fld) ((1ULL << __mlx5_bit_sz(typ, fld)) - 1ULL) 1037290650Shselasky 1038290650Shselaskyint mlx5e_xmit(struct ifnet *, struct mbuf *); 1039290650Shselasky 1040290650Shselaskyint mlx5e_open_locked(struct ifnet *); 1041290650Shselaskyint mlx5e_close_locked(struct ifnet *); 1042290650Shselasky 1043290650Shselaskyvoid mlx5e_cq_error_event(struct mlx5_core_cq *mcq, int event); 1044290650Shselaskyvoid mlx5e_rx_cq_comp(struct mlx5_core_cq *); 1045290650Shselaskyvoid mlx5e_tx_cq_comp(struct mlx5_core_cq *); 1046291070Shselaskystruct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); 1047290650Shselasky 1048347796Shselaskyvoid mlx5e_dim_work(struct work_struct *); 1049347796Shselaskyvoid mlx5e_dim_build_cq_param(struct mlx5e_priv *, struct mlx5e_cq_param *); 1050347796Shselasky 1051290650Shselaskyint mlx5e_open_flow_table(struct mlx5e_priv *priv); 1052290650Shselaskyvoid mlx5e_close_flow_table(struct mlx5e_priv *priv); 1053290650Shselaskyvoid mlx5e_set_rx_mode_core(struct mlx5e_priv *priv); 1054290650Shselaskyvoid mlx5e_set_rx_mode_work(struct work_struct *work); 1055290650Shselasky 1056290650Shselaskyvoid mlx5e_vlan_rx_add_vid(void *, struct ifnet *, u16); 1057290650Shselaskyvoid mlx5e_vlan_rx_kill_vid(void *, struct ifnet *, u16); 1058290650Shselaskyvoid mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); 1059290650Shselaskyvoid mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); 1060290650Shselaskyint mlx5e_add_all_vlan_rules(struct mlx5e_priv *priv); 1061290650Shselaskyvoid mlx5e_del_all_vlan_rules(struct mlx5e_priv *priv); 1062290650Shselasky 1063290650Shselaskystatic inline void 1064300280Shselaskymlx5e_tx_notify_hw(struct mlx5e_sq *sq, u32 *wqe, int bf_sz) 1065290650Shselasky{ 1066290650Shselasky u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; 1067290650Shselasky 1068290650Shselasky /* ensure wqe is visible to device before updating doorbell record */ 1069290650Shselasky wmb(); 1070290650Shselasky 1071290650Shselasky *sq->wq.db = cpu_to_be32(sq->pc); 1072290650Shselasky 1073290650Shselasky /* 1074290650Shselasky * Ensure the doorbell record is visible to device before ringing 1075290650Shselasky * the doorbell: 1076290650Shselasky */ 1077290650Shselasky wmb(); 1078290650Shselasky 1079290650Shselasky if (bf_sz) { 1080306237Shselasky __iowrite64_copy(sq->uar.bf_map + ofst, wqe, bf_sz); 1081290650Shselasky 1082290650Shselasky /* flush the write-combining mapped buffer */ 1083290650Shselasky wmb(); 1084290650Shselasky 1085290650Shselasky } else { 1086306238Shselasky mlx5_write64(wqe, sq->uar.map + ofst, 1087306238Shselasky MLX5_GET_DOORBELL_LOCK(&sq->priv->doorbell_lock)); 1088290650Shselasky } 1089290650Shselasky 1090290650Shselasky sq->bf_offset ^= sq->bf_buf_size; 1091290650Shselasky} 1092290650Shselasky 1093290650Shselaskystatic inline void 1094324522Shselaskymlx5e_cq_arm(struct mlx5e_cq *cq, spinlock_t *dblock) 1095290650Shselasky{ 1096290650Shselasky struct mlx5_core_cq *mcq; 1097290650Shselasky 1098290650Shselasky mcq = &cq->mcq; 1099324522Shselasky mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, dblock, cq->wq.cc); 1100290650Shselasky} 1101290650Shselasky 1102353234Shselasky#define mlx5e_dbg(_IGN, _priv, ...) mlx5_core_dbg((_priv)->mdev, __VA_ARGS__) 1103353234Shselasky 1104290650Shselaskyextern const struct ethtool_ops mlx5e_ethtool_ops; 1105290650Shselaskyvoid mlx5e_create_ethtool(struct mlx5e_priv *); 1106290650Shselaskyvoid mlx5e_create_stats(struct sysctl_ctx_list *, 1107290650Shselasky struct sysctl_oid_list *, const char *, 1108290650Shselasky const char **, unsigned, u64 *); 1109300280Shselaskyvoid mlx5e_send_nop(struct mlx5e_sq *, u32); 1110300277Shselaskyvoid mlx5e_sq_cev_timeout(void *); 1111292949Shselaskyint mlx5e_refresh_channel_params(struct mlx5e_priv *); 1112306236Shselaskyint mlx5e_open_cq(struct mlx5e_priv *, struct mlx5e_cq_param *, 1113306236Shselasky struct mlx5e_cq *, mlx5e_cq_comp_t *, int eq_ix); 1114306236Shselaskyvoid mlx5e_close_cq(struct mlx5e_cq *); 1115306239Shselaskyvoid mlx5e_free_sq_db(struct mlx5e_sq *); 1116306239Shselaskyint mlx5e_alloc_sq_db(struct mlx5e_sq *); 1117306239Shselaskyint mlx5e_enable_sq(struct mlx5e_sq *, struct mlx5e_sq_param *, int tis_num); 1118306239Shselaskyint mlx5e_modify_sq(struct mlx5e_sq *, int curr_state, int next_state); 1119306239Shselaskyvoid mlx5e_disable_sq(struct mlx5e_sq *); 1120306239Shselaskyvoid mlx5e_drain_sq(struct mlx5e_sq *); 1121331568Shselaskyvoid mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value); 1122331568Shselaskyvoid mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value); 1123331568Shselaskyvoid mlx5e_resume_sq(struct mlx5e_sq *sq); 1124341972Shselaskyvoid mlx5e_update_sq_inline(struct mlx5e_sq *sq); 1125341972Shselaskyvoid mlx5e_refresh_sq_inline(struct mlx5e_priv *priv); 1126353238Shselaskyint mlx5e_update_buf_lossy(struct mlx5e_priv *priv); 1127353244Shselaskyint mlx5e_fec_update(struct mlx5e_priv *priv); 1128361171Shselaskyint mlx5e_hw_temperature_update(struct mlx5e_priv *priv); 1129290650Shselasky 1130290650Shselasky#endif /* _MLX5_EN_H_ */ 1131