mlx5_main.c revision 353254
1290650Shselasky/*- 2347819Shselasky * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved. 3290650Shselasky * 4290650Shselasky * Redistribution and use in source and binary forms, with or without 5290650Shselasky * modification, are permitted provided that the following conditions 6290650Shselasky * are met: 7290650Shselasky * 1. Redistributions of source code must retain the above copyright 8290650Shselasky * notice, this list of conditions and the following disclaimer. 9290650Shselasky * 2. Redistributions in binary form must reproduce the above copyright 10290650Shselasky * notice, this list of conditions and the following disclaimer in the 11290650Shselasky * documentation and/or other materials provided with the distribution. 12290650Shselasky * 13290650Shselasky * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14290650Shselasky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15290650Shselasky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16290650Shselasky * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17290650Shselasky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18290650Shselasky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19290650Shselasky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20290650Shselasky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21290650Shselasky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22290650Shselasky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23290650Shselasky * SUCH DAMAGE. 24290650Shselasky * 25290650Shselasky * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_core/mlx5_main.c 353254 2019-10-07 10:21:37Z hselasky $ 26290650Shselasky */ 27290650Shselasky 28290650Shselasky#include <linux/kmod.h> 29290650Shselasky#include <linux/module.h> 30290650Shselasky#include <linux/errno.h> 31290650Shselasky#include <linux/pci.h> 32290650Shselasky#include <linux/dma-mapping.h> 33290650Shselasky#include <linux/slab.h> 34290650Shselasky#include <linux/io-mapping.h> 35290650Shselasky#include <linux/interrupt.h> 36347802Shselasky#include <linux/hardirq.h> 37290650Shselasky#include <dev/mlx5/driver.h> 38290650Shselasky#include <dev/mlx5/cq.h> 39290650Shselasky#include <dev/mlx5/qp.h> 40290650Shselasky#include <dev/mlx5/srq.h> 41353197Shselasky#include <dev/mlx5/mpfs.h> 42290650Shselasky#include <linux/delay.h> 43290650Shselasky#include <dev/mlx5/mlx5_ifc.h> 44341958Shselasky#include <dev/mlx5/mlx5_fpga/core.h> 45341958Shselasky#include <dev/mlx5/mlx5_lib/mlx5.h> 46290650Shselasky#include "mlx5_core.h" 47329200Shselasky#include "fs_core.h" 48290650Shselasky 49341948Shselaskystatic const char mlx5_version[] = "Mellanox Core driver " 50341948Shselasky DRIVER_VERSION " (" DRIVER_RELDATE ")"; 51290650ShselaskyMODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 52290650ShselaskyMODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver"); 53290650ShselaskyMODULE_LICENSE("Dual BSD/GPL"); 54290650ShselaskyMODULE_DEPEND(mlx5, linuxkpi, 1, 1, 1); 55347839ShselaskyMODULE_DEPEND(mlx5, mlxfw, 1, 1, 1); 56347847ShselaskyMODULE_DEPEND(mlx5, firmware, 1, 1, 1); 57290650ShselaskyMODULE_VERSION(mlx5, 1); 58290650Shselasky 59347835ShselaskySYSCTL_NODE(_hw, OID_AUTO, mlx5, CTLFLAG_RW, 0, "mlx5 hardware controls"); 60347835Shselasky 61290650Shselaskyint mlx5_core_debug_mask; 62347835ShselaskySYSCTL_INT(_hw_mlx5, OID_AUTO, debug_mask, CTLFLAG_RWTUN, 63347835Shselasky &mlx5_core_debug_mask, 0, 64347835Shselasky "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 65290650Shselasky 66290650Shselasky#define MLX5_DEFAULT_PROF 2 67347835Shselaskystatic int mlx5_prof_sel = MLX5_DEFAULT_PROF; 68347835ShselaskySYSCTL_INT(_hw_mlx5, OID_AUTO, prof_sel, CTLFLAG_RWTUN, 69347835Shselasky &mlx5_prof_sel, 0, 70347835Shselasky "profile selector. Valid range 0 - 2"); 71290650Shselasky 72347819Shselaskystatic int mlx5_fast_unload_enabled = 1; 73347819ShselaskySYSCTL_INT(_hw_mlx5, OID_AUTO, fast_unload_enabled, CTLFLAG_RWTUN, 74347819Shselasky &mlx5_fast_unload_enabled, 0, 75347819Shselasky "Set to enable fast unload. Clear to disable."); 76347819Shselasky 77290650Shselasky#define NUMA_NO_NODE -1 78290650Shselasky 79290650Shselaskystatic LIST_HEAD(intf_list); 80290650Shselaskystatic LIST_HEAD(dev_list); 81290650Shselaskystatic DEFINE_MUTEX(intf_mutex); 82290650Shselasky 83290650Shselaskystruct mlx5_device_context { 84290650Shselasky struct list_head list; 85290650Shselasky struct mlx5_interface *intf; 86290650Shselasky void *context; 87290650Shselasky}; 88290650Shselasky 89329209Shselaskyenum { 90329209Shselasky MLX5_ATOMIC_REQ_MODE_BE = 0x0, 91329209Shselasky MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 92329209Shselasky}; 93329209Shselasky 94290650Shselaskystatic struct mlx5_profile profiles[] = { 95290650Shselasky [0] = { 96290650Shselasky .mask = 0, 97290650Shselasky }, 98290650Shselasky [1] = { 99290650Shselasky .mask = MLX5_PROF_MASK_QP_SIZE, 100290650Shselasky .log_max_qp = 12, 101290650Shselasky }, 102290650Shselasky [2] = { 103290650Shselasky .mask = MLX5_PROF_MASK_QP_SIZE | 104290650Shselasky MLX5_PROF_MASK_MR_CACHE, 105290650Shselasky .log_max_qp = 17, 106290650Shselasky .mr_cache[0] = { 107290650Shselasky .size = 500, 108290650Shselasky .limit = 250 109290650Shselasky }, 110290650Shselasky .mr_cache[1] = { 111290650Shselasky .size = 500, 112290650Shselasky .limit = 250 113290650Shselasky }, 114290650Shselasky .mr_cache[2] = { 115290650Shselasky .size = 500, 116290650Shselasky .limit = 250 117290650Shselasky }, 118290650Shselasky .mr_cache[3] = { 119290650Shselasky .size = 500, 120290650Shselasky .limit = 250 121290650Shselasky }, 122290650Shselasky .mr_cache[4] = { 123290650Shselasky .size = 500, 124290650Shselasky .limit = 250 125290650Shselasky }, 126290650Shselasky .mr_cache[5] = { 127290650Shselasky .size = 500, 128290650Shselasky .limit = 250 129290650Shselasky }, 130290650Shselasky .mr_cache[6] = { 131290650Shselasky .size = 500, 132290650Shselasky .limit = 250 133290650Shselasky }, 134290650Shselasky .mr_cache[7] = { 135290650Shselasky .size = 500, 136290650Shselasky .limit = 250 137290650Shselasky }, 138290650Shselasky .mr_cache[8] = { 139290650Shselasky .size = 500, 140290650Shselasky .limit = 250 141290650Shselasky }, 142290650Shselasky .mr_cache[9] = { 143290650Shselasky .size = 500, 144290650Shselasky .limit = 250 145290650Shselasky }, 146290650Shselasky .mr_cache[10] = { 147290650Shselasky .size = 500, 148290650Shselasky .limit = 250 149290650Shselasky }, 150290650Shselasky .mr_cache[11] = { 151290650Shselasky .size = 500, 152290650Shselasky .limit = 250 153290650Shselasky }, 154290650Shselasky .mr_cache[12] = { 155290650Shselasky .size = 64, 156290650Shselasky .limit = 32 157290650Shselasky }, 158290650Shselasky .mr_cache[13] = { 159290650Shselasky .size = 32, 160290650Shselasky .limit = 16 161290650Shselasky }, 162290650Shselasky .mr_cache[14] = { 163290650Shselasky .size = 16, 164290650Shselasky .limit = 8 165290650Shselasky }, 166290650Shselasky }, 167290650Shselasky [3] = { 168290650Shselasky .mask = MLX5_PROF_MASK_QP_SIZE, 169290650Shselasky .log_max_qp = 17, 170290650Shselasky }, 171290650Shselasky}; 172290650Shselasky 173290650Shselaskystatic int set_dma_caps(struct pci_dev *pdev) 174290650Shselasky{ 175353224Shselasky struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 176290650Shselasky int err; 177290650Shselasky 178290650Shselasky err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 179290650Shselasky if (err) { 180353224Shselasky mlx5_core_warn(dev, "couldn't set 64-bit PCI DMA mask\n"); 181290650Shselasky err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 182290650Shselasky if (err) { 183353224Shselasky mlx5_core_err(dev, "Can't set PCI DMA mask, aborting\n"); 184290650Shselasky return err; 185290650Shselasky } 186290650Shselasky } 187290650Shselasky 188290650Shselasky err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 189290650Shselasky if (err) { 190353224Shselasky mlx5_core_warn(dev, "couldn't set 64-bit consistent PCI DMA mask\n"); 191290650Shselasky err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 192290650Shselasky if (err) { 193353224Shselasky mlx5_core_err(dev, "Can't set consistent PCI DMA mask, aborting\n"); 194290650Shselasky return err; 195290650Shselasky } 196290650Shselasky } 197290650Shselasky 198290650Shselasky dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 199290650Shselasky return err; 200290650Shselasky} 201290650Shselasky 202347862Shselaskyint mlx5_pci_read_power_status(struct mlx5_core_dev *dev, 203347862Shselasky u16 *p_power, u8 *p_status) 204347862Shselasky{ 205347862Shselasky u32 in[MLX5_ST_SZ_DW(mpein_reg)] = {}; 206347862Shselasky u32 out[MLX5_ST_SZ_DW(mpein_reg)] = {}; 207347862Shselasky int err; 208347862Shselasky 209347862Shselasky err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), 210347862Shselasky MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN, 0, 0); 211347862Shselasky 212347862Shselasky *p_status = MLX5_GET(mpein_reg, out, pwr_status); 213347862Shselasky *p_power = MLX5_GET(mpein_reg, out, pci_power); 214347862Shselasky return err; 215347862Shselasky} 216347862Shselasky 217331580Shselaskystatic int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 218331580Shselasky{ 219331580Shselasky struct pci_dev *pdev = dev->pdev; 220331580Shselasky int err = 0; 221331580Shselasky 222331580Shselasky mutex_lock(&dev->pci_status_mutex); 223331580Shselasky if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 224331580Shselasky err = pci_enable_device(pdev); 225331580Shselasky if (!err) 226331580Shselasky dev->pci_status = MLX5_PCI_STATUS_ENABLED; 227331580Shselasky } 228331580Shselasky mutex_unlock(&dev->pci_status_mutex); 229331580Shselasky 230331580Shselasky return err; 231331580Shselasky} 232331580Shselasky 233331580Shselaskystatic void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 234331580Shselasky{ 235331580Shselasky struct pci_dev *pdev = dev->pdev; 236331580Shselasky 237331580Shselasky mutex_lock(&dev->pci_status_mutex); 238331580Shselasky if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 239331580Shselasky pci_disable_device(pdev); 240331580Shselasky dev->pci_status = MLX5_PCI_STATUS_DISABLED; 241331580Shselasky } 242331580Shselasky mutex_unlock(&dev->pci_status_mutex); 243331580Shselasky} 244331580Shselasky 245290650Shselaskystatic int request_bar(struct pci_dev *pdev) 246290650Shselasky{ 247353224Shselasky struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 248290650Shselasky int err = 0; 249290650Shselasky 250290650Shselasky if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 251353224Shselasky mlx5_core_err(dev, "Missing registers BAR, aborting\n"); 252290650Shselasky return -ENODEV; 253290650Shselasky } 254290650Shselasky 255290650Shselasky err = pci_request_regions(pdev, DRIVER_NAME); 256290650Shselasky if (err) 257353224Shselasky mlx5_core_err(dev, "Couldn't get PCI resources, aborting\n"); 258290650Shselasky 259290650Shselasky return err; 260290650Shselasky} 261290650Shselasky 262290650Shselaskystatic void release_bar(struct pci_dev *pdev) 263290650Shselasky{ 264290650Shselasky pci_release_regions(pdev); 265290650Shselasky} 266290650Shselasky 267290650Shselaskystatic int mlx5_enable_msix(struct mlx5_core_dev *dev) 268290650Shselasky{ 269290650Shselasky struct mlx5_priv *priv = &dev->priv; 270290650Shselasky struct mlx5_eq_table *table = &priv->eq_table; 271290650Shselasky int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq); 272338554Shselasky int limit = dev->msix_eqvec; 273337112Shselasky int nvec = MLX5_EQ_VEC_COMP_BASE; 274290650Shselasky int i; 275290650Shselasky 276337112Shselasky if (limit > 0) 277337112Shselasky nvec += limit; 278337112Shselasky else 279337112Shselasky nvec += MLX5_CAP_GEN(dev, num_ports) * num_online_cpus(); 280337112Shselasky 281353189Shselasky if (nvec > num_eqs) 282353189Shselasky nvec = num_eqs; 283353189Shselasky if (nvec > 256) 284353189Shselasky nvec = 256; /* limit of firmware API */ 285290650Shselasky if (nvec <= MLX5_EQ_VEC_COMP_BASE) 286290650Shselasky return -ENOMEM; 287290650Shselasky 288290650Shselasky priv->msix_arr = kzalloc(nvec * sizeof(*priv->msix_arr), GFP_KERNEL); 289290650Shselasky 290290650Shselasky for (i = 0; i < nvec; i++) 291290650Shselasky priv->msix_arr[i].entry = i; 292290650Shselasky 293290650Shselasky nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr, 294290650Shselasky MLX5_EQ_VEC_COMP_BASE + 1, nvec); 295290650Shselasky if (nvec < 0) 296290650Shselasky return nvec; 297290650Shselasky 298290650Shselasky table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE; 299290650Shselasky return 0; 300290650Shselasky} 301290650Shselasky 302290650Shselaskystatic void mlx5_disable_msix(struct mlx5_core_dev *dev) 303290650Shselasky{ 304290650Shselasky struct mlx5_priv *priv = &dev->priv; 305290650Shselasky 306290650Shselasky pci_disable_msix(dev->pdev); 307290650Shselasky kfree(priv->msix_arr); 308290650Shselasky} 309290650Shselasky 310290650Shselaskystruct mlx5_reg_host_endianess { 311290650Shselasky u8 he; 312290650Shselasky u8 rsvd[15]; 313290650Shselasky}; 314290650Shselasky 315290650Shselasky 316290650Shselasky#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 317290650Shselasky 318290650Shselaskyenum { 319290650Shselasky MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 320306233Shselasky MLX5_DEV_CAP_FLAG_DCT | 321306233Shselasky MLX5_DEV_CAP_FLAG_DRAIN_SIGERR, 322290650Shselasky}; 323290650Shselasky 324353224Shselaskystatic u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 325290650Shselasky{ 326290650Shselasky switch (size) { 327290650Shselasky case 128: 328290650Shselasky return 0; 329290650Shselasky case 256: 330290650Shselasky return 1; 331290650Shselasky case 512: 332290650Shselasky return 2; 333290650Shselasky case 1024: 334290650Shselasky return 3; 335290650Shselasky case 2048: 336290650Shselasky return 4; 337290650Shselasky case 4096: 338290650Shselasky return 5; 339290650Shselasky default: 340353224Shselasky mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 341290650Shselasky return 0; 342290650Shselasky } 343290650Shselasky} 344290650Shselasky 345331807Shselaskystatic int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 346331807Shselasky enum mlx5_cap_type cap_type, 347331807Shselasky enum mlx5_cap_mode cap_mode) 348290650Shselasky{ 349290650Shselasky u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 350290650Shselasky int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 351290650Shselasky void *out, *hca_caps; 352290650Shselasky u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 353290650Shselasky int err; 354290650Shselasky 355290650Shselasky memset(in, 0, sizeof(in)); 356290650Shselasky out = kzalloc(out_sz, GFP_KERNEL); 357290650Shselasky 358290650Shselasky MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 359290650Shselasky MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 360290650Shselasky err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz); 361290650Shselasky if (err) { 362290650Shselasky mlx5_core_warn(dev, 363290650Shselasky "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 364290650Shselasky cap_type, cap_mode, err); 365290650Shselasky goto query_ex; 366290650Shselasky } 367290650Shselasky 368290650Shselasky hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 369290650Shselasky 370290650Shselasky switch (cap_mode) { 371290650Shselasky case HCA_CAP_OPMOD_GET_MAX: 372290650Shselasky memcpy(dev->hca_caps_max[cap_type], hca_caps, 373290650Shselasky MLX5_UN_SZ_BYTES(hca_cap_union)); 374290650Shselasky break; 375290650Shselasky case HCA_CAP_OPMOD_GET_CUR: 376290650Shselasky memcpy(dev->hca_caps_cur[cap_type], hca_caps, 377290650Shselasky MLX5_UN_SZ_BYTES(hca_cap_union)); 378290650Shselasky break; 379290650Shselasky default: 380290650Shselasky mlx5_core_warn(dev, 381290650Shselasky "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 382290650Shselasky cap_type, cap_mode); 383290650Shselasky err = -EINVAL; 384290650Shselasky break; 385290650Shselasky } 386290650Shselaskyquery_ex: 387290650Shselasky kfree(out); 388290650Shselasky return err; 389290650Shselasky} 390290650Shselasky 391331807Shselaskyint mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 392331807Shselasky{ 393331807Shselasky int ret; 394331807Shselasky 395331807Shselasky ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 396331807Shselasky if (ret) 397331807Shselasky return ret; 398331807Shselasky 399331807Shselasky return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 400331807Shselasky} 401331807Shselasky 402290650Shselaskystatic int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz) 403290650Shselasky{ 404331807Shselasky u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0}; 405290650Shselasky 406290650Shselasky MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 407290650Shselasky 408331807Shselasky return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out)); 409290650Shselasky} 410290650Shselasky 411290650Shselaskystatic int handle_hca_cap(struct mlx5_core_dev *dev) 412290650Shselasky{ 413290650Shselasky void *set_ctx = NULL; 414290650Shselasky struct mlx5_profile *prof = dev->profile; 415290650Shselasky int err = -ENOMEM; 416290650Shselasky int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 417290650Shselasky void *set_hca_cap; 418290650Shselasky 419290650Shselasky set_ctx = kzalloc(set_sz, GFP_KERNEL); 420290650Shselasky 421331807Shselasky err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 422290650Shselasky if (err) 423290650Shselasky goto query_ex; 424290650Shselasky 425290650Shselasky set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 426290650Shselasky capability); 427290650Shselasky memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL], 428290650Shselasky MLX5_ST_SZ_BYTES(cmd_hca_cap)); 429290650Shselasky 430290650Shselasky mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 431290650Shselasky mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 432290650Shselasky 128); 433290650Shselasky /* we limit the size of the pkey table to 128 entries for now */ 434290650Shselasky MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 435353224Shselasky to_fw_pkey_sz(dev, 128)); 436290650Shselasky 437290650Shselasky if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 438290650Shselasky MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 439290650Shselasky prof->log_max_qp); 440290650Shselasky 441290650Shselasky /* disable cmdif checksum */ 442290650Shselasky MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 443290650Shselasky 444306233Shselasky /* enable drain sigerr */ 445306233Shselasky MLX5_SET(cmd_hca_cap, set_hca_cap, drain_sigerr, 1); 446306233Shselasky 447290650Shselasky MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 448290650Shselasky 449290650Shselasky err = set_caps(dev, set_ctx, set_sz); 450290650Shselasky 451290650Shselaskyquery_ex: 452290650Shselasky kfree(set_ctx); 453290650Shselasky return err; 454290650Shselasky} 455290650Shselasky 456329209Shselaskystatic int handle_hca_cap_atomic(struct mlx5_core_dev *dev) 457329209Shselasky{ 458329209Shselasky void *set_ctx; 459329209Shselasky void *set_hca_cap; 460329209Shselasky int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 461329209Shselasky int req_endianness; 462329209Shselasky int err; 463329209Shselasky 464329209Shselasky if (MLX5_CAP_GEN(dev, atomic)) { 465331807Shselasky err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 466329209Shselasky if (err) 467329209Shselasky return err; 468329209Shselasky } else { 469329209Shselasky return 0; 470329209Shselasky } 471329209Shselasky 472329209Shselasky req_endianness = 473329209Shselasky MLX5_CAP_ATOMIC(dev, 474329209Shselasky supported_atomic_req_8B_endianess_mode_1); 475329209Shselasky 476329209Shselasky if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 477329209Shselasky return 0; 478329209Shselasky 479329209Shselasky set_ctx = kzalloc(set_sz, GFP_KERNEL); 480329209Shselasky if (!set_ctx) 481329209Shselasky return -ENOMEM; 482329209Shselasky 483329209Shselasky MLX5_SET(set_hca_cap_in, set_ctx, op_mod, 484329209Shselasky MLX5_SET_HCA_CAP_OP_MOD_ATOMIC << 1); 485329209Shselasky set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 486329209Shselasky 487329209Shselasky /* Set requestor to host endianness */ 488329209Shselasky MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode, 489329209Shselasky MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 490329209Shselasky 491329209Shselasky err = set_caps(dev, set_ctx, set_sz); 492329209Shselasky 493329209Shselasky kfree(set_ctx); 494329209Shselasky return err; 495329209Shselasky} 496329209Shselasky 497290650Shselaskystatic int set_hca_ctrl(struct mlx5_core_dev *dev) 498290650Shselasky{ 499290650Shselasky struct mlx5_reg_host_endianess he_in; 500290650Shselasky struct mlx5_reg_host_endianess he_out; 501290650Shselasky int err; 502290650Shselasky 503306233Shselasky if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH && 504306233Shselasky !MLX5_CAP_GEN(dev, roce)) 505306233Shselasky return 0; 506306233Shselasky 507290650Shselasky memset(&he_in, 0, sizeof(he_in)); 508290650Shselasky he_in.he = MLX5_SET_HOST_ENDIANNESS; 509290650Shselasky err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 510290650Shselasky &he_out, sizeof(he_out), 511290650Shselasky MLX5_REG_HOST_ENDIANNESS, 0, 1); 512290650Shselasky return err; 513290650Shselasky} 514290650Shselasky 515290650Shselaskystatic int mlx5_core_enable_hca(struct mlx5_core_dev *dev) 516290650Shselasky{ 517331807Shselasky u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0}; 518331807Shselasky u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0}; 519290650Shselasky 520290650Shselasky MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 521331807Shselasky return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); 522290650Shselasky} 523290650Shselasky 524290650Shselaskystatic int mlx5_core_disable_hca(struct mlx5_core_dev *dev) 525290650Shselasky{ 526331807Shselasky u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0}; 527331807Shselasky u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0}; 528290650Shselasky 529290650Shselasky MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 530331807Shselasky return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 531290650Shselasky} 532290650Shselasky 533290650Shselaskystatic int mlx5_core_set_issi(struct mlx5_core_dev *dev) 534290650Shselasky{ 535331807Shselasky u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0}; 536331807Shselasky u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0}; 537331807Shselasky u32 sup_issi; 538290650Shselasky int err; 539290650Shselasky 540290650Shselasky MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 541290650Shselasky 542331807Shselasky err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), query_out, sizeof(query_out)); 543290650Shselasky if (err) { 544331807Shselasky u32 syndrome; 545331807Shselasky u8 status; 546331807Shselasky 547331807Shselasky mlx5_cmd_mbox_status(query_out, &status, &syndrome); 548331807Shselasky if (status == MLX5_CMD_STAT_BAD_OP_ERR) { 549353224Shselasky mlx5_core_dbg(dev, "Only ISSI 0 is supported\n"); 550290650Shselasky return 0; 551290650Shselasky } 552290650Shselasky 553353224Shselasky mlx5_core_err(dev, "failed to query ISSI\n"); 554290650Shselasky return err; 555290650Shselasky } 556290650Shselasky 557290650Shselasky sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 558290650Shselasky 559290650Shselasky if (sup_issi & (1 << 1)) { 560331807Shselasky u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0}; 561331807Shselasky u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0}; 562290650Shselasky 563290650Shselasky MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 564290650Shselasky MLX5_SET(set_issi_in, set_in, current_issi, 1); 565290650Shselasky 566331807Shselasky err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), set_out, sizeof(set_out)); 567290650Shselasky if (err) { 568353224Shselasky mlx5_core_err(dev, "failed to set ISSI=1 err(%d)\n", err); 569290650Shselasky return err; 570290650Shselasky } 571290650Shselasky 572290650Shselasky dev->issi = 1; 573290650Shselasky 574290650Shselasky return 0; 575290650Shselasky } else if (sup_issi & (1 << 0)) { 576290650Shselasky return 0; 577290650Shselasky } 578290650Shselasky 579290650Shselasky return -ENOTSUPP; 580290650Shselasky} 581290650Shselasky 582290650Shselasky 583290650Shselaskyint mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn) 584290650Shselasky{ 585290650Shselasky struct mlx5_eq_table *table = &dev->priv.eq_table; 586290650Shselasky struct mlx5_eq *eq; 587290650Shselasky int err = -ENOENT; 588290650Shselasky 589290650Shselasky spin_lock(&table->lock); 590290650Shselasky list_for_each_entry(eq, &table->comp_eqs_list, list) { 591290650Shselasky if (eq->index == vector) { 592290650Shselasky *eqn = eq->eqn; 593290650Shselasky *irqn = eq->irqn; 594290650Shselasky err = 0; 595290650Shselasky break; 596290650Shselasky } 597290650Shselasky } 598290650Shselasky spin_unlock(&table->lock); 599290650Shselasky 600290650Shselasky return err; 601290650Shselasky} 602290650ShselaskyEXPORT_SYMBOL(mlx5_vector2eqn); 603290650Shselasky 604290650Shselaskystatic void free_comp_eqs(struct mlx5_core_dev *dev) 605290650Shselasky{ 606290650Shselasky struct mlx5_eq_table *table = &dev->priv.eq_table; 607290650Shselasky struct mlx5_eq *eq, *n; 608290650Shselasky 609290650Shselasky spin_lock(&table->lock); 610290650Shselasky list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { 611290650Shselasky list_del(&eq->list); 612290650Shselasky spin_unlock(&table->lock); 613290650Shselasky if (mlx5_destroy_unmap_eq(dev, eq)) 614290650Shselasky mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n", 615290650Shselasky eq->eqn); 616290650Shselasky kfree(eq); 617290650Shselasky spin_lock(&table->lock); 618290650Shselasky } 619290650Shselasky spin_unlock(&table->lock); 620290650Shselasky} 621290650Shselasky 622290650Shselaskystatic int alloc_comp_eqs(struct mlx5_core_dev *dev) 623290650Shselasky{ 624290650Shselasky struct mlx5_eq_table *table = &dev->priv.eq_table; 625290650Shselasky struct mlx5_eq *eq; 626290650Shselasky int ncomp_vec; 627290650Shselasky int nent; 628290650Shselasky int err; 629290650Shselasky int i; 630290650Shselasky 631290650Shselasky INIT_LIST_HEAD(&table->comp_eqs_list); 632290650Shselasky ncomp_vec = table->num_comp_vectors; 633290650Shselasky nent = MLX5_COMP_EQ_SIZE; 634290650Shselasky for (i = 0; i < ncomp_vec; i++) { 635290650Shselasky eq = kzalloc(sizeof(*eq), GFP_KERNEL); 636290650Shselasky 637290650Shselasky err = mlx5_create_map_eq(dev, eq, 638290650Shselasky i + MLX5_EQ_VEC_COMP_BASE, nent, 0, 639353199Shselasky &dev->priv.uuari.uars[0]); 640290650Shselasky if (err) { 641290650Shselasky kfree(eq); 642290650Shselasky goto clean; 643290650Shselasky } 644290650Shselasky mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn); 645290650Shselasky eq->index = i; 646290650Shselasky spin_lock(&table->lock); 647290650Shselasky list_add_tail(&eq->list, &table->comp_eqs_list); 648290650Shselasky spin_unlock(&table->lock); 649290650Shselasky } 650290650Shselasky 651290650Shselasky return 0; 652290650Shselasky 653290650Shselaskyclean: 654290650Shselasky free_comp_eqs(dev); 655290650Shselasky return err; 656290650Shselasky} 657290650Shselasky 658290650Shselaskystatic int map_bf_area(struct mlx5_core_dev *dev) 659290650Shselasky{ 660290650Shselasky resource_size_t bf_start = pci_resource_start(dev->pdev, 0); 661290650Shselasky resource_size_t bf_len = pci_resource_len(dev->pdev, 0); 662290650Shselasky 663290650Shselasky dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len); 664290650Shselasky 665290650Shselasky return dev->priv.bf_mapping ? 0 : -ENOMEM; 666290650Shselasky} 667290650Shselasky 668290650Shselaskystatic void unmap_bf_area(struct mlx5_core_dev *dev) 669290650Shselasky{ 670290650Shselasky if (dev->priv.bf_mapping) 671290650Shselasky io_mapping_free(dev->priv.bf_mapping); 672290650Shselasky} 673290650Shselasky 674290650Shselaskystatic inline int fw_initializing(struct mlx5_core_dev *dev) 675290650Shselasky{ 676290650Shselasky return ioread32be(&dev->iseg->initializing) >> 31; 677290650Shselasky} 678290650Shselasky 679353254Shselaskystatic int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 680353254Shselasky u32 warn_time_mili) 681290650Shselasky{ 682353254Shselasky int warn = jiffies + msecs_to_jiffies(warn_time_mili); 683353254Shselasky int end = jiffies + msecs_to_jiffies(max_wait_mili); 684290650Shselasky int err = 0; 685290650Shselasky 686353254Shselasky MPASS(max_wait_mili > warn_time_mili); 687353254Shselasky 688353254Shselasky while (fw_initializing(dev) == 1) { 689290650Shselasky if (time_after(jiffies, end)) { 690290650Shselasky err = -EBUSY; 691290650Shselasky break; 692290650Shselasky } 693353254Shselasky if (warn_time_mili && time_after(jiffies, warn)) { 694353254Shselasky mlx5_core_warn(dev, 695353254Shselasky "Waiting for FW initialization, timeout abort in %u s\n", 696353254Shselasky (unsigned int)(jiffies_to_msecs(end - warn) / 1000)); 697353254Shselasky warn = jiffies + msecs_to_jiffies(warn_time_mili); 698353254Shselasky } 699290650Shselasky msleep(FW_INIT_WAIT_MS); 700290650Shselasky } 701290650Shselasky 702353254Shselasky if (err != 0) 703353254Shselasky mlx5_core_dbg(dev, "Full initializing bit dword = 0x%x\n", 704353254Shselasky ioread32be(&dev->iseg->initializing)); 705353254Shselasky 706290650Shselasky return err; 707290650Shselasky} 708290650Shselasky 709331580Shselaskystatic void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv) 710290650Shselasky{ 711331580Shselasky struct mlx5_device_context *dev_ctx; 712331580Shselasky struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv); 713331580Shselasky 714331580Shselasky dev_ctx = kzalloc(sizeof(*dev_ctx), GFP_KERNEL); 715331580Shselasky if (!dev_ctx) 716331580Shselasky return; 717331580Shselasky 718331580Shselasky dev_ctx->intf = intf; 719331580Shselasky CURVNET_SET_QUIET(vnet0); 720331580Shselasky dev_ctx->context = intf->add(dev); 721331580Shselasky CURVNET_RESTORE(); 722331580Shselasky 723331580Shselasky if (dev_ctx->context) { 724331580Shselasky spin_lock_irq(&priv->ctx_lock); 725331580Shselasky list_add_tail(&dev_ctx->list, &priv->ctx_list); 726331580Shselasky spin_unlock_irq(&priv->ctx_lock); 727331580Shselasky } else { 728331580Shselasky kfree(dev_ctx); 729331580Shselasky } 730331580Shselasky} 731331580Shselasky 732331580Shselaskystatic void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv) 733331580Shselasky{ 734331580Shselasky struct mlx5_device_context *dev_ctx; 735331580Shselasky struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv); 736331580Shselasky 737331580Shselasky list_for_each_entry(dev_ctx, &priv->ctx_list, list) 738331580Shselasky if (dev_ctx->intf == intf) { 739331580Shselasky spin_lock_irq(&priv->ctx_lock); 740331580Shselasky list_del(&dev_ctx->list); 741331580Shselasky spin_unlock_irq(&priv->ctx_lock); 742331580Shselasky 743331580Shselasky intf->remove(dev, dev_ctx->context); 744331580Shselasky kfree(dev_ctx); 745331580Shselasky return; 746331580Shselasky } 747331580Shselasky} 748331580Shselasky 749341958Shselaskyint 750341958Shselaskymlx5_register_device(struct mlx5_core_dev *dev) 751331580Shselasky{ 752290650Shselasky struct mlx5_priv *priv = &dev->priv; 753331580Shselasky struct mlx5_interface *intf; 754290650Shselasky 755331580Shselasky mutex_lock(&intf_mutex); 756331580Shselasky list_add_tail(&priv->dev_list, &dev_list); 757331580Shselasky list_for_each_entry(intf, &intf_list, list) 758331580Shselasky mlx5_add_device(intf, priv); 759331580Shselasky mutex_unlock(&intf_mutex); 760331580Shselasky 761331580Shselasky return 0; 762331580Shselasky} 763331580Shselasky 764341958Shselaskyvoid 765341958Shselaskymlx5_unregister_device(struct mlx5_core_dev *dev) 766331580Shselasky{ 767331580Shselasky struct mlx5_priv *priv = &dev->priv; 768331580Shselasky struct mlx5_interface *intf; 769331580Shselasky 770331580Shselasky mutex_lock(&intf_mutex); 771331580Shselasky list_for_each_entry(intf, &intf_list, list) 772331580Shselasky mlx5_remove_device(intf, priv); 773331580Shselasky list_del(&priv->dev_list); 774331580Shselasky mutex_unlock(&intf_mutex); 775331580Shselasky} 776331580Shselasky 777331580Shselaskyint mlx5_register_interface(struct mlx5_interface *intf) 778331580Shselasky{ 779331580Shselasky struct mlx5_priv *priv; 780331580Shselasky 781331580Shselasky if (!intf->add || !intf->remove) 782331580Shselasky return -EINVAL; 783331580Shselasky 784331580Shselasky mutex_lock(&intf_mutex); 785331580Shselasky list_add_tail(&intf->list, &intf_list); 786331580Shselasky list_for_each_entry(priv, &dev_list, dev_list) 787331580Shselasky mlx5_add_device(intf, priv); 788331580Shselasky mutex_unlock(&intf_mutex); 789331580Shselasky 790331580Shselasky return 0; 791331580Shselasky} 792331580ShselaskyEXPORT_SYMBOL(mlx5_register_interface); 793331580Shselasky 794331580Shselaskyvoid mlx5_unregister_interface(struct mlx5_interface *intf) 795331580Shselasky{ 796331580Shselasky struct mlx5_priv *priv; 797331580Shselasky 798331580Shselasky mutex_lock(&intf_mutex); 799331580Shselasky list_for_each_entry(priv, &dev_list, dev_list) 800331580Shselasky mlx5_remove_device(intf, priv); 801331580Shselasky list_del(&intf->list); 802331580Shselasky mutex_unlock(&intf_mutex); 803331580Shselasky} 804331580ShselaskyEXPORT_SYMBOL(mlx5_unregister_interface); 805331580Shselasky 806331580Shselaskyvoid *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol) 807331580Shselasky{ 808331580Shselasky struct mlx5_priv *priv = &mdev->priv; 809331580Shselasky struct mlx5_device_context *dev_ctx; 810331580Shselasky unsigned long flags; 811331580Shselasky void *result = NULL; 812331580Shselasky 813331580Shselasky spin_lock_irqsave(&priv->ctx_lock, flags); 814331580Shselasky 815331580Shselasky list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list) 816331580Shselasky if ((dev_ctx->intf->protocol == protocol) && 817331580Shselasky dev_ctx->intf->get_dev) { 818331580Shselasky result = dev_ctx->intf->get_dev(dev_ctx->context); 819331580Shselasky break; 820331580Shselasky } 821331580Shselasky 822331580Shselasky spin_unlock_irqrestore(&priv->ctx_lock, flags); 823331580Shselasky 824331580Shselasky return result; 825331580Shselasky} 826331580ShselaskyEXPORT_SYMBOL(mlx5_get_protocol_dev); 827331580Shselasky 828347853Shselaskystatic int mlx5_auto_fw_update; 829347853ShselaskySYSCTL_INT(_hw_mlx5, OID_AUTO, auto_fw_update, CTLFLAG_RDTUN | CTLFLAG_NOFETCH, 830347853Shselasky &mlx5_auto_fw_update, 0, 831347853Shselasky "Allow automatic firmware update on driver start"); 832347847Shselaskystatic int 833347847Shselaskymlx5_firmware_update(struct mlx5_core_dev *dev) 834347847Shselasky{ 835347847Shselasky const struct firmware *fw; 836347847Shselasky int err; 837347847Shselasky 838347853Shselasky TUNABLE_INT_FETCH("hw.mlx5.auto_fw_update", &mlx5_auto_fw_update); 839347853Shselasky if (!mlx5_auto_fw_update) 840347853Shselasky return (0); 841347847Shselasky fw = firmware_get("mlx5fw_mfa"); 842347847Shselasky if (fw) { 843347847Shselasky err = mlx5_firmware_flash(dev, fw); 844347847Shselasky firmware_put(fw, FIRMWARE_UNLOAD); 845347847Shselasky } 846347847Shselasky else 847347847Shselasky return (-ENOENT); 848347847Shselasky 849347847Shselasky return err; 850347847Shselasky} 851347847Shselasky 852331580Shselaskystatic int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 853331580Shselasky{ 854331580Shselasky struct pci_dev *pdev = dev->pdev; 855331580Shselasky int err = 0; 856331580Shselasky 857290650Shselasky pci_set_drvdata(dev->pdev, dev); 858290650Shselasky strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN); 859290650Shselasky priv->name[MLX5_MAX_NAME_LEN - 1] = 0; 860290650Shselasky 861290650Shselasky mutex_init(&priv->pgdir_mutex); 862290650Shselasky INIT_LIST_HEAD(&priv->pgdir_list); 863290650Shselasky spin_lock_init(&priv->mkey_lock); 864290650Shselasky 865290650Shselasky priv->numa_node = NUMA_NO_NODE; 866290650Shselasky 867331580Shselasky err = mlx5_pci_enable_device(dev); 868290650Shselasky if (err) { 869353224Shselasky mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 870290650Shselasky goto err_dbg; 871290650Shselasky } 872290650Shselasky 873290650Shselasky err = request_bar(pdev); 874290650Shselasky if (err) { 875353224Shselasky mlx5_core_err(dev, "error requesting BARs, aborting\n"); 876290650Shselasky goto err_disable; 877290650Shselasky } 878290650Shselasky 879290650Shselasky pci_set_master(pdev); 880290650Shselasky 881290650Shselasky err = set_dma_caps(pdev); 882290650Shselasky if (err) { 883353224Shselasky mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 884290650Shselasky goto err_clr_master; 885290650Shselasky } 886290650Shselasky 887329212Shselasky dev->iseg_base = pci_resource_start(dev->pdev, 0); 888329212Shselasky dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 889290650Shselasky if (!dev->iseg) { 890290650Shselasky err = -ENOMEM; 891353224Shselasky mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 892290650Shselasky goto err_clr_master; 893290650Shselasky } 894331580Shselasky 895337105Shselasky return 0; 896331585Shselasky 897331580Shselaskyerr_clr_master: 898331580Shselasky release_bar(dev->pdev); 899331580Shselaskyerr_disable: 900331580Shselasky mlx5_pci_disable_device(dev); 901331580Shselaskyerr_dbg: 902331580Shselasky return err; 903331580Shselasky} 904331580Shselasky 905331580Shselaskystatic void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 906331580Shselasky{ 907331580Shselasky iounmap(dev->iseg); 908331580Shselasky release_bar(dev->pdev); 909331580Shselasky mlx5_pci_disable_device(dev); 910331580Shselasky} 911331580Shselasky 912331810Shselaskystatic int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 913331580Shselasky{ 914331580Shselasky int err; 915331580Shselasky 916337103Shselasky err = mlx5_vsc_find_cap(dev); 917337103Shselasky if (err) 918353224Shselasky mlx5_core_err(dev, "Unable to find vendor specific capabilities\n"); 919331815Shselasky 920331810Shselasky err = mlx5_query_hca_caps(dev); 921331810Shselasky if (err) { 922353224Shselasky mlx5_core_err(dev, "query hca failed\n"); 923331810Shselasky goto out; 924331810Shselasky } 925331810Shselasky 926331810Shselasky err = mlx5_query_board_id(dev); 927331810Shselasky if (err) { 928353224Shselasky mlx5_core_err(dev, "query board id failed\n"); 929331810Shselasky goto out; 930331810Shselasky } 931331810Shselasky 932331810Shselasky err = mlx5_eq_init(dev); 933331810Shselasky if (err) { 934353224Shselasky mlx5_core_err(dev, "failed to initialize eq\n"); 935331810Shselasky goto out; 936331810Shselasky } 937331810Shselasky 938331810Shselasky MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock); 939331810Shselasky 940331810Shselasky err = mlx5_init_cq_table(dev); 941331810Shselasky if (err) { 942353224Shselasky mlx5_core_err(dev, "failed to initialize cq table\n"); 943331810Shselasky goto err_eq_cleanup; 944331810Shselasky } 945331810Shselasky 946331810Shselasky mlx5_init_qp_table(dev); 947331810Shselasky mlx5_init_srq_table(dev); 948331810Shselasky mlx5_init_mr_table(dev); 949331810Shselasky 950341958Shselasky mlx5_init_reserved_gids(dev); 951341958Shselasky mlx5_fpga_init(dev); 952341958Shselasky 953331810Shselasky return 0; 954331810Shselasky 955331810Shselaskyerr_eq_cleanup: 956331810Shselasky mlx5_eq_cleanup(dev); 957331810Shselasky 958331810Shselaskyout: 959331810Shselasky return err; 960331810Shselasky} 961331810Shselasky 962331810Shselaskystatic void mlx5_cleanup_once(struct mlx5_core_dev *dev) 963331810Shselasky{ 964341958Shselasky mlx5_fpga_cleanup(dev); 965341958Shselasky mlx5_cleanup_reserved_gids(dev); 966331810Shselasky mlx5_cleanup_mr_table(dev); 967331810Shselasky mlx5_cleanup_srq_table(dev); 968331810Shselasky mlx5_cleanup_qp_table(dev); 969331810Shselasky mlx5_cleanup_cq_table(dev); 970331810Shselasky mlx5_eq_cleanup(dev); 971331810Shselasky} 972331810Shselasky 973331810Shselaskystatic int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, 974331810Shselasky bool boot) 975331810Shselasky{ 976331810Shselasky int err; 977331810Shselasky 978331580Shselasky mutex_lock(&dev->intf_state_mutex); 979331580Shselasky if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 980353224Shselasky mlx5_core_warn(dev, "interface is up, NOP\n"); 981331580Shselasky goto out; 982331580Shselasky } 983331580Shselasky 984353224Shselasky mlx5_core_dbg(dev, "firmware version: %d.%d.%d\n", 985353224Shselasky fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev)); 986290650Shselasky 987306233Shselasky /* 988306233Shselasky * On load removing any previous indication of internal error, 989306233Shselasky * device is up 990306233Shselasky */ 991306233Shselasky dev->state = MLX5_DEVICE_STATE_UP; 992306233Shselasky 993353254Shselasky /* wait for firmware to accept initialization segments configurations 994353254Shselasky */ 995353254Shselasky err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, 996353254Shselasky FW_INIT_WARN_MESSAGE_INTERVAL); 997353254Shselasky if (err) { 998353254Shselasky dev_err(&dev->pdev->dev, 999353254Shselasky "Firmware over %d MS in pre-initializing state, aborting\n", 1000353254Shselasky FW_PRE_INIT_TIMEOUT_MILI); 1001353254Shselasky goto out_err; 1002353254Shselasky } 1003353254Shselasky 1004290650Shselasky err = mlx5_cmd_init(dev); 1005290650Shselasky if (err) { 1006353254Shselasky mlx5_core_err(dev, 1007353254Shselasky "Failed initializing command interface, aborting\n"); 1008331580Shselasky goto out_err; 1009290650Shselasky } 1010290650Shselasky 1011353254Shselasky err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0); 1012290650Shselasky if (err) { 1013353254Shselasky mlx5_core_err(dev, 1014353254Shselasky "Firmware over %d MS in initializing state, aborting\n", 1015353254Shselasky FW_INIT_TIMEOUT_MILI); 1016290650Shselasky goto err_cmd_cleanup; 1017290650Shselasky } 1018290650Shselasky 1019290650Shselasky err = mlx5_core_enable_hca(dev); 1020290650Shselasky if (err) { 1021353224Shselasky mlx5_core_err(dev, "enable hca failed\n"); 1022331810Shselasky goto err_cmd_cleanup; 1023290650Shselasky } 1024290650Shselasky 1025290650Shselasky err = mlx5_core_set_issi(dev); 1026290650Shselasky if (err) { 1027353224Shselasky mlx5_core_err(dev, "failed to set issi\n"); 1028290650Shselasky goto err_disable_hca; 1029290650Shselasky } 1030290650Shselasky 1031290650Shselasky err = mlx5_pagealloc_start(dev); 1032290650Shselasky if (err) { 1033353224Shselasky mlx5_core_err(dev, "mlx5_pagealloc_start failed\n"); 1034290650Shselasky goto err_disable_hca; 1035290650Shselasky } 1036290650Shselasky 1037290650Shselasky err = mlx5_satisfy_startup_pages(dev, 1); 1038290650Shselasky if (err) { 1039353224Shselasky mlx5_core_err(dev, "failed to allocate boot pages\n"); 1040290650Shselasky goto err_pagealloc_stop; 1041290650Shselasky } 1042290650Shselasky 1043329209Shselasky err = set_hca_ctrl(dev); 1044329209Shselasky if (err) { 1045353224Shselasky mlx5_core_err(dev, "set_hca_ctrl failed\n"); 1046329209Shselasky goto reclaim_boot_pages; 1047329209Shselasky } 1048329209Shselasky 1049306233Shselasky err = handle_hca_cap(dev); 1050290650Shselasky if (err) { 1051353224Shselasky mlx5_core_err(dev, "handle_hca_cap failed\n"); 1052290650Shselasky goto reclaim_boot_pages; 1053290650Shselasky } 1054290650Shselasky 1055329209Shselasky err = handle_hca_cap_atomic(dev); 1056290650Shselasky if (err) { 1057353224Shselasky mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 1058290650Shselasky goto reclaim_boot_pages; 1059290650Shselasky } 1060290650Shselasky 1061290650Shselasky err = mlx5_satisfy_startup_pages(dev, 0); 1062290650Shselasky if (err) { 1063353224Shselasky mlx5_core_err(dev, "failed to allocate init pages\n"); 1064290650Shselasky goto reclaim_boot_pages; 1065290650Shselasky } 1066290650Shselasky 1067290650Shselasky err = mlx5_cmd_init_hca(dev); 1068290650Shselasky if (err) { 1069353224Shselasky mlx5_core_err(dev, "init hca failed\n"); 1070290650Shselasky goto reclaim_boot_pages; 1071290650Shselasky } 1072290650Shselasky 1073290650Shselasky mlx5_start_health_poll(dev); 1074290650Shselasky 1075331810Shselasky if (boot && mlx5_init_once(dev, priv)) { 1076353224Shselasky mlx5_core_err(dev, "sw objs init failed\n"); 1077290650Shselasky goto err_stop_poll; 1078290650Shselasky } 1079290650Shselasky 1080290650Shselasky err = mlx5_enable_msix(dev); 1081290650Shselasky if (err) { 1082353224Shselasky mlx5_core_err(dev, "enable msix failed\n"); 1083331810Shselasky goto err_cleanup_once; 1084290650Shselasky } 1085290650Shselasky 1086290650Shselasky err = mlx5_alloc_uuars(dev, &priv->uuari); 1087290650Shselasky if (err) { 1088353224Shselasky mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 1089331810Shselasky goto err_disable_msix; 1090290650Shselasky } 1091290650Shselasky 1092290650Shselasky err = mlx5_start_eqs(dev); 1093290650Shselasky if (err) { 1094353224Shselasky mlx5_core_err(dev, "Failed to start pages and async EQs\n"); 1095290650Shselasky goto err_free_uar; 1096290650Shselasky } 1097290650Shselasky 1098290650Shselasky err = alloc_comp_eqs(dev); 1099290650Shselasky if (err) { 1100353224Shselasky mlx5_core_err(dev, "Failed to alloc completion EQs\n"); 1101290650Shselasky goto err_stop_eqs; 1102290650Shselasky } 1103290650Shselasky 1104290650Shselasky if (map_bf_area(dev)) 1105353224Shselasky mlx5_core_err(dev, "Failed to map blue flame area\n"); 1106290650Shselasky 1107329200Shselasky err = mlx5_init_fs(dev); 1108329200Shselasky if (err) { 1109329200Shselasky mlx5_core_err(dev, "flow steering init %d\n", err); 1110331810Shselasky goto err_free_comp_eqs; 1111329200Shselasky } 1112329200Shselasky 1113353197Shselasky err = mlx5_mpfs_init(dev); 1114353197Shselasky if (err) { 1115353197Shselasky mlx5_core_err(dev, "mpfs init failed %d\n", err); 1116353197Shselasky goto err_fs; 1117353197Shselasky } 1118353197Shselasky 1119341958Shselasky err = mlx5_fpga_device_start(dev); 1120341958Shselasky if (err) { 1121353224Shselasky mlx5_core_err(dev, "fpga device start failed %d\n", err); 1122353197Shselasky goto err_mpfs; 1123341958Shselasky } 1124341958Shselasky 1125331580Shselasky err = mlx5_register_device(dev); 1126331580Shselasky if (err) { 1127353224Shselasky mlx5_core_err(dev, "mlx5_register_device failed %d\n", err); 1128353193Shselasky goto err_fpga; 1129331580Shselasky } 1130331580Shselasky 1131331580Shselasky set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1132331580Shselasky 1133331580Shselaskyout: 1134331580Shselasky mutex_unlock(&dev->intf_state_mutex); 1135290650Shselasky return 0; 1136290650Shselasky 1137353193Shselaskyerr_fpga: 1138353193Shselasky mlx5_fpga_device_stop(dev); 1139353193Shselasky 1140353197Shselaskyerr_mpfs: 1141353197Shselasky mlx5_mpfs_destroy(dev); 1142353197Shselasky 1143331810Shselaskyerr_fs: 1144331580Shselasky mlx5_cleanup_fs(dev); 1145331810Shselasky 1146331810Shselaskyerr_free_comp_eqs: 1147331810Shselasky free_comp_eqs(dev); 1148329200Shselasky unmap_bf_area(dev); 1149329200Shselasky 1150290650Shselaskyerr_stop_eqs: 1151290650Shselasky mlx5_stop_eqs(dev); 1152290650Shselasky 1153290650Shselaskyerr_free_uar: 1154290650Shselasky mlx5_free_uuars(dev, &priv->uuari); 1155290650Shselasky 1156331810Shselaskyerr_disable_msix: 1157290650Shselasky mlx5_disable_msix(dev); 1158290650Shselasky 1159331810Shselaskyerr_cleanup_once: 1160331810Shselasky if (boot) 1161331810Shselasky mlx5_cleanup_once(dev); 1162331810Shselasky 1163290650Shselaskyerr_stop_poll: 1164341934Shselasky mlx5_stop_health_poll(dev, boot); 1165290650Shselasky if (mlx5_cmd_teardown_hca(dev)) { 1166353224Shselasky mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1167331580Shselasky goto out_err; 1168290650Shselasky } 1169290650Shselasky 1170290650Shselaskyreclaim_boot_pages: 1171290650Shselasky mlx5_reclaim_startup_pages(dev); 1172290650Shselasky 1173290650Shselaskyerr_pagealloc_stop: 1174290650Shselasky mlx5_pagealloc_stop(dev); 1175290650Shselasky 1176290650Shselaskyerr_disable_hca: 1177290650Shselasky mlx5_core_disable_hca(dev); 1178290650Shselasky 1179290650Shselaskyerr_cmd_cleanup: 1180290650Shselasky mlx5_cmd_cleanup(dev); 1181290650Shselasky 1182331580Shselaskyout_err: 1183331580Shselasky dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1184331580Shselasky mutex_unlock(&dev->intf_state_mutex); 1185290650Shselasky 1186290650Shselasky return err; 1187290650Shselasky} 1188290650Shselasky 1189331810Shselaskystatic int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, 1190331810Shselasky bool cleanup) 1191290650Shselasky{ 1192331580Shselasky int err = 0; 1193290650Shselasky 1194331811Shselasky if (cleanup) 1195331811Shselasky mlx5_drain_health_recovery(dev); 1196331811Shselasky 1197331580Shselasky mutex_lock(&dev->intf_state_mutex); 1198347799Shselasky if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1199353224Shselasky mlx5_core_warn(dev, "%s: interface is down, NOP\n", __func__); 1200331810Shselasky if (cleanup) 1201331810Shselasky mlx5_cleanup_once(dev); 1202331580Shselasky goto out; 1203331580Shselasky } 1204331580Shselasky 1205331580Shselasky mlx5_unregister_device(dev); 1206331580Shselasky 1207341958Shselasky mlx5_fpga_device_stop(dev); 1208353197Shselasky mlx5_mpfs_destroy(dev); 1209329200Shselasky mlx5_cleanup_fs(dev); 1210290650Shselasky unmap_bf_area(dev); 1211322144Shselasky mlx5_wait_for_reclaim_vfs_pages(dev); 1212290650Shselasky free_comp_eqs(dev); 1213290650Shselasky mlx5_stop_eqs(dev); 1214290650Shselasky mlx5_free_uuars(dev, &priv->uuari); 1215290650Shselasky mlx5_disable_msix(dev); 1216331810Shselasky if (cleanup) 1217331810Shselasky mlx5_cleanup_once(dev); 1218341934Shselasky mlx5_stop_health_poll(dev, cleanup); 1219331580Shselasky err = mlx5_cmd_teardown_hca(dev); 1220331580Shselasky if (err) { 1221353224Shselasky mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1222331580Shselasky goto out; 1223290650Shselasky } 1224290650Shselasky mlx5_pagealloc_stop(dev); 1225290650Shselasky mlx5_reclaim_startup_pages(dev); 1226290650Shselasky mlx5_core_disable_hca(dev); 1227290650Shselasky mlx5_cmd_cleanup(dev); 1228290650Shselasky 1229331580Shselaskyout: 1230331580Shselasky clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1231331580Shselasky mutex_unlock(&dev->intf_state_mutex); 1232331580Shselasky return err; 1233290650Shselasky} 1234290650Shselasky 1235331580Shselaskyvoid mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event, 1236331580Shselasky unsigned long param) 1237290650Shselasky{ 1238290650Shselasky struct mlx5_priv *priv = &dev->priv; 1239290650Shselasky struct mlx5_device_context *dev_ctx; 1240290650Shselasky unsigned long flags; 1241290650Shselasky 1242290650Shselasky spin_lock_irqsave(&priv->ctx_lock, flags); 1243290650Shselasky 1244290650Shselasky list_for_each_entry(dev_ctx, &priv->ctx_list, list) 1245290650Shselasky if (dev_ctx->intf->event) 1246290650Shselasky dev_ctx->intf->event(dev, dev_ctx->context, event, param); 1247290650Shselasky 1248290650Shselasky spin_unlock_irqrestore(&priv->ctx_lock, flags); 1249290650Shselasky} 1250290650Shselasky 1251290650Shselaskystruct mlx5_core_event_handler { 1252290650Shselasky void (*event)(struct mlx5_core_dev *dev, 1253290650Shselasky enum mlx5_dev_event event, 1254290650Shselasky void *data); 1255290650Shselasky}; 1256290650Shselasky 1257353206Shselasky#define MLX5_STATS_DESC(a, b, c, d, e, ...) d, e, 1258353206Shselasky 1259353206Shselasky#define MLX5_PORT_MODULE_ERROR_STATS(m) \ 1260353206Shselaskym(+1, u64, power_budget_exceeded, "power_budget", "Module Power Budget Exceeded") \ 1261353206Shselaskym(+1, u64, long_range, "long_range", "Module Long Range for non MLNX cable/module") \ 1262353206Shselaskym(+1, u64, bus_stuck, "bus_stuck", "Module Bus stuck(I2C or data shorted)") \ 1263353206Shselaskym(+1, u64, no_eeprom, "no_eeprom", "No EEPROM/retry timeout") \ 1264353206Shselaskym(+1, u64, enforce_part_number, "enforce_part_number", "Module Enforce part number list") \ 1265353206Shselaskym(+1, u64, unknown_id, "unknown_id", "Module Unknown identifier") \ 1266353206Shselaskym(+1, u64, high_temp, "high_temp", "Module High Temperature") \ 1267353206Shselaskym(+1, u64, cable_shorted, "cable_shorted", "Module Cable is shorted") 1268353206Shselasky 1269353206Shselaskystatic const char *mlx5_pme_err_desc[] = { 1270353206Shselasky MLX5_PORT_MODULE_ERROR_STATS(MLX5_STATS_DESC) 1271353206Shselasky}; 1272353206Shselasky 1273290650Shselaskystatic int init_one(struct pci_dev *pdev, 1274290650Shselasky const struct pci_device_id *id) 1275290650Shselasky{ 1276290650Shselasky struct mlx5_core_dev *dev; 1277290650Shselasky struct mlx5_priv *priv; 1278338554Shselasky device_t bsddev = pdev->dev.bsddev; 1279353206Shselasky int i,err; 1280353206Shselasky struct sysctl_oid *pme_sysctl_node; 1281353206Shselasky struct sysctl_oid *pme_err_sysctl_node; 1282290650Shselasky 1283290650Shselasky dev = kzalloc(sizeof(*dev), GFP_KERNEL); 1284290650Shselasky priv = &dev->priv; 1285306233Shselasky if (id) 1286306233Shselasky priv->pci_dev_data = id->driver_data; 1287290650Shselasky 1288347835Shselasky if (mlx5_prof_sel < 0 || mlx5_prof_sel >= ARRAY_SIZE(profiles)) { 1289353224Shselasky device_printf(bsddev, 1290353224Shselasky "WARN: selected profile out of range, selecting default (%d)\n", 1291353224Shselasky MLX5_DEFAULT_PROF); 1292347835Shselasky mlx5_prof_sel = MLX5_DEFAULT_PROF; 1293290650Shselasky } 1294347835Shselasky dev->profile = &profiles[mlx5_prof_sel]; 1295331580Shselasky dev->pdev = pdev; 1296290650Shselasky dev->event = mlx5_core_event; 1297290650Shselasky 1298341948Shselasky /* Set desc */ 1299341948Shselasky device_set_desc(bsddev, mlx5_version); 1300341948Shselasky 1301338554Shselasky sysctl_ctx_init(&dev->sysctl_ctx); 1302338554Shselasky SYSCTL_ADD_INT(&dev->sysctl_ctx, 1303338554Shselasky SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1304338554Shselasky OID_AUTO, "msix_eqvec", CTLFLAG_RDTUN, &dev->msix_eqvec, 0, 1305338554Shselasky "Maximum number of MSIX event queue vectors, if set"); 1306347862Shselasky SYSCTL_ADD_INT(&dev->sysctl_ctx, 1307347862Shselasky SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1308347862Shselasky OID_AUTO, "power_status", CTLFLAG_RD, &dev->pwr_status, 0, 1309347862Shselasky "0:Invalid 1:Sufficient 2:Insufficient"); 1310347862Shselasky SYSCTL_ADD_INT(&dev->sysctl_ctx, 1311347862Shselasky SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1312347862Shselasky OID_AUTO, "power_value", CTLFLAG_RD, &dev->pwr_value, 0, 1313347862Shselasky "Current power value in Watts"); 1314338554Shselasky 1315353206Shselasky pme_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx, 1316353206Shselasky SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1317353206Shselasky OID_AUTO, "pme_stats", CTLFLAG_RD, NULL, 1318353206Shselasky "Port module event statistics"); 1319353206Shselasky if (pme_sysctl_node == NULL) { 1320353206Shselasky err = -ENOMEM; 1321353206Shselasky goto clean_sysctl_ctx; 1322353206Shselasky } 1323353206Shselasky pme_err_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx, 1324353206Shselasky SYSCTL_CHILDREN(pme_sysctl_node), 1325353206Shselasky OID_AUTO, "errors", CTLFLAG_RD, NULL, 1326353206Shselasky "Port module event error statistics"); 1327353206Shselasky if (pme_err_sysctl_node == NULL) { 1328353206Shselasky err = -ENOMEM; 1329353206Shselasky goto clean_sysctl_ctx; 1330353206Shselasky } 1331353206Shselasky SYSCTL_ADD_U64(&dev->sysctl_ctx, 1332353206Shselasky SYSCTL_CHILDREN(pme_sysctl_node), OID_AUTO, 1333353206Shselasky "module_plug", CTLFLAG_RD | CTLFLAG_MPSAFE, 1334353206Shselasky &dev->priv.pme_stats.status_counters[MLX5_MODULE_STATUS_PLUGGED_ENABLED], 1335353206Shselasky 0, "Number of time module plugged"); 1336353206Shselasky SYSCTL_ADD_U64(&dev->sysctl_ctx, 1337353206Shselasky SYSCTL_CHILDREN(pme_sysctl_node), OID_AUTO, 1338353206Shselasky "module_unplug", CTLFLAG_RD | CTLFLAG_MPSAFE, 1339353206Shselasky &dev->priv.pme_stats.status_counters[MLX5_MODULE_STATUS_UNPLUGGED], 1340353206Shselasky 0, "Number of time module unplugged"); 1341353206Shselasky for (i = 0 ; i < MLX5_MODULE_EVENT_ERROR_NUM; i++) { 1342353206Shselasky SYSCTL_ADD_U64(&dev->sysctl_ctx, 1343353206Shselasky SYSCTL_CHILDREN(pme_err_sysctl_node), OID_AUTO, 1344353206Shselasky mlx5_pme_err_desc[2 * i], CTLFLAG_RD | CTLFLAG_MPSAFE, 1345353206Shselasky &dev->priv.pme_stats.error_counters[i], 1346353206Shselasky 0, mlx5_pme_err_desc[2 * i + 1]); 1347353206Shselasky } 1348353206Shselasky 1349353206Shselasky 1350290650Shselasky INIT_LIST_HEAD(&priv->ctx_list); 1351290650Shselasky spin_lock_init(&priv->ctx_lock); 1352341930Shselasky mutex_init(&dev->pci_status_mutex); 1353341930Shselasky mutex_init(&dev->intf_state_mutex); 1354347880Shselasky mtx_init(&dev->dump_lock, "mlx5dmp", NULL, MTX_DEF | MTX_NEW); 1355331580Shselasky err = mlx5_pci_init(dev, priv); 1356290650Shselasky if (err) { 1357353224Shselasky mlx5_core_err(dev, "mlx5_pci_init failed %d\n", err); 1358331580Shselasky goto clean_dev; 1359290650Shselasky } 1360290650Shselasky 1361341930Shselasky err = mlx5_health_init(dev); 1362341930Shselasky if (err) { 1363353224Shselasky mlx5_core_err(dev, "mlx5_health_init failed %d\n", err); 1364341930Shselasky goto close_pci; 1365341930Shselasky } 1366331580Shselasky 1367331810Shselasky mlx5_pagealloc_init(dev); 1368331810Shselasky 1369331810Shselasky err = mlx5_load_one(dev, priv, true); 1370290650Shselasky if (err) { 1371353224Shselasky mlx5_core_err(dev, "mlx5_load_one failed %d\n", err); 1372331580Shselasky goto clean_health; 1373290650Shselasky } 1374290650Shselasky 1375331914Shselasky mlx5_fwdump_prep(dev); 1376331914Shselasky 1377347847Shselasky mlx5_firmware_update(dev); 1378347847Shselasky 1379341930Shselasky pci_save_state(bsddev); 1380290650Shselasky return 0; 1381290650Shselasky 1382331580Shselaskyclean_health: 1383331810Shselasky mlx5_pagealloc_cleanup(dev); 1384341930Shselasky mlx5_health_cleanup(dev); 1385331580Shselaskyclose_pci: 1386341930Shselasky mlx5_pci_close(dev, priv); 1387331580Shselaskyclean_dev: 1388353206Shselasky mtx_destroy(&dev->dump_lock); 1389353206Shselaskyclean_sysctl_ctx: 1390338554Shselasky sysctl_ctx_free(&dev->sysctl_ctx); 1391290650Shselasky kfree(dev); 1392290650Shselasky return err; 1393290650Shselasky} 1394290650Shselasky 1395290650Shselaskystatic void remove_one(struct pci_dev *pdev) 1396290650Shselasky{ 1397290650Shselasky struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1398331580Shselasky struct mlx5_priv *priv = &dev->priv; 1399290650Shselasky 1400331810Shselasky if (mlx5_unload_one(dev, priv, true)) { 1401353224Shselasky mlx5_core_err(dev, "mlx5_unload_one failed\n"); 1402331580Shselasky mlx5_health_cleanup(dev); 1403331580Shselasky return; 1404331580Shselasky } 1405331580Shselasky 1406331810Shselasky mlx5_pagealloc_cleanup(dev); 1407331580Shselasky mlx5_health_cleanup(dev); 1408347880Shselasky mlx5_fwdump_clean(dev); 1409331580Shselasky mlx5_pci_close(dev, priv); 1410347880Shselasky mtx_destroy(&dev->dump_lock); 1411331580Shselasky pci_set_drvdata(pdev, NULL); 1412338554Shselasky sysctl_ctx_free(&dev->sysctl_ctx); 1413290650Shselasky kfree(dev); 1414290650Shselasky} 1415290650Shselasky 1416331580Shselaskystatic pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 1417331580Shselasky pci_channel_state_t state) 1418331580Shselasky{ 1419331580Shselasky struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1420331580Shselasky struct mlx5_priv *priv = &dev->priv; 1421331580Shselasky 1422353224Shselasky mlx5_core_info(dev, "%s was called\n", __func__); 1423331810Shselasky mlx5_enter_error_state(dev, false); 1424331810Shselasky mlx5_unload_one(dev, priv, false); 1425331914Shselasky 1426331582Shselasky if (state) { 1427331582Shselasky mlx5_drain_health_wq(dev); 1428331582Shselasky mlx5_pci_disable_device(dev); 1429331582Shselasky } 1430331582Shselasky 1431331580Shselasky return state == pci_channel_io_perm_failure ? 1432331580Shselasky PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 1433331580Shselasky} 1434331580Shselasky 1435331580Shselaskystatic pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 1436331580Shselasky{ 1437331580Shselasky struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1438331580Shselasky int err = 0; 1439331580Shselasky 1440353224Shselasky mlx5_core_info(dev,"%s was called\n", __func__); 1441331580Shselasky 1442331580Shselasky err = mlx5_pci_enable_device(dev); 1443331580Shselasky if (err) { 1444353224Shselasky mlx5_core_err(dev, "mlx5_pci_enable_device failed with error code: %d\n" 1445353224Shselasky ,err); 1446331580Shselasky return PCI_ERS_RESULT_DISCONNECT; 1447331580Shselasky } 1448331580Shselasky pci_set_master(pdev); 1449331580Shselasky pci_set_powerstate(pdev->dev.bsddev, PCI_POWERSTATE_D0); 1450331580Shselasky pci_restore_state(pdev->dev.bsddev); 1451331816Shselasky pci_save_state(pdev->dev.bsddev); 1452331580Shselasky 1453331580Shselasky return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; 1454331580Shselasky} 1455331580Shselasky 1456331580Shselasky/* wait for the device to show vital signs. For now we check 1457331580Shselasky * that we can read the device ID and that the health buffer 1458331580Shselasky * shows a non zero value which is different than 0xffffffff 1459331580Shselasky */ 1460331580Shselaskystatic void wait_vital(struct pci_dev *pdev) 1461331580Shselasky{ 1462331580Shselasky struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1463331580Shselasky struct mlx5_core_health *health = &dev->priv.health; 1464331580Shselasky const int niter = 100; 1465331580Shselasky u32 count; 1466331580Shselasky u16 did; 1467331580Shselasky int i; 1468331580Shselasky 1469331580Shselasky /* Wait for firmware to be ready after reset */ 1470331580Shselasky msleep(1000); 1471331580Shselasky for (i = 0; i < niter; i++) { 1472331580Shselasky if (pci_read_config_word(pdev, 2, &did)) { 1473353224Shselasky mlx5_core_warn(dev, "failed reading config word\n"); 1474331580Shselasky break; 1475331580Shselasky } 1476331580Shselasky if (did == pdev->device) { 1477353224Shselasky mlx5_core_info(dev, 1478353224Shselasky "device ID correctly read after %d iterations\n", i); 1479331580Shselasky break; 1480331580Shselasky } 1481331580Shselasky msleep(50); 1482331580Shselasky } 1483331580Shselasky if (i == niter) 1484353224Shselasky mlx5_core_warn(dev, "could not read device ID\n"); 1485331580Shselasky 1486331580Shselasky for (i = 0; i < niter; i++) { 1487331580Shselasky count = ioread32be(health->health_counter); 1488331580Shselasky if (count && count != 0xffffffff) { 1489353224Shselasky mlx5_core_info(dev, 1490353224Shselasky "Counter value 0x%x after %d iterations\n", count, i); 1491331580Shselasky break; 1492331580Shselasky } 1493331580Shselasky msleep(50); 1494331580Shselasky } 1495331580Shselasky 1496331580Shselasky if (i == niter) 1497353224Shselasky mlx5_core_warn(dev, "could not read device ID\n"); 1498331580Shselasky} 1499331580Shselasky 1500331580Shselaskystatic void mlx5_pci_resume(struct pci_dev *pdev) 1501331580Shselasky{ 1502331580Shselasky struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1503331580Shselasky struct mlx5_priv *priv = &dev->priv; 1504331580Shselasky int err; 1505331580Shselasky 1506353224Shselasky mlx5_core_info(dev,"%s was called\n", __func__); 1507331580Shselasky 1508331580Shselasky wait_vital(pdev); 1509331580Shselasky 1510331810Shselasky err = mlx5_load_one(dev, priv, false); 1511331580Shselasky if (err) 1512353224Shselasky mlx5_core_err(dev, 1513353224Shselasky "mlx5_load_one failed with error code: %d\n" ,err); 1514331580Shselasky else 1515353224Shselasky mlx5_core_info(dev,"device recovered\n"); 1516331580Shselasky} 1517331580Shselasky 1518331580Shselaskystatic const struct pci_error_handlers mlx5_err_handler = { 1519331580Shselasky .error_detected = mlx5_pci_err_detected, 1520331580Shselasky .slot_reset = mlx5_pci_slot_reset, 1521331580Shselasky .resume = mlx5_pci_resume 1522331580Shselasky}; 1523331580Shselasky 1524331810Shselaskystatic int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 1525331810Shselasky{ 1526347818Shselasky bool fast_teardown, force_teardown; 1527331810Shselasky int err; 1528331810Shselasky 1529347819Shselasky if (!mlx5_fast_unload_enabled) { 1530347819Shselasky mlx5_core_dbg(dev, "fast unload is disabled by user\n"); 1531347819Shselasky return -EOPNOTSUPP; 1532347819Shselasky } 1533347819Shselasky 1534347818Shselasky fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1535347818Shselasky force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1536347818Shselasky 1537347818Shselasky mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1538347818Shselasky mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1539347818Shselasky 1540347818Shselasky if (!fast_teardown && !force_teardown) 1541331810Shselasky return -EOPNOTSUPP; 1542331810Shselasky 1543331810Shselasky if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1544331810Shselasky mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 1545331810Shselasky return -EAGAIN; 1546331810Shselasky } 1547331810Shselasky 1548341934Shselasky /* Panic tear down fw command will stop the PCI bus communication 1549341934Shselasky * with the HCA, so the health polll is no longer needed. 1550341934Shselasky */ 1551341934Shselasky mlx5_drain_health_wq(dev); 1552341934Shselasky mlx5_stop_health_poll(dev, false); 1553341934Shselasky 1554347818Shselasky err = mlx5_cmd_fast_teardown_hca(dev); 1555347818Shselasky if (!err) 1556347818Shselasky goto done; 1557347818Shselasky 1558331810Shselasky err = mlx5_cmd_force_teardown_hca(dev); 1559347818Shselasky if (!err) 1560347818Shselasky goto done; 1561331810Shselasky 1562347818Shselasky mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", err); 1563347818Shselasky mlx5_start_health_poll(dev); 1564347818Shselasky return err; 1565347818Shselaskydone: 1566331810Shselasky mlx5_enter_error_state(dev, true); 1567331810Shselasky return 0; 1568331810Shselasky} 1569331810Shselasky 1570347802Shselaskystatic void mlx5_disable_interrupts(struct mlx5_core_dev *mdev) 1571347802Shselasky{ 1572347802Shselasky int nvec = mdev->priv.eq_table.num_comp_vectors + MLX5_EQ_VEC_COMP_BASE; 1573347802Shselasky int x; 1574347802Shselasky 1575347802Shselasky mdev->priv.disable_irqs = 1; 1576347802Shselasky 1577347802Shselasky /* wait for all IRQ handlers to finish processing */ 1578347802Shselasky for (x = 0; x != nvec; x++) 1579347802Shselasky synchronize_irq(mdev->priv.msix_arr[x].vector); 1580347802Shselasky} 1581347802Shselasky 1582329211Shselaskystatic void shutdown_one(struct pci_dev *pdev) 1583329211Shselasky{ 1584331580Shselasky struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1585331580Shselasky struct mlx5_priv *priv = &dev->priv; 1586331810Shselasky int err; 1587331580Shselasky 1588347802Shselasky /* enter polling mode */ 1589347802Shselasky mlx5_cmd_use_polling(dev); 1590347802Shselasky 1591347802Shselasky /* disable all interrupts */ 1592347802Shselasky mlx5_disable_interrupts(dev); 1593347802Shselasky 1594331810Shselasky err = mlx5_try_fast_unload(dev); 1595331810Shselasky if (err) 1596331810Shselasky mlx5_unload_one(dev, priv, false); 1597331580Shselasky mlx5_pci_disable_device(dev); 1598329211Shselasky} 1599329211Shselasky 1600290650Shselaskystatic const struct pci_device_id mlx5_core_pci_table[] = { 1601290650Shselasky { PCI_VDEVICE(MELLANOX, 4113) }, /* Connect-IB */ 1602290650Shselasky { PCI_VDEVICE(MELLANOX, 4114) }, /* Connect-IB VF */ 1603290650Shselasky { PCI_VDEVICE(MELLANOX, 4115) }, /* ConnectX-4 */ 1604290650Shselasky { PCI_VDEVICE(MELLANOX, 4116) }, /* ConnectX-4 VF */ 1605290650Shselasky { PCI_VDEVICE(MELLANOX, 4117) }, /* ConnectX-4LX */ 1606290650Shselasky { PCI_VDEVICE(MELLANOX, 4118) }, /* ConnectX-4LX VF */ 1607306233Shselasky { PCI_VDEVICE(MELLANOX, 4119) }, /* ConnectX-5 */ 1608306233Shselasky { PCI_VDEVICE(MELLANOX, 4120) }, /* ConnectX-5 VF */ 1609290650Shselasky { PCI_VDEVICE(MELLANOX, 4121) }, 1610290650Shselasky { PCI_VDEVICE(MELLANOX, 4122) }, 1611290650Shselasky { PCI_VDEVICE(MELLANOX, 4123) }, 1612290650Shselasky { PCI_VDEVICE(MELLANOX, 4124) }, 1613290650Shselasky { PCI_VDEVICE(MELLANOX, 4125) }, 1614290650Shselasky { PCI_VDEVICE(MELLANOX, 4126) }, 1615290650Shselasky { PCI_VDEVICE(MELLANOX, 4127) }, 1616290650Shselasky { PCI_VDEVICE(MELLANOX, 4128) }, 1617290650Shselasky { PCI_VDEVICE(MELLANOX, 4129) }, 1618290650Shselasky { PCI_VDEVICE(MELLANOX, 4130) }, 1619290650Shselasky { PCI_VDEVICE(MELLANOX, 4131) }, 1620290650Shselasky { PCI_VDEVICE(MELLANOX, 4132) }, 1621290650Shselasky { PCI_VDEVICE(MELLANOX, 4133) }, 1622290650Shselasky { PCI_VDEVICE(MELLANOX, 4134) }, 1623290650Shselasky { PCI_VDEVICE(MELLANOX, 4135) }, 1624290650Shselasky { PCI_VDEVICE(MELLANOX, 4136) }, 1625290650Shselasky { PCI_VDEVICE(MELLANOX, 4137) }, 1626290650Shselasky { PCI_VDEVICE(MELLANOX, 4138) }, 1627290650Shselasky { PCI_VDEVICE(MELLANOX, 4139) }, 1628290650Shselasky { PCI_VDEVICE(MELLANOX, 4140) }, 1629290650Shselasky { PCI_VDEVICE(MELLANOX, 4141) }, 1630290650Shselasky { PCI_VDEVICE(MELLANOX, 4142) }, 1631290650Shselasky { PCI_VDEVICE(MELLANOX, 4143) }, 1632290650Shselasky { PCI_VDEVICE(MELLANOX, 4144) }, 1633290650Shselasky { 0, } 1634290650Shselasky}; 1635290650Shselasky 1636290650ShselaskyMODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 1637290650Shselasky 1638331809Shselaskyvoid mlx5_disable_device(struct mlx5_core_dev *dev) 1639331809Shselasky{ 1640331809Shselasky mlx5_pci_err_detected(dev->pdev, 0); 1641331809Shselasky} 1642331809Shselasky 1643331809Shselaskyvoid mlx5_recover_device(struct mlx5_core_dev *dev) 1644331809Shselasky{ 1645331809Shselasky mlx5_pci_disable_device(dev); 1646331809Shselasky if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) 1647331809Shselasky mlx5_pci_resume(dev->pdev); 1648331809Shselasky} 1649331809Shselasky 1650331586Shselaskystruct pci_driver mlx5_core_driver = { 1651290650Shselasky .name = DRIVER_NAME, 1652290650Shselasky .id_table = mlx5_core_pci_table, 1653329211Shselasky .shutdown = shutdown_one, 1654290650Shselasky .probe = init_one, 1655331580Shselasky .remove = remove_one, 1656331580Shselasky .err_handler = &mlx5_err_handler 1657290650Shselasky}; 1658290650Shselasky 1659290650Shselaskystatic int __init init(void) 1660290650Shselasky{ 1661290650Shselasky int err; 1662290650Shselasky 1663290650Shselasky err = pci_register_driver(&mlx5_core_driver); 1664290650Shselasky if (err) 1665331580Shselasky goto err_debug; 1666290650Shselasky 1667347871Shselasky err = mlx5_ctl_init(); 1668331586Shselasky if (err) 1669347871Shselasky goto err_ctl; 1670331586Shselasky 1671331586Shselasky return 0; 1672331586Shselasky 1673347871Shselaskyerr_ctl: 1674331586Shselasky pci_unregister_driver(&mlx5_core_driver); 1675290650Shselasky 1676290650Shselaskyerr_debug: 1677290650Shselasky return err; 1678290650Shselasky} 1679290650Shselasky 1680290650Shselaskystatic void __exit cleanup(void) 1681290650Shselasky{ 1682347871Shselasky mlx5_ctl_fini(); 1683290650Shselasky pci_unregister_driver(&mlx5_core_driver); 1684290650Shselasky} 1685290650Shselasky 1686290650Shselaskymodule_init(init); 1687290650Shselaskymodule_exit(cleanup); 1688