mlx5_main.c revision 353189
1290650Shselasky/*- 2347819Shselasky * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved. 3290650Shselasky * 4290650Shselasky * Redistribution and use in source and binary forms, with or without 5290650Shselasky * modification, are permitted provided that the following conditions 6290650Shselasky * are met: 7290650Shselasky * 1. Redistributions of source code must retain the above copyright 8290650Shselasky * notice, this list of conditions and the following disclaimer. 9290650Shselasky * 2. Redistributions in binary form must reproduce the above copyright 10290650Shselasky * notice, this list of conditions and the following disclaimer in the 11290650Shselasky * documentation and/or other materials provided with the distribution. 12290650Shselasky * 13290650Shselasky * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14290650Shselasky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15290650Shselasky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16290650Shselasky * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17290650Shselasky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18290650Shselasky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19290650Shselasky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20290650Shselasky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21290650Shselasky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22290650Shselasky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23290650Shselasky * SUCH DAMAGE. 24290650Shselasky * 25290650Shselasky * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_core/mlx5_main.c 353189 2019-10-07 08:40:34Z hselasky $ 26290650Shselasky */ 27290650Shselasky 28290650Shselasky#include <linux/kmod.h> 29290650Shselasky#include <linux/module.h> 30290650Shselasky#include <linux/errno.h> 31290650Shselasky#include <linux/pci.h> 32290650Shselasky#include <linux/dma-mapping.h> 33290650Shselasky#include <linux/slab.h> 34290650Shselasky#include <linux/io-mapping.h> 35290650Shselasky#include <linux/interrupt.h> 36347802Shselasky#include <linux/hardirq.h> 37290650Shselasky#include <dev/mlx5/driver.h> 38290650Shselasky#include <dev/mlx5/cq.h> 39290650Shselasky#include <dev/mlx5/qp.h> 40290650Shselasky#include <dev/mlx5/srq.h> 41290650Shselasky#include <linux/delay.h> 42290650Shselasky#include <dev/mlx5/mlx5_ifc.h> 43341958Shselasky#include <dev/mlx5/mlx5_fpga/core.h> 44341958Shselasky#include <dev/mlx5/mlx5_lib/mlx5.h> 45290650Shselasky#include "mlx5_core.h" 46329200Shselasky#include "fs_core.h" 47290650Shselasky 48341948Shselaskystatic const char mlx5_version[] = "Mellanox Core driver " 49341948Shselasky DRIVER_VERSION " (" DRIVER_RELDATE ")"; 50290650ShselaskyMODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 51290650ShselaskyMODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver"); 52290650ShselaskyMODULE_LICENSE("Dual BSD/GPL"); 53290650ShselaskyMODULE_DEPEND(mlx5, linuxkpi, 1, 1, 1); 54347839ShselaskyMODULE_DEPEND(mlx5, mlxfw, 1, 1, 1); 55347847ShselaskyMODULE_DEPEND(mlx5, firmware, 1, 1, 1); 56290650ShselaskyMODULE_VERSION(mlx5, 1); 57290650Shselasky 58347835ShselaskySYSCTL_NODE(_hw, OID_AUTO, mlx5, CTLFLAG_RW, 0, "mlx5 hardware controls"); 59347835Shselasky 60290650Shselaskyint mlx5_core_debug_mask; 61347835ShselaskySYSCTL_INT(_hw_mlx5, OID_AUTO, debug_mask, CTLFLAG_RWTUN, 62347835Shselasky &mlx5_core_debug_mask, 0, 63347835Shselasky "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 64290650Shselasky 65290650Shselasky#define MLX5_DEFAULT_PROF 2 66347835Shselaskystatic int mlx5_prof_sel = MLX5_DEFAULT_PROF; 67347835ShselaskySYSCTL_INT(_hw_mlx5, OID_AUTO, prof_sel, CTLFLAG_RWTUN, 68347835Shselasky &mlx5_prof_sel, 0, 69347835Shselasky "profile selector. Valid range 0 - 2"); 70290650Shselasky 71347819Shselaskystatic int mlx5_fast_unload_enabled = 1; 72347819ShselaskySYSCTL_INT(_hw_mlx5, OID_AUTO, fast_unload_enabled, CTLFLAG_RWTUN, 73347819Shselasky &mlx5_fast_unload_enabled, 0, 74347819Shselasky "Set to enable fast unload. Clear to disable."); 75347819Shselasky 76290650Shselasky#define NUMA_NO_NODE -1 77290650Shselasky 78290650Shselaskystatic LIST_HEAD(intf_list); 79290650Shselaskystatic LIST_HEAD(dev_list); 80290650Shselaskystatic DEFINE_MUTEX(intf_mutex); 81290650Shselasky 82290650Shselaskystruct mlx5_device_context { 83290650Shselasky struct list_head list; 84290650Shselasky struct mlx5_interface *intf; 85290650Shselasky void *context; 86290650Shselasky}; 87290650Shselasky 88329209Shselaskyenum { 89329209Shselasky MLX5_ATOMIC_REQ_MODE_BE = 0x0, 90329209Shselasky MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 91329209Shselasky}; 92329209Shselasky 93290650Shselaskystatic struct mlx5_profile profiles[] = { 94290650Shselasky [0] = { 95290650Shselasky .mask = 0, 96290650Shselasky }, 97290650Shselasky [1] = { 98290650Shselasky .mask = MLX5_PROF_MASK_QP_SIZE, 99290650Shselasky .log_max_qp = 12, 100290650Shselasky }, 101290650Shselasky [2] = { 102290650Shselasky .mask = MLX5_PROF_MASK_QP_SIZE | 103290650Shselasky MLX5_PROF_MASK_MR_CACHE, 104290650Shselasky .log_max_qp = 17, 105290650Shselasky .mr_cache[0] = { 106290650Shselasky .size = 500, 107290650Shselasky .limit = 250 108290650Shselasky }, 109290650Shselasky .mr_cache[1] = { 110290650Shselasky .size = 500, 111290650Shselasky .limit = 250 112290650Shselasky }, 113290650Shselasky .mr_cache[2] = { 114290650Shselasky .size = 500, 115290650Shselasky .limit = 250 116290650Shselasky }, 117290650Shselasky .mr_cache[3] = { 118290650Shselasky .size = 500, 119290650Shselasky .limit = 250 120290650Shselasky }, 121290650Shselasky .mr_cache[4] = { 122290650Shselasky .size = 500, 123290650Shselasky .limit = 250 124290650Shselasky }, 125290650Shselasky .mr_cache[5] = { 126290650Shselasky .size = 500, 127290650Shselasky .limit = 250 128290650Shselasky }, 129290650Shselasky .mr_cache[6] = { 130290650Shselasky .size = 500, 131290650Shselasky .limit = 250 132290650Shselasky }, 133290650Shselasky .mr_cache[7] = { 134290650Shselasky .size = 500, 135290650Shselasky .limit = 250 136290650Shselasky }, 137290650Shselasky .mr_cache[8] = { 138290650Shselasky .size = 500, 139290650Shselasky .limit = 250 140290650Shselasky }, 141290650Shselasky .mr_cache[9] = { 142290650Shselasky .size = 500, 143290650Shselasky .limit = 250 144290650Shselasky }, 145290650Shselasky .mr_cache[10] = { 146290650Shselasky .size = 500, 147290650Shselasky .limit = 250 148290650Shselasky }, 149290650Shselasky .mr_cache[11] = { 150290650Shselasky .size = 500, 151290650Shselasky .limit = 250 152290650Shselasky }, 153290650Shselasky .mr_cache[12] = { 154290650Shselasky .size = 64, 155290650Shselasky .limit = 32 156290650Shselasky }, 157290650Shselasky .mr_cache[13] = { 158290650Shselasky .size = 32, 159290650Shselasky .limit = 16 160290650Shselasky }, 161290650Shselasky .mr_cache[14] = { 162290650Shselasky .size = 16, 163290650Shselasky .limit = 8 164290650Shselasky }, 165290650Shselasky }, 166290650Shselasky [3] = { 167290650Shselasky .mask = MLX5_PROF_MASK_QP_SIZE, 168290650Shselasky .log_max_qp = 17, 169290650Shselasky }, 170290650Shselasky}; 171290650Shselasky 172290650Shselaskystatic int set_dma_caps(struct pci_dev *pdev) 173290650Shselasky{ 174290650Shselasky int err; 175290650Shselasky 176290650Shselasky err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 177290650Shselasky if (err) { 178290650Shselasky device_printf((&pdev->dev)->bsddev, "WARN: ""Warning: couldn't set 64-bit PCI DMA mask\n"); 179290650Shselasky err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 180290650Shselasky if (err) { 181290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""Can't set PCI DMA mask, aborting\n"); 182290650Shselasky return err; 183290650Shselasky } 184290650Shselasky } 185290650Shselasky 186290650Shselasky err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 187290650Shselasky if (err) { 188290650Shselasky device_printf((&pdev->dev)->bsddev, "WARN: ""Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 189290650Shselasky err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 190290650Shselasky if (err) { 191290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""Can't set consistent PCI DMA mask, aborting\n"); 192290650Shselasky return err; 193290650Shselasky } 194290650Shselasky } 195290650Shselasky 196290650Shselasky dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 197290650Shselasky return err; 198290650Shselasky} 199290650Shselasky 200347862Shselaskyint mlx5_pci_read_power_status(struct mlx5_core_dev *dev, 201347862Shselasky u16 *p_power, u8 *p_status) 202347862Shselasky{ 203347862Shselasky u32 in[MLX5_ST_SZ_DW(mpein_reg)] = {}; 204347862Shselasky u32 out[MLX5_ST_SZ_DW(mpein_reg)] = {}; 205347862Shselasky int err; 206347862Shselasky 207347862Shselasky err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), 208347862Shselasky MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN, 0, 0); 209347862Shselasky 210347862Shselasky *p_status = MLX5_GET(mpein_reg, out, pwr_status); 211347862Shselasky *p_power = MLX5_GET(mpein_reg, out, pci_power); 212347862Shselasky return err; 213347862Shselasky} 214347862Shselasky 215331580Shselaskystatic int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 216331580Shselasky{ 217331580Shselasky struct pci_dev *pdev = dev->pdev; 218331580Shselasky int err = 0; 219331580Shselasky 220331580Shselasky mutex_lock(&dev->pci_status_mutex); 221331580Shselasky if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 222331580Shselasky err = pci_enable_device(pdev); 223331580Shselasky if (!err) 224331580Shselasky dev->pci_status = MLX5_PCI_STATUS_ENABLED; 225331580Shselasky } 226331580Shselasky mutex_unlock(&dev->pci_status_mutex); 227331580Shselasky 228331580Shselasky return err; 229331580Shselasky} 230331580Shselasky 231331580Shselaskystatic void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 232331580Shselasky{ 233331580Shselasky struct pci_dev *pdev = dev->pdev; 234331580Shselasky 235331580Shselasky mutex_lock(&dev->pci_status_mutex); 236331580Shselasky if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 237331580Shselasky pci_disable_device(pdev); 238331580Shselasky dev->pci_status = MLX5_PCI_STATUS_DISABLED; 239331580Shselasky } 240331580Shselasky mutex_unlock(&dev->pci_status_mutex); 241331580Shselasky} 242331580Shselasky 243290650Shselaskystatic int request_bar(struct pci_dev *pdev) 244290650Shselasky{ 245290650Shselasky int err = 0; 246290650Shselasky 247290650Shselasky if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 248290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""Missing registers BAR, aborting\n"); 249290650Shselasky return -ENODEV; 250290650Shselasky } 251290650Shselasky 252290650Shselasky err = pci_request_regions(pdev, DRIVER_NAME); 253290650Shselasky if (err) 254290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""Couldn't get PCI resources, aborting\n"); 255290650Shselasky 256290650Shselasky return err; 257290650Shselasky} 258290650Shselasky 259290650Shselaskystatic void release_bar(struct pci_dev *pdev) 260290650Shselasky{ 261290650Shselasky pci_release_regions(pdev); 262290650Shselasky} 263290650Shselasky 264290650Shselaskystatic int mlx5_enable_msix(struct mlx5_core_dev *dev) 265290650Shselasky{ 266290650Shselasky struct mlx5_priv *priv = &dev->priv; 267290650Shselasky struct mlx5_eq_table *table = &priv->eq_table; 268290650Shselasky int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq); 269338554Shselasky int limit = dev->msix_eqvec; 270337112Shselasky int nvec = MLX5_EQ_VEC_COMP_BASE; 271290650Shselasky int i; 272290650Shselasky 273337112Shselasky if (limit > 0) 274337112Shselasky nvec += limit; 275337112Shselasky else 276337112Shselasky nvec += MLX5_CAP_GEN(dev, num_ports) * num_online_cpus(); 277337112Shselasky 278353189Shselasky if (nvec > num_eqs) 279353189Shselasky nvec = num_eqs; 280353189Shselasky if (nvec > 256) 281353189Shselasky nvec = 256; /* limit of firmware API */ 282290650Shselasky if (nvec <= MLX5_EQ_VEC_COMP_BASE) 283290650Shselasky return -ENOMEM; 284290650Shselasky 285290650Shselasky priv->msix_arr = kzalloc(nvec * sizeof(*priv->msix_arr), GFP_KERNEL); 286290650Shselasky 287290650Shselasky priv->irq_info = kzalloc(nvec * sizeof(*priv->irq_info), GFP_KERNEL); 288290650Shselasky 289290650Shselasky for (i = 0; i < nvec; i++) 290290650Shselasky priv->msix_arr[i].entry = i; 291290650Shselasky 292290650Shselasky nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr, 293290650Shselasky MLX5_EQ_VEC_COMP_BASE + 1, nvec); 294290650Shselasky if (nvec < 0) 295290650Shselasky return nvec; 296290650Shselasky 297290650Shselasky table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE; 298290650Shselasky 299290650Shselasky return 0; 300290650Shselasky 301290650Shselasky} 302290650Shselasky 303290650Shselaskystatic void mlx5_disable_msix(struct mlx5_core_dev *dev) 304290650Shselasky{ 305290650Shselasky struct mlx5_priv *priv = &dev->priv; 306290650Shselasky 307290650Shselasky pci_disable_msix(dev->pdev); 308290650Shselasky kfree(priv->irq_info); 309290650Shselasky kfree(priv->msix_arr); 310290650Shselasky} 311290650Shselasky 312290650Shselaskystruct mlx5_reg_host_endianess { 313290650Shselasky u8 he; 314290650Shselasky u8 rsvd[15]; 315290650Shselasky}; 316290650Shselasky 317290650Shselasky 318290650Shselasky#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 319290650Shselasky 320290650Shselaskyenum { 321290650Shselasky MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 322306233Shselasky MLX5_DEV_CAP_FLAG_DCT | 323306233Shselasky MLX5_DEV_CAP_FLAG_DRAIN_SIGERR, 324290650Shselasky}; 325290650Shselasky 326290650Shselaskystatic u16 to_fw_pkey_sz(u32 size) 327290650Shselasky{ 328290650Shselasky switch (size) { 329290650Shselasky case 128: 330290650Shselasky return 0; 331290650Shselasky case 256: 332290650Shselasky return 1; 333290650Shselasky case 512: 334290650Shselasky return 2; 335290650Shselasky case 1024: 336290650Shselasky return 3; 337290650Shselasky case 2048: 338290650Shselasky return 4; 339290650Shselasky case 4096: 340290650Shselasky return 5; 341290650Shselasky default: 342290650Shselasky printf("mlx5_core: WARN: ""invalid pkey table size %d\n", size); 343290650Shselasky return 0; 344290650Shselasky } 345290650Shselasky} 346290650Shselasky 347331807Shselaskystatic int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 348331807Shselasky enum mlx5_cap_type cap_type, 349331807Shselasky enum mlx5_cap_mode cap_mode) 350290650Shselasky{ 351290650Shselasky u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 352290650Shselasky int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 353290650Shselasky void *out, *hca_caps; 354290650Shselasky u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 355290650Shselasky int err; 356290650Shselasky 357290650Shselasky memset(in, 0, sizeof(in)); 358290650Shselasky out = kzalloc(out_sz, GFP_KERNEL); 359290650Shselasky 360290650Shselasky MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 361290650Shselasky MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 362290650Shselasky err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz); 363290650Shselasky if (err) { 364290650Shselasky mlx5_core_warn(dev, 365290650Shselasky "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 366290650Shselasky cap_type, cap_mode, err); 367290650Shselasky goto query_ex; 368290650Shselasky } 369290650Shselasky 370290650Shselasky hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 371290650Shselasky 372290650Shselasky switch (cap_mode) { 373290650Shselasky case HCA_CAP_OPMOD_GET_MAX: 374290650Shselasky memcpy(dev->hca_caps_max[cap_type], hca_caps, 375290650Shselasky MLX5_UN_SZ_BYTES(hca_cap_union)); 376290650Shselasky break; 377290650Shselasky case HCA_CAP_OPMOD_GET_CUR: 378290650Shselasky memcpy(dev->hca_caps_cur[cap_type], hca_caps, 379290650Shselasky MLX5_UN_SZ_BYTES(hca_cap_union)); 380290650Shselasky break; 381290650Shselasky default: 382290650Shselasky mlx5_core_warn(dev, 383290650Shselasky "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 384290650Shselasky cap_type, cap_mode); 385290650Shselasky err = -EINVAL; 386290650Shselasky break; 387290650Shselasky } 388290650Shselaskyquery_ex: 389290650Shselasky kfree(out); 390290650Shselasky return err; 391290650Shselasky} 392290650Shselasky 393331807Shselaskyint mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 394331807Shselasky{ 395331807Shselasky int ret; 396331807Shselasky 397331807Shselasky ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 398331807Shselasky if (ret) 399331807Shselasky return ret; 400331807Shselasky 401331807Shselasky return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 402331807Shselasky} 403331807Shselasky 404290650Shselaskystatic int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz) 405290650Shselasky{ 406331807Shselasky u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0}; 407290650Shselasky 408290650Shselasky MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 409290650Shselasky 410331807Shselasky return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out)); 411290650Shselasky} 412290650Shselasky 413290650Shselaskystatic int handle_hca_cap(struct mlx5_core_dev *dev) 414290650Shselasky{ 415290650Shselasky void *set_ctx = NULL; 416290650Shselasky struct mlx5_profile *prof = dev->profile; 417290650Shselasky int err = -ENOMEM; 418290650Shselasky int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 419290650Shselasky void *set_hca_cap; 420290650Shselasky 421290650Shselasky set_ctx = kzalloc(set_sz, GFP_KERNEL); 422290650Shselasky 423331807Shselasky err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 424290650Shselasky if (err) 425290650Shselasky goto query_ex; 426290650Shselasky 427290650Shselasky set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 428290650Shselasky capability); 429290650Shselasky memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL], 430290650Shselasky MLX5_ST_SZ_BYTES(cmd_hca_cap)); 431290650Shselasky 432290650Shselasky mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 433290650Shselasky mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 434290650Shselasky 128); 435290650Shselasky /* we limit the size of the pkey table to 128 entries for now */ 436290650Shselasky MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 437290650Shselasky to_fw_pkey_sz(128)); 438290650Shselasky 439290650Shselasky if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 440290650Shselasky MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 441290650Shselasky prof->log_max_qp); 442290650Shselasky 443290650Shselasky /* disable cmdif checksum */ 444290650Shselasky MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 445290650Shselasky 446306233Shselasky /* enable drain sigerr */ 447306233Shselasky MLX5_SET(cmd_hca_cap, set_hca_cap, drain_sigerr, 1); 448306233Shselasky 449290650Shselasky MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 450290650Shselasky 451290650Shselasky err = set_caps(dev, set_ctx, set_sz); 452290650Shselasky 453290650Shselaskyquery_ex: 454290650Shselasky kfree(set_ctx); 455290650Shselasky return err; 456290650Shselasky} 457290650Shselasky 458329209Shselaskystatic int handle_hca_cap_atomic(struct mlx5_core_dev *dev) 459329209Shselasky{ 460329209Shselasky void *set_ctx; 461329209Shselasky void *set_hca_cap; 462329209Shselasky int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 463329209Shselasky int req_endianness; 464329209Shselasky int err; 465329209Shselasky 466329209Shselasky if (MLX5_CAP_GEN(dev, atomic)) { 467331807Shselasky err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 468329209Shselasky if (err) 469329209Shselasky return err; 470329209Shselasky } else { 471329209Shselasky return 0; 472329209Shselasky } 473329209Shselasky 474329209Shselasky req_endianness = 475329209Shselasky MLX5_CAP_ATOMIC(dev, 476329209Shselasky supported_atomic_req_8B_endianess_mode_1); 477329209Shselasky 478329209Shselasky if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 479329209Shselasky return 0; 480329209Shselasky 481329209Shselasky set_ctx = kzalloc(set_sz, GFP_KERNEL); 482329209Shselasky if (!set_ctx) 483329209Shselasky return -ENOMEM; 484329209Shselasky 485329209Shselasky MLX5_SET(set_hca_cap_in, set_ctx, op_mod, 486329209Shselasky MLX5_SET_HCA_CAP_OP_MOD_ATOMIC << 1); 487329209Shselasky set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 488329209Shselasky 489329209Shselasky /* Set requestor to host endianness */ 490329209Shselasky MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode, 491329209Shselasky MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 492329209Shselasky 493329209Shselasky err = set_caps(dev, set_ctx, set_sz); 494329209Shselasky 495329209Shselasky kfree(set_ctx); 496329209Shselasky return err; 497329209Shselasky} 498329209Shselasky 499290650Shselaskystatic int set_hca_ctrl(struct mlx5_core_dev *dev) 500290650Shselasky{ 501290650Shselasky struct mlx5_reg_host_endianess he_in; 502290650Shselasky struct mlx5_reg_host_endianess he_out; 503290650Shselasky int err; 504290650Shselasky 505306233Shselasky if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH && 506306233Shselasky !MLX5_CAP_GEN(dev, roce)) 507306233Shselasky return 0; 508306233Shselasky 509290650Shselasky memset(&he_in, 0, sizeof(he_in)); 510290650Shselasky he_in.he = MLX5_SET_HOST_ENDIANNESS; 511290650Shselasky err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 512290650Shselasky &he_out, sizeof(he_out), 513290650Shselasky MLX5_REG_HOST_ENDIANNESS, 0, 1); 514290650Shselasky return err; 515290650Shselasky} 516290650Shselasky 517290650Shselaskystatic int mlx5_core_enable_hca(struct mlx5_core_dev *dev) 518290650Shselasky{ 519331807Shselasky u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0}; 520331807Shselasky u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0}; 521290650Shselasky 522290650Shselasky MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 523331807Shselasky return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); 524290650Shselasky} 525290650Shselasky 526290650Shselaskystatic int mlx5_core_disable_hca(struct mlx5_core_dev *dev) 527290650Shselasky{ 528331807Shselasky u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0}; 529331807Shselasky u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0}; 530290650Shselasky 531290650Shselasky MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 532331807Shselasky return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 533290650Shselasky} 534290650Shselasky 535290650Shselaskystatic int mlx5_core_set_issi(struct mlx5_core_dev *dev) 536290650Shselasky{ 537331807Shselasky u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0}; 538331807Shselasky u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0}; 539331807Shselasky u32 sup_issi; 540290650Shselasky int err; 541290650Shselasky 542290650Shselasky MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 543290650Shselasky 544331807Shselasky err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), query_out, sizeof(query_out)); 545290650Shselasky if (err) { 546331807Shselasky u32 syndrome; 547331807Shselasky u8 status; 548331807Shselasky 549331807Shselasky mlx5_cmd_mbox_status(query_out, &status, &syndrome); 550331807Shselasky if (status == MLX5_CMD_STAT_BAD_OP_ERR) { 551290650Shselasky pr_debug("Only ISSI 0 is supported\n"); 552290650Shselasky return 0; 553290650Shselasky } 554290650Shselasky 555290650Shselasky printf("mlx5_core: ERR: ""failed to query ISSI\n"); 556290650Shselasky return err; 557290650Shselasky } 558290650Shselasky 559290650Shselasky sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 560290650Shselasky 561290650Shselasky if (sup_issi & (1 << 1)) { 562331807Shselasky u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0}; 563331807Shselasky u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0}; 564290650Shselasky 565290650Shselasky MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 566290650Shselasky MLX5_SET(set_issi_in, set_in, current_issi, 1); 567290650Shselasky 568331807Shselasky err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), set_out, sizeof(set_out)); 569290650Shselasky if (err) { 570331807Shselasky printf("mlx5_core: ERR: ""failed to set ISSI=1 err(%d)\n", err); 571290650Shselasky return err; 572290650Shselasky } 573290650Shselasky 574290650Shselasky dev->issi = 1; 575290650Shselasky 576290650Shselasky return 0; 577290650Shselasky } else if (sup_issi & (1 << 0)) { 578290650Shselasky return 0; 579290650Shselasky } 580290650Shselasky 581290650Shselasky return -ENOTSUPP; 582290650Shselasky} 583290650Shselasky 584290650Shselasky 585290650Shselaskyint mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn) 586290650Shselasky{ 587290650Shselasky struct mlx5_eq_table *table = &dev->priv.eq_table; 588290650Shselasky struct mlx5_eq *eq; 589290650Shselasky int err = -ENOENT; 590290650Shselasky 591290650Shselasky spin_lock(&table->lock); 592290650Shselasky list_for_each_entry(eq, &table->comp_eqs_list, list) { 593290650Shselasky if (eq->index == vector) { 594290650Shselasky *eqn = eq->eqn; 595290650Shselasky *irqn = eq->irqn; 596290650Shselasky err = 0; 597290650Shselasky break; 598290650Shselasky } 599290650Shselasky } 600290650Shselasky spin_unlock(&table->lock); 601290650Shselasky 602290650Shselasky return err; 603290650Shselasky} 604290650ShselaskyEXPORT_SYMBOL(mlx5_vector2eqn); 605290650Shselasky 606290650Shselaskyint mlx5_rename_eq(struct mlx5_core_dev *dev, int eq_ix, char *name) 607290650Shselasky{ 608290650Shselasky struct mlx5_priv *priv = &dev->priv; 609290650Shselasky struct mlx5_eq_table *table = &priv->eq_table; 610290650Shselasky struct mlx5_eq *eq; 611290650Shselasky int err = -ENOENT; 612290650Shselasky 613290650Shselasky spin_lock(&table->lock); 614290650Shselasky list_for_each_entry(eq, &table->comp_eqs_list, list) { 615290650Shselasky if (eq->index == eq_ix) { 616290650Shselasky int irq_ix = eq_ix + MLX5_EQ_VEC_COMP_BASE; 617290650Shselasky 618290650Shselasky snprintf(priv->irq_info[irq_ix].name, MLX5_MAX_IRQ_NAME, 619290650Shselasky "%s-%d", name, eq_ix); 620290650Shselasky 621290650Shselasky err = 0; 622290650Shselasky break; 623290650Shselasky } 624290650Shselasky } 625290650Shselasky spin_unlock(&table->lock); 626290650Shselasky 627290650Shselasky return err; 628290650Shselasky} 629290650Shselasky 630290650Shselaskystatic void free_comp_eqs(struct mlx5_core_dev *dev) 631290650Shselasky{ 632290650Shselasky struct mlx5_eq_table *table = &dev->priv.eq_table; 633290650Shselasky struct mlx5_eq *eq, *n; 634290650Shselasky 635290650Shselasky spin_lock(&table->lock); 636290650Shselasky list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { 637290650Shselasky list_del(&eq->list); 638290650Shselasky spin_unlock(&table->lock); 639290650Shselasky if (mlx5_destroy_unmap_eq(dev, eq)) 640290650Shselasky mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n", 641290650Shselasky eq->eqn); 642290650Shselasky kfree(eq); 643290650Shselasky spin_lock(&table->lock); 644290650Shselasky } 645290650Shselasky spin_unlock(&table->lock); 646290650Shselasky} 647290650Shselasky 648290650Shselaskystatic int alloc_comp_eqs(struct mlx5_core_dev *dev) 649290650Shselasky{ 650290650Shselasky struct mlx5_eq_table *table = &dev->priv.eq_table; 651290650Shselasky char name[MLX5_MAX_IRQ_NAME]; 652290650Shselasky struct mlx5_eq *eq; 653290650Shselasky int ncomp_vec; 654290650Shselasky int nent; 655290650Shselasky int err; 656290650Shselasky int i; 657290650Shselasky 658290650Shselasky INIT_LIST_HEAD(&table->comp_eqs_list); 659290650Shselasky ncomp_vec = table->num_comp_vectors; 660290650Shselasky nent = MLX5_COMP_EQ_SIZE; 661290650Shselasky for (i = 0; i < ncomp_vec; i++) { 662290650Shselasky eq = kzalloc(sizeof(*eq), GFP_KERNEL); 663290650Shselasky 664290650Shselasky snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i); 665290650Shselasky err = mlx5_create_map_eq(dev, eq, 666290650Shselasky i + MLX5_EQ_VEC_COMP_BASE, nent, 0, 667290650Shselasky name, &dev->priv.uuari.uars[0]); 668290650Shselasky if (err) { 669290650Shselasky kfree(eq); 670290650Shselasky goto clean; 671290650Shselasky } 672290650Shselasky mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn); 673290650Shselasky eq->index = i; 674290650Shselasky spin_lock(&table->lock); 675290650Shselasky list_add_tail(&eq->list, &table->comp_eqs_list); 676290650Shselasky spin_unlock(&table->lock); 677290650Shselasky } 678290650Shselasky 679290650Shselasky return 0; 680290650Shselasky 681290650Shselaskyclean: 682290650Shselasky free_comp_eqs(dev); 683290650Shselasky return err; 684290650Shselasky} 685290650Shselasky 686290650Shselaskystatic int map_bf_area(struct mlx5_core_dev *dev) 687290650Shselasky{ 688290650Shselasky resource_size_t bf_start = pci_resource_start(dev->pdev, 0); 689290650Shselasky resource_size_t bf_len = pci_resource_len(dev->pdev, 0); 690290650Shselasky 691290650Shselasky dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len); 692290650Shselasky 693290650Shselasky return dev->priv.bf_mapping ? 0 : -ENOMEM; 694290650Shselasky} 695290650Shselasky 696290650Shselaskystatic void unmap_bf_area(struct mlx5_core_dev *dev) 697290650Shselasky{ 698290650Shselasky if (dev->priv.bf_mapping) 699290650Shselasky io_mapping_free(dev->priv.bf_mapping); 700290650Shselasky} 701290650Shselasky 702290650Shselaskystatic inline int fw_initializing(struct mlx5_core_dev *dev) 703290650Shselasky{ 704290650Shselasky return ioread32be(&dev->iseg->initializing) >> 31; 705290650Shselasky} 706290650Shselasky 707290650Shselaskystatic int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili) 708290650Shselasky{ 709290650Shselasky u64 end = jiffies + msecs_to_jiffies(max_wait_mili); 710290650Shselasky int err = 0; 711290650Shselasky 712290650Shselasky while (fw_initializing(dev)) { 713290650Shselasky if (time_after(jiffies, end)) { 714290650Shselasky err = -EBUSY; 715290650Shselasky break; 716290650Shselasky } 717290650Shselasky msleep(FW_INIT_WAIT_MS); 718290650Shselasky } 719290650Shselasky 720290650Shselasky return err; 721290650Shselasky} 722290650Shselasky 723331580Shselaskystatic void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv) 724290650Shselasky{ 725331580Shselasky struct mlx5_device_context *dev_ctx; 726331580Shselasky struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv); 727331580Shselasky 728331580Shselasky dev_ctx = kzalloc(sizeof(*dev_ctx), GFP_KERNEL); 729331580Shselasky if (!dev_ctx) 730331580Shselasky return; 731331580Shselasky 732331580Shselasky dev_ctx->intf = intf; 733331580Shselasky CURVNET_SET_QUIET(vnet0); 734331580Shselasky dev_ctx->context = intf->add(dev); 735331580Shselasky CURVNET_RESTORE(); 736331580Shselasky 737331580Shselasky if (dev_ctx->context) { 738331580Shselasky spin_lock_irq(&priv->ctx_lock); 739331580Shselasky list_add_tail(&dev_ctx->list, &priv->ctx_list); 740331580Shselasky spin_unlock_irq(&priv->ctx_lock); 741331580Shselasky } else { 742331580Shselasky kfree(dev_ctx); 743331580Shselasky } 744331580Shselasky} 745331580Shselasky 746331580Shselaskystatic void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv) 747331580Shselasky{ 748331580Shselasky struct mlx5_device_context *dev_ctx; 749331580Shselasky struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv); 750331580Shselasky 751331580Shselasky list_for_each_entry(dev_ctx, &priv->ctx_list, list) 752331580Shselasky if (dev_ctx->intf == intf) { 753331580Shselasky spin_lock_irq(&priv->ctx_lock); 754331580Shselasky list_del(&dev_ctx->list); 755331580Shselasky spin_unlock_irq(&priv->ctx_lock); 756331580Shselasky 757331580Shselasky intf->remove(dev, dev_ctx->context); 758331580Shselasky kfree(dev_ctx); 759331580Shselasky return; 760331580Shselasky } 761331580Shselasky} 762331580Shselasky 763341958Shselaskyint 764341958Shselaskymlx5_register_device(struct mlx5_core_dev *dev) 765331580Shselasky{ 766290650Shselasky struct mlx5_priv *priv = &dev->priv; 767331580Shselasky struct mlx5_interface *intf; 768290650Shselasky 769331580Shselasky mutex_lock(&intf_mutex); 770331580Shselasky list_add_tail(&priv->dev_list, &dev_list); 771331580Shselasky list_for_each_entry(intf, &intf_list, list) 772331580Shselasky mlx5_add_device(intf, priv); 773331580Shselasky mutex_unlock(&intf_mutex); 774331580Shselasky 775331580Shselasky return 0; 776331580Shselasky} 777331580Shselasky 778341958Shselaskyvoid 779341958Shselaskymlx5_unregister_device(struct mlx5_core_dev *dev) 780331580Shselasky{ 781331580Shselasky struct mlx5_priv *priv = &dev->priv; 782331580Shselasky struct mlx5_interface *intf; 783331580Shselasky 784331580Shselasky mutex_lock(&intf_mutex); 785331580Shselasky list_for_each_entry(intf, &intf_list, list) 786331580Shselasky mlx5_remove_device(intf, priv); 787331580Shselasky list_del(&priv->dev_list); 788331580Shselasky mutex_unlock(&intf_mutex); 789331580Shselasky} 790331580Shselasky 791331580Shselaskyint mlx5_register_interface(struct mlx5_interface *intf) 792331580Shselasky{ 793331580Shselasky struct mlx5_priv *priv; 794331580Shselasky 795331580Shselasky if (!intf->add || !intf->remove) 796331580Shselasky return -EINVAL; 797331580Shselasky 798331580Shselasky mutex_lock(&intf_mutex); 799331580Shselasky list_add_tail(&intf->list, &intf_list); 800331580Shselasky list_for_each_entry(priv, &dev_list, dev_list) 801331580Shselasky mlx5_add_device(intf, priv); 802331580Shselasky mutex_unlock(&intf_mutex); 803331580Shselasky 804331580Shselasky return 0; 805331580Shselasky} 806331580ShselaskyEXPORT_SYMBOL(mlx5_register_interface); 807331580Shselasky 808331580Shselaskyvoid mlx5_unregister_interface(struct mlx5_interface *intf) 809331580Shselasky{ 810331580Shselasky struct mlx5_priv *priv; 811331580Shselasky 812331580Shselasky mutex_lock(&intf_mutex); 813331580Shselasky list_for_each_entry(priv, &dev_list, dev_list) 814331580Shselasky mlx5_remove_device(intf, priv); 815331580Shselasky list_del(&intf->list); 816331580Shselasky mutex_unlock(&intf_mutex); 817331580Shselasky} 818331580ShselaskyEXPORT_SYMBOL(mlx5_unregister_interface); 819331580Shselasky 820331580Shselaskyvoid *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol) 821331580Shselasky{ 822331580Shselasky struct mlx5_priv *priv = &mdev->priv; 823331580Shselasky struct mlx5_device_context *dev_ctx; 824331580Shselasky unsigned long flags; 825331580Shselasky void *result = NULL; 826331580Shselasky 827331580Shselasky spin_lock_irqsave(&priv->ctx_lock, flags); 828331580Shselasky 829331580Shselasky list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list) 830331580Shselasky if ((dev_ctx->intf->protocol == protocol) && 831331580Shselasky dev_ctx->intf->get_dev) { 832331580Shselasky result = dev_ctx->intf->get_dev(dev_ctx->context); 833331580Shselasky break; 834331580Shselasky } 835331580Shselasky 836331580Shselasky spin_unlock_irqrestore(&priv->ctx_lock, flags); 837331580Shselasky 838331580Shselasky return result; 839331580Shselasky} 840331580ShselaskyEXPORT_SYMBOL(mlx5_get_protocol_dev); 841331580Shselasky 842347853Shselaskystatic int mlx5_auto_fw_update; 843347853ShselaskySYSCTL_INT(_hw_mlx5, OID_AUTO, auto_fw_update, CTLFLAG_RDTUN | CTLFLAG_NOFETCH, 844347853Shselasky &mlx5_auto_fw_update, 0, 845347853Shselasky "Allow automatic firmware update on driver start"); 846347847Shselaskystatic int 847347847Shselaskymlx5_firmware_update(struct mlx5_core_dev *dev) 848347847Shselasky{ 849347847Shselasky const struct firmware *fw; 850347847Shselasky int err; 851347847Shselasky 852347853Shselasky TUNABLE_INT_FETCH("hw.mlx5.auto_fw_update", &mlx5_auto_fw_update); 853347853Shselasky if (!mlx5_auto_fw_update) 854347853Shselasky return (0); 855347847Shselasky fw = firmware_get("mlx5fw_mfa"); 856347847Shselasky if (fw) { 857347847Shselasky err = mlx5_firmware_flash(dev, fw); 858347847Shselasky firmware_put(fw, FIRMWARE_UNLOAD); 859347847Shselasky } 860347847Shselasky else 861347847Shselasky return (-ENOENT); 862347847Shselasky 863347847Shselasky return err; 864347847Shselasky} 865347847Shselasky 866331580Shselaskystatic int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 867331580Shselasky{ 868331580Shselasky struct pci_dev *pdev = dev->pdev; 869331580Shselasky int err = 0; 870331580Shselasky 871290650Shselasky pci_set_drvdata(dev->pdev, dev); 872290650Shselasky strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN); 873290650Shselasky priv->name[MLX5_MAX_NAME_LEN - 1] = 0; 874290650Shselasky 875290650Shselasky mutex_init(&priv->pgdir_mutex); 876290650Shselasky INIT_LIST_HEAD(&priv->pgdir_list); 877290650Shselasky spin_lock_init(&priv->mkey_lock); 878290650Shselasky 879290650Shselasky priv->numa_node = NUMA_NO_NODE; 880290650Shselasky 881331580Shselasky err = mlx5_pci_enable_device(dev); 882290650Shselasky if (err) { 883290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""Cannot enable PCI device, aborting\n"); 884290650Shselasky goto err_dbg; 885290650Shselasky } 886290650Shselasky 887290650Shselasky err = request_bar(pdev); 888290650Shselasky if (err) { 889290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""error requesting BARs, aborting\n"); 890290650Shselasky goto err_disable; 891290650Shselasky } 892290650Shselasky 893290650Shselasky pci_set_master(pdev); 894290650Shselasky 895290650Shselasky err = set_dma_caps(pdev); 896290650Shselasky if (err) { 897290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""Failed setting DMA capabilities mask, aborting\n"); 898290650Shselasky goto err_clr_master; 899290650Shselasky } 900290650Shselasky 901329212Shselasky dev->iseg_base = pci_resource_start(dev->pdev, 0); 902329212Shselasky dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 903290650Shselasky if (!dev->iseg) { 904290650Shselasky err = -ENOMEM; 905290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""Failed mapping initialization segment, aborting\n"); 906290650Shselasky goto err_clr_master; 907290650Shselasky } 908331580Shselasky 909337105Shselasky return 0; 910331585Shselasky 911331580Shselaskyerr_clr_master: 912331580Shselasky release_bar(dev->pdev); 913331580Shselaskyerr_disable: 914331580Shselasky mlx5_pci_disable_device(dev); 915331580Shselaskyerr_dbg: 916331580Shselasky return err; 917331580Shselasky} 918331580Shselasky 919331580Shselaskystatic void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 920331580Shselasky{ 921331580Shselasky iounmap(dev->iseg); 922331580Shselasky release_bar(dev->pdev); 923331580Shselasky mlx5_pci_disable_device(dev); 924331580Shselasky} 925331580Shselasky 926331810Shselaskystatic int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 927331580Shselasky{ 928331580Shselasky struct pci_dev *pdev = dev->pdev; 929331580Shselasky int err; 930331580Shselasky 931337103Shselasky err = mlx5_vsc_find_cap(dev); 932337103Shselasky if (err) 933337103Shselasky dev_err(&pdev->dev, "Unable to find vendor specific capabilities\n"); 934331815Shselasky 935331810Shselasky err = mlx5_query_hca_caps(dev); 936331810Shselasky if (err) { 937331810Shselasky dev_err(&pdev->dev, "query hca failed\n"); 938331810Shselasky goto out; 939331810Shselasky } 940331810Shselasky 941331810Shselasky err = mlx5_query_board_id(dev); 942331810Shselasky if (err) { 943331810Shselasky dev_err(&pdev->dev, "query board id failed\n"); 944331810Shselasky goto out; 945331810Shselasky } 946331810Shselasky 947331810Shselasky err = mlx5_eq_init(dev); 948331810Shselasky if (err) { 949331810Shselasky dev_err(&pdev->dev, "failed to initialize eq\n"); 950331810Shselasky goto out; 951331810Shselasky } 952331810Shselasky 953331810Shselasky MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock); 954331810Shselasky 955331810Shselasky err = mlx5_init_cq_table(dev); 956331810Shselasky if (err) { 957331810Shselasky dev_err(&pdev->dev, "failed to initialize cq table\n"); 958331810Shselasky goto err_eq_cleanup; 959331810Shselasky } 960331810Shselasky 961331810Shselasky mlx5_init_qp_table(dev); 962331810Shselasky mlx5_init_srq_table(dev); 963331810Shselasky mlx5_init_mr_table(dev); 964331810Shselasky 965341958Shselasky mlx5_init_reserved_gids(dev); 966341958Shselasky mlx5_fpga_init(dev); 967341958Shselasky 968331810Shselasky return 0; 969331810Shselasky 970331810Shselaskyerr_eq_cleanup: 971331810Shselasky mlx5_eq_cleanup(dev); 972331810Shselasky 973331810Shselaskyout: 974331810Shselasky return err; 975331810Shselasky} 976331810Shselasky 977331810Shselaskystatic void mlx5_cleanup_once(struct mlx5_core_dev *dev) 978331810Shselasky{ 979341958Shselasky mlx5_fpga_cleanup(dev); 980341958Shselasky mlx5_cleanup_reserved_gids(dev); 981331810Shselasky mlx5_cleanup_mr_table(dev); 982331810Shselasky mlx5_cleanup_srq_table(dev); 983331810Shselasky mlx5_cleanup_qp_table(dev); 984331810Shselasky mlx5_cleanup_cq_table(dev); 985331810Shselasky mlx5_eq_cleanup(dev); 986331810Shselasky} 987331810Shselasky 988331810Shselaskystatic int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, 989331810Shselasky bool boot) 990331810Shselasky{ 991331810Shselasky struct pci_dev *pdev = dev->pdev; 992331810Shselasky int err; 993331810Shselasky 994331580Shselasky mutex_lock(&dev->intf_state_mutex); 995331580Shselasky if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 996331580Shselasky dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n", 997331580Shselasky __func__); 998331580Shselasky goto out; 999331580Shselasky } 1000331580Shselasky 1001290650Shselasky device_printf((&pdev->dev)->bsddev, "INFO: ""firmware version: %d.%d.%d\n", fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev)); 1002290650Shselasky 1003306233Shselasky /* 1004306233Shselasky * On load removing any previous indication of internal error, 1005306233Shselasky * device is up 1006306233Shselasky */ 1007306233Shselasky dev->state = MLX5_DEVICE_STATE_UP; 1008306233Shselasky 1009290650Shselasky err = mlx5_cmd_init(dev); 1010290650Shselasky if (err) { 1011290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""Failed initializing command interface, aborting\n"); 1012331580Shselasky goto out_err; 1013290650Shselasky } 1014290650Shselasky 1015290650Shselasky err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI); 1016290650Shselasky if (err) { 1017290650Shselasky device_printf((&dev->pdev->dev)->bsddev, "ERR: ""Firmware over %d MS in initializing state, aborting\n", FW_INIT_TIMEOUT_MILI); 1018290650Shselasky goto err_cmd_cleanup; 1019290650Shselasky } 1020290650Shselasky 1021290650Shselasky err = mlx5_core_enable_hca(dev); 1022290650Shselasky if (err) { 1023290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""enable hca failed\n"); 1024331810Shselasky goto err_cmd_cleanup; 1025290650Shselasky } 1026290650Shselasky 1027290650Shselasky err = mlx5_core_set_issi(dev); 1028290650Shselasky if (err) { 1029290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""failed to set issi\n"); 1030290650Shselasky goto err_disable_hca; 1031290650Shselasky } 1032290650Shselasky 1033290650Shselasky err = mlx5_pagealloc_start(dev); 1034290650Shselasky if (err) { 1035290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_pagealloc_start failed\n"); 1036290650Shselasky goto err_disable_hca; 1037290650Shselasky } 1038290650Shselasky 1039290650Shselasky err = mlx5_satisfy_startup_pages(dev, 1); 1040290650Shselasky if (err) { 1041290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""failed to allocate boot pages\n"); 1042290650Shselasky goto err_pagealloc_stop; 1043290650Shselasky } 1044290650Shselasky 1045329209Shselasky err = set_hca_ctrl(dev); 1046329209Shselasky if (err) { 1047329209Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""set_hca_ctrl failed\n"); 1048329209Shselasky goto reclaim_boot_pages; 1049329209Shselasky } 1050329209Shselasky 1051306233Shselasky err = handle_hca_cap(dev); 1052290650Shselasky if (err) { 1053306233Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""handle_hca_cap failed\n"); 1054290650Shselasky goto reclaim_boot_pages; 1055290650Shselasky } 1056290650Shselasky 1057329209Shselasky err = handle_hca_cap_atomic(dev); 1058290650Shselasky if (err) { 1059329209Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""handle_hca_cap_atomic failed\n"); 1060290650Shselasky goto reclaim_boot_pages; 1061290650Shselasky } 1062290650Shselasky 1063290650Shselasky err = mlx5_satisfy_startup_pages(dev, 0); 1064290650Shselasky if (err) { 1065290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""failed to allocate init pages\n"); 1066290650Shselasky goto reclaim_boot_pages; 1067290650Shselasky } 1068290650Shselasky 1069290650Shselasky err = mlx5_cmd_init_hca(dev); 1070290650Shselasky if (err) { 1071290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""init hca failed\n"); 1072290650Shselasky goto reclaim_boot_pages; 1073290650Shselasky } 1074290650Shselasky 1075290650Shselasky mlx5_start_health_poll(dev); 1076290650Shselasky 1077331810Shselasky if (boot && mlx5_init_once(dev, priv)) { 1078331810Shselasky dev_err(&pdev->dev, "sw objs init failed\n"); 1079290650Shselasky goto err_stop_poll; 1080290650Shselasky } 1081290650Shselasky 1082290650Shselasky err = mlx5_enable_msix(dev); 1083290650Shselasky if (err) { 1084290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""enable msix failed\n"); 1085331810Shselasky goto err_cleanup_once; 1086290650Shselasky } 1087290650Shselasky 1088290650Shselasky err = mlx5_alloc_uuars(dev, &priv->uuari); 1089290650Shselasky if (err) { 1090290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""Failed allocating uar, aborting\n"); 1091331810Shselasky goto err_disable_msix; 1092290650Shselasky } 1093290650Shselasky 1094290650Shselasky err = mlx5_start_eqs(dev); 1095290650Shselasky if (err) { 1096290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to start pages and async EQs\n"); 1097290650Shselasky goto err_free_uar; 1098290650Shselasky } 1099290650Shselasky 1100290650Shselasky err = alloc_comp_eqs(dev); 1101290650Shselasky if (err) { 1102290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to alloc completion EQs\n"); 1103290650Shselasky goto err_stop_eqs; 1104290650Shselasky } 1105290650Shselasky 1106290650Shselasky if (map_bf_area(dev)) 1107290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to map blue flame area\n"); 1108290650Shselasky 1109329200Shselasky err = mlx5_init_fs(dev); 1110329200Shselasky if (err) { 1111329200Shselasky mlx5_core_err(dev, "flow steering init %d\n", err); 1112331810Shselasky goto err_free_comp_eqs; 1113329200Shselasky } 1114329200Shselasky 1115341958Shselasky err = mlx5_fpga_device_start(dev); 1116341958Shselasky if (err) { 1117341958Shselasky dev_err(&pdev->dev, "fpga device start failed %d\n", err); 1118341958Shselasky goto err_fpga_start; 1119341958Shselasky } 1120341958Shselasky 1121331580Shselasky err = mlx5_register_device(dev); 1122331580Shselasky if (err) { 1123331580Shselasky dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err); 1124331810Shselasky goto err_fs; 1125331580Shselasky } 1126331580Shselasky 1127331580Shselasky set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1128331580Shselasky 1129331580Shselaskyout: 1130331580Shselasky mutex_unlock(&dev->intf_state_mutex); 1131290650Shselasky return 0; 1132290650Shselasky 1133341958Shselaskyerr_fpga_start: 1134331810Shselaskyerr_fs: 1135331580Shselasky mlx5_cleanup_fs(dev); 1136331810Shselasky 1137331810Shselaskyerr_free_comp_eqs: 1138331810Shselasky free_comp_eqs(dev); 1139329200Shselasky unmap_bf_area(dev); 1140329200Shselasky 1141290650Shselaskyerr_stop_eqs: 1142290650Shselasky mlx5_stop_eqs(dev); 1143290650Shselasky 1144290650Shselaskyerr_free_uar: 1145290650Shselasky mlx5_free_uuars(dev, &priv->uuari); 1146290650Shselasky 1147331810Shselaskyerr_disable_msix: 1148290650Shselasky mlx5_disable_msix(dev); 1149290650Shselasky 1150331810Shselaskyerr_cleanup_once: 1151331810Shselasky if (boot) 1152331810Shselasky mlx5_cleanup_once(dev); 1153331810Shselasky 1154290650Shselaskyerr_stop_poll: 1155341934Shselasky mlx5_stop_health_poll(dev, boot); 1156290650Shselasky if (mlx5_cmd_teardown_hca(dev)) { 1157290650Shselasky device_printf((&dev->pdev->dev)->bsddev, "ERR: ""tear_down_hca failed, skip cleanup\n"); 1158331580Shselasky goto out_err; 1159290650Shselasky } 1160290650Shselasky 1161290650Shselaskyreclaim_boot_pages: 1162290650Shselasky mlx5_reclaim_startup_pages(dev); 1163290650Shselasky 1164290650Shselaskyerr_pagealloc_stop: 1165290650Shselasky mlx5_pagealloc_stop(dev); 1166290650Shselasky 1167290650Shselaskyerr_disable_hca: 1168290650Shselasky mlx5_core_disable_hca(dev); 1169290650Shselasky 1170290650Shselaskyerr_cmd_cleanup: 1171290650Shselasky mlx5_cmd_cleanup(dev); 1172290650Shselasky 1173331580Shselaskyout_err: 1174331580Shselasky dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1175331580Shselasky mutex_unlock(&dev->intf_state_mutex); 1176290650Shselasky 1177290650Shselasky return err; 1178290650Shselasky} 1179290650Shselasky 1180331810Shselaskystatic int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, 1181331810Shselasky bool cleanup) 1182290650Shselasky{ 1183331580Shselasky int err = 0; 1184290650Shselasky 1185331811Shselasky if (cleanup) 1186331811Shselasky mlx5_drain_health_recovery(dev); 1187331811Shselasky 1188331580Shselasky mutex_lock(&dev->intf_state_mutex); 1189347799Shselasky if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1190331580Shselasky dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n", __func__); 1191331810Shselasky if (cleanup) 1192331810Shselasky mlx5_cleanup_once(dev); 1193331580Shselasky goto out; 1194331580Shselasky } 1195331580Shselasky 1196331580Shselasky mlx5_unregister_device(dev); 1197331580Shselasky 1198341958Shselasky mlx5_fpga_device_stop(dev); 1199329200Shselasky mlx5_cleanup_fs(dev); 1200290650Shselasky unmap_bf_area(dev); 1201322144Shselasky mlx5_wait_for_reclaim_vfs_pages(dev); 1202290650Shselasky free_comp_eqs(dev); 1203290650Shselasky mlx5_stop_eqs(dev); 1204290650Shselasky mlx5_free_uuars(dev, &priv->uuari); 1205290650Shselasky mlx5_disable_msix(dev); 1206331810Shselasky if (cleanup) 1207331810Shselasky mlx5_cleanup_once(dev); 1208341934Shselasky mlx5_stop_health_poll(dev, cleanup); 1209331580Shselasky err = mlx5_cmd_teardown_hca(dev); 1210331580Shselasky if (err) { 1211290650Shselasky device_printf((&dev->pdev->dev)->bsddev, "ERR: ""tear_down_hca failed, skip cleanup\n"); 1212331580Shselasky goto out; 1213290650Shselasky } 1214290650Shselasky mlx5_pagealloc_stop(dev); 1215290650Shselasky mlx5_reclaim_startup_pages(dev); 1216290650Shselasky mlx5_core_disable_hca(dev); 1217290650Shselasky mlx5_cmd_cleanup(dev); 1218290650Shselasky 1219331580Shselaskyout: 1220331580Shselasky clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1221331580Shselasky mutex_unlock(&dev->intf_state_mutex); 1222331580Shselasky return err; 1223290650Shselasky} 1224290650Shselasky 1225331580Shselaskyvoid mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event, 1226331580Shselasky unsigned long param) 1227290650Shselasky{ 1228290650Shselasky struct mlx5_priv *priv = &dev->priv; 1229290650Shselasky struct mlx5_device_context *dev_ctx; 1230290650Shselasky unsigned long flags; 1231290650Shselasky 1232290650Shselasky spin_lock_irqsave(&priv->ctx_lock, flags); 1233290650Shselasky 1234290650Shselasky list_for_each_entry(dev_ctx, &priv->ctx_list, list) 1235290650Shselasky if (dev_ctx->intf->event) 1236290650Shselasky dev_ctx->intf->event(dev, dev_ctx->context, event, param); 1237290650Shselasky 1238290650Shselasky spin_unlock_irqrestore(&priv->ctx_lock, flags); 1239290650Shselasky} 1240290650Shselasky 1241290650Shselaskystruct mlx5_core_event_handler { 1242290650Shselasky void (*event)(struct mlx5_core_dev *dev, 1243290650Shselasky enum mlx5_dev_event event, 1244290650Shselasky void *data); 1245290650Shselasky}; 1246290650Shselasky 1247290650Shselaskystatic int init_one(struct pci_dev *pdev, 1248290650Shselasky const struct pci_device_id *id) 1249290650Shselasky{ 1250290650Shselasky struct mlx5_core_dev *dev; 1251290650Shselasky struct mlx5_priv *priv; 1252338554Shselasky device_t bsddev = pdev->dev.bsddev; 1253290650Shselasky int err; 1254290650Shselasky 1255290650Shselasky dev = kzalloc(sizeof(*dev), GFP_KERNEL); 1256290650Shselasky priv = &dev->priv; 1257306233Shselasky if (id) 1258306233Shselasky priv->pci_dev_data = id->driver_data; 1259290650Shselasky 1260347835Shselasky if (mlx5_prof_sel < 0 || mlx5_prof_sel >= ARRAY_SIZE(profiles)) { 1261341930Shselasky device_printf(bsddev, "WARN: selected profile out of range, selecting default (%d)\n", MLX5_DEFAULT_PROF); 1262347835Shselasky mlx5_prof_sel = MLX5_DEFAULT_PROF; 1263290650Shselasky } 1264347835Shselasky dev->profile = &profiles[mlx5_prof_sel]; 1265331580Shselasky dev->pdev = pdev; 1266290650Shselasky dev->event = mlx5_core_event; 1267290650Shselasky 1268341948Shselasky /* Set desc */ 1269341948Shselasky device_set_desc(bsddev, mlx5_version); 1270341948Shselasky 1271338554Shselasky sysctl_ctx_init(&dev->sysctl_ctx); 1272338554Shselasky SYSCTL_ADD_INT(&dev->sysctl_ctx, 1273338554Shselasky SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1274338554Shselasky OID_AUTO, "msix_eqvec", CTLFLAG_RDTUN, &dev->msix_eqvec, 0, 1275338554Shselasky "Maximum number of MSIX event queue vectors, if set"); 1276347862Shselasky SYSCTL_ADD_INT(&dev->sysctl_ctx, 1277347862Shselasky SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1278347862Shselasky OID_AUTO, "power_status", CTLFLAG_RD, &dev->pwr_status, 0, 1279347862Shselasky "0:Invalid 1:Sufficient 2:Insufficient"); 1280347862Shselasky SYSCTL_ADD_INT(&dev->sysctl_ctx, 1281347862Shselasky SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1282347862Shselasky OID_AUTO, "power_value", CTLFLAG_RD, &dev->pwr_value, 0, 1283347862Shselasky "Current power value in Watts"); 1284338554Shselasky 1285290650Shselasky INIT_LIST_HEAD(&priv->ctx_list); 1286290650Shselasky spin_lock_init(&priv->ctx_lock); 1287341930Shselasky mutex_init(&dev->pci_status_mutex); 1288341930Shselasky mutex_init(&dev->intf_state_mutex); 1289347880Shselasky mtx_init(&dev->dump_lock, "mlx5dmp", NULL, MTX_DEF | MTX_NEW); 1290331580Shselasky err = mlx5_pci_init(dev, priv); 1291290650Shselasky if (err) { 1292341930Shselasky device_printf(bsddev, "ERR: mlx5_pci_init failed %d\n", err); 1293331580Shselasky goto clean_dev; 1294290650Shselasky } 1295290650Shselasky 1296341930Shselasky err = mlx5_health_init(dev); 1297341930Shselasky if (err) { 1298341930Shselasky device_printf(bsddev, "ERR: mlx5_health_init failed %d\n", err); 1299341930Shselasky goto close_pci; 1300341930Shselasky } 1301331580Shselasky 1302331810Shselasky mlx5_pagealloc_init(dev); 1303331810Shselasky 1304331810Shselasky err = mlx5_load_one(dev, priv, true); 1305290650Shselasky if (err) { 1306341930Shselasky device_printf(bsddev, "ERR: mlx5_load_one failed %d\n", err); 1307331580Shselasky goto clean_health; 1308290650Shselasky } 1309290650Shselasky 1310331914Shselasky mlx5_fwdump_prep(dev); 1311331914Shselasky 1312347847Shselasky mlx5_firmware_update(dev); 1313347847Shselasky 1314341930Shselasky pci_save_state(bsddev); 1315290650Shselasky return 0; 1316290650Shselasky 1317331580Shselaskyclean_health: 1318331810Shselasky mlx5_pagealloc_cleanup(dev); 1319341930Shselasky mlx5_health_cleanup(dev); 1320331580Shselaskyclose_pci: 1321341930Shselasky mlx5_pci_close(dev, priv); 1322331580Shselaskyclean_dev: 1323338554Shselasky sysctl_ctx_free(&dev->sysctl_ctx); 1324347880Shselasky mtx_destroy(&dev->dump_lock); 1325290650Shselasky kfree(dev); 1326290650Shselasky return err; 1327290650Shselasky} 1328290650Shselasky 1329290650Shselaskystatic void remove_one(struct pci_dev *pdev) 1330290650Shselasky{ 1331290650Shselasky struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1332331580Shselasky struct mlx5_priv *priv = &dev->priv; 1333290650Shselasky 1334331810Shselasky if (mlx5_unload_one(dev, priv, true)) { 1335331580Shselasky dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n"); 1336331580Shselasky mlx5_health_cleanup(dev); 1337331580Shselasky return; 1338331580Shselasky } 1339331580Shselasky 1340331810Shselasky mlx5_pagealloc_cleanup(dev); 1341331580Shselasky mlx5_health_cleanup(dev); 1342347880Shselasky mlx5_fwdump_clean(dev); 1343331580Shselasky mlx5_pci_close(dev, priv); 1344347880Shselasky mtx_destroy(&dev->dump_lock); 1345331580Shselasky pci_set_drvdata(pdev, NULL); 1346338554Shselasky sysctl_ctx_free(&dev->sysctl_ctx); 1347290650Shselasky kfree(dev); 1348290650Shselasky} 1349290650Shselasky 1350331580Shselaskystatic pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 1351331580Shselasky pci_channel_state_t state) 1352331580Shselasky{ 1353331580Shselasky struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1354331580Shselasky struct mlx5_priv *priv = &dev->priv; 1355331580Shselasky 1356331580Shselasky dev_info(&pdev->dev, "%s was called\n", __func__); 1357331810Shselasky mlx5_enter_error_state(dev, false); 1358331810Shselasky mlx5_unload_one(dev, priv, false); 1359331914Shselasky 1360331582Shselasky if (state) { 1361331582Shselasky mlx5_drain_health_wq(dev); 1362331582Shselasky mlx5_pci_disable_device(dev); 1363331582Shselasky } 1364331582Shselasky 1365331580Shselasky return state == pci_channel_io_perm_failure ? 1366331580Shselasky PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 1367331580Shselasky} 1368331580Shselasky 1369331580Shselaskystatic pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 1370331580Shselasky{ 1371331580Shselasky struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1372331580Shselasky int err = 0; 1373331580Shselasky 1374331580Shselasky dev_info(&pdev->dev, "%s was called\n", __func__); 1375331580Shselasky 1376331580Shselasky err = mlx5_pci_enable_device(dev); 1377331580Shselasky if (err) { 1378331580Shselasky dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n" 1379331580Shselasky , __func__, err); 1380331580Shselasky return PCI_ERS_RESULT_DISCONNECT; 1381331580Shselasky } 1382331580Shselasky pci_set_master(pdev); 1383331580Shselasky pci_set_powerstate(pdev->dev.bsddev, PCI_POWERSTATE_D0); 1384331580Shselasky pci_restore_state(pdev->dev.bsddev); 1385331816Shselasky pci_save_state(pdev->dev.bsddev); 1386331580Shselasky 1387331580Shselasky return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; 1388331580Shselasky} 1389331580Shselasky 1390331580Shselasky/* wait for the device to show vital signs. For now we check 1391331580Shselasky * that we can read the device ID and that the health buffer 1392331580Shselasky * shows a non zero value which is different than 0xffffffff 1393331580Shselasky */ 1394331580Shselaskystatic void wait_vital(struct pci_dev *pdev) 1395331580Shselasky{ 1396331580Shselasky struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1397331580Shselasky struct mlx5_core_health *health = &dev->priv.health; 1398331580Shselasky const int niter = 100; 1399331580Shselasky u32 count; 1400331580Shselasky u16 did; 1401331580Shselasky int i; 1402331580Shselasky 1403331580Shselasky /* Wait for firmware to be ready after reset */ 1404331580Shselasky msleep(1000); 1405331580Shselasky for (i = 0; i < niter; i++) { 1406331580Shselasky if (pci_read_config_word(pdev, 2, &did)) { 1407331580Shselasky dev_warn(&pdev->dev, "failed reading config word\n"); 1408331580Shselasky break; 1409331580Shselasky } 1410331580Shselasky if (did == pdev->device) { 1411331580Shselasky dev_info(&pdev->dev, "device ID correctly read after %d iterations\n", i); 1412331580Shselasky break; 1413331580Shselasky } 1414331580Shselasky msleep(50); 1415331580Shselasky } 1416331580Shselasky if (i == niter) 1417331580Shselasky dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__); 1418331580Shselasky 1419331580Shselasky for (i = 0; i < niter; i++) { 1420331580Shselasky count = ioread32be(health->health_counter); 1421331580Shselasky if (count && count != 0xffffffff) { 1422331580Shselasky dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i); 1423331580Shselasky break; 1424331580Shselasky } 1425331580Shselasky msleep(50); 1426331580Shselasky } 1427331580Shselasky 1428331580Shselasky if (i == niter) 1429331580Shselasky dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__); 1430331580Shselasky} 1431331580Shselasky 1432331580Shselaskystatic void mlx5_pci_resume(struct pci_dev *pdev) 1433331580Shselasky{ 1434331580Shselasky struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1435331580Shselasky struct mlx5_priv *priv = &dev->priv; 1436331580Shselasky int err; 1437331580Shselasky 1438331580Shselasky dev_info(&pdev->dev, "%s was called\n", __func__); 1439331580Shselasky 1440331580Shselasky wait_vital(pdev); 1441331580Shselasky 1442331810Shselasky err = mlx5_load_one(dev, priv, false); 1443331580Shselasky if (err) 1444331580Shselasky dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n" 1445331580Shselasky , __func__, err); 1446331580Shselasky else 1447331580Shselasky dev_info(&pdev->dev, "%s: device recovered\n", __func__); 1448331580Shselasky} 1449331580Shselasky 1450331580Shselaskystatic const struct pci_error_handlers mlx5_err_handler = { 1451331580Shselasky .error_detected = mlx5_pci_err_detected, 1452331580Shselasky .slot_reset = mlx5_pci_slot_reset, 1453331580Shselasky .resume = mlx5_pci_resume 1454331580Shselasky}; 1455331580Shselasky 1456331810Shselaskystatic int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 1457331810Shselasky{ 1458347818Shselasky bool fast_teardown, force_teardown; 1459331810Shselasky int err; 1460331810Shselasky 1461347819Shselasky if (!mlx5_fast_unload_enabled) { 1462347819Shselasky mlx5_core_dbg(dev, "fast unload is disabled by user\n"); 1463347819Shselasky return -EOPNOTSUPP; 1464347819Shselasky } 1465347819Shselasky 1466347818Shselasky fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1467347818Shselasky force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1468347818Shselasky 1469347818Shselasky mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1470347818Shselasky mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1471347818Shselasky 1472347818Shselasky if (!fast_teardown && !force_teardown) 1473331810Shselasky return -EOPNOTSUPP; 1474331810Shselasky 1475331810Shselasky if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1476331810Shselasky mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 1477331810Shselasky return -EAGAIN; 1478331810Shselasky } 1479331810Shselasky 1480341934Shselasky /* Panic tear down fw command will stop the PCI bus communication 1481341934Shselasky * with the HCA, so the health polll is no longer needed. 1482341934Shselasky */ 1483341934Shselasky mlx5_drain_health_wq(dev); 1484341934Shselasky mlx5_stop_health_poll(dev, false); 1485341934Shselasky 1486347818Shselasky err = mlx5_cmd_fast_teardown_hca(dev); 1487347818Shselasky if (!err) 1488347818Shselasky goto done; 1489347818Shselasky 1490331810Shselasky err = mlx5_cmd_force_teardown_hca(dev); 1491347818Shselasky if (!err) 1492347818Shselasky goto done; 1493331810Shselasky 1494347818Shselasky mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", err); 1495347818Shselasky mlx5_start_health_poll(dev); 1496347818Shselasky return err; 1497347818Shselaskydone: 1498331810Shselasky mlx5_enter_error_state(dev, true); 1499331810Shselasky return 0; 1500331810Shselasky} 1501331810Shselasky 1502347802Shselaskystatic void mlx5_disable_interrupts(struct mlx5_core_dev *mdev) 1503347802Shselasky{ 1504347802Shselasky int nvec = mdev->priv.eq_table.num_comp_vectors + MLX5_EQ_VEC_COMP_BASE; 1505347802Shselasky int x; 1506347802Shselasky 1507347802Shselasky mdev->priv.disable_irqs = 1; 1508347802Shselasky 1509347802Shselasky /* wait for all IRQ handlers to finish processing */ 1510347802Shselasky for (x = 0; x != nvec; x++) 1511347802Shselasky synchronize_irq(mdev->priv.msix_arr[x].vector); 1512347802Shselasky} 1513347802Shselasky 1514329211Shselaskystatic void shutdown_one(struct pci_dev *pdev) 1515329211Shselasky{ 1516331580Shselasky struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1517331580Shselasky struct mlx5_priv *priv = &dev->priv; 1518331810Shselasky int err; 1519331580Shselasky 1520347802Shselasky /* enter polling mode */ 1521347802Shselasky mlx5_cmd_use_polling(dev); 1522347802Shselasky 1523347802Shselasky /* disable all interrupts */ 1524347802Shselasky mlx5_disable_interrupts(dev); 1525347802Shselasky 1526331810Shselasky err = mlx5_try_fast_unload(dev); 1527331810Shselasky if (err) 1528331810Shselasky mlx5_unload_one(dev, priv, false); 1529331580Shselasky mlx5_pci_disable_device(dev); 1530329211Shselasky} 1531329211Shselasky 1532290650Shselaskystatic const struct pci_device_id mlx5_core_pci_table[] = { 1533290650Shselasky { PCI_VDEVICE(MELLANOX, 4113) }, /* Connect-IB */ 1534290650Shselasky { PCI_VDEVICE(MELLANOX, 4114) }, /* Connect-IB VF */ 1535290650Shselasky { PCI_VDEVICE(MELLANOX, 4115) }, /* ConnectX-4 */ 1536290650Shselasky { PCI_VDEVICE(MELLANOX, 4116) }, /* ConnectX-4 VF */ 1537290650Shselasky { PCI_VDEVICE(MELLANOX, 4117) }, /* ConnectX-4LX */ 1538290650Shselasky { PCI_VDEVICE(MELLANOX, 4118) }, /* ConnectX-4LX VF */ 1539306233Shselasky { PCI_VDEVICE(MELLANOX, 4119) }, /* ConnectX-5 */ 1540306233Shselasky { PCI_VDEVICE(MELLANOX, 4120) }, /* ConnectX-5 VF */ 1541290650Shselasky { PCI_VDEVICE(MELLANOX, 4121) }, 1542290650Shselasky { PCI_VDEVICE(MELLANOX, 4122) }, 1543290650Shselasky { PCI_VDEVICE(MELLANOX, 4123) }, 1544290650Shselasky { PCI_VDEVICE(MELLANOX, 4124) }, 1545290650Shselasky { PCI_VDEVICE(MELLANOX, 4125) }, 1546290650Shselasky { PCI_VDEVICE(MELLANOX, 4126) }, 1547290650Shselasky { PCI_VDEVICE(MELLANOX, 4127) }, 1548290650Shselasky { PCI_VDEVICE(MELLANOX, 4128) }, 1549290650Shselasky { PCI_VDEVICE(MELLANOX, 4129) }, 1550290650Shselasky { PCI_VDEVICE(MELLANOX, 4130) }, 1551290650Shselasky { PCI_VDEVICE(MELLANOX, 4131) }, 1552290650Shselasky { PCI_VDEVICE(MELLANOX, 4132) }, 1553290650Shselasky { PCI_VDEVICE(MELLANOX, 4133) }, 1554290650Shselasky { PCI_VDEVICE(MELLANOX, 4134) }, 1555290650Shselasky { PCI_VDEVICE(MELLANOX, 4135) }, 1556290650Shselasky { PCI_VDEVICE(MELLANOX, 4136) }, 1557290650Shselasky { PCI_VDEVICE(MELLANOX, 4137) }, 1558290650Shselasky { PCI_VDEVICE(MELLANOX, 4138) }, 1559290650Shselasky { PCI_VDEVICE(MELLANOX, 4139) }, 1560290650Shselasky { PCI_VDEVICE(MELLANOX, 4140) }, 1561290650Shselasky { PCI_VDEVICE(MELLANOX, 4141) }, 1562290650Shselasky { PCI_VDEVICE(MELLANOX, 4142) }, 1563290650Shselasky { PCI_VDEVICE(MELLANOX, 4143) }, 1564290650Shselasky { PCI_VDEVICE(MELLANOX, 4144) }, 1565290650Shselasky { 0, } 1566290650Shselasky}; 1567290650Shselasky 1568290650ShselaskyMODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 1569290650Shselasky 1570331809Shselaskyvoid mlx5_disable_device(struct mlx5_core_dev *dev) 1571331809Shselasky{ 1572331809Shselasky mlx5_pci_err_detected(dev->pdev, 0); 1573331809Shselasky} 1574331809Shselasky 1575331809Shselaskyvoid mlx5_recover_device(struct mlx5_core_dev *dev) 1576331809Shselasky{ 1577331809Shselasky mlx5_pci_disable_device(dev); 1578331809Shselasky if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) 1579331809Shselasky mlx5_pci_resume(dev->pdev); 1580331809Shselasky} 1581331809Shselasky 1582331586Shselaskystruct pci_driver mlx5_core_driver = { 1583290650Shselasky .name = DRIVER_NAME, 1584290650Shselasky .id_table = mlx5_core_pci_table, 1585329211Shselasky .shutdown = shutdown_one, 1586290650Shselasky .probe = init_one, 1587331580Shselasky .remove = remove_one, 1588331580Shselasky .err_handler = &mlx5_err_handler 1589290650Shselasky}; 1590290650Shselasky 1591290650Shselaskystatic int __init init(void) 1592290650Shselasky{ 1593290650Shselasky int err; 1594290650Shselasky 1595290650Shselasky err = pci_register_driver(&mlx5_core_driver); 1596290650Shselasky if (err) 1597331580Shselasky goto err_debug; 1598290650Shselasky 1599347871Shselasky err = mlx5_ctl_init(); 1600331586Shselasky if (err) 1601347871Shselasky goto err_ctl; 1602331586Shselasky 1603331586Shselasky return 0; 1604331586Shselasky 1605347871Shselaskyerr_ctl: 1606331586Shselasky pci_unregister_driver(&mlx5_core_driver); 1607290650Shselasky 1608290650Shselaskyerr_debug: 1609290650Shselasky return err; 1610290650Shselasky} 1611290650Shselasky 1612290650Shselaskystatic void __exit cleanup(void) 1613290650Shselasky{ 1614347871Shselasky mlx5_ctl_fini(); 1615290650Shselasky pci_unregister_driver(&mlx5_core_driver); 1616290650Shselasky} 1617290650Shselasky 1618290650Shselaskymodule_init(init); 1619290650Shselaskymodule_exit(cleanup); 1620