mlx5_main.c revision 347862
1/*- 2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_core/mlx5_main.c 347862 2019-05-16 18:13:02Z hselasky $ 26 */ 27 28#include <linux/kmod.h> 29#include <linux/module.h> 30#include <linux/errno.h> 31#include <linux/pci.h> 32#include <linux/dma-mapping.h> 33#include <linux/slab.h> 34#include <linux/io-mapping.h> 35#include <linux/interrupt.h> 36#include <linux/hardirq.h> 37#include <dev/mlx5/driver.h> 38#include <dev/mlx5/cq.h> 39#include <dev/mlx5/qp.h> 40#include <dev/mlx5/srq.h> 41#include <linux/delay.h> 42#include <dev/mlx5/mlx5_ifc.h> 43#include <dev/mlx5/mlx5_fpga/core.h> 44#include <dev/mlx5/mlx5_lib/mlx5.h> 45#include "mlx5_core.h" 46#include "fs_core.h" 47 48static const char mlx5_version[] = "Mellanox Core driver " 49 DRIVER_VERSION " (" DRIVER_RELDATE ")"; 50MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 51MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver"); 52MODULE_LICENSE("Dual BSD/GPL"); 53MODULE_DEPEND(mlx5, linuxkpi, 1, 1, 1); 54MODULE_DEPEND(mlx5, mlxfw, 1, 1, 1); 55MODULE_DEPEND(mlx5, firmware, 1, 1, 1); 56MODULE_VERSION(mlx5, 1); 57 58SYSCTL_NODE(_hw, OID_AUTO, mlx5, CTLFLAG_RW, 0, "mlx5 hardware controls"); 59 60int mlx5_core_debug_mask; 61SYSCTL_INT(_hw_mlx5, OID_AUTO, debug_mask, CTLFLAG_RWTUN, 62 &mlx5_core_debug_mask, 0, 63 "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 64 65#define MLX5_DEFAULT_PROF 2 66static int mlx5_prof_sel = MLX5_DEFAULT_PROF; 67SYSCTL_INT(_hw_mlx5, OID_AUTO, prof_sel, CTLFLAG_RWTUN, 68 &mlx5_prof_sel, 0, 69 "profile selector. Valid range 0 - 2"); 70 71static int mlx5_fast_unload_enabled = 1; 72SYSCTL_INT(_hw_mlx5, OID_AUTO, fast_unload_enabled, CTLFLAG_RWTUN, 73 &mlx5_fast_unload_enabled, 0, 74 "Set to enable fast unload. Clear to disable."); 75 76#define NUMA_NO_NODE -1 77 78static LIST_HEAD(intf_list); 79static LIST_HEAD(dev_list); 80static DEFINE_MUTEX(intf_mutex); 81 82struct mlx5_device_context { 83 struct list_head list; 84 struct mlx5_interface *intf; 85 void *context; 86}; 87 88enum { 89 MLX5_ATOMIC_REQ_MODE_BE = 0x0, 90 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 91}; 92 93static struct mlx5_profile profiles[] = { 94 [0] = { 95 .mask = 0, 96 }, 97 [1] = { 98 .mask = MLX5_PROF_MASK_QP_SIZE, 99 .log_max_qp = 12, 100 }, 101 [2] = { 102 .mask = MLX5_PROF_MASK_QP_SIZE | 103 MLX5_PROF_MASK_MR_CACHE, 104 .log_max_qp = 17, 105 .mr_cache[0] = { 106 .size = 500, 107 .limit = 250 108 }, 109 .mr_cache[1] = { 110 .size = 500, 111 .limit = 250 112 }, 113 .mr_cache[2] = { 114 .size = 500, 115 .limit = 250 116 }, 117 .mr_cache[3] = { 118 .size = 500, 119 .limit = 250 120 }, 121 .mr_cache[4] = { 122 .size = 500, 123 .limit = 250 124 }, 125 .mr_cache[5] = { 126 .size = 500, 127 .limit = 250 128 }, 129 .mr_cache[6] = { 130 .size = 500, 131 .limit = 250 132 }, 133 .mr_cache[7] = { 134 .size = 500, 135 .limit = 250 136 }, 137 .mr_cache[8] = { 138 .size = 500, 139 .limit = 250 140 }, 141 .mr_cache[9] = { 142 .size = 500, 143 .limit = 250 144 }, 145 .mr_cache[10] = { 146 .size = 500, 147 .limit = 250 148 }, 149 .mr_cache[11] = { 150 .size = 500, 151 .limit = 250 152 }, 153 .mr_cache[12] = { 154 .size = 64, 155 .limit = 32 156 }, 157 .mr_cache[13] = { 158 .size = 32, 159 .limit = 16 160 }, 161 .mr_cache[14] = { 162 .size = 16, 163 .limit = 8 164 }, 165 }, 166 [3] = { 167 .mask = MLX5_PROF_MASK_QP_SIZE, 168 .log_max_qp = 17, 169 }, 170}; 171 172static int set_dma_caps(struct pci_dev *pdev) 173{ 174 int err; 175 176 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 177 if (err) { 178 device_printf((&pdev->dev)->bsddev, "WARN: ""Warning: couldn't set 64-bit PCI DMA mask\n"); 179 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 180 if (err) { 181 device_printf((&pdev->dev)->bsddev, "ERR: ""Can't set PCI DMA mask, aborting\n"); 182 return err; 183 } 184 } 185 186 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 187 if (err) { 188 device_printf((&pdev->dev)->bsddev, "WARN: ""Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 189 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 190 if (err) { 191 device_printf((&pdev->dev)->bsddev, "ERR: ""Can't set consistent PCI DMA mask, aborting\n"); 192 return err; 193 } 194 } 195 196 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 197 return err; 198} 199 200int mlx5_pci_read_power_status(struct mlx5_core_dev *dev, 201 u16 *p_power, u8 *p_status) 202{ 203 u32 in[MLX5_ST_SZ_DW(mpein_reg)] = {}; 204 u32 out[MLX5_ST_SZ_DW(mpein_reg)] = {}; 205 int err; 206 207 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), 208 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN, 0, 0); 209 210 *p_status = MLX5_GET(mpein_reg, out, pwr_status); 211 *p_power = MLX5_GET(mpein_reg, out, pci_power); 212 return err; 213} 214 215static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 216{ 217 struct pci_dev *pdev = dev->pdev; 218 int err = 0; 219 220 mutex_lock(&dev->pci_status_mutex); 221 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 222 err = pci_enable_device(pdev); 223 if (!err) 224 dev->pci_status = MLX5_PCI_STATUS_ENABLED; 225 } 226 mutex_unlock(&dev->pci_status_mutex); 227 228 return err; 229} 230 231static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 232{ 233 struct pci_dev *pdev = dev->pdev; 234 235 mutex_lock(&dev->pci_status_mutex); 236 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 237 pci_disable_device(pdev); 238 dev->pci_status = MLX5_PCI_STATUS_DISABLED; 239 } 240 mutex_unlock(&dev->pci_status_mutex); 241} 242 243static int request_bar(struct pci_dev *pdev) 244{ 245 int err = 0; 246 247 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 248 device_printf((&pdev->dev)->bsddev, "ERR: ""Missing registers BAR, aborting\n"); 249 return -ENODEV; 250 } 251 252 err = pci_request_regions(pdev, DRIVER_NAME); 253 if (err) 254 device_printf((&pdev->dev)->bsddev, "ERR: ""Couldn't get PCI resources, aborting\n"); 255 256 return err; 257} 258 259static void release_bar(struct pci_dev *pdev) 260{ 261 pci_release_regions(pdev); 262} 263 264static int mlx5_enable_msix(struct mlx5_core_dev *dev) 265{ 266 struct mlx5_priv *priv = &dev->priv; 267 struct mlx5_eq_table *table = &priv->eq_table; 268 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq); 269 int limit = dev->msix_eqvec; 270 int nvec = MLX5_EQ_VEC_COMP_BASE; 271 int i; 272 273 if (limit > 0) 274 nvec += limit; 275 else 276 nvec += MLX5_CAP_GEN(dev, num_ports) * num_online_cpus(); 277 278 nvec = min_t(int, nvec, num_eqs); 279 if (nvec <= MLX5_EQ_VEC_COMP_BASE) 280 return -ENOMEM; 281 282 priv->msix_arr = kzalloc(nvec * sizeof(*priv->msix_arr), GFP_KERNEL); 283 284 priv->irq_info = kzalloc(nvec * sizeof(*priv->irq_info), GFP_KERNEL); 285 286 for (i = 0; i < nvec; i++) 287 priv->msix_arr[i].entry = i; 288 289 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr, 290 MLX5_EQ_VEC_COMP_BASE + 1, nvec); 291 if (nvec < 0) 292 return nvec; 293 294 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE; 295 296 return 0; 297 298} 299 300static void mlx5_disable_msix(struct mlx5_core_dev *dev) 301{ 302 struct mlx5_priv *priv = &dev->priv; 303 304 pci_disable_msix(dev->pdev); 305 kfree(priv->irq_info); 306 kfree(priv->msix_arr); 307} 308 309struct mlx5_reg_host_endianess { 310 u8 he; 311 u8 rsvd[15]; 312}; 313 314 315#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 316 317enum { 318 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 319 MLX5_DEV_CAP_FLAG_DCT | 320 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR, 321}; 322 323static u16 to_fw_pkey_sz(u32 size) 324{ 325 switch (size) { 326 case 128: 327 return 0; 328 case 256: 329 return 1; 330 case 512: 331 return 2; 332 case 1024: 333 return 3; 334 case 2048: 335 return 4; 336 case 4096: 337 return 5; 338 default: 339 printf("mlx5_core: WARN: ""invalid pkey table size %d\n", size); 340 return 0; 341 } 342} 343 344static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 345 enum mlx5_cap_type cap_type, 346 enum mlx5_cap_mode cap_mode) 347{ 348 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 349 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 350 void *out, *hca_caps; 351 u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 352 int err; 353 354 memset(in, 0, sizeof(in)); 355 out = kzalloc(out_sz, GFP_KERNEL); 356 357 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 358 MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 359 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz); 360 if (err) { 361 mlx5_core_warn(dev, 362 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 363 cap_type, cap_mode, err); 364 goto query_ex; 365 } 366 367 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 368 369 switch (cap_mode) { 370 case HCA_CAP_OPMOD_GET_MAX: 371 memcpy(dev->hca_caps_max[cap_type], hca_caps, 372 MLX5_UN_SZ_BYTES(hca_cap_union)); 373 break; 374 case HCA_CAP_OPMOD_GET_CUR: 375 memcpy(dev->hca_caps_cur[cap_type], hca_caps, 376 MLX5_UN_SZ_BYTES(hca_cap_union)); 377 break; 378 default: 379 mlx5_core_warn(dev, 380 "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 381 cap_type, cap_mode); 382 err = -EINVAL; 383 break; 384 } 385query_ex: 386 kfree(out); 387 return err; 388} 389 390int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 391{ 392 int ret; 393 394 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 395 if (ret) 396 return ret; 397 398 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 399} 400 401static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz) 402{ 403 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0}; 404 405 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 406 407 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out)); 408} 409 410static int handle_hca_cap(struct mlx5_core_dev *dev) 411{ 412 void *set_ctx = NULL; 413 struct mlx5_profile *prof = dev->profile; 414 int err = -ENOMEM; 415 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 416 void *set_hca_cap; 417 418 set_ctx = kzalloc(set_sz, GFP_KERNEL); 419 420 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 421 if (err) 422 goto query_ex; 423 424 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 425 capability); 426 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL], 427 MLX5_ST_SZ_BYTES(cmd_hca_cap)); 428 429 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 430 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 431 128); 432 /* we limit the size of the pkey table to 128 entries for now */ 433 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 434 to_fw_pkey_sz(128)); 435 436 if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 437 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 438 prof->log_max_qp); 439 440 /* disable cmdif checksum */ 441 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 442 443 /* enable drain sigerr */ 444 MLX5_SET(cmd_hca_cap, set_hca_cap, drain_sigerr, 1); 445 446 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 447 448 err = set_caps(dev, set_ctx, set_sz); 449 450query_ex: 451 kfree(set_ctx); 452 return err; 453} 454 455static int handle_hca_cap_atomic(struct mlx5_core_dev *dev) 456{ 457 void *set_ctx; 458 void *set_hca_cap; 459 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 460 int req_endianness; 461 int err; 462 463 if (MLX5_CAP_GEN(dev, atomic)) { 464 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 465 if (err) 466 return err; 467 } else { 468 return 0; 469 } 470 471 req_endianness = 472 MLX5_CAP_ATOMIC(dev, 473 supported_atomic_req_8B_endianess_mode_1); 474 475 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 476 return 0; 477 478 set_ctx = kzalloc(set_sz, GFP_KERNEL); 479 if (!set_ctx) 480 return -ENOMEM; 481 482 MLX5_SET(set_hca_cap_in, set_ctx, op_mod, 483 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC << 1); 484 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 485 486 /* Set requestor to host endianness */ 487 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode, 488 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 489 490 err = set_caps(dev, set_ctx, set_sz); 491 492 kfree(set_ctx); 493 return err; 494} 495 496static int set_hca_ctrl(struct mlx5_core_dev *dev) 497{ 498 struct mlx5_reg_host_endianess he_in; 499 struct mlx5_reg_host_endianess he_out; 500 int err; 501 502 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH && 503 !MLX5_CAP_GEN(dev, roce)) 504 return 0; 505 506 memset(&he_in, 0, sizeof(he_in)); 507 he_in.he = MLX5_SET_HOST_ENDIANNESS; 508 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 509 &he_out, sizeof(he_out), 510 MLX5_REG_HOST_ENDIANNESS, 0, 1); 511 return err; 512} 513 514static int mlx5_core_enable_hca(struct mlx5_core_dev *dev) 515{ 516 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0}; 517 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0}; 518 519 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 520 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); 521} 522 523static int mlx5_core_disable_hca(struct mlx5_core_dev *dev) 524{ 525 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0}; 526 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0}; 527 528 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 529 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 530} 531 532static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 533{ 534 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0}; 535 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0}; 536 u32 sup_issi; 537 int err; 538 539 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 540 541 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), query_out, sizeof(query_out)); 542 if (err) { 543 u32 syndrome; 544 u8 status; 545 546 mlx5_cmd_mbox_status(query_out, &status, &syndrome); 547 if (status == MLX5_CMD_STAT_BAD_OP_ERR) { 548 pr_debug("Only ISSI 0 is supported\n"); 549 return 0; 550 } 551 552 printf("mlx5_core: ERR: ""failed to query ISSI\n"); 553 return err; 554 } 555 556 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 557 558 if (sup_issi & (1 << 1)) { 559 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0}; 560 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0}; 561 562 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 563 MLX5_SET(set_issi_in, set_in, current_issi, 1); 564 565 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), set_out, sizeof(set_out)); 566 if (err) { 567 printf("mlx5_core: ERR: ""failed to set ISSI=1 err(%d)\n", err); 568 return err; 569 } 570 571 dev->issi = 1; 572 573 return 0; 574 } else if (sup_issi & (1 << 0)) { 575 return 0; 576 } 577 578 return -ENOTSUPP; 579} 580 581 582int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn) 583{ 584 struct mlx5_eq_table *table = &dev->priv.eq_table; 585 struct mlx5_eq *eq; 586 int err = -ENOENT; 587 588 spin_lock(&table->lock); 589 list_for_each_entry(eq, &table->comp_eqs_list, list) { 590 if (eq->index == vector) { 591 *eqn = eq->eqn; 592 *irqn = eq->irqn; 593 err = 0; 594 break; 595 } 596 } 597 spin_unlock(&table->lock); 598 599 return err; 600} 601EXPORT_SYMBOL(mlx5_vector2eqn); 602 603int mlx5_rename_eq(struct mlx5_core_dev *dev, int eq_ix, char *name) 604{ 605 struct mlx5_priv *priv = &dev->priv; 606 struct mlx5_eq_table *table = &priv->eq_table; 607 struct mlx5_eq *eq; 608 int err = -ENOENT; 609 610 spin_lock(&table->lock); 611 list_for_each_entry(eq, &table->comp_eqs_list, list) { 612 if (eq->index == eq_ix) { 613 int irq_ix = eq_ix + MLX5_EQ_VEC_COMP_BASE; 614 615 snprintf(priv->irq_info[irq_ix].name, MLX5_MAX_IRQ_NAME, 616 "%s-%d", name, eq_ix); 617 618 err = 0; 619 break; 620 } 621 } 622 spin_unlock(&table->lock); 623 624 return err; 625} 626 627static void free_comp_eqs(struct mlx5_core_dev *dev) 628{ 629 struct mlx5_eq_table *table = &dev->priv.eq_table; 630 struct mlx5_eq *eq, *n; 631 632 spin_lock(&table->lock); 633 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { 634 list_del(&eq->list); 635 spin_unlock(&table->lock); 636 if (mlx5_destroy_unmap_eq(dev, eq)) 637 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n", 638 eq->eqn); 639 kfree(eq); 640 spin_lock(&table->lock); 641 } 642 spin_unlock(&table->lock); 643} 644 645static int alloc_comp_eqs(struct mlx5_core_dev *dev) 646{ 647 struct mlx5_eq_table *table = &dev->priv.eq_table; 648 char name[MLX5_MAX_IRQ_NAME]; 649 struct mlx5_eq *eq; 650 int ncomp_vec; 651 int nent; 652 int err; 653 int i; 654 655 INIT_LIST_HEAD(&table->comp_eqs_list); 656 ncomp_vec = table->num_comp_vectors; 657 nent = MLX5_COMP_EQ_SIZE; 658 for (i = 0; i < ncomp_vec; i++) { 659 eq = kzalloc(sizeof(*eq), GFP_KERNEL); 660 661 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i); 662 err = mlx5_create_map_eq(dev, eq, 663 i + MLX5_EQ_VEC_COMP_BASE, nent, 0, 664 name, &dev->priv.uuari.uars[0]); 665 if (err) { 666 kfree(eq); 667 goto clean; 668 } 669 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn); 670 eq->index = i; 671 spin_lock(&table->lock); 672 list_add_tail(&eq->list, &table->comp_eqs_list); 673 spin_unlock(&table->lock); 674 } 675 676 return 0; 677 678clean: 679 free_comp_eqs(dev); 680 return err; 681} 682 683static int map_bf_area(struct mlx5_core_dev *dev) 684{ 685 resource_size_t bf_start = pci_resource_start(dev->pdev, 0); 686 resource_size_t bf_len = pci_resource_len(dev->pdev, 0); 687 688 dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len); 689 690 return dev->priv.bf_mapping ? 0 : -ENOMEM; 691} 692 693static void unmap_bf_area(struct mlx5_core_dev *dev) 694{ 695 if (dev->priv.bf_mapping) 696 io_mapping_free(dev->priv.bf_mapping); 697} 698 699static inline int fw_initializing(struct mlx5_core_dev *dev) 700{ 701 return ioread32be(&dev->iseg->initializing) >> 31; 702} 703 704static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili) 705{ 706 u64 end = jiffies + msecs_to_jiffies(max_wait_mili); 707 int err = 0; 708 709 while (fw_initializing(dev)) { 710 if (time_after(jiffies, end)) { 711 err = -EBUSY; 712 break; 713 } 714 msleep(FW_INIT_WAIT_MS); 715 } 716 717 return err; 718} 719 720static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv) 721{ 722 struct mlx5_device_context *dev_ctx; 723 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv); 724 725 dev_ctx = kzalloc(sizeof(*dev_ctx), GFP_KERNEL); 726 if (!dev_ctx) 727 return; 728 729 dev_ctx->intf = intf; 730 CURVNET_SET_QUIET(vnet0); 731 dev_ctx->context = intf->add(dev); 732 CURVNET_RESTORE(); 733 734 if (dev_ctx->context) { 735 spin_lock_irq(&priv->ctx_lock); 736 list_add_tail(&dev_ctx->list, &priv->ctx_list); 737 spin_unlock_irq(&priv->ctx_lock); 738 } else { 739 kfree(dev_ctx); 740 } 741} 742 743static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv) 744{ 745 struct mlx5_device_context *dev_ctx; 746 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv); 747 748 list_for_each_entry(dev_ctx, &priv->ctx_list, list) 749 if (dev_ctx->intf == intf) { 750 spin_lock_irq(&priv->ctx_lock); 751 list_del(&dev_ctx->list); 752 spin_unlock_irq(&priv->ctx_lock); 753 754 intf->remove(dev, dev_ctx->context); 755 kfree(dev_ctx); 756 return; 757 } 758} 759 760int 761mlx5_register_device(struct mlx5_core_dev *dev) 762{ 763 struct mlx5_priv *priv = &dev->priv; 764 struct mlx5_interface *intf; 765 766 mutex_lock(&intf_mutex); 767 list_add_tail(&priv->dev_list, &dev_list); 768 list_for_each_entry(intf, &intf_list, list) 769 mlx5_add_device(intf, priv); 770 mutex_unlock(&intf_mutex); 771 772 return 0; 773} 774 775void 776mlx5_unregister_device(struct mlx5_core_dev *dev) 777{ 778 struct mlx5_priv *priv = &dev->priv; 779 struct mlx5_interface *intf; 780 781 mutex_lock(&intf_mutex); 782 list_for_each_entry(intf, &intf_list, list) 783 mlx5_remove_device(intf, priv); 784 list_del(&priv->dev_list); 785 mutex_unlock(&intf_mutex); 786} 787 788int mlx5_register_interface(struct mlx5_interface *intf) 789{ 790 struct mlx5_priv *priv; 791 792 if (!intf->add || !intf->remove) 793 return -EINVAL; 794 795 mutex_lock(&intf_mutex); 796 list_add_tail(&intf->list, &intf_list); 797 list_for_each_entry(priv, &dev_list, dev_list) 798 mlx5_add_device(intf, priv); 799 mutex_unlock(&intf_mutex); 800 801 return 0; 802} 803EXPORT_SYMBOL(mlx5_register_interface); 804 805void mlx5_unregister_interface(struct mlx5_interface *intf) 806{ 807 struct mlx5_priv *priv; 808 809 mutex_lock(&intf_mutex); 810 list_for_each_entry(priv, &dev_list, dev_list) 811 mlx5_remove_device(intf, priv); 812 list_del(&intf->list); 813 mutex_unlock(&intf_mutex); 814} 815EXPORT_SYMBOL(mlx5_unregister_interface); 816 817void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol) 818{ 819 struct mlx5_priv *priv = &mdev->priv; 820 struct mlx5_device_context *dev_ctx; 821 unsigned long flags; 822 void *result = NULL; 823 824 spin_lock_irqsave(&priv->ctx_lock, flags); 825 826 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list) 827 if ((dev_ctx->intf->protocol == protocol) && 828 dev_ctx->intf->get_dev) { 829 result = dev_ctx->intf->get_dev(dev_ctx->context); 830 break; 831 } 832 833 spin_unlock_irqrestore(&priv->ctx_lock, flags); 834 835 return result; 836} 837EXPORT_SYMBOL(mlx5_get_protocol_dev); 838 839static int mlx5_auto_fw_update; 840SYSCTL_INT(_hw_mlx5, OID_AUTO, auto_fw_update, CTLFLAG_RDTUN | CTLFLAG_NOFETCH, 841 &mlx5_auto_fw_update, 0, 842 "Allow automatic firmware update on driver start"); 843static int 844mlx5_firmware_update(struct mlx5_core_dev *dev) 845{ 846 const struct firmware *fw; 847 int err; 848 849 TUNABLE_INT_FETCH("hw.mlx5.auto_fw_update", &mlx5_auto_fw_update); 850 if (!mlx5_auto_fw_update) 851 return (0); 852 fw = firmware_get("mlx5fw_mfa"); 853 if (fw) { 854 err = mlx5_firmware_flash(dev, fw); 855 firmware_put(fw, FIRMWARE_UNLOAD); 856 } 857 else 858 return (-ENOENT); 859 860 return err; 861} 862 863static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 864{ 865 struct pci_dev *pdev = dev->pdev; 866 int err = 0; 867 868 pci_set_drvdata(dev->pdev, dev); 869 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN); 870 priv->name[MLX5_MAX_NAME_LEN - 1] = 0; 871 872 mutex_init(&priv->pgdir_mutex); 873 INIT_LIST_HEAD(&priv->pgdir_list); 874 spin_lock_init(&priv->mkey_lock); 875 876 priv->numa_node = NUMA_NO_NODE; 877 878 err = mlx5_pci_enable_device(dev); 879 if (err) { 880 device_printf((&pdev->dev)->bsddev, "ERR: ""Cannot enable PCI device, aborting\n"); 881 goto err_dbg; 882 } 883 884 err = request_bar(pdev); 885 if (err) { 886 device_printf((&pdev->dev)->bsddev, "ERR: ""error requesting BARs, aborting\n"); 887 goto err_disable; 888 } 889 890 pci_set_master(pdev); 891 892 err = set_dma_caps(pdev); 893 if (err) { 894 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed setting DMA capabilities mask, aborting\n"); 895 goto err_clr_master; 896 } 897 898 dev->iseg_base = pci_resource_start(dev->pdev, 0); 899 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 900 if (!dev->iseg) { 901 err = -ENOMEM; 902 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed mapping initialization segment, aborting\n"); 903 goto err_clr_master; 904 } 905 906 return 0; 907 908err_clr_master: 909 release_bar(dev->pdev); 910err_disable: 911 mlx5_pci_disable_device(dev); 912err_dbg: 913 return err; 914} 915 916static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 917{ 918 iounmap(dev->iseg); 919 release_bar(dev->pdev); 920 mlx5_pci_disable_device(dev); 921} 922 923static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 924{ 925 struct pci_dev *pdev = dev->pdev; 926 int err; 927 928 err = mlx5_vsc_find_cap(dev); 929 if (err) 930 dev_err(&pdev->dev, "Unable to find vendor specific capabilities\n"); 931 932 err = mlx5_query_hca_caps(dev); 933 if (err) { 934 dev_err(&pdev->dev, "query hca failed\n"); 935 goto out; 936 } 937 938 err = mlx5_query_board_id(dev); 939 if (err) { 940 dev_err(&pdev->dev, "query board id failed\n"); 941 goto out; 942 } 943 944 err = mlx5_eq_init(dev); 945 if (err) { 946 dev_err(&pdev->dev, "failed to initialize eq\n"); 947 goto out; 948 } 949 950 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock); 951 952 err = mlx5_init_cq_table(dev); 953 if (err) { 954 dev_err(&pdev->dev, "failed to initialize cq table\n"); 955 goto err_eq_cleanup; 956 } 957 958 mlx5_init_qp_table(dev); 959 mlx5_init_srq_table(dev); 960 mlx5_init_mr_table(dev); 961 962 mlx5_init_reserved_gids(dev); 963 mlx5_fpga_init(dev); 964 965 return 0; 966 967err_eq_cleanup: 968 mlx5_eq_cleanup(dev); 969 970out: 971 return err; 972} 973 974static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 975{ 976 mlx5_fpga_cleanup(dev); 977 mlx5_cleanup_reserved_gids(dev); 978 mlx5_cleanup_mr_table(dev); 979 mlx5_cleanup_srq_table(dev); 980 mlx5_cleanup_qp_table(dev); 981 mlx5_cleanup_cq_table(dev); 982 mlx5_eq_cleanup(dev); 983} 984 985static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, 986 bool boot) 987{ 988 struct pci_dev *pdev = dev->pdev; 989 int err; 990 991 mutex_lock(&dev->intf_state_mutex); 992 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 993 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n", 994 __func__); 995 goto out; 996 } 997 998 device_printf((&pdev->dev)->bsddev, "INFO: ""firmware version: %d.%d.%d\n", fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev)); 999 1000 /* 1001 * On load removing any previous indication of internal error, 1002 * device is up 1003 */ 1004 dev->state = MLX5_DEVICE_STATE_UP; 1005 1006 err = mlx5_cmd_init(dev); 1007 if (err) { 1008 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed initializing command interface, aborting\n"); 1009 goto out_err; 1010 } 1011 1012 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI); 1013 if (err) { 1014 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""Firmware over %d MS in initializing state, aborting\n", FW_INIT_TIMEOUT_MILI); 1015 goto err_cmd_cleanup; 1016 } 1017 1018 err = mlx5_core_enable_hca(dev); 1019 if (err) { 1020 device_printf((&pdev->dev)->bsddev, "ERR: ""enable hca failed\n"); 1021 goto err_cmd_cleanup; 1022 } 1023 1024 err = mlx5_core_set_issi(dev); 1025 if (err) { 1026 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to set issi\n"); 1027 goto err_disable_hca; 1028 } 1029 1030 err = mlx5_pagealloc_start(dev); 1031 if (err) { 1032 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_pagealloc_start failed\n"); 1033 goto err_disable_hca; 1034 } 1035 1036 err = mlx5_satisfy_startup_pages(dev, 1); 1037 if (err) { 1038 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to allocate boot pages\n"); 1039 goto err_pagealloc_stop; 1040 } 1041 1042 err = set_hca_ctrl(dev); 1043 if (err) { 1044 device_printf((&pdev->dev)->bsddev, "ERR: ""set_hca_ctrl failed\n"); 1045 goto reclaim_boot_pages; 1046 } 1047 1048 err = handle_hca_cap(dev); 1049 if (err) { 1050 device_printf((&pdev->dev)->bsddev, "ERR: ""handle_hca_cap failed\n"); 1051 goto reclaim_boot_pages; 1052 } 1053 1054 err = handle_hca_cap_atomic(dev); 1055 if (err) { 1056 device_printf((&pdev->dev)->bsddev, "ERR: ""handle_hca_cap_atomic failed\n"); 1057 goto reclaim_boot_pages; 1058 } 1059 1060 err = mlx5_satisfy_startup_pages(dev, 0); 1061 if (err) { 1062 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to allocate init pages\n"); 1063 goto reclaim_boot_pages; 1064 } 1065 1066 err = mlx5_cmd_init_hca(dev); 1067 if (err) { 1068 device_printf((&pdev->dev)->bsddev, "ERR: ""init hca failed\n"); 1069 goto reclaim_boot_pages; 1070 } 1071 1072 mlx5_start_health_poll(dev); 1073 1074 if (boot && mlx5_init_once(dev, priv)) { 1075 dev_err(&pdev->dev, "sw objs init failed\n"); 1076 goto err_stop_poll; 1077 } 1078 1079 err = mlx5_enable_msix(dev); 1080 if (err) { 1081 device_printf((&pdev->dev)->bsddev, "ERR: ""enable msix failed\n"); 1082 goto err_cleanup_once; 1083 } 1084 1085 err = mlx5_alloc_uuars(dev, &priv->uuari); 1086 if (err) { 1087 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed allocating uar, aborting\n"); 1088 goto err_disable_msix; 1089 } 1090 1091 err = mlx5_start_eqs(dev); 1092 if (err) { 1093 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to start pages and async EQs\n"); 1094 goto err_free_uar; 1095 } 1096 1097 err = alloc_comp_eqs(dev); 1098 if (err) { 1099 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to alloc completion EQs\n"); 1100 goto err_stop_eqs; 1101 } 1102 1103 if (map_bf_area(dev)) 1104 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to map blue flame area\n"); 1105 1106 err = mlx5_init_fs(dev); 1107 if (err) { 1108 mlx5_core_err(dev, "flow steering init %d\n", err); 1109 goto err_free_comp_eqs; 1110 } 1111 1112 err = mlx5_fpga_device_start(dev); 1113 if (err) { 1114 dev_err(&pdev->dev, "fpga device start failed %d\n", err); 1115 goto err_fpga_start; 1116 } 1117 1118 err = mlx5_register_device(dev); 1119 if (err) { 1120 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err); 1121 goto err_fs; 1122 } 1123 1124 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1125 1126out: 1127 mutex_unlock(&dev->intf_state_mutex); 1128 return 0; 1129 1130err_fpga_start: 1131err_fs: 1132 mlx5_cleanup_fs(dev); 1133 1134err_free_comp_eqs: 1135 free_comp_eqs(dev); 1136 unmap_bf_area(dev); 1137 1138err_stop_eqs: 1139 mlx5_stop_eqs(dev); 1140 1141err_free_uar: 1142 mlx5_free_uuars(dev, &priv->uuari); 1143 1144err_disable_msix: 1145 mlx5_disable_msix(dev); 1146 1147err_cleanup_once: 1148 if (boot) 1149 mlx5_cleanup_once(dev); 1150 1151err_stop_poll: 1152 mlx5_stop_health_poll(dev, boot); 1153 if (mlx5_cmd_teardown_hca(dev)) { 1154 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""tear_down_hca failed, skip cleanup\n"); 1155 goto out_err; 1156 } 1157 1158reclaim_boot_pages: 1159 mlx5_reclaim_startup_pages(dev); 1160 1161err_pagealloc_stop: 1162 mlx5_pagealloc_stop(dev); 1163 1164err_disable_hca: 1165 mlx5_core_disable_hca(dev); 1166 1167err_cmd_cleanup: 1168 mlx5_cmd_cleanup(dev); 1169 1170out_err: 1171 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1172 mutex_unlock(&dev->intf_state_mutex); 1173 1174 return err; 1175} 1176 1177static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, 1178 bool cleanup) 1179{ 1180 int err = 0; 1181 1182 if (cleanup) 1183 mlx5_drain_health_recovery(dev); 1184 1185 mutex_lock(&dev->intf_state_mutex); 1186 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1187 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n", __func__); 1188 if (cleanup) 1189 mlx5_cleanup_once(dev); 1190 goto out; 1191 } 1192 1193 mlx5_unregister_device(dev); 1194 1195 mlx5_fpga_device_stop(dev); 1196 mlx5_cleanup_fs(dev); 1197 unmap_bf_area(dev); 1198 mlx5_wait_for_reclaim_vfs_pages(dev); 1199 free_comp_eqs(dev); 1200 mlx5_stop_eqs(dev); 1201 mlx5_free_uuars(dev, &priv->uuari); 1202 mlx5_disable_msix(dev); 1203 if (cleanup) 1204 mlx5_cleanup_once(dev); 1205 mlx5_stop_health_poll(dev, cleanup); 1206 err = mlx5_cmd_teardown_hca(dev); 1207 if (err) { 1208 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""tear_down_hca failed, skip cleanup\n"); 1209 goto out; 1210 } 1211 mlx5_pagealloc_stop(dev); 1212 mlx5_reclaim_startup_pages(dev); 1213 mlx5_core_disable_hca(dev); 1214 mlx5_cmd_cleanup(dev); 1215 1216out: 1217 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1218 mutex_unlock(&dev->intf_state_mutex); 1219 return err; 1220} 1221 1222void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event, 1223 unsigned long param) 1224{ 1225 struct mlx5_priv *priv = &dev->priv; 1226 struct mlx5_device_context *dev_ctx; 1227 unsigned long flags; 1228 1229 spin_lock_irqsave(&priv->ctx_lock, flags); 1230 1231 list_for_each_entry(dev_ctx, &priv->ctx_list, list) 1232 if (dev_ctx->intf->event) 1233 dev_ctx->intf->event(dev, dev_ctx->context, event, param); 1234 1235 spin_unlock_irqrestore(&priv->ctx_lock, flags); 1236} 1237 1238struct mlx5_core_event_handler { 1239 void (*event)(struct mlx5_core_dev *dev, 1240 enum mlx5_dev_event event, 1241 void *data); 1242}; 1243 1244static int init_one(struct pci_dev *pdev, 1245 const struct pci_device_id *id) 1246{ 1247 struct mlx5_core_dev *dev; 1248 struct mlx5_priv *priv; 1249 device_t bsddev = pdev->dev.bsddev; 1250 int err; 1251 1252 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 1253 priv = &dev->priv; 1254 if (id) 1255 priv->pci_dev_data = id->driver_data; 1256 1257 if (mlx5_prof_sel < 0 || mlx5_prof_sel >= ARRAY_SIZE(profiles)) { 1258 device_printf(bsddev, "WARN: selected profile out of range, selecting default (%d)\n", MLX5_DEFAULT_PROF); 1259 mlx5_prof_sel = MLX5_DEFAULT_PROF; 1260 } 1261 dev->profile = &profiles[mlx5_prof_sel]; 1262 dev->pdev = pdev; 1263 dev->event = mlx5_core_event; 1264 1265 /* Set desc */ 1266 device_set_desc(bsddev, mlx5_version); 1267 1268 sysctl_ctx_init(&dev->sysctl_ctx); 1269 SYSCTL_ADD_INT(&dev->sysctl_ctx, 1270 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1271 OID_AUTO, "msix_eqvec", CTLFLAG_RDTUN, &dev->msix_eqvec, 0, 1272 "Maximum number of MSIX event queue vectors, if set"); 1273 SYSCTL_ADD_INT(&dev->sysctl_ctx, 1274 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1275 OID_AUTO, "power_status", CTLFLAG_RD, &dev->pwr_status, 0, 1276 "0:Invalid 1:Sufficient 2:Insufficient"); 1277 SYSCTL_ADD_INT(&dev->sysctl_ctx, 1278 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1279 OID_AUTO, "power_value", CTLFLAG_RD, &dev->pwr_value, 0, 1280 "Current power value in Watts"); 1281 1282 INIT_LIST_HEAD(&priv->ctx_list); 1283 spin_lock_init(&priv->ctx_lock); 1284 mutex_init(&dev->pci_status_mutex); 1285 mutex_init(&dev->intf_state_mutex); 1286 err = mlx5_pci_init(dev, priv); 1287 if (err) { 1288 device_printf(bsddev, "ERR: mlx5_pci_init failed %d\n", err); 1289 goto clean_dev; 1290 } 1291 1292 err = mlx5_health_init(dev); 1293 if (err) { 1294 device_printf(bsddev, "ERR: mlx5_health_init failed %d\n", err); 1295 goto close_pci; 1296 } 1297 1298 mlx5_pagealloc_init(dev); 1299 1300 err = mlx5_load_one(dev, priv, true); 1301 if (err) { 1302 device_printf(bsddev, "ERR: mlx5_load_one failed %d\n", err); 1303 goto clean_health; 1304 } 1305 1306 mlx5_fwdump_prep(dev); 1307 1308 mlx5_firmware_update(dev); 1309 1310 pci_save_state(bsddev); 1311 return 0; 1312 1313clean_health: 1314 mlx5_pagealloc_cleanup(dev); 1315 mlx5_health_cleanup(dev); 1316close_pci: 1317 mlx5_pci_close(dev, priv); 1318clean_dev: 1319 sysctl_ctx_free(&dev->sysctl_ctx); 1320 kfree(dev); 1321 return err; 1322} 1323 1324static void remove_one(struct pci_dev *pdev) 1325{ 1326 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1327 struct mlx5_priv *priv = &dev->priv; 1328 1329 if (mlx5_unload_one(dev, priv, true)) { 1330 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n"); 1331 mlx5_health_cleanup(dev); 1332 return; 1333 } 1334 1335 mlx5_fwdump_clean(dev); 1336 mlx5_pagealloc_cleanup(dev); 1337 mlx5_health_cleanup(dev); 1338 mlx5_pci_close(dev, priv); 1339 pci_set_drvdata(pdev, NULL); 1340 sysctl_ctx_free(&dev->sysctl_ctx); 1341 kfree(dev); 1342} 1343 1344static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 1345 pci_channel_state_t state) 1346{ 1347 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1348 struct mlx5_priv *priv = &dev->priv; 1349 1350 dev_info(&pdev->dev, "%s was called\n", __func__); 1351 mlx5_enter_error_state(dev, false); 1352 mlx5_unload_one(dev, priv, false); 1353 1354 if (state) { 1355 mlx5_drain_health_wq(dev); 1356 mlx5_pci_disable_device(dev); 1357 } 1358 1359 return state == pci_channel_io_perm_failure ? 1360 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 1361} 1362 1363static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 1364{ 1365 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1366 int err = 0; 1367 1368 dev_info(&pdev->dev, "%s was called\n", __func__); 1369 1370 err = mlx5_pci_enable_device(dev); 1371 if (err) { 1372 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n" 1373 , __func__, err); 1374 return PCI_ERS_RESULT_DISCONNECT; 1375 } 1376 pci_set_master(pdev); 1377 pci_set_powerstate(pdev->dev.bsddev, PCI_POWERSTATE_D0); 1378 pci_restore_state(pdev->dev.bsddev); 1379 pci_save_state(pdev->dev.bsddev); 1380 1381 return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; 1382} 1383 1384/* wait for the device to show vital signs. For now we check 1385 * that we can read the device ID and that the health buffer 1386 * shows a non zero value which is different than 0xffffffff 1387 */ 1388static void wait_vital(struct pci_dev *pdev) 1389{ 1390 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1391 struct mlx5_core_health *health = &dev->priv.health; 1392 const int niter = 100; 1393 u32 count; 1394 u16 did; 1395 int i; 1396 1397 /* Wait for firmware to be ready after reset */ 1398 msleep(1000); 1399 for (i = 0; i < niter; i++) { 1400 if (pci_read_config_word(pdev, 2, &did)) { 1401 dev_warn(&pdev->dev, "failed reading config word\n"); 1402 break; 1403 } 1404 if (did == pdev->device) { 1405 dev_info(&pdev->dev, "device ID correctly read after %d iterations\n", i); 1406 break; 1407 } 1408 msleep(50); 1409 } 1410 if (i == niter) 1411 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__); 1412 1413 for (i = 0; i < niter; i++) { 1414 count = ioread32be(health->health_counter); 1415 if (count && count != 0xffffffff) { 1416 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i); 1417 break; 1418 } 1419 msleep(50); 1420 } 1421 1422 if (i == niter) 1423 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__); 1424} 1425 1426static void mlx5_pci_resume(struct pci_dev *pdev) 1427{ 1428 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1429 struct mlx5_priv *priv = &dev->priv; 1430 int err; 1431 1432 dev_info(&pdev->dev, "%s was called\n", __func__); 1433 1434 wait_vital(pdev); 1435 1436 err = mlx5_load_one(dev, priv, false); 1437 if (err) 1438 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n" 1439 , __func__, err); 1440 else 1441 dev_info(&pdev->dev, "%s: device recovered\n", __func__); 1442} 1443 1444static const struct pci_error_handlers mlx5_err_handler = { 1445 .error_detected = mlx5_pci_err_detected, 1446 .slot_reset = mlx5_pci_slot_reset, 1447 .resume = mlx5_pci_resume 1448}; 1449 1450static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 1451{ 1452 bool fast_teardown, force_teardown; 1453 int err; 1454 1455 if (!mlx5_fast_unload_enabled) { 1456 mlx5_core_dbg(dev, "fast unload is disabled by user\n"); 1457 return -EOPNOTSUPP; 1458 } 1459 1460 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1461 force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1462 1463 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1464 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1465 1466 if (!fast_teardown && !force_teardown) 1467 return -EOPNOTSUPP; 1468 1469 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1470 mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 1471 return -EAGAIN; 1472 } 1473 1474 /* Panic tear down fw command will stop the PCI bus communication 1475 * with the HCA, so the health polll is no longer needed. 1476 */ 1477 mlx5_drain_health_wq(dev); 1478 mlx5_stop_health_poll(dev, false); 1479 1480 err = mlx5_cmd_fast_teardown_hca(dev); 1481 if (!err) 1482 goto done; 1483 1484 err = mlx5_cmd_force_teardown_hca(dev); 1485 if (!err) 1486 goto done; 1487 1488 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", err); 1489 mlx5_start_health_poll(dev); 1490 return err; 1491done: 1492 mlx5_enter_error_state(dev, true); 1493 return 0; 1494} 1495 1496static void mlx5_disable_interrupts(struct mlx5_core_dev *mdev) 1497{ 1498 int nvec = mdev->priv.eq_table.num_comp_vectors + MLX5_EQ_VEC_COMP_BASE; 1499 int x; 1500 1501 mdev->priv.disable_irqs = 1; 1502 1503 /* wait for all IRQ handlers to finish processing */ 1504 for (x = 0; x != nvec; x++) 1505 synchronize_irq(mdev->priv.msix_arr[x].vector); 1506} 1507 1508static void shutdown_one(struct pci_dev *pdev) 1509{ 1510 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1511 struct mlx5_priv *priv = &dev->priv; 1512 int err; 1513 1514 /* enter polling mode */ 1515 mlx5_cmd_use_polling(dev); 1516 1517 /* disable all interrupts */ 1518 mlx5_disable_interrupts(dev); 1519 1520 err = mlx5_try_fast_unload(dev); 1521 if (err) 1522 mlx5_unload_one(dev, priv, false); 1523 mlx5_pci_disable_device(dev); 1524} 1525 1526static const struct pci_device_id mlx5_core_pci_table[] = { 1527 { PCI_VDEVICE(MELLANOX, 4113) }, /* Connect-IB */ 1528 { PCI_VDEVICE(MELLANOX, 4114) }, /* Connect-IB VF */ 1529 { PCI_VDEVICE(MELLANOX, 4115) }, /* ConnectX-4 */ 1530 { PCI_VDEVICE(MELLANOX, 4116) }, /* ConnectX-4 VF */ 1531 { PCI_VDEVICE(MELLANOX, 4117) }, /* ConnectX-4LX */ 1532 { PCI_VDEVICE(MELLANOX, 4118) }, /* ConnectX-4LX VF */ 1533 { PCI_VDEVICE(MELLANOX, 4119) }, /* ConnectX-5 */ 1534 { PCI_VDEVICE(MELLANOX, 4120) }, /* ConnectX-5 VF */ 1535 { PCI_VDEVICE(MELLANOX, 4121) }, 1536 { PCI_VDEVICE(MELLANOX, 4122) }, 1537 { PCI_VDEVICE(MELLANOX, 4123) }, 1538 { PCI_VDEVICE(MELLANOX, 4124) }, 1539 { PCI_VDEVICE(MELLANOX, 4125) }, 1540 { PCI_VDEVICE(MELLANOX, 4126) }, 1541 { PCI_VDEVICE(MELLANOX, 4127) }, 1542 { PCI_VDEVICE(MELLANOX, 4128) }, 1543 { PCI_VDEVICE(MELLANOX, 4129) }, 1544 { PCI_VDEVICE(MELLANOX, 4130) }, 1545 { PCI_VDEVICE(MELLANOX, 4131) }, 1546 { PCI_VDEVICE(MELLANOX, 4132) }, 1547 { PCI_VDEVICE(MELLANOX, 4133) }, 1548 { PCI_VDEVICE(MELLANOX, 4134) }, 1549 { PCI_VDEVICE(MELLANOX, 4135) }, 1550 { PCI_VDEVICE(MELLANOX, 4136) }, 1551 { PCI_VDEVICE(MELLANOX, 4137) }, 1552 { PCI_VDEVICE(MELLANOX, 4138) }, 1553 { PCI_VDEVICE(MELLANOX, 4139) }, 1554 { PCI_VDEVICE(MELLANOX, 4140) }, 1555 { PCI_VDEVICE(MELLANOX, 4141) }, 1556 { PCI_VDEVICE(MELLANOX, 4142) }, 1557 { PCI_VDEVICE(MELLANOX, 4143) }, 1558 { PCI_VDEVICE(MELLANOX, 4144) }, 1559 { 0, } 1560}; 1561 1562MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 1563 1564void mlx5_disable_device(struct mlx5_core_dev *dev) 1565{ 1566 mlx5_pci_err_detected(dev->pdev, 0); 1567} 1568 1569void mlx5_recover_device(struct mlx5_core_dev *dev) 1570{ 1571 mlx5_pci_disable_device(dev); 1572 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) 1573 mlx5_pci_resume(dev->pdev); 1574} 1575 1576struct pci_driver mlx5_core_driver = { 1577 .name = DRIVER_NAME, 1578 .id_table = mlx5_core_pci_table, 1579 .shutdown = shutdown_one, 1580 .probe = init_one, 1581 .remove = remove_one, 1582 .err_handler = &mlx5_err_handler 1583}; 1584 1585static int __init init(void) 1586{ 1587 int err; 1588 1589 err = pci_register_driver(&mlx5_core_driver); 1590 if (err) 1591 goto err_debug; 1592 1593 err = mlx5_fwdump_init(); 1594 if (err) 1595 goto err_fwdump; 1596 1597 return 0; 1598 1599err_fwdump: 1600 pci_unregister_driver(&mlx5_core_driver); 1601 1602err_debug: 1603 return err; 1604} 1605 1606static void __exit cleanup(void) 1607{ 1608 mlx5_fwdump_fini(); 1609 pci_unregister_driver(&mlx5_core_driver); 1610} 1611 1612module_init(init); 1613module_exit(cleanup); 1614