mlx5_main.c revision 347853
1290650Shselasky/*- 2347819Shselasky * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved. 3290650Shselasky * 4290650Shselasky * Redistribution and use in source and binary forms, with or without 5290650Shselasky * modification, are permitted provided that the following conditions 6290650Shselasky * are met: 7290650Shselasky * 1. Redistributions of source code must retain the above copyright 8290650Shselasky * notice, this list of conditions and the following disclaimer. 9290650Shselasky * 2. Redistributions in binary form must reproduce the above copyright 10290650Shselasky * notice, this list of conditions and the following disclaimer in the 11290650Shselasky * documentation and/or other materials provided with the distribution. 12290650Shselasky * 13290650Shselasky * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14290650Shselasky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15290650Shselasky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16290650Shselasky * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17290650Shselasky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18290650Shselasky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19290650Shselasky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20290650Shselasky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21290650Shselasky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22290650Shselasky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23290650Shselasky * SUCH DAMAGE. 24290650Shselasky * 25290650Shselasky * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_core/mlx5_main.c 347853 2019-05-16 18:05:16Z hselasky $ 26290650Shselasky */ 27290650Shselasky 28290650Shselasky#include <linux/kmod.h> 29290650Shselasky#include <linux/module.h> 30290650Shselasky#include <linux/errno.h> 31290650Shselasky#include <linux/pci.h> 32290650Shselasky#include <linux/dma-mapping.h> 33290650Shselasky#include <linux/slab.h> 34290650Shselasky#include <linux/io-mapping.h> 35290650Shselasky#include <linux/interrupt.h> 36347802Shselasky#include <linux/hardirq.h> 37290650Shselasky#include <dev/mlx5/driver.h> 38290650Shselasky#include <dev/mlx5/cq.h> 39290650Shselasky#include <dev/mlx5/qp.h> 40290650Shselasky#include <dev/mlx5/srq.h> 41290650Shselasky#include <linux/delay.h> 42290650Shselasky#include <dev/mlx5/mlx5_ifc.h> 43341958Shselasky#include <dev/mlx5/mlx5_fpga/core.h> 44341958Shselasky#include <dev/mlx5/mlx5_lib/mlx5.h> 45290650Shselasky#include "mlx5_core.h" 46329200Shselasky#include "fs_core.h" 47290650Shselasky 48341948Shselaskystatic const char mlx5_version[] = "Mellanox Core driver " 49341948Shselasky DRIVER_VERSION " (" DRIVER_RELDATE ")"; 50290650ShselaskyMODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 51290650ShselaskyMODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver"); 52290650ShselaskyMODULE_LICENSE("Dual BSD/GPL"); 53290650ShselaskyMODULE_DEPEND(mlx5, linuxkpi, 1, 1, 1); 54347839ShselaskyMODULE_DEPEND(mlx5, mlxfw, 1, 1, 1); 55347847ShselaskyMODULE_DEPEND(mlx5, firmware, 1, 1, 1); 56290650ShselaskyMODULE_VERSION(mlx5, 1); 57290650Shselasky 58347835ShselaskySYSCTL_NODE(_hw, OID_AUTO, mlx5, CTLFLAG_RW, 0, "mlx5 hardware controls"); 59347835Shselasky 60290650Shselaskyint mlx5_core_debug_mask; 61347835ShselaskySYSCTL_INT(_hw_mlx5, OID_AUTO, debug_mask, CTLFLAG_RWTUN, 62347835Shselasky &mlx5_core_debug_mask, 0, 63347835Shselasky "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 64290650Shselasky 65290650Shselasky#define MLX5_DEFAULT_PROF 2 66347835Shselaskystatic int mlx5_prof_sel = MLX5_DEFAULT_PROF; 67347835ShselaskySYSCTL_INT(_hw_mlx5, OID_AUTO, prof_sel, CTLFLAG_RWTUN, 68347835Shselasky &mlx5_prof_sel, 0, 69347835Shselasky "profile selector. Valid range 0 - 2"); 70290650Shselasky 71347819Shselaskystatic int mlx5_fast_unload_enabled = 1; 72347819ShselaskySYSCTL_INT(_hw_mlx5, OID_AUTO, fast_unload_enabled, CTLFLAG_RWTUN, 73347819Shselasky &mlx5_fast_unload_enabled, 0, 74347819Shselasky "Set to enable fast unload. Clear to disable."); 75347819Shselasky 76290650Shselasky#define NUMA_NO_NODE -1 77290650Shselasky 78290650Shselaskystatic LIST_HEAD(intf_list); 79290650Shselaskystatic LIST_HEAD(dev_list); 80290650Shselaskystatic DEFINE_MUTEX(intf_mutex); 81290650Shselasky 82290650Shselaskystruct mlx5_device_context { 83290650Shselasky struct list_head list; 84290650Shselasky struct mlx5_interface *intf; 85290650Shselasky void *context; 86290650Shselasky}; 87290650Shselasky 88329209Shselaskyenum { 89329209Shselasky MLX5_ATOMIC_REQ_MODE_BE = 0x0, 90329209Shselasky MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 91329209Shselasky}; 92329209Shselasky 93290650Shselaskystatic struct mlx5_profile profiles[] = { 94290650Shselasky [0] = { 95290650Shselasky .mask = 0, 96290650Shselasky }, 97290650Shselasky [1] = { 98290650Shselasky .mask = MLX5_PROF_MASK_QP_SIZE, 99290650Shselasky .log_max_qp = 12, 100290650Shselasky }, 101290650Shselasky [2] = { 102290650Shselasky .mask = MLX5_PROF_MASK_QP_SIZE | 103290650Shselasky MLX5_PROF_MASK_MR_CACHE, 104290650Shselasky .log_max_qp = 17, 105290650Shselasky .mr_cache[0] = { 106290650Shselasky .size = 500, 107290650Shselasky .limit = 250 108290650Shselasky }, 109290650Shselasky .mr_cache[1] = { 110290650Shselasky .size = 500, 111290650Shselasky .limit = 250 112290650Shselasky }, 113290650Shselasky .mr_cache[2] = { 114290650Shselasky .size = 500, 115290650Shselasky .limit = 250 116290650Shselasky }, 117290650Shselasky .mr_cache[3] = { 118290650Shselasky .size = 500, 119290650Shselasky .limit = 250 120290650Shselasky }, 121290650Shselasky .mr_cache[4] = { 122290650Shselasky .size = 500, 123290650Shselasky .limit = 250 124290650Shselasky }, 125290650Shselasky .mr_cache[5] = { 126290650Shselasky .size = 500, 127290650Shselasky .limit = 250 128290650Shselasky }, 129290650Shselasky .mr_cache[6] = { 130290650Shselasky .size = 500, 131290650Shselasky .limit = 250 132290650Shselasky }, 133290650Shselasky .mr_cache[7] = { 134290650Shselasky .size = 500, 135290650Shselasky .limit = 250 136290650Shselasky }, 137290650Shselasky .mr_cache[8] = { 138290650Shselasky .size = 500, 139290650Shselasky .limit = 250 140290650Shselasky }, 141290650Shselasky .mr_cache[9] = { 142290650Shselasky .size = 500, 143290650Shselasky .limit = 250 144290650Shselasky }, 145290650Shselasky .mr_cache[10] = { 146290650Shselasky .size = 500, 147290650Shselasky .limit = 250 148290650Shselasky }, 149290650Shselasky .mr_cache[11] = { 150290650Shselasky .size = 500, 151290650Shselasky .limit = 250 152290650Shselasky }, 153290650Shselasky .mr_cache[12] = { 154290650Shselasky .size = 64, 155290650Shselasky .limit = 32 156290650Shselasky }, 157290650Shselasky .mr_cache[13] = { 158290650Shselasky .size = 32, 159290650Shselasky .limit = 16 160290650Shselasky }, 161290650Shselasky .mr_cache[14] = { 162290650Shselasky .size = 16, 163290650Shselasky .limit = 8 164290650Shselasky }, 165290650Shselasky }, 166290650Shselasky [3] = { 167290650Shselasky .mask = MLX5_PROF_MASK_QP_SIZE, 168290650Shselasky .log_max_qp = 17, 169290650Shselasky }, 170290650Shselasky}; 171290650Shselasky 172290650Shselaskystatic int set_dma_caps(struct pci_dev *pdev) 173290650Shselasky{ 174290650Shselasky int err; 175290650Shselasky 176290650Shselasky err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 177290650Shselasky if (err) { 178290650Shselasky device_printf((&pdev->dev)->bsddev, "WARN: ""Warning: couldn't set 64-bit PCI DMA mask\n"); 179290650Shselasky err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 180290650Shselasky if (err) { 181290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""Can't set PCI DMA mask, aborting\n"); 182290650Shselasky return err; 183290650Shselasky } 184290650Shselasky } 185290650Shselasky 186290650Shselasky err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 187290650Shselasky if (err) { 188290650Shselasky device_printf((&pdev->dev)->bsddev, "WARN: ""Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 189290650Shselasky err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 190290650Shselasky if (err) { 191290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""Can't set consistent PCI DMA mask, aborting\n"); 192290650Shselasky return err; 193290650Shselasky } 194290650Shselasky } 195290650Shselasky 196290650Shselasky dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 197290650Shselasky return err; 198290650Shselasky} 199290650Shselasky 200331580Shselaskystatic int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 201331580Shselasky{ 202331580Shselasky struct pci_dev *pdev = dev->pdev; 203331580Shselasky int err = 0; 204331580Shselasky 205331580Shselasky mutex_lock(&dev->pci_status_mutex); 206331580Shselasky if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 207331580Shselasky err = pci_enable_device(pdev); 208331580Shselasky if (!err) 209331580Shselasky dev->pci_status = MLX5_PCI_STATUS_ENABLED; 210331580Shselasky } 211331580Shselasky mutex_unlock(&dev->pci_status_mutex); 212331580Shselasky 213331580Shselasky return err; 214331580Shselasky} 215331580Shselasky 216331580Shselaskystatic void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 217331580Shselasky{ 218331580Shselasky struct pci_dev *pdev = dev->pdev; 219331580Shselasky 220331580Shselasky mutex_lock(&dev->pci_status_mutex); 221331580Shselasky if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 222331580Shselasky pci_disable_device(pdev); 223331580Shselasky dev->pci_status = MLX5_PCI_STATUS_DISABLED; 224331580Shselasky } 225331580Shselasky mutex_unlock(&dev->pci_status_mutex); 226331580Shselasky} 227331580Shselasky 228290650Shselaskystatic int request_bar(struct pci_dev *pdev) 229290650Shselasky{ 230290650Shselasky int err = 0; 231290650Shselasky 232290650Shselasky if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 233290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""Missing registers BAR, aborting\n"); 234290650Shselasky return -ENODEV; 235290650Shselasky } 236290650Shselasky 237290650Shselasky err = pci_request_regions(pdev, DRIVER_NAME); 238290650Shselasky if (err) 239290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""Couldn't get PCI resources, aborting\n"); 240290650Shselasky 241290650Shselasky return err; 242290650Shselasky} 243290650Shselasky 244290650Shselaskystatic void release_bar(struct pci_dev *pdev) 245290650Shselasky{ 246290650Shselasky pci_release_regions(pdev); 247290650Shselasky} 248290650Shselasky 249290650Shselaskystatic int mlx5_enable_msix(struct mlx5_core_dev *dev) 250290650Shselasky{ 251290650Shselasky struct mlx5_priv *priv = &dev->priv; 252290650Shselasky struct mlx5_eq_table *table = &priv->eq_table; 253290650Shselasky int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq); 254338554Shselasky int limit = dev->msix_eqvec; 255337112Shselasky int nvec = MLX5_EQ_VEC_COMP_BASE; 256290650Shselasky int i; 257290650Shselasky 258337112Shselasky if (limit > 0) 259337112Shselasky nvec += limit; 260337112Shselasky else 261337112Shselasky nvec += MLX5_CAP_GEN(dev, num_ports) * num_online_cpus(); 262337112Shselasky 263290650Shselasky nvec = min_t(int, nvec, num_eqs); 264290650Shselasky if (nvec <= MLX5_EQ_VEC_COMP_BASE) 265290650Shselasky return -ENOMEM; 266290650Shselasky 267290650Shselasky priv->msix_arr = kzalloc(nvec * sizeof(*priv->msix_arr), GFP_KERNEL); 268290650Shselasky 269290650Shselasky priv->irq_info = kzalloc(nvec * sizeof(*priv->irq_info), GFP_KERNEL); 270290650Shselasky 271290650Shselasky for (i = 0; i < nvec; i++) 272290650Shselasky priv->msix_arr[i].entry = i; 273290650Shselasky 274290650Shselasky nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr, 275290650Shselasky MLX5_EQ_VEC_COMP_BASE + 1, nvec); 276290650Shselasky if (nvec < 0) 277290650Shselasky return nvec; 278290650Shselasky 279290650Shselasky table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE; 280290650Shselasky 281290650Shselasky return 0; 282290650Shselasky 283290650Shselasky} 284290650Shselasky 285290650Shselaskystatic void mlx5_disable_msix(struct mlx5_core_dev *dev) 286290650Shselasky{ 287290650Shselasky struct mlx5_priv *priv = &dev->priv; 288290650Shselasky 289290650Shselasky pci_disable_msix(dev->pdev); 290290650Shselasky kfree(priv->irq_info); 291290650Shselasky kfree(priv->msix_arr); 292290650Shselasky} 293290650Shselasky 294290650Shselaskystruct mlx5_reg_host_endianess { 295290650Shselasky u8 he; 296290650Shselasky u8 rsvd[15]; 297290650Shselasky}; 298290650Shselasky 299290650Shselasky 300290650Shselasky#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 301290650Shselasky 302290650Shselaskyenum { 303290650Shselasky MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 304306233Shselasky MLX5_DEV_CAP_FLAG_DCT | 305306233Shselasky MLX5_DEV_CAP_FLAG_DRAIN_SIGERR, 306290650Shselasky}; 307290650Shselasky 308290650Shselaskystatic u16 to_fw_pkey_sz(u32 size) 309290650Shselasky{ 310290650Shselasky switch (size) { 311290650Shselasky case 128: 312290650Shselasky return 0; 313290650Shselasky case 256: 314290650Shselasky return 1; 315290650Shselasky case 512: 316290650Shselasky return 2; 317290650Shselasky case 1024: 318290650Shselasky return 3; 319290650Shselasky case 2048: 320290650Shselasky return 4; 321290650Shselasky case 4096: 322290650Shselasky return 5; 323290650Shselasky default: 324290650Shselasky printf("mlx5_core: WARN: ""invalid pkey table size %d\n", size); 325290650Shselasky return 0; 326290650Shselasky } 327290650Shselasky} 328290650Shselasky 329331807Shselaskystatic int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 330331807Shselasky enum mlx5_cap_type cap_type, 331331807Shselasky enum mlx5_cap_mode cap_mode) 332290650Shselasky{ 333290650Shselasky u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 334290650Shselasky int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 335290650Shselasky void *out, *hca_caps; 336290650Shselasky u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 337290650Shselasky int err; 338290650Shselasky 339290650Shselasky memset(in, 0, sizeof(in)); 340290650Shselasky out = kzalloc(out_sz, GFP_KERNEL); 341290650Shselasky 342290650Shselasky MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 343290650Shselasky MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 344290650Shselasky err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz); 345290650Shselasky if (err) { 346290650Shselasky mlx5_core_warn(dev, 347290650Shselasky "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 348290650Shselasky cap_type, cap_mode, err); 349290650Shselasky goto query_ex; 350290650Shselasky } 351290650Shselasky 352290650Shselasky hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 353290650Shselasky 354290650Shselasky switch (cap_mode) { 355290650Shselasky case HCA_CAP_OPMOD_GET_MAX: 356290650Shselasky memcpy(dev->hca_caps_max[cap_type], hca_caps, 357290650Shselasky MLX5_UN_SZ_BYTES(hca_cap_union)); 358290650Shselasky break; 359290650Shselasky case HCA_CAP_OPMOD_GET_CUR: 360290650Shselasky memcpy(dev->hca_caps_cur[cap_type], hca_caps, 361290650Shselasky MLX5_UN_SZ_BYTES(hca_cap_union)); 362290650Shselasky break; 363290650Shselasky default: 364290650Shselasky mlx5_core_warn(dev, 365290650Shselasky "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 366290650Shselasky cap_type, cap_mode); 367290650Shselasky err = -EINVAL; 368290650Shselasky break; 369290650Shselasky } 370290650Shselaskyquery_ex: 371290650Shselasky kfree(out); 372290650Shselasky return err; 373290650Shselasky} 374290650Shselasky 375331807Shselaskyint mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 376331807Shselasky{ 377331807Shselasky int ret; 378331807Shselasky 379331807Shselasky ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 380331807Shselasky if (ret) 381331807Shselasky return ret; 382331807Shselasky 383331807Shselasky return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 384331807Shselasky} 385331807Shselasky 386290650Shselaskystatic int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz) 387290650Shselasky{ 388331807Shselasky u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0}; 389290650Shselasky 390290650Shselasky MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 391290650Shselasky 392331807Shselasky return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out)); 393290650Shselasky} 394290650Shselasky 395290650Shselaskystatic int handle_hca_cap(struct mlx5_core_dev *dev) 396290650Shselasky{ 397290650Shselasky void *set_ctx = NULL; 398290650Shselasky struct mlx5_profile *prof = dev->profile; 399290650Shselasky int err = -ENOMEM; 400290650Shselasky int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 401290650Shselasky void *set_hca_cap; 402290650Shselasky 403290650Shselasky set_ctx = kzalloc(set_sz, GFP_KERNEL); 404290650Shselasky 405331807Shselasky err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 406290650Shselasky if (err) 407290650Shselasky goto query_ex; 408290650Shselasky 409290650Shselasky set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 410290650Shselasky capability); 411290650Shselasky memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL], 412290650Shselasky MLX5_ST_SZ_BYTES(cmd_hca_cap)); 413290650Shselasky 414290650Shselasky mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 415290650Shselasky mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 416290650Shselasky 128); 417290650Shselasky /* we limit the size of the pkey table to 128 entries for now */ 418290650Shselasky MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 419290650Shselasky to_fw_pkey_sz(128)); 420290650Shselasky 421290650Shselasky if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 422290650Shselasky MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 423290650Shselasky prof->log_max_qp); 424290650Shselasky 425290650Shselasky /* disable cmdif checksum */ 426290650Shselasky MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 427290650Shselasky 428306233Shselasky /* enable drain sigerr */ 429306233Shselasky MLX5_SET(cmd_hca_cap, set_hca_cap, drain_sigerr, 1); 430306233Shselasky 431290650Shselasky MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 432290650Shselasky 433290650Shselasky err = set_caps(dev, set_ctx, set_sz); 434290650Shselasky 435290650Shselaskyquery_ex: 436290650Shselasky kfree(set_ctx); 437290650Shselasky return err; 438290650Shselasky} 439290650Shselasky 440329209Shselaskystatic int handle_hca_cap_atomic(struct mlx5_core_dev *dev) 441329209Shselasky{ 442329209Shselasky void *set_ctx; 443329209Shselasky void *set_hca_cap; 444329209Shselasky int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 445329209Shselasky int req_endianness; 446329209Shselasky int err; 447329209Shselasky 448329209Shselasky if (MLX5_CAP_GEN(dev, atomic)) { 449331807Shselasky err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 450329209Shselasky if (err) 451329209Shselasky return err; 452329209Shselasky } else { 453329209Shselasky return 0; 454329209Shselasky } 455329209Shselasky 456329209Shselasky req_endianness = 457329209Shselasky MLX5_CAP_ATOMIC(dev, 458329209Shselasky supported_atomic_req_8B_endianess_mode_1); 459329209Shselasky 460329209Shselasky if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 461329209Shselasky return 0; 462329209Shselasky 463329209Shselasky set_ctx = kzalloc(set_sz, GFP_KERNEL); 464329209Shselasky if (!set_ctx) 465329209Shselasky return -ENOMEM; 466329209Shselasky 467329209Shselasky MLX5_SET(set_hca_cap_in, set_ctx, op_mod, 468329209Shselasky MLX5_SET_HCA_CAP_OP_MOD_ATOMIC << 1); 469329209Shselasky set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 470329209Shselasky 471329209Shselasky /* Set requestor to host endianness */ 472329209Shselasky MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode, 473329209Shselasky MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 474329209Shselasky 475329209Shselasky err = set_caps(dev, set_ctx, set_sz); 476329209Shselasky 477329209Shselasky kfree(set_ctx); 478329209Shselasky return err; 479329209Shselasky} 480329209Shselasky 481290650Shselaskystatic int set_hca_ctrl(struct mlx5_core_dev *dev) 482290650Shselasky{ 483290650Shselasky struct mlx5_reg_host_endianess he_in; 484290650Shselasky struct mlx5_reg_host_endianess he_out; 485290650Shselasky int err; 486290650Shselasky 487306233Shselasky if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH && 488306233Shselasky !MLX5_CAP_GEN(dev, roce)) 489306233Shselasky return 0; 490306233Shselasky 491290650Shselasky memset(&he_in, 0, sizeof(he_in)); 492290650Shselasky he_in.he = MLX5_SET_HOST_ENDIANNESS; 493290650Shselasky err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 494290650Shselasky &he_out, sizeof(he_out), 495290650Shselasky MLX5_REG_HOST_ENDIANNESS, 0, 1); 496290650Shselasky return err; 497290650Shselasky} 498290650Shselasky 499290650Shselaskystatic int mlx5_core_enable_hca(struct mlx5_core_dev *dev) 500290650Shselasky{ 501331807Shselasky u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0}; 502331807Shselasky u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0}; 503290650Shselasky 504290650Shselasky MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 505331807Shselasky return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); 506290650Shselasky} 507290650Shselasky 508290650Shselaskystatic int mlx5_core_disable_hca(struct mlx5_core_dev *dev) 509290650Shselasky{ 510331807Shselasky u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0}; 511331807Shselasky u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0}; 512290650Shselasky 513290650Shselasky MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 514331807Shselasky return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 515290650Shselasky} 516290650Shselasky 517290650Shselaskystatic int mlx5_core_set_issi(struct mlx5_core_dev *dev) 518290650Shselasky{ 519331807Shselasky u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0}; 520331807Shselasky u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0}; 521331807Shselasky u32 sup_issi; 522290650Shselasky int err; 523290650Shselasky 524290650Shselasky MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 525290650Shselasky 526331807Shselasky err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), query_out, sizeof(query_out)); 527290650Shselasky if (err) { 528331807Shselasky u32 syndrome; 529331807Shselasky u8 status; 530331807Shselasky 531331807Shselasky mlx5_cmd_mbox_status(query_out, &status, &syndrome); 532331807Shselasky if (status == MLX5_CMD_STAT_BAD_OP_ERR) { 533290650Shselasky pr_debug("Only ISSI 0 is supported\n"); 534290650Shselasky return 0; 535290650Shselasky } 536290650Shselasky 537290650Shselasky printf("mlx5_core: ERR: ""failed to query ISSI\n"); 538290650Shselasky return err; 539290650Shselasky } 540290650Shselasky 541290650Shselasky sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 542290650Shselasky 543290650Shselasky if (sup_issi & (1 << 1)) { 544331807Shselasky u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0}; 545331807Shselasky u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0}; 546290650Shselasky 547290650Shselasky MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 548290650Shselasky MLX5_SET(set_issi_in, set_in, current_issi, 1); 549290650Shselasky 550331807Shselasky err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), set_out, sizeof(set_out)); 551290650Shselasky if (err) { 552331807Shselasky printf("mlx5_core: ERR: ""failed to set ISSI=1 err(%d)\n", err); 553290650Shselasky return err; 554290650Shselasky } 555290650Shselasky 556290650Shselasky dev->issi = 1; 557290650Shselasky 558290650Shselasky return 0; 559290650Shselasky } else if (sup_issi & (1 << 0)) { 560290650Shselasky return 0; 561290650Shselasky } 562290650Shselasky 563290650Shselasky return -ENOTSUPP; 564290650Shselasky} 565290650Shselasky 566290650Shselasky 567290650Shselaskyint mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn) 568290650Shselasky{ 569290650Shselasky struct mlx5_eq_table *table = &dev->priv.eq_table; 570290650Shselasky struct mlx5_eq *eq; 571290650Shselasky int err = -ENOENT; 572290650Shselasky 573290650Shselasky spin_lock(&table->lock); 574290650Shselasky list_for_each_entry(eq, &table->comp_eqs_list, list) { 575290650Shselasky if (eq->index == vector) { 576290650Shselasky *eqn = eq->eqn; 577290650Shselasky *irqn = eq->irqn; 578290650Shselasky err = 0; 579290650Shselasky break; 580290650Shselasky } 581290650Shselasky } 582290650Shselasky spin_unlock(&table->lock); 583290650Shselasky 584290650Shselasky return err; 585290650Shselasky} 586290650ShselaskyEXPORT_SYMBOL(mlx5_vector2eqn); 587290650Shselasky 588290650Shselaskyint mlx5_rename_eq(struct mlx5_core_dev *dev, int eq_ix, char *name) 589290650Shselasky{ 590290650Shselasky struct mlx5_priv *priv = &dev->priv; 591290650Shselasky struct mlx5_eq_table *table = &priv->eq_table; 592290650Shselasky struct mlx5_eq *eq; 593290650Shselasky int err = -ENOENT; 594290650Shselasky 595290650Shselasky spin_lock(&table->lock); 596290650Shselasky list_for_each_entry(eq, &table->comp_eqs_list, list) { 597290650Shselasky if (eq->index == eq_ix) { 598290650Shselasky int irq_ix = eq_ix + MLX5_EQ_VEC_COMP_BASE; 599290650Shselasky 600290650Shselasky snprintf(priv->irq_info[irq_ix].name, MLX5_MAX_IRQ_NAME, 601290650Shselasky "%s-%d", name, eq_ix); 602290650Shselasky 603290650Shselasky err = 0; 604290650Shselasky break; 605290650Shselasky } 606290650Shselasky } 607290650Shselasky spin_unlock(&table->lock); 608290650Shselasky 609290650Shselasky return err; 610290650Shselasky} 611290650Shselasky 612290650Shselaskystatic void free_comp_eqs(struct mlx5_core_dev *dev) 613290650Shselasky{ 614290650Shselasky struct mlx5_eq_table *table = &dev->priv.eq_table; 615290650Shselasky struct mlx5_eq *eq, *n; 616290650Shselasky 617290650Shselasky spin_lock(&table->lock); 618290650Shselasky list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { 619290650Shselasky list_del(&eq->list); 620290650Shselasky spin_unlock(&table->lock); 621290650Shselasky if (mlx5_destroy_unmap_eq(dev, eq)) 622290650Shselasky mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n", 623290650Shselasky eq->eqn); 624290650Shselasky kfree(eq); 625290650Shselasky spin_lock(&table->lock); 626290650Shselasky } 627290650Shselasky spin_unlock(&table->lock); 628290650Shselasky} 629290650Shselasky 630290650Shselaskystatic int alloc_comp_eqs(struct mlx5_core_dev *dev) 631290650Shselasky{ 632290650Shselasky struct mlx5_eq_table *table = &dev->priv.eq_table; 633290650Shselasky char name[MLX5_MAX_IRQ_NAME]; 634290650Shselasky struct mlx5_eq *eq; 635290650Shselasky int ncomp_vec; 636290650Shselasky int nent; 637290650Shselasky int err; 638290650Shselasky int i; 639290650Shselasky 640290650Shselasky INIT_LIST_HEAD(&table->comp_eqs_list); 641290650Shselasky ncomp_vec = table->num_comp_vectors; 642290650Shselasky nent = MLX5_COMP_EQ_SIZE; 643290650Shselasky for (i = 0; i < ncomp_vec; i++) { 644290650Shselasky eq = kzalloc(sizeof(*eq), GFP_KERNEL); 645290650Shselasky 646290650Shselasky snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i); 647290650Shselasky err = mlx5_create_map_eq(dev, eq, 648290650Shselasky i + MLX5_EQ_VEC_COMP_BASE, nent, 0, 649290650Shselasky name, &dev->priv.uuari.uars[0]); 650290650Shselasky if (err) { 651290650Shselasky kfree(eq); 652290650Shselasky goto clean; 653290650Shselasky } 654290650Shselasky mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn); 655290650Shselasky eq->index = i; 656290650Shselasky spin_lock(&table->lock); 657290650Shselasky list_add_tail(&eq->list, &table->comp_eqs_list); 658290650Shselasky spin_unlock(&table->lock); 659290650Shselasky } 660290650Shselasky 661290650Shselasky return 0; 662290650Shselasky 663290650Shselaskyclean: 664290650Shselasky free_comp_eqs(dev); 665290650Shselasky return err; 666290650Shselasky} 667290650Shselasky 668290650Shselaskystatic int map_bf_area(struct mlx5_core_dev *dev) 669290650Shselasky{ 670290650Shselasky resource_size_t bf_start = pci_resource_start(dev->pdev, 0); 671290650Shselasky resource_size_t bf_len = pci_resource_len(dev->pdev, 0); 672290650Shselasky 673290650Shselasky dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len); 674290650Shselasky 675290650Shselasky return dev->priv.bf_mapping ? 0 : -ENOMEM; 676290650Shselasky} 677290650Shselasky 678290650Shselaskystatic void unmap_bf_area(struct mlx5_core_dev *dev) 679290650Shselasky{ 680290650Shselasky if (dev->priv.bf_mapping) 681290650Shselasky io_mapping_free(dev->priv.bf_mapping); 682290650Shselasky} 683290650Shselasky 684290650Shselaskystatic inline int fw_initializing(struct mlx5_core_dev *dev) 685290650Shselasky{ 686290650Shselasky return ioread32be(&dev->iseg->initializing) >> 31; 687290650Shselasky} 688290650Shselasky 689290650Shselaskystatic int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili) 690290650Shselasky{ 691290650Shselasky u64 end = jiffies + msecs_to_jiffies(max_wait_mili); 692290650Shselasky int err = 0; 693290650Shselasky 694290650Shselasky while (fw_initializing(dev)) { 695290650Shselasky if (time_after(jiffies, end)) { 696290650Shselasky err = -EBUSY; 697290650Shselasky break; 698290650Shselasky } 699290650Shselasky msleep(FW_INIT_WAIT_MS); 700290650Shselasky } 701290650Shselasky 702290650Shselasky return err; 703290650Shselasky} 704290650Shselasky 705331580Shselaskystatic void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv) 706290650Shselasky{ 707331580Shselasky struct mlx5_device_context *dev_ctx; 708331580Shselasky struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv); 709331580Shselasky 710331580Shselasky dev_ctx = kzalloc(sizeof(*dev_ctx), GFP_KERNEL); 711331580Shselasky if (!dev_ctx) 712331580Shselasky return; 713331580Shselasky 714331580Shselasky dev_ctx->intf = intf; 715331580Shselasky CURVNET_SET_QUIET(vnet0); 716331580Shselasky dev_ctx->context = intf->add(dev); 717331580Shselasky CURVNET_RESTORE(); 718331580Shselasky 719331580Shselasky if (dev_ctx->context) { 720331580Shselasky spin_lock_irq(&priv->ctx_lock); 721331580Shselasky list_add_tail(&dev_ctx->list, &priv->ctx_list); 722331580Shselasky spin_unlock_irq(&priv->ctx_lock); 723331580Shselasky } else { 724331580Shselasky kfree(dev_ctx); 725331580Shselasky } 726331580Shselasky} 727331580Shselasky 728331580Shselaskystatic void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv) 729331580Shselasky{ 730331580Shselasky struct mlx5_device_context *dev_ctx; 731331580Shselasky struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv); 732331580Shselasky 733331580Shselasky list_for_each_entry(dev_ctx, &priv->ctx_list, list) 734331580Shselasky if (dev_ctx->intf == intf) { 735331580Shselasky spin_lock_irq(&priv->ctx_lock); 736331580Shselasky list_del(&dev_ctx->list); 737331580Shselasky spin_unlock_irq(&priv->ctx_lock); 738331580Shselasky 739331580Shselasky intf->remove(dev, dev_ctx->context); 740331580Shselasky kfree(dev_ctx); 741331580Shselasky return; 742331580Shselasky } 743331580Shselasky} 744331580Shselasky 745341958Shselaskyint 746341958Shselaskymlx5_register_device(struct mlx5_core_dev *dev) 747331580Shselasky{ 748290650Shselasky struct mlx5_priv *priv = &dev->priv; 749331580Shselasky struct mlx5_interface *intf; 750290650Shselasky 751331580Shselasky mutex_lock(&intf_mutex); 752331580Shselasky list_add_tail(&priv->dev_list, &dev_list); 753331580Shselasky list_for_each_entry(intf, &intf_list, list) 754331580Shselasky mlx5_add_device(intf, priv); 755331580Shselasky mutex_unlock(&intf_mutex); 756331580Shselasky 757331580Shselasky return 0; 758331580Shselasky} 759331580Shselasky 760341958Shselaskyvoid 761341958Shselaskymlx5_unregister_device(struct mlx5_core_dev *dev) 762331580Shselasky{ 763331580Shselasky struct mlx5_priv *priv = &dev->priv; 764331580Shselasky struct mlx5_interface *intf; 765331580Shselasky 766331580Shselasky mutex_lock(&intf_mutex); 767331580Shselasky list_for_each_entry(intf, &intf_list, list) 768331580Shselasky mlx5_remove_device(intf, priv); 769331580Shselasky list_del(&priv->dev_list); 770331580Shselasky mutex_unlock(&intf_mutex); 771331580Shselasky} 772331580Shselasky 773331580Shselaskyint mlx5_register_interface(struct mlx5_interface *intf) 774331580Shselasky{ 775331580Shselasky struct mlx5_priv *priv; 776331580Shselasky 777331580Shselasky if (!intf->add || !intf->remove) 778331580Shselasky return -EINVAL; 779331580Shselasky 780331580Shselasky mutex_lock(&intf_mutex); 781331580Shselasky list_add_tail(&intf->list, &intf_list); 782331580Shselasky list_for_each_entry(priv, &dev_list, dev_list) 783331580Shselasky mlx5_add_device(intf, priv); 784331580Shselasky mutex_unlock(&intf_mutex); 785331580Shselasky 786331580Shselasky return 0; 787331580Shselasky} 788331580ShselaskyEXPORT_SYMBOL(mlx5_register_interface); 789331580Shselasky 790331580Shselaskyvoid mlx5_unregister_interface(struct mlx5_interface *intf) 791331580Shselasky{ 792331580Shselasky struct mlx5_priv *priv; 793331580Shselasky 794331580Shselasky mutex_lock(&intf_mutex); 795331580Shselasky list_for_each_entry(priv, &dev_list, dev_list) 796331580Shselasky mlx5_remove_device(intf, priv); 797331580Shselasky list_del(&intf->list); 798331580Shselasky mutex_unlock(&intf_mutex); 799331580Shselasky} 800331580ShselaskyEXPORT_SYMBOL(mlx5_unregister_interface); 801331580Shselasky 802331580Shselaskyvoid *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol) 803331580Shselasky{ 804331580Shselasky struct mlx5_priv *priv = &mdev->priv; 805331580Shselasky struct mlx5_device_context *dev_ctx; 806331580Shselasky unsigned long flags; 807331580Shselasky void *result = NULL; 808331580Shselasky 809331580Shselasky spin_lock_irqsave(&priv->ctx_lock, flags); 810331580Shselasky 811331580Shselasky list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list) 812331580Shselasky if ((dev_ctx->intf->protocol == protocol) && 813331580Shselasky dev_ctx->intf->get_dev) { 814331580Shselasky result = dev_ctx->intf->get_dev(dev_ctx->context); 815331580Shselasky break; 816331580Shselasky } 817331580Shselasky 818331580Shselasky spin_unlock_irqrestore(&priv->ctx_lock, flags); 819331580Shselasky 820331580Shselasky return result; 821331580Shselasky} 822331580ShselaskyEXPORT_SYMBOL(mlx5_get_protocol_dev); 823331580Shselasky 824347853Shselaskystatic int mlx5_auto_fw_update; 825347853ShselaskySYSCTL_INT(_hw_mlx5, OID_AUTO, auto_fw_update, CTLFLAG_RDTUN | CTLFLAG_NOFETCH, 826347853Shselasky &mlx5_auto_fw_update, 0, 827347853Shselasky "Allow automatic firmware update on driver start"); 828347847Shselaskystatic int 829347847Shselaskymlx5_firmware_update(struct mlx5_core_dev *dev) 830347847Shselasky{ 831347847Shselasky const struct firmware *fw; 832347847Shselasky int err; 833347847Shselasky 834347853Shselasky TUNABLE_INT_FETCH("hw.mlx5.auto_fw_update", &mlx5_auto_fw_update); 835347853Shselasky if (!mlx5_auto_fw_update) 836347853Shselasky return (0); 837347847Shselasky fw = firmware_get("mlx5fw_mfa"); 838347847Shselasky if (fw) { 839347847Shselasky err = mlx5_firmware_flash(dev, fw); 840347847Shselasky firmware_put(fw, FIRMWARE_UNLOAD); 841347847Shselasky } 842347847Shselasky else 843347847Shselasky return (-ENOENT); 844347847Shselasky 845347847Shselasky return err; 846347847Shselasky} 847347847Shselasky 848331580Shselaskystatic int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 849331580Shselasky{ 850331580Shselasky struct pci_dev *pdev = dev->pdev; 851331580Shselasky int err = 0; 852331580Shselasky 853290650Shselasky pci_set_drvdata(dev->pdev, dev); 854290650Shselasky strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN); 855290650Shselasky priv->name[MLX5_MAX_NAME_LEN - 1] = 0; 856290650Shselasky 857290650Shselasky mutex_init(&priv->pgdir_mutex); 858290650Shselasky INIT_LIST_HEAD(&priv->pgdir_list); 859290650Shselasky spin_lock_init(&priv->mkey_lock); 860290650Shselasky 861290650Shselasky priv->numa_node = NUMA_NO_NODE; 862290650Shselasky 863331580Shselasky err = mlx5_pci_enable_device(dev); 864290650Shselasky if (err) { 865290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""Cannot enable PCI device, aborting\n"); 866290650Shselasky goto err_dbg; 867290650Shselasky } 868290650Shselasky 869290650Shselasky err = request_bar(pdev); 870290650Shselasky if (err) { 871290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""error requesting BARs, aborting\n"); 872290650Shselasky goto err_disable; 873290650Shselasky } 874290650Shselasky 875290650Shselasky pci_set_master(pdev); 876290650Shselasky 877290650Shselasky err = set_dma_caps(pdev); 878290650Shselasky if (err) { 879290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""Failed setting DMA capabilities mask, aborting\n"); 880290650Shselasky goto err_clr_master; 881290650Shselasky } 882290650Shselasky 883329212Shselasky dev->iseg_base = pci_resource_start(dev->pdev, 0); 884329212Shselasky dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 885290650Shselasky if (!dev->iseg) { 886290650Shselasky err = -ENOMEM; 887290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""Failed mapping initialization segment, aborting\n"); 888290650Shselasky goto err_clr_master; 889290650Shselasky } 890331580Shselasky 891337105Shselasky return 0; 892331585Shselasky 893331580Shselaskyerr_clr_master: 894331580Shselasky release_bar(dev->pdev); 895331580Shselaskyerr_disable: 896331580Shselasky mlx5_pci_disable_device(dev); 897331580Shselaskyerr_dbg: 898331580Shselasky return err; 899331580Shselasky} 900331580Shselasky 901331580Shselaskystatic void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 902331580Shselasky{ 903331580Shselasky iounmap(dev->iseg); 904331580Shselasky release_bar(dev->pdev); 905331580Shselasky mlx5_pci_disable_device(dev); 906331580Shselasky} 907331580Shselasky 908331810Shselaskystatic int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 909331580Shselasky{ 910331580Shselasky struct pci_dev *pdev = dev->pdev; 911331580Shselasky int err; 912331580Shselasky 913337103Shselasky err = mlx5_vsc_find_cap(dev); 914337103Shselasky if (err) 915337103Shselasky dev_err(&pdev->dev, "Unable to find vendor specific capabilities\n"); 916331815Shselasky 917331810Shselasky err = mlx5_query_hca_caps(dev); 918331810Shselasky if (err) { 919331810Shselasky dev_err(&pdev->dev, "query hca failed\n"); 920331810Shselasky goto out; 921331810Shselasky } 922331810Shselasky 923331810Shselasky err = mlx5_query_board_id(dev); 924331810Shselasky if (err) { 925331810Shselasky dev_err(&pdev->dev, "query board id failed\n"); 926331810Shselasky goto out; 927331810Shselasky } 928331810Shselasky 929331810Shselasky err = mlx5_eq_init(dev); 930331810Shselasky if (err) { 931331810Shselasky dev_err(&pdev->dev, "failed to initialize eq\n"); 932331810Shselasky goto out; 933331810Shselasky } 934331810Shselasky 935331810Shselasky MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock); 936331810Shselasky 937331810Shselasky err = mlx5_init_cq_table(dev); 938331810Shselasky if (err) { 939331810Shselasky dev_err(&pdev->dev, "failed to initialize cq table\n"); 940331810Shselasky goto err_eq_cleanup; 941331810Shselasky } 942331810Shselasky 943331810Shselasky mlx5_init_qp_table(dev); 944331810Shselasky mlx5_init_srq_table(dev); 945331810Shselasky mlx5_init_mr_table(dev); 946331810Shselasky 947341958Shselasky mlx5_init_reserved_gids(dev); 948341958Shselasky mlx5_fpga_init(dev); 949341958Shselasky 950331810Shselasky return 0; 951331810Shselasky 952331810Shselaskyerr_eq_cleanup: 953331810Shselasky mlx5_eq_cleanup(dev); 954331810Shselasky 955331810Shselaskyout: 956331810Shselasky return err; 957331810Shselasky} 958331810Shselasky 959331810Shselaskystatic void mlx5_cleanup_once(struct mlx5_core_dev *dev) 960331810Shselasky{ 961341958Shselasky mlx5_fpga_cleanup(dev); 962341958Shselasky mlx5_cleanup_reserved_gids(dev); 963331810Shselasky mlx5_cleanup_mr_table(dev); 964331810Shselasky mlx5_cleanup_srq_table(dev); 965331810Shselasky mlx5_cleanup_qp_table(dev); 966331810Shselasky mlx5_cleanup_cq_table(dev); 967331810Shselasky mlx5_eq_cleanup(dev); 968331810Shselasky} 969331810Shselasky 970331810Shselaskystatic int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, 971331810Shselasky bool boot) 972331810Shselasky{ 973331810Shselasky struct pci_dev *pdev = dev->pdev; 974331810Shselasky int err; 975331810Shselasky 976331580Shselasky mutex_lock(&dev->intf_state_mutex); 977331580Shselasky if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 978331580Shselasky dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n", 979331580Shselasky __func__); 980331580Shselasky goto out; 981331580Shselasky } 982331580Shselasky 983290650Shselasky device_printf((&pdev->dev)->bsddev, "INFO: ""firmware version: %d.%d.%d\n", fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev)); 984290650Shselasky 985306233Shselasky /* 986306233Shselasky * On load removing any previous indication of internal error, 987306233Shselasky * device is up 988306233Shselasky */ 989306233Shselasky dev->state = MLX5_DEVICE_STATE_UP; 990306233Shselasky 991290650Shselasky err = mlx5_cmd_init(dev); 992290650Shselasky if (err) { 993290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""Failed initializing command interface, aborting\n"); 994331580Shselasky goto out_err; 995290650Shselasky } 996290650Shselasky 997290650Shselasky err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI); 998290650Shselasky if (err) { 999290650Shselasky device_printf((&dev->pdev->dev)->bsddev, "ERR: ""Firmware over %d MS in initializing state, aborting\n", FW_INIT_TIMEOUT_MILI); 1000290650Shselasky goto err_cmd_cleanup; 1001290650Shselasky } 1002290650Shselasky 1003290650Shselasky err = mlx5_core_enable_hca(dev); 1004290650Shselasky if (err) { 1005290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""enable hca failed\n"); 1006331810Shselasky goto err_cmd_cleanup; 1007290650Shselasky } 1008290650Shselasky 1009290650Shselasky err = mlx5_core_set_issi(dev); 1010290650Shselasky if (err) { 1011290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""failed to set issi\n"); 1012290650Shselasky goto err_disable_hca; 1013290650Shselasky } 1014290650Shselasky 1015290650Shselasky err = mlx5_pagealloc_start(dev); 1016290650Shselasky if (err) { 1017290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_pagealloc_start failed\n"); 1018290650Shselasky goto err_disable_hca; 1019290650Shselasky } 1020290650Shselasky 1021290650Shselasky err = mlx5_satisfy_startup_pages(dev, 1); 1022290650Shselasky if (err) { 1023290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""failed to allocate boot pages\n"); 1024290650Shselasky goto err_pagealloc_stop; 1025290650Shselasky } 1026290650Shselasky 1027329209Shselasky err = set_hca_ctrl(dev); 1028329209Shselasky if (err) { 1029329209Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""set_hca_ctrl failed\n"); 1030329209Shselasky goto reclaim_boot_pages; 1031329209Shselasky } 1032329209Shselasky 1033306233Shselasky err = handle_hca_cap(dev); 1034290650Shselasky if (err) { 1035306233Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""handle_hca_cap failed\n"); 1036290650Shselasky goto reclaim_boot_pages; 1037290650Shselasky } 1038290650Shselasky 1039329209Shselasky err = handle_hca_cap_atomic(dev); 1040290650Shselasky if (err) { 1041329209Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""handle_hca_cap_atomic failed\n"); 1042290650Shselasky goto reclaim_boot_pages; 1043290650Shselasky } 1044290650Shselasky 1045290650Shselasky err = mlx5_satisfy_startup_pages(dev, 0); 1046290650Shselasky if (err) { 1047290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""failed to allocate init pages\n"); 1048290650Shselasky goto reclaim_boot_pages; 1049290650Shselasky } 1050290650Shselasky 1051290650Shselasky err = mlx5_cmd_init_hca(dev); 1052290650Shselasky if (err) { 1053290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""init hca failed\n"); 1054290650Shselasky goto reclaim_boot_pages; 1055290650Shselasky } 1056290650Shselasky 1057290650Shselasky mlx5_start_health_poll(dev); 1058290650Shselasky 1059331810Shselasky if (boot && mlx5_init_once(dev, priv)) { 1060331810Shselasky dev_err(&pdev->dev, "sw objs init failed\n"); 1061290650Shselasky goto err_stop_poll; 1062290650Shselasky } 1063290650Shselasky 1064290650Shselasky err = mlx5_enable_msix(dev); 1065290650Shselasky if (err) { 1066290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""enable msix failed\n"); 1067331810Shselasky goto err_cleanup_once; 1068290650Shselasky } 1069290650Shselasky 1070290650Shselasky err = mlx5_alloc_uuars(dev, &priv->uuari); 1071290650Shselasky if (err) { 1072290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""Failed allocating uar, aborting\n"); 1073331810Shselasky goto err_disable_msix; 1074290650Shselasky } 1075290650Shselasky 1076290650Shselasky err = mlx5_start_eqs(dev); 1077290650Shselasky if (err) { 1078290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to start pages and async EQs\n"); 1079290650Shselasky goto err_free_uar; 1080290650Shselasky } 1081290650Shselasky 1082290650Shselasky err = alloc_comp_eqs(dev); 1083290650Shselasky if (err) { 1084290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to alloc completion EQs\n"); 1085290650Shselasky goto err_stop_eqs; 1086290650Shselasky } 1087290650Shselasky 1088290650Shselasky if (map_bf_area(dev)) 1089290650Shselasky device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to map blue flame area\n"); 1090290650Shselasky 1091329200Shselasky err = mlx5_init_fs(dev); 1092329200Shselasky if (err) { 1093329200Shselasky mlx5_core_err(dev, "flow steering init %d\n", err); 1094331810Shselasky goto err_free_comp_eqs; 1095329200Shselasky } 1096329200Shselasky 1097341958Shselasky err = mlx5_fpga_device_start(dev); 1098341958Shselasky if (err) { 1099341958Shselasky dev_err(&pdev->dev, "fpga device start failed %d\n", err); 1100341958Shselasky goto err_fpga_start; 1101341958Shselasky } 1102341958Shselasky 1103331580Shselasky err = mlx5_register_device(dev); 1104331580Shselasky if (err) { 1105331580Shselasky dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err); 1106331810Shselasky goto err_fs; 1107331580Shselasky } 1108331580Shselasky 1109331580Shselasky set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1110331580Shselasky 1111331580Shselaskyout: 1112331580Shselasky mutex_unlock(&dev->intf_state_mutex); 1113290650Shselasky return 0; 1114290650Shselasky 1115341958Shselaskyerr_fpga_start: 1116331810Shselaskyerr_fs: 1117331580Shselasky mlx5_cleanup_fs(dev); 1118331810Shselasky 1119331810Shselaskyerr_free_comp_eqs: 1120331810Shselasky free_comp_eqs(dev); 1121329200Shselasky unmap_bf_area(dev); 1122329200Shselasky 1123290650Shselaskyerr_stop_eqs: 1124290650Shselasky mlx5_stop_eqs(dev); 1125290650Shselasky 1126290650Shselaskyerr_free_uar: 1127290650Shselasky mlx5_free_uuars(dev, &priv->uuari); 1128290650Shselasky 1129331810Shselaskyerr_disable_msix: 1130290650Shselasky mlx5_disable_msix(dev); 1131290650Shselasky 1132331810Shselaskyerr_cleanup_once: 1133331810Shselasky if (boot) 1134331810Shselasky mlx5_cleanup_once(dev); 1135331810Shselasky 1136290650Shselaskyerr_stop_poll: 1137341934Shselasky mlx5_stop_health_poll(dev, boot); 1138290650Shselasky if (mlx5_cmd_teardown_hca(dev)) { 1139290650Shselasky device_printf((&dev->pdev->dev)->bsddev, "ERR: ""tear_down_hca failed, skip cleanup\n"); 1140331580Shselasky goto out_err; 1141290650Shselasky } 1142290650Shselasky 1143290650Shselaskyreclaim_boot_pages: 1144290650Shselasky mlx5_reclaim_startup_pages(dev); 1145290650Shselasky 1146290650Shselaskyerr_pagealloc_stop: 1147290650Shselasky mlx5_pagealloc_stop(dev); 1148290650Shselasky 1149290650Shselaskyerr_disable_hca: 1150290650Shselasky mlx5_core_disable_hca(dev); 1151290650Shselasky 1152290650Shselaskyerr_cmd_cleanup: 1153290650Shselasky mlx5_cmd_cleanup(dev); 1154290650Shselasky 1155331580Shselaskyout_err: 1156331580Shselasky dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1157331580Shselasky mutex_unlock(&dev->intf_state_mutex); 1158290650Shselasky 1159290650Shselasky return err; 1160290650Shselasky} 1161290650Shselasky 1162331810Shselaskystatic int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, 1163331810Shselasky bool cleanup) 1164290650Shselasky{ 1165331580Shselasky int err = 0; 1166290650Shselasky 1167331811Shselasky if (cleanup) 1168331811Shselasky mlx5_drain_health_recovery(dev); 1169331811Shselasky 1170331580Shselasky mutex_lock(&dev->intf_state_mutex); 1171347799Shselasky if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1172331580Shselasky dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n", __func__); 1173331810Shselasky if (cleanup) 1174331810Shselasky mlx5_cleanup_once(dev); 1175331580Shselasky goto out; 1176331580Shselasky } 1177331580Shselasky 1178331580Shselasky mlx5_unregister_device(dev); 1179331580Shselasky 1180341958Shselasky mlx5_fpga_device_stop(dev); 1181329200Shselasky mlx5_cleanup_fs(dev); 1182290650Shselasky unmap_bf_area(dev); 1183322144Shselasky mlx5_wait_for_reclaim_vfs_pages(dev); 1184290650Shselasky free_comp_eqs(dev); 1185290650Shselasky mlx5_stop_eqs(dev); 1186290650Shselasky mlx5_free_uuars(dev, &priv->uuari); 1187290650Shselasky mlx5_disable_msix(dev); 1188331810Shselasky if (cleanup) 1189331810Shselasky mlx5_cleanup_once(dev); 1190341934Shselasky mlx5_stop_health_poll(dev, cleanup); 1191331580Shselasky err = mlx5_cmd_teardown_hca(dev); 1192331580Shselasky if (err) { 1193290650Shselasky device_printf((&dev->pdev->dev)->bsddev, "ERR: ""tear_down_hca failed, skip cleanup\n"); 1194331580Shselasky goto out; 1195290650Shselasky } 1196290650Shselasky mlx5_pagealloc_stop(dev); 1197290650Shselasky mlx5_reclaim_startup_pages(dev); 1198290650Shselasky mlx5_core_disable_hca(dev); 1199290650Shselasky mlx5_cmd_cleanup(dev); 1200290650Shselasky 1201331580Shselaskyout: 1202331580Shselasky clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1203331580Shselasky mutex_unlock(&dev->intf_state_mutex); 1204331580Shselasky return err; 1205290650Shselasky} 1206290650Shselasky 1207331580Shselaskyvoid mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event, 1208331580Shselasky unsigned long param) 1209290650Shselasky{ 1210290650Shselasky struct mlx5_priv *priv = &dev->priv; 1211290650Shselasky struct mlx5_device_context *dev_ctx; 1212290650Shselasky unsigned long flags; 1213290650Shselasky 1214290650Shselasky spin_lock_irqsave(&priv->ctx_lock, flags); 1215290650Shselasky 1216290650Shselasky list_for_each_entry(dev_ctx, &priv->ctx_list, list) 1217290650Shselasky if (dev_ctx->intf->event) 1218290650Shselasky dev_ctx->intf->event(dev, dev_ctx->context, event, param); 1219290650Shselasky 1220290650Shselasky spin_unlock_irqrestore(&priv->ctx_lock, flags); 1221290650Shselasky} 1222290650Shselasky 1223290650Shselaskystruct mlx5_core_event_handler { 1224290650Shselasky void (*event)(struct mlx5_core_dev *dev, 1225290650Shselasky enum mlx5_dev_event event, 1226290650Shselasky void *data); 1227290650Shselasky}; 1228290650Shselasky 1229290650Shselaskystatic int init_one(struct pci_dev *pdev, 1230290650Shselasky const struct pci_device_id *id) 1231290650Shselasky{ 1232290650Shselasky struct mlx5_core_dev *dev; 1233290650Shselasky struct mlx5_priv *priv; 1234338554Shselasky device_t bsddev = pdev->dev.bsddev; 1235290650Shselasky int err; 1236290650Shselasky 1237290650Shselasky dev = kzalloc(sizeof(*dev), GFP_KERNEL); 1238290650Shselasky priv = &dev->priv; 1239306233Shselasky if (id) 1240306233Shselasky priv->pci_dev_data = id->driver_data; 1241290650Shselasky 1242347835Shselasky if (mlx5_prof_sel < 0 || mlx5_prof_sel >= ARRAY_SIZE(profiles)) { 1243341930Shselasky device_printf(bsddev, "WARN: selected profile out of range, selecting default (%d)\n", MLX5_DEFAULT_PROF); 1244347835Shselasky mlx5_prof_sel = MLX5_DEFAULT_PROF; 1245290650Shselasky } 1246347835Shselasky dev->profile = &profiles[mlx5_prof_sel]; 1247331580Shselasky dev->pdev = pdev; 1248290650Shselasky dev->event = mlx5_core_event; 1249290650Shselasky 1250341948Shselasky /* Set desc */ 1251341948Shselasky device_set_desc(bsddev, mlx5_version); 1252341948Shselasky 1253338554Shselasky sysctl_ctx_init(&dev->sysctl_ctx); 1254338554Shselasky SYSCTL_ADD_INT(&dev->sysctl_ctx, 1255338554Shselasky SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1256338554Shselasky OID_AUTO, "msix_eqvec", CTLFLAG_RDTUN, &dev->msix_eqvec, 0, 1257338554Shselasky "Maximum number of MSIX event queue vectors, if set"); 1258338554Shselasky 1259290650Shselasky INIT_LIST_HEAD(&priv->ctx_list); 1260290650Shselasky spin_lock_init(&priv->ctx_lock); 1261341930Shselasky mutex_init(&dev->pci_status_mutex); 1262341930Shselasky mutex_init(&dev->intf_state_mutex); 1263331580Shselasky err = mlx5_pci_init(dev, priv); 1264290650Shselasky if (err) { 1265341930Shselasky device_printf(bsddev, "ERR: mlx5_pci_init failed %d\n", err); 1266331580Shselasky goto clean_dev; 1267290650Shselasky } 1268290650Shselasky 1269341930Shselasky err = mlx5_health_init(dev); 1270341930Shselasky if (err) { 1271341930Shselasky device_printf(bsddev, "ERR: mlx5_health_init failed %d\n", err); 1272341930Shselasky goto close_pci; 1273341930Shselasky } 1274331580Shselasky 1275331810Shselasky mlx5_pagealloc_init(dev); 1276331810Shselasky 1277331810Shselasky err = mlx5_load_one(dev, priv, true); 1278290650Shselasky if (err) { 1279341930Shselasky device_printf(bsddev, "ERR: mlx5_load_one failed %d\n", err); 1280331580Shselasky goto clean_health; 1281290650Shselasky } 1282290650Shselasky 1283331914Shselasky mlx5_fwdump_prep(dev); 1284331914Shselasky 1285347847Shselasky mlx5_firmware_update(dev); 1286347847Shselasky 1287341930Shselasky pci_save_state(bsddev); 1288290650Shselasky return 0; 1289290650Shselasky 1290331580Shselaskyclean_health: 1291331810Shselasky mlx5_pagealloc_cleanup(dev); 1292341930Shselasky mlx5_health_cleanup(dev); 1293331580Shselaskyclose_pci: 1294341930Shselasky mlx5_pci_close(dev, priv); 1295331580Shselaskyclean_dev: 1296338554Shselasky sysctl_ctx_free(&dev->sysctl_ctx); 1297290650Shselasky kfree(dev); 1298290650Shselasky return err; 1299290650Shselasky} 1300290650Shselasky 1301290650Shselaskystatic void remove_one(struct pci_dev *pdev) 1302290650Shselasky{ 1303290650Shselasky struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1304331580Shselasky struct mlx5_priv *priv = &dev->priv; 1305290650Shselasky 1306331810Shselasky if (mlx5_unload_one(dev, priv, true)) { 1307331580Shselasky dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n"); 1308331580Shselasky mlx5_health_cleanup(dev); 1309331580Shselasky return; 1310331580Shselasky } 1311331580Shselasky 1312331914Shselasky mlx5_fwdump_clean(dev); 1313331810Shselasky mlx5_pagealloc_cleanup(dev); 1314331580Shselasky mlx5_health_cleanup(dev); 1315331580Shselasky mlx5_pci_close(dev, priv); 1316331580Shselasky pci_set_drvdata(pdev, NULL); 1317338554Shselasky sysctl_ctx_free(&dev->sysctl_ctx); 1318290650Shselasky kfree(dev); 1319290650Shselasky} 1320290650Shselasky 1321331580Shselaskystatic pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 1322331580Shselasky pci_channel_state_t state) 1323331580Shselasky{ 1324331580Shselasky struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1325331580Shselasky struct mlx5_priv *priv = &dev->priv; 1326331580Shselasky 1327331580Shselasky dev_info(&pdev->dev, "%s was called\n", __func__); 1328331810Shselasky mlx5_enter_error_state(dev, false); 1329331810Shselasky mlx5_unload_one(dev, priv, false); 1330331914Shselasky 1331331582Shselasky if (state) { 1332331582Shselasky mlx5_drain_health_wq(dev); 1333331582Shselasky mlx5_pci_disable_device(dev); 1334331582Shselasky } 1335331582Shselasky 1336331580Shselasky return state == pci_channel_io_perm_failure ? 1337331580Shselasky PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 1338331580Shselasky} 1339331580Shselasky 1340331580Shselaskystatic pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 1341331580Shselasky{ 1342331580Shselasky struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1343331580Shselasky int err = 0; 1344331580Shselasky 1345331580Shselasky dev_info(&pdev->dev, "%s was called\n", __func__); 1346331580Shselasky 1347331580Shselasky err = mlx5_pci_enable_device(dev); 1348331580Shselasky if (err) { 1349331580Shselasky dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n" 1350331580Shselasky , __func__, err); 1351331580Shselasky return PCI_ERS_RESULT_DISCONNECT; 1352331580Shselasky } 1353331580Shselasky pci_set_master(pdev); 1354331580Shselasky pci_set_powerstate(pdev->dev.bsddev, PCI_POWERSTATE_D0); 1355331580Shselasky pci_restore_state(pdev->dev.bsddev); 1356331816Shselasky pci_save_state(pdev->dev.bsddev); 1357331580Shselasky 1358331580Shselasky return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; 1359331580Shselasky} 1360331580Shselasky 1361331580Shselasky/* wait for the device to show vital signs. For now we check 1362331580Shselasky * that we can read the device ID and that the health buffer 1363331580Shselasky * shows a non zero value which is different than 0xffffffff 1364331580Shselasky */ 1365331580Shselaskystatic void wait_vital(struct pci_dev *pdev) 1366331580Shselasky{ 1367331580Shselasky struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1368331580Shselasky struct mlx5_core_health *health = &dev->priv.health; 1369331580Shselasky const int niter = 100; 1370331580Shselasky u32 count; 1371331580Shselasky u16 did; 1372331580Shselasky int i; 1373331580Shselasky 1374331580Shselasky /* Wait for firmware to be ready after reset */ 1375331580Shselasky msleep(1000); 1376331580Shselasky for (i = 0; i < niter; i++) { 1377331580Shselasky if (pci_read_config_word(pdev, 2, &did)) { 1378331580Shselasky dev_warn(&pdev->dev, "failed reading config word\n"); 1379331580Shselasky break; 1380331580Shselasky } 1381331580Shselasky if (did == pdev->device) { 1382331580Shselasky dev_info(&pdev->dev, "device ID correctly read after %d iterations\n", i); 1383331580Shselasky break; 1384331580Shselasky } 1385331580Shselasky msleep(50); 1386331580Shselasky } 1387331580Shselasky if (i == niter) 1388331580Shselasky dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__); 1389331580Shselasky 1390331580Shselasky for (i = 0; i < niter; i++) { 1391331580Shselasky count = ioread32be(health->health_counter); 1392331580Shselasky if (count && count != 0xffffffff) { 1393331580Shselasky dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i); 1394331580Shselasky break; 1395331580Shselasky } 1396331580Shselasky msleep(50); 1397331580Shselasky } 1398331580Shselasky 1399331580Shselasky if (i == niter) 1400331580Shselasky dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__); 1401331580Shselasky} 1402331580Shselasky 1403331580Shselaskystatic void mlx5_pci_resume(struct pci_dev *pdev) 1404331580Shselasky{ 1405331580Shselasky struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1406331580Shselasky struct mlx5_priv *priv = &dev->priv; 1407331580Shselasky int err; 1408331580Shselasky 1409331580Shselasky dev_info(&pdev->dev, "%s was called\n", __func__); 1410331580Shselasky 1411331580Shselasky wait_vital(pdev); 1412331580Shselasky 1413331810Shselasky err = mlx5_load_one(dev, priv, false); 1414331580Shselasky if (err) 1415331580Shselasky dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n" 1416331580Shselasky , __func__, err); 1417331580Shselasky else 1418331580Shselasky dev_info(&pdev->dev, "%s: device recovered\n", __func__); 1419331580Shselasky} 1420331580Shselasky 1421331580Shselaskystatic const struct pci_error_handlers mlx5_err_handler = { 1422331580Shselasky .error_detected = mlx5_pci_err_detected, 1423331580Shselasky .slot_reset = mlx5_pci_slot_reset, 1424331580Shselasky .resume = mlx5_pci_resume 1425331580Shselasky}; 1426331580Shselasky 1427331810Shselaskystatic int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 1428331810Shselasky{ 1429347818Shselasky bool fast_teardown, force_teardown; 1430331810Shselasky int err; 1431331810Shselasky 1432347819Shselasky if (!mlx5_fast_unload_enabled) { 1433347819Shselasky mlx5_core_dbg(dev, "fast unload is disabled by user\n"); 1434347819Shselasky return -EOPNOTSUPP; 1435347819Shselasky } 1436347819Shselasky 1437347818Shselasky fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1438347818Shselasky force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1439347818Shselasky 1440347818Shselasky mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1441347818Shselasky mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1442347818Shselasky 1443347818Shselasky if (!fast_teardown && !force_teardown) 1444331810Shselasky return -EOPNOTSUPP; 1445331810Shselasky 1446331810Shselasky if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1447331810Shselasky mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 1448331810Shselasky return -EAGAIN; 1449331810Shselasky } 1450331810Shselasky 1451341934Shselasky /* Panic tear down fw command will stop the PCI bus communication 1452341934Shselasky * with the HCA, so the health polll is no longer needed. 1453341934Shselasky */ 1454341934Shselasky mlx5_drain_health_wq(dev); 1455341934Shselasky mlx5_stop_health_poll(dev, false); 1456341934Shselasky 1457347818Shselasky err = mlx5_cmd_fast_teardown_hca(dev); 1458347818Shselasky if (!err) 1459347818Shselasky goto done; 1460347818Shselasky 1461331810Shselasky err = mlx5_cmd_force_teardown_hca(dev); 1462347818Shselasky if (!err) 1463347818Shselasky goto done; 1464331810Shselasky 1465347818Shselasky mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", err); 1466347818Shselasky mlx5_start_health_poll(dev); 1467347818Shselasky return err; 1468347818Shselaskydone: 1469331810Shselasky mlx5_enter_error_state(dev, true); 1470331810Shselasky return 0; 1471331810Shselasky} 1472331810Shselasky 1473347802Shselaskystatic void mlx5_disable_interrupts(struct mlx5_core_dev *mdev) 1474347802Shselasky{ 1475347802Shselasky int nvec = mdev->priv.eq_table.num_comp_vectors + MLX5_EQ_VEC_COMP_BASE; 1476347802Shselasky int x; 1477347802Shselasky 1478347802Shselasky mdev->priv.disable_irqs = 1; 1479347802Shselasky 1480347802Shselasky /* wait for all IRQ handlers to finish processing */ 1481347802Shselasky for (x = 0; x != nvec; x++) 1482347802Shselasky synchronize_irq(mdev->priv.msix_arr[x].vector); 1483347802Shselasky} 1484347802Shselasky 1485329211Shselaskystatic void shutdown_one(struct pci_dev *pdev) 1486329211Shselasky{ 1487331580Shselasky struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1488331580Shselasky struct mlx5_priv *priv = &dev->priv; 1489331810Shselasky int err; 1490331580Shselasky 1491347802Shselasky /* enter polling mode */ 1492347802Shselasky mlx5_cmd_use_polling(dev); 1493347802Shselasky 1494347802Shselasky /* disable all interrupts */ 1495347802Shselasky mlx5_disable_interrupts(dev); 1496347802Shselasky 1497331810Shselasky err = mlx5_try_fast_unload(dev); 1498331810Shselasky if (err) 1499331810Shselasky mlx5_unload_one(dev, priv, false); 1500331580Shselasky mlx5_pci_disable_device(dev); 1501329211Shselasky} 1502329211Shselasky 1503290650Shselaskystatic const struct pci_device_id mlx5_core_pci_table[] = { 1504290650Shselasky { PCI_VDEVICE(MELLANOX, 4113) }, /* Connect-IB */ 1505290650Shselasky { PCI_VDEVICE(MELLANOX, 4114) }, /* Connect-IB VF */ 1506290650Shselasky { PCI_VDEVICE(MELLANOX, 4115) }, /* ConnectX-4 */ 1507290650Shselasky { PCI_VDEVICE(MELLANOX, 4116) }, /* ConnectX-4 VF */ 1508290650Shselasky { PCI_VDEVICE(MELLANOX, 4117) }, /* ConnectX-4LX */ 1509290650Shselasky { PCI_VDEVICE(MELLANOX, 4118) }, /* ConnectX-4LX VF */ 1510306233Shselasky { PCI_VDEVICE(MELLANOX, 4119) }, /* ConnectX-5 */ 1511306233Shselasky { PCI_VDEVICE(MELLANOX, 4120) }, /* ConnectX-5 VF */ 1512290650Shselasky { PCI_VDEVICE(MELLANOX, 4121) }, 1513290650Shselasky { PCI_VDEVICE(MELLANOX, 4122) }, 1514290650Shselasky { PCI_VDEVICE(MELLANOX, 4123) }, 1515290650Shselasky { PCI_VDEVICE(MELLANOX, 4124) }, 1516290650Shselasky { PCI_VDEVICE(MELLANOX, 4125) }, 1517290650Shselasky { PCI_VDEVICE(MELLANOX, 4126) }, 1518290650Shselasky { PCI_VDEVICE(MELLANOX, 4127) }, 1519290650Shselasky { PCI_VDEVICE(MELLANOX, 4128) }, 1520290650Shselasky { PCI_VDEVICE(MELLANOX, 4129) }, 1521290650Shselasky { PCI_VDEVICE(MELLANOX, 4130) }, 1522290650Shselasky { PCI_VDEVICE(MELLANOX, 4131) }, 1523290650Shselasky { PCI_VDEVICE(MELLANOX, 4132) }, 1524290650Shselasky { PCI_VDEVICE(MELLANOX, 4133) }, 1525290650Shselasky { PCI_VDEVICE(MELLANOX, 4134) }, 1526290650Shselasky { PCI_VDEVICE(MELLANOX, 4135) }, 1527290650Shselasky { PCI_VDEVICE(MELLANOX, 4136) }, 1528290650Shselasky { PCI_VDEVICE(MELLANOX, 4137) }, 1529290650Shselasky { PCI_VDEVICE(MELLANOX, 4138) }, 1530290650Shselasky { PCI_VDEVICE(MELLANOX, 4139) }, 1531290650Shselasky { PCI_VDEVICE(MELLANOX, 4140) }, 1532290650Shselasky { PCI_VDEVICE(MELLANOX, 4141) }, 1533290650Shselasky { PCI_VDEVICE(MELLANOX, 4142) }, 1534290650Shselasky { PCI_VDEVICE(MELLANOX, 4143) }, 1535290650Shselasky { PCI_VDEVICE(MELLANOX, 4144) }, 1536290650Shselasky { 0, } 1537290650Shselasky}; 1538290650Shselasky 1539290650ShselaskyMODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 1540290650Shselasky 1541331809Shselaskyvoid mlx5_disable_device(struct mlx5_core_dev *dev) 1542331809Shselasky{ 1543331809Shselasky mlx5_pci_err_detected(dev->pdev, 0); 1544331809Shselasky} 1545331809Shselasky 1546331809Shselaskyvoid mlx5_recover_device(struct mlx5_core_dev *dev) 1547331809Shselasky{ 1548331809Shselasky mlx5_pci_disable_device(dev); 1549331809Shselasky if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) 1550331809Shselasky mlx5_pci_resume(dev->pdev); 1551331809Shselasky} 1552331809Shselasky 1553331586Shselaskystruct pci_driver mlx5_core_driver = { 1554290650Shselasky .name = DRIVER_NAME, 1555290650Shselasky .id_table = mlx5_core_pci_table, 1556329211Shselasky .shutdown = shutdown_one, 1557290650Shselasky .probe = init_one, 1558331580Shselasky .remove = remove_one, 1559331580Shselasky .err_handler = &mlx5_err_handler 1560290650Shselasky}; 1561290650Shselasky 1562290650Shselaskystatic int __init init(void) 1563290650Shselasky{ 1564290650Shselasky int err; 1565290650Shselasky 1566290650Shselasky err = pci_register_driver(&mlx5_core_driver); 1567290650Shselasky if (err) 1568331580Shselasky goto err_debug; 1569290650Shselasky 1570331586Shselasky err = mlx5_fwdump_init(); 1571331586Shselasky if (err) 1572331586Shselasky goto err_fwdump; 1573331586Shselasky 1574331586Shselasky return 0; 1575331586Shselasky 1576331586Shselaskyerr_fwdump: 1577331586Shselasky pci_unregister_driver(&mlx5_core_driver); 1578290650Shselasky 1579290650Shselaskyerr_debug: 1580290650Shselasky return err; 1581290650Shselasky} 1582290650Shselasky 1583290650Shselaskystatic void __exit cleanup(void) 1584290650Shselasky{ 1585331586Shselasky mlx5_fwdump_fini(); 1586290650Shselasky pci_unregister_driver(&mlx5_core_driver); 1587290650Shselasky} 1588290650Shselasky 1589290650Shselaskymodule_init(init); 1590290650Shselaskymodule_exit(cleanup); 1591