mlx5_main.c revision 331580
1/*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_core/mlx5_main.c 331580 2018-03-26 20:33:31Z hselasky $ 26 */ 27 28#define LINUXKPI_PARAM_PREFIX mlx5_ 29 30#include <linux/kmod.h> 31#include <linux/module.h> 32#include <linux/errno.h> 33#include <linux/pci.h> 34#include <linux/dma-mapping.h> 35#include <linux/slab.h> 36#include <linux/io-mapping.h> 37#include <linux/interrupt.h> 38#include <dev/mlx5/driver.h> 39#include <dev/mlx5/cq.h> 40#include <dev/mlx5/qp.h> 41#include <dev/mlx5/srq.h> 42#include <linux/delay.h> 43#include <dev/mlx5/mlx5_ifc.h> 44#include "mlx5_core.h" 45#include "fs_core.h" 46 47MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 48MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver"); 49MODULE_LICENSE("Dual BSD/GPL"); 50#if (__FreeBSD_version >= 1100000) 51MODULE_DEPEND(mlx5, linuxkpi, 1, 1, 1); 52#endif 53MODULE_VERSION(mlx5, 1); 54 55int mlx5_core_debug_mask; 56module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644); 57MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 58 59#define MLX5_DEFAULT_PROF 2 60static int prof_sel = MLX5_DEFAULT_PROF; 61module_param_named(prof_sel, prof_sel, int, 0444); 62MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 63 64#define NUMA_NO_NODE -1 65 66static LIST_HEAD(intf_list); 67static LIST_HEAD(dev_list); 68static DEFINE_MUTEX(intf_mutex); 69 70struct mlx5_device_context { 71 struct list_head list; 72 struct mlx5_interface *intf; 73 void *context; 74}; 75 76enum { 77 MLX5_ATOMIC_REQ_MODE_BE = 0x0, 78 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 79}; 80 81static struct mlx5_profile profiles[] = { 82 [0] = { 83 .mask = 0, 84 }, 85 [1] = { 86 .mask = MLX5_PROF_MASK_QP_SIZE, 87 .log_max_qp = 12, 88 }, 89 [2] = { 90 .mask = MLX5_PROF_MASK_QP_SIZE | 91 MLX5_PROF_MASK_MR_CACHE, 92 .log_max_qp = 17, 93 .mr_cache[0] = { 94 .size = 500, 95 .limit = 250 96 }, 97 .mr_cache[1] = { 98 .size = 500, 99 .limit = 250 100 }, 101 .mr_cache[2] = { 102 .size = 500, 103 .limit = 250 104 }, 105 .mr_cache[3] = { 106 .size = 500, 107 .limit = 250 108 }, 109 .mr_cache[4] = { 110 .size = 500, 111 .limit = 250 112 }, 113 .mr_cache[5] = { 114 .size = 500, 115 .limit = 250 116 }, 117 .mr_cache[6] = { 118 .size = 500, 119 .limit = 250 120 }, 121 .mr_cache[7] = { 122 .size = 500, 123 .limit = 250 124 }, 125 .mr_cache[8] = { 126 .size = 500, 127 .limit = 250 128 }, 129 .mr_cache[9] = { 130 .size = 500, 131 .limit = 250 132 }, 133 .mr_cache[10] = { 134 .size = 500, 135 .limit = 250 136 }, 137 .mr_cache[11] = { 138 .size = 500, 139 .limit = 250 140 }, 141 .mr_cache[12] = { 142 .size = 64, 143 .limit = 32 144 }, 145 .mr_cache[13] = { 146 .size = 32, 147 .limit = 16 148 }, 149 .mr_cache[14] = { 150 .size = 16, 151 .limit = 8 152 }, 153 }, 154 [3] = { 155 .mask = MLX5_PROF_MASK_QP_SIZE, 156 .log_max_qp = 17, 157 }, 158}; 159 160static int set_dma_caps(struct pci_dev *pdev) 161{ 162 int err; 163 164 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 165 if (err) { 166 device_printf((&pdev->dev)->bsddev, "WARN: ""Warning: couldn't set 64-bit PCI DMA mask\n"); 167 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 168 if (err) { 169 device_printf((&pdev->dev)->bsddev, "ERR: ""Can't set PCI DMA mask, aborting\n"); 170 return err; 171 } 172 } 173 174 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 175 if (err) { 176 device_printf((&pdev->dev)->bsddev, "WARN: ""Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 177 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 178 if (err) { 179 device_printf((&pdev->dev)->bsddev, "ERR: ""Can't set consistent PCI DMA mask, aborting\n"); 180 return err; 181 } 182 } 183 184 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 185 return err; 186} 187 188static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 189{ 190 struct pci_dev *pdev = dev->pdev; 191 int err = 0; 192 193 mutex_lock(&dev->pci_status_mutex); 194 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 195 err = pci_enable_device(pdev); 196 if (!err) 197 dev->pci_status = MLX5_PCI_STATUS_ENABLED; 198 } 199 mutex_unlock(&dev->pci_status_mutex); 200 201 return err; 202} 203 204static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 205{ 206 struct pci_dev *pdev = dev->pdev; 207 208 mutex_lock(&dev->pci_status_mutex); 209 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 210 pci_disable_device(pdev); 211 dev->pci_status = MLX5_PCI_STATUS_DISABLED; 212 } 213 mutex_unlock(&dev->pci_status_mutex); 214} 215 216static int request_bar(struct pci_dev *pdev) 217{ 218 int err = 0; 219 220 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 221 device_printf((&pdev->dev)->bsddev, "ERR: ""Missing registers BAR, aborting\n"); 222 return -ENODEV; 223 } 224 225 err = pci_request_regions(pdev, DRIVER_NAME); 226 if (err) 227 device_printf((&pdev->dev)->bsddev, "ERR: ""Couldn't get PCI resources, aborting\n"); 228 229 return err; 230} 231 232static void release_bar(struct pci_dev *pdev) 233{ 234 pci_release_regions(pdev); 235} 236 237static int mlx5_enable_msix(struct mlx5_core_dev *dev) 238{ 239 struct mlx5_priv *priv = &dev->priv; 240 struct mlx5_eq_table *table = &priv->eq_table; 241 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq); 242 int nvec; 243 int i; 244 245 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() + 246 MLX5_EQ_VEC_COMP_BASE; 247 nvec = min_t(int, nvec, num_eqs); 248 if (nvec <= MLX5_EQ_VEC_COMP_BASE) 249 return -ENOMEM; 250 251 priv->msix_arr = kzalloc(nvec * sizeof(*priv->msix_arr), GFP_KERNEL); 252 253 priv->irq_info = kzalloc(nvec * sizeof(*priv->irq_info), GFP_KERNEL); 254 255 for (i = 0; i < nvec; i++) 256 priv->msix_arr[i].entry = i; 257 258 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr, 259 MLX5_EQ_VEC_COMP_BASE + 1, nvec); 260 if (nvec < 0) 261 return nvec; 262 263 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE; 264 265 return 0; 266 267} 268 269static void mlx5_disable_msix(struct mlx5_core_dev *dev) 270{ 271 struct mlx5_priv *priv = &dev->priv; 272 273 pci_disable_msix(dev->pdev); 274 kfree(priv->irq_info); 275 kfree(priv->msix_arr); 276} 277 278struct mlx5_reg_host_endianess { 279 u8 he; 280 u8 rsvd[15]; 281}; 282 283 284#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 285 286enum { 287 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 288 MLX5_DEV_CAP_FLAG_DCT | 289 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR, 290}; 291 292static u16 to_fw_pkey_sz(u32 size) 293{ 294 switch (size) { 295 case 128: 296 return 0; 297 case 256: 298 return 1; 299 case 512: 300 return 2; 301 case 1024: 302 return 3; 303 case 2048: 304 return 4; 305 case 4096: 306 return 5; 307 default: 308 printf("mlx5_core: WARN: ""invalid pkey table size %d\n", size); 309 return 0; 310 } 311} 312 313int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type, 314 enum mlx5_cap_mode cap_mode) 315{ 316 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 317 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 318 void *out, *hca_caps; 319 u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 320 int err; 321 322 memset(in, 0, sizeof(in)); 323 out = kzalloc(out_sz, GFP_KERNEL); 324 325 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 326 MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 327 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz); 328 if (err) 329 goto query_ex; 330 331 err = mlx5_cmd_status_to_err_v2(out); 332 if (err) { 333 mlx5_core_warn(dev, 334 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 335 cap_type, cap_mode, err); 336 goto query_ex; 337 } 338 339 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 340 341 switch (cap_mode) { 342 case HCA_CAP_OPMOD_GET_MAX: 343 memcpy(dev->hca_caps_max[cap_type], hca_caps, 344 MLX5_UN_SZ_BYTES(hca_cap_union)); 345 break; 346 case HCA_CAP_OPMOD_GET_CUR: 347 memcpy(dev->hca_caps_cur[cap_type], hca_caps, 348 MLX5_UN_SZ_BYTES(hca_cap_union)); 349 break; 350 default: 351 mlx5_core_warn(dev, 352 "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 353 cap_type, cap_mode); 354 err = -EINVAL; 355 break; 356 } 357query_ex: 358 kfree(out); 359 return err; 360} 361 362static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz) 363{ 364 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)]; 365 int err; 366 367 memset(out, 0, sizeof(out)); 368 369 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 370 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out)); 371 if (err) 372 return err; 373 374 err = mlx5_cmd_status_to_err_v2(out); 375 376 return err; 377} 378 379static int handle_hca_cap(struct mlx5_core_dev *dev) 380{ 381 void *set_ctx = NULL; 382 struct mlx5_profile *prof = dev->profile; 383 int err = -ENOMEM; 384 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 385 void *set_hca_cap; 386 387 set_ctx = kzalloc(set_sz, GFP_KERNEL); 388 389 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_MAX); 390 if (err) 391 goto query_ex; 392 393 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR); 394 if (err) 395 goto query_ex; 396 397 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 398 capability); 399 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL], 400 MLX5_ST_SZ_BYTES(cmd_hca_cap)); 401 402 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 403 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 404 128); 405 /* we limit the size of the pkey table to 128 entries for now */ 406 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 407 to_fw_pkey_sz(128)); 408 409 if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 410 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 411 prof->log_max_qp); 412 413 /* disable cmdif checksum */ 414 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 415 416 /* enable drain sigerr */ 417 MLX5_SET(cmd_hca_cap, set_hca_cap, drain_sigerr, 1); 418 419 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 420 421 err = set_caps(dev, set_ctx, set_sz); 422 423query_ex: 424 kfree(set_ctx); 425 return err; 426} 427 428static int handle_hca_cap_atomic(struct mlx5_core_dev *dev) 429{ 430 void *set_ctx; 431 void *set_hca_cap; 432 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 433 int req_endianness; 434 int err; 435 436 if (MLX5_CAP_GEN(dev, atomic)) { 437 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC, 438 HCA_CAP_OPMOD_GET_MAX); 439 if (err) 440 return err; 441 442 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC, 443 HCA_CAP_OPMOD_GET_CUR); 444 if (err) 445 return err; 446 } else { 447 return 0; 448 } 449 450 req_endianness = 451 MLX5_CAP_ATOMIC(dev, 452 supported_atomic_req_8B_endianess_mode_1); 453 454 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 455 return 0; 456 457 set_ctx = kzalloc(set_sz, GFP_KERNEL); 458 if (!set_ctx) 459 return -ENOMEM; 460 461 MLX5_SET(set_hca_cap_in, set_ctx, op_mod, 462 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC << 1); 463 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 464 465 /* Set requestor to host endianness */ 466 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode, 467 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 468 469 err = set_caps(dev, set_ctx, set_sz); 470 471 kfree(set_ctx); 472 return err; 473} 474 475static int set_hca_ctrl(struct mlx5_core_dev *dev) 476{ 477 struct mlx5_reg_host_endianess he_in; 478 struct mlx5_reg_host_endianess he_out; 479 int err; 480 481 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH && 482 !MLX5_CAP_GEN(dev, roce)) 483 return 0; 484 485 memset(&he_in, 0, sizeof(he_in)); 486 he_in.he = MLX5_SET_HOST_ENDIANNESS; 487 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 488 &he_out, sizeof(he_out), 489 MLX5_REG_HOST_ENDIANNESS, 0, 1); 490 return err; 491} 492 493static int mlx5_core_enable_hca(struct mlx5_core_dev *dev) 494{ 495 u32 in[MLX5_ST_SZ_DW(enable_hca_in)]; 496 u32 out[MLX5_ST_SZ_DW(enable_hca_out)]; 497 498 memset(in, 0, sizeof(in)); 499 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 500 memset(out, 0, sizeof(out)); 501 return mlx5_cmd_exec_check_status(dev, in, sizeof(in), 502 out, sizeof(out)); 503} 504 505static int mlx5_core_disable_hca(struct mlx5_core_dev *dev) 506{ 507 u32 in[MLX5_ST_SZ_DW(disable_hca_in)]; 508 u32 out[MLX5_ST_SZ_DW(disable_hca_out)]; 509 510 memset(in, 0, sizeof(in)); 511 512 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 513 memset(out, 0, sizeof(out)); 514 return mlx5_cmd_exec_check_status(dev, in, sizeof(in), 515 out, sizeof(out)); 516} 517 518static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 519{ 520 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)]; 521 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)]; 522 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)]; 523 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)]; 524 int err; 525 u32 sup_issi; 526 527 memset(query_in, 0, sizeof(query_in)); 528 memset(query_out, 0, sizeof(query_out)); 529 530 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 531 532 err = mlx5_cmd_exec_check_status(dev, query_in, sizeof(query_in), 533 query_out, sizeof(query_out)); 534 if (err) { 535 if (((struct mlx5_outbox_hdr *)query_out)->status == 536 MLX5_CMD_STAT_BAD_OP_ERR) { 537 pr_debug("Only ISSI 0 is supported\n"); 538 return 0; 539 } 540 541 printf("mlx5_core: ERR: ""failed to query ISSI\n"); 542 return err; 543 } 544 545 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 546 547 if (sup_issi & (1 << 1)) { 548 memset(set_in, 0, sizeof(set_in)); 549 memset(set_out, 0, sizeof(set_out)); 550 551 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 552 MLX5_SET(set_issi_in, set_in, current_issi, 1); 553 554 err = mlx5_cmd_exec_check_status(dev, set_in, sizeof(set_in), 555 set_out, sizeof(set_out)); 556 if (err) { 557 printf("mlx5_core: ERR: ""failed to set ISSI=1\n"); 558 return err; 559 } 560 561 dev->issi = 1; 562 563 return 0; 564 } else if (sup_issi & (1 << 0)) { 565 return 0; 566 } 567 568 return -ENOTSUPP; 569} 570 571 572int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn) 573{ 574 struct mlx5_eq_table *table = &dev->priv.eq_table; 575 struct mlx5_eq *eq; 576 int err = -ENOENT; 577 578 spin_lock(&table->lock); 579 list_for_each_entry(eq, &table->comp_eqs_list, list) { 580 if (eq->index == vector) { 581 *eqn = eq->eqn; 582 *irqn = eq->irqn; 583 err = 0; 584 break; 585 } 586 } 587 spin_unlock(&table->lock); 588 589 return err; 590} 591EXPORT_SYMBOL(mlx5_vector2eqn); 592 593int mlx5_rename_eq(struct mlx5_core_dev *dev, int eq_ix, char *name) 594{ 595 struct mlx5_priv *priv = &dev->priv; 596 struct mlx5_eq_table *table = &priv->eq_table; 597 struct mlx5_eq *eq; 598 int err = -ENOENT; 599 600 spin_lock(&table->lock); 601 list_for_each_entry(eq, &table->comp_eqs_list, list) { 602 if (eq->index == eq_ix) { 603 int irq_ix = eq_ix + MLX5_EQ_VEC_COMP_BASE; 604 605 snprintf(priv->irq_info[irq_ix].name, MLX5_MAX_IRQ_NAME, 606 "%s-%d", name, eq_ix); 607 608 err = 0; 609 break; 610 } 611 } 612 spin_unlock(&table->lock); 613 614 return err; 615} 616 617static void free_comp_eqs(struct mlx5_core_dev *dev) 618{ 619 struct mlx5_eq_table *table = &dev->priv.eq_table; 620 struct mlx5_eq *eq, *n; 621 622 spin_lock(&table->lock); 623 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { 624 list_del(&eq->list); 625 spin_unlock(&table->lock); 626 if (mlx5_destroy_unmap_eq(dev, eq)) 627 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n", 628 eq->eqn); 629 kfree(eq); 630 spin_lock(&table->lock); 631 } 632 spin_unlock(&table->lock); 633} 634 635static int alloc_comp_eqs(struct mlx5_core_dev *dev) 636{ 637 struct mlx5_eq_table *table = &dev->priv.eq_table; 638 char name[MLX5_MAX_IRQ_NAME]; 639 struct mlx5_eq *eq; 640 int ncomp_vec; 641 int nent; 642 int err; 643 int i; 644 645 INIT_LIST_HEAD(&table->comp_eqs_list); 646 ncomp_vec = table->num_comp_vectors; 647 nent = MLX5_COMP_EQ_SIZE; 648 for (i = 0; i < ncomp_vec; i++) { 649 eq = kzalloc(sizeof(*eq), GFP_KERNEL); 650 651 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i); 652 err = mlx5_create_map_eq(dev, eq, 653 i + MLX5_EQ_VEC_COMP_BASE, nent, 0, 654 name, &dev->priv.uuari.uars[0]); 655 if (err) { 656 kfree(eq); 657 goto clean; 658 } 659 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn); 660 eq->index = i; 661 spin_lock(&table->lock); 662 list_add_tail(&eq->list, &table->comp_eqs_list); 663 spin_unlock(&table->lock); 664 } 665 666 return 0; 667 668clean: 669 free_comp_eqs(dev); 670 return err; 671} 672 673static int map_bf_area(struct mlx5_core_dev *dev) 674{ 675 resource_size_t bf_start = pci_resource_start(dev->pdev, 0); 676 resource_size_t bf_len = pci_resource_len(dev->pdev, 0); 677 678 dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len); 679 680 return dev->priv.bf_mapping ? 0 : -ENOMEM; 681} 682 683static void unmap_bf_area(struct mlx5_core_dev *dev) 684{ 685 if (dev->priv.bf_mapping) 686 io_mapping_free(dev->priv.bf_mapping); 687} 688 689static inline int fw_initializing(struct mlx5_core_dev *dev) 690{ 691 return ioread32be(&dev->iseg->initializing) >> 31; 692} 693 694static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili) 695{ 696 u64 end = jiffies + msecs_to_jiffies(max_wait_mili); 697 int err = 0; 698 699 while (fw_initializing(dev)) { 700 if (time_after(jiffies, end)) { 701 err = -EBUSY; 702 break; 703 } 704 msleep(FW_INIT_WAIT_MS); 705 } 706 707 return err; 708} 709 710static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv) 711{ 712 struct mlx5_device_context *dev_ctx; 713 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv); 714 715 dev_ctx = kzalloc(sizeof(*dev_ctx), GFP_KERNEL); 716 if (!dev_ctx) 717 return; 718 719 dev_ctx->intf = intf; 720 CURVNET_SET_QUIET(vnet0); 721 dev_ctx->context = intf->add(dev); 722 CURVNET_RESTORE(); 723 724 if (dev_ctx->context) { 725 spin_lock_irq(&priv->ctx_lock); 726 list_add_tail(&dev_ctx->list, &priv->ctx_list); 727 spin_unlock_irq(&priv->ctx_lock); 728 } else { 729 kfree(dev_ctx); 730 } 731} 732 733static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv) 734{ 735 struct mlx5_device_context *dev_ctx; 736 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv); 737 738 list_for_each_entry(dev_ctx, &priv->ctx_list, list) 739 if (dev_ctx->intf == intf) { 740 spin_lock_irq(&priv->ctx_lock); 741 list_del(&dev_ctx->list); 742 spin_unlock_irq(&priv->ctx_lock); 743 744 intf->remove(dev, dev_ctx->context); 745 kfree(dev_ctx); 746 return; 747 } 748} 749 750static int mlx5_register_device(struct mlx5_core_dev *dev) 751{ 752 struct mlx5_priv *priv = &dev->priv; 753 struct mlx5_interface *intf; 754 755 mutex_lock(&intf_mutex); 756 list_add_tail(&priv->dev_list, &dev_list); 757 list_for_each_entry(intf, &intf_list, list) 758 mlx5_add_device(intf, priv); 759 mutex_unlock(&intf_mutex); 760 761 return 0; 762} 763 764static void mlx5_unregister_device(struct mlx5_core_dev *dev) 765{ 766 struct mlx5_priv *priv = &dev->priv; 767 struct mlx5_interface *intf; 768 769 mutex_lock(&intf_mutex); 770 list_for_each_entry(intf, &intf_list, list) 771 mlx5_remove_device(intf, priv); 772 list_del(&priv->dev_list); 773 mutex_unlock(&intf_mutex); 774} 775 776int mlx5_register_interface(struct mlx5_interface *intf) 777{ 778 struct mlx5_priv *priv; 779 780 if (!intf->add || !intf->remove) 781 return -EINVAL; 782 783 mutex_lock(&intf_mutex); 784 list_add_tail(&intf->list, &intf_list); 785 list_for_each_entry(priv, &dev_list, dev_list) 786 mlx5_add_device(intf, priv); 787 mutex_unlock(&intf_mutex); 788 789 return 0; 790} 791EXPORT_SYMBOL(mlx5_register_interface); 792 793void mlx5_unregister_interface(struct mlx5_interface *intf) 794{ 795 struct mlx5_priv *priv; 796 797 mutex_lock(&intf_mutex); 798 list_for_each_entry(priv, &dev_list, dev_list) 799 mlx5_remove_device(intf, priv); 800 list_del(&intf->list); 801 mutex_unlock(&intf_mutex); 802} 803EXPORT_SYMBOL(mlx5_unregister_interface); 804 805void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol) 806{ 807 struct mlx5_priv *priv = &mdev->priv; 808 struct mlx5_device_context *dev_ctx; 809 unsigned long flags; 810 void *result = NULL; 811 812 spin_lock_irqsave(&priv->ctx_lock, flags); 813 814 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list) 815 if ((dev_ctx->intf->protocol == protocol) && 816 dev_ctx->intf->get_dev) { 817 result = dev_ctx->intf->get_dev(dev_ctx->context); 818 break; 819 } 820 821 spin_unlock_irqrestore(&priv->ctx_lock, flags); 822 823 return result; 824} 825EXPORT_SYMBOL(mlx5_get_protocol_dev); 826 827static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 828{ 829 struct pci_dev *pdev = dev->pdev; 830 int err = 0; 831 832 pci_set_drvdata(dev->pdev, dev); 833 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN); 834 priv->name[MLX5_MAX_NAME_LEN - 1] = 0; 835 836 mutex_init(&priv->pgdir_mutex); 837 INIT_LIST_HEAD(&priv->pgdir_list); 838 spin_lock_init(&priv->mkey_lock); 839 840 priv->numa_node = NUMA_NO_NODE; 841 842 err = mlx5_pci_enable_device(dev); 843 if (err) { 844 device_printf((&pdev->dev)->bsddev, "ERR: ""Cannot enable PCI device, aborting\n"); 845 goto err_dbg; 846 } 847 848 err = request_bar(pdev); 849 if (err) { 850 device_printf((&pdev->dev)->bsddev, "ERR: ""error requesting BARs, aborting\n"); 851 goto err_disable; 852 } 853 854 pci_set_master(pdev); 855 856 err = set_dma_caps(pdev); 857 if (err) { 858 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed setting DMA capabilities mask, aborting\n"); 859 goto err_clr_master; 860 } 861 862 dev->iseg_base = pci_resource_start(dev->pdev, 0); 863 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 864 if (!dev->iseg) { 865 err = -ENOMEM; 866 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed mapping initialization segment, aborting\n"); 867 goto err_clr_master; 868 } 869 870 return 0; 871 872err_clr_master: 873 pci_clear_master(dev->pdev); 874 release_bar(dev->pdev); 875err_disable: 876 mlx5_pci_disable_device(dev); 877err_dbg: 878 return err; 879} 880 881static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 882{ 883 iounmap(dev->iseg); 884 pci_clear_master(dev->pdev); 885 release_bar(dev->pdev); 886 mlx5_pci_disable_device(dev); 887} 888 889static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 890{ 891 struct pci_dev *pdev = dev->pdev; 892 int err; 893 894 mutex_lock(&dev->intf_state_mutex); 895 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 896 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n", 897 __func__); 898 goto out; 899 } 900 901 device_printf((&pdev->dev)->bsddev, "INFO: ""firmware version: %d.%d.%d\n", fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev)); 902 903 /* 904 * On load removing any previous indication of internal error, 905 * device is up 906 */ 907 dev->state = MLX5_DEVICE_STATE_UP; 908 909 err = mlx5_cmd_init(dev); 910 if (err) { 911 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed initializing command interface, aborting\n"); 912 goto out_err; 913 } 914 915 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI); 916 if (err) { 917 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""Firmware over %d MS in initializing state, aborting\n", FW_INIT_TIMEOUT_MILI); 918 goto err_cmd_cleanup; 919 } 920 921 mlx5_pagealloc_init(dev); 922 923 err = mlx5_core_enable_hca(dev); 924 if (err) { 925 device_printf((&pdev->dev)->bsddev, "ERR: ""enable hca failed\n"); 926 goto err_pagealloc_cleanup; 927 } 928 929 err = mlx5_core_set_issi(dev); 930 if (err) { 931 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to set issi\n"); 932 goto err_disable_hca; 933 } 934 935 err = mlx5_pagealloc_start(dev); 936 if (err) { 937 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_pagealloc_start failed\n"); 938 goto err_disable_hca; 939 } 940 941 err = mlx5_satisfy_startup_pages(dev, 1); 942 if (err) { 943 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to allocate boot pages\n"); 944 goto err_pagealloc_stop; 945 } 946 947 err = set_hca_ctrl(dev); 948 if (err) { 949 device_printf((&pdev->dev)->bsddev, "ERR: ""set_hca_ctrl failed\n"); 950 goto reclaim_boot_pages; 951 } 952 953 err = handle_hca_cap(dev); 954 if (err) { 955 device_printf((&pdev->dev)->bsddev, "ERR: ""handle_hca_cap failed\n"); 956 goto reclaim_boot_pages; 957 } 958 959 err = handle_hca_cap_atomic(dev); 960 if (err) { 961 device_printf((&pdev->dev)->bsddev, "ERR: ""handle_hca_cap_atomic failed\n"); 962 goto reclaim_boot_pages; 963 } 964 965 err = mlx5_satisfy_startup_pages(dev, 0); 966 if (err) { 967 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to allocate init pages\n"); 968 goto reclaim_boot_pages; 969 } 970 971 err = mlx5_cmd_init_hca(dev); 972 if (err) { 973 device_printf((&pdev->dev)->bsddev, "ERR: ""init hca failed\n"); 974 goto reclaim_boot_pages; 975 } 976 977 mlx5_start_health_poll(dev); 978 979 err = mlx5_query_hca_caps(dev); 980 if (err) { 981 device_printf((&pdev->dev)->bsddev, "ERR: ""query hca failed\n"); 982 goto err_stop_poll; 983 } 984 985 err = mlx5_query_board_id(dev); 986 if (err) { 987 device_printf((&pdev->dev)->bsddev, "ERR: ""query board id failed\n"); 988 goto err_stop_poll; 989 } 990 991 err = mlx5_enable_msix(dev); 992 if (err) { 993 device_printf((&pdev->dev)->bsddev, "ERR: ""enable msix failed\n"); 994 goto err_stop_poll; 995 } 996 997 err = mlx5_eq_init(dev); 998 if (err) { 999 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to initialize eq\n"); 1000 goto disable_msix; 1001 } 1002 1003 err = mlx5_alloc_uuars(dev, &priv->uuari); 1004 if (err) { 1005 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed allocating uar, aborting\n"); 1006 goto err_eq_cleanup; 1007 } 1008 1009 err = mlx5_start_eqs(dev); 1010 if (err) { 1011 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to start pages and async EQs\n"); 1012 goto err_free_uar; 1013 } 1014 1015 err = alloc_comp_eqs(dev); 1016 if (err) { 1017 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to alloc completion EQs\n"); 1018 goto err_stop_eqs; 1019 } 1020 1021 if (map_bf_area(dev)) 1022 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to map blue flame area\n"); 1023 1024 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock); 1025 1026 mlx5_init_cq_table(dev); 1027 mlx5_init_qp_table(dev); 1028 mlx5_init_srq_table(dev); 1029 mlx5_init_mr_table(dev); 1030 1031 err = mlx5_init_fs(dev); 1032 if (err) { 1033 mlx5_core_err(dev, "flow steering init %d\n", err); 1034 goto err_init_tables; 1035 } 1036 1037 err = mlx5_register_device(dev); 1038 if (err) { 1039 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err); 1040 goto err_reg_dev; 1041 } 1042 1043 clear_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state); 1044 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1045 1046out: 1047 mutex_unlock(&dev->intf_state_mutex); 1048 return 0; 1049 1050err_reg_dev: 1051 mlx5_cleanup_fs(dev); 1052err_init_tables: 1053 mlx5_cleanup_mr_table(dev); 1054 mlx5_cleanup_srq_table(dev); 1055 mlx5_cleanup_qp_table(dev); 1056 mlx5_cleanup_cq_table(dev); 1057 unmap_bf_area(dev); 1058 1059err_stop_eqs: 1060 mlx5_stop_eqs(dev); 1061 1062err_free_uar: 1063 mlx5_free_uuars(dev, &priv->uuari); 1064 1065err_eq_cleanup: 1066 mlx5_eq_cleanup(dev); 1067 1068disable_msix: 1069 mlx5_disable_msix(dev); 1070 1071err_stop_poll: 1072 mlx5_stop_health_poll(dev); 1073 if (mlx5_cmd_teardown_hca(dev)) { 1074 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""tear_down_hca failed, skip cleanup\n"); 1075 goto out_err; 1076 } 1077 1078reclaim_boot_pages: 1079 mlx5_reclaim_startup_pages(dev); 1080 1081err_pagealloc_stop: 1082 mlx5_pagealloc_stop(dev); 1083 1084err_disable_hca: 1085 mlx5_core_disable_hca(dev); 1086 1087err_pagealloc_cleanup: 1088 mlx5_pagealloc_cleanup(dev); 1089 1090err_cmd_cleanup: 1091 mlx5_cmd_cleanup(dev); 1092 1093out_err: 1094 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1095 mutex_unlock(&dev->intf_state_mutex); 1096 1097 return err; 1098} 1099 1100static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 1101{ 1102 int err = 0; 1103 1104 mutex_lock(&dev->intf_state_mutex); 1105 if (test_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state)) { 1106 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n", __func__); 1107 goto out; 1108 } 1109 1110 mlx5_unregister_device(dev); 1111 1112 mlx5_cleanup_fs(dev); 1113 mlx5_cleanup_mr_table(dev); 1114 mlx5_cleanup_srq_table(dev); 1115 mlx5_cleanup_qp_table(dev); 1116 mlx5_cleanup_cq_table(dev); 1117 unmap_bf_area(dev); 1118 mlx5_wait_for_reclaim_vfs_pages(dev); 1119 free_comp_eqs(dev); 1120 mlx5_stop_eqs(dev); 1121 mlx5_free_uuars(dev, &priv->uuari); 1122 mlx5_eq_cleanup(dev); 1123 mlx5_disable_msix(dev); 1124 mlx5_stop_health_poll(dev); 1125 err = mlx5_cmd_teardown_hca(dev); 1126 if (err) { 1127 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""tear_down_hca failed, skip cleanup\n"); 1128 goto out; 1129 } 1130 mlx5_pagealloc_stop(dev); 1131 mlx5_reclaim_startup_pages(dev); 1132 mlx5_core_disable_hca(dev); 1133 mlx5_pagealloc_cleanup(dev); 1134 mlx5_cmd_cleanup(dev); 1135 1136out: 1137 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1138 set_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state); 1139 mutex_unlock(&dev->intf_state_mutex); 1140 return err; 1141} 1142 1143void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event, 1144 unsigned long param) 1145{ 1146 struct mlx5_priv *priv = &dev->priv; 1147 struct mlx5_device_context *dev_ctx; 1148 unsigned long flags; 1149 1150 spin_lock_irqsave(&priv->ctx_lock, flags); 1151 1152 list_for_each_entry(dev_ctx, &priv->ctx_list, list) 1153 if (dev_ctx->intf->event) 1154 dev_ctx->intf->event(dev, dev_ctx->context, event, param); 1155 1156 spin_unlock_irqrestore(&priv->ctx_lock, flags); 1157} 1158 1159struct mlx5_core_event_handler { 1160 void (*event)(struct mlx5_core_dev *dev, 1161 enum mlx5_dev_event event, 1162 void *data); 1163}; 1164 1165 1166static int init_one(struct pci_dev *pdev, 1167 const struct pci_device_id *id) 1168{ 1169 struct mlx5_core_dev *dev; 1170 struct mlx5_priv *priv; 1171 int err; 1172 1173 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 1174 priv = &dev->priv; 1175 if (id) 1176 priv->pci_dev_data = id->driver_data; 1177 1178 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profiles)) { 1179 printf("mlx5_core: WARN: ""selected profile out of range, selecting default (%d)\n", MLX5_DEFAULT_PROF); 1180 prof_sel = MLX5_DEFAULT_PROF; 1181 } 1182 dev->profile = &profiles[prof_sel]; 1183 dev->pdev = pdev; 1184 dev->event = mlx5_core_event; 1185 1186 INIT_LIST_HEAD(&priv->ctx_list); 1187 spin_lock_init(&priv->ctx_lock); 1188 mutex_init(&dev->pci_status_mutex); 1189 mutex_init(&dev->intf_state_mutex); 1190 err = mlx5_pci_init(dev, priv); 1191 if (err) { 1192 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_pci_init failed %d\n", err); 1193 goto clean_dev; 1194 } 1195 1196 err = mlx5_health_init(dev); 1197 if (err) { 1198 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_health_init failed %d\n", err); 1199 goto close_pci; 1200 } 1201 1202 err = mlx5_load_one(dev, priv); 1203 if (err) { 1204 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_register_device failed %d\n", err); 1205 goto clean_health; 1206 } 1207 1208 1209 return 0; 1210 1211clean_health: 1212 mlx5_health_cleanup(dev); 1213close_pci: 1214 mlx5_pci_close(dev, priv); 1215clean_dev: 1216 kfree(dev); 1217 return err; 1218} 1219 1220static void remove_one(struct pci_dev *pdev) 1221{ 1222 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1223 struct mlx5_priv *priv = &dev->priv; 1224 1225 if (mlx5_unload_one(dev, priv)) { 1226 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n"); 1227 mlx5_health_cleanup(dev); 1228 return; 1229 } 1230 1231 mlx5_health_cleanup(dev); 1232 mlx5_pci_close(dev, priv); 1233 pci_set_drvdata(pdev, NULL); 1234 kfree(dev); 1235} 1236 1237static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 1238 pci_channel_state_t state) 1239{ 1240 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1241 struct mlx5_priv *priv = &dev->priv; 1242 1243 dev_info(&pdev->dev, "%s was called\n", __func__); 1244 mlx5_enter_error_state(dev); 1245 mlx5_unload_one(dev, priv); 1246 mlx5_pci_disable_device(dev); 1247 return state == pci_channel_io_perm_failure ? 1248 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 1249} 1250 1251static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 1252{ 1253 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1254 int err = 0; 1255 1256 dev_info(&pdev->dev, "%s was called\n", __func__); 1257 1258 err = mlx5_pci_enable_device(dev); 1259 if (err) { 1260 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n" 1261 , __func__, err); 1262 return PCI_ERS_RESULT_DISCONNECT; 1263 } 1264 pci_set_master(pdev); 1265 pci_set_powerstate(pdev->dev.bsddev, PCI_POWERSTATE_D0); 1266 pci_restore_state(pdev->dev.bsddev); 1267 1268 return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; 1269} 1270 1271void mlx5_disable_device(struct mlx5_core_dev *dev) 1272{ 1273 mlx5_pci_err_detected(dev->pdev, 0); 1274} 1275 1276/* wait for the device to show vital signs. For now we check 1277 * that we can read the device ID and that the health buffer 1278 * shows a non zero value which is different than 0xffffffff 1279 */ 1280static void wait_vital(struct pci_dev *pdev) 1281{ 1282 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1283 struct mlx5_core_health *health = &dev->priv.health; 1284 const int niter = 100; 1285 u32 count; 1286 u16 did; 1287 int i; 1288 1289 /* Wait for firmware to be ready after reset */ 1290 msleep(1000); 1291 for (i = 0; i < niter; i++) { 1292 if (pci_read_config_word(pdev, 2, &did)) { 1293 dev_warn(&pdev->dev, "failed reading config word\n"); 1294 break; 1295 } 1296 if (did == pdev->device) { 1297 dev_info(&pdev->dev, "device ID correctly read after %d iterations\n", i); 1298 break; 1299 } 1300 msleep(50); 1301 } 1302 if (i == niter) 1303 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__); 1304 1305 for (i = 0; i < niter; i++) { 1306 count = ioread32be(health->health_counter); 1307 if (count && count != 0xffffffff) { 1308 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i); 1309 break; 1310 } 1311 msleep(50); 1312 } 1313 1314 if (i == niter) 1315 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__); 1316} 1317 1318static void mlx5_pci_resume(struct pci_dev *pdev) 1319{ 1320 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1321 struct mlx5_priv *priv = &dev->priv; 1322 int err; 1323 1324 dev_info(&pdev->dev, "%s was called\n", __func__); 1325 1326 pci_save_state(pdev->dev.bsddev); 1327 wait_vital(pdev); 1328 1329 err = mlx5_load_one(dev, priv); 1330 if (err) 1331 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n" 1332 , __func__, err); 1333 else 1334 dev_info(&pdev->dev, "%s: device recovered\n", __func__); 1335} 1336 1337static const struct pci_error_handlers mlx5_err_handler = { 1338 .error_detected = mlx5_pci_err_detected, 1339 .slot_reset = mlx5_pci_slot_reset, 1340 .resume = mlx5_pci_resume 1341}; 1342 1343static void shutdown_one(struct pci_dev *pdev) 1344{ 1345 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1346 struct mlx5_priv *priv = &dev->priv; 1347 1348 set_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &dev->intf_state); 1349 mlx5_unload_one(dev, priv); 1350 mlx5_pci_disable_device(dev); 1351} 1352 1353static const struct pci_device_id mlx5_core_pci_table[] = { 1354 { PCI_VDEVICE(MELLANOX, 4113) }, /* Connect-IB */ 1355 { PCI_VDEVICE(MELLANOX, 4114) }, /* Connect-IB VF */ 1356 { PCI_VDEVICE(MELLANOX, 4115) }, /* ConnectX-4 */ 1357 { PCI_VDEVICE(MELLANOX, 4116) }, /* ConnectX-4 VF */ 1358 { PCI_VDEVICE(MELLANOX, 4117) }, /* ConnectX-4LX */ 1359 { PCI_VDEVICE(MELLANOX, 4118) }, /* ConnectX-4LX VF */ 1360 { PCI_VDEVICE(MELLANOX, 4119) }, /* ConnectX-5 */ 1361 { PCI_VDEVICE(MELLANOX, 4120) }, /* ConnectX-5 VF */ 1362 { PCI_VDEVICE(MELLANOX, 4121) }, 1363 { PCI_VDEVICE(MELLANOX, 4122) }, 1364 { PCI_VDEVICE(MELLANOX, 4123) }, 1365 { PCI_VDEVICE(MELLANOX, 4124) }, 1366 { PCI_VDEVICE(MELLANOX, 4125) }, 1367 { PCI_VDEVICE(MELLANOX, 4126) }, 1368 { PCI_VDEVICE(MELLANOX, 4127) }, 1369 { PCI_VDEVICE(MELLANOX, 4128) }, 1370 { PCI_VDEVICE(MELLANOX, 4129) }, 1371 { PCI_VDEVICE(MELLANOX, 4130) }, 1372 { PCI_VDEVICE(MELLANOX, 4131) }, 1373 { PCI_VDEVICE(MELLANOX, 4132) }, 1374 { PCI_VDEVICE(MELLANOX, 4133) }, 1375 { PCI_VDEVICE(MELLANOX, 4134) }, 1376 { PCI_VDEVICE(MELLANOX, 4135) }, 1377 { PCI_VDEVICE(MELLANOX, 4136) }, 1378 { PCI_VDEVICE(MELLANOX, 4137) }, 1379 { PCI_VDEVICE(MELLANOX, 4138) }, 1380 { PCI_VDEVICE(MELLANOX, 4139) }, 1381 { PCI_VDEVICE(MELLANOX, 4140) }, 1382 { PCI_VDEVICE(MELLANOX, 4141) }, 1383 { PCI_VDEVICE(MELLANOX, 4142) }, 1384 { PCI_VDEVICE(MELLANOX, 4143) }, 1385 { PCI_VDEVICE(MELLANOX, 4144) }, 1386 { 0, } 1387}; 1388 1389MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 1390 1391static struct pci_driver mlx5_core_driver = { 1392 .name = DRIVER_NAME, 1393 .id_table = mlx5_core_pci_table, 1394 .shutdown = shutdown_one, 1395 .probe = init_one, 1396 .remove = remove_one, 1397 .err_handler = &mlx5_err_handler 1398}; 1399 1400static int __init init(void) 1401{ 1402 int err; 1403 1404 err = pci_register_driver(&mlx5_core_driver); 1405 if (err) 1406 goto err_debug; 1407 1408 1409 return 0; 1410 1411err_debug: 1412 return err; 1413} 1414 1415static void __exit cleanup(void) 1416{ 1417 pci_unregister_driver(&mlx5_core_driver); 1418} 1419 1420module_init(init); 1421module_exit(cleanup); 1422