mlx5_eq.c revision 353266
1/*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_core/mlx5_eq.c 353266 2019-10-07 10:31:27Z hselasky $ 26 */ 27 28#include <linux/interrupt.h> 29#include <linux/module.h> 30#include <dev/mlx5/port.h> 31#include <dev/mlx5/mlx5_ifc.h> 32#include <dev/mlx5/mlx5_fpga/core.h> 33#include "mlx5_core.h" 34 35#include "opt_rss.h" 36 37#ifdef RSS 38#include <net/rss_config.h> 39#include <netinet/in_rss.h> 40#endif 41 42enum { 43 MLX5_EQE_SIZE = sizeof(struct mlx5_eqe), 44 MLX5_EQE_OWNER_INIT_VAL = 0x1, 45}; 46 47enum { 48 MLX5_NUM_SPARE_EQE = 0x80, 49 MLX5_NUM_ASYNC_EQE = 0x100, 50 MLX5_NUM_CMD_EQE = 32, 51}; 52 53enum { 54 MLX5_EQ_DOORBEL_OFFSET = 0x40, 55}; 56 57#define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG) | \ 58 (1ull << MLX5_EVENT_TYPE_COMM_EST) | \ 59 (1ull << MLX5_EVENT_TYPE_SQ_DRAINED) | \ 60 (1ull << MLX5_EVENT_TYPE_CQ_ERROR) | \ 61 (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR) | \ 62 (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED) | \ 63 (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \ 64 (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR) | \ 65 (1ull << MLX5_EVENT_TYPE_PORT_CHANGE) | \ 66 (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR) | \ 67 (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE) | \ 68 (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT)) 69 70struct map_eq_in { 71 u64 mask; 72 u32 reserved; 73 u32 unmap_eqn; 74}; 75 76struct cre_des_eq { 77 u8 reserved[15]; 78 u8 eqn; 79}; 80 81/*Function prototype*/ 82static void mlx5_port_module_event(struct mlx5_core_dev *dev, 83 struct mlx5_eqe *eqe); 84static void mlx5_port_general_notification_event(struct mlx5_core_dev *dev, 85 struct mlx5_eqe *eqe); 86 87static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn) 88{ 89 u32 in[MLX5_ST_SZ_DW(destroy_eq_in)] = {0}; 90 u32 out[MLX5_ST_SZ_DW(destroy_eq_out)] = {0}; 91 92 MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ); 93 MLX5_SET(destroy_eq_in, in, eq_number, eqn); 94 95 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 96} 97 98static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry) 99{ 100 return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE); 101} 102 103static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq) 104{ 105 struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1)); 106 107 return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe; 108} 109 110static const char *eqe_type_str(u8 type) 111{ 112 switch (type) { 113 case MLX5_EVENT_TYPE_COMP: 114 return "MLX5_EVENT_TYPE_COMP"; 115 case MLX5_EVENT_TYPE_PATH_MIG: 116 return "MLX5_EVENT_TYPE_PATH_MIG"; 117 case MLX5_EVENT_TYPE_COMM_EST: 118 return "MLX5_EVENT_TYPE_COMM_EST"; 119 case MLX5_EVENT_TYPE_SQ_DRAINED: 120 return "MLX5_EVENT_TYPE_SQ_DRAINED"; 121 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 122 return "MLX5_EVENT_TYPE_SRQ_LAST_WQE"; 123 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 124 return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT"; 125 case MLX5_EVENT_TYPE_CQ_ERROR: 126 return "MLX5_EVENT_TYPE_CQ_ERROR"; 127 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 128 return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR"; 129 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 130 return "MLX5_EVENT_TYPE_PATH_MIG_FAILED"; 131 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 132 return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR"; 133 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 134 return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR"; 135 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 136 return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR"; 137 case MLX5_EVENT_TYPE_INTERNAL_ERROR: 138 return "MLX5_EVENT_TYPE_INTERNAL_ERROR"; 139 case MLX5_EVENT_TYPE_PORT_CHANGE: 140 return "MLX5_EVENT_TYPE_PORT_CHANGE"; 141 case MLX5_EVENT_TYPE_GPIO_EVENT: 142 return "MLX5_EVENT_TYPE_GPIO_EVENT"; 143 case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT: 144 return "MLX5_EVENT_TYPE_PORT_MODULE_EVENT"; 145 case MLX5_EVENT_TYPE_TEMP_WARN_EVENT: 146 return "MLX5_EVENT_TYPE_TEMP_WARN_EVENT"; 147 case MLX5_EVENT_TYPE_REMOTE_CONFIG: 148 return "MLX5_EVENT_TYPE_REMOTE_CONFIG"; 149 case MLX5_EVENT_TYPE_DB_BF_CONGESTION: 150 return "MLX5_EVENT_TYPE_DB_BF_CONGESTION"; 151 case MLX5_EVENT_TYPE_STALL_EVENT: 152 return "MLX5_EVENT_TYPE_STALL_EVENT"; 153 case MLX5_EVENT_TYPE_CMD: 154 return "MLX5_EVENT_TYPE_CMD"; 155 case MLX5_EVENT_TYPE_PAGE_REQUEST: 156 return "MLX5_EVENT_TYPE_PAGE_REQUEST"; 157 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE: 158 return "MLX5_EVENT_TYPE_NIC_VPORT_CHANGE"; 159 case MLX5_EVENT_TYPE_FPGA_ERROR: 160 return "MLX5_EVENT_TYPE_FPGA_ERROR"; 161 case MLX5_EVENT_TYPE_FPGA_QP_ERROR: 162 return "MLX5_EVENT_TYPE_FPGA_QP_ERROR"; 163 case MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT: 164 return "MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT"; 165 case MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT: 166 return "MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT"; 167 default: 168 return "Unrecognized event"; 169 } 170} 171 172static enum mlx5_dev_event port_subtype_event(u8 subtype) 173{ 174 switch (subtype) { 175 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 176 return MLX5_DEV_EVENT_PORT_DOWN; 177 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 178 return MLX5_DEV_EVENT_PORT_UP; 179 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 180 return MLX5_DEV_EVENT_PORT_INITIALIZED; 181 case MLX5_PORT_CHANGE_SUBTYPE_LID: 182 return MLX5_DEV_EVENT_LID_CHANGE; 183 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 184 return MLX5_DEV_EVENT_PKEY_CHANGE; 185 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 186 return MLX5_DEV_EVENT_GUID_CHANGE; 187 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 188 return MLX5_DEV_EVENT_CLIENT_REREG; 189 } 190 return -1; 191} 192 193static enum mlx5_dev_event dcbx_subevent(u8 subtype) 194{ 195 switch (subtype) { 196 case MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX: 197 return MLX5_DEV_EVENT_ERROR_STATE_DCBX; 198 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE: 199 return MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE; 200 case MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE: 201 return MLX5_DEV_EVENT_LOCAL_OPER_CHANGE; 202 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE: 203 return MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE; 204 } 205 return -1; 206} 207 208static void eq_update_ci(struct mlx5_eq *eq, int arm) 209{ 210 __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2); 211 u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24); 212 __raw_writel((__force u32) cpu_to_be32(val), addr); 213 /* We still want ordering, just not swabbing, so add a barrier */ 214 mb(); 215} 216 217static void 218mlx5_temp_warning_event(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe) 219{ 220 221 mlx5_core_warn(dev, 222 "High temperature on sensors with bit set %#jx %#jx\n", 223 (uintmax_t)be64_to_cpu(eqe->data.temp_warning.sensor_warning_msb), 224 (uintmax_t)be64_to_cpu(eqe->data.temp_warning.sensor_warning_lsb)); 225} 226 227static int mlx5_eq_int(struct mlx5_core_dev *dev, struct mlx5_eq *eq) 228{ 229 struct mlx5_eqe *eqe; 230 int eqes_found = 0; 231 int set_ci = 0; 232 u32 cqn; 233 u32 rsn; 234 u8 port; 235 236 while ((eqe = next_eqe_sw(eq))) { 237 /* 238 * Make sure we read EQ entry contents after we've 239 * checked the ownership bit. 240 */ 241 rmb(); 242 243 mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n", 244 eq->eqn, eqe_type_str(eqe->type)); 245 switch (eqe->type) { 246 case MLX5_EVENT_TYPE_COMP: 247 cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff; 248 mlx5_cq_completion(dev, cqn); 249 break; 250 251 case MLX5_EVENT_TYPE_PATH_MIG: 252 case MLX5_EVENT_TYPE_COMM_EST: 253 case MLX5_EVENT_TYPE_SQ_DRAINED: 254 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 255 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 256 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 257 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 258 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 259 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; 260 mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n", 261 eqe_type_str(eqe->type), eqe->type, rsn); 262 mlx5_rsc_event(dev, rsn, eqe->type); 263 break; 264 265 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 266 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 267 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; 268 mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n", 269 eqe_type_str(eqe->type), eqe->type, rsn); 270 mlx5_srq_event(dev, rsn, eqe->type); 271 break; 272 273 case MLX5_EVENT_TYPE_CMD: 274 if (dev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 275 mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector), 276 MLX5_CMD_MODE_EVENTS); 277 } 278 break; 279 280 case MLX5_EVENT_TYPE_PORT_CHANGE: 281 port = (eqe->data.port.port >> 4) & 0xf; 282 switch (eqe->sub_type) { 283 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 284 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 285 case MLX5_PORT_CHANGE_SUBTYPE_LID: 286 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 287 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 288 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 289 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 290 if (dev->event) 291 dev->event(dev, port_subtype_event(eqe->sub_type), 292 (unsigned long)port); 293 break; 294 default: 295 mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n", 296 port, eqe->sub_type); 297 } 298 break; 299 300 case MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT: 301 port = (eqe->data.port.port >> 4) & 0xf; 302 switch (eqe->sub_type) { 303 case MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX: 304 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE: 305 case MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE: 306 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE: 307 if (dev->event) 308 dev->event(dev, 309 dcbx_subevent(eqe->sub_type), 310 0); 311 break; 312 default: 313 mlx5_core_warn(dev, 314 "dcbx event with unrecognized subtype: port %d, sub_type %d\n", 315 port, eqe->sub_type); 316 } 317 break; 318 319 case MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT: 320 mlx5_port_general_notification_event(dev, eqe); 321 break; 322 323 case MLX5_EVENT_TYPE_CQ_ERROR: 324 cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff; 325 mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n", 326 cqn, eqe->data.cq_err.syndrome); 327 mlx5_cq_event(dev, cqn, eqe->type); 328 break; 329 330 case MLX5_EVENT_TYPE_PAGE_REQUEST: 331 { 332 u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id); 333 s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages); 334 335 mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n", 336 func_id, npages); 337 mlx5_core_req_pages_handler(dev, func_id, npages); 338 } 339 break; 340 341 case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT: 342 mlx5_port_module_event(dev, eqe); 343 break; 344 345 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE: 346 { 347 struct mlx5_eqe_vport_change *vc_eqe = 348 &eqe->data.vport_change; 349 u16 vport_num = be16_to_cpu(vc_eqe->vport_num); 350 351 if (dev->event) 352 dev->event(dev, 353 MLX5_DEV_EVENT_VPORT_CHANGE, 354 (unsigned long)vport_num); 355 } 356 break; 357 358 case MLX5_EVENT_TYPE_FPGA_ERROR: 359 case MLX5_EVENT_TYPE_FPGA_QP_ERROR: 360 mlx5_fpga_event(dev, eqe->type, &eqe->data.raw); 361 break; 362 case MLX5_EVENT_TYPE_TEMP_WARN_EVENT: 363 mlx5_temp_warning_event(dev, eqe); 364 break; 365 366 default: 367 mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n", 368 eqe->type, eq->eqn); 369 break; 370 } 371 372 ++eq->cons_index; 373 eqes_found = 1; 374 ++set_ci; 375 376 /* The HCA will think the queue has overflowed if we 377 * don't tell it we've been processing events. We 378 * create our EQs with MLX5_NUM_SPARE_EQE extra 379 * entries, so we must update our consumer index at 380 * least that often. 381 */ 382 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) { 383 eq_update_ci(eq, 0); 384 set_ci = 0; 385 } 386 } 387 388 eq_update_ci(eq, 1); 389 390 return eqes_found; 391} 392 393static irqreturn_t mlx5_msix_handler(int irq, void *eq_ptr) 394{ 395 struct mlx5_eq *eq = eq_ptr; 396 struct mlx5_core_dev *dev = eq->dev; 397 398 /* check if IRQs are not disabled */ 399 if (likely(dev->priv.disable_irqs == 0)) 400 mlx5_eq_int(dev, eq); 401 402 /* MSI-X vectors always belong to us */ 403 return IRQ_HANDLED; 404} 405 406static void init_eq_buf(struct mlx5_eq *eq) 407{ 408 struct mlx5_eqe *eqe; 409 int i; 410 411 for (i = 0; i < eq->nent; i++) { 412 eqe = get_eqe(eq, i); 413 eqe->owner = MLX5_EQE_OWNER_INIT_VAL; 414 } 415} 416 417int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 418 int nent, u64 mask, struct mlx5_uar *uar) 419{ 420 u32 out[MLX5_ST_SZ_DW(create_eq_out)] = {0}; 421 struct mlx5_priv *priv = &dev->priv; 422 __be64 *pas; 423 void *eqc; 424 int inlen; 425 u32 *in; 426 int err; 427 428 eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE); 429 eq->cons_index = 0; 430 err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, 2 * PAGE_SIZE, 431 &eq->buf); 432 if (err) 433 return err; 434 435 init_eq_buf(eq); 436 437 inlen = MLX5_ST_SZ_BYTES(create_eq_in) + 438 MLX5_FLD_SZ_BYTES(create_eq_in, pas[0]) * eq->buf.npages; 439 in = mlx5_vzalloc(inlen); 440 if (!in) { 441 err = -ENOMEM; 442 goto err_buf; 443 } 444 445 pas = (__be64 *)MLX5_ADDR_OF(create_eq_in, in, pas); 446 mlx5_fill_page_array(&eq->buf, pas); 447 448 MLX5_SET(create_eq_in, in, opcode, MLX5_CMD_OP_CREATE_EQ); 449 MLX5_SET64(create_eq_in, in, event_bitmask, mask); 450 451 eqc = MLX5_ADDR_OF(create_eq_in, in, eq_context_entry); 452 MLX5_SET(eqc, eqc, log_eq_size, ilog2(eq->nent)); 453 MLX5_SET(eqc, eqc, uar_page, uar->index); 454 MLX5_SET(eqc, eqc, intr, vecidx); 455 MLX5_SET(eqc, eqc, log_page_size, 456 eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 457 458 err = mlx5_cmd_exec(dev, in, inlen, out, sizeof(out)); 459 if (err) 460 goto err_in; 461 462 eq->eqn = MLX5_GET(create_eq_out, out, eq_number); 463 eq->irqn = vecidx; 464 eq->dev = dev; 465 eq->doorbell = uar->map + MLX5_EQ_DOORBEL_OFFSET; 466 err = request_irq(priv->msix_arr[vecidx].vector, mlx5_msix_handler, 0, 467 "mlx5_core", eq); 468 if (err) 469 goto err_eq; 470#ifdef RSS 471 if (vecidx >= MLX5_EQ_VEC_COMP_BASE) { 472 u8 bucket = vecidx - MLX5_EQ_VEC_COMP_BASE; 473 err = bind_irq_to_cpu(priv->msix_arr[vecidx].vector, 474 rss_getcpu(bucket % rss_getnumbuckets())); 475 if (err) 476 goto err_irq; 477 } 478#else 479 if (0) 480 goto err_irq; 481#endif 482 483 484 /* EQs are created in ARMED state 485 */ 486 eq_update_ci(eq, 1); 487 488 kvfree(in); 489 return 0; 490 491err_irq: 492 free_irq(priv->msix_arr[vecidx].vector, eq); 493 494err_eq: 495 mlx5_cmd_destroy_eq(dev, eq->eqn); 496 497err_in: 498 kvfree(in); 499 500err_buf: 501 mlx5_buf_free(dev, &eq->buf); 502 return err; 503} 504EXPORT_SYMBOL_GPL(mlx5_create_map_eq); 505 506int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq) 507{ 508 int err; 509 510 free_irq(dev->priv.msix_arr[eq->irqn].vector, eq); 511 err = mlx5_cmd_destroy_eq(dev, eq->eqn); 512 if (err) 513 mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n", 514 eq->eqn); 515 mlx5_buf_free(dev, &eq->buf); 516 517 return err; 518} 519EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq); 520 521int mlx5_eq_init(struct mlx5_core_dev *dev) 522{ 523 int err; 524 525 spin_lock_init(&dev->priv.eq_table.lock); 526 527 err = 0; 528 529 return err; 530} 531 532 533void mlx5_eq_cleanup(struct mlx5_core_dev *dev) 534{ 535} 536 537int mlx5_start_eqs(struct mlx5_core_dev *dev) 538{ 539 struct mlx5_eq_table *table = &dev->priv.eq_table; 540 u64 async_event_mask = MLX5_ASYNC_EVENT_MASK; 541 int err; 542 543 if (MLX5_CAP_GEN(dev, port_module_event)) 544 async_event_mask |= (1ull << 545 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT); 546 547 if (MLX5_CAP_GEN(dev, nic_vport_change_event)) 548 async_event_mask |= (1ull << 549 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE); 550 551 if (MLX5_CAP_GEN(dev, dcbx)) 552 async_event_mask |= (1ull << 553 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT); 554 555 if (MLX5_CAP_GEN(dev, fpga)) 556 async_event_mask |= (1ull << MLX5_EVENT_TYPE_FPGA_ERROR) | 557 (1ull << MLX5_EVENT_TYPE_FPGA_QP_ERROR); 558 559 if (MLX5_CAP_GEN(dev, temp_warn_event)) 560 async_event_mask |= (1ull << MLX5_EVENT_TYPE_TEMP_WARN_EVENT); 561 562 if (MLX5_CAP_GEN(dev, general_notification_event)) { 563 async_event_mask |= (1ull << 564 MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT); 565 } 566 567 err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD, 568 MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD, 569 &dev->priv.uuari.uars[0]); 570 if (err) { 571 mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err); 572 return err; 573 } 574 575 mlx5_cmd_use_events(dev); 576 577 err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC, 578 MLX5_NUM_ASYNC_EQE, async_event_mask, 579 &dev->priv.uuari.uars[0]); 580 if (err) { 581 mlx5_core_warn(dev, "failed to create async EQ %d\n", err); 582 goto err1; 583 } 584 585 err = mlx5_create_map_eq(dev, &table->pages_eq, 586 MLX5_EQ_VEC_PAGES, 587 /* TODO: sriov max_vf + */ 1, 588 1 << MLX5_EVENT_TYPE_PAGE_REQUEST, 589 &dev->priv.uuari.uars[0]); 590 if (err) { 591 mlx5_core_warn(dev, "failed to create pages EQ %d\n", err); 592 goto err2; 593 } 594 595 return err; 596 597err2: 598 mlx5_destroy_unmap_eq(dev, &table->async_eq); 599 600err1: 601 mlx5_cmd_use_polling(dev); 602 mlx5_destroy_unmap_eq(dev, &table->cmd_eq); 603 return err; 604} 605 606int mlx5_stop_eqs(struct mlx5_core_dev *dev) 607{ 608 struct mlx5_eq_table *table = &dev->priv.eq_table; 609 int err; 610 611 err = mlx5_destroy_unmap_eq(dev, &table->pages_eq); 612 if (err) 613 return err; 614 615 mlx5_destroy_unmap_eq(dev, &table->async_eq); 616 mlx5_cmd_use_polling(dev); 617 618 err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq); 619 if (err) 620 mlx5_cmd_use_events(dev); 621 622 return err; 623} 624 625int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 626 u32 *out, int outlen) 627{ 628 u32 in[MLX5_ST_SZ_DW(query_eq_in)] = {0}; 629 630 memset(out, 0, outlen); 631 MLX5_SET(query_eq_in, in, opcode, MLX5_CMD_OP_QUERY_EQ); 632 MLX5_SET(query_eq_in, in, eq_number, eq->eqn); 633 634 return mlx5_cmd_exec(dev, in, sizeof(in), out, outlen); 635} 636EXPORT_SYMBOL_GPL(mlx5_core_eq_query); 637 638static const char *mlx5_port_module_event_error_type_to_string(u8 error_type) 639{ 640 switch (error_type) { 641 case MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED: 642 return "Power budget exceeded"; 643 case MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE: 644 return "Long Range for non MLNX cable"; 645 case MLX5_MODULE_EVENT_ERROR_BUS_STUCK: 646 return "Bus stuck(I2C or data shorted)"; 647 case MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT: 648 return "No EEPROM/retry timeout"; 649 case MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST: 650 return "Enforce part number list"; 651 case MLX5_MODULE_EVENT_ERROR_UNSUPPORTED_CABLE: 652 return "Unknown identifier"; 653 case MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE: 654 return "High Temperature"; 655 case MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED: 656 return "Bad or shorted cable/module"; 657 default: 658 return "Unknown error type"; 659 } 660} 661 662unsigned int mlx5_query_module_status(struct mlx5_core_dev *dev, int module_num) 663{ 664 if (module_num < 0 || module_num >= MLX5_MAX_PORTS) 665 return 0; /* undefined */ 666 return dev->module_status[module_num]; 667} 668 669static void mlx5_port_module_event(struct mlx5_core_dev *dev, 670 struct mlx5_eqe *eqe) 671{ 672 unsigned int module_num; 673 unsigned int module_status; 674 unsigned int error_type; 675 struct mlx5_eqe_port_module_event *module_event_eqe; 676 677 module_event_eqe = &eqe->data.port_module_event; 678 679 module_num = (unsigned int)module_event_eqe->module; 680 module_status = (unsigned int)module_event_eqe->module_status & 681 PORT_MODULE_EVENT_MODULE_STATUS_MASK; 682 error_type = (unsigned int)module_event_eqe->error_type & 683 PORT_MODULE_EVENT_ERROR_TYPE_MASK; 684 685 if (module_status < MLX5_MODULE_STATUS_NUM) 686 dev->priv.pme_stats.status_counters[module_status]++; 687 switch (module_status) { 688 case MLX5_MODULE_STATUS_PLUGGED_ENABLED: 689 mlx5_core_info(dev, 690 "Module %u, status: plugged and enabled\n", 691 module_num); 692 break; 693 694 case MLX5_MODULE_STATUS_UNPLUGGED: 695 mlx5_core_info(dev, 696 "Module %u, status: unplugged\n", module_num); 697 break; 698 699 case MLX5_MODULE_STATUS_ERROR: 700 mlx5_core_err(dev, 701 "Module %u, status: error, %s (%d)\n", 702 module_num, 703 mlx5_port_module_event_error_type_to_string(error_type), 704 error_type); 705 if (error_type < MLX5_MODULE_EVENT_ERROR_NUM) 706 dev->priv.pme_stats.error_counters[error_type]++; 707 break; 708 709 default: 710 mlx5_core_info(dev, 711 "Module %u, unknown status %d\n", module_num, module_status); 712 } 713 /* store module status */ 714 if (module_num < MLX5_MAX_PORTS) 715 dev->module_status[module_num] = module_status; 716} 717 718static void mlx5_port_general_notification_event(struct mlx5_core_dev *dev, 719 struct mlx5_eqe *eqe) 720{ 721 u8 port = (eqe->data.port.port >> 4) & 0xf; 722 u32 rqn; 723 struct mlx5_eqe_general_notification_event *general_event; 724 725 switch (eqe->sub_type) { 726 case MLX5_GEN_EVENT_SUBTYPE_DELAY_DROP_TIMEOUT: 727 general_event = &eqe->data.general_notifications; 728 rqn = be32_to_cpu(general_event->rq_user_index_delay_drop) & 729 0xffffff; 730 break; 731 case MLX5_GEN_EVENT_SUBTYPE_PCI_POWER_CHANGE_EVENT: 732 mlx5_trigger_health_watchdog(dev); 733 break; 734 default: 735 mlx5_core_warn(dev, 736 "general event with unrecognized subtype: port %d, sub_type %d\n", 737 port, eqe->sub_type); 738 break; 739 } 740} 741 742