mlx5_eq.c revision 347798
1/*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_core/mlx5_eq.c 347798 2019-05-16 17:11:45Z hselasky $ 26 */ 27 28#include <linux/interrupt.h> 29#include <linux/module.h> 30#include <dev/mlx5/port.h> 31#include <dev/mlx5/mlx5_ifc.h> 32#include <dev/mlx5/mlx5_fpga/core.h> 33#include "mlx5_core.h" 34 35#include "opt_rss.h" 36 37#ifdef RSS 38#include <net/rss_config.h> 39#include <netinet/in_rss.h> 40#endif 41 42enum { 43 MLX5_EQE_SIZE = sizeof(struct mlx5_eqe), 44 MLX5_EQE_OWNER_INIT_VAL = 0x1, 45}; 46 47enum { 48 MLX5_NUM_SPARE_EQE = 0x80, 49 MLX5_NUM_ASYNC_EQE = 0x100, 50 MLX5_NUM_CMD_EQE = 32, 51}; 52 53enum { 54 MLX5_EQ_DOORBEL_OFFSET = 0x40, 55}; 56 57#define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG) | \ 58 (1ull << MLX5_EVENT_TYPE_COMM_EST) | \ 59 (1ull << MLX5_EVENT_TYPE_SQ_DRAINED) | \ 60 (1ull << MLX5_EVENT_TYPE_CQ_ERROR) | \ 61 (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR) | \ 62 (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED) | \ 63 (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \ 64 (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR) | \ 65 (1ull << MLX5_EVENT_TYPE_PORT_CHANGE) | \ 66 (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR) | \ 67 (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE) | \ 68 (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT)) 69 70struct map_eq_in { 71 u64 mask; 72 u32 reserved; 73 u32 unmap_eqn; 74}; 75 76struct cre_des_eq { 77 u8 reserved[15]; 78 u8 eqn; 79}; 80 81/*Function prototype*/ 82static void mlx5_port_module_event(struct mlx5_core_dev *dev, 83 struct mlx5_eqe *eqe); 84static void mlx5_port_general_notification_event(struct mlx5_core_dev *dev, 85 struct mlx5_eqe *eqe); 86 87static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn) 88{ 89 u32 in[MLX5_ST_SZ_DW(destroy_eq_in)] = {0}; 90 u32 out[MLX5_ST_SZ_DW(destroy_eq_out)] = {0}; 91 92 MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ); 93 MLX5_SET(destroy_eq_in, in, eq_number, eqn); 94 95 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 96} 97 98static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry) 99{ 100 return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE); 101} 102 103static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq) 104{ 105 struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1)); 106 107 return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe; 108} 109 110static const char *eqe_type_str(u8 type) 111{ 112 switch (type) { 113 case MLX5_EVENT_TYPE_COMP: 114 return "MLX5_EVENT_TYPE_COMP"; 115 case MLX5_EVENT_TYPE_PATH_MIG: 116 return "MLX5_EVENT_TYPE_PATH_MIG"; 117 case MLX5_EVENT_TYPE_COMM_EST: 118 return "MLX5_EVENT_TYPE_COMM_EST"; 119 case MLX5_EVENT_TYPE_SQ_DRAINED: 120 return "MLX5_EVENT_TYPE_SQ_DRAINED"; 121 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 122 return "MLX5_EVENT_TYPE_SRQ_LAST_WQE"; 123 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 124 return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT"; 125 case MLX5_EVENT_TYPE_CQ_ERROR: 126 return "MLX5_EVENT_TYPE_CQ_ERROR"; 127 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 128 return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR"; 129 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 130 return "MLX5_EVENT_TYPE_PATH_MIG_FAILED"; 131 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 132 return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR"; 133 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 134 return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR"; 135 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 136 return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR"; 137 case MLX5_EVENT_TYPE_INTERNAL_ERROR: 138 return "MLX5_EVENT_TYPE_INTERNAL_ERROR"; 139 case MLX5_EVENT_TYPE_PORT_CHANGE: 140 return "MLX5_EVENT_TYPE_PORT_CHANGE"; 141 case MLX5_EVENT_TYPE_GPIO_EVENT: 142 return "MLX5_EVENT_TYPE_GPIO_EVENT"; 143 case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT: 144 return "MLX5_EVENT_TYPE_PORT_MODULE_EVENT"; 145 case MLX5_EVENT_TYPE_REMOTE_CONFIG: 146 return "MLX5_EVENT_TYPE_REMOTE_CONFIG"; 147 case MLX5_EVENT_TYPE_DB_BF_CONGESTION: 148 return "MLX5_EVENT_TYPE_DB_BF_CONGESTION"; 149 case MLX5_EVENT_TYPE_STALL_EVENT: 150 return "MLX5_EVENT_TYPE_STALL_EVENT"; 151 case MLX5_EVENT_TYPE_CMD: 152 return "MLX5_EVENT_TYPE_CMD"; 153 case MLX5_EVENT_TYPE_PAGE_REQUEST: 154 return "MLX5_EVENT_TYPE_PAGE_REQUEST"; 155 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE: 156 return "MLX5_EVENT_TYPE_NIC_VPORT_CHANGE"; 157 case MLX5_EVENT_TYPE_FPGA_ERROR: 158 return "MLX5_EVENT_TYPE_FPGA_ERROR"; 159 case MLX5_EVENT_TYPE_FPGA_QP_ERROR: 160 return "MLX5_EVENT_TYPE_FPGA_QP_ERROR"; 161 case MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT: 162 return "MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT"; 163 case MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT: 164 return "MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT"; 165 default: 166 return "Unrecognized event"; 167 } 168} 169 170static enum mlx5_dev_event port_subtype_event(u8 subtype) 171{ 172 switch (subtype) { 173 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 174 return MLX5_DEV_EVENT_PORT_DOWN; 175 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 176 return MLX5_DEV_EVENT_PORT_UP; 177 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 178 return MLX5_DEV_EVENT_PORT_INITIALIZED; 179 case MLX5_PORT_CHANGE_SUBTYPE_LID: 180 return MLX5_DEV_EVENT_LID_CHANGE; 181 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 182 return MLX5_DEV_EVENT_PKEY_CHANGE; 183 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 184 return MLX5_DEV_EVENT_GUID_CHANGE; 185 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 186 return MLX5_DEV_EVENT_CLIENT_REREG; 187 } 188 return -1; 189} 190 191static enum mlx5_dev_event dcbx_subevent(u8 subtype) 192{ 193 switch (subtype) { 194 case MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX: 195 return MLX5_DEV_EVENT_ERROR_STATE_DCBX; 196 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE: 197 return MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE; 198 case MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE: 199 return MLX5_DEV_EVENT_LOCAL_OPER_CHANGE; 200 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE: 201 return MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE; 202 } 203 return -1; 204} 205 206static void eq_update_ci(struct mlx5_eq *eq, int arm) 207{ 208 __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2); 209 u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24); 210 __raw_writel((__force u32) cpu_to_be32(val), addr); 211 /* We still want ordering, just not swabbing, so add a barrier */ 212 mb(); 213} 214 215static int mlx5_eq_int(struct mlx5_core_dev *dev, struct mlx5_eq *eq) 216{ 217 struct mlx5_eqe *eqe; 218 int eqes_found = 0; 219 int set_ci = 0; 220 u32 cqn; 221 u32 rsn; 222 u8 port; 223 224 while ((eqe = next_eqe_sw(eq))) { 225 /* 226 * Make sure we read EQ entry contents after we've 227 * checked the ownership bit. 228 */ 229 rmb(); 230 231 mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n", 232 eq->eqn, eqe_type_str(eqe->type)); 233 switch (eqe->type) { 234 case MLX5_EVENT_TYPE_COMP: 235 cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff; 236 mlx5_cq_completion(dev, cqn); 237 break; 238 239 case MLX5_EVENT_TYPE_PATH_MIG: 240 case MLX5_EVENT_TYPE_COMM_EST: 241 case MLX5_EVENT_TYPE_SQ_DRAINED: 242 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 243 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 244 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 245 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 246 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 247 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; 248 mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n", 249 eqe_type_str(eqe->type), eqe->type, rsn); 250 mlx5_rsc_event(dev, rsn, eqe->type); 251 break; 252 253 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 254 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 255 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; 256 mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n", 257 eqe_type_str(eqe->type), eqe->type, rsn); 258 mlx5_srq_event(dev, rsn, eqe->type); 259 break; 260 261 case MLX5_EVENT_TYPE_CMD: 262 if (dev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 263 mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector), 264 MLX5_CMD_MODE_EVENTS); 265 } 266 break; 267 268 case MLX5_EVENT_TYPE_PORT_CHANGE: 269 port = (eqe->data.port.port >> 4) & 0xf; 270 switch (eqe->sub_type) { 271 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 272 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 273 case MLX5_PORT_CHANGE_SUBTYPE_LID: 274 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 275 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 276 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 277 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 278 if (dev->event) 279 dev->event(dev, port_subtype_event(eqe->sub_type), 280 (unsigned long)port); 281 break; 282 default: 283 mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n", 284 port, eqe->sub_type); 285 } 286 break; 287 288 case MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT: 289 port = (eqe->data.port.port >> 4) & 0xf; 290 switch (eqe->sub_type) { 291 case MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX: 292 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE: 293 case MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE: 294 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE: 295 if (dev->event) 296 dev->event(dev, 297 dcbx_subevent(eqe->sub_type), 298 0); 299 break; 300 default: 301 mlx5_core_warn(dev, 302 "dcbx event with unrecognized subtype: port %d, sub_type %d\n", 303 port, eqe->sub_type); 304 } 305 break; 306 307 case MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT: 308 mlx5_port_general_notification_event(dev, eqe); 309 break; 310 311 case MLX5_EVENT_TYPE_CQ_ERROR: 312 cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff; 313 mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n", 314 cqn, eqe->data.cq_err.syndrome); 315 mlx5_cq_event(dev, cqn, eqe->type); 316 break; 317 318 case MLX5_EVENT_TYPE_PAGE_REQUEST: 319 { 320 u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id); 321 s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages); 322 323 mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n", 324 func_id, npages); 325 mlx5_core_req_pages_handler(dev, func_id, npages); 326 } 327 break; 328 329 case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT: 330 mlx5_port_module_event(dev, eqe); 331 break; 332 333 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE: 334 { 335 struct mlx5_eqe_vport_change *vc_eqe = 336 &eqe->data.vport_change; 337 u16 vport_num = be16_to_cpu(vc_eqe->vport_num); 338 339 if (dev->event) 340 dev->event(dev, 341 MLX5_DEV_EVENT_VPORT_CHANGE, 342 (unsigned long)vport_num); 343 } 344 break; 345 346 case MLX5_EVENT_TYPE_FPGA_ERROR: 347 case MLX5_EVENT_TYPE_FPGA_QP_ERROR: 348 mlx5_fpga_event(dev, eqe->type, &eqe->data.raw); 349 break; 350 351 default: 352 mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n", 353 eqe->type, eq->eqn); 354 break; 355 } 356 357 ++eq->cons_index; 358 eqes_found = 1; 359 ++set_ci; 360 361 /* The HCA will think the queue has overflowed if we 362 * don't tell it we've been processing events. We 363 * create our EQs with MLX5_NUM_SPARE_EQE extra 364 * entries, so we must update our consumer index at 365 * least that often. 366 */ 367 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) { 368 eq_update_ci(eq, 0); 369 set_ci = 0; 370 } 371 } 372 373 eq_update_ci(eq, 1); 374 375 return eqes_found; 376} 377 378static irqreturn_t mlx5_msix_handler(int irq, void *eq_ptr) 379{ 380 struct mlx5_eq *eq = eq_ptr; 381 struct mlx5_core_dev *dev = eq->dev; 382 383 mlx5_eq_int(dev, eq); 384 385 /* MSI-X vectors always belong to us */ 386 return IRQ_HANDLED; 387} 388 389static void init_eq_buf(struct mlx5_eq *eq) 390{ 391 struct mlx5_eqe *eqe; 392 int i; 393 394 for (i = 0; i < eq->nent; i++) { 395 eqe = get_eqe(eq, i); 396 eqe->owner = MLX5_EQE_OWNER_INIT_VAL; 397 } 398} 399 400int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 401 int nent, u64 mask, const char *name, struct mlx5_uar *uar) 402{ 403 u32 out[MLX5_ST_SZ_DW(create_eq_out)] = {0}; 404 struct mlx5_priv *priv = &dev->priv; 405 __be64 *pas; 406 void *eqc; 407 int inlen; 408 u32 *in; 409 int err; 410 411 eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE); 412 eq->cons_index = 0; 413 err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, 2 * PAGE_SIZE, 414 &eq->buf); 415 if (err) 416 return err; 417 418 init_eq_buf(eq); 419 420 inlen = MLX5_ST_SZ_BYTES(create_eq_in) + 421 MLX5_FLD_SZ_BYTES(create_eq_in, pas[0]) * eq->buf.npages; 422 in = mlx5_vzalloc(inlen); 423 if (!in) { 424 err = -ENOMEM; 425 goto err_buf; 426 } 427 428 pas = (__be64 *)MLX5_ADDR_OF(create_eq_in, in, pas); 429 mlx5_fill_page_array(&eq->buf, pas); 430 431 MLX5_SET(create_eq_in, in, opcode, MLX5_CMD_OP_CREATE_EQ); 432 MLX5_SET64(create_eq_in, in, event_bitmask, mask); 433 434 eqc = MLX5_ADDR_OF(create_eq_in, in, eq_context_entry); 435 MLX5_SET(eqc, eqc, log_eq_size, ilog2(eq->nent)); 436 MLX5_SET(eqc, eqc, uar_page, uar->index); 437 MLX5_SET(eqc, eqc, intr, vecidx); 438 MLX5_SET(eqc, eqc, log_page_size, 439 eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 440 441 err = mlx5_cmd_exec(dev, in, inlen, out, sizeof(out)); 442 if (err) 443 goto err_in; 444 445 eq->eqn = MLX5_GET(create_eq_out, out, eq_number); 446 eq->irqn = vecidx; 447 eq->dev = dev; 448 eq->doorbell = uar->map + MLX5_EQ_DOORBEL_OFFSET; 449 snprintf(priv->irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s", 450 name, pci_name(dev->pdev)); 451 err = request_irq(priv->msix_arr[vecidx].vector, mlx5_msix_handler, 0, 452 priv->irq_info[vecidx].name, eq); 453 if (err) 454 goto err_eq; 455#ifdef RSS 456 if (vecidx >= MLX5_EQ_VEC_COMP_BASE) { 457 u8 bucket = vecidx - MLX5_EQ_VEC_COMP_BASE; 458 err = bind_irq_to_cpu(priv->msix_arr[vecidx].vector, 459 rss_getcpu(bucket % rss_getnumbuckets())); 460 if (err) 461 goto err_irq; 462 } 463#else 464 if (0) 465 goto err_irq; 466#endif 467 468 469 /* EQs are created in ARMED state 470 */ 471 eq_update_ci(eq, 1); 472 473 kvfree(in); 474 return 0; 475 476err_irq: 477 free_irq(priv->msix_arr[vecidx].vector, eq); 478 479err_eq: 480 mlx5_cmd_destroy_eq(dev, eq->eqn); 481 482err_in: 483 kvfree(in); 484 485err_buf: 486 mlx5_buf_free(dev, &eq->buf); 487 return err; 488} 489EXPORT_SYMBOL_GPL(mlx5_create_map_eq); 490 491int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq) 492{ 493 int err; 494 495 free_irq(dev->priv.msix_arr[eq->irqn].vector, eq); 496 err = mlx5_cmd_destroy_eq(dev, eq->eqn); 497 if (err) 498 mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n", 499 eq->eqn); 500 mlx5_buf_free(dev, &eq->buf); 501 502 return err; 503} 504EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq); 505 506int mlx5_eq_init(struct mlx5_core_dev *dev) 507{ 508 int err; 509 510 spin_lock_init(&dev->priv.eq_table.lock); 511 512 err = 0; 513 514 return err; 515} 516 517 518void mlx5_eq_cleanup(struct mlx5_core_dev *dev) 519{ 520} 521 522int mlx5_start_eqs(struct mlx5_core_dev *dev) 523{ 524 struct mlx5_eq_table *table = &dev->priv.eq_table; 525 u64 async_event_mask = MLX5_ASYNC_EVENT_MASK; 526 int err; 527 528 if (MLX5_CAP_GEN(dev, port_module_event)) 529 async_event_mask |= (1ull << 530 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT); 531 532 if (MLX5_CAP_GEN(dev, nic_vport_change_event)) 533 async_event_mask |= (1ull << 534 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE); 535 536 if (MLX5_CAP_GEN(dev, dcbx)) 537 async_event_mask |= (1ull << 538 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT); 539 540 if (MLX5_CAP_GEN(dev, fpga)) 541 async_event_mask |= (1ull << MLX5_EVENT_TYPE_FPGA_ERROR) | 542 (1ull << MLX5_EVENT_TYPE_FPGA_QP_ERROR); 543 544 err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD, 545 MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD, 546 "mlx5_cmd_eq", &dev->priv.uuari.uars[0]); 547 if (err) { 548 mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err); 549 return err; 550 } 551 552 mlx5_cmd_use_events(dev); 553 554 err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC, 555 MLX5_NUM_ASYNC_EQE, async_event_mask, 556 "mlx5_async_eq", &dev->priv.uuari.uars[0]); 557 if (err) { 558 mlx5_core_warn(dev, "failed to create async EQ %d\n", err); 559 goto err1; 560 } 561 562 err = mlx5_create_map_eq(dev, &table->pages_eq, 563 MLX5_EQ_VEC_PAGES, 564 /* TODO: sriov max_vf + */ 1, 565 1 << MLX5_EVENT_TYPE_PAGE_REQUEST, "mlx5_pages_eq", 566 &dev->priv.uuari.uars[0]); 567 if (err) { 568 mlx5_core_warn(dev, "failed to create pages EQ %d\n", err); 569 goto err2; 570 } 571 572 return err; 573 574err2: 575 mlx5_destroy_unmap_eq(dev, &table->async_eq); 576 577err1: 578 mlx5_cmd_use_polling(dev); 579 mlx5_destroy_unmap_eq(dev, &table->cmd_eq); 580 return err; 581} 582 583int mlx5_stop_eqs(struct mlx5_core_dev *dev) 584{ 585 struct mlx5_eq_table *table = &dev->priv.eq_table; 586 int err; 587 588 err = mlx5_destroy_unmap_eq(dev, &table->pages_eq); 589 if (err) 590 return err; 591 592 mlx5_destroy_unmap_eq(dev, &table->async_eq); 593 mlx5_cmd_use_polling(dev); 594 595 err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq); 596 if (err) 597 mlx5_cmd_use_events(dev); 598 599 return err; 600} 601 602int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 603 u32 *out, int outlen) 604{ 605 u32 in[MLX5_ST_SZ_DW(query_eq_in)] = {0}; 606 607 memset(out, 0, outlen); 608 MLX5_SET(query_eq_in, in, opcode, MLX5_CMD_OP_QUERY_EQ); 609 MLX5_SET(query_eq_in, in, eq_number, eq->eqn); 610 611 return mlx5_cmd_exec(dev, in, sizeof(in), out, outlen); 612} 613EXPORT_SYMBOL_GPL(mlx5_core_eq_query); 614 615static const char *mlx5_port_module_event_error_type_to_string(u8 error_type) 616{ 617 switch (error_type) { 618 case MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED: 619 return "Power Budget Exceeded"; 620 case MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE: 621 return "Long Range for non MLNX cable/module"; 622 case MLX5_MODULE_EVENT_ERROR_BUS_STUCK: 623 return "Bus stuck(I2C or data shorted)"; 624 case MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT: 625 return "No EEPROM/retry timeout"; 626 case MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST: 627 return "Enforce part number list"; 628 case MLX5_MODULE_EVENT_ERROR_UNSUPPORTED_CABLE: 629 return "Unsupported Cable"; 630 case MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE: 631 return "High Temperature"; 632 case MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED: 633 return "Cable is shorted"; 634 case MLX5_MODULE_EVENT_ERROR_PCIE_SYSTEM_POWER_SLOT_EXCEEDED: 635 return "One or more network ports have been powered " 636 "down due to insufficient/unadvertised power on " 637 "the PCIe slot. Please refer to the card's user " 638 "manual for power specifications or contact " 639 "Mellanox support."; 640 641 default: 642 return "Unknown error type"; 643 } 644} 645 646unsigned int mlx5_query_module_status(struct mlx5_core_dev *dev, int module_num) 647{ 648 if (module_num < 0 || module_num >= MLX5_MAX_PORTS) 649 return 0; /* undefined */ 650 return dev->module_status[module_num]; 651} 652 653static void mlx5_port_module_event(struct mlx5_core_dev *dev, 654 struct mlx5_eqe *eqe) 655{ 656 unsigned int module_num; 657 unsigned int module_status; 658 unsigned int error_type; 659 struct mlx5_eqe_port_module_event *module_event_eqe; 660 struct pci_dev *pdev = dev->pdev; 661 662 module_event_eqe = &eqe->data.port_module_event; 663 664 module_num = (unsigned int)module_event_eqe->module; 665 module_status = (unsigned int)module_event_eqe->module_status & 666 PORT_MODULE_EVENT_MODULE_STATUS_MASK; 667 error_type = (unsigned int)module_event_eqe->error_type & 668 PORT_MODULE_EVENT_ERROR_TYPE_MASK; 669 670 switch (module_status) { 671 case MLX5_MODULE_STATUS_PLUGGED_ENABLED: 672 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: plugged and enabled\n", module_num); 673 break; 674 675 case MLX5_MODULE_STATUS_UNPLUGGED: 676 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: unplugged\n", module_num); 677 break; 678 679 case MLX5_MODULE_STATUS_ERROR: 680 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: error, %s\n", module_num, mlx5_port_module_event_error_type_to_string(error_type)); 681 break; 682 683 case MLX5_MODULE_STATUS_PLUGGED_DISABLED: 684 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: plugged but disabled\n", module_num); 685 break; 686 687 default: 688 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, unknown status\n", module_num); 689 } 690 /* store module status */ 691 if (module_num < MLX5_MAX_PORTS) 692 dev->module_status[module_num] = module_status; 693} 694 695static void mlx5_port_general_notification_event(struct mlx5_core_dev *dev, 696 struct mlx5_eqe *eqe) 697{ 698 u8 port = (eqe->data.port.port >> 4) & 0xf; 699 u32 rqn = 0; 700 struct mlx5_eqe_general_notification_event *general_event = NULL; 701 702 switch (eqe->sub_type) { 703 case MLX5_GEN_EVENT_SUBTYPE_DELAY_DROP_TIMEOUT: 704 general_event = &eqe->data.general_notifications; 705 rqn = be32_to_cpu(general_event->rq_user_index_delay_drop) & 706 0xffffff; 707 break; 708 default: 709 mlx5_core_warn(dev, 710 "general event with unrecognized subtype: port %d, sub_type %d\n", 711 port, eqe->sub_type); 712 break; 713 } 714} 715 716