mlx5_eq.c revision 331580
1/*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_core/mlx5_eq.c 331580 2018-03-26 20:33:31Z hselasky $ 26 */ 27 28#include <linux/interrupt.h> 29#include <linux/module.h> 30#include <dev/mlx5/port.h> 31#include <dev/mlx5/mlx5_ifc.h> 32#include "mlx5_core.h" 33 34#include "opt_rss.h" 35 36#ifdef RSS 37#include <net/rss_config.h> 38#include <netinet/in_rss.h> 39#endif 40 41enum { 42 MLX5_EQE_SIZE = sizeof(struct mlx5_eqe), 43 MLX5_EQE_OWNER_INIT_VAL = 0x1, 44}; 45 46enum { 47 MLX5_NUM_SPARE_EQE = 0x80, 48 MLX5_NUM_ASYNC_EQE = 0x100, 49 MLX5_NUM_CMD_EQE = 32, 50}; 51 52enum { 53 MLX5_EQ_DOORBEL_OFFSET = 0x40, 54}; 55 56#define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG) | \ 57 (1ull << MLX5_EVENT_TYPE_COMM_EST) | \ 58 (1ull << MLX5_EVENT_TYPE_SQ_DRAINED) | \ 59 (1ull << MLX5_EVENT_TYPE_CQ_ERROR) | \ 60 (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR) | \ 61 (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED) | \ 62 (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \ 63 (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR) | \ 64 (1ull << MLX5_EVENT_TYPE_PORT_CHANGE) | \ 65 (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR) | \ 66 (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE) | \ 67 (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT)) 68 69struct map_eq_in { 70 u64 mask; 71 u32 reserved; 72 u32 unmap_eqn; 73}; 74 75struct cre_des_eq { 76 u8 reserved[15]; 77 u8 eqn; 78}; 79 80/*Function prototype*/ 81static void mlx5_port_module_event(struct mlx5_core_dev *dev, 82 struct mlx5_eqe *eqe); 83static void mlx5_port_general_notification_event(struct mlx5_core_dev *dev, 84 struct mlx5_eqe *eqe); 85 86static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn) 87{ 88 u32 in[MLX5_ST_SZ_DW(destroy_eq_in)]; 89 u32 out[MLX5_ST_SZ_DW(destroy_eq_out)]; 90 91 memset(in, 0, sizeof(in)); 92 93 MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ); 94 MLX5_SET(destroy_eq_in, in, eq_number, eqn); 95 96 memset(out, 0, sizeof(out)); 97 return mlx5_cmd_exec_check_status(dev, in, sizeof(in), 98 out, sizeof(out)); 99} 100 101static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry) 102{ 103 return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE); 104} 105 106static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq) 107{ 108 struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1)); 109 110 return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe; 111} 112 113static const char *eqe_type_str(u8 type) 114{ 115 switch (type) { 116 case MLX5_EVENT_TYPE_COMP: 117 return "MLX5_EVENT_TYPE_COMP"; 118 case MLX5_EVENT_TYPE_PATH_MIG: 119 return "MLX5_EVENT_TYPE_PATH_MIG"; 120 case MLX5_EVENT_TYPE_COMM_EST: 121 return "MLX5_EVENT_TYPE_COMM_EST"; 122 case MLX5_EVENT_TYPE_SQ_DRAINED: 123 return "MLX5_EVENT_TYPE_SQ_DRAINED"; 124 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 125 return "MLX5_EVENT_TYPE_SRQ_LAST_WQE"; 126 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 127 return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT"; 128 case MLX5_EVENT_TYPE_CQ_ERROR: 129 return "MLX5_EVENT_TYPE_CQ_ERROR"; 130 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 131 return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR"; 132 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 133 return "MLX5_EVENT_TYPE_PATH_MIG_FAILED"; 134 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 135 return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR"; 136 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 137 return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR"; 138 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 139 return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR"; 140 case MLX5_EVENT_TYPE_INTERNAL_ERROR: 141 return "MLX5_EVENT_TYPE_INTERNAL_ERROR"; 142 case MLX5_EVENT_TYPE_PORT_CHANGE: 143 return "MLX5_EVENT_TYPE_PORT_CHANGE"; 144 case MLX5_EVENT_TYPE_GPIO_EVENT: 145 return "MLX5_EVENT_TYPE_GPIO_EVENT"; 146 case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT: 147 return "MLX5_EVENT_TYPE_PORT_MODULE_EVENT"; 148 case MLX5_EVENT_TYPE_REMOTE_CONFIG: 149 return "MLX5_EVENT_TYPE_REMOTE_CONFIG"; 150 case MLX5_EVENT_TYPE_DB_BF_CONGESTION: 151 return "MLX5_EVENT_TYPE_DB_BF_CONGESTION"; 152 case MLX5_EVENT_TYPE_STALL_EVENT: 153 return "MLX5_EVENT_TYPE_STALL_EVENT"; 154 case MLX5_EVENT_TYPE_CMD: 155 return "MLX5_EVENT_TYPE_CMD"; 156 case MLX5_EVENT_TYPE_PAGE_REQUEST: 157 return "MLX5_EVENT_TYPE_PAGE_REQUEST"; 158 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE: 159 return "MLX5_EVENT_TYPE_NIC_VPORT_CHANGE"; 160 case MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT: 161 return "MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT"; 162 case MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT: 163 return "MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT"; 164 default: 165 return "Unrecognized event"; 166 } 167} 168 169static enum mlx5_dev_event port_subtype_event(u8 subtype) 170{ 171 switch (subtype) { 172 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 173 return MLX5_DEV_EVENT_PORT_DOWN; 174 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 175 return MLX5_DEV_EVENT_PORT_UP; 176 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 177 return MLX5_DEV_EVENT_PORT_INITIALIZED; 178 case MLX5_PORT_CHANGE_SUBTYPE_LID: 179 return MLX5_DEV_EVENT_LID_CHANGE; 180 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 181 return MLX5_DEV_EVENT_PKEY_CHANGE; 182 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 183 return MLX5_DEV_EVENT_GUID_CHANGE; 184 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 185 return MLX5_DEV_EVENT_CLIENT_REREG; 186 } 187 return -1; 188} 189 190static enum mlx5_dev_event dcbx_subevent(u8 subtype) 191{ 192 switch (subtype) { 193 case MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX: 194 return MLX5_DEV_EVENT_ERROR_STATE_DCBX; 195 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE: 196 return MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE; 197 case MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE: 198 return MLX5_DEV_EVENT_LOCAL_OPER_CHANGE; 199 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE: 200 return MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE; 201 } 202 return -1; 203} 204 205static void eq_update_ci(struct mlx5_eq *eq, int arm) 206{ 207 __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2); 208 u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24); 209 __raw_writel((__force u32) cpu_to_be32(val), addr); 210 /* We still want ordering, just not swabbing, so add a barrier */ 211 mb(); 212} 213 214static int mlx5_eq_int(struct mlx5_core_dev *dev, struct mlx5_eq *eq) 215{ 216 struct mlx5_eqe *eqe; 217 int eqes_found = 0; 218 int set_ci = 0; 219 u32 cqn; 220 u32 rsn; 221 u8 port; 222 223 while ((eqe = next_eqe_sw(eq))) { 224 /* 225 * Make sure we read EQ entry contents after we've 226 * checked the ownership bit. 227 */ 228 rmb(); 229 230 mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n", 231 eq->eqn, eqe_type_str(eqe->type)); 232 switch (eqe->type) { 233 case MLX5_EVENT_TYPE_COMP: 234 cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff; 235 mlx5_cq_completion(dev, cqn); 236 break; 237 238 case MLX5_EVENT_TYPE_PATH_MIG: 239 case MLX5_EVENT_TYPE_COMM_EST: 240 case MLX5_EVENT_TYPE_SQ_DRAINED: 241 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 242 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 243 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 244 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 245 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 246 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; 247 mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n", 248 eqe_type_str(eqe->type), eqe->type, rsn); 249 mlx5_rsc_event(dev, rsn, eqe->type); 250 break; 251 252 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 253 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 254 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; 255 mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n", 256 eqe_type_str(eqe->type), eqe->type, rsn); 257 mlx5_srq_event(dev, rsn, eqe->type); 258 break; 259 260 case MLX5_EVENT_TYPE_CMD: 261 mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector)); 262 break; 263 264 case MLX5_EVENT_TYPE_PORT_CHANGE: 265 port = (eqe->data.port.port >> 4) & 0xf; 266 switch (eqe->sub_type) { 267 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 268 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 269 case MLX5_PORT_CHANGE_SUBTYPE_LID: 270 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 271 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 272 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 273 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 274 if (dev->event) 275 dev->event(dev, port_subtype_event(eqe->sub_type), 276 (unsigned long)port); 277 break; 278 default: 279 mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n", 280 port, eqe->sub_type); 281 } 282 break; 283 284 case MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT: 285 port = (eqe->data.port.port >> 4) & 0xf; 286 switch (eqe->sub_type) { 287 case MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX: 288 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE: 289 case MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE: 290 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE: 291 if (dev->event) 292 dev->event(dev, 293 dcbx_subevent(eqe->sub_type), 294 0); 295 break; 296 default: 297 mlx5_core_warn(dev, 298 "dcbx event with unrecognized subtype: port %d, sub_type %d\n", 299 port, eqe->sub_type); 300 } 301 break; 302 303 case MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT: 304 mlx5_port_general_notification_event(dev, eqe); 305 break; 306 307 case MLX5_EVENT_TYPE_CQ_ERROR: 308 cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff; 309 mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n", 310 cqn, eqe->data.cq_err.syndrome); 311 mlx5_cq_event(dev, cqn, eqe->type); 312 break; 313 314 case MLX5_EVENT_TYPE_PAGE_REQUEST: 315 { 316 u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id); 317 s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages); 318 319 mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n", 320 func_id, npages); 321 mlx5_core_req_pages_handler(dev, func_id, npages); 322 } 323 break; 324 325 case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT: 326 mlx5_port_module_event(dev, eqe); 327 break; 328 329 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE: 330 { 331 struct mlx5_eqe_vport_change *vc_eqe = 332 &eqe->data.vport_change; 333 u16 vport_num = be16_to_cpu(vc_eqe->vport_num); 334 335 if (dev->event) 336 dev->event(dev, 337 MLX5_DEV_EVENT_VPORT_CHANGE, 338 (unsigned long)vport_num); 339 } 340 break; 341 342 default: 343 mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n", 344 eqe->type, eq->eqn); 345 break; 346 } 347 348 ++eq->cons_index; 349 eqes_found = 1; 350 ++set_ci; 351 352 /* The HCA will think the queue has overflowed if we 353 * don't tell it we've been processing events. We 354 * create our EQs with MLX5_NUM_SPARE_EQE extra 355 * entries, so we must update our consumer index at 356 * least that often. 357 */ 358 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) { 359 eq_update_ci(eq, 0); 360 set_ci = 0; 361 } 362 } 363 364 eq_update_ci(eq, 1); 365 366 return eqes_found; 367} 368 369static irqreturn_t mlx5_msix_handler(int irq, void *eq_ptr) 370{ 371 struct mlx5_eq *eq = eq_ptr; 372 struct mlx5_core_dev *dev = eq->dev; 373 374 mlx5_eq_int(dev, eq); 375 376 /* MSI-X vectors always belong to us */ 377 return IRQ_HANDLED; 378} 379 380static void init_eq_buf(struct mlx5_eq *eq) 381{ 382 struct mlx5_eqe *eqe; 383 int i; 384 385 for (i = 0; i < eq->nent; i++) { 386 eqe = get_eqe(eq, i); 387 eqe->owner = MLX5_EQE_OWNER_INIT_VAL; 388 } 389} 390 391int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 392 int nent, u64 mask, const char *name, struct mlx5_uar *uar) 393{ 394 struct mlx5_priv *priv = &dev->priv; 395 struct mlx5_create_eq_mbox_in *in; 396 struct mlx5_create_eq_mbox_out out; 397 int err; 398 int inlen; 399 400 eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE); 401 eq->cons_index = 0; 402 err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, 2 * PAGE_SIZE, 403 &eq->buf); 404 if (err) 405 return err; 406 407 init_eq_buf(eq); 408 409 inlen = sizeof(*in) + sizeof(in->pas[0]) * eq->buf.npages; 410 in = mlx5_vzalloc(inlen); 411 if (!in) { 412 err = -ENOMEM; 413 goto err_buf; 414 } 415 memset(&out, 0, sizeof(out)); 416 417 mlx5_fill_page_array(&eq->buf, in->pas); 418 419 in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_CREATE_EQ); 420 in->ctx.log_sz_usr_page = cpu_to_be32(ilog2(eq->nent) << 24 | uar->index); 421 in->ctx.intr = vecidx; 422 in->ctx.log_page_size = eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT; 423 in->events_mask = cpu_to_be64(mask); 424 425 err = mlx5_cmd_exec(dev, in, inlen, &out, sizeof(out)); 426 if (err) 427 goto err_in; 428 429 if (out.hdr.status) { 430 err = mlx5_cmd_status_to_err(&out.hdr); 431 goto err_in; 432 } 433 434 eq->eqn = out.eq_number; 435 eq->irqn = vecidx; 436 eq->dev = dev; 437 eq->doorbell = uar->map + MLX5_EQ_DOORBEL_OFFSET; 438 snprintf(priv->irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s", 439 name, pci_name(dev->pdev)); 440 err = request_irq(priv->msix_arr[vecidx].vector, mlx5_msix_handler, 0, 441 priv->irq_info[vecidx].name, eq); 442 if (err) 443 goto err_eq; 444#ifdef RSS 445 if (vecidx >= MLX5_EQ_VEC_COMP_BASE) { 446 u8 bucket = vecidx - MLX5_EQ_VEC_COMP_BASE; 447 err = bind_irq_to_cpu(priv->msix_arr[vecidx].vector, 448 rss_getcpu(bucket % rss_getnumbuckets())); 449 if (err) 450 goto err_irq; 451 } 452#else 453 if (0) 454 goto err_irq; 455#endif 456 457 458 /* EQs are created in ARMED state 459 */ 460 eq_update_ci(eq, 1); 461 462 kvfree(in); 463 return 0; 464 465err_irq: 466 free_irq(priv->msix_arr[vecidx].vector, eq); 467 468err_eq: 469 mlx5_cmd_destroy_eq(dev, eq->eqn); 470 471err_in: 472 kvfree(in); 473 474err_buf: 475 mlx5_buf_free(dev, &eq->buf); 476 return err; 477} 478EXPORT_SYMBOL_GPL(mlx5_create_map_eq); 479 480int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq) 481{ 482 int err; 483 484 free_irq(dev->priv.msix_arr[eq->irqn].vector, eq); 485 err = mlx5_cmd_destroy_eq(dev, eq->eqn); 486 if (err) 487 mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n", 488 eq->eqn); 489 mlx5_buf_free(dev, &eq->buf); 490 491 return err; 492} 493EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq); 494 495int mlx5_eq_init(struct mlx5_core_dev *dev) 496{ 497 int err; 498 499 spin_lock_init(&dev->priv.eq_table.lock); 500 501 err = 0; 502 503 return err; 504} 505 506 507void mlx5_eq_cleanup(struct mlx5_core_dev *dev) 508{ 509} 510 511int mlx5_start_eqs(struct mlx5_core_dev *dev) 512{ 513 struct mlx5_eq_table *table = &dev->priv.eq_table; 514 u64 async_event_mask = MLX5_ASYNC_EVENT_MASK; 515 int err; 516 517 if (MLX5_CAP_GEN(dev, port_module_event)) 518 async_event_mask |= (1ull << 519 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT); 520 521 if (MLX5_CAP_GEN(dev, nic_vport_change_event)) 522 async_event_mask |= (1ull << 523 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE); 524 525 if (MLX5_CAP_GEN(dev, dcbx)) 526 async_event_mask |= (1ull << 527 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT); 528 529 err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD, 530 MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD, 531 "mlx5_cmd_eq", &dev->priv.uuari.uars[0]); 532 if (err) { 533 mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err); 534 return err; 535 } 536 537 mlx5_cmd_use_events(dev); 538 539 err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC, 540 MLX5_NUM_ASYNC_EQE, async_event_mask, 541 "mlx5_async_eq", &dev->priv.uuari.uars[0]); 542 if (err) { 543 mlx5_core_warn(dev, "failed to create async EQ %d\n", err); 544 goto err1; 545 } 546 547 err = mlx5_create_map_eq(dev, &table->pages_eq, 548 MLX5_EQ_VEC_PAGES, 549 /* TODO: sriov max_vf + */ 1, 550 1 << MLX5_EVENT_TYPE_PAGE_REQUEST, "mlx5_pages_eq", 551 &dev->priv.uuari.uars[0]); 552 if (err) { 553 mlx5_core_warn(dev, "failed to create pages EQ %d\n", err); 554 goto err2; 555 } 556 557 return err; 558 559err2: 560 mlx5_destroy_unmap_eq(dev, &table->async_eq); 561 562err1: 563 mlx5_cmd_use_polling(dev); 564 mlx5_destroy_unmap_eq(dev, &table->cmd_eq); 565 return err; 566} 567 568int mlx5_stop_eqs(struct mlx5_core_dev *dev) 569{ 570 struct mlx5_eq_table *table = &dev->priv.eq_table; 571 int err; 572 573 err = mlx5_destroy_unmap_eq(dev, &table->pages_eq); 574 if (err) 575 return err; 576 577 mlx5_destroy_unmap_eq(dev, &table->async_eq); 578 mlx5_cmd_use_polling(dev); 579 580 err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq); 581 if (err) 582 mlx5_cmd_use_events(dev); 583 584 return err; 585} 586 587int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 588 struct mlx5_query_eq_mbox_out *out, int outlen) 589{ 590 struct mlx5_query_eq_mbox_in in; 591 int err; 592 593 memset(&in, 0, sizeof(in)); 594 memset(out, 0, outlen); 595 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_EQ); 596 in.eqn = eq->eqn; 597 err = mlx5_cmd_exec(dev, &in, sizeof(in), out, outlen); 598 if (err) 599 return err; 600 601 if (out->hdr.status) 602 err = mlx5_cmd_status_to_err(&out->hdr); 603 604 return err; 605} 606 607EXPORT_SYMBOL_GPL(mlx5_core_eq_query); 608 609static const char *mlx5_port_module_event_error_type_to_string(u8 error_type) 610{ 611 switch (error_type) { 612 case MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED: 613 return "Power Budget Exceeded"; 614 case MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE: 615 return "Long Range for non MLNX cable/module"; 616 case MLX5_MODULE_EVENT_ERROR_BUS_STUCK: 617 return "Bus stuck(I2C or data shorted)"; 618 case MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT: 619 return "No EEPROM/retry timeout"; 620 case MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST: 621 return "Enforce part number list"; 622 case MLX5_MODULE_EVENT_ERROR_UNSUPPORTED_CABLE: 623 return "Unsupported Cable"; 624 case MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE: 625 return "High Temperature"; 626 case MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED: 627 return "Cable is shorted"; 628 629 default: 630 return "Unknown error type"; 631 } 632} 633 634unsigned int mlx5_query_module_status(struct mlx5_core_dev *dev, int module_num) 635{ 636 if (module_num < 0 || module_num >= MLX5_MAX_PORTS) 637 return 0; /* undefined */ 638 return dev->module_status[module_num]; 639} 640 641static void mlx5_port_module_event(struct mlx5_core_dev *dev, 642 struct mlx5_eqe *eqe) 643{ 644 unsigned int module_num; 645 unsigned int module_status; 646 unsigned int error_type; 647 struct mlx5_eqe_port_module_event *module_event_eqe; 648 struct pci_dev *pdev = dev->pdev; 649 650 module_event_eqe = &eqe->data.port_module_event; 651 652 module_num = (unsigned int)module_event_eqe->module; 653 module_status = (unsigned int)module_event_eqe->module_status & 654 PORT_MODULE_EVENT_MODULE_STATUS_MASK; 655 error_type = (unsigned int)module_event_eqe->error_type & 656 PORT_MODULE_EVENT_ERROR_TYPE_MASK; 657 658 switch (module_status) { 659 case MLX5_MODULE_STATUS_PLUGGED_ENABLED: 660 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: plugged and enabled\n", module_num); 661 break; 662 663 case MLX5_MODULE_STATUS_UNPLUGGED: 664 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: unplugged\n", module_num); 665 break; 666 667 case MLX5_MODULE_STATUS_ERROR: 668 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: error, %s\n", module_num, mlx5_port_module_event_error_type_to_string(error_type)); 669 break; 670 671 case MLX5_MODULE_STATUS_PLUGGED_DISABLED: 672 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: plugged but disabled\n", module_num); 673 break; 674 675 default: 676 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, unknown status\n", module_num); 677 } 678 /* store module status */ 679 if (module_num < MLX5_MAX_PORTS) 680 dev->module_status[module_num] = module_status; 681} 682 683static void mlx5_port_general_notification_event(struct mlx5_core_dev *dev, 684 struct mlx5_eqe *eqe) 685{ 686 u8 port = (eqe->data.port.port >> 4) & 0xf; 687 u32 rqn = 0; 688 struct mlx5_eqe_general_notification_event *general_event = NULL; 689 690 switch (eqe->sub_type) { 691 case MLX5_GEN_EVENT_SUBTYPE_DELAY_DROP_TIMEOUT: 692 general_event = &eqe->data.general_notifications; 693 rqn = be32_to_cpu(general_event->rq_user_index_delay_drop) & 694 0xffffff; 695 break; 696 default: 697 mlx5_core_warn(dev, 698 "general event with unrecognized subtype: port %d, sub_type %d\n", 699 port, eqe->sub_type); 700 break; 701 } 702} 703 704