mlx5_core.h revision 365412
10SN/A/*- 22362SN/A * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 30SN/A * 40SN/A * Redistribution and use in source and binary forms, with or without 50SN/A * modification, are permitted provided that the following conditions 60SN/A * are met: 72362SN/A * 1. Redistributions of source code must retain the above copyright 80SN/A * notice, this list of conditions and the following disclaimer. 92362SN/A * 2. Redistributions in binary form must reproduce the above copyright 100SN/A * notice, this list of conditions and the following disclaimer in the 110SN/A * documentation and/or other materials provided with the distribution. 120SN/A * 130SN/A * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 140SN/A * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 150SN/A * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 160SN/A * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 170SN/A * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 180SN/A * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 190SN/A * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 200SN/A * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 212362SN/A * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 222362SN/A * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 232362SN/A * SUCH DAMAGE. 240SN/A * 250SN/A * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_core/mlx5_core.h 365412 2020-09-07 10:50:47Z kib $ 260SN/A */ 270SN/A 280SN/A#ifndef __MLX5_CORE_H__ 290SN/A#define __MLX5_CORE_H__ 300SN/A 310SN/A#include <linux/types.h> 320SN/A#include <linux/kernel.h> 330SN/A#include <linux/sched.h> 340SN/A 350SN/A#include <dev/mlxfw/mlxfw.h> 360SN/A 370SN/A#define DRIVER_NAME "mlx5_core" 380SN/A#ifndef DRIVER_VERSION 390SN/A#define DRIVER_VERSION "3.5.2" 400SN/A#endif 410SN/A#define DRIVER_RELDATE "September 2019" 420SN/A 430SN/Aextern int mlx5_core_debug_mask; 440SN/A 450SN/A#define mlx5_core_dbg(dev, format, ...) \ 460SN/A pr_debug("%s:%s:%d:(pid %d): " format, \ 470SN/A (dev)->priv.name, __func__, __LINE__, curthread->td_proc->p_pid, \ 480SN/A ##__VA_ARGS__) 499529SN/A 500SN/A#define mlx5_core_dbg_mask(dev, mask, format, ...) \ 519529SN/Ado { \ 520SN/A if ((mask) & mlx5_core_debug_mask) \ 530SN/A mlx5_core_dbg(dev, format, ##__VA_ARGS__); \ 540SN/A} while (0) 550SN/A 560SN/A#define mlx5_core_err(_dev, format, ...) \ 570SN/A device_printf((_dev)->pdev->dev.bsddev, "ERR: ""%s:%d:(pid %d): " format, \ 580SN/A __func__, __LINE__, curthread->td_proc->p_pid, \ 590SN/A ##__VA_ARGS__) 600SN/A 610SN/A#define mlx5_core_warn(_dev, format, ...) \ 629529SN/A device_printf((_dev)->pdev->dev.bsddev, "WARN: ""%s:%d:(pid %d): " format, \ 630SN/A __func__, __LINE__, curthread->td_proc->p_pid, \ 649529SN/A ##__VA_ARGS__) 650SN/A 660SN/A#define mlx5_core_info(_dev, format, ...) \ 670SN/A device_printf((_dev)->pdev->dev.bsddev, "INFO: ""%s:%d:(pid %d): " format, \ 680SN/A __func__, __LINE__, curthread->td_proc->p_pid, \ 690SN/A ##__VA_ARGS__) 700SN/A 710SN/Aenum { 720SN/A MLX5_CMD_DATA, /* print command payload only */ 730SN/A MLX5_CMD_TIME, /* print command execution time */ 740SN/A}; 750SN/A 760SN/Aenum mlx5_semaphore_space_address { 770SN/A MLX5_SEMAPHORE_SW_RESET = 0x20, 780SN/A}; 790SN/A 800SN/Astruct mlx5_core_dev; 810SN/A 820SN/Aenum mlx5_pddr_page_select { 830SN/A MLX5_PDDR_OPERATIONAL_INFO_PAGE = 0x0, 840SN/A MLX5_PDDR_TROUBLESHOOTING_INFO_PAGE = 0x1, 850SN/A MLX5_PDDR_MODULE_INFO_PAGE = 0x3, 860SN/A}; 870SN/A 880SN/Aenum mlx5_pddr_monitor_opcodes { 890SN/A MLX5_LINK_NO_ISSUE_OBSERVED = 0x0, 900SN/A MLX5_LINK_PORT_CLOSED = 0x1, 910SN/A MLX5_LINK_AN_FAILURE = 0x2, 920SN/A MLX5_LINK_TRAINING_FAILURE = 0x5, 930SN/A MLX5_LINK_LOGICAL_MISMATCH = 0x9, 940SN/A MLX5_LINK_REMOTE_FAULT_INDICATION = 0xe, 950SN/A MLX5_LINK_BAD_SIGNAL_INTEGRITY = 0xf, 960SN/A MLX5_LINK_CABLE_COMPLIANCE_CODE_MISMATCH = 0x10, 970SN/A MLX5_LINK_INTERNAL_ERR = 0x17, 980SN/A MLX5_LINK_INFO_NOT_AVAIL = 0x3ff, 990SN/A MLX5_LINK_CABLE_UNPLUGGED = 0x400, 1000SN/A MLX5_LINK_LONG_RANGE_FOR_NON_MLX_CABLE = 0x401, 1010SN/A MLX5_LINK_BUS_STUCK = 0x402, 1020SN/A MLX5_LINK_UNSUPP_EEPROM = 0x403, 1030SN/A MLX5_LINK_PART_NUM_LIST = 0x404, 1040SN/A MLX5_LINK_UNSUPP_CABLE = 0x405, 1050SN/A MLX5_LINK_MODULE_TEMP_SHUTDOWN = 0x406, 1060SN/A MLX5_LINK_SHORTED_CABLE = 0x407, 1070SN/A MLX5_LINK_POWER_BUDGET_EXCEEDED = 0x408, 1080SN/A MLX5_LINK_MNG_FORCED_DOWN = 0x409, 1090SN/A}; 1100SN/A 1110SN/Aint mlx5_query_hca_caps(struct mlx5_core_dev *dev); 1120SN/Aint mlx5_query_board_id(struct mlx5_core_dev *dev); 1130SN/Aint mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam, 1140SN/A u8 feature_group, u8 access_reg_group); 1150SN/Aint mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, 1160SN/A u8 feature_group, u8 access_reg_group); 1170SN/Aint mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcap, 1180SN/A u8 feature_group, u8 access_reg_group); 1190SN/Aint mlx5_query_mfrl_reg(struct mlx5_core_dev *mdev, u8 *reset_level); 1200SN/Aint mlx5_set_mfrl_reg(struct mlx5_core_dev *mdev, u8 reset_level); 1210SN/Aint mlx5_cmd_init_hca(struct mlx5_core_dev *dev); 1220SN/Aint mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev); 1230SN/Aint mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev); 1240SN/Aint mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev); 1250SN/Avoid mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event, 1260SN/A unsigned long param); 1270SN/Avoid mlx5_enter_error_state(struct mlx5_core_dev *dev, bool force); 1280SN/Avoid mlx5_disable_device(struct mlx5_core_dev *dev); 1290SN/Avoid mlx5_recover_device(struct mlx5_core_dev *dev); 1300SN/Aint mlx5_query_pddr_troubleshooting_info(struct mlx5_core_dev *mdev, 1310SN/A u16 *monitor_opcode, 1320SN/A u8 *status_message, size_t sm_len); 1330SN/A 1340SN/Aint mlx5_register_device(struct mlx5_core_dev *dev); 1350SN/Avoid mlx5_unregister_device(struct mlx5_core_dev *dev); 1360SN/A 1370SN/Aint mlx5_firmware_flash(struct mlx5_core_dev *dev, const struct firmware *fw); 1380SN/A 1390SN/Avoid mlx5e_init(void); 1400SN/Avoid mlx5e_cleanup(void); 1410SN/A 1420SN/Aint mlx5_ctl_init(void); 1430SN/Avoid mlx5_ctl_fini(void); 1440SN/Avoid mlx5_fwdump_prep(struct mlx5_core_dev *mdev); 1450SN/Aint mlx5_fwdump(struct mlx5_core_dev *mdev); 1460SN/Avoid mlx5_fwdump_clean(struct mlx5_core_dev *mdev); 1470SN/A 1480SN/Astruct mlx5_crspace_regmap { 1490SN/A uint32_t addr; 1500SN/A unsigned cnt; 1510SN/A}; 1520SN/A 1530SN/Aextern struct pci_driver mlx5_core_driver; 1540SN/A 1550SN/ASYSCTL_DECL(_hw_mlx5); 1560SN/A 1570SN/Aenum { 1580SN/A MLX5_NIC_IFC_FULL = 0, 1590SN/A MLX5_NIC_IFC_DISABLED = 1, 1600SN/A MLX5_NIC_IFC_NO_DRAM_NIC = 2, 1610SN/A MLX5_NIC_IFC_INVALID = 3, 1620SN/A MLX5_NIC_IFC_SW_RESET = 7, 1630SN/A}; 1640SN/A 1650SN/Au8 mlx5_get_nic_state(struct mlx5_core_dev *dev); 1660SN/Avoid mlx5_set_nic_state(struct mlx5_core_dev *dev, u8 state); 1670SN/A 1680SN/A#endif /* __MLX5_CORE_H__ */ 1690SN/A