driver.h revision 353206
1/*- 2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: stable/11/sys/dev/mlx5/driver.h 353206 2019-10-07 09:01:59Z hselasky $ 26 */ 27 28#ifndef MLX5_DRIVER_H 29#define MLX5_DRIVER_H 30 31#include <linux/kernel.h> 32#include <linux/completion.h> 33#include <linux/pci.h> 34#include <linux/cache.h> 35#include <linux/rbtree.h> 36#include <linux/if_ether.h> 37#include <linux/semaphore.h> 38#include <linux/slab.h> 39#include <linux/vmalloc.h> 40#include <linux/radix-tree.h> 41#include <linux/idr.h> 42 43#include <dev/mlx5/device.h> 44#include <dev/mlx5/doorbell.h> 45#include <dev/mlx5/srq.h> 46 47#define MLX5_QCOUNTER_SETS_NETDEV 64 48#define MLX5_MAX_NUMBER_OF_VFS 128 49 50enum { 51 MLX5_BOARD_ID_LEN = 64, 52 MLX5_MAX_NAME_LEN = 16, 53}; 54 55enum { 56 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, 57}; 58 59enum { 60 CMD_OWNER_SW = 0x0, 61 CMD_OWNER_HW = 0x1, 62 CMD_STATUS_SUCCESS = 0, 63}; 64 65enum mlx5_sqp_t { 66 MLX5_SQP_SMI = 0, 67 MLX5_SQP_GSI = 1, 68 MLX5_SQP_IEEE_1588 = 2, 69 MLX5_SQP_SNIFFER = 3, 70 MLX5_SQP_SYNC_UMR = 4, 71}; 72 73enum { 74 MLX5_MAX_PORTS = 2, 75}; 76 77enum { 78 MLX5_EQ_VEC_PAGES = 0, 79 MLX5_EQ_VEC_CMD = 1, 80 MLX5_EQ_VEC_ASYNC = 2, 81 MLX5_EQ_VEC_COMP_BASE, 82}; 83 84enum { 85 MLX5_ATOMIC_MODE_OFF = 16, 86 MLX5_ATOMIC_MODE_NONE = 0 << MLX5_ATOMIC_MODE_OFF, 87 MLX5_ATOMIC_MODE_IB_COMP = 1 << MLX5_ATOMIC_MODE_OFF, 88 MLX5_ATOMIC_MODE_CX = 2 << MLX5_ATOMIC_MODE_OFF, 89 MLX5_ATOMIC_MODE_8B = 3 << MLX5_ATOMIC_MODE_OFF, 90 MLX5_ATOMIC_MODE_16B = 4 << MLX5_ATOMIC_MODE_OFF, 91 MLX5_ATOMIC_MODE_32B = 5 << MLX5_ATOMIC_MODE_OFF, 92 MLX5_ATOMIC_MODE_64B = 6 << MLX5_ATOMIC_MODE_OFF, 93 MLX5_ATOMIC_MODE_128B = 7 << MLX5_ATOMIC_MODE_OFF, 94 MLX5_ATOMIC_MODE_256B = 8 << MLX5_ATOMIC_MODE_OFF, 95}; 96 97enum { 98 MLX5_ATOMIC_MODE_DCT_OFF = 20, 99 MLX5_ATOMIC_MODE_DCT_NONE = 0 << MLX5_ATOMIC_MODE_DCT_OFF, 100 MLX5_ATOMIC_MODE_DCT_IB_COMP = 1 << MLX5_ATOMIC_MODE_DCT_OFF, 101 MLX5_ATOMIC_MODE_DCT_CX = 2 << MLX5_ATOMIC_MODE_DCT_OFF, 102 MLX5_ATOMIC_MODE_DCT_8B = 3 << MLX5_ATOMIC_MODE_DCT_OFF, 103 MLX5_ATOMIC_MODE_DCT_16B = 4 << MLX5_ATOMIC_MODE_DCT_OFF, 104 MLX5_ATOMIC_MODE_DCT_32B = 5 << MLX5_ATOMIC_MODE_DCT_OFF, 105 MLX5_ATOMIC_MODE_DCT_64B = 6 << MLX5_ATOMIC_MODE_DCT_OFF, 106 MLX5_ATOMIC_MODE_DCT_128B = 7 << MLX5_ATOMIC_MODE_DCT_OFF, 107 MLX5_ATOMIC_MODE_DCT_256B = 8 << MLX5_ATOMIC_MODE_DCT_OFF, 108}; 109 110enum { 111 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, 112 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, 113 MLX5_ATOMIC_OPS_MASKED_CMP_SWAP = 1 << 2, 114 MLX5_ATOMIC_OPS_MASKED_FETCH_ADD = 1 << 3, 115}; 116 117enum { 118 MLX5_REG_QPTS = 0x4002, 119 MLX5_REG_QETCR = 0x4005, 120 MLX5_REG_QPDP = 0x4007, 121 MLX5_REG_QTCT = 0x400A, 122 MLX5_REG_QPDPM = 0x4013, 123 MLX5_REG_QHLL = 0x4016, 124 MLX5_REG_QCAM = 0x4019, 125 MLX5_REG_DCBX_PARAM = 0x4020, 126 MLX5_REG_DCBX_APP = 0x4021, 127 MLX5_REG_PCAP = 0x5001, 128 MLX5_REG_FPGA_CAP = 0x4022, 129 MLX5_REG_FPGA_CTRL = 0x4023, 130 MLX5_REG_FPGA_ACCESS_REG = 0x4024, 131 MLX5_REG_FPGA_SHELL_CNTR = 0x4025, 132 MLX5_REG_PMTU = 0x5003, 133 MLX5_REG_PTYS = 0x5004, 134 MLX5_REG_PAOS = 0x5006, 135 MLX5_REG_PFCC = 0x5007, 136 MLX5_REG_PPCNT = 0x5008, 137 MLX5_REG_PMAOS = 0x5012, 138 MLX5_REG_PUDE = 0x5009, 139 MLX5_REG_PPTB = 0x500B, 140 MLX5_REG_PBMC = 0x500C, 141 MLX5_REG_PMPE = 0x5010, 142 MLX5_REG_PELC = 0x500e, 143 MLX5_REG_PVLC = 0x500f, 144 MLX5_REG_PMLP = 0x5002, 145 MLX5_REG_PCAM = 0x507f, 146 MLX5_REG_NODE_DESC = 0x6001, 147 MLX5_REG_HOST_ENDIANNESS = 0x7004, 148 MLX5_REG_MTMP = 0x900a, 149 MLX5_REG_MCIA = 0x9014, 150 MLX5_REG_MFRL = 0x9028, 151 MLX5_REG_MPCNT = 0x9051, 152 MLX5_REG_MCQI = 0x9061, 153 MLX5_REG_MCC = 0x9062, 154 MLX5_REG_MCDA = 0x9063, 155 MLX5_REG_MCAM = 0x907f, 156}; 157 158enum dbg_rsc_type { 159 MLX5_DBG_RSC_QP, 160 MLX5_DBG_RSC_EQ, 161 MLX5_DBG_RSC_CQ, 162}; 163 164enum { 165 MLX5_INTERFACE_PROTOCOL_IB = 0, 166 MLX5_INTERFACE_PROTOCOL_ETH = 1, 167 MLX5_INTERFACE_NUMBER = 2, 168}; 169 170struct mlx5_field_desc { 171 struct dentry *dent; 172 int i; 173}; 174 175struct mlx5_rsc_debug { 176 struct mlx5_core_dev *dev; 177 void *object; 178 enum dbg_rsc_type type; 179 struct dentry *root; 180 struct mlx5_field_desc fields[0]; 181}; 182 183enum mlx5_dev_event { 184 MLX5_DEV_EVENT_SYS_ERROR, 185 MLX5_DEV_EVENT_PORT_UP, 186 MLX5_DEV_EVENT_PORT_DOWN, 187 MLX5_DEV_EVENT_PORT_INITIALIZED, 188 MLX5_DEV_EVENT_LID_CHANGE, 189 MLX5_DEV_EVENT_PKEY_CHANGE, 190 MLX5_DEV_EVENT_GUID_CHANGE, 191 MLX5_DEV_EVENT_CLIENT_REREG, 192 MLX5_DEV_EVENT_VPORT_CHANGE, 193 MLX5_DEV_EVENT_ERROR_STATE_DCBX, 194 MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE, 195 MLX5_DEV_EVENT_LOCAL_OPER_CHANGE, 196 MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE, 197}; 198 199enum mlx5_port_status { 200 MLX5_PORT_UP = 1 << 0, 201 MLX5_PORT_DOWN = 1 << 1, 202}; 203 204enum { 205 MLX5_VSC_SPACE_SUPPORTED = 0x1, 206 MLX5_VSC_SPACE_OFFSET = 0x4, 207 MLX5_VSC_COUNTER_OFFSET = 0x8, 208 MLX5_VSC_SEMA_OFFSET = 0xC, 209 MLX5_VSC_ADDR_OFFSET = 0x10, 210 MLX5_VSC_DATA_OFFSET = 0x14, 211 MLX5_VSC_MAX_RETRIES = 0x1000, 212}; 213 214#define MLX5_PROT_MASK(link_mode) (1 << link_mode) 215 216struct mlx5_uuar_info { 217 struct mlx5_uar *uars; 218 int num_uars; 219 int num_low_latency_uuars; 220 unsigned long *bitmap; 221 unsigned int *count; 222 struct mlx5_bf *bfs; 223 224 /* 225 * protect uuar allocation data structs 226 */ 227 struct mutex lock; 228 u32 ver; 229}; 230 231struct mlx5_bf { 232 void __iomem *reg; 233 void __iomem *regreg; 234 int buf_size; 235 struct mlx5_uar *uar; 236 unsigned long offset; 237 int need_lock; 238 /* protect blue flame buffer selection when needed 239 */ 240 spinlock_t lock; 241 242 /* serialize 64 bit writes when done as two 32 bit accesses 243 */ 244 spinlock_t lock32; 245 int uuarn; 246}; 247 248struct mlx5_cmd_first { 249 __be32 data[4]; 250}; 251 252struct cache_ent; 253struct mlx5_fw_page { 254 union { 255 struct rb_node rb_node; 256 struct list_head list; 257 }; 258 struct mlx5_cmd_first first; 259 struct mlx5_core_dev *dev; 260 bus_dmamap_t dma_map; 261 bus_addr_t dma_addr; 262 void *virt_addr; 263 struct cache_ent *cache; 264 u32 numpages; 265 u16 load_done; 266#define MLX5_LOAD_ST_NONE 0 267#define MLX5_LOAD_ST_SUCCESS 1 268#define MLX5_LOAD_ST_FAILURE 2 269 u16 func_id; 270}; 271#define mlx5_cmd_msg mlx5_fw_page 272 273struct mlx5_cmd_debug { 274 struct dentry *dbg_root; 275 struct dentry *dbg_in; 276 struct dentry *dbg_out; 277 struct dentry *dbg_outlen; 278 struct dentry *dbg_status; 279 struct dentry *dbg_run; 280 void *in_msg; 281 void *out_msg; 282 u8 status; 283 u16 inlen; 284 u16 outlen; 285}; 286 287struct cache_ent { 288 /* protect block chain allocations 289 */ 290 spinlock_t lock; 291 struct list_head head; 292}; 293 294struct cmd_msg_cache { 295 struct cache_ent large; 296 struct cache_ent med; 297 298}; 299 300struct mlx5_traffic_counter { 301 u64 packets; 302 u64 octets; 303}; 304 305enum mlx5_cmd_mode { 306 MLX5_CMD_MODE_POLLING, 307 MLX5_CMD_MODE_EVENTS 308}; 309 310struct mlx5_cmd_stats { 311 u64 sum; 312 u64 n; 313 struct dentry *root; 314 struct dentry *avg; 315 struct dentry *count; 316 /* protect command average calculations */ 317 spinlock_t lock; 318}; 319 320struct mlx5_cmd { 321 struct mlx5_fw_page *cmd_page; 322 bus_dma_tag_t dma_tag; 323 struct sx dma_sx; 324 struct mtx dma_mtx; 325#define MLX5_DMA_OWNED(dev) mtx_owned(&(dev)->cmd.dma_mtx) 326#define MLX5_DMA_LOCK(dev) mtx_lock(&(dev)->cmd.dma_mtx) 327#define MLX5_DMA_UNLOCK(dev) mtx_unlock(&(dev)->cmd.dma_mtx) 328 struct cv dma_cv; 329#define MLX5_DMA_DONE(dev) cv_broadcast(&(dev)->cmd.dma_cv) 330#define MLX5_DMA_WAIT(dev) cv_wait(&(dev)->cmd.dma_cv, &(dev)->cmd.dma_mtx) 331 void *cmd_buf; 332 dma_addr_t dma; 333 u16 cmdif_rev; 334 u8 log_sz; 335 u8 log_stride; 336 int max_reg_cmds; 337 int events; 338 u32 __iomem *vector; 339 340 /* protect command queue allocations 341 */ 342 spinlock_t alloc_lock; 343 344 /* protect token allocations 345 */ 346 spinlock_t token_lock; 347 u8 token; 348 unsigned long bitmask; 349 struct semaphore sem; 350 struct semaphore pages_sem; 351 enum mlx5_cmd_mode mode; 352 struct mlx5_cmd_work_ent * volatile ent_arr[MLX5_MAX_COMMANDS]; 353 volatile enum mlx5_cmd_mode ent_mode[MLX5_MAX_COMMANDS]; 354 struct mlx5_cmd_debug dbg; 355 struct cmd_msg_cache cache; 356 int checksum_disabled; 357 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; 358}; 359 360struct mlx5_port_caps { 361 int gid_table_len; 362 int pkey_table_len; 363 u8 ext_port_cap; 364}; 365 366struct mlx5_buf { 367 bus_dma_tag_t dma_tag; 368 bus_dmamap_t dma_map; 369 struct mlx5_core_dev *dev; 370 struct { 371 void *buf; 372 } direct; 373 u64 *page_list; 374 int npages; 375 int size; 376 u8 page_shift; 377 u8 load_done; 378}; 379 380struct mlx5_frag_buf { 381 struct mlx5_buf_list *frags; 382 int npages; 383 int size; 384 u8 page_shift; 385}; 386 387struct mlx5_eq { 388 struct mlx5_core_dev *dev; 389 __be32 __iomem *doorbell; 390 u32 cons_index; 391 struct mlx5_buf buf; 392 int size; 393 u8 irqn; 394 u8 eqn; 395 int nent; 396 u64 mask; 397 struct list_head list; 398 int index; 399 struct mlx5_rsc_debug *dbg; 400}; 401 402struct mlx5_core_psv { 403 u32 psv_idx; 404 struct psv_layout { 405 u32 pd; 406 u16 syndrome; 407 u16 reserved; 408 u16 bg; 409 u16 app_tag; 410 u32 ref_tag; 411 } psv; 412}; 413 414struct mlx5_core_sig_ctx { 415 struct mlx5_core_psv psv_memory; 416 struct mlx5_core_psv psv_wire; 417#if (__FreeBSD_version >= 1100000) 418 struct ib_sig_err err_item; 419#endif 420 bool sig_status_checked; 421 bool sig_err_exists; 422 u32 sigerr_count; 423}; 424 425enum { 426 MLX5_MKEY_MR = 1, 427 MLX5_MKEY_MW, 428 MLX5_MKEY_MR_USER, 429}; 430 431struct mlx5_core_mkey { 432 u64 iova; 433 u64 size; 434 u32 key; 435 u32 pd; 436 u32 type; 437}; 438 439struct mlx5_core_mr { 440 u64 iova; 441 u64 size; 442 u32 key; 443 u32 pd; 444}; 445 446enum mlx5_res_type { 447 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, 448 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, 449 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, 450 MLX5_RES_SRQ = 3, 451 MLX5_RES_XSRQ = 4, 452 MLX5_RES_DCT = 5, 453}; 454 455struct mlx5_core_rsc_common { 456 enum mlx5_res_type res; 457 atomic_t refcount; 458 struct completion free; 459}; 460 461struct mlx5_core_srq { 462 struct mlx5_core_rsc_common common; /* must be first */ 463 u32 srqn; 464 int max; 465 size_t max_gs; 466 size_t max_avail_gather; 467 int wqe_shift; 468 void (*event)(struct mlx5_core_srq *, int); 469 atomic_t refcount; 470 struct completion free; 471}; 472 473struct mlx5_eq_table { 474 void __iomem *update_ci; 475 void __iomem *update_arm_ci; 476 struct list_head comp_eqs_list; 477 struct mlx5_eq pages_eq; 478 struct mlx5_eq async_eq; 479 struct mlx5_eq cmd_eq; 480 int num_comp_vectors; 481 /* protect EQs list 482 */ 483 spinlock_t lock; 484}; 485 486struct mlx5_uar { 487 u32 index; 488 void __iomem *bf_map; 489 void __iomem *map; 490}; 491 492 493struct mlx5_core_health { 494 struct mlx5_health_buffer __iomem *health; 495 __be32 __iomem *health_counter; 496 struct timer_list timer; 497 u32 prev; 498 int miss_counter; 499 u32 fatal_error; 500 struct workqueue_struct *wq_watchdog; 501 struct work_struct work_watchdog; 502 /* wq spinlock to synchronize draining */ 503 spinlock_t wq_lock; 504 struct workqueue_struct *wq; 505 unsigned long flags; 506 struct work_struct work; 507 struct delayed_work recover_work; 508 unsigned int last_reset_req; 509 struct work_struct work_cmd_completion; 510 struct workqueue_struct *wq_cmd; 511}; 512 513#define MLX5_CQ_LINEAR_ARRAY_SIZE 1024 514 515struct mlx5_cq_linear_array_entry { 516 spinlock_t lock; 517 struct mlx5_core_cq * volatile cq; 518}; 519 520struct mlx5_cq_table { 521 /* protect radix tree 522 */ 523 spinlock_t lock; 524 struct radix_tree_root tree; 525 struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE]; 526}; 527 528struct mlx5_qp_table { 529 /* protect radix tree 530 */ 531 spinlock_t lock; 532 struct radix_tree_root tree; 533}; 534 535struct mlx5_srq_table { 536 /* protect radix tree 537 */ 538 spinlock_t lock; 539 struct radix_tree_root tree; 540}; 541 542struct mlx5_mr_table { 543 /* protect radix tree 544 */ 545 spinlock_t lock; 546 struct radix_tree_root tree; 547}; 548 549struct mlx5_pme_stats { 550 u64 status_counters[MLX5_MODULE_STATUS_NUM]; 551 u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM]; 552}; 553 554struct mlx5_priv { 555 char name[MLX5_MAX_NAME_LEN]; 556 struct mlx5_eq_table eq_table; 557 struct msix_entry *msix_arr; 558 struct mlx5_uuar_info uuari; 559 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock); 560 int disable_irqs; 561 562 struct io_mapping *bf_mapping; 563 564 /* pages stuff */ 565 struct workqueue_struct *pg_wq; 566 struct rb_root page_root; 567 s64 fw_pages; 568 atomic_t reg_pages; 569 s64 pages_per_func[MLX5_MAX_NUMBER_OF_VFS]; 570 struct mlx5_core_health health; 571 572 struct mlx5_srq_table srq_table; 573 574 /* start: qp staff */ 575 struct mlx5_qp_table qp_table; 576 struct dentry *qp_debugfs; 577 struct dentry *eq_debugfs; 578 struct dentry *cq_debugfs; 579 struct dentry *cmdif_debugfs; 580 /* end: qp staff */ 581 582 /* start: cq staff */ 583 struct mlx5_cq_table cq_table; 584 /* end: cq staff */ 585 586 /* start: mr staff */ 587 struct mlx5_mr_table mr_table; 588 /* end: mr staff */ 589 590 /* start: alloc staff */ 591 int numa_node; 592 593 struct mutex pgdir_mutex; 594 struct list_head pgdir_list; 595 /* end: alloc staff */ 596 struct dentry *dbg_root; 597 598 /* protect mkey key part */ 599 spinlock_t mkey_lock; 600 u8 mkey_key; 601 602 struct list_head dev_list; 603 struct list_head ctx_list; 604 spinlock_t ctx_lock; 605 unsigned long pci_dev_data; 606 struct mlx5_pme_stats pme_stats; 607}; 608 609enum mlx5_device_state { 610 MLX5_DEVICE_STATE_UP, 611 MLX5_DEVICE_STATE_INTERNAL_ERROR, 612}; 613 614enum mlx5_interface_state { 615 MLX5_INTERFACE_STATE_UP, 616}; 617 618enum mlx5_pci_status { 619 MLX5_PCI_STATUS_DISABLED, 620 MLX5_PCI_STATUS_ENABLED, 621}; 622 623#define MLX5_MAX_RESERVED_GIDS 8 624 625struct mlx5_rsvd_gids { 626 unsigned int start; 627 unsigned int count; 628 struct ida ida; 629}; 630 631struct mlx5_special_contexts { 632 int resd_lkey; 633}; 634 635struct mlx5_flow_root_namespace; 636struct mlx5_core_dev { 637 struct pci_dev *pdev; 638 /* sync pci state */ 639 struct mutex pci_status_mutex; 640 enum mlx5_pci_status pci_status; 641 char board_id[MLX5_BOARD_ID_LEN]; 642 struct mlx5_cmd cmd; 643 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 644 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 645 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 646 struct { 647 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; 648 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)]; 649 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; 650 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; 651 } caps; 652 phys_addr_t iseg_base; 653 struct mlx5_init_seg __iomem *iseg; 654 enum mlx5_device_state state; 655 /* sync interface state */ 656 struct mutex intf_state_mutex; 657 unsigned long intf_state; 658 void (*event) (struct mlx5_core_dev *dev, 659 enum mlx5_dev_event event, 660 unsigned long param); 661 struct mlx5_priv priv; 662 struct mlx5_profile *profile; 663 atomic_t num_qps; 664 u32 vsc_addr; 665 u32 issi; 666 struct mlx5_special_contexts special_contexts; 667 unsigned int module_status[MLX5_MAX_PORTS]; 668 struct mlx5_flow_root_namespace *root_ns; 669 struct mlx5_flow_root_namespace *fdb_root_ns; 670 struct mlx5_flow_root_namespace *esw_egress_root_ns; 671 struct mlx5_flow_root_namespace *esw_ingress_root_ns; 672 struct mlx5_flow_root_namespace *sniffer_rx_root_ns; 673 struct mlx5_flow_root_namespace *sniffer_tx_root_ns; 674 u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER]; 675 const struct mlx5_crspace_regmap *dump_rege; 676 uint32_t *dump_data; 677 unsigned dump_size; 678 bool dump_valid; 679 bool dump_copyout; 680 struct mtx dump_lock; 681 682 struct sysctl_ctx_list sysctl_ctx; 683 int msix_eqvec; 684 int pwr_status; 685 int pwr_value; 686 687 struct { 688 struct mlx5_rsvd_gids reserved_gids; 689 atomic_t roce_en; 690 } roce; 691 692 struct { 693 spinlock_t spinlock; 694#define MLX5_MPFS_TABLE_MAX 32 695 long bitmap[BITS_TO_LONGS(MLX5_MPFS_TABLE_MAX)]; 696 } mpfs; 697#ifdef CONFIG_MLX5_FPGA 698 struct mlx5_fpga_device *fpga; 699#endif 700}; 701 702enum { 703 MLX5_WOL_DISABLE = 0, 704 MLX5_WOL_SECURED_MAGIC = 1 << 1, 705 MLX5_WOL_MAGIC = 1 << 2, 706 MLX5_WOL_ARP = 1 << 3, 707 MLX5_WOL_BROADCAST = 1 << 4, 708 MLX5_WOL_MULTICAST = 1 << 5, 709 MLX5_WOL_UNICAST = 1 << 6, 710 MLX5_WOL_PHY_ACTIVITY = 1 << 7, 711}; 712 713struct mlx5_db { 714 __be32 *db; 715 union { 716 struct mlx5_db_pgdir *pgdir; 717 struct mlx5_ib_user_db_page *user_page; 718 } u; 719 dma_addr_t dma; 720 int index; 721}; 722 723struct mlx5_net_counters { 724 u64 packets; 725 u64 octets; 726}; 727 728struct mlx5_ptys_reg { 729 u8 an_dis_admin; 730 u8 an_dis_ap; 731 u8 local_port; 732 u8 proto_mask; 733 u32 eth_proto_cap; 734 u16 ib_link_width_cap; 735 u16 ib_proto_cap; 736 u32 eth_proto_admin; 737 u16 ib_link_width_admin; 738 u16 ib_proto_admin; 739 u32 eth_proto_oper; 740 u16 ib_link_width_oper; 741 u16 ib_proto_oper; 742 u32 eth_proto_lp_advertise; 743}; 744 745struct mlx5_pvlc_reg { 746 u8 local_port; 747 u8 vl_hw_cap; 748 u8 vl_admin; 749 u8 vl_operational; 750}; 751 752struct mlx5_pmtu_reg { 753 u8 local_port; 754 u16 max_mtu; 755 u16 admin_mtu; 756 u16 oper_mtu; 757}; 758 759struct mlx5_vport_counters { 760 struct mlx5_net_counters received_errors; 761 struct mlx5_net_counters transmit_errors; 762 struct mlx5_net_counters received_ib_unicast; 763 struct mlx5_net_counters transmitted_ib_unicast; 764 struct mlx5_net_counters received_ib_multicast; 765 struct mlx5_net_counters transmitted_ib_multicast; 766 struct mlx5_net_counters received_eth_broadcast; 767 struct mlx5_net_counters transmitted_eth_broadcast; 768 struct mlx5_net_counters received_eth_unicast; 769 struct mlx5_net_counters transmitted_eth_unicast; 770 struct mlx5_net_counters received_eth_multicast; 771 struct mlx5_net_counters transmitted_eth_multicast; 772}; 773 774enum { 775 MLX5_DB_PER_PAGE = MLX5_ADAPTER_PAGE_SIZE / L1_CACHE_BYTES, 776}; 777 778struct mlx5_core_dct { 779 struct mlx5_core_rsc_common common; /* must be first */ 780 void (*event)(struct mlx5_core_dct *, int); 781 int dctn; 782 struct completion drained; 783 struct mlx5_rsc_debug *dbg; 784 int pid; 785}; 786 787enum { 788 MLX5_COMP_EQ_SIZE = 1024, 789}; 790 791enum { 792 MLX5_PTYS_IB = 1 << 0, 793 MLX5_PTYS_EN = 1 << 2, 794}; 795 796struct mlx5_db_pgdir { 797 struct list_head list; 798 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE); 799 struct mlx5_fw_page *fw_page; 800 __be32 *db_page; 801 dma_addr_t db_dma; 802}; 803 804typedef void (*mlx5_cmd_cbk_t)(int status, void *context); 805 806struct mlx5_cmd_work_ent { 807 struct mlx5_cmd_msg *in; 808 struct mlx5_cmd_msg *out; 809 int uin_size; 810 void *uout; 811 int uout_size; 812 mlx5_cmd_cbk_t callback; 813 struct delayed_work cb_timeout_work; 814 void *context; 815 int idx; 816 struct completion done; 817 struct mlx5_cmd *cmd; 818 struct work_struct work; 819 struct mlx5_cmd_layout *lay; 820 int ret; 821 int page_queue; 822 u8 status; 823 u8 token; 824 u64 ts1; 825 u64 ts2; 826 u16 op; 827 u8 busy; 828 bool polling; 829}; 830 831struct mlx5_pas { 832 u64 pa; 833 u8 log_sz; 834}; 835 836enum port_state_policy { 837 MLX5_POLICY_DOWN = 0, 838 MLX5_POLICY_UP = 1, 839 MLX5_POLICY_FOLLOW = 2, 840 MLX5_POLICY_INVALID = 0xffffffff 841}; 842 843static inline void * 844mlx5_buf_offset(struct mlx5_buf *buf, int offset) 845{ 846 return ((char *)buf->direct.buf + offset); 847} 848 849 850extern struct workqueue_struct *mlx5_core_wq; 851 852#define STRUCT_FIELD(header, field) \ 853 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ 854 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 855 856static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) 857{ 858 return pci_get_drvdata(pdev); 859} 860 861extern struct dentry *mlx5_debugfs_root; 862 863static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) 864{ 865 return ioread32be(&dev->iseg->fw_rev) & 0xffff; 866} 867 868static inline u16 fw_rev_min(struct mlx5_core_dev *dev) 869{ 870 return ioread32be(&dev->iseg->fw_rev) >> 16; 871} 872 873static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) 874{ 875 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; 876} 877 878static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev) 879{ 880 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 881} 882 883static inline int mlx5_get_gid_table_len(u16 param) 884{ 885 if (param > 4) { 886 printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n"); 887 return 0; 888 } 889 890 return 8 * (1 << param); 891} 892 893static inline void *mlx5_vzalloc(unsigned long size) 894{ 895 void *rtn; 896 897 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); 898 return rtn; 899} 900 901static inline void *mlx5_vmalloc(unsigned long size) 902{ 903 void *rtn; 904 905 rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN); 906 if (!rtn) 907 rtn = vmalloc(size); 908 return rtn; 909} 910 911static inline u32 mlx5_base_mkey(const u32 key) 912{ 913 return key & 0xffffff00u; 914} 915 916int mlx5_cmd_init(struct mlx5_core_dev *dev); 917void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 918void mlx5_cmd_use_events(struct mlx5_core_dev *dev); 919void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 920void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); 921int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); 922int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 923 int out_size); 924int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, 925 void *out, int out_size, mlx5_cmd_cbk_t callback, 926 void *context); 927int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, 928 void *out, int out_size); 929int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 930int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 931int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 932int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 933int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 934void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 935void mlx5_health_cleanup(struct mlx5_core_dev *dev); 936int mlx5_health_init(struct mlx5_core_dev *dev); 937void mlx5_start_health_poll(struct mlx5_core_dev *dev); 938void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health); 939void mlx5_drain_health_wq(struct mlx5_core_dev *dev); 940void mlx5_drain_health_recovery(struct mlx5_core_dev *dev); 941void mlx5_trigger_health_work(struct mlx5_core_dev *dev); 942void mlx5_trigger_health_watchdog(struct mlx5_core_dev *dev); 943 944#define mlx5_buf_alloc_node(dev, size, direct, buf, node) \ 945 mlx5_buf_alloc(dev, size, direct, buf) 946int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct, 947 struct mlx5_buf *buf); 948void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); 949int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 950 struct mlx5_srq_attr *in); 951int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); 952int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 953 struct mlx5_srq_attr *out); 954int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 955int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 956 u16 lwm, int is_srq); 957void mlx5_init_mr_table(struct mlx5_core_dev *dev); 958void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev); 959int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, 960 struct mlx5_core_mr *mkey, 961 u32 *in, int inlen, 962 u32 *out, int outlen, 963 mlx5_cmd_cbk_t callback, void *context); 964int mlx5_core_create_mkey(struct mlx5_core_dev *dev, 965 struct mlx5_core_mr *mr, 966 u32 *in, int inlen); 967int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey); 968int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey, 969 u32 *out, int outlen); 970int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 971 u32 *mkey); 972int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); 973int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); 974int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, 975 u16 opmod, u8 port); 976void mlx5_fwp_flush(struct mlx5_fw_page *fwp); 977void mlx5_fwp_invalidate(struct mlx5_fw_page *fwp); 978struct mlx5_fw_page *mlx5_fwp_alloc(struct mlx5_core_dev *dev, gfp_t flags, unsigned num); 979void mlx5_fwp_free(struct mlx5_fw_page *fwp); 980u64 mlx5_fwp_get_dma(struct mlx5_fw_page *fwp, size_t offset); 981void *mlx5_fwp_get_virt(struct mlx5_fw_page *fwp, size_t offset); 982void mlx5_pagealloc_init(struct mlx5_core_dev *dev); 983void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 984int mlx5_pagealloc_start(struct mlx5_core_dev *dev); 985void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 986void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 987 s32 npages); 988int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 989int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); 990s64 mlx5_wait_for_reclaim_vfs_pages(struct mlx5_core_dev *dev); 991void mlx5_register_debugfs(void); 992void mlx5_unregister_debugfs(void); 993int mlx5_eq_init(struct mlx5_core_dev *dev); 994void mlx5_eq_cleanup(struct mlx5_core_dev *dev); 995void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); 996void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); 997void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); 998void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); 999struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); 1000void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vector, enum mlx5_cmd_mode mode); 1001void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); 1002int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 1003 int nent, u64 mask, struct mlx5_uar *uar); 1004int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 1005int mlx5_start_eqs(struct mlx5_core_dev *dev); 1006int mlx5_stop_eqs(struct mlx5_core_dev *dev); 1007int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn); 1008int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 1009int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 1010int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable, 1011 u64 addr); 1012 1013int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); 1014void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); 1015int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 1016 int size_in, void *data_out, int size_out, 1017 u16 reg_num, int arg, int write); 1018 1019void mlx5_toggle_port_link(struct mlx5_core_dev *dev); 1020 1021int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 1022void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 1023int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 1024 u32 *out, int outlen); 1025int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); 1026void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); 1027int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); 1028void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); 1029int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); 1030int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, 1031 int node); 1032void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); 1033 1034const char *mlx5_command_str(int command); 1035int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); 1036void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); 1037int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, 1038 int npsvs, u32 *sig_index); 1039int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); 1040void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); 1041u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev); 1042int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode); 1043int mlx5_set_dropless_mode(struct mlx5_core_dev *dev, u16 timeout); 1044int mlx5_query_dropless_mode(struct mlx5_core_dev *dev, u16 *timeout); 1045int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode); 1046int mlx5_core_access_pvlc(struct mlx5_core_dev *dev, 1047 struct mlx5_pvlc_reg *pvlc, int write); 1048int mlx5_core_access_ptys(struct mlx5_core_dev *dev, 1049 struct mlx5_ptys_reg *ptys, int write); 1050int mlx5_core_access_pmtu(struct mlx5_core_dev *dev, 1051 struct mlx5_pmtu_reg *pmtu, int write); 1052int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port); 1053int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port); 1054int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 1055 int priority, int *is_enable); 1056int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 1057 int priority, int enable); 1058int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol, 1059 void *out, int out_size); 1060int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev, 1061 void *in, int in_size); 1062int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear, 1063 void *out, int out_size); 1064int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in, 1065 int in_size); 1066int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev, 1067 u8 num_of_samples, u16 sample_index, 1068 void *out, int out_size); 1069int mlx5_vsc_find_cap(struct mlx5_core_dev *mdev); 1070int mlx5_vsc_lock(struct mlx5_core_dev *mdev); 1071void mlx5_vsc_unlock(struct mlx5_core_dev *mdev); 1072int mlx5_vsc_set_space(struct mlx5_core_dev *mdev, u16 space); 1073int mlx5_vsc_write(struct mlx5_core_dev *mdev, u32 addr, const u32 *data); 1074int mlx5_vsc_read(struct mlx5_core_dev *mdev, u32 addr, u32 *data); 1075int mlx5_vsc_lock_addr_space(struct mlx5_core_dev *mdev, u32 addr); 1076int mlx5_vsc_unlock_addr_space(struct mlx5_core_dev *mdev, u32 addr); 1077int mlx5_pci_read_power_status(struct mlx5_core_dev *mdev, 1078 u16 *p_power, u8 *p_status); 1079 1080static inline u32 mlx5_mkey_to_idx(u32 mkey) 1081{ 1082 return mkey >> 8; 1083} 1084 1085static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) 1086{ 1087 return mkey_idx << 8; 1088} 1089 1090static inline u8 mlx5_mkey_variant(u32 mkey) 1091{ 1092 return mkey & 0xff; 1093} 1094 1095enum { 1096 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, 1097 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, 1098}; 1099 1100enum { 1101 MAX_MR_CACHE_ENTRIES = 15, 1102}; 1103 1104struct mlx5_interface { 1105 void * (*add)(struct mlx5_core_dev *dev); 1106 void (*remove)(struct mlx5_core_dev *dev, void *context); 1107 void (*event)(struct mlx5_core_dev *dev, void *context, 1108 enum mlx5_dev_event event, unsigned long param); 1109 void * (*get_dev)(void *context); 1110 int protocol; 1111 struct list_head list; 1112}; 1113 1114void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); 1115int mlx5_register_interface(struct mlx5_interface *intf); 1116void mlx5_unregister_interface(struct mlx5_interface *intf); 1117 1118unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); 1119int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, 1120 u8 roce_version, u8 roce_l3_type, const u8 *gid, 1121 const u8 *mac, bool vlan, u16 vlan_id); 1122 1123struct mlx5_profile { 1124 u64 mask; 1125 u8 log_max_qp; 1126 struct { 1127 int size; 1128 int limit; 1129 } mr_cache[MAX_MR_CACHE_ENTRIES]; 1130}; 1131 1132enum { 1133 MLX5_PCI_DEV_IS_VF = 1 << 0, 1134}; 1135 1136enum { 1137 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, 1138}; 1139 1140static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) 1141{ 1142 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); 1143} 1144 1145#endif /* MLX5_DRIVER_H */ 1146