driver.h revision 353197
1/*- 2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: stable/11/sys/dev/mlx5/driver.h 353197 2019-10-07 08:47:08Z hselasky $ 26 */ 27 28#ifndef MLX5_DRIVER_H 29#define MLX5_DRIVER_H 30 31#include <linux/kernel.h> 32#include <linux/completion.h> 33#include <linux/pci.h> 34#include <linux/cache.h> 35#include <linux/rbtree.h> 36#include <linux/if_ether.h> 37#include <linux/semaphore.h> 38#include <linux/slab.h> 39#include <linux/vmalloc.h> 40#include <linux/radix-tree.h> 41#include <linux/idr.h> 42 43#include <dev/mlx5/device.h> 44#include <dev/mlx5/doorbell.h> 45#include <dev/mlx5/srq.h> 46 47#define MLX5_QCOUNTER_SETS_NETDEV 64 48#define MLX5_MAX_NUMBER_OF_VFS 128 49 50enum { 51 MLX5_BOARD_ID_LEN = 64, 52 MLX5_MAX_NAME_LEN = 16, 53}; 54 55enum { 56 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, 57}; 58 59enum { 60 CMD_OWNER_SW = 0x0, 61 CMD_OWNER_HW = 0x1, 62 CMD_STATUS_SUCCESS = 0, 63}; 64 65enum mlx5_sqp_t { 66 MLX5_SQP_SMI = 0, 67 MLX5_SQP_GSI = 1, 68 MLX5_SQP_IEEE_1588 = 2, 69 MLX5_SQP_SNIFFER = 3, 70 MLX5_SQP_SYNC_UMR = 4, 71}; 72 73enum { 74 MLX5_MAX_PORTS = 2, 75}; 76 77enum { 78 MLX5_EQ_VEC_PAGES = 0, 79 MLX5_EQ_VEC_CMD = 1, 80 MLX5_EQ_VEC_ASYNC = 2, 81 MLX5_EQ_VEC_COMP_BASE, 82}; 83 84enum { 85 MLX5_MAX_IRQ_NAME = 32 86}; 87 88enum { 89 MLX5_ATOMIC_MODE_OFF = 16, 90 MLX5_ATOMIC_MODE_NONE = 0 << MLX5_ATOMIC_MODE_OFF, 91 MLX5_ATOMIC_MODE_IB_COMP = 1 << MLX5_ATOMIC_MODE_OFF, 92 MLX5_ATOMIC_MODE_CX = 2 << MLX5_ATOMIC_MODE_OFF, 93 MLX5_ATOMIC_MODE_8B = 3 << MLX5_ATOMIC_MODE_OFF, 94 MLX5_ATOMIC_MODE_16B = 4 << MLX5_ATOMIC_MODE_OFF, 95 MLX5_ATOMIC_MODE_32B = 5 << MLX5_ATOMIC_MODE_OFF, 96 MLX5_ATOMIC_MODE_64B = 6 << MLX5_ATOMIC_MODE_OFF, 97 MLX5_ATOMIC_MODE_128B = 7 << MLX5_ATOMIC_MODE_OFF, 98 MLX5_ATOMIC_MODE_256B = 8 << MLX5_ATOMIC_MODE_OFF, 99}; 100 101enum { 102 MLX5_ATOMIC_MODE_DCT_OFF = 20, 103 MLX5_ATOMIC_MODE_DCT_NONE = 0 << MLX5_ATOMIC_MODE_DCT_OFF, 104 MLX5_ATOMIC_MODE_DCT_IB_COMP = 1 << MLX5_ATOMIC_MODE_DCT_OFF, 105 MLX5_ATOMIC_MODE_DCT_CX = 2 << MLX5_ATOMIC_MODE_DCT_OFF, 106 MLX5_ATOMIC_MODE_DCT_8B = 3 << MLX5_ATOMIC_MODE_DCT_OFF, 107 MLX5_ATOMIC_MODE_DCT_16B = 4 << MLX5_ATOMIC_MODE_DCT_OFF, 108 MLX5_ATOMIC_MODE_DCT_32B = 5 << MLX5_ATOMIC_MODE_DCT_OFF, 109 MLX5_ATOMIC_MODE_DCT_64B = 6 << MLX5_ATOMIC_MODE_DCT_OFF, 110 MLX5_ATOMIC_MODE_DCT_128B = 7 << MLX5_ATOMIC_MODE_DCT_OFF, 111 MLX5_ATOMIC_MODE_DCT_256B = 8 << MLX5_ATOMIC_MODE_DCT_OFF, 112}; 113 114enum { 115 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, 116 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, 117 MLX5_ATOMIC_OPS_MASKED_CMP_SWAP = 1 << 2, 118 MLX5_ATOMIC_OPS_MASKED_FETCH_ADD = 1 << 3, 119}; 120 121enum { 122 MLX5_REG_QPTS = 0x4002, 123 MLX5_REG_QETCR = 0x4005, 124 MLX5_REG_QPDP = 0x4007, 125 MLX5_REG_QTCT = 0x400A, 126 MLX5_REG_QPDPM = 0x4013, 127 MLX5_REG_QHLL = 0x4016, 128 MLX5_REG_QCAM = 0x4019, 129 MLX5_REG_DCBX_PARAM = 0x4020, 130 MLX5_REG_DCBX_APP = 0x4021, 131 MLX5_REG_PCAP = 0x5001, 132 MLX5_REG_FPGA_CAP = 0x4022, 133 MLX5_REG_FPGA_CTRL = 0x4023, 134 MLX5_REG_FPGA_ACCESS_REG = 0x4024, 135 MLX5_REG_FPGA_SHELL_CNTR = 0x4025, 136 MLX5_REG_PMTU = 0x5003, 137 MLX5_REG_PTYS = 0x5004, 138 MLX5_REG_PAOS = 0x5006, 139 MLX5_REG_PFCC = 0x5007, 140 MLX5_REG_PPCNT = 0x5008, 141 MLX5_REG_PMAOS = 0x5012, 142 MLX5_REG_PUDE = 0x5009, 143 MLX5_REG_PPTB = 0x500B, 144 MLX5_REG_PBMC = 0x500C, 145 MLX5_REG_PMPE = 0x5010, 146 MLX5_REG_PELC = 0x500e, 147 MLX5_REG_PVLC = 0x500f, 148 MLX5_REG_PMLP = 0x5002, 149 MLX5_REG_PCAM = 0x507f, 150 MLX5_REG_NODE_DESC = 0x6001, 151 MLX5_REG_HOST_ENDIANNESS = 0x7004, 152 MLX5_REG_MTMP = 0x900a, 153 MLX5_REG_MCIA = 0x9014, 154 MLX5_REG_MFRL = 0x9028, 155 MLX5_REG_MPCNT = 0x9051, 156 MLX5_REG_MCQI = 0x9061, 157 MLX5_REG_MCC = 0x9062, 158 MLX5_REG_MCDA = 0x9063, 159 MLX5_REG_MCAM = 0x907f, 160}; 161 162enum dbg_rsc_type { 163 MLX5_DBG_RSC_QP, 164 MLX5_DBG_RSC_EQ, 165 MLX5_DBG_RSC_CQ, 166}; 167 168enum { 169 MLX5_INTERFACE_PROTOCOL_IB = 0, 170 MLX5_INTERFACE_PROTOCOL_ETH = 1, 171 MLX5_INTERFACE_NUMBER = 2, 172}; 173 174struct mlx5_field_desc { 175 struct dentry *dent; 176 int i; 177}; 178 179struct mlx5_rsc_debug { 180 struct mlx5_core_dev *dev; 181 void *object; 182 enum dbg_rsc_type type; 183 struct dentry *root; 184 struct mlx5_field_desc fields[0]; 185}; 186 187enum mlx5_dev_event { 188 MLX5_DEV_EVENT_SYS_ERROR, 189 MLX5_DEV_EVENT_PORT_UP, 190 MLX5_DEV_EVENT_PORT_DOWN, 191 MLX5_DEV_EVENT_PORT_INITIALIZED, 192 MLX5_DEV_EVENT_LID_CHANGE, 193 MLX5_DEV_EVENT_PKEY_CHANGE, 194 MLX5_DEV_EVENT_GUID_CHANGE, 195 MLX5_DEV_EVENT_CLIENT_REREG, 196 MLX5_DEV_EVENT_VPORT_CHANGE, 197 MLX5_DEV_EVENT_ERROR_STATE_DCBX, 198 MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE, 199 MLX5_DEV_EVENT_LOCAL_OPER_CHANGE, 200 MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE, 201}; 202 203enum mlx5_port_status { 204 MLX5_PORT_UP = 1 << 0, 205 MLX5_PORT_DOWN = 1 << 1, 206}; 207 208enum { 209 MLX5_VSC_SPACE_SUPPORTED = 0x1, 210 MLX5_VSC_SPACE_OFFSET = 0x4, 211 MLX5_VSC_COUNTER_OFFSET = 0x8, 212 MLX5_VSC_SEMA_OFFSET = 0xC, 213 MLX5_VSC_ADDR_OFFSET = 0x10, 214 MLX5_VSC_DATA_OFFSET = 0x14, 215 MLX5_VSC_MAX_RETRIES = 0x1000, 216}; 217 218#define MLX5_PROT_MASK(link_mode) (1 << link_mode) 219 220struct mlx5_uuar_info { 221 struct mlx5_uar *uars; 222 int num_uars; 223 int num_low_latency_uuars; 224 unsigned long *bitmap; 225 unsigned int *count; 226 struct mlx5_bf *bfs; 227 228 /* 229 * protect uuar allocation data structs 230 */ 231 struct mutex lock; 232 u32 ver; 233}; 234 235struct mlx5_bf { 236 void __iomem *reg; 237 void __iomem *regreg; 238 int buf_size; 239 struct mlx5_uar *uar; 240 unsigned long offset; 241 int need_lock; 242 /* protect blue flame buffer selection when needed 243 */ 244 spinlock_t lock; 245 246 /* serialize 64 bit writes when done as two 32 bit accesses 247 */ 248 spinlock_t lock32; 249 int uuarn; 250}; 251 252struct mlx5_cmd_first { 253 __be32 data[4]; 254}; 255 256struct cache_ent; 257struct mlx5_fw_page { 258 union { 259 struct rb_node rb_node; 260 struct list_head list; 261 }; 262 struct mlx5_cmd_first first; 263 struct mlx5_core_dev *dev; 264 bus_dmamap_t dma_map; 265 bus_addr_t dma_addr; 266 void *virt_addr; 267 struct cache_ent *cache; 268 u32 numpages; 269 u16 load_done; 270#define MLX5_LOAD_ST_NONE 0 271#define MLX5_LOAD_ST_SUCCESS 1 272#define MLX5_LOAD_ST_FAILURE 2 273 u16 func_id; 274}; 275#define mlx5_cmd_msg mlx5_fw_page 276 277struct mlx5_cmd_debug { 278 struct dentry *dbg_root; 279 struct dentry *dbg_in; 280 struct dentry *dbg_out; 281 struct dentry *dbg_outlen; 282 struct dentry *dbg_status; 283 struct dentry *dbg_run; 284 void *in_msg; 285 void *out_msg; 286 u8 status; 287 u16 inlen; 288 u16 outlen; 289}; 290 291struct cache_ent { 292 /* protect block chain allocations 293 */ 294 spinlock_t lock; 295 struct list_head head; 296}; 297 298struct cmd_msg_cache { 299 struct cache_ent large; 300 struct cache_ent med; 301 302}; 303 304struct mlx5_traffic_counter { 305 u64 packets; 306 u64 octets; 307}; 308 309enum mlx5_cmd_mode { 310 MLX5_CMD_MODE_POLLING, 311 MLX5_CMD_MODE_EVENTS 312}; 313 314struct mlx5_cmd_stats { 315 u64 sum; 316 u64 n; 317 struct dentry *root; 318 struct dentry *avg; 319 struct dentry *count; 320 /* protect command average calculations */ 321 spinlock_t lock; 322}; 323 324struct mlx5_cmd { 325 struct mlx5_fw_page *cmd_page; 326 bus_dma_tag_t dma_tag; 327 struct sx dma_sx; 328 struct mtx dma_mtx; 329#define MLX5_DMA_OWNED(dev) mtx_owned(&(dev)->cmd.dma_mtx) 330#define MLX5_DMA_LOCK(dev) mtx_lock(&(dev)->cmd.dma_mtx) 331#define MLX5_DMA_UNLOCK(dev) mtx_unlock(&(dev)->cmd.dma_mtx) 332 struct cv dma_cv; 333#define MLX5_DMA_DONE(dev) cv_broadcast(&(dev)->cmd.dma_cv) 334#define MLX5_DMA_WAIT(dev) cv_wait(&(dev)->cmd.dma_cv, &(dev)->cmd.dma_mtx) 335 void *cmd_buf; 336 dma_addr_t dma; 337 u16 cmdif_rev; 338 u8 log_sz; 339 u8 log_stride; 340 int max_reg_cmds; 341 int events; 342 u32 __iomem *vector; 343 344 /* protect command queue allocations 345 */ 346 spinlock_t alloc_lock; 347 348 /* protect token allocations 349 */ 350 spinlock_t token_lock; 351 u8 token; 352 unsigned long bitmask; 353 struct semaphore sem; 354 struct semaphore pages_sem; 355 enum mlx5_cmd_mode mode; 356 struct mlx5_cmd_work_ent * volatile ent_arr[MLX5_MAX_COMMANDS]; 357 volatile enum mlx5_cmd_mode ent_mode[MLX5_MAX_COMMANDS]; 358 struct mlx5_cmd_debug dbg; 359 struct cmd_msg_cache cache; 360 int checksum_disabled; 361 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; 362}; 363 364struct mlx5_port_caps { 365 int gid_table_len; 366 int pkey_table_len; 367 u8 ext_port_cap; 368}; 369 370struct mlx5_buf { 371 bus_dma_tag_t dma_tag; 372 bus_dmamap_t dma_map; 373 struct mlx5_core_dev *dev; 374 struct { 375 void *buf; 376 } direct; 377 u64 *page_list; 378 int npages; 379 int size; 380 u8 page_shift; 381 u8 load_done; 382}; 383 384struct mlx5_frag_buf { 385 struct mlx5_buf_list *frags; 386 int npages; 387 int size; 388 u8 page_shift; 389}; 390 391struct mlx5_eq { 392 struct mlx5_core_dev *dev; 393 __be32 __iomem *doorbell; 394 u32 cons_index; 395 struct mlx5_buf buf; 396 int size; 397 u8 irqn; 398 u8 eqn; 399 int nent; 400 u64 mask; 401 struct list_head list; 402 int index; 403 struct mlx5_rsc_debug *dbg; 404}; 405 406struct mlx5_core_psv { 407 u32 psv_idx; 408 struct psv_layout { 409 u32 pd; 410 u16 syndrome; 411 u16 reserved; 412 u16 bg; 413 u16 app_tag; 414 u32 ref_tag; 415 } psv; 416}; 417 418struct mlx5_core_sig_ctx { 419 struct mlx5_core_psv psv_memory; 420 struct mlx5_core_psv psv_wire; 421#if (__FreeBSD_version >= 1100000) 422 struct ib_sig_err err_item; 423#endif 424 bool sig_status_checked; 425 bool sig_err_exists; 426 u32 sigerr_count; 427}; 428 429enum { 430 MLX5_MKEY_MR = 1, 431 MLX5_MKEY_MW, 432 MLX5_MKEY_MR_USER, 433}; 434 435struct mlx5_core_mkey { 436 u64 iova; 437 u64 size; 438 u32 key; 439 u32 pd; 440 u32 type; 441}; 442 443struct mlx5_core_mr { 444 u64 iova; 445 u64 size; 446 u32 key; 447 u32 pd; 448}; 449 450enum mlx5_res_type { 451 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, 452 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, 453 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, 454 MLX5_RES_SRQ = 3, 455 MLX5_RES_XSRQ = 4, 456 MLX5_RES_DCT = 5, 457}; 458 459struct mlx5_core_rsc_common { 460 enum mlx5_res_type res; 461 atomic_t refcount; 462 struct completion free; 463}; 464 465struct mlx5_core_srq { 466 struct mlx5_core_rsc_common common; /* must be first */ 467 u32 srqn; 468 int max; 469 size_t max_gs; 470 size_t max_avail_gather; 471 int wqe_shift; 472 void (*event)(struct mlx5_core_srq *, int); 473 atomic_t refcount; 474 struct completion free; 475}; 476 477struct mlx5_eq_table { 478 void __iomem *update_ci; 479 void __iomem *update_arm_ci; 480 struct list_head comp_eqs_list; 481 struct mlx5_eq pages_eq; 482 struct mlx5_eq async_eq; 483 struct mlx5_eq cmd_eq; 484 int num_comp_vectors; 485 /* protect EQs list 486 */ 487 spinlock_t lock; 488}; 489 490struct mlx5_uar { 491 u32 index; 492 void __iomem *bf_map; 493 void __iomem *map; 494}; 495 496 497struct mlx5_core_health { 498 struct mlx5_health_buffer __iomem *health; 499 __be32 __iomem *health_counter; 500 struct timer_list timer; 501 u32 prev; 502 int miss_counter; 503 u32 fatal_error; 504 struct workqueue_struct *wq_watchdog; 505 struct work_struct work_watchdog; 506 /* wq spinlock to synchronize draining */ 507 spinlock_t wq_lock; 508 struct workqueue_struct *wq; 509 unsigned long flags; 510 struct work_struct work; 511 struct delayed_work recover_work; 512 unsigned int last_reset_req; 513 struct work_struct work_cmd_completion; 514 struct workqueue_struct *wq_cmd; 515}; 516 517#define MLX5_CQ_LINEAR_ARRAY_SIZE 1024 518 519struct mlx5_cq_linear_array_entry { 520 spinlock_t lock; 521 struct mlx5_core_cq * volatile cq; 522}; 523 524struct mlx5_cq_table { 525 /* protect radix tree 526 */ 527 spinlock_t lock; 528 struct radix_tree_root tree; 529 struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE]; 530}; 531 532struct mlx5_qp_table { 533 /* protect radix tree 534 */ 535 spinlock_t lock; 536 struct radix_tree_root tree; 537}; 538 539struct mlx5_srq_table { 540 /* protect radix tree 541 */ 542 spinlock_t lock; 543 struct radix_tree_root tree; 544}; 545 546struct mlx5_mr_table { 547 /* protect radix tree 548 */ 549 spinlock_t lock; 550 struct radix_tree_root tree; 551}; 552 553struct mlx5_irq_info { 554 char name[MLX5_MAX_IRQ_NAME]; 555}; 556 557struct mlx5_priv { 558 char name[MLX5_MAX_NAME_LEN]; 559 struct mlx5_eq_table eq_table; 560 struct msix_entry *msix_arr; 561 struct mlx5_irq_info *irq_info; 562 struct mlx5_uuar_info uuari; 563 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock); 564 int disable_irqs; 565 566 struct io_mapping *bf_mapping; 567 568 /* pages stuff */ 569 struct workqueue_struct *pg_wq; 570 struct rb_root page_root; 571 s64 fw_pages; 572 atomic_t reg_pages; 573 s64 pages_per_func[MLX5_MAX_NUMBER_OF_VFS]; 574 struct mlx5_core_health health; 575 576 struct mlx5_srq_table srq_table; 577 578 /* start: qp staff */ 579 struct mlx5_qp_table qp_table; 580 struct dentry *qp_debugfs; 581 struct dentry *eq_debugfs; 582 struct dentry *cq_debugfs; 583 struct dentry *cmdif_debugfs; 584 /* end: qp staff */ 585 586 /* start: cq staff */ 587 struct mlx5_cq_table cq_table; 588 /* end: cq staff */ 589 590 /* start: mr staff */ 591 struct mlx5_mr_table mr_table; 592 /* end: mr staff */ 593 594 /* start: alloc staff */ 595 int numa_node; 596 597 struct mutex pgdir_mutex; 598 struct list_head pgdir_list; 599 /* end: alloc staff */ 600 struct dentry *dbg_root; 601 602 /* protect mkey key part */ 603 spinlock_t mkey_lock; 604 u8 mkey_key; 605 606 struct list_head dev_list; 607 struct list_head ctx_list; 608 spinlock_t ctx_lock; 609 unsigned long pci_dev_data; 610}; 611 612enum mlx5_device_state { 613 MLX5_DEVICE_STATE_UP, 614 MLX5_DEVICE_STATE_INTERNAL_ERROR, 615}; 616 617enum mlx5_interface_state { 618 MLX5_INTERFACE_STATE_UP, 619}; 620 621enum mlx5_pci_status { 622 MLX5_PCI_STATUS_DISABLED, 623 MLX5_PCI_STATUS_ENABLED, 624}; 625 626#define MLX5_MAX_RESERVED_GIDS 8 627 628struct mlx5_rsvd_gids { 629 unsigned int start; 630 unsigned int count; 631 struct ida ida; 632}; 633 634struct mlx5_special_contexts { 635 int resd_lkey; 636}; 637 638struct mlx5_flow_root_namespace; 639struct mlx5_core_dev { 640 struct pci_dev *pdev; 641 /* sync pci state */ 642 struct mutex pci_status_mutex; 643 enum mlx5_pci_status pci_status; 644 char board_id[MLX5_BOARD_ID_LEN]; 645 struct mlx5_cmd cmd; 646 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 647 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 648 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 649 struct { 650 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; 651 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)]; 652 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; 653 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; 654 } caps; 655 phys_addr_t iseg_base; 656 struct mlx5_init_seg __iomem *iseg; 657 enum mlx5_device_state state; 658 /* sync interface state */ 659 struct mutex intf_state_mutex; 660 unsigned long intf_state; 661 void (*event) (struct mlx5_core_dev *dev, 662 enum mlx5_dev_event event, 663 unsigned long param); 664 struct mlx5_priv priv; 665 struct mlx5_profile *profile; 666 atomic_t num_qps; 667 u32 vsc_addr; 668 u32 issi; 669 struct mlx5_special_contexts special_contexts; 670 unsigned int module_status[MLX5_MAX_PORTS]; 671 struct mlx5_flow_root_namespace *root_ns; 672 struct mlx5_flow_root_namespace *fdb_root_ns; 673 struct mlx5_flow_root_namespace *esw_egress_root_ns; 674 struct mlx5_flow_root_namespace *esw_ingress_root_ns; 675 struct mlx5_flow_root_namespace *sniffer_rx_root_ns; 676 struct mlx5_flow_root_namespace *sniffer_tx_root_ns; 677 u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER]; 678 const struct mlx5_crspace_regmap *dump_rege; 679 uint32_t *dump_data; 680 unsigned dump_size; 681 bool dump_valid; 682 bool dump_copyout; 683 struct mtx dump_lock; 684 685 struct sysctl_ctx_list sysctl_ctx; 686 int msix_eqvec; 687 int pwr_status; 688 int pwr_value; 689 690 struct { 691 struct mlx5_rsvd_gids reserved_gids; 692 atomic_t roce_en; 693 } roce; 694 695 struct { 696 spinlock_t spinlock; 697#define MLX5_MPFS_TABLE_MAX 32 698 long bitmap[BITS_TO_LONGS(MLX5_MPFS_TABLE_MAX)]; 699 } mpfs; 700#ifdef CONFIG_MLX5_FPGA 701 struct mlx5_fpga_device *fpga; 702#endif 703}; 704 705enum { 706 MLX5_WOL_DISABLE = 0, 707 MLX5_WOL_SECURED_MAGIC = 1 << 1, 708 MLX5_WOL_MAGIC = 1 << 2, 709 MLX5_WOL_ARP = 1 << 3, 710 MLX5_WOL_BROADCAST = 1 << 4, 711 MLX5_WOL_MULTICAST = 1 << 5, 712 MLX5_WOL_UNICAST = 1 << 6, 713 MLX5_WOL_PHY_ACTIVITY = 1 << 7, 714}; 715 716struct mlx5_db { 717 __be32 *db; 718 union { 719 struct mlx5_db_pgdir *pgdir; 720 struct mlx5_ib_user_db_page *user_page; 721 } u; 722 dma_addr_t dma; 723 int index; 724}; 725 726struct mlx5_net_counters { 727 u64 packets; 728 u64 octets; 729}; 730 731struct mlx5_ptys_reg { 732 u8 an_dis_admin; 733 u8 an_dis_ap; 734 u8 local_port; 735 u8 proto_mask; 736 u32 eth_proto_cap; 737 u16 ib_link_width_cap; 738 u16 ib_proto_cap; 739 u32 eth_proto_admin; 740 u16 ib_link_width_admin; 741 u16 ib_proto_admin; 742 u32 eth_proto_oper; 743 u16 ib_link_width_oper; 744 u16 ib_proto_oper; 745 u32 eth_proto_lp_advertise; 746}; 747 748struct mlx5_pvlc_reg { 749 u8 local_port; 750 u8 vl_hw_cap; 751 u8 vl_admin; 752 u8 vl_operational; 753}; 754 755struct mlx5_pmtu_reg { 756 u8 local_port; 757 u16 max_mtu; 758 u16 admin_mtu; 759 u16 oper_mtu; 760}; 761 762struct mlx5_vport_counters { 763 struct mlx5_net_counters received_errors; 764 struct mlx5_net_counters transmit_errors; 765 struct mlx5_net_counters received_ib_unicast; 766 struct mlx5_net_counters transmitted_ib_unicast; 767 struct mlx5_net_counters received_ib_multicast; 768 struct mlx5_net_counters transmitted_ib_multicast; 769 struct mlx5_net_counters received_eth_broadcast; 770 struct mlx5_net_counters transmitted_eth_broadcast; 771 struct mlx5_net_counters received_eth_unicast; 772 struct mlx5_net_counters transmitted_eth_unicast; 773 struct mlx5_net_counters received_eth_multicast; 774 struct mlx5_net_counters transmitted_eth_multicast; 775}; 776 777enum { 778 MLX5_DB_PER_PAGE = MLX5_ADAPTER_PAGE_SIZE / L1_CACHE_BYTES, 779}; 780 781struct mlx5_core_dct { 782 struct mlx5_core_rsc_common common; /* must be first */ 783 void (*event)(struct mlx5_core_dct *, int); 784 int dctn; 785 struct completion drained; 786 struct mlx5_rsc_debug *dbg; 787 int pid; 788}; 789 790enum { 791 MLX5_COMP_EQ_SIZE = 1024, 792}; 793 794enum { 795 MLX5_PTYS_IB = 1 << 0, 796 MLX5_PTYS_EN = 1 << 2, 797}; 798 799struct mlx5_db_pgdir { 800 struct list_head list; 801 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE); 802 struct mlx5_fw_page *fw_page; 803 __be32 *db_page; 804 dma_addr_t db_dma; 805}; 806 807typedef void (*mlx5_cmd_cbk_t)(int status, void *context); 808 809struct mlx5_cmd_work_ent { 810 struct mlx5_cmd_msg *in; 811 struct mlx5_cmd_msg *out; 812 int uin_size; 813 void *uout; 814 int uout_size; 815 mlx5_cmd_cbk_t callback; 816 struct delayed_work cb_timeout_work; 817 void *context; 818 int idx; 819 struct completion done; 820 struct mlx5_cmd *cmd; 821 struct work_struct work; 822 struct mlx5_cmd_layout *lay; 823 int ret; 824 int page_queue; 825 u8 status; 826 u8 token; 827 u64 ts1; 828 u64 ts2; 829 u16 op; 830 u8 busy; 831 bool polling; 832}; 833 834struct mlx5_pas { 835 u64 pa; 836 u8 log_sz; 837}; 838 839enum port_state_policy { 840 MLX5_POLICY_DOWN = 0, 841 MLX5_POLICY_UP = 1, 842 MLX5_POLICY_FOLLOW = 2, 843 MLX5_POLICY_INVALID = 0xffffffff 844}; 845 846static inline void * 847mlx5_buf_offset(struct mlx5_buf *buf, int offset) 848{ 849 return ((char *)buf->direct.buf + offset); 850} 851 852 853extern struct workqueue_struct *mlx5_core_wq; 854 855#define STRUCT_FIELD(header, field) \ 856 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ 857 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 858 859static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) 860{ 861 return pci_get_drvdata(pdev); 862} 863 864extern struct dentry *mlx5_debugfs_root; 865 866static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) 867{ 868 return ioread32be(&dev->iseg->fw_rev) & 0xffff; 869} 870 871static inline u16 fw_rev_min(struct mlx5_core_dev *dev) 872{ 873 return ioread32be(&dev->iseg->fw_rev) >> 16; 874} 875 876static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) 877{ 878 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; 879} 880 881static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev) 882{ 883 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 884} 885 886static inline int mlx5_get_gid_table_len(u16 param) 887{ 888 if (param > 4) { 889 printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n"); 890 return 0; 891 } 892 893 return 8 * (1 << param); 894} 895 896static inline void *mlx5_vzalloc(unsigned long size) 897{ 898 void *rtn; 899 900 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); 901 return rtn; 902} 903 904static inline void *mlx5_vmalloc(unsigned long size) 905{ 906 void *rtn; 907 908 rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN); 909 if (!rtn) 910 rtn = vmalloc(size); 911 return rtn; 912} 913 914static inline u32 mlx5_base_mkey(const u32 key) 915{ 916 return key & 0xffffff00u; 917} 918 919int mlx5_cmd_init(struct mlx5_core_dev *dev); 920void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 921void mlx5_cmd_use_events(struct mlx5_core_dev *dev); 922void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 923void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); 924int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); 925int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 926 int out_size); 927int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, 928 void *out, int out_size, mlx5_cmd_cbk_t callback, 929 void *context); 930int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, 931 void *out, int out_size); 932int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 933int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 934int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 935int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 936int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 937void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 938void mlx5_health_cleanup(struct mlx5_core_dev *dev); 939int mlx5_health_init(struct mlx5_core_dev *dev); 940void mlx5_start_health_poll(struct mlx5_core_dev *dev); 941void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health); 942void mlx5_drain_health_wq(struct mlx5_core_dev *dev); 943void mlx5_drain_health_recovery(struct mlx5_core_dev *dev); 944void mlx5_trigger_health_work(struct mlx5_core_dev *dev); 945void mlx5_trigger_health_watchdog(struct mlx5_core_dev *dev); 946 947#define mlx5_buf_alloc_node(dev, size, direct, buf, node) \ 948 mlx5_buf_alloc(dev, size, direct, buf) 949int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct, 950 struct mlx5_buf *buf); 951void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); 952int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 953 struct mlx5_srq_attr *in); 954int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); 955int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 956 struct mlx5_srq_attr *out); 957int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 958int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 959 u16 lwm, int is_srq); 960void mlx5_init_mr_table(struct mlx5_core_dev *dev); 961void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev); 962int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, 963 struct mlx5_core_mr *mkey, 964 u32 *in, int inlen, 965 u32 *out, int outlen, 966 mlx5_cmd_cbk_t callback, void *context); 967int mlx5_core_create_mkey(struct mlx5_core_dev *dev, 968 struct mlx5_core_mr *mr, 969 u32 *in, int inlen); 970int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey); 971int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey, 972 u32 *out, int outlen); 973int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 974 u32 *mkey); 975int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); 976int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); 977int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, 978 u16 opmod, u8 port); 979void mlx5_fwp_flush(struct mlx5_fw_page *fwp); 980void mlx5_fwp_invalidate(struct mlx5_fw_page *fwp); 981struct mlx5_fw_page *mlx5_fwp_alloc(struct mlx5_core_dev *dev, gfp_t flags, unsigned num); 982void mlx5_fwp_free(struct mlx5_fw_page *fwp); 983u64 mlx5_fwp_get_dma(struct mlx5_fw_page *fwp, size_t offset); 984void *mlx5_fwp_get_virt(struct mlx5_fw_page *fwp, size_t offset); 985void mlx5_pagealloc_init(struct mlx5_core_dev *dev); 986void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 987int mlx5_pagealloc_start(struct mlx5_core_dev *dev); 988void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 989void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 990 s32 npages); 991int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 992int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); 993s64 mlx5_wait_for_reclaim_vfs_pages(struct mlx5_core_dev *dev); 994void mlx5_register_debugfs(void); 995void mlx5_unregister_debugfs(void); 996int mlx5_eq_init(struct mlx5_core_dev *dev); 997void mlx5_eq_cleanup(struct mlx5_core_dev *dev); 998void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); 999void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); 1000void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); 1001void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); 1002struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); 1003void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vector, enum mlx5_cmd_mode mode); 1004void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); 1005int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 1006 int nent, u64 mask, const char *name, struct mlx5_uar *uar); 1007int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 1008int mlx5_start_eqs(struct mlx5_core_dev *dev); 1009int mlx5_stop_eqs(struct mlx5_core_dev *dev); 1010int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn); 1011int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 1012int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 1013int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable, 1014 u64 addr); 1015 1016int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); 1017void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); 1018int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 1019 int size_in, void *data_out, int size_out, 1020 u16 reg_num, int arg, int write); 1021 1022void mlx5_toggle_port_link(struct mlx5_core_dev *dev); 1023 1024int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 1025void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 1026int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 1027 u32 *out, int outlen); 1028int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); 1029void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); 1030int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); 1031void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); 1032int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); 1033int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, 1034 int node); 1035void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); 1036 1037const char *mlx5_command_str(int command); 1038int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); 1039void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); 1040int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, 1041 int npsvs, u32 *sig_index); 1042int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); 1043void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); 1044u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev); 1045int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode); 1046int mlx5_set_dropless_mode(struct mlx5_core_dev *dev, u16 timeout); 1047int mlx5_query_dropless_mode(struct mlx5_core_dev *dev, u16 *timeout); 1048int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode); 1049int mlx5_core_access_pvlc(struct mlx5_core_dev *dev, 1050 struct mlx5_pvlc_reg *pvlc, int write); 1051int mlx5_core_access_ptys(struct mlx5_core_dev *dev, 1052 struct mlx5_ptys_reg *ptys, int write); 1053int mlx5_core_access_pmtu(struct mlx5_core_dev *dev, 1054 struct mlx5_pmtu_reg *pmtu, int write); 1055int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port); 1056int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port); 1057int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 1058 int priority, int *is_enable); 1059int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 1060 int priority, int enable); 1061int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol, 1062 void *out, int out_size); 1063int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev, 1064 void *in, int in_size); 1065int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear, 1066 void *out, int out_size); 1067int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in, 1068 int in_size); 1069int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev, 1070 u8 num_of_samples, u16 sample_index, 1071 void *out, int out_size); 1072int mlx5_vsc_find_cap(struct mlx5_core_dev *mdev); 1073int mlx5_vsc_lock(struct mlx5_core_dev *mdev); 1074void mlx5_vsc_unlock(struct mlx5_core_dev *mdev); 1075int mlx5_vsc_set_space(struct mlx5_core_dev *mdev, u16 space); 1076int mlx5_vsc_write(struct mlx5_core_dev *mdev, u32 addr, const u32 *data); 1077int mlx5_vsc_read(struct mlx5_core_dev *mdev, u32 addr, u32 *data); 1078int mlx5_vsc_lock_addr_space(struct mlx5_core_dev *mdev, u32 addr); 1079int mlx5_vsc_unlock_addr_space(struct mlx5_core_dev *mdev, u32 addr); 1080int mlx5_pci_read_power_status(struct mlx5_core_dev *mdev, 1081 u16 *p_power, u8 *p_status); 1082 1083static inline u32 mlx5_mkey_to_idx(u32 mkey) 1084{ 1085 return mkey >> 8; 1086} 1087 1088static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) 1089{ 1090 return mkey_idx << 8; 1091} 1092 1093static inline u8 mlx5_mkey_variant(u32 mkey) 1094{ 1095 return mkey & 0xff; 1096} 1097 1098enum { 1099 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, 1100 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, 1101}; 1102 1103enum { 1104 MAX_MR_CACHE_ENTRIES = 15, 1105}; 1106 1107struct mlx5_interface { 1108 void * (*add)(struct mlx5_core_dev *dev); 1109 void (*remove)(struct mlx5_core_dev *dev, void *context); 1110 void (*event)(struct mlx5_core_dev *dev, void *context, 1111 enum mlx5_dev_event event, unsigned long param); 1112 void * (*get_dev)(void *context); 1113 int protocol; 1114 struct list_head list; 1115}; 1116 1117void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); 1118int mlx5_register_interface(struct mlx5_interface *intf); 1119void mlx5_unregister_interface(struct mlx5_interface *intf); 1120 1121unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); 1122int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, 1123 u8 roce_version, u8 roce_l3_type, const u8 *gid, 1124 const u8 *mac, bool vlan, u16 vlan_id); 1125 1126struct mlx5_profile { 1127 u64 mask; 1128 u8 log_max_qp; 1129 struct { 1130 int size; 1131 int limit; 1132 } mr_cache[MAX_MR_CACHE_ENTRIES]; 1133}; 1134 1135enum { 1136 MLX5_PCI_DEV_IS_VF = 1 << 0, 1137}; 1138 1139enum { 1140 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, 1141}; 1142 1143static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) 1144{ 1145 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); 1146} 1147 1148#endif /* MLX5_DRIVER_H */ 1149